Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	pll_config_t
	PLL configuration structure. More...

struct	pll_setup_t
	PLL0 setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
	User-defined the size of cache for CLOCK_PllGetConfig() function. More...

#define	ROM_CLOCKS
	Clock ip name array for ROM. More...

#define	SRAM_CLOCKS
	Clock ip name array for SRAM. More...

#define	FLASH_CLOCKS
	Clock ip name array for FLASH. More...

#define	FMC_CLOCKS
	Clock ip name array for FMC. More...

#define	INPUTMUX_CLOCKS
	Clock ip name array for INPUTMUX. More...

#define	IOCON_CLOCKS
	Clock ip name array for IOCON. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	PINT_CLOCKS
	Clock ip name array for PINT. More...

#define	GINT_CLOCKS
	Clock ip name array for GINT. More...

#define	DMA_CLOCKS
	Clock ip name array for DMA. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	WWDT_CLOCKS
	Clock ip name array for WWDT. More...

#define	RTC_CLOCKS
	Clock ip name array for RTC. More...

#define	MAILBOX_CLOCKS
	Clock ip name array for Mailbox. More...

#define	LPADC_CLOCKS
	Clock ip name array for LPADC. More...

#define	LPDAC_CLOCKS
	Clock ip name array for DAC. More...

#define	MRT_CLOCKS
	Clock ip name array for MRT. More...

#define	OSTIMER_CLOCKS
	Clock ip name array for OSTIMER. More...

#define	SCT_CLOCKS
	Clock ip name array for SCT0. More...

#define	MCAN_CLOCKS
	Clock ip name array for MCAN. More...

#define	UTICK_CLOCKS
	Clock ip name array for UTICK. More...

#define	FLEXCOMM_CLOCKS
	Clock ip name array for FLEXCOMM. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	BI2C_CLOCKS
	Clock ip name array for BI2C. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LSPI. More...

#define	FLEXI2S_CLOCKS
	Clock ip name array for FLEXI2S. More...

#define	CTIMER_CLOCKS
	Clock ip name array for CTIMER. More...

#define	COMP_CLOCKS
	Clock ip name array for COMP.

#define	FREQME_CLOCKS
	Clock ip name array for FREQME. More...

#define	CDOG_CLOCKS
	Clock ip name array for CDOG. More...

#define	RNG_CLOCKS
	Clock ip name array for RNG. More...

#define	USBHMR0_CLOCKS
	Clock ip name array for USBHMR0. More...

#define	USBHSL0_CLOCKS
	Clock ip name array for USBHSL0. More...

#define	ANALOGCTRL_CLOCKS
	Clock ip name array for ANALOGCTRL. More...

#define	HS_LSPI_CLOCKS
	Clock ip name array for HS_LSPI. More...

#define	GPIO_SEC_CLOCKS
	Clock ip name array for GPIO_SEC. More...

#define	GPIO_SEC_INT_CLOCKS
	Clock ip name array for GPIO_SEC_INT. More...

#define	USBD_CLOCKS
	Clock ip name array for USBD. More...

#define	SYSCTL_CLOCKS
	Clock ip name array for SYSCTL. More...

#define	DMIC_CLOCKS
	Clock ip name array for DMIC. More...

#define	PWM_CLOCKS
	Clock ip name array for PWM. More...

#define	ENC_CLOCKS
	Clock ip name array for ENC. More...

#define	OPAMP_CLOCKS
	Clock ip name array for OPAMP. More...

#define	VREF_CLOCKS
	Clock ip name array for VREF. More...

#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI.

#define	CACHE64_CLOCKS
	Clock ip name array for Cache64.

#define	I3C_CLOCKS
	Clock ip name array for I3C.

#define	HSCMP_CLOCKS
	Clock ip name array for HSCMP.

#define	POWERQUAD_CLOCKS
	Clock ip name array for PowerQuad. More...

#define	AOI_CLOCKS
	Clock ip name array for AOI. More...

#define	CLK_GATE_REG_OFFSET_SHIFT 8U
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

#define	BUS_CLK kCLOCK_BusClk
	Peripherals clock source definition. More...

#define	CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) \| (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U))
	Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards. More...

#define	PLL_CONFIGFLAG_USEINRATE (1U << 0U)
	PLL configuration structure flags for 'flags' field These flags control how the PLL configuration function sets up the PLL setup structure. More...

#define	PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
	Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware.

#define	PLL_SETUPFLAG_POWERUP (1U << 0U)
	PLL setup structure flags for 'flags' field These flags control how the PLL setup function sets up the PLL. More...

#define	PLL_SETUPFLAG_WAITLOCK (1U << 1U)
	Setup will wait for PLL lock, implies the PLL will be pwoered on.

#define	PLL_SETUPFLAG_ADGVOLT (1U << 2U)
	Optimize system voltage for the new PLL rate.

#define	PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U)
	Use feedback divider by 2 in divider path.

Enumerations
enum	clock_ip_name_t { kCLOCK_IpInvalid = 0U, kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1U), kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3U), kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4U), kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5U), kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6U), kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7U), kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8U), kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10U), kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11U), kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13U), kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14U), kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15U), kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16U), kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17U), kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18U), kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19U), kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20U), kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21U), kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22U), kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23U), kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26U), kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27U), kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28U), kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29U), kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0U), kCLOCK_Ostimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1U), kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2U), kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7U), kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10U), kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11U), kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12U), kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13U), kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14U), kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15U), kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16U), kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17U), kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18U), kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_Dmic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19U), kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22U), kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25U), kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26U), kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27U), kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1U), kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2U), kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8U), kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11U), kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13U), kCLOCK_Pmux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14U), kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15U), kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16U), kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17U), kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18U), kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19U), kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21U), kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22U), kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23U), kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24U), kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27U), kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28U), kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29U), kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30U), kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0U), kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3U), kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4U), kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5U), kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6U), kCLOCK_Aoi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7U), kCLOCK_Aoi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8U), kCLOCK_Ftm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 9U), kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 10U), kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11U), kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12U), kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13U), kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14U), kCLOCK_Hscmp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15U), kCLOCK_Hscmp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 16U), kCLOCK_Hscmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 17U), kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18U) }
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

enum	clock_name_t { kCLOCK_CoreSysClk, kCLOCK_BusClk, kCLOCK_ClockOut, kCLOCK_FroHf, kCLOCK_Pll1Out, kCLOCK_Mclk, kCLOCK_Fro12M, kCLOCK_Fro1M, kCLOCK_ExtClk, kCLOCK_Pll0Out, kCLOCK_PllClkDiv, kCLOCK_FlexI2S }
	Clock name used to get clock frequency. More...

enum	clock_attach_id_t { kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 0, 0), kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) \| MUX_B(CM_MAINCLKSELB, 0, 0), kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) \| MUX_B(CM_MAINCLKSELB, 0, 0), kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) \| MUX_B(CM_MAINCLKSELB, 0, 0), kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 1, 0), kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 2, 0), kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 3, 0), kSYSTICK_DIV_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), kPLL1_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4) , kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), kPLL1_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), kMCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), kPLL1_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), kMCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), kPLL1_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), kMCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), kPLL1_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), kMCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), kMAIN_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 0), kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), kEXT_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), kMAIN_CLK_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 0), kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), kMAIN_CLK_to_USB0 = MUX_A(CM_USB0CLKSEL, 0), kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), kFRO_HF_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), kPLL1_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), kMAIN_CLK_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) \| MUX_B(CM_FRGCLKSEL0, 0, 0), kPLL_CLK_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) \| MUX_B(CM_FRGCLKSEL0, 1, 0), kFRO_HF_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) \| MUX_B(CM_FRGCLKSEL0, 2, 0), kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), kMCLK_IN_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), kMAIN_CLK_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) \| MUX_B(CM_FRGCLKSEL1, 0, 0), kPLL_CLK_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) \| MUX_B(CM_FRGCLKSEL1, 1, 0), kFRO_HF_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) \| MUX_B(CM_FRGCLKSEL1, 2, 0), kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), kMCLK_IN_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), kMAIN_CLK_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) \| MUX_B(CM_FRGCLKSEL2, 0, 0), kPLL_CLK_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) \| MUX_B(CM_FRGCLKSEL2, 1, 0), kFRO_HF_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) \| MUX_B(CM_FRGCLKSEL2, 2, 0), kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), kMCLK_IN_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), kMAIN_CLK_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) \| MUX_B(CM_FRGCLKSEL3, 0, 0), kPLL_CLK_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) \| MUX_B(CM_FRGCLKSEL3, 1, 0), kFRO_HF_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) \| MUX_B(CM_FRGCLKSEL3, 2, 0), kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), kMCLK_IN_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), kMAIN_CLK_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) \| MUX_B(CM_FRGCLKSEL4, 0, 0), kPLL_CLK_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) \| MUX_B(CM_FRGCLKSEL4, 1, 0), kFRO_HF_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) \| MUX_B(CM_FRGCLKSEL4, 2, 0), kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), kMCLK_IN_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), kMAIN_CLK_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) \| MUX_B(CM_FRGCLKSEL5, 0, 0), kPLL_CLK_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) \| MUX_B(CM_FRGCLKSEL5, 1, 0), kFRO_HF_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) \| MUX_B(CM_FRGCLKSEL5, 2, 0), kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), kMCLK_IN_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), kMAIN_CLK_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) \| MUX_B(CM_FRGCLKSEL6, 0, 0), kPLL_CLK_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) \| MUX_B(CM_FRGCLKSEL6, 1, 0), kFRO_HF_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) \| MUX_B(CM_FRGCLKSEL6, 2, 0), kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), kMCLK_IN_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), kMAIN_CLK_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) \| MUX_B(CM_FRGCLKSEL7, 0, 0), kPLL_CLK_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) \| MUX_B(CM_FRGCLKSEL7, 1, 0), kFRO_HF_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) \| MUX_B(CM_FRGCLKSEL7, 2, 0), kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), kMCLK_IN_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), kPLL_CLK_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), kMAIN_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 0), kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), kEXT_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 2), kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), kPLL1_to_SCT = MUX_A(CM_SCTCLKSEL, 4), kMCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 7), kMAIN_CLK_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 0), kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), kPLL1_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), kFRO1M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 6), kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), kMAIN_CLK_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 0), kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), kPLL1_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), kFRO1M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 6), kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), kMAIN_CLK_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 0), kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), kPLL1_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), kFRO1M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 6), kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), kMAIN_CLK_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 0), kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 7), kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), kPLL1_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 7), kMAIN_CLK_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 0), kFRO_HF_DIV_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 1), kNONE_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 7), kI3CFCLKSEL_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 0), kFRO1M_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 1), kNONE_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 7), kMAIN_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 0), kPLL0_to_DMIC = MUX_A(CM_DMICFCLKSEL, 1), kEXT_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), kFRO_HF_to_DMIC = MUX_A(CM_DMICFCLKSEL, 3), kPLL1_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), kMCLK_IN_to_DMIC = MUX_A(CM_DMICFCLKSEL, 5), kNONE_to_DMIC = MUX_A(CM_DMICFCLKSEL, 7), kFRO32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 0), kXTAL32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 1), kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), kFRO32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 0), kXTAL32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 1), kFRO32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), kAHB_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), kNONE_to_NONE = (int)0x80000000U }

enum	clock_div_name_t { kCLOCK_DivSystickClk = (0), kCLOCK_DivArmTrClkDiv = ((0x308 - 0x300) / 4), kCLOCK_DivCanClk = ((0x30C - 0x300) / 4), kCLOCK_DivFlexFrg0 = ((0x320 - 0x300) / 4), kCLOCK_DivFlexFrg1 = ((0x324 - 0x300) / 4), kCLOCK_DivFlexFrg2 = ((0x328 - 0x300) / 4), kCLOCK_DivFlexFrg3 = ((0x32C - 0x300) / 4), kCLOCK_DivFlexFrg4 = ((0x330 - 0x300) / 4), kCLOCK_DivFlexFrg5 = ((0x334 - 0x300) / 4), kCLOCK_DivFlexFrg6 = ((0x338 - 0x300) / 4), kCLOCK_DivFlexFrg7 = ((0x33C - 0x300) / 4), kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), kCLOCK_DivWdtClk = ((0x38C - 0x300) / 4), kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), kCLOCK_DivUsb0Clk = ((0x398 - 0x300) / 4), kCLOCK_DivMclk = ((0x3AC - 0x300) / 4), kCLOCK_DivSctClk = ((0x3B4 - 0x300) / 4), kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), kCLOCK_DivDac0Clk = ((0x494 - 0x300) / 4), kCLOCK_DivDac1Clk = ((0x49C - 0x300) / 4), kCLOCK_DivDac2Clk = ((0x4A4 - 0x300) / 4), kCLOCK_DivFlexSpiClk = ((0x4AC - 0x300) / 4), kCLOCK_DivI3cFclkStc = ((0x538 - 0x300) / 4), kCLOCK_DivI3cFclkS = ((0x53C - 0x300) / 4), kCLOCK_DivI3cFclk = ((0x540 - 0x300) / 4), kCLOCK_DivDmicClk = ((0x54C - 0x300) / 4), kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4) }

enum	ss_progmodfm_t { kSS_MF_512 = (0 << 20), kSS_MF_384 = (1 << 20), kSS_MF_256 = (2 << 20), kSS_MF_128 = (3 << 20), kSS_MF_64 = (4 << 20), kSS_MF_32 = (5 << 20), kSS_MF_24 = (6 << 20), kSS_MF_16 = (7 << 20) }
	PLL Spread Spectrum (SS) Programmable modulation frequency See (MF) field in the PLL0SSCG1 register in the UM. More...

enum	ss_progmoddp_t { kSS_MR_K0 = (0 << 23), kSS_MR_K1 = (1 << 23), kSS_MR_K1_5 = (2 << 23), kSS_MR_K2 = (3 << 23), kSS_MR_K3 = (4 << 23), kSS_MR_K4 = (5 << 23), kSS_MR_K6 = (6 << 23), kSS_MR_K8 = (7 << 23) }
	PLL Spread Spectrum (SS) Programmable frequency modulation depth See (MR) field in the PLL0SSCG1 register in the UM. More...

enum	ss_modwvctrl_t { kSS_MC_NOC = (0 << 26), kSS_MC_RECC = (2 << 26), kSS_MC_MAXC = (3 << 26) }
	PLL Spread Spectrum (SS) Modulation waveform control See (MC) field in the PLL0SSCG1 register in the UM. More...

enum	pll_error_t { kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) }
	PLL status definitions. More...

enum	clock_usbfs_src_t { kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, kCLOCK_UsbfsSrcNone }
	USB FS clock source definition. More...

enum	clock_usb_phy_src_t { kCLOCK_UsbPhySrcExt = 0U }
	Source of the USB HS PHY. More...

Functions
static void	CLOCK_EnableClock (clock_ip_name_t clk)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t clk)
	Disable the clock for specific IP. More...

status_t	CLOCK_SetupFROClocking (uint32_t iFreq)
	Initialize the Core clock to given frequency (12, 48 or 96 MHz). Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is enabled. More...

void	CLOCK_SetFLASHAccessCyclesForFreq (uint32_t system_freq_hz)
	Set the flash wait states for the input freuqency. More...

status_t	CLOCK_SetupExtClocking (uint32_t iFreq)
	Initialize the external osc clock to given frequency. More...

status_t	CLOCK_SetupI2SMClkClocking (uint32_t iFreq)
	Initialize the I2S MCLK clock to given frequency. More...

status_t	CLOCK_SetupPLUClkInClocking (uint32_t iFreq)
	Initialize the PLU CLKIN clock to given frequency. More...

void	CLOCK_AttachClk (clock_attach_id_t connection)
	Configure the clock selection muxes. More...

clock_attach_id_t	CLOCK_GetClockAttachId (clock_attach_id_t attachId)
	Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id. More...

void	CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
	Setup peripheral clock dividers. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Return Frequency of selected clock. More...

uint32_t	CLOCK_GetFro12MFreq (void)
	Return Frequency of FRO 12MHz. More...

uint32_t	CLOCK_GetFro1MFreq (void)
	Return Frequency of FRO 1MHz. More...

uint32_t	CLOCK_GetClockOutClkFreq (void)
	Return Frequency of ClockOut. More...

uint32_t	CLOCK_GetMCanClkFreq (void)
	Return Frequency of Can Clock. More...

uint32_t	CLOCK_GetAdcClkFreq (uint32_t id)
	Return Frequency of Adc Clock. More...

uint32_t	CLOCK_GetUsb0ClkFreq (void)
	Return Frequency of Usb0 Clock. More...

uint32_t	CLOCK_GetMclkClkFreq (void)
	Return Frequency of MClk Clock. More...

uint32_t	CLOCK_GetSctClkFreq (void)
	Return Frequency of SCTimer Clock. More...

uint32_t	CLOCK_GetExtClkFreq (void)
	Return Frequency of External Clock. More...

uint32_t	CLOCK_GetWdtClkFreq (void)
	Return Frequency of Watchdog. More...

uint32_t	CLOCK_GetFroHfFreq (void)
	Return Frequency of High-Freq output of FRO. More...

uint32_t	CLOCK_GetPll0OutFreq (void)
	Return Frequency of PLL. More...

uint32_t	CLOCK_GetPll1OutFreq (void)
	Return Frequency of USB PLL. More...

uint32_t	CLOCK_GetPllClkDivFreq (void)
	Return Frequency of PLL_CLK_DIV. More...

uint32_t	CLOCK_GetOsc32KFreq (void)
	Return Frequency of 32kHz osc. More...

uint32_t	CLOCK_GetFC32KFreq (void)
	Return Frequency of Flexcomm 32kHz osc. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Return Frequency of Core System. More...

uint32_t	CLOCK_GetI2SMClkFreq (void)
	Return Frequency of I2S MCLK Clock. More...

uint32_t	CLOCK_GetFrgFreq (uint32_t id)
	Return Frequency of FRG Clock. More...

uint32_t	CLOCK_GetFlexCommClkFreq (uint32_t id)
	Return Frequency of FlexComm Clock. More...

uint32_t	CLOCK_GetHsLspiClkFreq (void)
	Return Frequency of High speed SPI Clock. More...

uint32_t	CLOCK_GetCTimerClkFreq (uint32_t id)
	Return Frequency of CTimer functional Clock. More...

uint32_t	CLOCK_GetSystickClkFreq (void)
	Return Frequency of SystickClock. More...

uint32_t	CLOCK_GetFlexSpiClkFreq (void)
	Return Frequency of FlexSPI. More...

uint32_t	CLOCK_GetDmicClkFreq (void)
	Return Frequency of DMIC. More...

uint32_t	CLOCK_GetDacClkFreq (uint32_t id)
	Return Frequency of DAC Clock. More...

uint32_t	CLOCK_GetI3cSTCClkFreq (void)
	Return Frequency of I3C function slow TC Clock. More...

uint32_t	CLOCK_GetI3cSClkFreq (void)
	Return Frequency of I3C function slow Clock. More...

uint32_t	CLOCK_GetI3cClkFreq (void)
	Return Frequency of I3C function Clock. More...

uint32_t	CLOCK_GetPLL0InClockRate (void)
	Return PLL0 input clock rate. More...

uint32_t	CLOCK_GetPLL1InClockRate (void)
	Return PLL1 input clock rate. More...

uint32_t	CLOCK_GetPLL0OutClockRate (bool recompute)
	Return PLL0 output clock rate. More...

uint32_t	CLOCK_GetPLL1OutClockRate (bool recompute)
	Return PLL1 output clock rate. More...

__STATIC_INLINE void	CLOCK_SetBypassPLL0 (bool bypass)
	Enables and disables PLL0 bypass mode. More...

__STATIC_INLINE void	CLOCK_SetBypassPLL1 (bool bypass)
	Enables and disables PLL1 bypass mode. More...

__STATIC_INLINE bool	CLOCK_IsPLL0Locked (void)
	Check if PLL is locked or not. More...

__STATIC_INLINE bool	CLOCK_IsPLL1Locked (void)
	Check if PLL1 is locked or not. More...

void	CLOCK_SetStoredPLL0ClockRate (uint32_t rate)
	Store the current PLL0 rate. More...

uint32_t	CLOCK_GetPLL0OutFromSetup (pll_setup_t *pSetup)
	Return PLL0 output clock rate from setup structure. More...

uint32_t	CLOCK_GetPLL1OutFromSetup (pll_setup_t *pSetup)
	Return PLL1 output clock rate from setup structure. More...

pll_error_t	CLOCK_SetupPLL0Data (pll_config_t pControl, pll_setup_t pSetup)
	Set PLL0 output based on the passed PLL setup data. More...

pll_error_t	CLOCK_SetupPLL0Prec (pll_setup_t *pSetup, uint32_t flagcfg)
	Set PLL output from PLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetPLL0Freq (const pll_setup_t *pSetup)
	Set PLL output from PLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetPLL1Freq (const pll_setup_t *pSetup)
	Set PLL output from PLL setup structure (precise frequency) More...

void	CLOCK_SetupPLL0Mult (uint32_t multiply_by, uint32_t input_freq)
	Set PLL0 output based on the multiplier and input frequency. More...

static void	CLOCK_DisableUsbDevicefs0Clock (clock_ip_name_t clk)
	Disable USB clock. More...

bool	CLOCK_EnableUsbfs0DeviceClock (clock_usbfs_src_t src, uint32_t freq)
	Enable USB Device FS clock. More...

bool	CLOCK_EnableUsbfs0HostClock (clock_usbfs_src_t src, uint32_t freq)
	Enable USB HOST FS clock. More...

void	CLOCK_EnableOstimer32kClock (void)
	Enable the OSTIMER 32k clock. More...

void	CLOCK_XtalHfCapabankTrim (int32_t pi32_hfXtalIecLoadpF_x100, int32_t pi32_hfXtalPPcbParCappF_x100, int32_t pi32_hfXtalNPcbParCappF_x100)
	Sets board-specific trim values for High Frequency crystal oscillator. More...

void	CLOCK_Xtal32khzCapabankTrim (int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100)
	Sets board-specific trim values for 32kHz XTAL. More...

void	CLOCK_FroHfTrim (void)
	Initialize the trim value for FRO HF. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
	CLOCK driver version 2.3.1. More...

Data Structure Documentation

struct pll_config_t

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

Data Fields
uint32_t	desiredRate
	Desired PLL rate in Hz.

uint32_t	inputRate
	PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set.

uint32_t	flags
	PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions.

ss_progmodfm_t	ss_mf
	SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.

ss_progmoddp_t	ss_mr
	SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.

ss_modwvctrl_t	ss_mc
	SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.

bool	mfDither
	false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag

struct pll_setup_t

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

Data Fields
uint32_t	pllctrl
	PLL control register PLL0CTRL.

uint32_t	pllndec
	PLL NDEC register PLL0NDEC.

uint32_t	pllpdec
	PLL PDEC register PLL0PDEC.

uint32_t	pllmdec
	PLL MDEC registers PLL0PDEC.

uint32_t	pllsscg [2]
	PLL SSCTL registers PLL0SSCG.

uint32_t	pllRate
	Acutal PLL rate.

uint32_t	flags
	PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U

Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function would cache the recent calulation and accelerate the execution to get the right settings.

#define ROM_CLOCKS

Value:

{              \
        kCLOCK_Rom \
    }

#define SRAM_CLOCKS

Value:

{                                                          \
        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
    }

#define FLASH_CLOCKS

Value:

{                \
        kCLOCK_Flash \
    }

#define FMC_CLOCKS

Value:

{              \
        kCLOCK_Fmc \
    }

#define INPUTMUX_CLOCKS

Value:

{                   \
        kCLOCK_InputMux \
    }

#define IOCON_CLOCKS

Value:

{                \
        kCLOCK_Iocon \
    }

#define GPIO_CLOCKS

Value:

{                                                          \
        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \
    }

#define PINT_CLOCKS

Value:

{               \
        kCLOCK_Pint \
    }

#define GINT_CLOCKS

Value:

{                            \
        kCLOCK_Gint, kCLOCK_Gint \
    }

#define DMA_CLOCKS

Value:

{                            \
        kCLOCK_Dma0, kCLOCK_Dma1 \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define WWDT_CLOCKS

Value:

{               \
        kCLOCK_Wwdt \
    }

#define RTC_CLOCKS

Value:

{               \
        kCLOCK_Rtc0 \
    }

#define MAILBOX_CLOCKS

Value:

{                  \
        kCLOCK_Mailbox \
    }

#define LPADC_CLOCKS

Value:

{                            \
        kCLOCK_Adc0, kCLOCK_Adc1 \
    }

#define LPDAC_CLOCKS

Value:

{                                         \
        kCLOCK_Dac0, kCLOCK_Dac1, kCLOCK_Dac2 \
    }

#define MRT_CLOCKS

Value:

{              \
        kCLOCK_Mrt \
    }

#define OSTIMER_CLOCKS

Value:

{                  \
        kCLOCK_Ostimer \
    }

#define SCT_CLOCKS

Value:

{              \
        kCLOCK_Sct \
    }

#define MCAN_CLOCKS

Value:

{               \
        kCLOCK_Mcan \
    }

#define UTICK_CLOCKS

Value:

{                \
        kCLOCK_Utick \
    }

#define FLEXCOMM_CLOCKS

Value:

{                                                                                                               \
        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
            kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi                                                      \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
            kCLOCK_MinUart6, kCLOCK_MinUart7                                                                  \
    }

#define BI2C_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
    }

#define LPSPI_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
    }

#define FLEXI2S_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7                                                                  \
    }

#define CTIMER_CLOCKS

Value:

{                                                                             \
        kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
    }

#define FREQME_CLOCKS

Value:

{                 \
        kCLOCK_Freqme \
    }

#define CDOG_CLOCKS

Value:

{               \
        kCLOCK_Cdog \
    }

#define RNG_CLOCKS

Value:

{              \
        kCLOCK_Rng \
    }

#define USBHMR0_CLOCKS

Value:

{                  \
        kCLOCK_Usbhmr0 \
    }

#define USBHSL0_CLOCKS

Value:

{                  \
        kCLOCK_Usbhsl0 \
    }

#define ANALOGCTRL_CLOCKS

Value:

{                     \
        kCLOCK_AnalogCtrl \
    }

#define HS_LSPI_CLOCKS

Value:

{                  \
        kCLOCK_Hs_Lspi \
    }

#define GPIO_SEC_CLOCKS

Value:

{                   \
        kCLOCK_Gpio_Sec \
    }

#define GPIO_SEC_INT_CLOCKS

Value:

{                       \
        kCLOCK_Gpio_Sec_Int \
    }

#define USBD_CLOCKS

Value:

{                \
        kCLOCK_Usbd0 \
    }

#define SYSCTL_CLOCKS

Value:

{                 \
        kCLOCK_Sysctl \
    }

#define DMIC_CLOCKS

Value:

{               \
        kCLOCK_Dmic \
    }

#define PWM_CLOCKS

Value:

{                                                          \
        {kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0},  \
        {                                                      \
            kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \
        }                                                      \
    }

#define ENC_CLOCKS

Value:

{                            \
        kCLOCK_Enc0, kCLOCK_Enc1 \
    }

#define OPAMP_CLOCKS

Value:

{                                               \
        kCLOCK_Opamp0, kCLOCK_Opamp1, kCLOCK_Opamp2 \
    }

#define VREF_CLOCKS

Value:

{               \
        kCLOCK_Vref \
    }

#define POWERQUAD_CLOCKS

Value:

{                    \
        kCLOCK_PowerQuad \
    }

#define AOI_CLOCKS

Value:

{                            \
        kCLOCK_Aoi0, kCLOCK_Aoi1 \
    }

#define CLK_GATE_REG_OFFSET_SHIFT 8U

#define BUS_CLK kCLOCK_BusClk

#define CLK_ATTACH_ID	(	mux,
		sel,
		pos
	)	((((uint32_t)(mux) << 0U) \| (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U))

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

#define PLL_CONFIGFLAG_USEINRATE (1U << 0U)

When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the configuration structure must be assigned with the expected PLL frequency. If the PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration function and the driver will determine the PLL rate from the currently selected PLL source. This flag might be used to configure the PLL input clock more accurately when using the WDT oscillator or a more dyanmic CLKIN source.

When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider are not used.
Flag to use InputRate in PLL configuration structure for setup

#define PLL_SETUPFLAG_POWERUP (1U << 0U)

Setup will power on the PLL after setup

Enumeration Type Documentation

enum clock_ip_name_t

Enumerator
kCLOCK_IpInvalid	Invalid IP name.
kCLOCK_Rom	Clock gate name: Rom.
kCLOCK_Sram1	Clock gate name: Sram1.
kCLOCK_Sram2	Clock gate name: Sram2.
kCLOCK_Sram3	Clock gate name: Sram3.
kCLOCK_Sram4	Clock gate name: Sram4.
kCLOCK_Flash	Clock gate name: Flash.
kCLOCK_Fmc	Clock gate name: Fmc.
kCLOCK_Flexspi	Clock gate name: Flexspi.
kCLOCK_InputMux	Clock gate name: InputMux.
kCLOCK_Iocon	Clock gate name: Iocon.
kCLOCK_Gpio0	Clock gate name: Gpio0.
kCLOCK_Gpio1	Clock gate name: Gpio1.
kCLOCK_Gpio2	Clock gate name: Gpio2.
kCLOCK_Gpio3	Clock gate name: Gpio3.
kCLOCK_Pint	Clock gate name: Pint.
kCLOCK_Gint	Clock gate name: Gint.
kCLOCK_Dma0	Clock gate name: Dma0.
kCLOCK_Crc0	Clock gate name: Crc.
kCLOCK_Wwdt	Clock gate name: Wwdt.
kCLOCK_Rtc0	Clock gate name: Rtc0.
kCLOCK_Mailbox	Clock gate name: Mailbox.
kCLOCK_Adc0	Clock gate name: Adc0.
kCLOCK_Adc1	Clock gate name: Adc1.
kCLOCK_Dac0	Clock gate name: Dac0.
kCLOCK_Mrt	Clock gate name: Mrt.
kCLOCK_Ostimer	Clock gate name: Ostimer.
kCLOCK_Sct	Clock gate name: Sct.
kCLOCK_Mcan	Clock gate name: Mcan.
kCLOCK_Utick	Clock gate name: Utick.
kCLOCK_FlexComm0	Clock gate name: FlexComm0.
kCLOCK_FlexComm1	Clock gate name: FlexComm1.
kCLOCK_FlexComm2	Clock gate name: FlexComm2.
kCLOCK_FlexComm3	Clock gate name: FlexComm3.
kCLOCK_FlexComm4	Clock gate name: FlexComm4.
kCLOCK_FlexComm5	Clock gate name: FlexComm5.
kCLOCK_FlexComm6	Clock gate name: FlexComm6.
kCLOCK_FlexComm7	Clock gate name: FlexComm7.
kCLOCK_MinUart0	Clock gate name: MinUart0.
kCLOCK_MinUart1	Clock gate name: MinUart1.
kCLOCK_MinUart2	Clock gate name: MinUart2.
kCLOCK_MinUart3	Clock gate name: MinUart3.
kCLOCK_MinUart4	Clock gate name: MinUart4.
kCLOCK_MinUart5	Clock gate name: MinUart5.
kCLOCK_MinUart6	Clock gate name: MinUart6.
kCLOCK_MinUart7	Clock gate name: MinUart7.
kCLOCK_LSpi0	Clock gate name: LSpi0.
kCLOCK_LSpi1	Clock gate name: LSpi1.
kCLOCK_LSpi2	Clock gate name: LSpi2.
kCLOCK_LSpi3	Clock gate name: LSpi3.
kCLOCK_LSpi4	Clock gate name: LSpi4.
kCLOCK_LSpi5	Clock gate name: LSpi5.
kCLOCK_LSpi6	Clock gate name: LSpi6.
kCLOCK_LSpi7	Clock gate name: LSpi7.
kCLOCK_BI2c0	Clock gate name: BI2c0.
kCLOCK_BI2c1	Clock gate name: BI2c1.
kCLOCK_BI2c2	Clock gate name: BI2c2.
kCLOCK_BI2c3	Clock gate name: BI2c3.
kCLOCK_BI2c4	Clock gate name: BI2c4.
kCLOCK_BI2c5	Clock gate name: BI2c5.
kCLOCK_BI2c6	Clock gate name: BI2c6.
kCLOCK_BI2c7	Clock gate name: BI2c7.
kCLOCK_FlexI2s0	Clock gate name: FlexI2s0.
kCLOCK_FlexI2s1	Clock gate name: FlexI2s1.
kCLOCK_FlexI2s2	Clock gate name: FlexI2s2.
kCLOCK_FlexI2s3	Clock gate name: FlexI2s3.
kCLOCK_FlexI2s4	Clock gate name: FlexI2s4.
kCLOCK_FlexI2s5	Clock gate name: FlexI2s5.
kCLOCK_FlexI2s6	Clock gate name: FlexI2s6.
kCLOCK_FlexI2s7	Clock gate name: FlexI2s7.
kCLOCK_Dmic	Clock gate name: Dmic.
kCLOCK_Timer2	Clock gate name: Timer2.
kCLOCK_Usbd0	Clock gate name: Usbd0.
kCLOCK_Timer0	Clock gate name: Timer0.
kCLOCK_Timer1	Clock gate name: Timer1.
kCLOCK_Dma1	Clock gate name: Dma1.
kCLOCK_Comp	Clock gate name: Comp.
kCLOCK_Freqme	Clock gate name: Freqme.
kCLOCK_Cdog	Clock gate name: Cdog.
kCLOCK_Rng	Clock gate name: Rng.
kCLOCK_Pmux1	Clock gate name: Pmux1.
kCLOCK_Sysctl	Clock gate name: Sysctl.
kCLOCK_Usbhmr0	Clock gate name: Usbhmr0.
kCLOCK_Usbhsl0	Clock gate name: Usbhsl0.
kCLOCK_Css	Clock gate name: Css.
kCLOCK_PowerQuad	Clock gate name: PowerQuad.
kCLOCK_Timer3	Clock gate name: Timer3.
kCLOCK_Timer4	Clock gate name: Timer4.
kCLOCK_Puf	Clock gate name: Puf.
kCLOCK_Pkc	Clock gate name: Pkc.
kCLOCK_AnalogCtrl	Clock gate name: AnalogCtrl.
kCLOCK_Hs_Lspi	Clock gate name: Lspi.
kCLOCK_Gpio_Sec	Clock gate name: Sec.
kCLOCK_Gpio_Sec_Int	Clock gate name: Int.
kCLOCK_I3c0	Clock gate name: I3c0.
kCLOCK_Enc0	Clock gate name: Enc0.
kCLOCK_Enc1	Clock gate name: Enc1.
kCLOCK_Pwm0	Clock gate name: Pwm0.
kCLOCK_Pwm1	Clock gate name: Pwm1.
kCLOCK_Aoi0	Clock gate name: Aoi0.
kCLOCK_Aoi1	Clock gate name: Aoi1.
kCLOCK_Ftm0	Clock gate name: Ftm0.
kCLOCK_Dac1	Clock gate name: Dac1.
kCLOCK_Dac2	Clock gate name: Dac2.
kCLOCK_Opamp0	Clock gate name: Opamp0.
kCLOCK_Opamp1	Clock gate name: Opamp1.
kCLOCK_Opamp2	Clock gate name: Opamp2.
kCLOCK_Hscmp0	Clock gate name: Hscmp0.
kCLOCK_Hscmp1	Clock gate name: Hscmp1.
kCLOCK_Hscmp2	Clock gate name: Hscmp2.
kCLOCK_Vref	Clock gate name: Vref.

enum clock_name_t

Enumerator
kCLOCK_CoreSysClk	Core/system clock (aka MAIN_CLK)
kCLOCK_BusClk	Bus clock (AHB clock)
kCLOCK_ClockOut	CLOCKOUT.
kCLOCK_FroHf	FRO48/96.
kCLOCK_Pll1Out	PLL1 Output.
kCLOCK_Mclk	MCLK.
kCLOCK_Fro12M	FRO12M.
kCLOCK_Fro1M	FRO1M.
kCLOCK_ExtClk	External Clock.
kCLOCK_Pll0Out	PLL0 Output.
kCLOCK_PllClkDiv	PLLCLKDIV clock.
kCLOCK_FlexI2S	FlexI2S clock.

enum clock_attach_id_t

Enumerator
kFRO12M_to_MAIN_CLK	Attach FRO12M to MAIN_CLK.
kEXT_CLK_to_MAIN_CLK	Attach EXT_CLK to MAIN_CLK.
kFRO1M_to_MAIN_CLK	Attach FRO1M to MAIN_CLK.
kFRO_HF_to_MAIN_CLK	Attach FRO_HF to MAIN_CLK.
kPLL0_to_MAIN_CLK	Attach PLL0 to MAIN_CLK.
kPLL1_to_MAIN_CLK	Attach PLL1 to MAIN_CLK.
kOSC32K_to_MAIN_CLK	Attach OSC32K to MAIN_CLK.
kSYSTICK_DIV_to_SYSTICK0	Attach SYSTICK_DIV to SYSTICK0.
kFRO1M_to_SYSTICK0	Attach FRO1M to SYSTICK0.
kOSC32K_to_SYSTICK0	Attach OSC32K to SYSTICK0.
kNONE_to_SYSTICK0	Attach NONE to SYSTICK0.
kTRACE_DIV_to_TRACE	Attach TRACE_DIV to TRACE.
kFRO1M_to_TRACE	Attach FRO1M to TRACE.
kOSC32K_to_TRACE	Attach OSC32K to TRACE.
kNONE_to_TRACE	Attach NONE to TRACE.
kMAIN_CLK_to_CTIMER0	Attach MAIN_CLK to CTIMER0.
kPLL0_to_CTIMER0	Attach PLL0 to CTIMER0.
kPLL1_to_CTIMER0	Attach PLL1 to CTIMER0.
kFRO_HF_to_CTIMER0	Attach FRO_HF to CTIMER0.
kFRO1M_to_CTIMER0	Attach FRO1M to CTIMER0.
kOSC32K_to_CTIMER0	Attach OSC32K to CTIMER0.
kNONE_to_CTIMER0	Attach NONE to CTIMER0.
kMAIN_CLK_to_CTIMER1	Attach MAIN_CLK to CTIMER1.
kPLL0_to_CTIMER1	Attach PLL0 to CTIMER1.
kPLL1_to_CTIMER1	Attach PLL1 to CTIMER1.
kFRO_HF_to_CTIMER1	Attach FRO_HF to CTIMER1.
kFRO1M_to_CTIMER1	Attach FRO1M to CTIMER1.
kMCLK_IN_to_CTIMER1	Attach MCLK_IN to CTIMER1.
kOSC32K_to_CTIMER1	Attach OSC32K to CTIMER1.
kNONE_to_CTIMER1	Attach NONE to CTIMER1.
kMAIN_CLK_to_CTIMER2	Attach MAIN_CLK to CTIMER2.
kPLL0_to_CTIMER2	Attach PLL0 to CTIMER2.
kPLL1_to_CTIMER2	Attach PLL1 to CTIMER2.
kFRO_HF_to_CTIMER2	Attach FRO_HF to CTIMER2.
kFRO1M_to_CTIMER2	Attach FRO1M to CTIMER2.
kMCLK_IN_to_CTIMER2	Attach MCLK_IN to CTIMER2.
kOSC32K_to_CTIMER2	Attach OSC32K to CTIMER2.
kNONE_to_CTIMER2	Attach NONE to CTIMER2.
kMAIN_CLK_to_CTIMER3	Attach MAIN_CLK to CTIMER3.
kPLL0_to_CTIMER3	Attach PLL0 to CTIMER3.
kPLL1_to_CTIMER3	Attach PLL1 to CTIMER3.
kFRO_HF_to_CTIMER3	Attach FRO_HF to CTIMER3.
kFRO1M_to_CTIMER3	Attach FRO1M to CTIMER3.
kMCLK_IN_to_CTIMER3	Attach MCLK_IN to CTIMER3.
kOSC32K_to_CTIMER3	Attach OSC32K to CTIMER3.
kNONE_to_CTIMER3	Attach NONE to CTIMER3.
kMAIN_CLK_to_CTIMER4	Attach MAIN_CLK to CTIMER4.
kPLL0_to_CTIMER4	Attach PLL0 to CTIMER4.
kPLL1_to_CTIMER4	Attach PLL1 to CTIMER4.
kFRO_HF_to_CTIMER4	Attach FRO_HF to CTIMER4.
kFRO1M_to_CTIMER4	Attach FRO1M to CTIMER4.
kMCLK_IN_to_CTIMER4	Attach MCLK_IN to CTIMER4.
kOSC32K_to_CTIMER4	Attach OSC32K to CTIMER4.
kNONE_to_CTIMER4	Attach NONE to CTIMER4.
kMAIN_CLK_to_CLKOUT	Attach MAIN_CLK to CLKOUT.
kPLL0_to_CLKOUT	Attach PLL0 to CLKOUT.
kEXT_CLK_to_CLKOUT	Attach EXT_CLK to CLKOUT.
kFRO_HF_to_CLKOUT	Attach FRO_HF to CLKOUT.
kFRO1M_to_CLKOUT	Attach FRO1M to CLKOUT.
kPLL1_to_CLKOUT	Attach PLL1 to CLKOUT.
kOSC32K_to_CLKOUT	Attach OSC32K to CLKOUT.
kNONE_to_CLKOUT	Attach NONE to CLKOUT.
kFRO12M_to_PLL0	Attach FRO12M to PLL0.
kEXT_CLK_to_PLL0	Attach EXT_CLK to PLL0.
kFRO1M_to_PLL0	Attach FRO1M to PLL0.
kOSC32K_to_PLL0	Attach OSC32K to PLL0.
kNONE_to_PLL0	Attach NONE to PLL0.
kFRO12M_to_PLL1	Attach FRO12M to PLL1.
kEXT_CLK_to_PLL1	Attach EXT_CLK to PLL1.
kFRO1M_to_PLL1	Attach FRO1M to PLL1.
kOSC32K_to_PLL1	Attach OSC32K to PLL1.
kNONE_to_PLL1	Attach NONE to PLL1.
kMCAN_DIV_to_MCAN	Attach MCAN_DIV to MCAN.
kFRO1M_to_MCAN	Attach FRO1M to MCAN.
kOSC32K_to_MCAN	Attach OSC32K to MCAN.
kNONE_to_MCAN	Attach NONE to MCAN.
kMAIN_CLK_to_ADC0	Attach MAIN_CLK to ADC0.
kPLL0_to_ADC0	Attach PLL0 to ADC0.
kFRO_HF_to_ADC0	Attach FRO_HF to ADC0.
kEXT_CLK_to_ADC0	Attach XO to ADC0.
kNONE_to_ADC0	Attach NONE to ADC0.
kMAIN_CLK_to_ADC1	Attach MAIN_CLK to ADC1.
kPLL0_to_ADC1	Attach PLL0 to ADC1.
kFRO_HF_to_ADC1	Attach FRO_HF to ADC1.
kNONE_to_ADC1	Attach NONE to ADC1.
kMAIN_CLK_to_USB0	Attach MAIN_CLK to USB0.
kPLL0_to_USB0	Attach PLL0 to USB0.
kFRO_HF_to_USB0	Attach FRO_HF to USB0.
kPLL1_to_USB0	Attach PLL1 to USB0.
kNONE_to_USB0	Attach NONE to USB0.
kMAIN_CLK_to_FLEXCOMM0	Attach MAIN_CLK to FLEXCOMM0.
kMAIN_CLK_FRG0_to_FLEXCOMM0	Attach Main clock to FlexComm0.
kPLL_CLK_DIV_FRG0_to_FLEXCOMM0	Attach PLL clock DIV Frg to FlexComm0.
kFRO_HF_DIV_FRG0_to_FLEXCOMM0	Attach FRO HF DIV FRG to FlexComm0.
kFRO12M_to_FLEXCOMM0	Attach FRO12M to FLEXCOMM0.
kFRO_HF_DIV_to_FLEXCOMM0	Attach FRO_HF_DIV to FLEXCOMM0.
kFRO1M_to_FLEXCOMM0	Attach FRO1M to FLEXCOMM0.
kMCLK_IN_to_FLEXCOMM0	Attach MCLK_IN to FLEXCOMM0.
kOSC32K_to_FLEXCOMM0	Attach OSC32K to FLEXCOMM0.
kNONE_to_FLEXCOMM0	Attach NONE to FLEXCOMM0.
kMAIN_CLK_to_FLEXCOMM1	Attach MAIN_CLK to FLEXCOMM1.
kMAIN_CLK_FRG1_to_FLEXCOMM1	Attach Main clock to FlexComm1.
kPLL_CLK_DIV_FRG1_to_FLEXCOMM1	Attach PLL clock DIV Frg to FlexComm1.
kFRO_HF_DIV_FRG1_to_FLEXCOMM1	Attach FRO HF DIV FRG to FlexComm1.
kFRO12M_to_FLEXCOMM1	Attach FRO12M to FLEXCOMM1.
kFRO_HF_DIV_to_FLEXCOMM1	Attach FRO_HF_DIV to FLEXCOMM1.
kFRO1M_to_FLEXCOMM1	Attach FRO1M to FLEXCOMM1.
kMCLK_IN_to_FLEXCOMM1	Attach MCLK_IN to FLEXCOMM1.
kOSC32K_to_FLEXCOMM1	Attach OSC32K to FLEXCOMM1.
kNONE_to_FLEXCOMM1	Attach NONE to FLEXCOMM1.
kMAIN_CLK_to_FLEXCOMM2	Attach MAIN_CLK to FLEXCOMM2.
kMAIN_CLK_FRG2_to_FLEXCOMM2	Attach Main clock to FlexComm2.
kPLL_CLK_DIV_FRG2_to_FLEXCOMM2	Attach PLL clock DIV Frg to FlexComm2.
kFRO_HF_DIV_FRG2_to_FLEXCOMM2	Attach FRO HF DIV FRG to FlexComm2.
kFRO12M_to_FLEXCOMM2	Attach FRO12M to FLEXCOMM2.
kFRO_HF_DIV_to_FLEXCOMM2	Attach FRO_HF_DIV to FLEXCOMM2.
kFRO1M_to_FLEXCOMM2	Attach FRO1M to FLEXCOMM2.
kMCLK_IN_to_FLEXCOMM2	Attach MCLK_IN to FLEXCOMM2.
kOSC32K_to_FLEXCOMM2	Attach OSC32K to FLEXCOMM2.
kNONE_to_FLEXCOMM2	Attach NONE to FLEXCOMM2.
kMAIN_CLK_to_FLEXCOMM3	Attach MAIN_CLK to FLEXCOMM3.
kMAIN_CLK_FRG3_to_FLEXCOMM3	Attach Main clock to FlexComm3.
kPLL_CLK_DIV_FRG3_to_FLEXCOMM3	Attach PLL clock DIV Frg to FlexComm3.
kFRO_HF_DIV_FRG3_to_FLEXCOMM3	Attach FRO HF DIV FRG to FlexComm3.
kFRO12M_to_FLEXCOMM3	Attach FRO12M to FLEXCOMM3.
kFRO_HF_DIV_to_FLEXCOMM3	Attach FRO_HF_DIV to FLEXCOMM3.
kFRO1M_to_FLEXCOMM3	Attach FRO1M to FLEXCOMM3.
kMCLK_IN_to_FLEXCOMM3	Attach MCLK_IN to FLEXCOMM3.
kOSC32K_to_FLEXCOMM3	Attach OSC32K to FLEXCOMM3.
kNONE_to_FLEXCOMM3	Attach NONE to FLEXCOMM3.
kMAIN_CLK_to_FLEXCOMM4	Attach MAIN_CLK to FLEXCOMM4.
kMAIN_CLK_FRG4_to_FLEXCOMM4	Attach Main clock to FlexComm4.
kPLL_CLK_DIV_FRG4_to_FLEXCOMM4	Attach PLL clock DIV Frg to FlexComm4.
kFRO_HF_DIV_FRG4_to_FLEXCOMM4	Attach FRO HF DIV FRG to FlexComm4.
kFRO12M_to_FLEXCOMM4	Attach FRO12M to FLEXCOMM4.
kFRO_HF_DIV_to_FLEXCOMM4	Attach FRO_HF_DIV to FLEXCOMM4.
kFRO1M_to_FLEXCOMM4	Attach FRO1M to FLEXCOMM4.
kMCLK_IN_to_FLEXCOMM4	Attach MCLK_IN to FLEXCOMM4.
kOSC32K_to_FLEXCOMM4	Attach OSC32K to FLEXCOMM4.
kNONE_to_FLEXCOMM4	Attach NONE to FLEXCOMM4.
kMAIN_CLK_to_FLEXCOMM5	Attach MAIN_CLK to FLEXCOMM5.
kMAIN_CLK_FRG5_to_FLEXCOMM5	Attach Main clock to FlexComm5.
kPLL_CLK_DIV_FRG5_to_FLEXCOMM5	Attach PLL clock DIV Frg to FlexComm5.
kFRO_HF_DIV_FRG5_to_FLEXCOMM5	Attach FRO HF DIV FRG to FlexComm5.
kFRO12M_to_FLEXCOMM5	Attach FRO12M to FLEXCOMM5.
kFRO_HF_DIV_to_FLEXCOMM5	Attach FRO_HF_DIV to FLEXCOMM5.
kFRO1M_to_FLEXCOMM5	Attach FRO1M to FLEXCOMM5.
kMCLK_IN_to_FLEXCOMM5	Attach MCLK_IN to FLEXCOMM5.
kOSC32K_to_FLEXCOMM5	Attach OSC32K to FLEXCOMM5.
kNONE_to_FLEXCOMM5	Attach NONE to FLEXCOMM5.
kMAIN_CLK_to_FLEXCOMM6	Attach MAIN_CLK to FLEXCOMM6.
kMAIN_CLK_FRG6_to_FLEXCOMM6	Attach Main clock to FlexComm6.
kPLL_CLK_DIV_FRG6_to_FLEXCOMM6	Attach PLL clock DIV Frg to FlexComm6.
kFRO_HF_DIV_FRG6_to_FLEXCOMM6	Attach FRO HF DIV FRG to FlexComm6.
kFRO12M_to_FLEXCOMM6	Attach FRO12M to FLEXCOMM6.
kFRO_HF_DIV_to_FLEXCOMM6	Attach FRO_HF_DIV to FLEXCOMM6.
kFRO1M_to_FLEXCOMM6	Attach FRO1M to FLEXCOMM6.
kMCLK_IN_to_FLEXCOMM6	Attach MCLK_IN to FLEXCOMM6.
kOSC32K_to_FLEXCOMM6	Attach OSC32K to FLEXCOMM6.
kNONE_to_FLEXCOMM6	Attach NONE to FLEXCOMM6.
kMAIN_CLK_to_FLEXCOMM7	Attach MAIN_CLK to FLEXCOMM7.
kMAIN_CLK_FRG7_to_FLEXCOMM7	Attach Main clock to FlexComm7.
kPLL_CLK_DIV_FRG7_to_FLEXCOMM7	Attach PLL clock DIV Frg to FlexComm7.
kFRO_HF_DIV_FRG7_to_FLEXCOMM7	Attach PLL clock DIV Frg to FlexComm7.
kFRO12M_to_FLEXCOMM7	Attach FRO12M to FLEXCOMM7.
kFRO_HF_DIV_to_FLEXCOMM7	Attach FRO_HF_DIV to FLEXCOMM7.
kFRO1M_to_FLEXCOMM7	Attach FRO1M to FLEXCOMM7.
kMCLK_IN_to_FLEXCOMM7	Attach MCLK_IN to FLEXCOMM7.
kOSC32K_to_FLEXCOMM7	Attach OSC32K to FLEXCOMM7.
kNONE_to_FLEXCOMM7	Attach NONE to FLEXCOMM7.
kMAIN_CLK_to_HSLSPI	Attach MAIN_CLK to HSLSPI.
kPLL_CLK_DIV_to_HSLSPI	Attach PLL_CLK_DIV to HSLSPI.
kFRO12M_to_HSLSPI	Attach FRO12M to HSLSPI.
kFRO_HF_DIV_to_HSLSPI	Attach FRO_HF_DIV to HSLSPI.
kFRO1M_to_HSLSPI	Attach FRO1M to HSLSPI.
kOSC32K_to_HSLSPI	Attach OSC32K to HSLSPI.
kNONE_to_HSLSPI	Attach NONE to HSLSPI.
kFRO_HF_to_MCLK	Attach FRO_HF to MCLK.
kPLL0_to_MCLK	Attach PLL0 to MCLK.
kNONE_to_MCLK	Attach NONE to MCLK.
kMAIN_CLK_to_SCT	Attach MAIN_CLK to SCT.
kPLL0_to_SCT	Attach PLL0 to SCT.
kEXT_CLK_to_SCT	Attach EXT_CLK to SCT.
kFRO_HF_to_SCT	Attach FRO_HF to SCT.
kPLL1_to_SCT	Attach PLL1 to SCT.
kMCLK_IN_to_SCT	Attach MCLK_IN to SCT.
kNONE_to_SCT	Attach NONE to SCT.
kMAIN_CLK_to_DAC0	Attach MAIN_CLK to DAC0.
kPLL0_to_DAC0	Attach PLL0 to DAC0.
kFRO_HF_to_DAC0	Attach FRO_HF to DAC0.
kFRO12M_to_DAC0	Attach FRO12M to DAC0.
kPLL1_to_DAC0	Attach PLL1 to DAC0.
kFRO1M_to_DAC0	Attach FRO1M to DAC0.
kNONE_to_DAC0	Attach NONE to DAC0.
kMAIN_CLK_to_DAC1	Attach MAIN_CLK to DAC1.
kPLL0_to_DAC1	Attach PLL0 to DAC1.
kFRO_HF_to_DAC1	Attach FRO_HF to DAC1.
kFRO12M_to_DAC1	Attach FRO12M to DAC1.
kPLL1_to_DAC1	Attach PLL1 to DAC1.
kFRO1M_to_DAC1	Attach FRO1M to DAC1.
kNONE_to_DAC1	Attach NONE to DAC1.
kMAIN_CLK_to_DAC2	Attach MAIN_CLK to DAC2.
kPLL0_to_DAC2	Attach PLL0 to DAC2.
kFRO_HF_to_DAC2	Attach FRO_HF to DAC2.
kFRO12M_to_DAC2	Attach FRO12M to DAC2.
kPLL1_to_DAC2	Attach PLL1 to DAC2.
kFRO1M_to_DAC2	Attach FRO1M to DAC2.
kNONE_to_DAC2	Attach NONE to DAC2.
kMAIN_CLK_to_FLEXSPI	Attach MAIN_CLK to FLEXSPI.
kPLL0_to_FLEXSPI	Attach PLL0 to FLEXSPI.
kFRO_HF_to_FLEXSPI	Attach FRO_HF to FLEXSPI.
kPLL1_to_FLEXSPI	Attach PLL1 to FLEXSPI.
kNONE_to_FLEXSPI	Attach NONE to FLEXSPI.
kPLL0_to_PLLCLKDIV	Attach PLL0 to PLLCLKDIV.
kPLL1_to_PLLCLKDIV	Attach PLL1 to PLLCLKDIV.
kNONE_to_PLLCLKDIV	Attach NONE to PLLCLKDIV.
kMAIN_CLK_to_I3CFCLK	Attach MAIN_CLK to I3CFCLK.
kFRO_HF_DIV_to_I3CFCLK	Attach FRO_HF_DIV to I3CFCLK.
kNONE_to_I3CFCLK	Attach NONE to I3CFCLK.
kI3CFCLKSEL_to_I3CFCLKSTC	Attach I3CFCLKSEL to I3CFCLKSTC.
kFRO1M_to_I3CFCLKSTC	Attach FRO1M to I3CFCLKSTC.
kNONE_to_I3CFCLKSTC	Attach NONE to I3CFCLKSTC.
kMAIN_CLK_to_DMIC	Attach MAIN_CLK to DMIC.
kPLL0_to_DMIC	Attach PLL0 to DMIC.
kEXT_CLK_to_DMIC	Attach EXT_CLK to DMIC.
kFRO_HF_to_DMIC	Attach FRO_HF to DMIC.
kPLL1_to_DMIC	Attach PLL1 to DMIC.
kMCLK_IN_to_DMIC	Attach MCLK_IN to DMIC.
kNONE_to_DMIC	Attach NONE to DMIC.
kFRO32K_to_FCOSC32K	Attach FRO32K to FCOSC32K.
kXTAL32K_to_FCOSC32K	Attach XTAL32K to FCOSC32K.
kFRO32K_to_OSC32K	Attach FRO32K to OSC32K.
kXTAL32K_to_OSC32K	Attach XTAL32K to OSC32K.
kFRO32K_to_FC32K	Attach FRO32K to FC32K.
kXTAL32K_to_FC32K	Attach XTAL32K to FC32K.
kFRO32K_to_OSTIMER	Attach FRO32K to OSTIMER.
kOSC32K_to_OSTIMER	Attach OSC32K to OSTIMER.
kFRO1M_to_OSTIMER	Attach FRO1M to OSTIMER.
kAHB_CLK_to_OSTIMER	Attach AHB_CLK to OSTIMER.
kNONE_to_NONE	Attach NONE to NONE.

enum clock_div_name_t

Enumerator
kCLOCK_DivSystickClk	Systick Clock Divider.
kCLOCK_DivArmTrClkDiv	Trace Clock Divider.
kCLOCK_DivCanClk	Can Clock Divider.
kCLOCK_DivFlexFrg0	FRGCTRL0 register.
kCLOCK_DivFlexFrg1	FRGCTRL1 register.
kCLOCK_DivFlexFrg2	FRGCTRL2 register.
kCLOCK_DivFlexFrg3	FRGCTRL3 register.
kCLOCK_DivFlexFrg4	FRGCTRL4 register.
kCLOCK_DivFlexFrg5	FRGCTRL5 register.
kCLOCK_DivFlexFrg6	FRGCTRL6 register.
kCLOCK_DivFlexFrg7	FRGCTRL7 register.
kCLOCK_DivAhbClk	Ahb Clock Divider.
kCLOCK_DivClkOut	Clk Out Divider.
kCLOCK_DivFrohfClk	Frohf Divider.
kCLOCK_DivWdtClk	Wdt Clock Divider.
kCLOCK_DivAdc0Clk	Adc0 Clock Divider.
kCLOCK_DivUsb0Clk	Usb0 Clock Divider.
kCLOCK_DivMclk	Mclk Divider.
kCLOCK_DivSctClk	Sct Clock Divider.
kCLOCK_DivPllClk	Pll0 Clock Divider.
kCLOCK_DivCtimer0Clk	Ctimer0 Clock Divider.
kCLOCK_DivCtimer1Clk	Ctimer1 Clock Divider.
kCLOCK_DivCtimer2Clk	Ctimer2 Clock Divider.
kCLOCK_DivCtimer3Clk	Ctimer3 Clock Divider.
kCLOCK_DivCtimer4Clk	Ctimer4 Clock Divider.
kCLOCK_DivAdc1Clk	Adc1 Clock Divider.
kCLOCK_DivDac0Clk	Dac0 Clock Divider.
kCLOCK_DivDac1Clk	Dac1 Clock Divider.
kCLOCK_DivDac2Clk	Dac2 Clock Divider.
kCLOCK_DivFlexSpiClk	Flex Spi Clock Divider.
kCLOCK_DivI3cFclkStc	I3c Fclk Stc Divider.
kCLOCK_DivI3cFclkS	I3c Fclk S Divider.
kCLOCK_DivI3cFclk	I3c Fclk Divider.
kCLOCK_DivDmicClk	Dmic Clock Divider.
kCLOCK_DivFlexcom0Clk	Flexcom0 Clock Divider.
kCLOCK_DivFlexcom1Clk	Flexcom1 Clock Divider.
kCLOCK_DivFlexcom2Clk	Flexcom2 Clock Divider.
kCLOCK_DivFlexcom3Clk	Flexcom3 Clock Divider.
kCLOCK_DivFlexcom4Clk	Flexcom4 Clock Divider.
kCLOCK_DivFlexcom5Clk	Flexcom5 Clock Divider.
kCLOCK_DivFlexcom6Clk	Flexcom6 Clock Divider.
kCLOCK_DivFlexcom7Clk	Flexcom7 Clock Divider.

enum ss_progmodfm_t

Enumerator
kSS_MF_512	Nss = 512 (fm ? 3.9 - 7.8 kHz)
kSS_MF_384	Nss ?= 384 (fm ? 5.2 - 10.4 kHz)
kSS_MF_256	Nss = 256 (fm ? 7.8 - 15.6 kHz)
kSS_MF_128	Nss = 128 (fm ? 15.6 - 31.3 kHz)
kSS_MF_64	Nss = 64 (fm ? 32.3 - 64.5 kHz)
kSS_MF_32	Nss = 32 (fm ? 62.5- 125 kHz)
kSS_MF_24	Nss ?= 24 (fm ? 83.3- 166.6 kHz)
kSS_MF_16	Nss = 16 (fm ? 125- 250 kHz)

enum ss_progmoddp_t

Enumerator
kSS_MR_K0	k = 0 (no spread spectrum)
kSS_MR_K1	k = 1
kSS_MR_K1_5	k = 1.5
kSS_MR_K2	k = 2
kSS_MR_K3	k = 3
kSS_MR_K4	k = 4
kSS_MR_K6	k = 6
kSS_MR_K8	k = 8

enum ss_modwvctrl_t

Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

Enumerator

kSS_MC_NOC

no compensation

kSS_MC_RECC

recommended setting

kSS_MC_MAXC

max.

compensation

enum pll_error_t

Enumerator
kStatus_PLL_Success	PLL operation was successful.
kStatus_PLL_OutputTooLow	PLL output rate request was too low.
kStatus_PLL_OutputTooHigh	PLL output rate request was too high.
kStatus_PLL_InputTooLow	PLL input rate is too low.
kStatus_PLL_InputTooHigh	PLL input rate is too high.
kStatus_PLL_OutsideIntLimit	Requested output rate isn't possible.
kStatus_PLL_CCOTooLow	Requested CCO rate isn't possible.
kStatus_PLL_CCOTooHigh	Requested CCO rate isn't possible.

enum clock_usbfs_src_t

Enumerator
kCLOCK_UsbfsSrcFro	Use FRO 96 MHz.
kCLOCK_UsbfsSrcPll0	Use PLL0 output.
kCLOCK_UsbfsSrcMainClock	Use Main clock.
kCLOCK_UsbfsSrcPll1	Use PLL1 clock.
kCLOCK_UsbfsSrcNone	this may be selected in order to reduce power when no output is needed.

enum clock_usb_phy_src_t

Enumerator
kCLOCK_UsbPhySrcExt	Use external crystal.

Function Documentation

static void CLOCK_EnableClock ( clock_ip_name_t clk )

inlinestatic

Parameters

clk	: Clock to be enabled.

Returns: Nothing

static void CLOCK_DisableClock ( clock_ip_name_t clk )

inlinestatic

Parameters

clk	: Clock to be Disabled.

Returns: Nothing

status_t CLOCK_SetupFROClocking ( uint32_t iFreq )

Parameters

iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)

Returns: returns success or fail status.

void CLOCK_SetFLASHAccessCyclesForFreq ( uint32_t system_freq_hz )

Parameters

system_freq_hz : Input frequency

Returns: Nothing

status_t CLOCK_SetupExtClocking ( uint32_t iFreq )

Parameters

iFreq : Desired frequency (must be equal to exact rate in Hz)

Returns: returns success or fail status.

status_t CLOCK_SetupI2SMClkClocking ( uint32_t iFreq )

Parameters

iFreq : Desired frequency (must be equal to exact rate in Hz)

Returns: returns success or fail status.

status_t CLOCK_SetupPLUClkInClocking ( uint32_t iFreq )

Parameters

iFreq : Desired frequency (must be equal to exact rate in Hz)

Returns: returns success or fail status.

void CLOCK_AttachClk ( clock_attach_id_t connection )

Parameters

connection : Clock to be configured.

Returns: Nothing

clock_attach_id_t CLOCK_GetClockAttachId ( clock_attach_id_t attachId )

Parameters

attachId : Clock attach id to get.

Returns: Clock source value.

void CLOCK_SetClkDiv	(	clock_div_name_t	div_name,
		uint32_t	divided_by_value,
		bool	reset
	)

Parameters

div_name	: Clock divider name
divided_by_value,:	Value to be divided
reset	: Whether to reset the divider counter.

Returns: Nothing

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

Returns: Frequency of selected clock

uint32_t CLOCK_GetFro12MFreq ( void )

Returns: Frequency of FRO 12MHz

uint32_t CLOCK_GetFro1MFreq ( void )

Returns: Frequency of FRO 1MHz

uint32_t CLOCK_GetClockOutClkFreq ( void )

Returns: Frequency of ClockOut

uint32_t CLOCK_GetMCanClkFreq ( void )

Returns: Frequency of Can.

uint32_t CLOCK_GetAdcClkFreq ( uint32_t id )

Returns: Frequency of Adc.

uint32_t CLOCK_GetUsb0ClkFreq ( void )

Returns: Frequency of Usb0 Clock.

uint32_t CLOCK_GetMclkClkFreq ( void )

Returns: Frequency of MClk Clock.

uint32_t CLOCK_GetSctClkFreq ( void )

Returns: Frequency of SCTimer Clock.

uint32_t CLOCK_GetExtClkFreq ( void )

Returns: Frequency of External Clock. If no external clock is used returns 0.

uint32_t CLOCK_GetWdtClkFreq ( void )

Returns: Frequency of Watchdog

uint32_t CLOCK_GetFroHfFreq ( void )

Returns: Frequency of High-Freq output of FRO

uint32_t CLOCK_GetPll0OutFreq ( void )

Returns: Frequency of PLL

uint32_t CLOCK_GetPll1OutFreq ( void )

Returns: Frequency of PLL

uint32_t CLOCK_GetPllClkDivFreq ( void )

Returns: Frequency of PLL_CLK_DIV

uint32_t CLOCK_GetOsc32KFreq ( void )

Returns: Frequency of 32kHz osc

uint32_t CLOCK_GetFC32KFreq ( void )

Returns: Frequency of Flexcomm 32kHz osc

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Frequency of Core System

uint32_t CLOCK_GetI2SMClkFreq ( void )

Returns: Frequency of I2S MCLK Clock

uint32_t CLOCK_GetFrgFreq ( uint32_t id )

Returns: Frequency of FRG Clock

uint32_t CLOCK_GetFlexCommClkFreq ( uint32_t id )

Returns: Frequency of FlexComm Clock

uint32_t CLOCK_GetHsLspiClkFreq ( void )

Returns: Frequency of High speed SPI Clock

uint32_t CLOCK_GetCTimerClkFreq ( uint32_t id )

Returns: Frequency of CTimer functional Clock

uint32_t CLOCK_GetSystickClkFreq ( void )

Returns: Frequency of Systick Clock

uint32_t CLOCK_GetFlexSpiClkFreq ( void )

Returns: Frequency of FlexSPI Clock

uint32_t CLOCK_GetDmicClkFreq ( void )

Returns: Frequency of DMIC Clock

uint32_t CLOCK_GetDacClkFreq ( uint32_t id )

Returns: Frequency of DAC Clock

uint32_t CLOCK_GetI3cSTCClkFreq ( void )

Returns: Frequency of I3C function slow TC Clock

uint32_t CLOCK_GetI3cSClkFreq ( void )

Returns: Frequency of I3C function slow Clock

uint32_t CLOCK_GetI3cClkFreq ( void )

Returns: Frequency of I3C function Clock

uint32_t CLOCK_GetPLL0InClockRate ( void )

Returns: PLL0 input clock rate

uint32_t CLOCK_GetPLL1InClockRate ( void )

Returns: PLL1 input clock rate

uint32_t CLOCK_GetPLL0OutClockRate ( bool recompute )

Parameters

recompute : Forces a PLL rate recomputation if true

Returns: PLL0 output clock rate

Note: The PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

uint32_t CLOCK_GetPLL1OutClockRate ( bool recompute )

Parameters

recompute : Forces a PLL rate recomputation if true

Returns: PLL1 output clock rate

Note: The PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

__STATIC_INLINE void CLOCK_SetBypassPLL0 ( bool bypass )

bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass

Returns: PLL0 output clock rate

__STATIC_INLINE void CLOCK_SetBypassPLL1 ( bool bypass )

bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass

Returns: PLL1 output clock rate

__STATIC_INLINE bool CLOCK_IsPLL0Locked ( void )

Returns: true if the PLL is locked, false if not locked

__STATIC_INLINE bool CLOCK_IsPLL1Locked ( void )

Returns: true if the PLL1 is locked, false if not locked

void CLOCK_SetStoredPLL0ClockRate ( uint32_t rate )

Parameters

rate,: Current rate of the PLL0

Returns: Nothing

uint32_t CLOCK_GetPLL0OutFromSetup ( pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: System PLL output clock rate the setup structure will generate

uint32_t CLOCK_GetPLL1OutFromSetup ( pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: PLL0 output clock rate the setup structure will generate

pll_error_t CLOCK_SetupPLL0Data	(	pll_config_t *	pControl,
		pll_setup_t *	pSetup
	)

Parameters

pControl	: Pointer to populated PLL control structure to generate setup with
pSetup	: Pointer to PLL setup structure to be filled

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: Actual frequency for setup may vary from the desired frequency based on the accuracy of input clocks, rounding, non-fractional PLL mode, etc.

pll_error_t CLOCK_SetupPLL0Prec	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetPLL0Freq ( const pll_setup_t * pSetup )

Parameters

pSetup : Pointer to populated PLL setup structure

Returns: kStatus_PLL_Success on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetPLL1Freq ( const pll_setup_t * pSetup )

Parameters

pSetup : Pointer to populated PLL setup structure

Returns: kStatus_PLL_Success on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

void CLOCK_SetupPLL0Mult	(	uint32_t	multiply_by,
		uint32_t	input_freq
	)

Parameters

multiply_by	: multiplier
input_freq	: Clock input frequency of the PLL

Returns: Nothing

Note: Unlike the Chip_Clock_SetupSystemPLLPrec() function, this function does not disable or enable PLL power, wait for PLL lock, or adjust system voltages. These must be done in the application. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

static void CLOCK_DisableUsbDevicefs0Clock ( clock_ip_name_t clk )

inlinestatic

Disable USB clock.

bool CLOCK_EnableUsbfs0DeviceClock	(	clock_usbfs_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB Device Full Speed clock.

bool CLOCK_EnableUsbfs0HostClock	(	clock_usbfs_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB HOST Full Speed clock.

void CLOCK_EnableOstimer32kClock ( void )

Returns: Nothing

void CLOCK_XtalHfCapabankTrim	(	int32_t	pi32_hfXtalIecLoadpF_x100,
		int32_t	pi32_hfXtalPPcbParCappF_x100,
		int32_t	pi32_hfXtalNPcbParCappF_x100
	)

Parameters

pi32_hfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_hfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_hfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns: none

Note: Following default Values can be used: pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void CLOCK_Xtal32khzCapabankTrim	(	int32_t	pi32_32kfXtalIecLoadpF_x100,
		int32_t	pi32_32kfXtalPPcbParCappF_x100,
		int32_t	pi32_32kfXtalNPcbParCappF_x100
	)

Parameters

pi32_32kfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns: none

Note: Following default Values can be used: pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void CLOCK_FroHfTrim ( void )

Returns: none

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