Reset Driver

Overview

Reset driver supports peripheral reset and system reset.

Macros
#define	ADC_RSTS

Enumerations
enum	SYSCON_RSTn_t {   kROM_RST_SHIFT_RSTn = 0 | 1U,   kSRAM1_RST_SHIFT_RSTn = 0 | 3U,   kSRAM2_RST_SHIFT_RSTn = 0 | 4U,   kFLASH_RST_SHIFT_RSTn = 0 | 7U,   kFMC_RST_SHIFT_RSTn = 0 | 8U,   kMUX0_RST_SHIFT_RSTn = 0 | 11U,   kIOCON_RST_SHIFT_RSTn = 0 | 13U,   kGPIO0_RST_SHIFT_RSTn = 0 | 14U,   kGPIO1_RST_SHIFT_RSTn = 0 | 15U,   kPINT_RST_SHIFT_RSTn = 0 | 18U,   kGINT_RST_SHIFT_RSTn = 0 | 19U,   kDMA0_RST_SHIFT_RSTn = 0 | 20U,   kCRC_RST_SHIFT_RSTn = 0 | 21U,   kWWDT_RST_SHIFT_RSTn = 0 | 22U,   kRTC_RST_SHIFT_RSTn = 0 | 23U,   kMAILBOX_RST_SHIFT_RSTn = 0 | 26U,   kADC0_RST_SHIFT_RSTn = 0 | 27U,   kMRT_RST_SHIFT_RSTn = 65536 | 0U,   kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U,   kSCT0_RST_SHIFT_RSTn = 65536 | 2U,   kMCAN_RST_SHIFT_RSTn = 65536 | 7U,   kUTICK_RST_SHIFT_RSTn = 65536 | 10U,   kFC0_RST_SHIFT_RSTn = 65536 | 11U,   kFC1_RST_SHIFT_RSTn = 65536 | 12U,   kFC2_RST_SHIFT_RSTn = 65536 | 13U,   kFC3_RST_SHIFT_RSTn = 65536 | 14U,   kFC4_RST_SHIFT_RSTn = 65536 | 15U,   kFC5_RST_SHIFT_RSTn = 65536 | 16U,   kFC6_RST_SHIFT_RSTn = 65536 | 17U,   kFC7_RST_SHIFT_RSTn = 65536 | 18U,   kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U,   kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U,   kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U,   kEZHA_RST_SHIFT_RSTn = 65536 | 30U,   kEZHB_RST_SHIFT_RSTn = 65536 | 31U,   kDMA1_RST_SHIFT_RSTn = 131072 | 1U,   kCMP_RST_SHIFT_RSTn = 131072 | 2U,   kSRAM3_RST_SHIFT_RSTn = 131072 | 6U,   kFREQME_RST_SHIFT_RSTn = 131072 | 8U,   kCDOG_RST_SHIFT_RSTn = 131072 | 11U,   kRNG_RST_SHIFT_RSTn = 131072 | 13U,   kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U,   kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U,   kPLULUT_RST_SHIFT_RSTn = 131072 | 20U,   kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U,   kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U,   kPUF_RST_SHIFT_RSTn = 131072 | 23U,   kCASPER_RST_SHIFT_RSTn = 131072 | 24U,   kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U,   kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U,   kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U,   kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U }
	Enumeration for peripheral reset control bits. More...

Functions
void	RESET_SetPeripheralReset (reset_ip_name_t peripheral)
	Assert reset to peripheral. More...
void	RESET_ClearPeripheralReset (reset_ip_name_t peripheral)
	Clear reset to peripheral. More...
void	RESET_PeripheralReset (reset_ip_name_t peripheral)
	Reset peripheral module. More...

Driver version
#define	FSL_RESET_DRIVER_VERSION   (MAKE_VERSION(2, 3, 3))
	reset driver version 2.3.3. More...

Macro Definition Documentation

#define FSL_RESET_DRIVER_VERSION   (MAKE_VERSION(2, 3, 3))

#define ADC_RSTS

Value:

{                        \
        kADC0_RST_SHIFT_RSTn \
    } /* Reset bits for ADC peripheral */

Array initializers with peripheral reset bits

Enumeration Type Documentation

enum SYSCON_RSTn_t

Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers

Enumerator
kROM_RST_SHIFT_RSTn	ROM reset control
kSRAM1_RST_SHIFT_RSTn	SRAM1 reset control
kSRAM2_RST_SHIFT_RSTn	SRAM2 reset control
kFLASH_RST_SHIFT_RSTn	Flash controller reset control
kFMC_RST_SHIFT_RSTn	Flash accelerator reset control
kMUX0_RST_SHIFT_RSTn	Input mux0 reset control
kIOCON_RST_SHIFT_RSTn	IOCON reset control
kGPIO0_RST_SHIFT_RSTn	GPIO0 reset control
kGPIO1_RST_SHIFT_RSTn	GPIO1 reset control
kPINT_RST_SHIFT_RSTn	Pin interrupt (PINT) reset control
kGINT_RST_SHIFT_RSTn	Grouped interrupt (PINT) reset control.
kDMA0_RST_SHIFT_RSTn	DMA reset control
kCRC_RST_SHIFT_RSTn	CRC reset control
kWWDT_RST_SHIFT_RSTn	Watchdog timer reset control
kRTC_RST_SHIFT_RSTn	RTC reset control
kMAILBOX_RST_SHIFT_RSTn	Mailbox reset control
kADC0_RST_SHIFT_RSTn	ADC0 reset control
kMRT_RST_SHIFT_RSTn	Multi-rate timer (MRT) reset control
kOSTIMER0_RST_SHIFT_RSTn	OSTimer0 reset control
kSCT0_RST_SHIFT_RSTn	SCTimer/PWM 0 (SCT0) reset control
kMCAN_RST_SHIFT_RSTn	MCAN reset control
kUTICK_RST_SHIFT_RSTn	Micro-tick timer reset control
kFC0_RST_SHIFT_RSTn	Flexcomm Interface 0 reset control
kFC1_RST_SHIFT_RSTn	Flexcomm Interface 1 reset control
kFC2_RST_SHIFT_RSTn	Flexcomm Interface 2 reset control
kFC3_RST_SHIFT_RSTn	Flexcomm Interface 3 reset control
kFC4_RST_SHIFT_RSTn	Flexcomm Interface 4 reset control
kFC5_RST_SHIFT_RSTn	Flexcomm Interface 5 reset control
kFC6_RST_SHIFT_RSTn	Flexcomm Interface 6 reset control
kFC7_RST_SHIFT_RSTn	Flexcomm Interface 7 reset control
kCTIMER2_RST_SHIFT_RSTn	CTimer 2 reset control
kCTIMER0_RST_SHIFT_RSTn	CTimer 0 reset control
kCTIMER1_RST_SHIFT_RSTn	CTimer 1 reset control
kEZHA_RST_SHIFT_RSTn	EZHA reset control
kEZHB_RST_SHIFT_RSTn	EZHB reset control
kDMA1_RST_SHIFT_RSTn	DMA1 reset control
kCMP_RST_SHIFT_RSTn	CMP reset control
kSRAM3_RST_SHIFT_RSTn	SRAM3 reset control
kFREQME_RST_SHIFT_RSTn	FREQME reset control
kCDOG_RST_SHIFT_RSTn	Code Watchdog reset control
kRNG_RST_SHIFT_RSTn	RNG reset control
kSYSCTL_RST_SHIFT_RSTn	SYSCTL reset control
kHASHCRYPT_RST_SHIFT_RSTn	HASHCRYPT reset control
kPLULUT_RST_SHIFT_RSTn	PLU LUT reset control
kCTIMER3_RST_SHIFT_RSTn	CTimer 3 reset control
kCTIMER4_RST_SHIFT_RSTn	CTimer 4 reset control
kPUF_RST_SHIFT_RSTn	PUF reset control
kCASPER_RST_SHIFT_RSTn	CASPER reset control
kANALOGCTL_RST_SHIFT_RSTn	ANALOG_CTL reset control
kHSLSPI_RST_SHIFT_RSTn	HS LSPI reset control
kGPIOSEC_RST_SHIFT_RSTn	GPIO Secure reset control
kGPIOSECINT_RST_SHIFT_RSTn	GPIO Secure int reset control

Function Documentation

void RESET_SetPeripheralReset

(

reset_ip_name_t

peripheral

)

Asserts reset signal to specified peripheral module.

Parameters

peripheral

Assert reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_ClearPeripheralReset

(

reset_ip_name_t

peripheral

)

Clears reset signal to specified peripheral module, allows it to operate.

Parameters

peripheral

Clear reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_PeripheralReset

(

reset_ip_name_t

peripheral

)

Reset peripheral module.

Parameters

peripheral

Peripheral to reset. The enum argument contains encoding of reset register and reset bit position in the reset register.