MCUXpresso SDK API Reference Manual  Rev 2.13.0
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Clock Driver

Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Files

file  fsl_clock.h
 

Data Structures

struct  clock_sys_pll_config_t
 PLL configuration for SYSPLL. More...
 
struct  clock_audio_pll_config_t
 PLL configuration for SYSPLL. More...
 
struct  clock_frg_clk_config_t
 PLL configuration for FRG. More...
 

Macros

#define CMP_CLOCKS
 Clock ip name array for ACMP. More...
 
#define FLEXCOMM_CLOCKS
 Clock ip name array for FLEXCOMM. More...
 
#define USART_CLOCKS
 Clock ip name array for LPUART. More...
 
#define I2C_CLOCKS
 Clock ip name array for I2C. More...
 
#define I3C_CLOCKS
 Clock ip name array for I3C. More...
 
#define SPI_CLOCKS
 Clock ip name array for SPI. More...
 
#define FLEXI2S_CLOCKS
 Clock ip name array for FLEXI2S. More...
 
#define UTICK_CLOCKS
 Clock ip name array for UTICK. More...
 
#define DMIC_CLOCKS
 Clock ip name array for DMIC. More...
 
#define CTIMER_CLOCKS
 Clock ip name array for CT32B. More...
 
#define GPIO_CLOCKS
 Clock ip name array for GPIO. More...
 
#define LPADC_CLOCKS
 Clock ip name array for ADC. More...
 
#define MRT_CLOCKS
 Clock ip name array for MRT. More...
 
#define SCT_CLOCKS
 Clock ip name array for SCT. More...
 
#define RTC_CLOCKS
 Clock ip name array for RTC. More...
 
#define WWDT_CLOCKS
 Clock ip name array for WWDT. More...
 
#define CRC_CLOCKS
 Clock ip name array for CRC. More...
 
#define USBD_CLOCKS
 Clock ip name array for USBD. More...
 
#define DMA_CLOCKS
 Clock ip name array for DMA. More...
 
#define PINT_CLOCKS
 Clock ip name array for PINT. More...
 
#define FLEXSPI_CLOCKS
 Clock ip name array for FLEXSPI.
 
#define CACHE64_CLOCKS
 Clock ip name array for Cache64.
 
#define MU_CLOCKS
 Clock ip name array for MUA.
 
#define SEMA42_CLOCKS
 Clock ip name array for SEMA.
 
#define TRNG_CLOCKS
 Clock ip name array for RNG.
 
#define PUF_CLOCKS
 Clock ip name array for PUF.
 
#define HASHCRYPT_CLOCKS
 Clock ip name array for HashCrypt.
 
#define CASPER_CLOCKS
 Clock ip name array for Casper.
 
#define USDHC_CLOCKS
 Clock ip name array for uSDHC.
 
#define OSTIMER_CLOCKS
 Clock ip name array for OSTimer.
 
#define POWERQUAD_CLOCKS
 Clock ip name array for Powerquad.
 
#define CLK_GATE_REG_OFFSET_SHIFT   8U
 Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
 
#define SYSPLL0CLKSEL_OFFSET   0x200
 Clock Mux Switches The encoding is as follows each connection identified is 32bits wide starting from LSB upwards. More...
 

Enumerations

enum  clock_ip_name_t {
  kCLOCK_IpInvalid = 0U,
  kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
  kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
  kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
  kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
  kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
  kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12),
  kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
  kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17),
  kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
  kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21),
  kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
  kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23),
  kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
  kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
  kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3),
  kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15),
  kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
  kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
  kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
  kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
  kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
  kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
  kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
  kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
  kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
  kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
  kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
  kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
  kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
  kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
  kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
  kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
  kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
  kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
  kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
  kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
  kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
  kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
  kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
  kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
  kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
  kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
  kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
  kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
  kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
  kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
  kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
  kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
  kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
  kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
  kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
  kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
  kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
  kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
  kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
  kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
  kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
  kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
  kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
  kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
  kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
  kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
  kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
  kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
  kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
  kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
  kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
  kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
  kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2),
  kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3),
  kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4),
  kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5),
  kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6),
  kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7),
  kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
  kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23),
  kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24),
  kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28),
  kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29),
  kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
  kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
  kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
  kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
  kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
  kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
  kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
  kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
  kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10),
  kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16),
  kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
  kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31)
}
 Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
 
enum  clock_name_t {
  kCLOCK_CoreSysClk,
  kCLOCK_BusClk,
  kCLOCK_MclkClk,
  kCLOCK_ClockOutClk,
  kCLOCK_AdcClk,
  kCLOCK_FlexspiClk,
  kCLOCK_SctClk,
  kCLOCK_Wdt0Clk,
  kCLOCK_Wdt1Clk,
  kCLOCK_SystickClk,
  kCLOCK_Sdio0Clk,
  kCLOCK_Sdio1Clk,
  kCLOCK_I3cClk,
  kCLOCK_UsbClk,
  kCLOCK_DmicClk,
  kCLOCK_DspCpuClk,
  kCLOCK_AcmpClk,
  kCLOCK_Flexcomm0Clk,
  kCLOCK_Flexcomm1Clk,
  kCLOCK_Flexcomm2Clk,
  kCLOCK_Flexcomm3Clk,
  kCLOCK_Flexcomm4Clk,
  kCLOCK_Flexcomm5Clk,
  kCLOCK_Flexcomm6Clk,
  kCLOCK_Flexcomm7Clk,
  kCLOCK_Flexcomm14Clk,
  kCLOCK_Flexcomm15Clk
}
 Clock name used to get clock frequency. More...
 
enum  clock_pfd_t {
  kCLOCK_Pfd0 = 0U,
  kCLOCK_Pfd1 = 1U,
  kCLOCK_Pfd2 = 2U,
  kCLOCK_Pfd3 = 3U
}
 PLL PFD clock name. More...
 
enum  clock_attach_id_t {
  kSFRO_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0),
  kXTALIN_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1),
  kFFRO_DIV2_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 2),
  kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7),
  kSFRO_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0),
  kXTALIN_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1),
  kFFRO_DIV2_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 2),
  kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7),
  kFFRO_DIV4_to_MAIN_CLK,
  kXTALIN_CLK_to_MAIN_CLK,
  kLPOSC_to_MAIN_CLK,
  kFFRO_to_MAIN_CLK,
  kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1),
  kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2),
  kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 3),
  kFFRO_to_DSP_MAIN_CLK,
  kXTALIN_CLK_to_DSP_MAIN_CLK,
  kLPOSC_to_DSP_MAIN_CLK,
  kSFRO_to_DSP_MAIN_CLK,
  kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1),
  kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2),
  kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3),
  kSFRO_to_ADC_CLK,
  kXTALIN_CLK_to_ADC_CLK,
  kLPOSC_to_ADC_CLK,
  kFFRO_to_ADC_CLK,
  kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1),
  kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3),
  kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 5),
  kSFRO_to_CLKOUT,
  kXTALIN_CLK_to_CLKOUT,
  kLPOSC_to_CLKOUT,
  kFFRO_to_CLKOUT,
  kMAIN_CLK_to_CLKOUT,
  kDSP_MAIN_to_CLKOUT,
  kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1),
  kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2),
  kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3),
  kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4),
  kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5),
  kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6),
  kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7),
  kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 0),
  kFFRO_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 1),
  kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 7),
  kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 0),
  kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 1),
  kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 7),
  kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 0),
  kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 1),
  kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 2),
  kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 0),
  kMAIN_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 1),
  kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 2),
  kFFRO_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 3),
  kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 4),
  kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0),
  kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1),
  kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2),
  kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3),
  kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4),
  kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5),
  kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7),
  kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0),
  kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7),
  kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0),
  kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7),
  kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0),
  kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7),
  kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 0),
  kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 1),
  kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 7),
  kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0),
  kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1),
  kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2),
  kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3),
  kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0),
  kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1),
  kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2),
  kFFRO_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3),
  kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4),
  kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0),
  kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1),
  kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2),
  kFFRO_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3),
  kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4),
  kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7),
  kXTALIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0),
  kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1),
  kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7),
  kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0),
  kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1),
  kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7),
  kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0),
  kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3),
  kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4),
  k32K_WAKE_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 5),
  kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0),
  kSFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1),
  kFFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2),
  kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3),
  kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 4),
  kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7),
  kSFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0),
  kFFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1),
  kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2),
  kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3),
  kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 4),
  kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0),
  kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1),
  kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2),
  kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3),
  kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4),
  kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 5),
  kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0),
  kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1),
  kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2),
  kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3),
  kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4),
  kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 5),
  kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0),
  kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1),
  kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2),
  kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3),
  kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4),
  kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 5),
  kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0),
  kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1),
  kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2),
  kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3),
  kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4),
  kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 5),
  kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7),
  kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0),
  kSFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1),
  kFFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2),
  kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3),
  kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4),
  kLPOSC_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 5),
  kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7)
}
 The enumerator of clock attach Id. More...
 
enum  clock_div_name_t {
  kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0),
  kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0),
  kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0),
  kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0),
  kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0),
  kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0),
  kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0),
  kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0),
  kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKDIV_OFFSET, 0),
  kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0),
  kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0),
  kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0),
  kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0),
  kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0),
  kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0),
  kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0),
  kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTDIV_OFFSET, 0),
  kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0),
  kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0),
  kCLOCK_DivDspRamClk = CLKCTL1_TUPLE_MUXA(DSPMAINRAMCLKDIV_OFFSET, 0),
  kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0),
  kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0),
  kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKDIV_OFFSET, 0),
  kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCDIV_OFFSET, 0),
  kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSDIV_OFFSET, 0)
}
 Clock dividers. More...
 
enum  clock_ffro_freq_t {
  kCLOCK_Ffro48M,
  kCLOCK_Ffro60M
}
 FFRO frequence configuration. More...
 
enum  sys_pll_src_t {
  kCLOCK_SysPllSFroClk = 0,
  kCLOCK_SysPllXtalIn = 1,
  kCLOCK_SysPllFFroDiv2 = 2,
  kCLOCK_SysPllNone = 7
}
 SysPLL Reference Input Clock Source. More...
 
enum  sys_pll_mult_t {
  kCLOCK_SysPllMult16 = 0,
  kCLOCK_SysPllMult17,
  kCLOCK_SysPllMult18,
  kCLOCK_SysPllMult19,
  kCLOCK_SysPllMult20,
  kCLOCK_SysPllMult21,
  kCLOCK_SysPllMult22
}
 SysPLL Multiplication Factor. More...
 
enum  audio_pll_src_t {
  kCLOCK_AudioPllSFroClk = 0,
  kCLOCK_AudioPllXtalIn = 1,
  kCLOCK_AudioPllFFroDiv2 = 2,
  kCLOCK_AudioPllNone = 7
}
 AudioPll Reference Input Clock Source. More...
 
enum  audio_pll_mult_t {
  kCLOCK_AudioPllMult16 = 0,
  kCLOCK_AudioPllMult17,
  kCLOCK_AudioPllMult18,
  kCLOCK_AudioPllMult19,
  kCLOCK_AudioPllMult20,
  kCLOCK_AudioPllMult21,
  kCLOCK_AudioPllMult22
}
 AudioPll Multiplication Factor. More...
 

Functions

void CLOCK_AttachClk (clock_attach_id_t connection)
 Configure the clock selection muxes. More...
 
void CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divider)
 Setup peripheral clock dividers. More...
 
uint32_t CLOCK_GetFreq (clock_name_t clockName)
 Return Frequency of selected clock. More...
 
uint32_t CLOCK_GetFRGClock (uint32_t id)
 Return Input frequency for the Fractional baud rate generator. More...
 
void CLOCK_SetFRGClock (const clock_frg_clk_config_t *config)
 Set output of the Fractional baud rate generator. More...
 
static uint32_t CLOCK_GetSFroFreq (void)
 Return Frequency of FRO 16MHz. More...
 
uint32_t CLOCK_GetSysPllFreq (void)
 Return Frequency of SYSPLL. More...
 
uint32_t CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
 Get current output frequency of specific System PLL PFD. More...
 
uint32_t CLOCK_GetAudioPllFreq (void)
 Return Frequency of AUDIO PLL. More...
 
uint32_t CLOCK_GetAudioPfdFreq (clock_pfd_t pfd)
 Get current output frequency of specific Audio PLL PFD. More...
 
uint32_t CLOCK_GetFFroFreq (void)
 Return Frequency of High-Freq output of FRO. More...
 
uint32_t CLOCK_GetMainClkFreq (void)
 Return Frequency of main clk. More...
 
uint32_t CLOCK_GetDspMainClkFreq (void)
 Return Frequency of DSP main clk. More...
 
uint32_t CLOCK_GetAcmpClkFreq (void)
 Return Frequency of ACMP clk. More...
 
uint32_t CLOCK_GetDmicClkFreq (void)
 Return Frequency of DMIC clk. More...
 
uint32_t CLOCK_GetUsbClkFreq (void)
 Return Frequency of USB clk. More...
 
uint32_t CLOCK_GetSdioClkFreq (uint32_t id)
 Return Frequency of SDIO clk. More...
 
uint32_t CLOCK_GetI3cClkFreq (void)
 Return Frequency of I3C clk. More...
 
uint32_t CLOCK_GetSystickClkFreq (void)
 Return Frequency of systick clk. More...
 
uint32_t CLOCK_GetWdtClkFreq (uint32_t id)
 Return Frequency of WDT clk. More...
 
uint32_t CLOCK_GetMclkClkFreq (void)
 Return Frequency of mclk. More...
 
uint32_t CLOCK_GetSctClkFreq (void)
 Return Frequency of sct. More...
 
void CLOCK_EnableSysOscClk (bool enable, bool enableLowPower, uint32_t delay_us)
 Enable/Disable sys osc clock from external crystal clock. More...
 
static uint32_t CLOCK_GetXtalInClkFreq (void)
 Return Frequency of sys osc Clock. More...
 
static uint32_t CLOCK_GetMclkInClkFreq (void)
 Return Frequency of MCLK Input Clock. More...
 
static uint32_t CLOCK_GetLpOscFreq (void)
 Return Frequency of Lower power osc. More...
 
static uint32_t CLOCK_GetOsc32KFreq (void)
 Return Frequency of 32kHz osc. More...
 
static void CLOCK_EnableOsc32K (bool enable)
 Enables and disables 32kHz osc. More...
 
static uint32_t CLOCK_GetWakeClk32KFreq (void)
 Return Frequency of 32khz wake clk. More...
 
static void CLOCK_SetXtalFreq (uint32_t freq)
 Set the XTALIN (system OSC) frequency based on board setting. More...
 
static void CLOCK_SetClkinFreq (uint32_t freq)
 Set the CLKIN (CLKIN pin) frequency based on board setting. More...
 
static void CLOCK_SetMclkFreq (uint32_t freq)
 Set the MCLK in (mclk_in) clock frequency based on board setting. More...
 
uint32_t CLOCK_GetFlexCommClkFreq (uint32_t id)
 Return Frequency of Flexcomm functional Clock. More...
 
uint32_t CLOCK_GetCtimerClkFreq (uint32_t id)
 Return Frequency of Ctimer Clock. More...
 
uint32_t CLOCK_GetClockOutClkFreq (void)
 Return Frequency of ClockOut. More...
 
uint32_t CLOCK_GetAdcClkFreq (void)
 Return Frequency of Adc Clock. More...
 
uint32_t CLOCK_GetFlexspiClkFreq (void)
 Return Frequency of Flexspi Clock. More...
 
void CLOCK_EnableFfroClk (clock_ffro_freq_t ffroFreq)
 
void CLOCK_EnableSfroClk (void)
 
void CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
 Initialize the System PLL. More...
 
static void CLOCK_DeinitSysPll (void)
 brief Deinit the System PLL. More...
 
void CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t divider)
 Initialize the System PLL PFD. More...
 
static void CLOCK_DeinitSysPfd (clock_pfd_t pfd)
 brief Disable the audio PLL PFD. More...
 
void CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
 Initialize the audio PLL. More...
 
static void CLOCK_DeinitAudioPll (void)
 brief Deinit the Audio PLL. More...
 
void CLOCK_InitAudioPfd (clock_pfd_t pfd, uint8_t divider)
 Initialize the audio PLL PFD. More...
 
static void CLOCK_DeinitAudioPfd (uint32_t pfd)
 brief Disable the audio PLL PFD. More...
 
void CLOCK_EnableUsbhsDeviceClock (void)
 Enable USB HS device PLL clock. More...
 
void CLOCK_EnableUsbhsHostClock (void)
 Enable USB HS host PLL clock. More...
 
bool CLOCK_EnableUsbHs0PhyPllClock (clock_attach_id_t src, uint32_t freq)
 brief Enable USB hs0PhyPll clock. More...
 

Variables

volatile uint32_t g_xtalFreq
 External XTAL (SYSOSC) clock frequency. More...
 
volatile uint32_t g_clkinFreq
 External CLK_IN pin clock frequency (clkin) clock frequency. More...
 
volatile uint32_t g_mclkFreq
 External XTAL (SYSOSC) clock frequency. More...
 

Driver version

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 7, 2))
 CLOCK driver version 2.7.2. More...
 

Data Structure Documentation

struct clock_sys_pll_config_t

Data Fields

sys_pll_src_t sys_pll_src
 Reference Input Clock Source.
 
uint32_t numerator
 30 bit numerator of fractional loop divider. More...
 
uint32_t denominator
 30 bit numerator of fractional loop divider. More...
 
sys_pll_mult_t sys_pll_mult
 Multiplication Factor.
 

Field Documentation

uint32_t clock_sys_pll_config_t::numerator
uint32_t clock_sys_pll_config_t::denominator
struct clock_audio_pll_config_t

Data Fields

audio_pll_src_t audio_pll_src
 Reference Input Clock Source.
 
uint32_t numerator
 30 bit numerator of fractional loop divider. More...
 
uint32_t denominator
 30 bit numerator of fractional loop divider. More...
 
audio_pll_mult_t audio_pll_mult
 Multiplication Factor.
 

Field Documentation

uint32_t clock_audio_pll_config_t::numerator
uint32_t clock_audio_pll_config_t::denominator
struct clock_frg_clk_config_t

Public Types

enum  {
  kCLOCK_FrgMainClk = 0,
  kCLOCK_FrgPllDiv,
  kCLOCK_FrgSFro,
  kCLOCK_FrgFFro
}
 

Data Fields

uint8_t num
 FRG clock.
 
uint8_t divider
 Denominator of the fractional divider. More...
 
uint8_t mult
 Numerator of the fractional divider. More...
 

Member Enumeration Documentation

anonymous enum
Enumerator
kCLOCK_FrgMainClk 

Main System clock.

kCLOCK_FrgPllDiv 

Main pll clock divider.

kCLOCK_FrgSFro 

16MHz FRO

kCLOCK_FrgFFro 

FRO48/60.

Field Documentation

uint8_t clock_frg_clk_config_t::divider
uint8_t clock_frg_clk_config_t::mult

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 7, 2))
#define CMP_CLOCKS
Value:
{ \
}
Clock gate name: Acmp0.
Definition: fsl_clock.h:285
#define FLEXCOMM_CLOCKS
Value:
{ \
}
Clock gate name: Flexcomm7.
Definition: fsl_clock.h:299
Clock gate name: Flexcomm1.
Definition: fsl_clock.h:293
Clock gate name: Flexcomm0.
Definition: fsl_clock.h:292
Clock gate name: Flexcomm2.
Definition: fsl_clock.h:294
Clock gate name: Flexcomm5.
Definition: fsl_clock.h:297
Clock gate name: Flexcomm3.
Definition: fsl_clock.h:295
Clock gate name: Flexcomm4.
Definition: fsl_clock.h:296
Clock gate name: Flexcomm14.
Definition: fsl_clock.h:300
Clock gate name: Flexcomm6.
Definition: fsl_clock.h:298
Clock gate name: Flexcomm15.
Definition: fsl_clock.h:301
#define USART_CLOCKS
Value:
{ \
}
Clock gate name: Usart2.
Definition: fsl_clock.h:304
Clock gate name: Usart0.
Definition: fsl_clock.h:302
Clock gate name: Usart1.
Definition: fsl_clock.h:303
Clock gate name: Usart6.
Definition: fsl_clock.h:308
Clock gate name: Usart5.
Definition: fsl_clock.h:307
Clock gate name: Usart3.
Definition: fsl_clock.h:305
Clock gate name: Usart7.
Definition: fsl_clock.h:309
Clock gate name: Usart4.
Definition: fsl_clock.h:306
#define I2C_CLOCKS
Value:
{ \
}
Clock gate name: I2c0.
Definition: fsl_clock.h:318
Clock gate name: I2c3.
Definition: fsl_clock.h:321
Clock gate name: I2c1.
Definition: fsl_clock.h:319
Clock gate name: I2c5.
Definition: fsl_clock.h:323
Clock gate name: I2c4.
Definition: fsl_clock.h:322
Clock gate name: I2c7.
Definition: fsl_clock.h:325
Clock gate name: I2c6.
Definition: fsl_clock.h:324
Clock gate name: I2c2.
Definition: fsl_clock.h:320
Clock gate name: I2c15.
Definition: fsl_clock.h:326
#define I3C_CLOCKS
Value:
{ \
}
Clock gate name: I3c0.
Definition: fsl_clock.h:362
#define SPI_CLOCKS
Value:
{ \
}
Clock gate name: Spi5.
Definition: fsl_clock.h:332
Clock gate name: Spi2.
Definition: fsl_clock.h:329
Clock gate name: Spi4.
Definition: fsl_clock.h:331
Clock gate name: Spi14.
Definition: fsl_clock.h:335
Clock gate name: Spi0.
Definition: fsl_clock.h:327
Clock gate name: Spi6.
Definition: fsl_clock.h:333
Clock gate name: Spi3.
Definition: fsl_clock.h:330
Clock gate name: Spi1.
Definition: fsl_clock.h:328
Clock gate name: Spi7.
Definition: fsl_clock.h:334
#define FLEXI2S_CLOCKS
Value:
{ \
kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
}
#define UTICK_CLOCKS
Value:
{ \
}
Clock gate name: Utick0.
Definition: fsl_clock.h:289
#define DMIC_CLOCKS
Value:
{ \
}
Clock gate name: Dmic0.
Definition: fsl_clock.h:336
#define CTIMER_CLOCKS
Value:
{ \
}
Clock gate name: Ct32b0.
Definition: fsl_clock.h:354
Clock gate name: Ct32b4.
Definition: fsl_clock.h:358
Clock gate name: Ct32b1.
Definition: fsl_clock.h:355
Clock gate name: Ct32b2.
Definition: fsl_clock.h:356
Clock gate name: Ct32b3.
Definition: fsl_clock.h:357
#define GPIO_CLOCKS
Value:
{ \
}
Clock gate name: HsGpio2.
Definition: fsl_clock.h:341
Clock gate name: HsGpio6.
Definition: fsl_clock.h:345
Clock gate name: HsGpio5.
Definition: fsl_clock.h:344
Clock gate name: HsGpio4.
Definition: fsl_clock.h:343
Clock gate name: HsGpio7.
Definition: fsl_clock.h:346
Clock gate name: HsGpio0.
Definition: fsl_clock.h:339
Clock gate name: HsGpio1.
Definition: fsl_clock.h:340
Clock gate name: HsGpio3.
Definition: fsl_clock.h:342
#define LPADC_CLOCKS
Value:
{ \
}
Clock gate name: Adc0.
Definition: fsl_clock.h:286
#define MRT_CLOCKS
Value:
{ \
}
Clock gate name: Mrt0.
Definition: fsl_clock.h:360
#define SCT_CLOCKS
Value:
{ \
}
Clock gate name: Sct.
Definition: fsl_clock.h:281
#define RTC_CLOCKS
Value:
{ \
}
Clock gate name: Rtc.
Definition: fsl_clock.h:359
#define WWDT_CLOCKS
Value:
{ \
}
Clock gate name: Wwdt0.
Definition: fsl_clock.h:290
Clock gate name: Wwdt1.
Definition: fsl_clock.h:361
#define CRC_CLOCKS
Value:
{ \
}
Clock gate name: Crc.
Definition: fsl_clock.h:347
#define USBD_CLOCKS
Value:
{ \
}
Clock gate name: UsbhsDevice.
Definition: fsl_clock.h:278
#define DMA_CLOCKS
Value:
{ \
}
Clock gate name: Dmac0.
Definition: fsl_clock.h:348
Clock gate name: Dmac1.
Definition: fsl_clock.h:349
#define PINT_CLOCKS
Value:
{ \
}
Clock gate name: Pint.
Definition: fsl_clock.h:363
#define CLK_GATE_REG_OFFSET_SHIFT   8U
#define SYSPLL0CLKSEL_OFFSET   0x200

[12 bits for reg offset, 0 means end of descriptor, 4 bits for choice] [bit 31 define CLKCTL0 or CLKCTL1]*

Enumeration Type Documentation

Enumerator
kCLOCK_IpInvalid 

Invalid Ip Name.

kCLOCK_RomCtrlr 

Clock gate name: RomCtrlr.

kCLOCK_PowerQuad 

Clock gate name: PowerQuad.

kCLOCK_Casper 

Clock gate name: Casper.

kCLOCK_HashCrypt 

Clock gate name: HashCrypt.

kCLOCK_Puf 

Clock gate name: Puf.

kCLOCK_Rng 

Clock gate name: Rng.

kCLOCK_Flexspi 

Clock gate name: Flexspi.

kCLOCK_OtpCtrl 

Clock gate name: OtpCtrl.

kCLOCK_UsbhsPhy 

Clock gate name: UsbhsPhy.

kCLOCK_UsbhsDevice 

Clock gate name: UsbhsDevice.

kCLOCK_UsbhsHost 

Clock gate name: UsbhsHost.

kCLOCK_UsbhsSram 

Clock gate name: UsbhsSram.

kCLOCK_Sct 

Clock gate name: Sct.

kCLOCK_Sdio0 

Clock gate name: Sdio0.

kCLOCK_Sdio1 

Clock gate name: Sdio1.

kCLOCK_Acmp0 

Clock gate name: Acmp0.

kCLOCK_Adc0 

Clock gate name: Adc0.

kCLOCK_ShsGpio0 

Clock gate name: ShsGpio0.

kCLOCK_Utick0 

Clock gate name: Utick0.

kCLOCK_Wwdt0 

Clock gate name: Wwdt0.

kCLOCK_Flexcomm0 

Clock gate name: Flexcomm0.

kCLOCK_Flexcomm1 

Clock gate name: Flexcomm1.

kCLOCK_Flexcomm2 

Clock gate name: Flexcomm2.

kCLOCK_Flexcomm3 

Clock gate name: Flexcomm3.

kCLOCK_Flexcomm4 

Clock gate name: Flexcomm4.

kCLOCK_Flexcomm5 

Clock gate name: Flexcomm5.

kCLOCK_Flexcomm6 

Clock gate name: Flexcomm6.

kCLOCK_Flexcomm7 

Clock gate name: Flexcomm7.

kCLOCK_Flexcomm14 

Clock gate name: Flexcomm14.

kCLOCK_Flexcomm15 

Clock gate name: Flexcomm15.

kCLOCK_Usart0 

Clock gate name: Usart0.

kCLOCK_Usart1 

Clock gate name: Usart1.

kCLOCK_Usart2 

Clock gate name: Usart2.

kCLOCK_Usart3 

Clock gate name: Usart3.

kCLOCK_Usart4 

Clock gate name: Usart4.

kCLOCK_Usart5 

Clock gate name: Usart5.

kCLOCK_Usart6 

Clock gate name: Usart6.

kCLOCK_Usart7 

Clock gate name: Usart7.

kCLOCK_I2s0 

Clock gate name: I2s0.

kCLOCK_I2s1 

Clock gate name: I2s1.

kCLOCK_I2s2 

Clock gate name: I2s2.

kCLOCK_I2s3 

Clock gate name: I2s3.

kCLOCK_I2s4 

Clock gate name: I2s4.

kCLOCK_I2s5 

Clock gate name: I2s5.

kCLOCK_I2s6 

Clock gate name: I2s6.

kCLOCK_I2s7 

Clock gate name: I2s7.

kCLOCK_I2c0 

Clock gate name: I2c0.

kCLOCK_I2c1 

Clock gate name: I2c1.

kCLOCK_I2c2 

Clock gate name: I2c2.

kCLOCK_I2c3 

Clock gate name: I2c3.

kCLOCK_I2c4 

Clock gate name: I2c4.

kCLOCK_I2c5 

Clock gate name: I2c5.

kCLOCK_I2c6 

Clock gate name: I2c6.

kCLOCK_I2c7 

Clock gate name: I2c7.

kCLOCK_I2c15 

Clock gate name: I2c15.

kCLOCK_Spi0 

Clock gate name: Spi0.

kCLOCK_Spi1 

Clock gate name: Spi1.

kCLOCK_Spi2 

Clock gate name: Spi2.

kCLOCK_Spi3 

Clock gate name: Spi3.

kCLOCK_Spi4 

Clock gate name: Spi4.

kCLOCK_Spi5 

Clock gate name: Spi5.

kCLOCK_Spi6 

Clock gate name: Spi6.

kCLOCK_Spi7 

Clock gate name: Spi7.

kCLOCK_Spi14 

Clock gate name: Spi14.

kCLOCK_Dmic0 

Clock gate name: Dmic0.

kCLOCK_OsEventTimer 

Clock gate name: OsEventTimer.

kCLOCK_HsGpio0 

Clock gate name: HsGpio0.

kCLOCK_HsGpio1 

Clock gate name: HsGpio1.

kCLOCK_HsGpio2 

Clock gate name: HsGpio2.

kCLOCK_HsGpio3 

Clock gate name: HsGpio3.

kCLOCK_HsGpio4 

Clock gate name: HsGpio4.

kCLOCK_HsGpio5 

Clock gate name: HsGpio5.

kCLOCK_HsGpio6 

Clock gate name: HsGpio6.

kCLOCK_HsGpio7 

Clock gate name: HsGpio7.

kCLOCK_Crc 

Clock gate name: Crc.

kCLOCK_Dmac0 

Clock gate name: Dmac0.

kCLOCK_Dmac1 

Clock gate name: Dmac1.

kCLOCK_Mu 

Clock gate name: Mu.

kCLOCK_Sema 

Clock gate name: Sema.

kCLOCK_Freqme 

Clock gate name: Freqme.

kCLOCK_Ct32b0 

Clock gate name: Ct32b0.

kCLOCK_Ct32b1 

Clock gate name: Ct32b1.

kCLOCK_Ct32b2 

Clock gate name: Ct32b2.

kCLOCK_Ct32b3 

Clock gate name: Ct32b3.

kCLOCK_Ct32b4 

Clock gate name: Ct32b4.

kCLOCK_Rtc 

Clock gate name: Rtc.

kCLOCK_Mrt0 

Clock gate name: Mrt0.

kCLOCK_Wwdt1 

Clock gate name: Wwdt1.

kCLOCK_I3c0 

Clock gate name: I3c0.

kCLOCK_Pint 

Clock gate name: Pint.

kCLOCK_InputMux 

Clock gate name: Input Mux.

Enumerator
kCLOCK_CoreSysClk 

Core clock (aka HCLK)

kCLOCK_BusClk 

Bus clock (AHB/APB clock, aka HCLK)

kCLOCK_MclkClk 

MCLK, to MCLK pin.

kCLOCK_ClockOutClk 

CLOCKOUT.

kCLOCK_AdcClk 

ADC.

kCLOCK_FlexspiClk 

FLEXSPI.

kCLOCK_SctClk 

SCT.

kCLOCK_Wdt0Clk 

Watchdog0.

kCLOCK_Wdt1Clk 

Watchdog1.

kCLOCK_SystickClk 

Systick.

kCLOCK_Sdio0Clk 

SDIO0.

kCLOCK_Sdio1Clk 

SDIO1.

kCLOCK_I3cClk 

I3C.

kCLOCK_UsbClk 

USB.

kCLOCK_DmicClk 

Digital Mic clock.

kCLOCK_DspCpuClk 

DSP clock.

kCLOCK_AcmpClk 

Acmp clock.

kCLOCK_Flexcomm0Clk 

Flexcomm0Clock.

kCLOCK_Flexcomm1Clk 

Flexcomm1Clock.

kCLOCK_Flexcomm2Clk 

Flexcomm2Clock.

kCLOCK_Flexcomm3Clk 

Flexcomm3Clock.

kCLOCK_Flexcomm4Clk 

Flexcomm4Clock.

kCLOCK_Flexcomm5Clk 

Flexcomm5Clock.

kCLOCK_Flexcomm6Clk 

Flexcomm6Clock.

kCLOCK_Flexcomm7Clk 

Flexcomm7Clock.

kCLOCK_Flexcomm14Clk 

Flexcomm14Clock.

kCLOCK_Flexcomm15Clk 

Flexcomm15Clock.

Enumerator
kCLOCK_Pfd0 

PLL PFD0.

kCLOCK_Pfd1 

PLL PFD1.

kCLOCK_Pfd2 

PLL PFD2.

kCLOCK_Pfd3 

PLL PFD3.

Enumerator
kSFRO_to_SYS_PLL 

Attach SFRO to SYS_PLL.

kXTALIN_CLK_to_SYS_PLL 

Attach XTALIN_CLK to SYS_PLL.

kFFRO_DIV2_to_SYS_PLL 

Attach FFRO_DIV2 to SYS_PLL.

kNONE_to_SYS_PLL 

Attach NONE to SYS_PLL.

kSFRO_to_AUDIO_PLL 

Attach SFRO to AUDIO_PLL.

kXTALIN_CLK_to_AUDIO_PLL 

Attach XTALIN_CLK to AUDIO_PLL.

kFFRO_DIV2_to_AUDIO_PLL 

Attach FFRO_DIV2 to AUDIO_PLL.

kNONE_to_AUDIO_PLL 

Attach NONE to AUDIO_PLL.

kFFRO_DIV4_to_MAIN_CLK 

Attach FFRO_DIV4 to MAIN_CLK.

kXTALIN_CLK_to_MAIN_CLK 

Attach XTALIN_CLK to MAIN_CLK.

kLPOSC_to_MAIN_CLK 

Attach LPOSC to MAIN_CLK.

kFFRO_to_MAIN_CLK 

Attach FFRO to MAIN_CLK.

kSFRO_to_MAIN_CLK 

Attach SFRO to MAIN_CLK.

kMAIN_PLL_to_MAIN_CLK 

Attach MAIN_PLL to MAIN_CLK.

kOSC32K_to_MAIN_CLK 

Attach OSC32K to MAIN_CLK.

kFFRO_to_DSP_MAIN_CLK 

Attach FFRO to DSP_MAIN_CLK.

kXTALIN_CLK_to_DSP_MAIN_CLK 

Attach XTALIN_CLK to DSP_MAIN_CLK.

kLPOSC_to_DSP_MAIN_CLK 

Attach LPOSC to DSP_MAIN_CLK.

kSFRO_to_DSP_MAIN_CLK 

Attach SFRO to DSP_MAIN_CLK.

kMAIN_PLL_to_DSP_MAIN_CLK 

Attach MAIN_PLL to DSP_MAIN_CLK.

kDSP_PLL_to_DSP_MAIN_CLK 

Attach DSP_PLL to DSP_MAIN_CLK.

kOSC32K_to_DSP_MAIN_CLK 

Attach OSC32K to DSP_MAIN_CLK.

kSFRO_to_ADC_CLK 

Attach SFRO to ADC_CLK.

kXTALIN_CLK_to_ADC_CLK 

Attach XTALIN_CLK to ADC_CLK.

kLPOSC_to_ADC_CLK 

Attach LPOSC to ADC_CLK.

kFFRO_to_ADC_CLK 

Attach FFRO to ADC_CLK.

kMAIN_PLL_to_ADC_CLK 

Attach MAIN_PLL to ADC_CLK.

kAUX0_PLL_to_ADC_CLK 

Attach AUX0_PLL to ADC_CLK.

kAUX1_PLL_to_ADC_CLK 

Attach AUX1_PLL to ADC_CLK.

kSFRO_to_CLKOUT 

Attach SFRO to CLKOUT.

kXTALIN_CLK_to_CLKOUT 

Attach XTALIN_CLK to CLKOUT.

kLPOSC_to_CLKOUT 

Attach LPOSC to CLKOUT.

kFFRO_to_CLKOUT 

Attach FFRO to CLKOUT.

kMAIN_CLK_to_CLKOUT 

Attach MAIN_CLK to CLKOUT.

kDSP_MAIN_to_CLKOUT 

Attach DSP_MAIN to CLKOUT.

kMAIN_PLL_to_CLKOUT 

Attach MAIN_PLL to CLKOUT.

kAUX0_PLL_to_CLKOUT 

Attach AUX0_PLL to CLKOUT.

kDSP_PLL_to_CLKOUT 

Attach DSP_PLL to CLKOUT.

kAUX1_PLL_to_CLKOUT 

Attach AUX1_PLL to CLKOUT.

kAUDIO_PLL_to_CLKOUT 

Attach AUDIO_PLL to CLKOUT.

kOSC32K_to_CLKOUT 

Attach OSC32K to CLKOUT.

kNONE_to_CLKOUT 

Attach NONE to CLKOUT.

kMAIN_CLK_to_I3C_CLK 

Attach MAIN_CLK to I3C_CLK.

kFFRO_to_I3C_CLK 

Attach FFRO to I3C_CLK.

kNONE_to_I3C_CLK 

Attach NONE to I3C_CLK.

kI3C_CLK_to_I3C_TC_CLK 

Attach I3C_CLK to I3C_TC_CLK.

kLPOSC_to_I3C_TC_CLK 

Attach LPOSC to I3C_TC_CLK.

kNONE_to_I3C_TC_CLK 

Attach NONE to I3C_TC_CLK.

kLPOSC_to_OSTIMER_CLK 

Attach LPOSC to OSTIMER_CLK.

kOSC32K_to_OSTIMER_CLK 

Attach OSC32K to OSTIMER_CLK.

kHCLK_to_OSTIMER_CLK 

Attach HCLK to OSTIMER_CLK.

kNONE_to_OSTIMER_CLK 

Attach NONE to OSTIMER_CLK.

kMAIN_CLK_to_FLEXSPI_CLK 

Attach MAIN_CLK to FLEXSPI_CLK.

kMAIN_PLL_to_FLEXSPI_CLK 

Attach MAIN_PLL to FLEXSPI_CLK.

kAUX0_PLL_to_FLEXSPI_CLK 

Attach AUX0_PLL to FLEXSPI_CLK.

kFFRO_to_FLEXSPI_CLK 

Attach FFRO to FLEXSPI_CLK.

kAUX1_PLL_to_FLEXSPI_CLK 

Attach AUX1_PLL to FLEXSPI_CLK.

kNONE_to_FLEXSPI_CLK 

Attach NONE to FLEXSPI_CLK.

kMAIN_CLK_to_SCT_CLK 

Attach MAIN_CLK to SCT_CLK.

kMAIN_PLL_to_SCT_CLK 

Attach MAIN_PLL to SCT_CLK.

kAUX0_PLL_to_SCT_CLK 

Attach AUX0_PLL to SCT_CLK.

kFFRO_to_SCT_CLK 

Attach FFRO to SCT_CLK.

kAUX1_PLL_to_SCT_CLK 

Attach AUX1_PLL to SCT_CLK.

kAUDIO_PLL_to_SCT_CLK 

Attach AUDIO_PLL to SCT_CLK.

kNONE_to_SCT_CLK 

Attach NONE to SCT_CLK.

kLPOSC_to_UTICK_CLK 

Attach LPOSC to UTICK_CLK.

kNONE_to_UTICK_CLK 

Attach NONE to UTICK_CLK.

kLPOSC_to_WDT0_CLK 

Attach LPOSC to WDT0_CLK.

kNONE_to_WDT0_CLK 

Attach NONE to WDT0_CLK.

kLPOSC_to_WDT1_CLK 

Attach LPOSC to WDT1_CLK.

kNONE_to_WDT1_CLK 

Attach NONE to WDT1_CLK.

kOSC32K_to_32KHZWAKE_CLK 

Attach OSC32K to 32KHZWAKE_CLK.

kLPOSC_DIV32_to_32KHZWAKE_CLK 

Attach LPOSC_DIV32 to 32KHZWAKE_CLK.

kNONE_to_32KHZWAKE_CLK 

Attach NONE to 32KHZWAKE_CLK.

kMAIN_CLK_DIV_to_SYSTICK_CLK 

Attach MAIN_CLK_DIV to SYSTICK_CLK.

kLPOSC_to_SYSTICK_CLK 

Attach LPOSC to SYSTICK_CLK.

kOSC32K_to_SYSTICK_CLK 

Attach OSC32K to SYSTICK_CLK.

kSFRO_to_SYSTICK_CLK 

Attach SFRO to SYSTICK_CLK.

kNONE_to_SYSTICK_CLK 

Attach NONE to SYSTICK_CLK.

kMAIN_CLK_to_SDIO0_CLK 

Attach MAIN_CLK to SDIO0_CLK.

kMAIN_PLL_to_SDIO0_CLK 

Attach MAIN_PLL to SDIO0_CLK.

kAUX0_PLL_to_SDIO0_CLK 

Attach AUX0_PLL to SDIO0_CLK.

kFFRO_to_SDIO0_CLK 

Attach FFRO to SDIO0_CLK.

kAUX1_PLL_to_SDIO0_CLK 

Attach AUX1_PLL to SDIO0_CLK.

kNONE_to_SDIO0_CLK 

Attach NONE to SDIO0_CLK.

kMAIN_CLK_to_SDIO1_CLK 

Attach MAIN_CLK to SDIO1_CLK.

kMAIN_PLL_to_SDIO1_CLK 

Attach MAIN_PLL to SDIO1_CLK.

kAUX0_PLL_to_SDIO1_CLK 

Attach AUX0_PLL to SDIO1_CLK.

kFFRO_to_SDIO1_CLK 

Attach FFRO to SDIO1_CLK.

kAUX1_PLL_to_SDIO1_CLK 

Attach AUX1_PLL to SDIO1_CLK.

kNONE_to_SDIO1_CLK 

Attach NONE to SDIO1_CLK.

kXTALIN_CLK_to_USB_CLK 

Attach XTALIN_CLK to USB_CLK.

kMAIN_CLK_to_USB_CLK 

Attach MAIN_CLK to USB_CLK.

kNONE_to_USB_CLK 

Attach NONE to USB_CLK.

kFFRO_to_MCLK_CLK 

Attach FFRO to MCLK_CLK.

kAUDIO_PLL_to_MCLK_CLK 

Attach AUDIO_PLL to MCLK_CLK.

kNONE_to_MCLK_CLK 

Attach NONE to MCLK_CLK.

kSFRO_to_DMIC_CLK 

Attach SFRO to DMIC_CLK.

kFFRO_to_DMIC_CLK 

Attach FFRO to DMIC_CLK.

kAUDIO_PLL_to_DMIC_CLK 

Attach AUDIO_PLL to DMIC_CLK.

kMASTER_CLK_to_DMIC_CLK 

Attach MASTER_CLK to DMIC_CLK.

kLPOSC_to_DMIC_CLK 

Attach LPOSC to DMIC_CLK.

k32K_WAKE_CLK_to_DMIC_CLK 

Attach 32K_WAKE_CLK to DMIC_CLK.

kNONE_to_DMIC_CLK 

Attach NONE to DMIC_CLK.

kMAIN_CLK_to_ACMP_CLK 

Attach MAIN_CLK to ACMP_CLK.

kSFRO_to_ACMP_CLK 

Attach SFRO to ACMP_CLK.

kFFRO_to_ACMP_CLK 

Attach FFRO to ACMP_CLK.

kAUX0_PLL_to_ACMP_CLK 

Attach AUX0_PLL to ACMP_CLK.

kAUX1_PLL_to_ACMP_CLK 

Attach AUX1_PLL to ACMP_CLK.

kNONE_to_ACMP_CLK 

Attach NONE to ACMP_CLK.

kSFRO_to_FLEXCOMM0 

Attach SFRO to FLEXCOMM0.

kFFRO_to_FLEXCOMM0 

Attach FFRO to FLEXCOMM0.

kAUDIO_PLL_to_FLEXCOMM0 

Attach AUDIO_PLL to FLEXCOMM0.

kMASTER_CLK_to_FLEXCOMM0 

Attach MASTER_CLK to FLEXCOMM0.

kFRG_to_FLEXCOMM0 

Attach FRG to FLEXCOMM0.

kNONE_to_FLEXCOMM0 

Attach NONE to FLEXCOMM0.

kSFRO_to_FLEXCOMM1 

Attach SFRO to FLEXCOMM1.

kFFRO_to_FLEXCOMM1 

Attach FFRO to FLEXCOMM1.

kAUDIO_PLL_to_FLEXCOMM1 

Attach AUDIO_PLL to FLEXCOMM1.

kMASTER_CLK_to_FLEXCOMM1 

Attach MASTER_CLK to FLEXCOMM1.

kFRG_to_FLEXCOMM1 

Attach FRG to FLEXCOMM1.

kNONE_to_FLEXCOMM1 

Attach NONE to FLEXCOMM1.

kSFRO_to_FLEXCOMM2 

Attach SFRO to FLEXCOMM2.

kFFRO_to_FLEXCOMM2 

Attach FFRO to FLEXCOMM2.

kAUDIO_PLL_to_FLEXCOMM2 

Attach AUDIO_PLL to FLEXCOMM2.

kMASTER_CLK_to_FLEXCOMM2 

Attach MASTER_CLK to FLEXCOMM2.

kFRG_to_FLEXCOMM2 

Attach FRG to FLEXCOMM2.

kNONE_to_FLEXCOMM2 

Attach NONE to FLEXCOMM2.

kSFRO_to_FLEXCOMM3 

Attach SFRO to FLEXCOMM3.

kFFRO_to_FLEXCOMM3 

Attach FFRO to FLEXCOMM3.

kAUDIO_PLL_to_FLEXCOMM3 

Attach AUDIO_PLL to FLEXCOMM3.

kMASTER_CLK_to_FLEXCOMM3 

Attach MASTER_CLK to FLEXCOMM3.

kFRG_to_FLEXCOMM3 

Attach FRG to FLEXCOMM3.

kNONE_to_FLEXCOMM3 

Attach NONE to FLEXCOMM3.

kSFRO_to_FLEXCOMM4 

Attach SFRO to FLEXCOMM4.

kFFRO_to_FLEXCOMM4 

Attach FFRO to FLEXCOMM4.

kAUDIO_PLL_to_FLEXCOMM4 

Attach AUDIO_PLL to FLEXCOMM4.

kMASTER_CLK_to_FLEXCOMM4 

Attach MASTER_CLK to FLEXCOMM4.

kFRG_to_FLEXCOMM4 

Attach FRG to FLEXCOMM4.

kNONE_to_FLEXCOMM4 

Attach NONE to FLEXCOMM4.

kSFRO_to_FLEXCOMM5 

Attach SFRO to FLEXCOMM5.

kFFRO_to_FLEXCOMM5 

Attach FFRO to FLEXCOMM5.

kAUDIO_PLL_to_FLEXCOMM5 

Attach AUDIO_PLL to FLEXCOMM5.

kMASTER_CLK_to_FLEXCOMM5 

Attach MASTER_CLK to FLEXCOMM5.

kFRG_to_FLEXCOMM5 

Attach FRG to FLEXCOMM5.

kNONE_to_FLEXCOMM5 

Attach NONE to FLEXCOMM5.

kSFRO_to_FLEXCOMM6 

Attach SFRO to FLEXCOMM6.

kFFRO_to_FLEXCOMM6 

Attach FFRO to FLEXCOMM6.

kAUDIO_PLL_to_FLEXCOMM6 

Attach AUDIO_PLL to FLEXCOMM6.

kMASTER_CLK_to_FLEXCOMM6 

Attach MASTER_CLK to FLEXCOMM6.

kFRG_to_FLEXCOMM6 

Attach FRG to FLEXCOMM6.

kNONE_to_FLEXCOMM6 

Attach NONE to FLEXCOMM6.

kSFRO_to_FLEXCOMM7 

Attach SFRO to FLEXCOMM7.

kFFRO_to_FLEXCOMM7 

Attach FFRO to FLEXCOMM7.

kAUDIO_PLL_to_FLEXCOMM7 

Attach AUDIO_PLL to FLEXCOMM7.

kMASTER_CLK_to_FLEXCOMM7 

Attach MASTER_CLK to FLEXCOMM7.

kFRG_to_FLEXCOMM7 

Attach FRG to FLEXCOMM7.

kNONE_to_FLEXCOMM7 

Attach NONE to FLEXCOMM7.

kSFRO_to_FLEXCOMM14 

Attach SFRO to FLEXCOMM14.

kFFRO_to_FLEXCOMM14 

Attach FFRO to FLEXCOMM14.

kAUDIO_PLL_to_FLEXCOMM14 

Attach AUDIO_PLL to FLEXCOMM14.

kMASTER_CLK_to_FLEXCOMM14 

Attach MASTER_CLK to FLEXCOMM14.

kFRG_to_FLEXCOMM14 

Attach FRG to FLEXCOMM14.

kNONE_to_FLEXCOMM14 

Attach NONE to FLEXCOMM14.

kSFRO_to_FLEXCOMM15 

Attach SFRO to FLEXCOMM15.

kFFRO_to_FLEXCOMM15 

Attach FFRO to FLEXCOMM15.

kAUDIO_PLL_to_FLEXCOMM15 

Attach AUDIO_PLL to FLEXCOMM15.

kMASTER_CLK_to_FLEXCOMM15 

Attach MASTER_CLK to FLEXCOMM15.

kFRG_to_FLEXCOMM15 

Attach FRG to FLEXCOMM15.

kNONE_to_FLEXCOMM15 

Attach NONE to FLEXCOMM15.

kMAIN_CLK_to_CTIMER0 

Attach MAIN_CLK to CTIMER0.

kSFRO_to_CTIMER0 

Attach SFRO to CTIMER0.

kFFRO_to_CTIMER0 

Attach FFRO to CTIMER0.

kAUDIO_PLL_to_CTIMER0 

Attach AUDIO_PLL to CTIMER0.

kMASTER_CLK_to_CTIMER0 

Attach MASTER_CLK to CTIMER0.

kLPOSC_to_CTIMER0 

Attach LPOSC to CTIMER0.

kNONE_to_CTIMER0 

Attach NONE to CTIMER0.

kMAIN_CLK_to_CTIMER1 

Attach MAIN_CLK to CTIMER1.

kSFRO_to_CTIMER1 

Attach SFRO to CTIMER1.

kFFRO_to_CTIMER1 

Attach FFRO to CTIMER1.

kAUDIO_PLL_to_CTIMER1 

Attach AUDIO_PLL to CTIMER1.

kMASTER_CLK_to_CTIMER1 

Attach MASTER_CLK to CTIMER1.

kLPOSC_to_CTIMER1 

Attach LPOSC to CTIMER1.

kNONE_to_CTIMER1 

Attach NONE to CTIMER1.

kMAIN_CLK_to_CTIMER2 

Attach MAIN_CLK to CTIMER2.

kSFRO_to_CTIMER2 

Attach SFRO to CTIMER2.

kFFRO_to_CTIMER2 

Attach FFRO to CTIMER2.

kAUDIO_PLL_to_CTIMER2 

Attach AUDIO_PLL to CTIMER2.

kMASTER_CLK_to_CTIMER2 

Attach MASTER_CLK to CTIMER2.

kLPOSC_to_CTIMER2 

Attach LPOSC to CTIMER2.

kNONE_to_CTIMER2 

Attach NONE to CTIMER2.

kMAIN_CLK_to_CTIMER3 

Attach MAIN_CLK to CTIMER3.

kSFRO_to_CTIMER3 

Attach SFRO to CTIMER3.

kFFRO_to_CTIMER3 

Attach FFRO to CTIMER3.

kAUDIO_PLL_to_CTIMER3 

Attach AUDIO_PLL to CTIMER3.

kMASTER_CLK_to_CTIMER3 

Attach MASTER_CLK to CTIMER3.

kLPOSC_to_CTIMER3 

Attach LPOSC to CTIMER3.

kNONE_to_CTIMER3 

Attach NONE to CTIMER3.

kMAIN_CLK_to_CTIMER4 

Attach MAIN_CLK to CTIMER4.

kSFRO_to_CTIMER4 

Attach SFRO to CTIMER4.

kFFRO_to_CTIMER4 

Attach FFRO to CTIMER4.

kAUDIO_PLL_to_CTIMER4 

Attach AUDIO_PLL to CTIMER4.

kMASTER_CLK_to_CTIMER4 

Attach MASTER_CLK to CTIMER4.

kLPOSC_to_CTIMER4 

Attach LPOSC to CTIMER4.

kNONE_to_CTIMER4 

Attach NONE to CTIMER4.

Enumerator
kCLOCK_DivSysCpuAhbClk 

Sys Cpu Ahb Clk Divider.

kCLOCK_DivMainPllClk 

Main Pll Clk Divider.

kCLOCK_DivDspPllClk 

Dsp Pll Clk Divider.

kCLOCK_DivAux0PllClk 

Aux0 Pll Clk Divider.

kCLOCK_DivAux1PllClk 

Aux1 Pll Clk Divider.

kCLOCK_DivPfc0Clk 

Pfc0 Clk Divider.

kCLOCK_DivPfc1Clk 

Pfc1 Clk Divider.

kCLOCK_DivAdcClk 

Adc Clk Divider.

kCLOCK_DivFlexspiClk 

Flexspi Clk Divider.

kCLOCK_DivSctClk 

Sct Clk Divider.

kCLOCK_DivSdio0Clk 

Sdio0 Clk Divider.

kCLOCK_DivSdio1Clk 

Sdio1 Clk Divider.

kCLOCK_DivSystickClk 

Systick Clk Divider.

kCLOCK_DivUsbHsFclk 

Usb Hs Fclk Divider.

kCLOCK_DivAudioPllClk 

Audio Pll Clk Divider.

kCLOCK_DivAcmpClk 

Acmp Clk Divider.

kCLOCK_DivClockOut 

Clock Out Divider.

kCLOCK_DivDmicClk 

Dmic Clk Divider.

kCLOCK_DivDspCpuClk 

Dsp Cpu Clk Divider.

kCLOCK_DivDspRamClk 

Dsp Ram Clk Divider.

kCLOCK_DivMclkClk 

Mclk Clk Divider.

kCLOCK_DivPllFrgClk 

Pll Frg Clk Divider.

kCLOCK_DivI3cClk 

I3c Clk Divider.

kCLOCK_DivI3cTcClk 

I3c Tc Clk Divider.

kCLOCK_DivI3cSlowClk 

I3c Slow Clk Divider.

Enumerator
kCLOCK_Ffro48M 

48MHz FFRO clock.

kCLOCK_Ffro60M 

60MHz FFRO clock.

Enumerator
kCLOCK_SysPllSFroClk 

16MHz FRO clock

kCLOCK_SysPllXtalIn 

OSC clock.

kCLOCK_SysPllFFroDiv2 

FRO48/60 div2 clock.

kCLOCK_SysPllNone 

Gated to reduce power.

Enumerator
kCLOCK_SysPllMult16 

Divide by 16.

kCLOCK_SysPllMult17 

Divide by 17.

kCLOCK_SysPllMult18 

Divide by 18.

kCLOCK_SysPllMult19 

Divide by 19.

kCLOCK_SysPllMult20 

Divide by 20.

kCLOCK_SysPllMult21 

Divide by 21.

kCLOCK_SysPllMult22 

Divide by 22.

Enumerator
kCLOCK_AudioPllSFroClk 

16MHz FRO clock

kCLOCK_AudioPllXtalIn 

OSC clock.

kCLOCK_AudioPllFFroDiv2 

FRO48/60 div2 clock.

kCLOCK_AudioPllNone 

Gated to reduce power.

Enumerator
kCLOCK_AudioPllMult16 

Divide by 16.

kCLOCK_AudioPllMult17 

Divide by 17.

kCLOCK_AudioPllMult18 

Divide by 18.

kCLOCK_AudioPllMult19 

Divide by 19.

kCLOCK_AudioPllMult20 

Divide by 20.

kCLOCK_AudioPllMult21 

Divide by 21.

kCLOCK_AudioPllMult22 

Divide by 22.

Function Documentation

void CLOCK_AttachClk ( clock_attach_id_t  connection)
Parameters
connection: Clock to be configured.
Returns
Nothing
void CLOCK_SetClkDiv ( clock_div_name_t  div_name,
uint32_t  divider 
)
Parameters
div_name: Clock divider name
divider: Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
Returns
Nothing
uint32_t CLOCK_GetFreq ( clock_name_t  clockName)
Returns
Frequency of selected clock
uint32_t CLOCK_GetFRGClock ( uint32_t  id)
Returns
Input Frequency for FRG
void CLOCK_SetFRGClock ( const clock_frg_clk_config_t config)
Parameters
config: Configuration to set to FRGn clock.
static uint32_t CLOCK_GetSFroFreq ( void  )
inlinestatic
Returns
Frequency of FRO 16MHz
uint32_t CLOCK_GetSysPllFreq ( void  )
Returns
Frequency of SYSPLL
uint32_t CLOCK_GetSysPfdFreq ( clock_pfd_t  pfd)
Parameters
pfd: pfd name to get frequency.
Returns
Frequency of SYSPLL PFD.
uint32_t CLOCK_GetAudioPllFreq ( void  )
Returns
Frequency of AUDIO PLL
uint32_t CLOCK_GetAudioPfdFreq ( clock_pfd_t  pfd)
Parameters
pfd: pfd name to get frequency.
Returns
Frequency of AUDIO PLL PFD.
uint32_t CLOCK_GetFFroFreq ( void  )
Returns
Frequency of High-Freq output of FRO
uint32_t CLOCK_GetMainClkFreq ( void  )
Returns
Frequency of main clk
uint32_t CLOCK_GetDspMainClkFreq ( void  )
Returns
Frequency of DSP main clk
uint32_t CLOCK_GetAcmpClkFreq ( void  )
Returns
Frequency of ACMP clk
uint32_t CLOCK_GetDmicClkFreq ( void  )
Returns
Frequency of DMIC clk
uint32_t CLOCK_GetUsbClkFreq ( void  )
Returns
Frequency of USB clk
uint32_t CLOCK_GetSdioClkFreq ( uint32_t  id)
Parameters
id: SDIO index to get frequency.
Returns
Frequency of SDIO clk
uint32_t CLOCK_GetI3cClkFreq ( void  )
Returns
Frequency of I3C clk
uint32_t CLOCK_GetSystickClkFreq ( void  )
Returns
Frequency of systick clk
uint32_t CLOCK_GetWdtClkFreq ( uint32_t  id)
Parameters
id: WDT index to get frequency.
Returns
Frequency of WDT clk
uint32_t CLOCK_GetMclkClkFreq ( void  )
Returns
Frequency of mclk clk
uint32_t CLOCK_GetSctClkFreq ( void  )
Returns
Frequency of sct clk
void CLOCK_EnableSysOscClk ( bool  enable,
bool  enableLowPower,
uint32_t  delay_us 
)
Parameters
enable: true to enable system osc clock, false to bypass system osc.
enableLowPower: true to enable low power mode, false to enable high gain mode.
delay_us: Delay time after OSC power up.
static uint32_t CLOCK_GetXtalInClkFreq ( void  )
inlinestatic
Returns
Frequency of sys osc Clock. Or CLK_IN pin frequency.
static uint32_t CLOCK_GetMclkInClkFreq ( void  )
inlinestatic
Returns
Frequency of MCLK input Clock.
static uint32_t CLOCK_GetLpOscFreq ( void  )
inlinestatic
Returns
Frequency of LPOSC
static uint32_t CLOCK_GetOsc32KFreq ( void  )
inlinestatic
Returns
Frequency of 32kHz osc
static void CLOCK_EnableOsc32K ( bool  enable)
inlinestatic
Parameters
enable: true to enable 32k osc clock, false to disable clock
static uint32_t CLOCK_GetWakeClk32KFreq ( void  )
inlinestatic
Returns
Frequency of 32kHz wake clk
static void CLOCK_SetXtalFreq ( uint32_t  freq)
inlinestatic
Parameters
freq: The XTAL input clock frequency in Hz.
static void CLOCK_SetClkinFreq ( uint32_t  freq)
inlinestatic
Parameters
freq: The CLK_IN pin input clock frequency in Hz.
static void CLOCK_SetMclkFreq ( uint32_t  freq)
inlinestatic
Parameters
freq: The MCLK input clock frequency in Hz.
uint32_t CLOCK_GetFlexCommClkFreq ( uint32_t  id)
Parameters
id: flexcomm index to get frequency.
Returns
Frequency of Flexcomm functional Clock
uint32_t CLOCK_GetCtimerClkFreq ( uint32_t  id)
Parameters
id: ctimer index to get frequency.
Returns
Frequency of Ctimer Clock
uint32_t CLOCK_GetClockOutClkFreq ( void  )
Returns
Frequency of ClockOut
uint32_t CLOCK_GetAdcClkFreq ( void  )
Returns
Frequency of Adc Clock.
uint32_t CLOCK_GetFlexspiClkFreq ( void  )
Returns
Frequency of Flexspi.
void CLOCK_EnableFfroClk ( clock_ffro_freq_t  ffroFreq)

brief Enable FFRO 48M/60M clock. param ffroFreq : target fro frequency. return Nothing

void CLOCK_EnableSfroClk ( void  )

brief Enable SFRO clock. param Nothing return Nothing

void CLOCK_InitSysPll ( const clock_sys_pll_config_t config)
Parameters
config: Configuration to set to PLL.
static void CLOCK_DeinitSysPll ( void  )
inlinestatic

param none.

void CLOCK_InitSysPfd ( clock_pfd_t  pfd,
uint8_t  divider 
)
Parameters
pfd: Which PFD clock to enable.
divider: The PFD divider value.
Note
It is recommended that PFD settings are kept between 12-35.
static void CLOCK_DeinitSysPfd ( clock_pfd_t  pfd)
inlinestatic

param pfd : Which PFD clock to disable.

void CLOCK_InitAudioPll ( const clock_audio_pll_config_t config)
Parameters
config: Configuration to set to PLL.
static void CLOCK_DeinitAudioPll ( void  )
inlinestatic

param none.

void CLOCK_InitAudioPfd ( clock_pfd_t  pfd,
uint8_t  divider 
)
Parameters
pfd: Which PFD clock to enable.
divider: The PFD divider value.
Note
It is recommended that PFD settings are kept between 12-35.
static void CLOCK_DeinitAudioPfd ( uint32_t  pfd)
inlinestatic

param pfd : Which PFD clock to disable.

void CLOCK_EnableUsbhsDeviceClock ( void  )

This function enables USB HS device PLL clock.

void CLOCK_EnableUsbhsHostClock ( void  )

This function enables USB HS host PLL clock.

bool CLOCK_EnableUsbHs0PhyPllClock ( clock_attach_id_t  src,
uint32_t  freq 
)

param src USB HS clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

Variable Documentation

volatile uint32_t g_xtalFreq

The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 16MHz,

* CLOCK_SetXtalFreq(160000000);
*
volatile uint32_t g_clkinFreq

The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetClkinFreq to set the value in to clock driver. For example, if CLK_IN is 16MHz,

* CLOCK_SetClkinFreq(160000000);
*
volatile uint32_t g_mclkFreq

The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the function CLOCK_SetMclkInFreq to set the value in to clock driver. For example, if mclk_In is 16MHz,

* CLOCK_SetMclkInFreq(160000000);
*