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MCUXpresso SDK API Reference Manual
Rev 2.13.0
NXP Semiconductors
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The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
The clock driver supports:
Files | |
file | fsl_clock.h |
Data Structures | |
struct | clock_sys_pll_config_t |
PLL configuration for SYSPLL. More... | |
struct | clock_audio_pll_config_t |
PLL configuration for SYSPLL. More... | |
struct | clock_frg_clk_config_t |
PLL configuration for FRG. More... | |
Macros | |
#define | CMP_CLOCKS |
Clock ip name array for ACMP. More... | |
#define | FLEXCOMM_CLOCKS |
Clock ip name array for FLEXCOMM. More... | |
#define | USART_CLOCKS |
Clock ip name array for LPUART. More... | |
#define | I2C_CLOCKS |
Clock ip name array for I2C. More... | |
#define | I3C_CLOCKS |
Clock ip name array for I3C. More... | |
#define | SPI_CLOCKS |
Clock ip name array for SPI. More... | |
#define | FLEXI2S_CLOCKS |
Clock ip name array for FLEXI2S. More... | |
#define | UTICK_CLOCKS |
Clock ip name array for UTICK. More... | |
#define | DMIC_CLOCKS |
Clock ip name array for DMIC. More... | |
#define | CTIMER_CLOCKS |
Clock ip name array for CT32B. More... | |
#define | GPIO_CLOCKS |
Clock ip name array for GPIO. More... | |
#define | LPADC_CLOCKS |
Clock ip name array for ADC. More... | |
#define | MRT_CLOCKS |
Clock ip name array for MRT. More... | |
#define | SCT_CLOCKS |
Clock ip name array for SCT. More... | |
#define | RTC_CLOCKS |
Clock ip name array for RTC. More... | |
#define | WWDT_CLOCKS |
Clock ip name array for WWDT. More... | |
#define | CRC_CLOCKS |
Clock ip name array for CRC. More... | |
#define | USBD_CLOCKS |
Clock ip name array for USBD. More... | |
#define | DMA_CLOCKS |
Clock ip name array for DMA. More... | |
#define | PINT_CLOCKS |
Clock ip name array for PINT. More... | |
#define | FLEXSPI_CLOCKS |
Clock ip name array for FLEXSPI. | |
#define | CACHE64_CLOCKS |
Clock ip name array for Cache64. | |
#define | MU_CLOCKS |
Clock ip name array for MUA. | |
#define | SEMA42_CLOCKS |
Clock ip name array for SEMA. | |
#define | TRNG_CLOCKS |
Clock ip name array for RNG. | |
#define | PUF_CLOCKS |
Clock ip name array for PUF. | |
#define | HASHCRYPT_CLOCKS |
Clock ip name array for HashCrypt. | |
#define | CASPER_CLOCKS |
Clock ip name array for Casper. | |
#define | USDHC_CLOCKS |
Clock ip name array for uSDHC. | |
#define | OSTIMER_CLOCKS |
Clock ip name array for OSTimer. | |
#define | POWERQUAD_CLOCKS |
Clock ip name array for Powerquad. | |
#define | CLK_GATE_REG_OFFSET_SHIFT 8U |
Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More... | |
#define | SYSPLL0CLKSEL_OFFSET 0x200 |
Clock Mux Switches The encoding is as follows each connection identified is 32bits wide starting from LSB upwards. More... | |
Enumerations | |
enum | clock_ip_name_t { kCLOCK_IpInvalid = 0U, kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21), kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22), kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23), kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24), kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15), kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24), kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27), kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28), kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29), kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31), kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30), kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31) } |
Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More... | |
enum | clock_name_t { kCLOCK_CoreSysClk, kCLOCK_BusClk, kCLOCK_MclkClk, kCLOCK_ClockOutClk, kCLOCK_AdcClk, kCLOCK_FlexspiClk, kCLOCK_SctClk, kCLOCK_Wdt0Clk, kCLOCK_Wdt1Clk, kCLOCK_SystickClk, kCLOCK_Sdio0Clk, kCLOCK_Sdio1Clk, kCLOCK_I3cClk, kCLOCK_UsbClk, kCLOCK_DmicClk, kCLOCK_DspCpuClk, kCLOCK_AcmpClk, kCLOCK_Flexcomm0Clk, kCLOCK_Flexcomm1Clk, kCLOCK_Flexcomm2Clk, kCLOCK_Flexcomm3Clk, kCLOCK_Flexcomm4Clk, kCLOCK_Flexcomm5Clk, kCLOCK_Flexcomm6Clk, kCLOCK_Flexcomm7Clk, kCLOCK_Flexcomm14Clk, kCLOCK_Flexcomm15Clk } |
Clock name used to get clock frequency. More... | |
enum | clock_pfd_t { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U } |
PLL PFD clock name. More... | |
enum | clock_attach_id_t { kSFRO_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0), kXTALIN_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1), kFFRO_DIV2_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 2), kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7), kSFRO_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0), kXTALIN_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1), kFFRO_DIV2_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 2), kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7), kFFRO_DIV4_to_MAIN_CLK, kXTALIN_CLK_to_MAIN_CLK, kLPOSC_to_MAIN_CLK, kFFRO_to_MAIN_CLK, kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1), kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2), kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 3), kFFRO_to_DSP_MAIN_CLK, kXTALIN_CLK_to_DSP_MAIN_CLK, kLPOSC_to_DSP_MAIN_CLK, kSFRO_to_DSP_MAIN_CLK, kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1), kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2), kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3), kSFRO_to_ADC_CLK, kXTALIN_CLK_to_ADC_CLK, kLPOSC_to_ADC_CLK, kFFRO_to_ADC_CLK, kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1), kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3), kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 5), kSFRO_to_CLKOUT, kXTALIN_CLK_to_CLKOUT, kLPOSC_to_CLKOUT, kFFRO_to_CLKOUT, kMAIN_CLK_to_CLKOUT, kDSP_MAIN_to_CLKOUT, kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1), kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2), kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3), kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4), kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5), kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6), kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7), kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 0), kFFRO_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 1), kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 7), kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 0), kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 1), kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 7), kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 0), kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 1), kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 2), kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 7), kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 0), kMAIN_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 1), kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 2), kFFRO_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 3), kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 4), kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 7), kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0), kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1), kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2), kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3), kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4), kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5), kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7), kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0), kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7), kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0), kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7), kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0), kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7), kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 0), kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 1), kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 7), kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3), kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7), kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0), kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1), kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2), kFFRO_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3), kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4), kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7), kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0), kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1), kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2), kFFRO_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3), kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4), kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7), kXTALIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0), kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1), kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7), kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0), kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1), kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7), kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0), kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2), kMASTER_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3), kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4), k32K_WAKE_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 5), kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7), kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0), kSFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1), kFFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2), kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3), kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 4), kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7), kSFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0), kFFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1), kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2), kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3), kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 4), kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7), kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0), kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1), kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2), kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3), kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4), kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 5), kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7), kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0), kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1), kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2), kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3), kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4), kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 5), kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7), kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0), kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1), kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2), kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3), kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4), kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 5), kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7), kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0), kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1), kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2), kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3), kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4), kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 5), kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7), kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0), kSFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1), kFFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2), kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3), kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4), kLPOSC_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 5), kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7) } |
The enumerator of clock attach Id. More... | |
enum | clock_div_name_t { kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0), kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0), kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0), kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0), kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0), kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0), kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0), kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0), kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKDIV_OFFSET, 0), kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0), kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0), kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0), kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0), kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTDIV_OFFSET, 0), kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0), kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), kCLOCK_DivDspRamClk = CLKCTL1_TUPLE_MUXA(DSPMAINRAMCLKDIV_OFFSET, 0), kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0), kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0), kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKDIV_OFFSET, 0), kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCDIV_OFFSET, 0), kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSDIV_OFFSET, 0) } |
Clock dividers. More... | |
enum | clock_ffro_freq_t { kCLOCK_Ffro48M, kCLOCK_Ffro60M } |
FFRO frequence configuration. More... | |
enum | sys_pll_src_t { kCLOCK_SysPllSFroClk = 0, kCLOCK_SysPllXtalIn = 1, kCLOCK_SysPllFFroDiv2 = 2, kCLOCK_SysPllNone = 7 } |
SysPLL Reference Input Clock Source. More... | |
enum | sys_pll_mult_t { kCLOCK_SysPllMult16 = 0, kCLOCK_SysPllMult17, kCLOCK_SysPllMult18, kCLOCK_SysPllMult19, kCLOCK_SysPllMult20, kCLOCK_SysPllMult21, kCLOCK_SysPllMult22 } |
SysPLL Multiplication Factor. More... | |
enum | audio_pll_src_t { kCLOCK_AudioPllSFroClk = 0, kCLOCK_AudioPllXtalIn = 1, kCLOCK_AudioPllFFroDiv2 = 2, kCLOCK_AudioPllNone = 7 } |
AudioPll Reference Input Clock Source. More... | |
enum | audio_pll_mult_t { kCLOCK_AudioPllMult16 = 0, kCLOCK_AudioPllMult17, kCLOCK_AudioPllMult18, kCLOCK_AudioPllMult19, kCLOCK_AudioPllMult20, kCLOCK_AudioPllMult21, kCLOCK_AudioPllMult22 } |
AudioPll Multiplication Factor. More... | |
Functions | |
void | CLOCK_AttachClk (clock_attach_id_t connection) |
Configure the clock selection muxes. More... | |
void | CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divider) |
Setup peripheral clock dividers. More... | |
uint32_t | CLOCK_GetFreq (clock_name_t clockName) |
Return Frequency of selected clock. More... | |
uint32_t | CLOCK_GetFRGClock (uint32_t id) |
Return Input frequency for the Fractional baud rate generator. More... | |
void | CLOCK_SetFRGClock (const clock_frg_clk_config_t *config) |
Set output of the Fractional baud rate generator. More... | |
static uint32_t | CLOCK_GetSFroFreq (void) |
Return Frequency of FRO 16MHz. More... | |
uint32_t | CLOCK_GetSysPllFreq (void) |
Return Frequency of SYSPLL. More... | |
uint32_t | CLOCK_GetSysPfdFreq (clock_pfd_t pfd) |
Get current output frequency of specific System PLL PFD. More... | |
uint32_t | CLOCK_GetAudioPllFreq (void) |
Return Frequency of AUDIO PLL. More... | |
uint32_t | CLOCK_GetAudioPfdFreq (clock_pfd_t pfd) |
Get current output frequency of specific Audio PLL PFD. More... | |
uint32_t | CLOCK_GetFFroFreq (void) |
Return Frequency of High-Freq output of FRO. More... | |
uint32_t | CLOCK_GetMainClkFreq (void) |
Return Frequency of main clk. More... | |
uint32_t | CLOCK_GetDspMainClkFreq (void) |
Return Frequency of DSP main clk. More... | |
uint32_t | CLOCK_GetAcmpClkFreq (void) |
Return Frequency of ACMP clk. More... | |
uint32_t | CLOCK_GetDmicClkFreq (void) |
Return Frequency of DMIC clk. More... | |
uint32_t | CLOCK_GetUsbClkFreq (void) |
Return Frequency of USB clk. More... | |
uint32_t | CLOCK_GetSdioClkFreq (uint32_t id) |
Return Frequency of SDIO clk. More... | |
uint32_t | CLOCK_GetI3cClkFreq (void) |
Return Frequency of I3C clk. More... | |
uint32_t | CLOCK_GetSystickClkFreq (void) |
Return Frequency of systick clk. More... | |
uint32_t | CLOCK_GetWdtClkFreq (uint32_t id) |
Return Frequency of WDT clk. More... | |
uint32_t | CLOCK_GetMclkClkFreq (void) |
Return Frequency of mclk. More... | |
uint32_t | CLOCK_GetSctClkFreq (void) |
Return Frequency of sct. More... | |
void | CLOCK_EnableSysOscClk (bool enable, bool enableLowPower, uint32_t delay_us) |
Enable/Disable sys osc clock from external crystal clock. More... | |
static uint32_t | CLOCK_GetXtalInClkFreq (void) |
Return Frequency of sys osc Clock. More... | |
static uint32_t | CLOCK_GetMclkInClkFreq (void) |
Return Frequency of MCLK Input Clock. More... | |
static uint32_t | CLOCK_GetLpOscFreq (void) |
Return Frequency of Lower power osc. More... | |
static uint32_t | CLOCK_GetOsc32KFreq (void) |
Return Frequency of 32kHz osc. More... | |
static void | CLOCK_EnableOsc32K (bool enable) |
Enables and disables 32kHz osc. More... | |
static uint32_t | CLOCK_GetWakeClk32KFreq (void) |
Return Frequency of 32khz wake clk. More... | |
static void | CLOCK_SetXtalFreq (uint32_t freq) |
Set the XTALIN (system OSC) frequency based on board setting. More... | |
static void | CLOCK_SetClkinFreq (uint32_t freq) |
Set the CLKIN (CLKIN pin) frequency based on board setting. More... | |
static void | CLOCK_SetMclkFreq (uint32_t freq) |
Set the MCLK in (mclk_in) clock frequency based on board setting. More... | |
uint32_t | CLOCK_GetFlexCommClkFreq (uint32_t id) |
Return Frequency of Flexcomm functional Clock. More... | |
uint32_t | CLOCK_GetCtimerClkFreq (uint32_t id) |
Return Frequency of Ctimer Clock. More... | |
uint32_t | CLOCK_GetClockOutClkFreq (void) |
Return Frequency of ClockOut. More... | |
uint32_t | CLOCK_GetAdcClkFreq (void) |
Return Frequency of Adc Clock. More... | |
uint32_t | CLOCK_GetFlexspiClkFreq (void) |
Return Frequency of Flexspi Clock. More... | |
void | CLOCK_EnableFfroClk (clock_ffro_freq_t ffroFreq) |
void | CLOCK_EnableSfroClk (void) |
void | CLOCK_InitSysPll (const clock_sys_pll_config_t *config) |
Initialize the System PLL. More... | |
static void | CLOCK_DeinitSysPll (void) |
brief Deinit the System PLL. More... | |
void | CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t divider) |
Initialize the System PLL PFD. More... | |
static void | CLOCK_DeinitSysPfd (clock_pfd_t pfd) |
brief Disable the audio PLL PFD. More... | |
void | CLOCK_InitAudioPll (const clock_audio_pll_config_t *config) |
Initialize the audio PLL. More... | |
static void | CLOCK_DeinitAudioPll (void) |
brief Deinit the Audio PLL. More... | |
void | CLOCK_InitAudioPfd (clock_pfd_t pfd, uint8_t divider) |
Initialize the audio PLL PFD. More... | |
static void | CLOCK_DeinitAudioPfd (uint32_t pfd) |
brief Disable the audio PLL PFD. More... | |
void | CLOCK_EnableUsbhsDeviceClock (void) |
Enable USB HS device PLL clock. More... | |
void | CLOCK_EnableUsbhsHostClock (void) |
Enable USB HS host PLL clock. More... | |
bool | CLOCK_EnableUsbHs0PhyPllClock (clock_attach_id_t src, uint32_t freq) |
brief Enable USB hs0PhyPll clock. More... | |
Variables | |
volatile uint32_t | g_xtalFreq |
External XTAL (SYSOSC) clock frequency. More... | |
volatile uint32_t | g_clkinFreq |
External CLK_IN pin clock frequency (clkin) clock frequency. More... | |
volatile uint32_t | g_mclkFreq |
External XTAL (SYSOSC) clock frequency. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 2)) |
CLOCK driver version 2.7.2. More... | |
struct clock_sys_pll_config_t |
Data Fields | |
sys_pll_src_t | sys_pll_src |
Reference Input Clock Source. | |
uint32_t | numerator |
30 bit numerator of fractional loop divider. More... | |
uint32_t | denominator |
30 bit numerator of fractional loop divider. More... | |
sys_pll_mult_t | sys_pll_mult |
Multiplication Factor. | |
uint32_t clock_sys_pll_config_t::numerator |
uint32_t clock_sys_pll_config_t::denominator |
struct clock_audio_pll_config_t |
Data Fields | |
audio_pll_src_t | audio_pll_src |
Reference Input Clock Source. | |
uint32_t | numerator |
30 bit numerator of fractional loop divider. More... | |
uint32_t | denominator |
30 bit numerator of fractional loop divider. More... | |
audio_pll_mult_t | audio_pll_mult |
Multiplication Factor. | |
uint32_t clock_audio_pll_config_t::numerator |
uint32_t clock_audio_pll_config_t::denominator |
struct clock_frg_clk_config_t |
Public Types | |
enum | { kCLOCK_FrgMainClk = 0, kCLOCK_FrgPllDiv, kCLOCK_FrgSFro, kCLOCK_FrgFFro } |
Data Fields | |
uint8_t | num |
FRG clock. | |
uint8_t | divider |
Denominator of the fractional divider. More... | |
uint8_t | mult |
Numerator of the fractional divider. More... | |
anonymous enum |
uint8_t clock_frg_clk_config_t::divider |
uint8_t clock_frg_clk_config_t::mult |
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 2)) |
#define CMP_CLOCKS |
#define FLEXCOMM_CLOCKS |
#define USART_CLOCKS |
#define I2C_CLOCKS |
#define I3C_CLOCKS |
#define SPI_CLOCKS |
#define FLEXI2S_CLOCKS |
#define UTICK_CLOCKS |
#define DMIC_CLOCKS |
#define CTIMER_CLOCKS |
#define GPIO_CLOCKS |
#define LPADC_CLOCKS |
#define MRT_CLOCKS |
#define SCT_CLOCKS |
#define RTC_CLOCKS |
#define WWDT_CLOCKS |
#define CRC_CLOCKS |
#define USBD_CLOCKS |
#define DMA_CLOCKS |
#define PINT_CLOCKS |
#define CLK_GATE_REG_OFFSET_SHIFT 8U |
#define SYSPLL0CLKSEL_OFFSET 0x200 |
[12 bits for reg offset, 0 means end of descriptor, 4 bits for choice] [bit 31 define CLKCTL0 or CLKCTL1]*
enum clock_ip_name_t |
enum clock_name_t |
enum clock_pfd_t |
enum clock_attach_id_t |
enum clock_div_name_t |
enum clock_ffro_freq_t |
enum sys_pll_src_t |
enum sys_pll_mult_t |
enum audio_pll_src_t |
enum audio_pll_mult_t |
void CLOCK_AttachClk | ( | clock_attach_id_t | connection | ) |
connection | : Clock to be configured. |
void CLOCK_SetClkDiv | ( | clock_div_name_t | div_name, |
uint32_t | divider | ||
) |
div_name | : Clock divider name |
divider | : Value to be divided. Divided clock frequency = Undivided clock frequency / divider. |
uint32_t CLOCK_GetFreq | ( | clock_name_t | clockName | ) |
uint32_t CLOCK_GetFRGClock | ( | uint32_t | id | ) |
void CLOCK_SetFRGClock | ( | const clock_frg_clk_config_t * | config | ) |
config | : Configuration to set to FRGn clock. |
|
inlinestatic |
uint32_t CLOCK_GetSysPllFreq | ( | void | ) |
uint32_t CLOCK_GetSysPfdFreq | ( | clock_pfd_t | pfd | ) |
pfd | : pfd name to get frequency. |
uint32_t CLOCK_GetAudioPllFreq | ( | void | ) |
uint32_t CLOCK_GetAudioPfdFreq | ( | clock_pfd_t | pfd | ) |
pfd | : pfd name to get frequency. |
uint32_t CLOCK_GetFFroFreq | ( | void | ) |
uint32_t CLOCK_GetMainClkFreq | ( | void | ) |
uint32_t CLOCK_GetDspMainClkFreq | ( | void | ) |
uint32_t CLOCK_GetAcmpClkFreq | ( | void | ) |
uint32_t CLOCK_GetDmicClkFreq | ( | void | ) |
uint32_t CLOCK_GetUsbClkFreq | ( | void | ) |
uint32_t CLOCK_GetSdioClkFreq | ( | uint32_t | id | ) |
id | : SDIO index to get frequency. |
uint32_t CLOCK_GetI3cClkFreq | ( | void | ) |
uint32_t CLOCK_GetSystickClkFreq | ( | void | ) |
uint32_t CLOCK_GetWdtClkFreq | ( | uint32_t | id | ) |
id | : WDT index to get frequency. |
uint32_t CLOCK_GetMclkClkFreq | ( | void | ) |
uint32_t CLOCK_GetSctClkFreq | ( | void | ) |
void CLOCK_EnableSysOscClk | ( | bool | enable, |
bool | enableLowPower, | ||
uint32_t | delay_us | ||
) |
enable | : true to enable system osc clock, false to bypass system osc. |
enableLowPower | : true to enable low power mode, false to enable high gain mode. |
delay_us | : Delay time after OSC power up. |
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enable | : true to enable 32k osc clock, false to disable clock |
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freq | : The XTAL input clock frequency in Hz. |
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freq | : The CLK_IN pin input clock frequency in Hz. |
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freq | : The MCLK input clock frequency in Hz. |
uint32_t CLOCK_GetFlexCommClkFreq | ( | uint32_t | id | ) |
id | : flexcomm index to get frequency. |
uint32_t CLOCK_GetCtimerClkFreq | ( | uint32_t | id | ) |
id | : ctimer index to get frequency. |
uint32_t CLOCK_GetClockOutClkFreq | ( | void | ) |
uint32_t CLOCK_GetAdcClkFreq | ( | void | ) |
uint32_t CLOCK_GetFlexspiClkFreq | ( | void | ) |
void CLOCK_EnableFfroClk | ( | clock_ffro_freq_t | ffroFreq | ) |
brief Enable FFRO 48M/60M clock. param ffroFreq : target fro frequency. return Nothing
void CLOCK_EnableSfroClk | ( | void | ) |
brief Enable SFRO clock. param Nothing return Nothing
void CLOCK_InitSysPll | ( | const clock_sys_pll_config_t * | config | ) |
config | : Configuration to set to PLL. |
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param none.
void CLOCK_InitSysPfd | ( | clock_pfd_t | pfd, |
uint8_t | divider | ||
) |
pfd | : Which PFD clock to enable. |
divider | : The PFD divider value. |
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param pfd : Which PFD clock to disable.
void CLOCK_InitAudioPll | ( | const clock_audio_pll_config_t * | config | ) |
config | : Configuration to set to PLL. |
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param none.
void CLOCK_InitAudioPfd | ( | clock_pfd_t | pfd, |
uint8_t | divider | ||
) |
pfd | : Which PFD clock to enable. |
divider | : The PFD divider value. |
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param pfd : Which PFD clock to disable.
void CLOCK_EnableUsbhsDeviceClock | ( | void | ) |
This function enables USB HS device PLL clock.
void CLOCK_EnableUsbhsHostClock | ( | void | ) |
This function enables USB HS host PLL clock.
bool CLOCK_EnableUsbHs0PhyPllClock | ( | clock_attach_id_t | src, |
uint32_t | freq | ||
) |
param src USB HS clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.
volatile uint32_t g_xtalFreq |
The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 16MHz,
volatile uint32_t g_clkinFreq |
The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetClkinFreq to set the value in to clock driver. For example, if CLK_IN is 16MHz,
volatile uint32_t g_mclkFreq |
The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the function CLOCK_SetMclkInFreq to set the value in to clock driver. For example, if mclk_In is 16MHz,