MCUXpresso SDK API Reference Manual  Rev 2.14.0
NXP Semiconductors
 All Data Structures Functions Variables Typedefs Enumerations Enumerator Groups Pages
Edma_soc

Overview

Macros

#define FSL_EDMA_SOC_IP_DMA3   (1)
 DMA IP version.
 
#define EDMA_BASE_PTRS
 DMA base table.
 
#define EDMA_CHANNEL_OFFSET   0x10000U
 EDMA base address convert macro.
 

Enumerations

enum  dma_request_source_t {
  kDmaRequestDisabled = 0U,
  Dma3RequestMuxCAN1 = 1U | 0x100U,
  Dma3RequestMuxGPIO1Request0 = 3U | 0x100U,
  Dma3RequestMuxGPIO1Request1 = 4U | 0x100U,
  Dma3RequestMuxI3C1ToBusRequest = 5U | 0x100U,
  Dma3RequestMuxI3C1FromBusRequest = 6U | 0x100U,
  Dma3RequestMuxLPI2C1Tx = 7U | 0x100U,
  Dma3RequestMuxLPI2C1Rx = 8U | 0x100U,
  Dma3RequestMuxLPI2C2Tx = 9U | 0x100U,
  Dma3RequestMuxLPI2C2Rx = 10U | 0x100U,
  Dma3RequestMuxLPSPI1Tx = 11U | 0x100U,
  Dma3RequestMuxLPSPI1Rx = 12U | 0x100U,
  Dma3RequestMuxLPSPI2Tx = 13U | 0x100U,
  Dma3RequestMuxLPSPI2Rx = 14U | 0x100U,
  Dma3RequestMuxLPTMR1Request = 15U | 0x100U,
  Dma3RequestMuxLPUART1Tx = 16U | 0x100U,
  Dma3RequestMuxLPUART1Rx = 17U | 0x100U,
  Dma3RequestMuxLPUART2Tx = 18U | 0x100U,
  Dma3RequestMuxLPUART2Rx = 19U | 0x100U,
  Dma3RequestMuxEdgelockRequest = 20U | 0x100U,
  Dma3RequestMuxSai1Tx = 21U | 0x100U,
  Dma3RequestMuxSai1Rx = 22U | 0x100U,
  Dma3RequestMuxTPM1Request0Request2 = 23U | 0x100U,
  Dma3RequestMuxTPM1Request1Request3 = 24U | 0x100U,
  Dma3RequestMuxTPM1OverflowRequest = 25U | 0x100U,
  Dma3RequestMuxTPM2Request0Request2 = 26U | 0x100U,
  Dma3RequestMuxTPM2Request1Request3 = 27U | 0x100U,
  Dma3RequestMuxTPM2OverflowRequest = 28U | 0x100U,
  Dma3RequestMuxPDMRequest = 29U | 0x100U,
  Dma3RequestMuxADC1Request = 30U | 0x100U,
  Dma4RequestMuxCAN2 = 1U | 0x200U,
  Dma4RequestMuxGPIO2Request0 = 2U | 0x200U,
  Dma4RequestMuxGPIO2Request1 = 3U | 0x200U,
  Dma4RequestMuxGPIO3Request0 = 4U | 0x200U,
  Dma4RequestMuxGPIO3Request1 = 5U | 0x200U,
  Dma4RequestMuxI3C2ToBusRequest = 6U | 0x200U,
  Dma4RequestMuxI3C2FromBusRequest = 7U | 0x200U,
  Dma4RequestMuxLPI2C3Tx = 8U | 0x200U,
  Dma4RequestMuxLPI2C3Rx = 9U | 0x200U,
  Dma4RequestMuxLPI2C4Tx = 10U | 0x200U,
  Dma4RequestMuxLPI2C4Rx = 11U | 0x200U,
  Dma4RequestMuxLPSPI3Tx = 12U | 0x200U,
  Dma4RequestMuxLPSPI3Rx = 13U | 0x200U,
  Dma4RequestMuxLPSPI4Tx = 14U | 0x200U,
  Dma4RequestMuxLPSPI4Rx = 15U | 0x200U,
  Dma4RequestMuxLPTMR2Request = 16U | 0x200U,
  Dma4RequestMuxLPUART3Tx = 17U | 0x200U,
  Dma4RequestMuxLPUART3Rx = 18U | 0x200U,
  Dma4RequestMuxLPUART4Tx = 19U | 0x200U,
  Dma4RequestMuxLPUART4Rx = 20U | 0x200U,
  Dma4RequestMuxLPUART5Tx = 21U | 0x200U,
  Dma4RequestMuxLPUART5Rx = 22U | 0x200U,
  Dma4RequestMuxLPUART6Tx = 23U | 0x200U,
  Dma4RequestMuxLPUART6Rx = 24U | 0x200U,
  Dma4RequestMuxTPM3Request0Request2 = 25U | 0x200U,
  Dma4RequestMuxTPM3Request1Request3 = 26U | 0x200U,
  Dma4RequestMuxTPM3OverflowRequest = 27U | 0x200U,
  Dma4RequestMuxTPM4Request0Request2 = 28U | 0x200U,
  Dma4RequestMuxTPM4Request1Request3 = 29U | 0x200U,
  Dma4RequestMuxTPM4OverflowRequest = 30U | 0x200U,
  Dma4RequestMuxTPM5Request0Request2 = 31U | 0x200U,
  Dma4RequestMuxTPM5Request1Request3 = 32U | 0x200U,
  Dma4RequestMuxTPM5OverflowRequest = 33U | 0x200U,
  Dma4RequestMuxTPM6Request0Request2 = 34U | 0x200U,
  Dma4RequestMuxTPM6Request1Request3 = 35U | 0x200U,
  Dma4RequestMuxTPM6OverflowRequest = 36U | 0x200U,
  Dma4RequestMuxFlexIO1Request0 = 37U | 0x200U,
  Dma4RequestMuxFlexIO1Request1 = 38U | 0x200U,
  Dma4RequestMuxFlexIO1Request2 = 39U | 0x200U,
  Dma4RequestMuxFlexIO1Request3 = 40U | 0x200U,
  Dma4RequestMuxFlexIO1Request4 = 41U | 0x200U,
  Dma4RequestMuxFlexIO1Request5 = 42U | 0x200U,
  Dma4RequestMuxFlexIO1Request6 = 43U | 0x200U,
  Dma4RequestMuxFlexIO1Request7 = 44U | 0x200U,
  Dma4RequestMuxFlexIO2Request0 = 45U | 0x200U,
  Dma4RequestMuxFlexIO2Request1 = 46U | 0x200U,
  Dma4RequestMuxFlexIO2Request2 = 47U | 0x200U,
  Dma4RequestMuxFlexIO2Request3 = 48U | 0x200U,
  Dma4RequestMuxFlexIO2Request4 = 49U | 0x200U,
  Dma4RequestMuxFlexIO2Request5 = 50U | 0x200U,
  Dma4RequestMuxFlexIO2Request6 = 51U | 0x200U,
  Dma4RequestMuxFlexIO2Request7 = 52U | 0x200U,
  Dma4RequestMuxFlexSPI1Tx = 53U | 0x200U,
  Dma4RequestMuxFlexSPI1Rx = 54U | 0x200U,
  Dma4RequestMuxSai2Tx = 58U | 0x200U,
  Dma4RequestMuxSai2Rx = 59U | 0x200U,
  Dma4RequestMuxSai3Tx = 60U | 0x200U,
  Dma4RequestMuxSai3Rx = 61U | 0x200U,
  Dma4RequestMuxGPIO4Request0 = 62U | 0x200U,
  Dma4RequestMuxGPIO4Request1 = 63U | 0x200U,
  Dma4RequestMuxSPDIFRequest = 65U | 0x200U,
  Dma4RequestMuxSPDIFRequest1 = 66U | 0x200U,
  Dma4RequestMuxENETRequest = 67U | 0x200U,
  Dma4RequestMuxENETRequest1 = 68U | 0x200U,
  Dma4RequestMuxENETRequest2 = 69U | 0x200U,
  Dma4RequestMuxENETRequest3 = 70U | 0x200U,
  Dma4RequestMuxLPI2C5Tx = 71U | 0x200U,
  Dma4RequestMuxLPI2C5Rx = 72U | 0x200U,
  Dma4RequestMuxLPI2C6Tx = 73U | 0x200U,
  Dma4RequestMuxLPI2C6Rx = 74U | 0x200U,
  Dma4RequestMuxLPI2C7Tx = 75U | 0x200U,
  Dma4RequestMuxLPI2C7Rx = 76U | 0x200U,
  Dma4RequestMuxLPI2C8Tx = 77U | 0x200U,
  Dma4RequestMuxLPI2C8Rx = 78U | 0x200U,
  Dma4RequestMuxLPSPI5Tx = 79U | 0x200U,
  Dma4RequestMuxLPSPI5Rx = 80U | 0x200U,
  Dma4RequestMuxLPSPI6Tx = 81U | 0x200U,
  Dma4RequestMuxLPSPI6Rx = 82U | 0x200U,
  Dma4RequestMuxLPSPI7Tx = 83U | 0x200U,
  Dma4RequestMuxLPSPI7Rx = 84U | 0x200U,
  Dma4RequestMuxLPSPI8Tx = 85U | 0x200U,
  Dma4RequestMuxLPSPI8Rx = 86U | 0x200U,
  Dma4RequestMuxLPUART7Tx = 87U | 0x200U,
  Dma4RequestMuxLPUART7Rx = 88U | 0x200U,
  Dma4RequestMuxLPUART8Tx = 89U | 0x200U,
  Dma4RequestMuxLPUART8Rx = 90U | 0x200U,
  Dma4RequestMuxENET_QOSRequest = 91U | 0x200U,
  Dma4RequestMuxENET_QOSRequest1 = 92U | 0x200U,
  Dma4RequestMuxENET_QOSRequest2 = 93U | 0x200U,
  Dma4RequestMuxENET_QOSRequest3 = 94U | 0x200U
}
 dma request source More...
 

Driver version

#define FSL_EDMA_SOC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))
 Driver version 2.0.0. More...
 

Macro Definition Documentation

#define FSL_EDMA_SOC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))

Enumeration Type Documentation

Enumerator
kDmaRequestDisabled 

DSisabled

Dma3RequestMuxCAN1 

CAN1

Dma3RequestMuxGPIO1Request0 

GPIO1 channel 0

Dma3RequestMuxGPIO1Request1 

GPIO1 channel 1

Dma3RequestMuxI3C1ToBusRequest 

I3C1 To-bus Request

Dma3RequestMuxI3C1FromBusRequest 

I3C1 From-bus Request

Dma3RequestMuxLPI2C1Tx 

LPI2C1

Dma3RequestMuxLPI2C1Rx 

LPI2C1

Dma3RequestMuxLPI2C2Tx 

LPI2C2

Dma3RequestMuxLPI2C2Rx 

LPI2C2

Dma3RequestMuxLPSPI1Tx 

LPSPI1 Transmit

Dma3RequestMuxLPSPI1Rx 

LPSPI1 Receive

Dma3RequestMuxLPSPI2Tx 

LPSPI2 Transmit

Dma3RequestMuxLPSPI2Rx 

LPSPI2 Receive

Dma3RequestMuxLPTMR1Request 

LPTMR1 Request

Dma3RequestMuxLPUART1Tx 

LPUART1 Transmit

Dma3RequestMuxLPUART1Rx 

LPUART1 Receive

Dma3RequestMuxLPUART2Tx 

LPUART2 Transmit

Dma3RequestMuxLPUART2Rx 

LPUART2 Receive

Dma3RequestMuxEdgelockRequest 

Edgelock enclave DMA Request

Dma3RequestMuxSai1Tx 

SAI1 Transmit

Dma3RequestMuxSai1Rx 

SAI1 Receive

Dma3RequestMuxTPM1Request0Request2 

TPM1 request 0 and request 2

Dma3RequestMuxTPM1Request1Request3 

TPM1 request 1 and request 3

Dma3RequestMuxTPM1OverflowRequest 

TPM1 Overflow request

Dma3RequestMuxTPM2Request0Request2 

TPM2 request 0 and request 2

Dma3RequestMuxTPM2Request1Request3 

TPM2 request 1 and request 3

Dma3RequestMuxTPM2OverflowRequest 

TPM2 Overflow request

Dma3RequestMuxPDMRequest 

PDM

Dma3RequestMuxADC1Request 

ADC1

Dma4RequestMuxCAN2 

CAN2

Dma4RequestMuxGPIO2Request0 

GPIO2 channel 0

Dma4RequestMuxGPIO2Request1 

GPIO2 channel 1

Dma4RequestMuxGPIO3Request0 

GPIO3 channel 0

Dma4RequestMuxGPIO3Request1 

GPIO3 channel 1

Dma4RequestMuxI3C2ToBusRequest 

I3C2 To-bus Request

Dma4RequestMuxI3C2FromBusRequest 

I3C2 From-bus Request

Dma4RequestMuxLPI2C3Tx 

LPI2C3

Dma4RequestMuxLPI2C3Rx 

LPI2C3

Dma4RequestMuxLPI2C4Tx 

LPI2C4

Dma4RequestMuxLPI2C4Rx 

LPI2C4

Dma4RequestMuxLPSPI3Tx 

LPSPI3 Transmit

Dma4RequestMuxLPSPI3Rx 

LPSPI3 Receive

Dma4RequestMuxLPSPI4Tx 

LPSPI4 Transmit

Dma4RequestMuxLPSPI4Rx 

LPSPI4 Receive

Dma4RequestMuxLPTMR2Request 

LPTMR2 Request

Dma4RequestMuxLPUART3Tx 

LPUART3 Transmit

Dma4RequestMuxLPUART3Rx 

LPUART3 Receive

Dma4RequestMuxLPUART4Tx 

LPUART4 Transmit

Dma4RequestMuxLPUART4Rx 

LPUART4 Receive

Dma4RequestMuxLPUART5Tx 

LPUART5 Transmit

Dma4RequestMuxLPUART5Rx 

LPUART5 Receive

Dma4RequestMuxLPUART6Tx 

LPUART6 Transmit

Dma4RequestMuxLPUART6Rx 

LPUART6 Receive

Dma4RequestMuxTPM3Request0Request2 

TPM3 request 0 and request 2

Dma4RequestMuxTPM3Request1Request3 

TPM3 request 1 and request 3

Dma4RequestMuxTPM3OverflowRequest 

TPM3 Overflow request

Dma4RequestMuxTPM4Request0Request2 

TPM4 request 0 and request 2

Dma4RequestMuxTPM4Request1Request3 

TPM4 request 1 and request 3

Dma4RequestMuxTPM4OverflowRequest 

TPM4 Overflow request

Dma4RequestMuxTPM5Request0Request2 

TPM5 request 0 and request 2

Dma4RequestMuxTPM5Request1Request3 

TPM5 request 1 and request 3

Dma4RequestMuxTPM5OverflowRequest 

TPM5 Overflow request

Dma4RequestMuxTPM6Request0Request2 

TPM6 request 0 and request 2

Dma4RequestMuxTPM6Request1Request3 

TPM6 request 1 and request 3

Dma4RequestMuxTPM6OverflowRequest 

TPM6 Overflow request

Dma4RequestMuxFlexIO1Request0 

FlexIO1 Request0

Dma4RequestMuxFlexIO1Request1 

FlexIO1 Request1

Dma4RequestMuxFlexIO1Request2 

FlexIO1 Request2

Dma4RequestMuxFlexIO1Request3 

FlexIO1 Request3

Dma4RequestMuxFlexIO1Request4 

FlexIO1 Request4

Dma4RequestMuxFlexIO1Request5 

FlexIO1 Request5

Dma4RequestMuxFlexIO1Request6 

FlexIO1 Request6

Dma4RequestMuxFlexIO1Request7 

FlexIO1 Request7

Dma4RequestMuxFlexIO2Request0 

FlexIO2 Request0

Dma4RequestMuxFlexIO2Request1 

FlexIO2 Request1

Dma4RequestMuxFlexIO2Request2 

FlexIO2 Request2

Dma4RequestMuxFlexIO2Request3 

FlexIO2 Request3

Dma4RequestMuxFlexIO2Request4 

FlexIO2 Request4

Dma4RequestMuxFlexIO2Request5 

FlexIO2 Request5

Dma4RequestMuxFlexIO2Request6 

FlexIO2 Request6

Dma4RequestMuxFlexIO2Request7 

FlexIO2 Request7

Dma4RequestMuxFlexSPI1Tx 

FlexSPI1 Transmit

Dma4RequestMuxFlexSPI1Rx 

FlexSPI1 Receive

Dma4RequestMuxSai2Tx 

SAI2 Transmit

Dma4RequestMuxSai2Rx 

SAI2 Receive

Dma4RequestMuxSai3Tx 

SAI3 Transmit

Dma4RequestMuxSai3Rx 

SAI3 Receive

Dma4RequestMuxGPIO4Request0 

GPIO4 channel 0

Dma4RequestMuxGPIO4Request1 

GPIO4 channel 1

Dma4RequestMuxSPDIFRequest 

SPDIF

Dma4RequestMuxSPDIFRequest1 

SPDIF

Dma4RequestMuxENETRequest 

ENET

Dma4RequestMuxENETRequest1 

ENET

Dma4RequestMuxENETRequest2 

ENET

Dma4RequestMuxENETRequest3 

ENET

Dma4RequestMuxLPI2C5Tx 

LPI2C5

Dma4RequestMuxLPI2C5Rx 

LPI2C5

Dma4RequestMuxLPI2C6Tx 

LPI2C6

Dma4RequestMuxLPI2C6Rx 

LPI2C6

Dma4RequestMuxLPI2C7Tx 

LPI2C7

Dma4RequestMuxLPI2C7Rx 

LPI2C7

Dma4RequestMuxLPI2C8Tx 

LPI2C8

Dma4RequestMuxLPI2C8Rx 

LPI2C8

Dma4RequestMuxLPSPI5Tx 

LPSPI5 Transmit

Dma4RequestMuxLPSPI5Rx 

LPSPI5 Receive

Dma4RequestMuxLPSPI6Tx 

LPSPI6 Transmit

Dma4RequestMuxLPSPI6Rx 

LPSPI6 Receive

Dma4RequestMuxLPSPI7Tx 

LPSPI7 Transmit

Dma4RequestMuxLPSPI7Rx 

LPSPI7 Receive

Dma4RequestMuxLPSPI8Tx 

LPSPI8 Transmit

Dma4RequestMuxLPSPI8Rx 

LPSPI8 Receive

Dma4RequestMuxLPUART7Tx 

LPUART7 Transmit

Dma4RequestMuxLPUART7Rx 

LPUART7 Receive

Dma4RequestMuxLPUART8Tx 

LPUART8 Transmit

Dma4RequestMuxLPUART8Rx 

LPUART8 Receive

Dma4RequestMuxENET_QOSRequest 

ENET_QOS

Dma4RequestMuxENET_QOSRequest1 

ENET_QOS

Dma4RequestMuxENET_QOSRequest2 

ENET_QOS

Dma4RequestMuxENET_QOSRequest3 

ENET_QOS