| Enumerator |
|---|
| kDmaRequestDisabled |
DSisabled
|
| Dma3RequestMuxCAN1 |
CAN1
|
| Dma3RequestMuxGPIO1Request0 |
GPIO1 channel 0
|
| Dma3RequestMuxGPIO1Request1 |
GPIO1 channel 1
|
| Dma3RequestMuxI3C1ToBusRequest |
I3C1 To-bus Request
|
| Dma3RequestMuxI3C1FromBusRequest |
I3C1 From-bus Request
|
| Dma3RequestMuxLPI2C1Tx |
LPI2C1
|
| Dma3RequestMuxLPI2C1Rx |
LPI2C1
|
| Dma3RequestMuxLPI2C2Tx |
LPI2C2
|
| Dma3RequestMuxLPI2C2Rx |
LPI2C2
|
| Dma3RequestMuxLPSPI1Tx |
LPSPI1 Transmit
|
| Dma3RequestMuxLPSPI1Rx |
LPSPI1 Receive
|
| Dma3RequestMuxLPSPI2Tx |
LPSPI2 Transmit
|
| Dma3RequestMuxLPSPI2Rx |
LPSPI2 Receive
|
| Dma3RequestMuxLPTMR1Request |
LPTMR1 Request
|
| Dma3RequestMuxLPUART1Tx |
LPUART1 Transmit
|
| Dma3RequestMuxLPUART1Rx |
LPUART1 Receive
|
| Dma3RequestMuxLPUART2Tx |
LPUART2 Transmit
|
| Dma3RequestMuxLPUART2Rx |
LPUART2 Receive
|
| Dma3RequestMuxEdgelockRequest |
Edgelock enclave DMA Request
|
| Dma3RequestMuxSai1Tx |
SAI1 Transmit
|
| Dma3RequestMuxSai1Rx |
SAI1 Receive
|
| Dma3RequestMuxTPM1Request0Request2 |
TPM1 request 0 and request 2
|
| Dma3RequestMuxTPM1Request1Request3 |
TPM1 request 1 and request 3
|
| Dma3RequestMuxTPM1OverflowRequest |
TPM1 Overflow request
|
| Dma3RequestMuxTPM2Request0Request2 |
TPM2 request 0 and request 2
|
| Dma3RequestMuxTPM2Request1Request3 |
TPM2 request 1 and request 3
|
| Dma3RequestMuxTPM2OverflowRequest |
TPM2 Overflow request
|
| Dma3RequestMuxPDMRequest |
PDM
|
| Dma3RequestMuxADC1Request |
ADC1
|
| Dma4RequestMuxCAN2 |
CAN2
|
| Dma4RequestMuxGPIO2Request0 |
GPIO2 channel 0
|
| Dma4RequestMuxGPIO2Request1 |
GPIO2 channel 1
|
| Dma4RequestMuxGPIO3Request0 |
GPIO3 channel 0
|
| Dma4RequestMuxGPIO3Request1 |
GPIO3 channel 1
|
| Dma4RequestMuxI3C2ToBusRequest |
I3C2 To-bus Request
|
| Dma4RequestMuxI3C2FromBusRequest |
I3C2 From-bus Request
|
| Dma4RequestMuxLPI2C3Tx |
LPI2C3
|
| Dma4RequestMuxLPI2C3Rx |
LPI2C3
|
| Dma4RequestMuxLPI2C4Tx |
LPI2C4
|
| Dma4RequestMuxLPI2C4Rx |
LPI2C4
|
| Dma4RequestMuxLPSPI3Tx |
LPSPI3 Transmit
|
| Dma4RequestMuxLPSPI3Rx |
LPSPI3 Receive
|
| Dma4RequestMuxLPSPI4Tx |
LPSPI4 Transmit
|
| Dma4RequestMuxLPSPI4Rx |
LPSPI4 Receive
|
| Dma4RequestMuxLPTMR2Request |
LPTMR2 Request
|
| Dma4RequestMuxLPUART3Tx |
LPUART3 Transmit
|
| Dma4RequestMuxLPUART3Rx |
LPUART3 Receive
|
| Dma4RequestMuxLPUART4Tx |
LPUART4 Transmit
|
| Dma4RequestMuxLPUART4Rx |
LPUART4 Receive
|
| Dma4RequestMuxLPUART5Tx |
LPUART5 Transmit
|
| Dma4RequestMuxLPUART5Rx |
LPUART5 Receive
|
| Dma4RequestMuxLPUART6Tx |
LPUART6 Transmit
|
| Dma4RequestMuxLPUART6Rx |
LPUART6 Receive
|
| Dma4RequestMuxTPM3Request0Request2 |
TPM3 request 0 and request 2
|
| Dma4RequestMuxTPM3Request1Request3 |
TPM3 request 1 and request 3
|
| Dma4RequestMuxTPM3OverflowRequest |
TPM3 Overflow request
|
| Dma4RequestMuxTPM4Request0Request2 |
TPM4 request 0 and request 2
|
| Dma4RequestMuxTPM4Request1Request3 |
TPM4 request 1 and request 3
|
| Dma4RequestMuxTPM4OverflowRequest |
TPM4 Overflow request
|
| Dma4RequestMuxTPM5Request0Request2 |
TPM5 request 0 and request 2
|
| Dma4RequestMuxTPM5Request1Request3 |
TPM5 request 1 and request 3
|
| Dma4RequestMuxTPM5OverflowRequest |
TPM5 Overflow request
|
| Dma4RequestMuxTPM6Request0Request2 |
TPM6 request 0 and request 2
|
| Dma4RequestMuxTPM6Request1Request3 |
TPM6 request 1 and request 3
|
| Dma4RequestMuxTPM6OverflowRequest |
TPM6 Overflow request
|
| Dma4RequestMuxFlexIO1Request0 |
FlexIO1 Request0
|
| Dma4RequestMuxFlexIO1Request1 |
FlexIO1 Request1
|
| Dma4RequestMuxFlexIO1Request2 |
FlexIO1 Request2
|
| Dma4RequestMuxFlexIO1Request3 |
FlexIO1 Request3
|
| Dma4RequestMuxFlexIO1Request4 |
FlexIO1 Request4
|
| Dma4RequestMuxFlexIO1Request5 |
FlexIO1 Request5
|
| Dma4RequestMuxFlexIO1Request6 |
FlexIO1 Request6
|
| Dma4RequestMuxFlexIO1Request7 |
FlexIO1 Request7
|
| Dma4RequestMuxFlexIO2Request0 |
FlexIO2 Request0
|
| Dma4RequestMuxFlexIO2Request1 |
FlexIO2 Request1
|
| Dma4RequestMuxFlexIO2Request2 |
FlexIO2 Request2
|
| Dma4RequestMuxFlexIO2Request3 |
FlexIO2 Request3
|
| Dma4RequestMuxFlexIO2Request4 |
FlexIO2 Request4
|
| Dma4RequestMuxFlexIO2Request5 |
FlexIO2 Request5
|
| Dma4RequestMuxFlexIO2Request6 |
FlexIO2 Request6
|
| Dma4RequestMuxFlexIO2Request7 |
FlexIO2 Request7
|
| Dma4RequestMuxFlexSPI1Tx |
FlexSPI1 Transmit
|
| Dma4RequestMuxFlexSPI1Rx |
FlexSPI1 Receive
|
| Dma4RequestMuxSai2Tx |
SAI2 Transmit
|
| Dma4RequestMuxSai2Rx |
SAI2 Receive
|
| Dma4RequestMuxSai3Tx |
SAI3 Transmit
|
| Dma4RequestMuxSai3Rx |
SAI3 Receive
|
| Dma4RequestMuxGPIO4Request0 |
GPIO4 channel 0
|
| Dma4RequestMuxGPIO4Request1 |
GPIO4 channel 1
|
| Dma4RequestMuxSPDIFRequest |
SPDIF
|
| Dma4RequestMuxSPDIFRequest1 |
SPDIF
|
| Dma4RequestMuxENETRequest |
ENET
|
| Dma4RequestMuxENETRequest1 |
ENET
|
| Dma4RequestMuxENETRequest2 |
ENET
|
| Dma4RequestMuxENETRequest3 |
ENET
|
| Dma4RequestMuxLPI2C5Tx |
LPI2C5
|
| Dma4RequestMuxLPI2C5Rx |
LPI2C5
|
| Dma4RequestMuxLPI2C6Tx |
LPI2C6
|
| Dma4RequestMuxLPI2C6Rx |
LPI2C6
|
| Dma4RequestMuxLPI2C7Tx |
LPI2C7
|
| Dma4RequestMuxLPI2C7Rx |
LPI2C7
|
| Dma4RequestMuxLPI2C8Tx |
LPI2C8
|
| Dma4RequestMuxLPI2C8Rx |
LPI2C8
|
| Dma4RequestMuxLPSPI5Tx |
LPSPI5 Transmit
|
| Dma4RequestMuxLPSPI5Rx |
LPSPI5 Receive
|
| Dma4RequestMuxLPSPI6Tx |
LPSPI6 Transmit
|
| Dma4RequestMuxLPSPI6Rx |
LPSPI6 Receive
|
| Dma4RequestMuxLPSPI7Tx |
LPSPI7 Transmit
|
| Dma4RequestMuxLPSPI7Rx |
LPSPI7 Receive
|
| Dma4RequestMuxLPSPI8Tx |
LPSPI8 Transmit
|
| Dma4RequestMuxLPSPI8Rx |
LPSPI8 Receive
|
| Dma4RequestMuxLPUART7Tx |
LPUART7 Transmit
|
| Dma4RequestMuxLPUART7Rx |
LPUART7 Receive
|
| Dma4RequestMuxLPUART8Tx |
LPUART8 Transmit
|
| Dma4RequestMuxLPUART8Rx |
LPUART8 Receive
|
| Dma4RequestMuxENET_QOSRequest |
ENET_QOS
|
| Dma4RequestMuxENET_QOSRequest1 |
ENET_QOS
|
| Dma4RequestMuxENET_QOSRequest2 |
ENET_QOS
|
| Dma4RequestMuxENET_QOSRequest3 |
ENET_QOS
|
