The MCUXpresso SDK provides a peripheral driver for the System Reset Controller (SRC) module.
The System Reset Controller (SRC) controls the reset and boot operation of the SoC. It is responsible for the generation of all reset signals and boot decoding. The reset controller determines the source and the type of reset, such as POR, WARM, COLD, and performs the necessary reset qualification and stretching sequences. Based on the type of reset, the reset logic generates the reset sequence for the entire IC.
| Enumerator |
|---|
| kSRC_WarmBootIndicationFlag |
WARM boot indication shows that WARM boot was initiated by software.
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| kSRC_TemperatureSensorResetFlag |
Indicates whether the reset was the result of software reset from on-chip Temperature Sensor.
Temperature Sensor Interrupt needs to be served before this bit can be cleaned.
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| kSRC_JTAGSoftwareResetFlag |
Indicates whether the reset was the result of setting SJC_GPCCR bit 31.
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| kSRC_JTAGGeneratedResetFlag |
Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST or HIGHZ.
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| kSRC_WatchdogResetFlag |
Indicates a reset has been caused by the watchdog timer timing out.
This reset source can be blocked by disabling the watchdog.
|
This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated.
| Enumerator |
|---|
| kSRC_WarmResetWaitAlways |
System will wait until MMDC acknowledge is asserted.
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| kSRC_WarmResetWaitClk16 |
Wait 16 32KHz clock cycles before switching the reset.
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| kSRC_WarmResetWaitClk32 |
Wait 32 32KHz clock cycles before switching the reset.
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| kSRC_WarmResetWaitClk64 |
Wait 64 32KHz clock cycles before switching the reset.
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| static void SRC_EnableWDOGReset |
( |
SRC_Type * |
base, |
|
|
bool |
enable |
|
) |
| |
|
inlinestatic |
WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear that bit is the hardware reset.
- Parameters
-
| base | SRC peripheral base address. |
| enable | Enable the reset or not. |
This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated.
- Parameters
-
| static void SRC_EnableWarmReset |
( |
SRC_Type * |
base, |
|
|
bool |
enable |
|
) |
| |
|
inlinestatic |
Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset. Otherwise, all the WARM reset sources would generate COLD reset.
- Parameters
-
| base | SRC peripheral base address. |
| enable | Enable the WARM reset or not. |
| static uint32_t SRC_GetBootModeWord1 |
( |
SRC_Type * |
base | ) |
|
|
inlinestatic |
The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. See to chip-specific document for detail information about value.
- Parameters
-
| base | SRC peripheral base address. |
- Returns
- status of BOOT_CFGx pins of the chip.
| static uint32_t SRC_GetBootModeWord2 |
( |
SRC_Type * |
base | ) |
|
|
inlinestatic |
The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values that controls boot of the chip. See to chip-specific document for detail information about value.
- Parameters
-
| base | SRC peripheral base address. |
- Returns
- status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
| static void SRC_SetWarmBootIndication |
( |
SRC_Type * |
base, |
|
|
bool |
enable |
|
) |
| |
|
inlinestatic |
WARM boot indication shows that WARM boot was initiated by software. This indicates to the software that it saved the needed information in the memory before initiating the WARM reset. In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot bit should be used as indication only after a warm_reset sequence. Software should clear this bit after warm_reset to indicate that the next warm_reset is not performed with warm_boot.
- Parameters
-
| base | SRC peripheral base address. |
| enable | Assert the flag or not. |
| static uint32_t SRC_GetResetStatusFlags |
( |
SRC_Type * |
base | ) |
|
|
inlinestatic |
| void SRC_ClearResetStatusFlags |
( |
SRC_Type * |
base, |
|
|
uint32_t |
flags |
|
) |
| |
| static void SRC_SetGeneralPurposeRegister |
( |
SRC_Type * |
base, |
|
|
uint32_t |
index, |
|
|
uint32_t |
value |
|
) |
| |
|
inlinestatic |
General purpose registers (GPRx) would hold the value during reset process. Wakeup function could be kept in these register. For example, the GPR1 holds the entry function for waking-up from Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the arbitray values.
- Parameters
-
| base | SRC peripheral base address. |
| index | The index of GPRx register array. Note index 0 reponses the GPR1 register. |
| value | Setting value for GPRx register. |
| static uint32_t SRC_GetGeneralPurposeRegister |
( |
SRC_Type * |
base, |
|
|
uint32_t |
index |
|
) |
| |
|
inlinestatic |
- Parameters
-
| base | SRC peripheral base address. |
| index | The index of GPRx register array. Note index 0 reponses the GPR1 register. |
- Returns
- The setting value for GPRx register.
