Overview

The MCUXpresso SDK provides a driver for the MU module of MCUXpresso SDK devices.

Function description

The MU driver provides these functions:

Functions to initialize the MU module.
Functions to send and receive messages.
Functions for MU flags for both MU sides.
Functions for status flags and interrupts.
Other miscellaneous functions.

MU initialization

The function MU_Init() initializes the MU module and enables the MU clock. It should be called before any other MU functions.
The function MU_Deinit() deinitializes the MU module and disables the MU clock. No MU functions can be called after this function.

MU message

The MU message must be sent when the transmit register is empty. The MU driver provides blocking API and non-blocking API to send message.
The MU_SendMsgNonBlocking() function writes a message to the MU transmit register without checking the transmit register status. The upper layer should check that the transmit register is empty before calling this function. This function can be used in the ISR for better performance.
The MU_SendMsg() function is a blocking function. It waits until the transmit register is empty and sends the message.
Correspondingly, there are blocking and non-blocking APIs for receiving a message. The MU_ReadMsgNonBlocking() function is a non-blocking API. The MU_ReadMsg() function is the blocking API.

MU flags

The MU driver provides 3-bit general purpose flags. When the flags are set on one side, they are reflected on the other side.
The MU flags must be set when the previous flags have been updated to the other side. The MU driver provides a non-blocking function and a blocking function. The blocking function MU_SetFlags() waits until previous flags have been updated to the other side and then sets flags. The non-blocking function sets the flags directly. Ensure that the kMU_FlagsUpdatingFlag is not pending before calling this function.
The function MU_GetFlags() gets the MU flags on the current side.

Status and interrupt

The function MU_GetStatusFlags() returns all MU status flags. Use the _mu_status_flags to check for specific flags, for example, to check RX0 and RX1 register full, use the following code:

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mu The receive full flags are cleared automatically after messages are read out. The transmit empty flags are cleared automatically after new messages are written to the transmit register. The general purpose interrupt flags must be cleared manually using the function MU_ClearStatusFlags().
Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mu To enable or disable a specific interrupt, use MU_EnableInterrupts() and MU_DisableInterrupts() functions. The interrupts to enable or disable should be passed in as a bit mask of the _mu_interrupt_enable.
The MU_TriggerInterrupts() function triggers general purpose interrupts and NMI to the other core. The interrupts to trigger are passed in as a bit mask of the _mu_interrupt_trigger. If previously triggered interrupts have not been processed by the other side, this function returns an error.

MU misc functions

The MU_BootCoreB() and MU_HoldCoreBReset() functions should only be used from A side. They are used to boot the core B or to hold core B in reset.
The MU_ResetBothSides() function resets MU at both A and B sides. However, only the A side can call this function.
If a core enters stop mode, the platform clock of this core is disabled by default. The function MU_SetClockOnOtherCoreEnable() forces the other core's platform clock to remain enabled even after that core has entered a stop mode. In this case, the other core's platform clock keeps running until the current core enters stop mode too.
Function MU_GetOtherCorePowerMode() gets the power mode of the other core.

Typedefs
typedef enum _mu_msg_reg_index	mu_msg_reg_index_t
	MU message register.

Enumerations
enum	_mu_status_flags { kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), kMU_EventPendingFlag = MU_SR_EP_MASK, kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK }
	MU status flags. More...

enum	_mu_interrupt_enable { kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)), kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK }
	MU interrupt source to enable. More...

enum	_mu_interrupt_trigger { kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) }
	MU interrupt that could be triggered to the other core. More...

enum	_mu_msg_reg_index
	MU message register.

Driver version
#define	FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
	MU driver version. More...

MU initialization.
void	MU_Init (MU_Type *base)
	Initializes the MU module. More...

void	MU_Deinit (MU_Type *base)
	De-initializes the MU module. More...

MU Message
static void	MU_SendMsgNonBlocking (MU_Type *base, uint32_t regIndex, uint32_t msg)
	Writes a message to the TX register. More...

void	MU_SendMsg (MU_Type *base, uint32_t regIndex, uint32_t msg)
	Blocks to send a message. More...

static uint32_t	MU_ReceiveMsgNonBlocking (MU_Type *base, uint32_t regIndex)
	Reads a message from the RX register. More...

uint32_t	MU_ReceiveMsg (MU_Type *base, uint32_t regIndex)
	Blocks to receive a message. More...

MU Flags
static void	MU_SetFlagsNonBlocking (MU_Type *base, uint32_t flags)
	Sets the 3-bit MU flags reflect on the other MU side. More...

void	MU_SetFlags (MU_Type *base, uint32_t flags)
	Blocks setting the 3-bit MU flags reflect on the other MU side. More...

static uint32_t	MU_GetFlags (MU_Type *base)
	Gets the current value of the 3-bit MU flags set by the other side. More...

Status and Interrupt.
static uint32_t	MU_GetStatusFlags (MU_Type *base)
	Gets the MU status flags. More...

static uint32_t	MU_GetInterruptsPending (MU_Type *base)
	Gets the MU IRQ pending status. More...

static void	MU_ClearStatusFlags (MU_Type *base, uint32_t mask)
	Clears the specific MU status flags. More...

static void	MU_EnableInterrupts (MU_Type *base, uint32_t mask)
	Enables the specific MU interrupts. More...

static void	MU_DisableInterrupts (MU_Type *base, uint32_t mask)
	Disables the specific MU interrupts. More...

status_t	MU_TriggerInterrupts (MU_Type *base, uint32_t mask)
	Triggers interrupts to the other core. More...

static void	MU_ClearNmi (MU_Type *base)
	Clear non-maskable interrupt (NMI) sent by the other core. More...

MU misc functions
void	MU_BootCoreB (MU_Type *base, mu_core_boot_mode_t mode)
	Boots the core at B side. More...

static void	MU_HoldCoreBReset (MU_Type *base)
	Holds the core reset of B side. More...

void	MU_BootOtherCore (MU_Type *base, mu_core_boot_mode_t mode)
	Boots the other core. More...

static void	MU_HoldOtherCoreReset (MU_Type *base)
	Holds the other core reset. More...

static void	MU_ResetBothSides (MU_Type *base)
	Resets the MU for both A side and B side. More...

static void	MU_MaskHardwareReset (MU_Type *base, bool mask)
	Mask hardware reset by the other core. More...

void	MU_HardwareResetOtherCore (MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)
	Hardware reset the other core. More...

static void	MU_SetClockOnOtherCoreEnable (MU_Type *base, bool enable)
	Enables or disables the clock on the other core. More...

static mu_power_mode_t	MU_GetOtherCorePowerMode (MU_Type *base)
	Gets the power mode of the other core. More...

Macro Definition Documentation

#define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))

Enumeration Type Documentation

enum _mu_status_flags

Enumerator
kMU_Tx0EmptyFlag	TX0 empty.
kMU_Tx1EmptyFlag	TX1 empty.
kMU_Tx2EmptyFlag	TX2 empty.
kMU_Tx3EmptyFlag	TX3 empty.
kMU_Rx0FullFlag	RX0 full.
kMU_Rx1FullFlag	RX1 full.
kMU_Rx2FullFlag	RX2 full.
kMU_Rx3FullFlag	RX3 full.
kMU_GenInt0Flag	General purpose interrupt 0 pending.
kMU_GenInt1Flag	General purpose interrupt 1 pending.
kMU_GenInt2Flag	General purpose interrupt 2 pending.
kMU_GenInt3Flag	General purpose interrupt 3 pending.
kMU_EventPendingFlag	MU event pending.
kMU_FlagsUpdatingFlag	MU flags update is on-going.
kMU_ResetAssertInterruptFlag	The other core reset assert interrupt pending.
kMU_ResetDeassertInterruptFlag	The other core reset de-assert interrupt pending.
kMU_MuResetInterruptFlag	The other side initializes MU reset.
kMU_HardwareResetInterruptFlag	Current side has been hardware reset by the other side.

enum _mu_interrupt_enable

Enumerator
kMU_Tx0EmptyInterruptEnable	TX0 empty.
kMU_Tx1EmptyInterruptEnable	TX1 empty.
kMU_Tx2EmptyInterruptEnable	TX2 empty.
kMU_Tx3EmptyInterruptEnable	TX3 empty.
kMU_Rx0FullInterruptEnable	RX0 full.
kMU_Rx1FullInterruptEnable	RX1 full.
kMU_Rx2FullInterruptEnable	RX2 full.
kMU_Rx3FullInterruptEnable	RX3 full.
kMU_GenInt0InterruptEnable	General purpose interrupt 0.
kMU_GenInt1InterruptEnable	General purpose interrupt 1.
kMU_GenInt2InterruptEnable	General purpose interrupt 2.
kMU_GenInt3InterruptEnable	General purpose interrupt 3.
kMU_ResetAssertInterruptEnable	The other core reset assert interrupt.
kMU_ResetDeassertInterruptEnable	The other core reset de-assert interrupt.
kMU_MuResetInterruptEnable	The other side initializes MU reset. The interrupt is ORed with the general purpose interrupt 3. The general purpose interrupt 3 is issued when the other side set the MU reset and this interrupt is enabled.
kMU_HardwareResetInterruptEnable	Current side has been hardware reset by the other side.

enum _mu_interrupt_trigger

Enumerator
kMU_NmiInterruptTrigger	NMI interrupt.
kMU_GenInt0InterruptTrigger	General purpose interrupt 0.
kMU_GenInt1InterruptTrigger	General purpose interrupt 1.
kMU_GenInt2InterruptTrigger	General purpose interrupt 2.
kMU_GenInt3InterruptTrigger	General purpose interrupt 3.

Function Documentation

void MU_Init ( MU_Type * base )

This function enables the MU clock only.

Parameters

base	MU peripheral base address.

void MU_Deinit ( MU_Type * base )

This function disables the MU clock only.

Parameters

base	MU peripheral base address.

static void MU_SendMsgNonBlocking	(	MU_Type *	base,
		uint32_t	regIndex,
		uint32_t	msg
	)

inlinestatic

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

* while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
* MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.
* 

Parameters

base	MU peripheral base address.
regIndex	TX register index, see mu_msg_reg_index_t.
msg	Message to send.

void MU_SendMsg	(	MU_Type *	base,
		uint32_t	regIndex,
		uint32_t	msg
	)

This function waits until the TX register is empty and sends the message.

Parameters

base	MU peripheral base address.
regIndex	MU message register, see mu_msg_reg_index_t.
msg	Message to send.

static uint32_t MU_ReceiveMsgNonBlocking	(	MU_Type *	base,
		uint32_t	regIndex
	)

inlinestatic

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

* uint32_t msg;
* while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
* {
* }  Wait for the RX0 register full.
*
* msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.
* 

Parameters

base	MU peripheral base address.
regIndex	RX register index, see mu_msg_reg_index_t.

Returns: The received message.

uint32_t MU_ReceiveMsg	(	MU_Type *	base,
		uint32_t	regIndex
	)

This function waits until the RX register is full and receives the message.

Parameters

base	MU peripheral base address.
regIndex	MU message register, see mu_msg_reg_index_t

Returns: The received message.

static void MU_SetFlagsNonBlocking	(	MU_Type *	base,
		uint32_t	flags
	)

inlinestatic

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

* while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
* {
* }  Wait for previous MU flags updating.
*
* MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.
* 

Parameters

base	MU peripheral base address.
flags	The 3-bit MU flags to set.

void MU_SetFlags	(	MU_Type *	base,
		uint32_t	flags
	)

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

Parameters

base	MU peripheral base address.
flags	The 3-bit MU flags to set.

static uint32_t MU_GetFlags ( MU_Type * base )

inlinestatic

This function gets the current 3-bit MU flags on the current side.

Parameters

base	MU peripheral base address.

Returns: flags Current value of the 3-bit flags.

static uint32_t MU_GetStatusFlags ( MU_Type * base )

inlinestatic

This function returns the bit mask of the MU status flags. See _mu_status_flags.

* uint32_t flags;
* flags = MU_GetStatusFlags(base);  Get all status flags.
* if (kMU_Tx0EmptyFlag & flags)
* {
*     The TX0 register is empty. Message can be sent.
*     MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
* }
* if (kMU_Tx1EmptyFlag & flags)
* {
*     The TX1 register is empty. Message can be sent.
*     MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
* }
* 

Parameters

base	MU peripheral base address.

Returns: Bit mask of the MU status flags, see _mu_status_flags.

static uint32_t MU_GetInterruptsPending ( MU_Type * base )

inlinestatic

This function returns the bit mask of the pending MU IRQs.

Parameters

base	MU peripheral base address.

Returns: Bit mask of the MU IRQs pending.

static void MU_ClearStatusFlags	(	MU_Type *	base,
		uint32_t	mask
	)

inlinestatic

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

* Clear general interrupt 0 and general interrupt 1 pending flags.
* MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);
* 

Parameters

base	MU peripheral base address.
mask	Bit mask of the MU status flags. See _mu_status_flags. The following flags are cleared by hardware, this function could not clear them. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_EventPendingFlag kMU_FlagsUpdatingFlag kMU_OtherSideInResetFlag

static void MU_EnableInterrupts	(	MU_Type *	base,
		uint32_t	mask
	)

inlinestatic

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

*    Enable general interrupt 0 and TX0 empty interrupt.
* MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
* 

Parameters

base	MU peripheral base address.
mask	Bit mask of the MU interrupts. See _mu_interrupt_enable.

static void MU_DisableInterrupts	(	MU_Type *	base,
		uint32_t	mask
	)

inlinestatic

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

*    Disable general interrupt 0 and TX0 empty interrupt.
* MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
* 

Parameters

base	MU peripheral base address.
mask	Bit mask of the MU interrupts. See _mu_interrupt_enable.

status_t MU_TriggerInterrupts	(	MU_Type *	base,
		uint32_t	mask
	)

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

* if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
* {
*      Previous general purpose interrupt 0 or general purpose interrupt 2
*      has not been processed by the other core.
* }
* 

Parameters

base	MU peripheral base address.
mask	Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.

Return values

kStatus_Success	Interrupts have been triggered successfully.
kStatus_Fail	Previous interrupts have not been accepted.

static void MU_ClearNmi ( MU_Type * base )

inlinestatic

This function clears non-maskable interrupt (NMI) sent by the other core.

Parameters

base	MU peripheral base address.

void MU_BootCoreB	(	MU_Type *	base,
		mu_core_boot_mode_t	mode
	)

This function sets the B side core's boot configuration and releases the core from reset.

Parameters

base	MU peripheral base address.
mode	Core B boot mode.

Note: Only MU side A can use this function.

static void MU_HoldCoreBReset ( MU_Type * base )

inlinestatic

This function causes the core of B side to be held in reset following any reset event.

Parameters

base	MU peripheral base address.

Note: Only A side could call this function.

void MU_BootOtherCore	(	MU_Type *	base,
		mu_core_boot_mode_t	mode
	)

This function boots the other core with a boot configuration.

Parameters

base	MU peripheral base address.
mode	The other core boot mode.

static void MU_HoldOtherCoreReset ( MU_Type * base )

inlinestatic

This function causes the other core to be held in reset following any reset event.

Parameters

base	MU peripheral base address.

static void MU_ResetBothSides ( MU_Type * base )

inlinestatic

This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.

Parameters

base	MU peripheral base address.

Note: For some platforms, only MU side A could use this function, check reference manual for details.

static void MU_MaskHardwareReset	(	MU_Type *	base,
		bool	mask
	)

inlinestatic

The other core could call MU_HardwareResetOtherCore() to reset current core. To mask the reset, call this function and pass in true.

Parameters

base	MU peripheral base address.
mask	Pass true to mask the hardware reset, pass false to unmask it.

void MU_HardwareResetOtherCore	(	MU_Type *	base,
		bool	waitReset,
		bool	holdReset,
		mu_core_boot_mode_t	bootMode
	)

This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.

Example 1: Reset the other core, and no hold reset

* MU_HardwareResetOtherCore(MU_A, true, false, bootMode);

*

In this example, the core at MU side B will reset with the specified boot mode.

Example 2: Reset the other core and hold it, then boot the other core later.

*  Here the other core enters reset, and the reset is hold
* MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);
*  Current core boot the other core when necessary.
* MU_BootOtherCore(MU_A, bootMode);
* 

Parameters

base	MU peripheral base address.
waitReset	Wait the other core enters reset. true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked. false: Don't wait the reset.
holdReset	Hold the other core reset or not. true: Hold the other core in reset, this function returns directly when the other core enters reset. false: Don't hold the other core in reset, this function waits until the other core out of reset.
bootMode	Boot mode of the other core, if `holdReset` is true, this parameter is useless.

static void MU_SetClockOnOtherCoreEnable	(	MU_Type *	base,
		bool	enable
	)

inlinestatic

This function enables or disables the platform clock on the other core when that core enters a stop mode. If disabled, the platform clock for the other core is disabled when it enters stop mode. If enabled, the platform clock keeps running on the other core in stop mode, until this core also enters stop mode.

Parameters

base	MU peripheral base address.
enable	Enable or disable the clock on the other core.

static mu_power_mode_t MU_GetOtherCorePowerMode ( MU_Type * base )

inlinestatic

This function gets the power mode of the other core.

Parameters

base	MU peripheral base address.

Returns: Power mode of the other core.

Overview

Function description

MU initialization

MU message

MU flags

Status and interrupt

MU misc functions

Typedefs

Enumerations

Driver version

MU initialization.

MU Message

MU Flags

Status and Interrupt.

MU misc functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation