Overview

The MCUXpresso SDK provides a peripheral driver for the Enhanced Quadrature Encoder/Decoder () module of MCUXpresso SDK devices.

This section describes the programming interface of the EQDC Peripheral driver. The EQDC driver configures the EQDC module and provides a functional interface for the user to build the EQDC application.

Function groups

Initialization and De-initialization

This function group initializes default configuration structure for the EQDC counter and initializes EQDC counter with the normal configuration and de-initialize EQDC module. Some APIs are also created to control the features.

Status

This function group get/clear the EQDC status.

Interrupts

This function group enable/disable the EQDC interrupts.

Value Operation

This function group get the counter/hold value of positions.

Typical use case

Polling Configuration

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/eqdc

Data Structures
struct	eqdc_config_t
	Define user configuration structure for EQDC module. More...

Macros
#define	EQDC_CTRL_W1C_FLAGS (EQDC_CTRL_HIRQ_MASK \| EQDC_CTRL_XIRQ_MASK \| EQDC_CTRL_WDIRQ_MASK)
	W1C bits in EQDC CTRL registers. More...

#define	EQDC_INTCTRL_W1C_FLAGS
	W1C bits in EQDC INTCTRL registers. More...

#define	EQDC_CTRL_INT_EN (EQDC_CTRL_HIE_MASK \| EQDC_CTRL_XIE_MASK \| EQDC_CTRL_WDIE_MASK)
	Interrupt enable bits in EQDC CTRL registers. More...

#define	EQDC_INTCTRL_INT_EN
	Interrupt enable bits in EQDC INTCTRL registers. More...

#define	EQDC_CTRL_INT_FLAGS (EQDC_CTRL_HIRQ_MASK \| EQDC_CTRL_XIRQ_MASK \| EQDC_CTRL_WDIRQ_MASK)
	Interrupt flag bits in EQDC CTRL registers. More...

#define	EQDC_INTCTRL_INT_FLAGS
	Interrupt flag bits in EQDC INTCTRL registers. More...

Enumerations
enum	_eqdc_status_flags { kEQDC_HomeEnableTransitionFlag = EQDC_CTRL_HIRQ_MASK, kEQDC_IndexPresetPulseFlag = EQDC_CTRL_XIRQ_MASK, kEQDC_WatchdogTimeoutFlag = EQDC_CTRL_WDIRQ_MASK, kEQDC_SimultPhaseChangeFlag, kEQDC_CountDirectionChangeFlag, kEQDC_PositionRollOverFlag, kEQDC_PositionRollUnderFlag, kEQDC_PositionCompare0Flag, kEQDC_PositionCompare1Flag, kEQDC_PositionCompare2Flag, kEQDC_PositionCompare3Flag }
	EQDC status flags, these flags indicate the counter's events. More...

enum	_eqdc_signal_status { kEQDC_SignalStatusRawHomeEnable = EQDC_IMR_HOME_ENABLE_MASK, kEQDC_SignalStatusRawIndexPreset = EQDC_IMR_INDEX_PRESET_MASK, kEQDC_SignalStatusRawPhaseB = EQDC_IMR_PHB_MASK, kEQDC_SignalStatusRawPhaseA = EQDC_IMR_PHA_MASK, kEQDC_SignalStatusFilteredHomeEnable = EQDC_IMR_FHOM_ENA_MASK, kEQDC_SignalStatusFilteredIndexPreset = EQDC_IMR_FIND_PRE_MASK, kEQDC_SignalStatusFilteredPhaseB = EQDC_IMR_FPHB_MASK, kEQDC_SignalStatusFilteredPhaseA = EQDC_IMR_FPHA_MASK, kEQDC_SignalStatusPositionCompare0Flag = EQDC_IMR_CMPF0_MASK, kEQDC_SignalStatusPositionCompare1Flag = EQDC_IMR_CMP1F_MASK, kEQDC_SignalStatusPositionCompare2Flag = EQDC_IMR_CMP2F_MASK, kEQDC_SignalStatusPositionCompare3Flag = EQDC_IMR_CMP3F_MASK, kEQDC_SignalStatusCountDirectionFlagHold = EQDC_IMR_DIRH_MASK, kEQDC_SignalStatusCountDirectionFlag = EQDC_IMR_DIR_MASK }
	Signal status, these flags indicate the raw and filtered input signal status. More...

enum	_eqdc_interrupt_enable { kEQDC_HomeEnableTransitionInterruptEnable, kEQDC_IndexPresetPulseInterruptEnable = EQDC_CTRL_XIE_MASK, kEQDC_WatchdogTimeoutInterruptEnable = EQDC_CTRL_WDIE_MASK, kEQDC_SimultPhaseChangeInterruptEnable, kEQDC_CountDirectionChangeInterruptEnable, kEQDC_PositionRollOverInterruptEnable = (uint32_t)EQDC_INTCTRL_ROIE_MASK << 16U, kEQDC_PositionRollUnderInterruptEnable, kEQDC_PositionCompare0InterruptEnable, kEQDC_PositionCompare1InterruptEnable, kEQDC_PositionCompare2InterruptEnable, kEQDC_PositionCompare3InterruptEnable }
	Interrupt enable/disable mask. More...

enum	eqdc_home_enable_init_pos_counter_mode_t { kEQDC_HomeInitPosCounterDisabled = 0U, kEQDC_HomeInitPosCounterOnRisingEdge = EQDC_CTRL_HIP_MASK, kEQDC_HomeInitPosCounterOnFallingEdge = EQDC_CTRL_HIP_MASK \| EQDC_CTRL_HNE_MASK }
	Define HOME/ENABLE signal's trigger mode. More...

enum	eqdc_index_preset_init_pos_counter_mode_t { kEQDC_IndexInitPosCounterDisabled = 0U, kEQDC_IndexInitPosCounterOnRisingEdge = EQDC_CTRL_XIP_MASK, kEQDC_IndexInitPosCounterOnFallingEdge = EQDC_CTRL_XIP_MASK \| EQDC_CTRL_XNE_MASK }
	Define INDEX/PRESET signal's trigger mode. More...

enum	eqdc_operate_mode_t { kEQDC_QuadratureDecodeOperationMode = 0U, kEQDC_QuadratureCountOperationMode, kEQDC_SinglePhaseDecodeOperationMode, kEQDC_SinglePhaseCountOperationMode }
	Define type for decoder opertion mode. More...

enum	eqdc_count_mode_t { kEQDC_QuadratureX4 = 0U, kEQDC_QuadratureX2 = 1U, kEQDC_QuadratureX1 = 2U, kEQDC_UpDownPulseCount, kEQDC_SignedCountDoubleEdge, kEQDC_SignedCountSingleEdge }
	Define type for decoder count mode. More...

enum	eqdc_output_pulse_mode_t { kEQDC_OutputPulseOnCounterEqualCompare = 0U, kEQDC_OutputPulseOnReadingPositionCounter }
	Define type for the condition of POSMATCH pulses. More...

enum	eqdc_revolution_count_condition_t { kEQDC_RevolutionCountOnIndexPulse = 0U, kEQDC_RevolutionCountOnRollOverModulus }
	Define type for determining how the revolution counter (REV) is incremented/decremented. More...

enum	eqdc_filter_sample_count_t { kEQDC_Filter3Samples = 0U, kEQDC_Filter4Samples = 1U, kEQDC_Filter5Samples = 2U, kEQDC_Filter6Samples = 3U, kEQDC_Filter7Samples = 4U, kEQDC_Filter8Samples = 5U, kEQDC_Filter9Samples = 6U, kEQDC_Filter10Samples = 7U }
	Input Filter Sample Count. More...

enum	eqdc_count_direction_flag_t { kEQDC_CountDirectionDown = 0U, kEQDC_CountDirectionUp }
	Count direction. More...

enum	eqdc_prescaler_t { kEQDC_Prescaler1 = 0U, kEQDC_Prescaler2 = 1U, kEQDC_Prescaler4 = 2U, kEQDC_Prescaler8 = 3U, kEQDC_Prescaler16 = 4U, kEQDC_Prescaler32 = 5U, kEQDC_Prescaler64 = 6U, kEQDC_Prescaler128 = 7U, kEQDC_Prescaler256 = 8U, kEQDC_Prescaler512 = 9U, kEQDC_Prescaler1024 = 10U, kEQDC_Prescaler2048 = 11U, kEQDC_Prescaler4096 = 12U, kEQDC_Prescaler8192 = 13U, kEQDC_Prescaler16384 = 14U, kEQDC_Prescaler32768 = 15U }
	Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER). More...

Initialization and deinitialization Interfaces
void	EQDC_Init (EQDC_Type base, const eqdc_config_t psConfig)
	Initializes the EQDC module. More...

void	EQDC_GetDefaultConfig (eqdc_config_t *psConfig)
	Gets an available pre-defined configuration. More...

void	EQDC_Deinit (EQDC_Type *base)
	De-initializes the EQDC module. More...

void	EQDC_SetOperateMode (EQDC_Type *base, eqdc_operate_mode_t operateMode)
	Initializes the mode of operation. More...

static void	EQDC_SetCountMode (EQDC_Type *base, eqdc_count_mode_t countMode)
	Initializes the mode of count. More...

Watchdog
static void	EQDC_EnableWatchdog (EQDC_Type *base, bool bEnable)
	Enable watchdog for EQDC module. More...

static void	EQDC_SetWatchdogTimeout (EQDC_Type *base, uint16_t u16Timeout)
	Set watchdog timeout value. More...

DMA
static void	EQDC_EnableDMA (EQDC_Type *base, bool bEnable)
	Enable DMA for EQDC module. More...

Double-set Registers Loading Operation
static void	EQDC_SetBufferedRegisterLoadUpdateMode (EQDC_Type *base)
	Set Buffered Register Load (Update) Mode. More...

static void	EQDC_ClearBufferedRegisterLoadUpdateMode (EQDC_Type *base)
	Clear Buffered Register Load (Update) Mode. More...

static void	EQDC_SetEqdcLdok (EQDC_Type *base)
	Set load okay. More...

static uint8_t	EQDC_GetEqdcLdok (EQDC_Type *base)
	Get load okay. More...

static void	EQDC_ClearEqdcLdok (EQDC_Type *base)
	Clear load okay. More...

Status
static uint32_t	EQDC_GetStatusFlags (EQDC_Type *base)
	Get the status flags. More...

static void	EQDC_ClearStatusFlags (EQDC_Type *base, uint32_t u32Flags)
	Clear the status flags. More...

static uint16_t	EQDC_GetSignalStatusFlags (EQDC_Type *base)
	Get the signals' real-time status. More...

static eqdc_count_direction_flag_t	EQDC_GetLastCountDirection (EQDC_Type *base)
	Get the direction of the last count. More...

Interrupts
static void	EQDC_EnableInterrupts (EQDC_Type *base, uint32_t u32Interrupts)
	Enable the interrupts. More...

static void	EQDC_DisableInterrupts (EQDC_Type *base, uint32_t u32Interrupts)
	Disable the interrupts. More...

Counter Operation
static void	EQDC_DoSoftwareLoadInitialPositionValue (EQDC_Type *base)
	Load the initial position value to position counter. More...

static void	EQDC_SetInitialPositionValue (EQDC_Type *base, uint32_t u32PositionInitValue)
	Set initial position value for EQDC module. More...

static void	EQDC_SetPositionCounterValue (EQDC_Type *base, uint32_t positionCounterValue)
	Set position counter value. More...

static void	EQDC_SetPositionModulusValue (EQDC_Type *base, uint32_t positionModulusValue)
	Set position counter modulus value. More...

static void	EQDC_SetPositionCompare0Value (EQDC_Type *base, uint32_t u32PositionComp0Value)
	Set position counter compare 0 value. More...

static void	EQDC_SetPositionCompare1Value (EQDC_Type *base, uint32_t u32PositionComp1Value)
	Set position counter compare 1 value. More...

static void	EQDC_SetPositionCompare2Value (EQDC_Type *base, uint32_t u32PositionComp2Value)
	Set position counter compare 2 value. More...

static void	EQDC_SetPositionCompare3Value (EQDC_Type *base, uint32_t u32PositionComp3Value)
	Set position counter compare 3 value. More...

static uint32_t	EQDC_GetPosition (EQDC_Type *base)
	Get the current position counter's value. More...

static uint32_t	EQDC_GetHoldPosition (EQDC_Type *base)
	Get the hold position counter's value. More...

static uint32_t	EQDC_GetHoldPosition1 (EQDC_Type *base)
	Get the hold position counter1's value. More...

static uint32_t	EQDC_GetHoldPosition2 (EQDC_Type *base)
	Get the hold position counter2's value. More...

static uint32_t	EQDC_GetHoldPosition3 (EQDC_Type *base)
	Get the hold position counter3's value. More...

static uint16_t	EQDC_GetPositionDifference (EQDC_Type *base)
	Get the position difference counter's value. More...

static uint16_t	EQDC_GetHoldPositionDifference (EQDC_Type *base)
	Get the hold position difference counter's value. More...

static uint16_t	EQDC_GetRevolution (EQDC_Type *base)
	Get the revolution counter's value. More...

static uint16_t	EQDC_GetHoldRevolution (EQDC_Type *base)
	Get the hold revolution counter's value. More...

static uint16_t	EQDC_GetLastEdgeTime (EQDC_Type *base)
	Get the last edge time. More...

static uint16_t	EQDC_GetHoldLastEdgeTime (EQDC_Type *base)
	Get the hold last edge time. More...

static uint16_t	EQDC_GetPositionDifferencePeriod (EQDC_Type *base)
	Get the Position Difference Period counter value. More...

static uint16_t	EQDC_GetBufferedPositionDifferencePeriod (EQDC_Type *base)
	Get buffered Position Difference Period counter value. More...

static uint16_t	EQDC_GetHoldPositionDifferencePeriod (EQDC_Type *base)
	Get Hold Position Difference Period counter value. More...

Data Structure Documentation

struct eqdc_config_t

Data Fields
bool	enableReverseDirection
	Enable reverse direction counting. More...

bool	countOnce
	Selects modulo loop or one shot counting mode. More...

bool	enableDma
	Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)

bool	bufferedRegisterLoadMode
	selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). More...

bool	enableTriggerInitPositionCounter
	Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER's rising edge. More...

bool	enableIndexInitPositionCounter
	Enables the feature that the position counter to be initialized by Index Event Edge Mark. More...

bool	enableTriggerClearPositionRegisters
	Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER's rising edge. More...

bool	enableTriggerHoldPositionRegisters
	Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER's rising edge. More...

bool	filterPhaseA
	Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed. More...

bool	filterPhaseB
	Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed. More...

bool	filterIndPre
	Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed. More...

bool	filterHomEna
	Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed. More...

bool	enableWatchdog
	Enable the watchdog to detect if the target is moving or not. More...

uint16_t	watchdogTimeoutValue
	Watchdog timeout count value. More...

eqdc_prescaler_t	prescaler
	Prescaler. More...

bool	filterClockSourceselection
	Filter Clock Source selection. More...

eqdc_filter_sample_count_t	filterSampleCount
	Input Filter Sample Count. More...

uint8_t	filterSamplePeriod
	Input Filter Sample Period. More...

eqdc_operate_mode_t	operateMode
	Selects operation mode. More...

eqdc_count_mode_t	countMode
	Selects count mode. More...

eqdc_home_enable_init_pos_counter_mode_t	homeEnableInitPosCounterMode
	Select how HOME/Enable signal used to initialize position counters. More...

eqdc_index_preset_init_pos_counter_mode_t	indexPresetInitPosCounterMode
	Select how INDEX/Preset signal used to initialize position counters. More...

eqdc_output_pulse_mode_t	outputPulseMode
	The condition of POSMATCH pulses. More...

uint32_t	positionCompareValue [4]
	Position compare 0 ~ 3 value. More...

eqdc_revolution_count_condition_t	revolutionCountCondition
	Revolution Counter Modulus Enable. More...

uint32_t	positionModulusValue
	Position modulus value. More...

uint32_t	positionInitialValue
	Position initial value. More...

uint32_t	positionCounterValue
	Position counter value. More...

bool	enablePeriodMeasurement
	Enable period measurement. More...

uint16_t	enabledInterruptsMask
	Mask of interrupts to be enabled, should be OR'ed value of _eqdc_interrupt_enable. More...

Field Documentation

bool eqdc_config_t::enableReverseDirection

bool eqdc_config_t::countOnce

bool eqdc_config_t::bufferedRegisterLoadMode

bool eqdc_config_t::enableTriggerInitPositionCounter

bool eqdc_config_t::enableIndexInitPositionCounter

This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:

When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.

When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.

bool eqdc_config_t::enableTriggerClearPositionRegisters

bool eqdc_config_t::enableTriggerHoldPositionRegisters

bool eqdc_config_t::filterPhaseA

bool eqdc_config_t::filterPhaseB

bool eqdc_config_t::filterIndPre

bool eqdc_config_t::filterHomEna

bool eqdc_config_t::enableWatchdog

uint16_t eqdc_config_t::watchdogTimeoutValue

It stores the timeout count for the quadrature decoder module watchdog timer.

eqdc_prescaler_t eqdc_config_t::prescaler

bool eqdc_config_t::filterClockSourceselection

eqdc_filter_sample_count_t eqdc_config_t::filterSampleCount

This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.

uint8_t eqdc_config_t::filterSamplePeriod

This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

eqdc_operate_mode_t eqdc_config_t::operateMode

eqdc_count_mode_t eqdc_config_t::countMode

eqdc_home_enable_init_pos_counter_mode_t eqdc_config_t::homeEnableInitPosCounterMode

eqdc_index_preset_init_pos_counter_mode_t eqdc_config_t::indexPresetInitPosCounterMode

eqdc_output_pulse_mode_t eqdc_config_t::outputPulseMode

uint32_t eqdc_config_t::positionCompareValue[4]

The available value is a 32-bit number.

eqdc_revolution_count_condition_t eqdc_config_t::revolutionCountCondition

uint32_t eqdc_config_t::positionModulusValue

The available value is a 32-bit number.

uint32_t eqdc_config_t::positionInitialValue

The available value is a 32-bit number.

uint32_t eqdc_config_t::positionCounterValue

When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.

bool eqdc_config_t::enablePeriodMeasurement

When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.

uint16_t eqdc_config_t::enabledInterruptsMask

Macro Definition Documentation

#define EQDC_CTRL_W1C_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)

#define EQDC_INTCTRL_W1C_FLAGS

Value:

(EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \

EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK)

#define EQDC_CTRL_INT_EN (EQDC_CTRL_HIE_MASK | EQDC_CTRL_XIE_MASK | EQDC_CTRL_WDIE_MASK)

#define EQDC_INTCTRL_INT_EN

Value:

(EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK | \

EQDC_INTCTRL_CMP0IE_MASK | EQDC_INTCTRL_CMP1IE_MASK | EQDC_INTCTRL_CMP2IE_MASK | EQDC_INTCTRL_CMP3IE_MASK)

#define EQDC_CTRL_INT_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)

#define EQDC_INTCTRL_INT_FLAGS

Value:

(EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \

EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK)

Enumeration Type Documentation

enum _eqdc_status_flags

Enumerator
kEQDC_HomeEnableTransitionFlag	HOME/ENABLE signal transition occured.
kEQDC_IndexPresetPulseFlag	INDEX/PRESET pulse occured.
kEQDC_WatchdogTimeoutFlag	Watchdog timeout occured.
kEQDC_SimultPhaseChangeFlag	Simultaneous change of PHASEA and PHASEB occured.
kEQDC_CountDirectionChangeFlag	Count direction change interrupt enable.
kEQDC_PositionRollOverFlag	Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.
kEQDC_PositionRollUnderFlag	Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.
kEQDC_PositionCompare0Flag	Position counter match the COMP0 value.
kEQDC_PositionCompare1Flag	Position counter match the COMP1 value.
kEQDC_PositionCompare2Flag	Position counter match the COMP2 value.
kEQDC_PositionCompare3Flag	Position counter match the COMP3 value.

enum _eqdc_signal_status

Enumerator
kEQDC_SignalStatusRawHomeEnable	Raw HOME/ENABLE input.
kEQDC_SignalStatusRawIndexPreset	Raw INDEX/PRESET input.
kEQDC_SignalStatusRawPhaseB	Raw PHASEB input.
kEQDC_SignalStatusRawPhaseA	Raw PHASEA input.
kEQDC_SignalStatusFilteredHomeEnable	The filtered HOME/ENABLE input.
kEQDC_SignalStatusFilteredIndexPreset	The filtered INDEX/PRESET input.
kEQDC_SignalStatusFilteredPhaseB	The filtered PHASEB input.
kEQDC_SignalStatusFilteredPhaseA	The filtered PHASEA input.
kEQDC_SignalStatusPositionCompare0Flag	Position Compare 0 Flag Output.
kEQDC_SignalStatusPositionCompare1Flag	Position Compare 1 Flag Output.
kEQDC_SignalStatusPositionCompare2Flag	Position Compare 2 Flag Output.
kEQDC_SignalStatusPositionCompare3Flag	Position Compare 3 Flag Output.
kEQDC_SignalStatusCountDirectionFlagHold	Count Direction Flag Hold.
kEQDC_SignalStatusCountDirectionFlag	Count Direction Flag Output.

enum _eqdc_interrupt_enable

Enumerator
kEQDC_HomeEnableTransitionInterruptEnable	HOME/ENABLE signal transition interrupt enable.
kEQDC_IndexPresetPulseInterruptEnable	INDEX/PRESET pulse interrupt enable.
kEQDC_WatchdogTimeoutInterruptEnable	Watchdog timeout interrupt enable.
kEQDC_SimultPhaseChangeInterruptEnable	Simultaneous PHASEA and PHASEB change interrupt enable.
kEQDC_CountDirectionChangeInterruptEnable	Count direction change interrupt enable.
kEQDC_PositionRollOverInterruptEnable	Roll-over interrupt enable.
kEQDC_PositionRollUnderInterruptEnable	Roll-under interrupt enable.
kEQDC_PositionCompare0InterruptEnable	Position compare 0 interrupt enable.
kEQDC_PositionCompare1InterruptEnable	Position compare 1 interrupt enable.
kEQDC_PositionCompare2InterruptEnable	Position compare 2 interrupt enable.
kEQDC_PositionCompare3InterruptEnable	Position compare 3 interrupt enable.

enum eqdc_home_enable_init_pos_counter_mode_t

Enumerator
kEQDC_HomeInitPosCounterDisabled	Don't use HOME/ENABLE signal to initialize the position counter.
kEQDC_HomeInitPosCounterOnRisingEdge	Use positive going edge to trigger initialization of position counters.
kEQDC_HomeInitPosCounterOnFallingEdge	Use negative going edge to trigger initialization of position counters.

enum eqdc_index_preset_init_pos_counter_mode_t

Enumerator
kEQDC_IndexInitPosCounterDisabled	INDEX/PRESET pulse does not initialize the position counter.
kEQDC_IndexInitPosCounterOnRisingEdge	Use INDEX/PRESET pulse rising edge to initialize position counter.
kEQDC_IndexInitPosCounterOnFallingEdge	Use INDEX/PRESET pulse falling edge to initialize position counter.

enum eqdc_operate_mode_t

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

Enumerator
kEQDC_QuadratureDecodeOperationMode	Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.
kEQDC_QuadratureCountOperationMode	Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.
kEQDC_SinglePhaseDecodeOperationMode	Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.
kEQDC_SinglePhaseCountOperationMode	Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.

enum eqdc_count_mode_t

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

Enumerator
kEQDC_QuadratureX4	Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
kEQDC_QuadratureX2	Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
kEQDC_QuadratureX1	Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
kEQDC_UpDownPulseCount	Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.
kEQDC_SignedCountDoubleEdge	Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.
kEQDC_SignedCountSingleEdge	Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enum eqdc_output_pulse_mode_t

Enumerator
kEQDC_OutputPulseOnCounterEqualCompare	POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).
kEQDC_OutputPulseOnReadingPositionCounter	POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).

enum eqdc_revolution_count_condition_t

Enumerator
kEQDC_RevolutionCountOnIndexPulse	Use INDEX pulse to increment/decrement revolution counter.
kEQDC_RevolutionCountOnRollOverModulus	Use modulus counting roll-over/under to increment/decrement revolution counter.

enum eqdc_filter_sample_count_t

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

Enumerator
kEQDC_Filter3Samples	3 samples.
kEQDC_Filter4Samples	4 samples.
kEQDC_Filter5Samples	5 samples.
kEQDC_Filter6Samples	6 samples.
kEQDC_Filter7Samples	7 samples.
kEQDC_Filter8Samples	8 samples.
kEQDC_Filter9Samples	9 samples.
kEQDC_Filter10Samples	10 samples.

enum eqdc_count_direction_flag_t

Enumerator
kEQDC_CountDirectionDown	Last count was in down direction.
kEQDC_CountDirectionUp	Last count was in up direction.

enum eqdc_prescaler_t

Enumerator
kEQDC_Prescaler1	Prescaler value 1.
kEQDC_Prescaler2	Prescaler value 2.
kEQDC_Prescaler4	Prescaler value 4.
kEQDC_Prescaler8	Prescaler value 8.
kEQDC_Prescaler16	Prescaler value 16.
kEQDC_Prescaler32	Prescaler value 32.
kEQDC_Prescaler64	Prescaler value 64.
kEQDC_Prescaler128	Prescaler value 128.
kEQDC_Prescaler256	Prescaler value 256.
kEQDC_Prescaler512	Prescaler value 512.
kEQDC_Prescaler1024	Prescaler value 1024.
kEQDC_Prescaler2048	Prescaler value 2048.
kEQDC_Prescaler4096	Prescaler value 4096.
kEQDC_Prescaler8192	Prescaler value 8192.
kEQDC_Prescaler16384	Prescaler value 16384.
kEQDC_Prescaler32768	Prescaler value 32768.

Function Documentation

void EQDC_Init	(	EQDC_Type *	base,
		const eqdc_config_t *	psConfig
	)

This function initializes the EQDC by enabling the IP bus clock (optional).

Parameters

base	EQDC peripheral base address.
psConfig	Pointer to configuration structure.

void EQDC_GetDefaultConfig ( eqdc_config_t * psConfig )

The default value are:

psConfig->enableReverseDirection              = false;
psConfig->countOnce                           = false;
psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
psConfig->countMode                           = kEQDC_QuadratureX4;
psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
psConfig->enableIndexInitPositionCounter      = false;
psConfig->enableDma                           = false;
psConfig->bufferedRegisterLoadMode            = false;
psConfig->enableTriggerInitPositionCounter    = false;
psConfig->enableTriggerClearPositionRegisters = false;
psConfig->enableTriggerHoldPositionRegisters  = false;
psConfig->enableWatchdog                      = false;
psConfig->watchdogTimeoutValue                = 0xFFFFU;
psConfig->filterPhaseA                        = 0U;
psConfig->filterPhaseB                        = 0U;
psConfig->filterIndPre                        = 0U;
psConfig->filterHomEna                        = 0U;
psConfig->filterClockSourceselection          = false;
psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
psConfig->filterSamplePeriod                  = 0U;
psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
psConfig->positionCompareValue[0]                = 0xFFFFFFFFU;
psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
psConfig->positionModulusValue                = 0U;
psConfig->positionInitialValue                = 0U;
psConfig->positionCounterValue                = 0U;
psConfig->enablePeriodMeasurement             = false;
psConfig->prescaler                           = kEQDC_Prescaler1;
psConfig->enabledInterruptsMask               = 0U;

Parameters

psConfig Pointer to configuration structure.

void EQDC_Deinit ( EQDC_Type * base )

This function deinitializes the EQDC by disabling the IP bus clock (optional).

Parameters

base	EQDC peripheral base address.

void EQDC_SetOperateMode	(	EQDC_Type *	base,
		eqdc_operate_mode_t	operateMode
	)

This function initializes mode of operation by enabling the IP bus clock (optional).

Parameters

base	EQDC peripheral base address.
operateMode	Select operation mode.

static void EQDC_SetCountMode	(	EQDC_Type *	base,
		eqdc_count_mode_t	countMode
	)

inlinestatic

These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved

Parameters

base	EQDC peripheral base address.
countMode	Select count mode.

static void EQDC_EnableWatchdog	(	EQDC_Type *	base,
		bool	bEnable
	)

inlinestatic

Parameters

base	EQDC peripheral base address
bEnable	Enables or disables the watchdog

static void EQDC_SetWatchdogTimeout	(	EQDC_Type *	base,
		uint16_t	u16Timeout
	)

inlinestatic

Parameters

base	EQDC peripheral base address
u16Timeout	Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out

static void EQDC_EnableDMA	(	EQDC_Type *	base,
		bool	bEnable
	)

inlinestatic

Parameters

base	EQDC peripheral base address
bEnable	Enables or disables the DMA

static void EQDC_SetBufferedRegisterLoadUpdateMode ( EQDC_Type * base )

inlinestatic

This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address

static void EQDC_ClearBufferedRegisterLoadUpdateMode ( EQDC_Type * base )

inlinestatic

Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address

static void EQDC_SetEqdcLdok ( EQDC_Type * base )

inlinestatic

Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.

Parameters

base	EQDC peripheral base address.

static uint8_t EQDC_GetEqdcLdok ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

static void EQDC_ClearEqdcLdok ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

static uint32_t EQDC_GetStatusFlags ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

Returns: Logical OR'ed value of the status flags, _eqdc_status_flags.

static void EQDC_ClearStatusFlags	(	EQDC_Type *	base,
		uint32_t	u32Flags
	)

inlinestatic

Parameters

base	EQDC peripheral base address.
u32Flags	Logical OR'ed value of the flags to clear, _eqdc_status_flags.

static uint16_t EQDC_GetSignalStatusFlags ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

Returns: Logical OR'ed value of the real-time signal status, _eqdc_signal_status.

static eqdc_count_direction_flag_t EQDC_GetLastCountDirection ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

Returns: Direction of the last count.

static void EQDC_EnableInterrupts	(	EQDC_Type *	base,
		uint32_t	u32Interrupts
	)

inlinestatic

Parameters

base	EQDC peripheral base address.
u32Interrupts	Logical OR'ed value of the interrupts, _eqdc_interrupt_enable.

static void EQDC_DisableInterrupts	(	EQDC_Type *	base,
		uint32_t	u32Interrupts
	)

inlinestatic

Parameters

base	EQDC peripheral base address.
u32Interrupts	Logical OR'ed value of the interrupts, _eqdc_interrupt_enable.

static void EQDC_DoSoftwareLoadInitialPositionValue ( EQDC_Type * base )

inlinestatic

Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters

base	EQDC peripheral base address.

static void EQDC_SetInitialPositionValue	(	EQDC_Type *	base,
		uint32_t	u32PositionInitValue
	)

inlinestatic

Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
u32PositionInitValue	Position initial value

static void EQDC_SetPositionCounterValue	(	EQDC_Type *	base,
		uint32_t	positionCounterValue
	)

inlinestatic

Set the position counter value (POS or UPOS, LPOS).

Parameters

base	EQDC peripheral base address
positionCounterValue	Position counter value

static void EQDC_SetPositionModulusValue	(	EQDC_Type *	base,
		uint32_t	positionModulusValue
	)

inlinestatic

Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
positionModulusValue	Position modulus value

static void EQDC_SetPositionCompare0Value	(	EQDC_Type *	base,
		uint32_t	u32PositionComp0Value
	)

inlinestatic

Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
u32PositionComp0Value	Position modulus value

static void EQDC_SetPositionCompare1Value	(	EQDC_Type *	base,
		uint32_t	u32PositionComp1Value
	)

inlinestatic

Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
u32PositionComp1Value	Position modulus value

static void EQDC_SetPositionCompare2Value	(	EQDC_Type *	base,
		uint32_t	u32PositionComp2Value
	)

inlinestatic

Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
u32PositionComp2Value	Position modulus value

static void EQDC_SetPositionCompare3Value	(	EQDC_Type *	base,
		uint32_t	u32PositionComp3Value
	)

inlinestatic

Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are "buffered" into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters

base	EQDC peripheral base address
u32PositionComp3Value	Position modulus value

static uint32_t EQDC_GetPosition ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

Returns: Current position counter's value.

static uint32_t EQDC_GetHoldPosition ( EQDC_Type * base )

inlinestatic

The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters

base	EQDC peripheral base address.

Returns: Hold position counter's value.

static uint32_t EQDC_GetHoldPosition1 ( EQDC_Type * base )

inlinestatic

The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].

Parameters

base	EQDC peripheral base address.

Returns: Hold position counter1's value.

static uint32_t EQDC_GetHoldPosition2 ( EQDC_Type * base )

inlinestatic

The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].

Parameters

base	EQDC peripheral base address.

Returns: Hold position counter2's value.

static uint32_t EQDC_GetHoldPosition3 ( EQDC_Type * base )

inlinestatic

The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].

Parameters

base	EQDC peripheral base address.

Returns: Hold position counter3's value.

static uint16_t EQDC_GetPositionDifference ( EQDC_Type * base )

inlinestatic

Parameters

base	EQDC peripheral base address.

Returns: The position difference counter's value.

static uint16_t EQDC_GetHoldPositionDifference ( EQDC_Type * base )

inlinestatic

The position difference (POSD) value is loaded to hold position difference (POSDH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters

base	EQDC peripheral base address.

Returns: Hold position difference counter's value.

static uint16_t EQDC_GetRevolution ( EQDC_Type * base )

inlinestatic

Get the revolution counter (REV) value.

Parameters

base	EQDC peripheral base address.

Returns: The revolution counter's value.

static uint16_t EQDC_GetHoldRevolution ( EQDC_Type * base )

inlinestatic

The revolution counter (REV) value is loaded to hold revolution (REVH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters

base	EQDC peripheral base address.

Returns: Hold position revolution counter's value.

static uint16_t EQDC_GetLastEdgeTime ( EQDC_Type * base )

inlinestatic

Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters

base	EQDC peripheral base address.

Returns: The last edge time.

static uint16_t EQDC_GetHoldLastEdgeTime ( EQDC_Type * base )

inlinestatic

The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.

Parameters

base	EQDC peripheral base address.

Returns: Hold of last edge time.

static uint16_t EQDC_GetPositionDifferencePeriod ( EQDC_Type * base )

inlinestatic

The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters

base	EQDC peripheral base address.

Returns: The position difference period counter value.

static uint16_t EQDC_GetBufferedPositionDifferencePeriod ( EQDC_Type * base )

inlinestatic

The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.

Parameters

base	EQDC peripheral base address.

Returns: The buffered position difference period counter value.

static uint16_t EQDC_GetHoldPositionDifferencePeriod ( EQDC_Type * base )

inlinestatic

The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.

Parameters

base	EQDC peripheral base address.

Returns: The hold position difference period counter value.

Overview

Function groups

Initialization and De-initialization

Status

Interrupts

Value Operation

Typical use case

Polling Configuration

Data Structures

Macros

Enumerations

Initialization and deinitialization Interfaces

Watchdog

DMA

Double-set Registers Loading Operation

Status

Interrupts

Counter Operation

Data Structure Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation