Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	clock_arm_pll_config_t
	PLL configuration for ARM. More...

struct	clock_usb_pll_config_t
	PLL configuration for USB. More...

struct	clock_pll_ss_config_t
	Spread specturm configure Pll. More...

struct	clock_sys_pll2_config_t
	PLL configure for Sys Pll2. More...

struct	clock_sys_pll1_config_t
	PLL configure for Sys Pll1. More...

struct	clock_audio_pll_config_t
	PLL configuration for AUDIO. More...

struct	clock_root_config_t
	Clock root configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CCSR_OFFSET 0x0C
	CCM registers offset.

#define	ARM_PLL_OFFSET 0x00
	CCM Analog registers offset.

#define	CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) \| (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.

#define	PLL_SYS1_1G_FREQ (1000000000UL)
	SYS_PLL_FREQ frequency in Hz.

#define	LPADC_CLOCKS
	Clock gate name array for LPADC. More...

#define	AOI_CLOCKS
	Clock gate name array for AOI. More...

#define	ASRC_CLOCKS
	Clock ip name array for ASRC. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	DCDC_CLOCKS
	Clock gate name array for DCDC. More...

#define	ECAT_CLOCKS
	Clock ip name array for ECAT. More...

#define	EDMA_CLOCKS
	Clock gate name array for EDMA. More...

#define	ENC_CLOCKS
	Clock ip name array for ENC. More...

#define	EWM_CLOCKS
	Clock gate name array for EWM. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	FLEXSPI_CLOCKS
	Clock gate name array for FLEXSPI. More...

#define	FLEXSPI_SLV_CLOCKS
	Clock gate name array for FLEXSPI_SLV. More...

#define	GPC_CLOCKS
	Clock gate name array for GPC. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	GPT_CLOCKS
	Clock ip name array for GPT. More...

#define	I3C_CLOCKS
	Clock ip name array for I3C. More...

#define	IEE_CLOCKS
	Clock ip name array for IEE. More...

#define	KPP_CLOCKS
	Clock ip name array for KPP. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	LPTMR_CLOCKS
	Clock ip name array for LPTMR. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	PDM_CLOCKS
	Clock ip name array for MIC. More...

#define	MU_CLOCKS
	Clock gate name array for MU. More...

#define	NETC_CLOCKS
	Clock ip name array for NETC. More...

#define	OCOTP_CLOCKS
	Clock ip name array for OCOTP. More...

#define	PWM_CLOCKS
	Clock ip name array for PWM. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	SEMA42_CLOCKS
	Clock gate name array for Sema. More...

#define	SEMC_CLOCKS
	Clock ip name array for SEMC. More...

#define	SERDES_CLOCKS
	Clock ip name array for SERDES. More...

#define	SINC_CLOCKS
	Clock ip name array for SINC. More...

#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...

#define	SRC_CLOCKS
	Clock gate name array for SRC. More...

#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...

#define	TPM_CLOCKS
	Clock ip name array for TPM. More...

#define	USB_CLOCKS
	Clock ip name array for USB. More...

#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...

#define	WDOG_CLOCKS
	Clock gate name array for WDOG. More...

#define	XBAR_CLOCKS
	Clock ip name array for XBAR. More...

#define	CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
	For compatible with other platforms without CCM. More...

Enumerations
enum	clock_lpcg_t { kCLOCK_M7 = 0, kCLOCK_M33 = 1, kCLOCK_Edgelock = 2, kCLOCK_Sim_Aon = 3, kCLOCK_Sim_Wakeup = 4, kCLOCK_Sim_Mega = 5, kCLOCK_Sim_R = 6, kCLOCK_Anadig = 7, kCLOCK_Dcdc = 8, kCLOCK_Src = 9, kCLOCK_Ccm = 10, kCLOCK_Gpc = 11, kCLOCK_Adc1 = 12, kCLOCK_Adc2 = 13, kCLOCK_Dac = 14, kCLOCK_Acmp1 = 15, kCLOCK_Acmp2 = 16, kCLOCK_Acmp3 = 17, kCLOCK_Acmp4 = 18, kCLOCK_Wdog1 = 19, kCLOCK_Wdog2 = 20, kCLOCK_Wdog3 = 21, kCLOCK_Wdog4 = 22, kCLOCK_Wdog5 = 23, kCLOCK_Ewm0 = 24, kCLOCK_Sema1 = 25, kCLOCK_Sema2 = 26, kCLOCK_Mu_A = 27, kCLOCK_Mu_B = 28, kCLOCK_Edma3 = 29, kCLOCK_Edma4 = 30, kCLOCK_Romcp = 31, kCLOCK_Ocram1 = 32, kCLOCK_Ocram2 = 33, kCLOCK_Flexspi1 = 34, kCLOCK_Flexspi2 = 35, kCLOCK_Flexspi_Slv = 36, kCLOCK_Trdc = 37, kCLOCK_Ocotp = 38, kCLOCK_Semc = 39, kCLOCK_Iee = 40, kCLOCK_Cstrace = 41, kCLOCK_Csswo = 42, kCLOCK_Iomuxc1 = 43, kCLOCK_Iomuxc2 = 44, kCLOCK_Gpio1 = 45, kCLOCK_Gpio2 = 46, kCLOCK_Gpio3 = 47, kCLOCK_Gpio4 = 48, kCLOCK_Gpio5 = 49, kCLOCK_Gpio6 = 50, kCLOCK_Flexio1 = 51, kCLOCK_Flexio2 = 52, kCLOCK_Lpit1 = 53, kCLOCK_Lpit2 = 54, kCLOCK_Lpit3 = 55, kCLOCK_Lptmr1 = 56, kCLOCK_Lptmr2 = 57, kCLOCK_Lptmr3 = 58, kCLOCK_Tpm1 = 59, kCLOCK_Tpm2 = 60, kCLOCK_Tpm3 = 61, kCLOCK_Tpm4 = 62, kCLOCK_Tpm5 = 63, kCLOCK_Tpm6 = 64, kCLOCK_Qtimer1 = 65, kCLOCK_Qtimer2 = 66, kCLOCK_Qtimer3 = 67, kCLOCK_Qtimer4 = 68, kCLOCK_Qtimer5 = 69, kCLOCK_Qtimer6 = 70, kCLOCK_Qtimer7 = 71, kCLOCK_Qtimer8 = 72, kCLOCK_Gpt1 = 73, kCLOCK_Gpt2 = 74, kCLOCK_Syscount = 75, kCLOCK_Can1 = 76, kCLOCK_Can2 = 77, kCLOCK_Can3 = 78, kCLOCK_Lpuart1 = 79, kCLOCK_Lpuart2 = 80, kCLOCK_Lpuart3 = 81, kCLOCK_Lpuart4 = 82, kCLOCK_Lpuart5 = 83, kCLOCK_Lpuart6 = 84, kCLOCK_Lpuart7 = 85, kCLOCK_Lpuart8 = 86, kCLOCK_Lpuart9 = 87, kCLOCK_Lpuart10 = 88, kCLOCK_Lpuart11 = 89, kCLOCK_Lpuart12 = 90, kCLOCK_Lpi2c1 = 91, kCLOCK_Lpi2c2 = 92, kCLOCK_Lpi2c3 = 93, kCLOCK_Lpi2c4 = 94, kCLOCK_Lpi2c5 = 95, kCLOCK_Lpi2c6 = 96, kCLOCK_Lpspi1 = 97, kCLOCK_Lpspi2 = 98, kCLOCK_Lpspi3 = 99, kCLOCK_Lpspi4 = 100, kCLOCK_Lpspi5 = 101, kCLOCK_Lpspi6 = 102, kCLOCK_I3c1 = 103, kCLOCK_I3c2 = 104, kCLOCK_Usdhc1 = 105, kCLOCK_Usdhc2 = 106, kCLOCK_Usb = 107, kCLOCK_Sinc1 = 108, kCLOCK_Sinc2 = 109, kCLOCK_Sinc3 = 110, kCLOCK_Xbar1 = 111, kCLOCK_Xbar2 = 112, kCLOCK_Xbar3 = 113, kCLOCK_Aoi1 = 114, kCLOCK_Aoi2 = 115, kCLOCK_Aoi3 = 116, kCLOCK_Aoi4 = 117, kCLOCK_Enc1 = 118, kCLOCK_Enc2 = 119, kCLOCK_Enc3 = 120, kCLOCK_Enc4 = 121, kCLOCK_Kpp = 122, kCLOCK_Pwm1 = 123, kCLOCK_Pwm2 = 124, kCLOCK_Pwm3 = 125, kCLOCK_Pwm4 = 126, kCLOCK_Ecat = 127, kCLOCK_Netc = 128, kCLOCK_Serdes1 = 129, kCLOCK_Serdes2 = 130, kCLOCK_Serdes3 = 131, kCLOCK_Xcelbusx = 132, kCLOCK_Xriocu4 = 133, kCLOCK_Sptp = 134, kCLOCK_Mctrl = 135, kCLOCK_Sai1 = 136, kCLOCK_Sai2 = 137, kCLOCK_Sai3 = 138, kCLOCK_Sai4 = 139, kCLOCK_Spdif = 140, kCLOCK_Asrc = 141, kCLOCK_Pdm = 142, kCLOCK_Vref = 143, kCLOCK_Bist = 144, kCLOCK_Ssi_W2M7 = 145, kCLOCK_Ssi_M72W = 146, kCLOCK_Ssi_W2Ao = 147, kCLOCK_Ssi_Ao2W = 148, kCLOCK_IpInvalid }
	Clock LPCG index. More...

enum	clock_name_t { kCLOCK_OscRc24M = 0, kCLOCK_OscRc400M = 1, kCLOCK_Osc24M = 2, kCLOCK_Osc24MOut = 3, kCLOCK_ArmPll = 4, kCLOCK_ArmPllOut = 5, kCLOCK_SysPll2 = 6, kCLOCK_SysPll2Out = 7, kCLOCK_SysPll2Pfd0 = 8, kCLOCK_SysPll2Pfd1 = 9, kCLOCK_SysPll2Pfd2 = 10, kCLOCK_SysPll2Pfd3 = 11, kCLOCK_SysPll3 = 12, kCLOCK_SysPll3Out = 13, kCLOCK_SysPll3Div2 = 14, kCLOCK_SysPll3Pfd0 = 15, kCLOCK_SysPll3Pfd1 = 16, kCLOCK_SysPll3Pfd2 = 17, kCLOCK_SysPll3Pfd3 = 18, kCLOCK_SysPll1 = 19, kCLOCK_SysPll1Out = 20, kCLOCK_SysPll1Div2 = 21, kCLOCK_SysPll1Div5 = 22, kCLOCK_AudioPll = 23, kCLOCK_AudioPllOut = 24, kCLOCK_CpuClk, kCLOCK_CoreSysClk }
	Clock name. More...

enum	clock_root_t { kCLOCK_Root_M7 = 0, kCLOCK_Root_M33 = 1, kCLOCK_Root_Edgelock = 2, kCLOCK_Root_Bus_Aon = 3, kCLOCK_Root_Bus_Wakeup = 4, kCLOCK_Root_Wakeup_Axi = 5, kCLOCK_Root_Swo_Trace = 6, kCLOCK_Root_M33_Systick = 7, kCLOCK_Root_M7_Systick = 8, kCLOCK_Root_Flexio1 = 9, kCLOCK_Root_Flexio2 = 10, kCLOCK_Root_Lpit3 = 11, kCLOCK_Root_Lptimer1 = 12, kCLOCK_Root_Lptimer2 = 13, kCLOCK_Root_Lptimer3 = 14, kCLOCK_Root_Tpm2 = 15, kCLOCK_Root_Tpm4 = 16, kCLOCK_Root_Tpm5 = 17, kCLOCK_Root_Tpm6 = 18, kCLOCK_Root_Gpt1 = 19, kCLOCK_Root_Gpt2 = 20, kCLOCK_Root_Flexspi1 = 21, kCLOCK_Root_Flexspi2 = 22, kCLOCK_Root_Flexspi_Slv = 23, kCLOCK_Root_Can1 = 24, kCLOCK_Root_Can2 = 25, kCLOCK_Root_Can3 = 26, kCLOCK_Root_Lpuart0102 = 27, kCLOCK_Root_Lpuart0304 = 28, kCLOCK_Root_Lpuart0506 = 29, kCLOCK_Root_Lpuart0708 = 30, kCLOCK_Root_Lpuart0910 = 31, kCLOCK_Root_Lpuart1112 = 32, kCLOCK_Root_Lpi2c0102 = 33, kCLOCK_Root_Lpi2c0304 = 34, kCLOCK_Root_Lpi2c0506 = 35, kCLOCK_Root_Lpspi0102 = 36, kCLOCK_Root_Lpspi0304 = 37, kCLOCK_Root_Lpspi0506 = 38, kCLOCK_Root_I3c1 = 39, kCLOCK_Root_I3c2 = 40, kCLOCK_Root_Usdhc1 = 41, kCLOCK_Root_Usdhc2 = 42, kCLOCK_Root_Semc = 43, kCLOCK_Root_Adc1 = 44, kCLOCK_Root_Adc2 = 45, kCLOCK_Root_Acmp = 46, kCLOCK_Root_Ecat = 47, kCLOCK_Root_Enet = 48, kCLOCK_Root_Tmr_1588 = 49, kCLOCK_Root_Netc = 50, kCLOCK_Root_Mac0 = 51, kCLOCK_Root_Mac1 = 52, kCLOCK_Root_Mac2 = 53, kCLOCK_Root_Mac3 = 54, kCLOCK_Root_Mac4 = 55, kCLOCK_Root_Serdes0 = 56, kCLOCK_Root_Serdes1 = 57, kCLOCK_Root_Serdes2 = 58, kCLOCK_Root_Serdes0_1G = 59, kCLOCK_Root_Serdes1_1G = 60, kCLOCK_Root_Serdes2_1G = 61, kCLOCK_Root_Xcelbusx = 62, kCLOCK_Root_Xriocu4 = 63, kCLOCK_Root_Mctrl = 64, kCLOCK_Root_Sai1 = 65, kCLOCK_Root_Sai2 = 66, kCLOCK_Root_Sai3 = 67, kCLOCK_Root_Sai4 = 68, kCLOCK_Root_Spdif = 69, kCLOCK_Root_Asrc = 70, kCLOCK_Root_Mic = 71, kCLOCK_Root_Cko1 = 72, kCLOCK_Root_Cko2 = 73 }
	Root clock index. More...

enum	clock_root_mux_source_t { kCLOCK_M7_ClockRoot_MuxOscRc24M = 0U, kCLOCK_M7_ClockRoot_MuxOscRc400M = 1U, kCLOCK_M7_ClockRoot_MuxArmPllOut = 2U, kCLOCK_M7_ClockRoot_MuxSysPll3Out = 3U, kCLOCK_M33_ClockRoot_MuxOscRc24M = 0U, kCLOCK_M33_ClockRoot_MuxOscRc400M = 1U, kCLOCK_M33_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_M33_ClockRoot_MuxArmPllOut = 3U, kCLOCK_EDGELOCK_ClockRoot_MuxOscRc24M = 0U, kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M = 1U, kCLOCK_EDGELOCK_ClockRoot_MuxSysPll1Out = 2U, kCLOCK_EDGELOCK_ClockRoot_MuxSysPll2Pfd1 = 3U, kCLOCK_BUS_AON_ClockRoot_MuxOscRc24M = 0U, kCLOCK_BUS_AON_ClockRoot_MuxOscRc400M = 1U, kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out = 2U, kCLOCK_BUS_AON_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc24M = 0U, kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc400M = 1U, kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out = 2U, kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll3Pfd1 = 3U, kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc24M = 0U, kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc400M = 1U, kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll2Pfd1 = 3U, kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc24M = 0U, kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc400M = 1U, kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut = 2U, kCLOCK_M33_SYSTICK_ClockRoot_MuxSysPll3Div2 = 3U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M = 0U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 1U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 2U, kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 3U, kCLOCK_FLEXIO1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_FLEXIO2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_LPIT3_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPIT3_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPIT3_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPTIMER1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPTIMER1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPTIMER1_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPTIMER2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPTIMER2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPTIMER2_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPTIMER3_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPTIMER3_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPTIMER3_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_TPM2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_TPM2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_TPM2_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_TPM4_ClockRoot_MuxOscRc24M = 0U, kCLOCK_TPM4_ClockRoot_MuxOscRc400M = 1U, kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_TPM4_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_TPM5_ClockRoot_MuxOscRc24M = 0U, kCLOCK_TPM5_ClockRoot_MuxOscRc400M = 1U, kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_TPM5_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_TPM6_ClockRoot_MuxOscRc24M = 0U, kCLOCK_TPM6_ClockRoot_MuxOscRc400M = 1U, kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_TPM6_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_GPT1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_GPT1_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_GPT2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_GPT2_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 2U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd0 = 3U, kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2 = 2U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd1 = 3U, kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc24M = 0U, kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc400M = 1U, kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out = 2U, kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll1Out = 3U, kCLOCK_CAN1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_CAN1_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 3U, kCLOCK_CAN2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_CAN2_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 3U, kCLOCK_CAN3_ClockRoot_MuxOscRc24M = 0U, kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 1U, kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 3U, kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART0102_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART0102_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART0304_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART0304_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART0506_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART0506_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART0708_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART0708_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART0910_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART0910_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPUART1112_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPUART1112_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPI2C0102_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPI2C0102_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPI2C0102_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPI2C0304_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPI2C0304_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPI2C0304_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPI2C0506_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPI2C0506_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_LPI2C0506_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPSPI0102_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1 = 2U, kCLOCK_LPSPI0102_ClockRoot_MuxSysPll2Out = 3U, kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPSPI0304_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1 = 2U, kCLOCK_LPSPI0304_ClockRoot_MuxSysPll2Out = 3U, kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M = 0U, kCLOCK_LPSPI0506_ClockRoot_MuxOscRc400M = 1U, kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1 = 2U, kCLOCK_LPSPI0506_ClockRoot_MuxSysPll2Out = 3U, kCLOCK_I3C1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_I3C1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_I3C1_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_I3C2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_I3C2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_I3C2_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_USDHC1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 2U, kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_USDHC2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 2U, kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_SEMC_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SEMC_ClockRoot_MuxSysPll1Out = 2U, kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd0 = 3U, kCLOCK_ADC1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_ADC2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_ACMP_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_ECAT_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ECAT_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_ECAT_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_ENET_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ENET_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ENET_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_ENET_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M = 0U, kCLOCK_TMR_1588_ClockRoot_MuxOscRc400M = 1U, kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_TMR_1588_ClockRoot_MuxSysPll2Pfd3 = 3U, kCLOCK_NETC_ClockRoot_MuxOscRc24M = 0U, kCLOCK_NETC_ClockRoot_MuxOscRc400M = 1U, kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3 = 2U, kCLOCK_NETC_ClockRoot_MuxSysPll2Pfd1 = 3U, kCLOCK_MAC0_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MAC0_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_MAC0_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_MAC1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MAC1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_MAC1_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_MAC2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MAC2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_MAC2_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_MAC3_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MAC3_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_MAC3_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_MAC4_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MAC4_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_MAC4_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_SERDES0_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES0_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_SERDES1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_SERDES2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div2 = 2U, kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div5 = 3U, kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES0_1G_ClockRoot_MuxSysPll1Out = 2U, kCLOCK_SERDES0_1G_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES1_1G_ClockRoot_MuxSysPll1Out = 2U, kCLOCK_SERDES1_1G_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SERDES2_1G_ClockRoot_MuxSysPll1Out = 2U, kCLOCK_SERDES2_1G_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_XCELBUSX_ClockRoot_MuxOscRc24M = 0U, kCLOCK_XCELBUSX_ClockRoot_MuxOscRc400M = 1U, kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Pfd1 = 3U, kCLOCK_XRIOCU4_ClockRoot_MuxOscRc24M = 0U, kCLOCK_XRIOCU4_ClockRoot_MuxOscRc400M = 1U, kCLOCK_XRIOCU4_ClockRoot_MuxOsc24MOut = 2U, kCLOCK_XRIOCU4_ClockRoot_MuxSysPll3Div2 = 3U, kCLOCK_MCTRL_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MCTRL_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MCTRL_ClockRoot_MuxSysPll1Div5 = 2U, kCLOCK_MCTRL_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_SAI1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 2U, kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_SAI2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 2U, kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_SAI3_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 2U, kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_SAI4_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 2U, kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_SPDIF_ClockRoot_MuxOscRc24M = 0U, kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 1U, kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 2U, kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 3U, kCLOCK_ASRC_ClockRoot_MuxOscRc24M = 0U, kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 1U, kCLOCK_ASRC_ClockRoot_MuxSysPll3Out = 2U, kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_MIC_ClockRoot_MuxOscRc24M = 0U, kCLOCK_MIC_ClockRoot_MuxOscRc400M = 1U, kCLOCK_MIC_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 3U, kCLOCK_CKO1_ClockRoot_MuxOscRc24M = 0U, kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 1U, kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2 = 2U, kCLOCK_CKO1_ClockRoot_MuxSysPll1Div2 = 3U, kCLOCK_CKO2_ClockRoot_MuxOscRc24M = 0U, kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 1U, kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5 = 2U, kCLOCK_CKO2_ClockRoot_MuxArmPllOut = 3U }
	The enumerator of clock roots' clock source mux value. More...

enum	clock_osc_t { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...

enum	clock_gate_value_t { kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK }
	Clock gate value. More...

enum	clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...

enum	clock_usb_src_t { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...

enum	clock_usb_phy_src_t { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...

enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...

enum	clock_pll_post_div_t { kCLOCK_PllPostDiv2 = 0U, kCLOCK_PllPostDiv4 = 1U, kCLOCK_PllPostDiv8 = 2U, kCLOCK_PllPostDiv1 = 3U }
	PLL post divider enumeration. More...

enum	clock_pll_t { kCLOCK_PllArm, kCLOCK_PllSys1, kCLOCK_PllSys2, kCLOCK_PllSys3, kCLOCK_PllAudio, kCLOCK_PllInvalid = -1 }
	PLL name. More...

enum	clock_pfd_t { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...

enum	clock_control_mode_t { kCLOCK_SoftwareMode = 0U, kCLOCK_GpcMode }
	The enumeration of control mode. More...

enum	clock_24MOsc_mode_t { kCLOCK_24MOscHighGainMode = 0U, kCLOCK_24MOscBypassMode = 1U, kCLOCK_24MOscLowPowerMode = 2U }
	The enumeration of 24MHz crystal oscillator mode. More...

enum	clock_1MHzOut_behavior_t { kCLOCK_1MHzOutDisable = 0U, kCLOCK_1MHzOutEnableLocked1Mhz = 1U, kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U }
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. More...

enum	clock_level_t { kCLOCK_Level0 = 0x0UL, kCLOCK_Level1 = 0x1UL, kCLOCK_Level2 = 0x2UL, kCLOCK_Level3 = 0x3UL, kCLOCK_Level4 = 0x4UL }
	The clock dependence level. More...

Functions
static void	CLOCK_SetRootClockMux (clock_root_t root, uint8_t src)
	Set CCM Root Clock MUX node to certain value. More...

static uint32_t	CLOCK_GetRootClockMux (clock_root_t root)
	Get CCM Root Clock MUX value. More...

static clock_name_t	CLOCK_GetRootClockSource (clock_root_t root, uint32_t src)
	Get CCM Root Clock Source. More...

static void	CLOCK_SetRootClockDiv (clock_root_t root, uint32_t div)
	Set CCM Root Clock DIV certain value. More...

static uint32_t	CLOCK_GetRootClockDiv (clock_root_t root)
	Get CCM DIV node value. More...

static void	CLOCK_PowerOffRootClock (clock_root_t root)
	Power Off Root Clock. More...

static void	CLOCK_PowerOnRootClock (clock_root_t root)
	Power On Root Clock. More...

static void	CLOCK_SetRootClock (clock_root_t root, const clock_root_config_t *config)
	Configure Root Clock. More...

static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...

static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...

static uint32_t	CLOCK_GetRootClockFreq (clock_root_t root)
	Gets the clock frequency for a specific root clock name. More...

uint32_t	CLOCK_GetM7Freq (void)
	Get the CCM CPU/core/system frequency. More...

uint32_t	CLOCK_GetM33Freq (void)
	Get the CCM CPU/core/system frequency. More...

static bool	CLOCK_IsPllBypassed (clock_pll_t pll)
	Check if PLL is bypassed. More...

static bool	CLOCK_IsPllEnabled (clock_pll_t pll)
	Check if PLL is enabled. More...

void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL. More...

status_t	CLOCK_CalcArmPllFreq (clock_arm_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitArmPllWithFreq (uint32_t freqInMhz)
	Initializes the Arm PLL with Specific Frequency (in Mhz). More...

void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL.

void	CLOCK_CalcPllSpreadSpectrum (uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
	Calculate spread spectrum step and stop. More...

void	CLOCK_InitSysPll1 (const clock_sys_pll1_config_t *config)
	Initialize the System PLL1. More...

void	CLOCK_DeinitSysPll1 (void)
	De-initialize the System PLL1.

void	CLOCK_InitSysPll2 (const clock_sys_pll2_config_t *config)
	Initialize the System PLL2. More...

void	CLOCK_DeinitSysPll2 (void)
	De-initialize the System PLL2.

bool	CLOCK_IsSysPll2PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL2 PFD is enabled. More...

void	CLOCK_InitSysPll3 (void)
	Initialize the System PLL3. More...

void	CLOCK_DeinitSysPll3 (void)
	De-initialize the System PLL3.

bool	CLOCK_IsSysPll3PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL3 PFD is enabled. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
	CLOCK driver version. More...

#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000UL)

OSC operations
static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...

void	CLOCK_SetClockSourceControlMode (clock_name_t name, clock_control_mode_t controlMode)
	Set the control mode of a specifed clock. More...

static void	CLOCK_OSC_EnableOscRc24M (bool enable)
	Enable/disable 24MHz RC oscillator. More...

void	CLOCK_OSC_EnableOsc24M (void)
	Enable OSC 24Mhz. More...

static void	CLOCK_OSC_GateOsc24M (bool enableGate)
	Gate/ungate the 24MHz crystal oscillator output. More...

void	CLOCK_OSC_SetOsc24MWorkMode (clock_24MOsc_mode_t workMode)
	Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode. More...

void	CLOCK_OSC_EnableOscRc400M (void)
	Enable OSC RC 400Mhz. More...

static void	CLOCK_OSC_GateOscRc400M (bool enableGate)
	Gate/ungate 400MHz RC oscillator. More...

void	CLOCK_OSC_TrimOscRc400M (bool enable, bool bypass, uint16_t trim)
	Trims OSC RC 400MHz. More...

void	CLOCK_OSC_SetOscRc400MRefClkDiv (uint8_t divValue)
	Set the divide value for ref_clk to generate slow clock. More...

void	CLOCK_OSC_SetOscRc400MFastClkCount (uint16_t targetCount)
	Set the target count for the fast clock. More...

void	CLOCK_OSC_SetOscRc400MHysteresisValue (uint8_t negHysteresis, uint8_t posHysteresis)
	Set the negative and positive hysteresis value for the tuned clock. More...

void	CLOCK_OSC_BypassOscRc400MTuneLogic (bool enableBypass)
	Bypass/un-bypass the tune logic. More...

void	CLOCK_OSC_EnableOscRc400MTuneLogic (bool enable)
	Start/Stop the tune logic. More...

void	CLOCK_OSC_FreezeOscRc400MTuneValue (bool enableFreeze)
	Freeze/Unfreeze the tuning value. More...

void	CLOCK_OSC_SetOscRc400MTuneValue (uint8_t tuneValue)
	Set the 400MHz RC oscillator tune value when the tune logic is disabled. More...

void	CLOCK_OSC_Set1MHzOutputBehavior (clock_1MHzOut_behavior_t behavior)
	Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output. More...

void	CLOCK_OSC_SetLocked1MHzCount (uint16_t count)
	Set the count for the locked 1MHz clock out. More...

bool	CLOCK_OSC_CheckLocked1MHzErrorFlag (void)
	Check the error flag for locked 1MHz clock out. More...

void	CLOCK_OSC_ClearLocked1MHzErrorFlag (void)
	Clear the error flag for locked 1MHz clock out.

uint16_t	CLOCK_OSC_GetCurrentOscRc400MFastClockCount (void)
	Get current count for the fast clock during the tune process. More...

uint8_t	CLOCK_OSC_GetCurrentOscRc400MTuneValue (void)
	Get current tune value used by oscillator during tune process. More...

PLL/PFD operations
void	CLOCK_SetPllBypass (clock_pll_t pll, bool bypass)
	PLL bypass setting. More...

status_t	CLOCK_CalcAudioPllFreq (clock_audio_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitAudioPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Audio PLL with Specific Frequency (in Mhz). More...

void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...

void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL.

uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...

void	CLOCK_InitPfd (clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
	Initialize PLL PFD. More...

void	CLOCK_DeinitPfd (clock_pll_t pll, clock_pfd_t pfd)
	De-initialize selected PLL PFD. More...

uint32_t	CLOCK_GetPfdFreq (clock_pll_t pll, clock_pfd_t pfd)
	Get current PFD output frequency. More...

uint32_t	CLOCK_GetFreqFromObs (uint8_t obsIndex, uint32_t obsSigIndex)

bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

static void	CLOCK_OSCPLL_LockWhiteList (clock_name_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_OSCPLL_SetWhiteList (clock_name_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

void	CLOCK_OSCPLL_ControlByCpuLowPowerMode (clock_name_t name, uint32_t domainMap, clock_level_t level)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_ROOT_LockWhiteList (clock_root_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_ROOT_SetWhiteList (clock_root_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static void	CLOCK_LPCG_LockWhiteList (clock_lpcg_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_LPCG_SetWhiteList (clock_lpcg_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

void	CLOCK_LPCG_ControlByCpuLowPowerMode (clock_lpcg_t name, uint32_t domainMap, clock_level_t level)
	Set this clock works in CPU Low Power Mode. More...

Data Structure Documentation

struct clock_arm_pll_config_t

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

Data Fields
clock_pll_post_div_t	postDivider
	Post divider. More...

uint32_t	loopDivider
	PLL loop divider. More...

Field Documentation

clock_pll_post_div_t clock_arm_pll_config_t::postDivider

uint32_t clock_arm_pll_config_t::loopDivider

Valid range: 104-208.

struct clock_usb_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

uint8_t clock_usb_pll_config_t::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct clock_pll_ss_config_t

Data Fields
uint16_t	stop
	Spread spectrum stop value to get frequency change. More...

uint16_t	step
	Spread spectrum step value to get frequency change step. More...

Field Documentation

uint16_t clock_pll_ss_config_t::stop

uint16_t clock_pll_ss_config_t::step

struct clock_sys_pll2_config_t

Data Fields
uint32_t	mfd
	Denominator of spread spectrum.

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

struct clock_sys_pll1_config_t

Data Fields
bool	pllDiv2En
	Enable Sys Pll1 divide-by-2 clock or not. More...

bool	pllDiv5En
	Enable Sys Pll1 divide-by-5 clock or not. More...

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

bool clock_sys_pll1_config_t::pllDiv2En

bool clock_sys_pll1_config_t::pllDiv5En

struct clock_audio_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	postDivider
	Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

uint8_t clock_audio_pll_config_t::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t clock_audio_pll_config_t::postDivider

uint32_t clock_audio_pll_config_t::numerator

struct clock_root_config_t

Data Fields
uint8_t	mux
	See clock_root_mux_source_t for details. More...

uint8_t	div
	it's the actual divider

Field Documentation

uint8_t clock_root_config_t::mux

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))

#define LPADC_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
    }

#define AOI_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2, kCLOCK_Aoi3, kCLOCK_Aoi4 \
    }

#define ASRC_CLOCKS

Value:

{               \
        kCLOCK_Asrc \
    }

#define CMP_CLOCKS

Value:

{                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

#define DAC_CLOCKS

Value:

{              \
        kCLOCK_Dac \
    }

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

#define ECAT_CLOCKS

Value:

{               \
        kCLOCK_ECAT \
    }

#define EDMA_CLOCKS

Value:

{                                                \
        kCLOCK_Edma3, kCLOCK_Edma4 \
    }

#define ENC_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define FLEXCAN_CLOCKS

Value:

{                                                           \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
    }

#define FLEXIO_CLOCKS

Value:

{                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

#define FLEXSPI_CLOCKS

Value:

{                                                      \
        kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
    }

#define FLEXSPI_SLV_CLOCKS

Value:

{                      \
        kCLOCK_Flexspi_Slv \
    }

#define GPC_CLOCKS

Value:

{              \
        kCLOCK_Gpc \
    }

#define GPIO_CLOCKS

Value:

{                                                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, kCLOCK_Gpio6 \
    }

#define GPT_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
    }

#define I3C_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_I3c1, kCLOCK_I3c2 \
    }

#define IEE_CLOCKS

Value:

{              \
        kCLOCK_Iee \
    }

#define KPP_CLOCKS

Value:

{              \
        kCLOCK_Kpp \
    }

#define LPI2C_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
    }

#define LPIT_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpit1, kCLOCK_Lpit2, kCLOCK_Lpit3 \
    }

#define LPSPI_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
    }

#define LPTMR_CLOCKS

Value:

{                                                                 \
        kCLOCK_IpInvalid, kCLOCK_Lptmr1, kCLOCK_Lptmr2, kCLOCK_Lptmr3 \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
            kCLOCK_Lpuart12                                                                                   \
    }

#define PDM_CLOCKS

Value:

{              \
        kCLOCK_Pdm \
    }

#define MU_CLOCKS

Value:

{                            \
        kCLOCK_Mu_B, kCLOCK_Mu_B \
    }

#define NETC_CLOCKS

Value:

{               \
        kCLOCK_Netc \
    }

#define OCOTP_CLOCKS

Value:

{                \
        kCLOCK_Ocotp \
    }

#define PWM_CLOCKS

Value:

{                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

#define SAI_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
    }

#define SEMA42_CLOCKS

Value:

{                                                \
        kCLOCK_IpInvalid, kCLOCK_Sema1, kCLOCK_Sema2 \
    }

#define SEMC_CLOCKS

Value:

{               \
        kCLOCK_Semc \
    }

#define SERDES_CLOCKS

Value:

{                                                                    \
        kCLOCK_IpInvalid, kCLOCK_Serdes1, kCLOCK_Serdes2, kCLOCK_Serdes3 \
    }

#define SINC_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Sinc1, kCLOCK_Sinc2, kCLOCK_Sinc3 \
    }

#define SPDIF_CLOCKS

Value:

{                \
        kCLOCK_Spdif \
    }

#define SRC_CLOCKS

Value:

{              \
        kCLOCK_Src \
    }

#define TMR_CLOCKS

Value:

{                                                                                                     \
        kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4, kCLOCK_Qtimer5, \
            kCLOCK_Qtimer6, kCLOCK_Qtimer7, kCLOCK_Qtimer8                                                \
    }

#define TPM_CLOCKS

Value:

{                                                                                                  \
        kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6 \
    }

#define USB_CLOCKS

Value:

{              \
        kCLOCK_Usb \
    }

#define USDHC_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

#define WDOG_CLOCKS

Value:

{                                                                                          \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4, kCLOCK_Wdog5 \
    }

#define XBAR_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

Enumeration Type Documentation

enum clock_lpcg_t

Enumerator
kCLOCK_M7	Clock LPCG M7.
kCLOCK_M33	Clock LPCG M33.
kCLOCK_Edgelock	Clock LPCG Edgelock.
kCLOCK_Sim_Aon	Clock LPCG Sim_Aon.
kCLOCK_Sim_Wakeup	Clock LPCG Sim_Wakeup.
kCLOCK_Sim_Mega	Clock LPCG Sim_Mega.
kCLOCK_Sim_R	Clock LPCG Sim_R.
kCLOCK_Anadig	Clock LPCG Anadig.
kCLOCK_Dcdc	Clock LPCG Dcdc.
kCLOCK_Src	Clock LPCG Src.
kCLOCK_Ccm	Clock LPCG Ccm.
kCLOCK_Gpc	Clock LPCG Gpc.
kCLOCK_Adc1	Clock LPCG Adc1.
kCLOCK_Adc2	Clock LPCG Adc2.
kCLOCK_Dac	Clock LPCG Dac.
kCLOCK_Acmp1	Clock LPCG Acmp1.
kCLOCK_Acmp2	Clock LPCG Acmp2.
kCLOCK_Acmp3	Clock LPCG Acmp3.
kCLOCK_Acmp4	Clock LPCG Acmp4.
kCLOCK_Wdog1	Clock LPCG Wdog1.
kCLOCK_Wdog2	Clock LPCG Wdog2.
kCLOCK_Wdog3	Clock LPCG Wdog3.
kCLOCK_Wdog4	Clock LPCG Wdog4.
kCLOCK_Wdog5	Clock LPCG Wdog5.
kCLOCK_Ewm0	Clock LPCG Ewm0.
kCLOCK_Sema1	Clock LPCG Sema1.
kCLOCK_Sema2	Clock LPCG Sema2.
kCLOCK_Mu_A	Clock LPCG Mu_A.
kCLOCK_Mu_B	Clock LPCG Mu_B.
kCLOCK_Edma3	Clock LPCG Edma3.
kCLOCK_Edma4	Clock LPCG Edma4.
kCLOCK_Romcp	Clock LPCG Romcp.
kCLOCK_Ocram1	Clock LPCG Ocram1.
kCLOCK_Ocram2	Clock LPCG Ocram2.
kCLOCK_Flexspi1	Clock LPCG Flexspi1.
kCLOCK_Flexspi2	Clock LPCG Flexspi2.
kCLOCK_Flexspi_Slv	Clock LPCG Flexspi_Slv.
kCLOCK_Trdc	Clock LPCG Trdc.
kCLOCK_Ocotp	Clock LPCG Ocotp.
kCLOCK_Semc	Clock LPCG Semc.
kCLOCK_Iee	Clock LPCG Iee.
kCLOCK_Cstrace	Clock LPCG Cstrace.
kCLOCK_Csswo	Clock LPCG Csswo.
kCLOCK_Iomuxc1	Clock LPCG Iomuxc1.
kCLOCK_Iomuxc2	Clock LPCG Iomuxc2.
kCLOCK_Gpio1	Clock LPCG Gpio1.
kCLOCK_Gpio2	Clock LPCG Gpio2.
kCLOCK_Gpio3	Clock LPCG Gpio3.
kCLOCK_Gpio4	Clock LPCG Gpio4.
kCLOCK_Gpio5	Clock LPCG Gpio5.
kCLOCK_Gpio6	Clock LPCG Gpio6.
kCLOCK_Flexio1	Clock LPCG Flexio1.
kCLOCK_Flexio2	Clock LPCG Flexio2.
kCLOCK_Lpit1	Clock LPCG Lpit1.
kCLOCK_Lpit2	Clock LPCG Lpit2.
kCLOCK_Lpit3	Clock LPCG Lpit3.
kCLOCK_Lptmr1	Clock LPCG Lptmr1.
kCLOCK_Lptmr2	Clock LPCG Lptmr2.
kCLOCK_Lptmr3	Clock LPCG Lptmr3.
kCLOCK_Tpm1	Clock LPCG Tpm1.
kCLOCK_Tpm2	Clock LPCG Tpm2.
kCLOCK_Tpm3	Clock LPCG Tpm3.
kCLOCK_Tpm4	Clock LPCG Tpm4.
kCLOCK_Tpm5	Clock LPCG Tpm5.
kCLOCK_Tpm6	Clock LPCG Tpm6.
kCLOCK_Qtimer1	Clock LPCG Qtimer1.
kCLOCK_Qtimer2	Clock LPCG Qtimer2.
kCLOCK_Qtimer3	Clock LPCG Qtimer3.
kCLOCK_Qtimer4	Clock LPCG Qtimer4.
kCLOCK_Qtimer5	Clock LPCG Qtimer5.
kCLOCK_Qtimer6	Clock LPCG Qtimer6.
kCLOCK_Qtimer7	Clock LPCG Qtimer7.
kCLOCK_Qtimer8	Clock LPCG Qtimer8.
kCLOCK_Gpt1	Clock LPCG Gpt1.
kCLOCK_Gpt2	Clock LPCG Gpt2.
kCLOCK_Syscount	Clock LPCG Syscount.
kCLOCK_Can1	Clock LPCG Can1.
kCLOCK_Can2	Clock LPCG Can2.
kCLOCK_Can3	Clock LPCG Can3.
kCLOCK_Lpuart1	Clock LPCG Lpuart1.
kCLOCK_Lpuart2	Clock LPCG Lpuart2.
kCLOCK_Lpuart3	Clock LPCG Lpuart3.
kCLOCK_Lpuart4	Clock LPCG Lpuart4.
kCLOCK_Lpuart5	Clock LPCG Lpuart5.
kCLOCK_Lpuart6	Clock LPCG Lpuart6.
kCLOCK_Lpuart7	Clock LPCG Lpuart7.
kCLOCK_Lpuart8	Clock LPCG Lpuart8.
kCLOCK_Lpuart9	Clock LPCG Lpuart9.
kCLOCK_Lpuart10	Clock LPCG Lpuart10.
kCLOCK_Lpuart11	Clock LPCG Lpuart11.
kCLOCK_Lpuart12	Clock LPCG Lpuart12.
kCLOCK_Lpi2c1	Clock LPCG Lpi2c1.
kCLOCK_Lpi2c2	Clock LPCG Lpi2c2.
kCLOCK_Lpi2c3	Clock LPCG Lpi2c3.
kCLOCK_Lpi2c4	Clock LPCG Lpi2c4.
kCLOCK_Lpi2c5	Clock LPCG Lpi2c5.
kCLOCK_Lpi2c6	Clock LPCG Lpi2c6.
kCLOCK_Lpspi1	Clock LPCG Lpspi1.
kCLOCK_Lpspi2	Clock LPCG Lpspi2.
kCLOCK_Lpspi3	Clock LPCG Lpspi3.
kCLOCK_Lpspi4	Clock LPCG Lpspi4.
kCLOCK_Lpspi5	Clock LPCG Lpspi5.
kCLOCK_Lpspi6	Clock LPCG Lpspi6.
kCLOCK_I3c1	Clock LPCG I3c1.
kCLOCK_I3c2	Clock LPCG I3c2.
kCLOCK_Usdhc1	Clock LPCG Usdhc1.
kCLOCK_Usdhc2	Clock LPCG Usdhc2.
kCLOCK_Usb	Clock LPCG Usb.
kCLOCK_Sinc1	Clock LPCG Sinc1.
kCLOCK_Sinc2	Clock LPCG Sinc2.
kCLOCK_Sinc3	Clock LPCG Sinc3.
kCLOCK_Xbar1	Clock LPCG Xbar1.
kCLOCK_Xbar2	Clock LPCG Xbar2.
kCLOCK_Xbar3	Clock LPCG Xbar3.
kCLOCK_Aoi1	Clock LPCG Aoi1.
kCLOCK_Aoi2	Clock LPCG Aoi2.
kCLOCK_Aoi3	Clock LPCG Aoi3.
kCLOCK_Aoi4	Clock LPCG Aoi4.
kCLOCK_Enc1	Clock LPCG Enc1.
kCLOCK_Enc2	Clock LPCG Enc2.
kCLOCK_Enc3	Clock LPCG Enc3.
kCLOCK_Enc4	Clock LPCG Enc4.
kCLOCK_Kpp	Clock LPCG Kpp.
kCLOCK_Pwm1	Clock LPCG Pwm1.
kCLOCK_Pwm2	Clock LPCG Pwm2.
kCLOCK_Pwm3	Clock LPCG Pwm3.
kCLOCK_Pwm4	Clock LPCG Pwm4.
kCLOCK_Ecat	Clock LPCG Ecat.
kCLOCK_Netc	Clock LPCG Netc.
kCLOCK_Serdes1	Clock LPCG Serdes1.
kCLOCK_Serdes2	Clock LPCG Serdes2.
kCLOCK_Serdes3	Clock LPCG Serdes3.
kCLOCK_Xcelbusx	Clock LPCG Xcelbusx.
kCLOCK_Xriocu4	Clock LPCG Xriocu4.
kCLOCK_Sptp	Clock LPCG Sptp.
kCLOCK_Mctrl	Clock LPCG Mctrl.
kCLOCK_Sai1	Clock LPCG Sai1.
kCLOCK_Sai2	Clock LPCG Sai2.
kCLOCK_Sai3	Clock LPCG Sai3.
kCLOCK_Sai4	Clock LPCG Sai4.
kCLOCK_Spdif	Clock LPCG Spdif.
kCLOCK_Asrc	Clock LPCG Asrc.
kCLOCK_Pdm	Clock LPCG Mic.
kCLOCK_Vref	Clock LPCG Vref.
kCLOCK_Bist	Clock LPCG Bist.
kCLOCK_Ssi_W2M7	Clock LPCG Ssi_W2M7.
kCLOCK_Ssi_M72W	Clock LPCG Ssi_M72W.
kCLOCK_Ssi_W2Ao	Clock LPCG Ssi_W2Ao.
kCLOCK_Ssi_Ao2W	Clock LPCG Ssi_Ao2W.
kCLOCK_IpInvalid	Invalid value.

enum clock_name_t

Enumerator
kCLOCK_OscRc24M	24MHz RC Oscillator.
kCLOCK_OscRc400M	400MHz RC Oscillator.
kCLOCK_Osc24M	24MHz Oscillator.
kCLOCK_Osc24MOut	24MHz Oscillator Out.
kCLOCK_ArmPll	ARM PLL.
kCLOCK_ArmPllOut	ARM PLL Out.
kCLOCK_SysPll2	SYS PLL2.
kCLOCK_SysPll2Out	SYS PLL2 OUT.
kCLOCK_SysPll2Pfd0	SYS PLL2 PFD0.
kCLOCK_SysPll2Pfd1	SYS PLL2 PFD1.
kCLOCK_SysPll2Pfd2	SYS PLL2 PFD2.
kCLOCK_SysPll2Pfd3	SYS PLL2 PFD3.
kCLOCK_SysPll3	SYS PLL3.
kCLOCK_SysPll3Out	SYS PLL3 OUT.
kCLOCK_SysPll3Div2	SYS PLL3 DIV2.
kCLOCK_SysPll3Pfd0	SYS PLL3 PFD0.
kCLOCK_SysPll3Pfd1	SYS PLL3 PFD1.
kCLOCK_SysPll3Pfd2	SYS PLL3 PFD2.
kCLOCK_SysPll3Pfd3	SYS PLL3 PFD3.
kCLOCK_SysPll1	SYS PLL1.
kCLOCK_SysPll1Out	SYS PLL1 OUT.
kCLOCK_SysPll1Div2	SYS PLL1 DIV2.
kCLOCK_SysPll1Div5	SYS PLL1 DIV5.
kCLOCK_AudioPll	SYS AUDIO PLL.
kCLOCK_AudioPllOut	SYS AUDIO PLL OUT.
kCLOCK_CpuClk	SYS CPU CLK.
kCLOCK_CoreSysClk	SYS CORE SYS CLK.

enum clock_root_t

Enumerator
kCLOCK_Root_M7	CLOCK Root M7.
kCLOCK_Root_M33	CLOCK Root M33.
kCLOCK_Root_Edgelock	CLOCK Root Edgelock.
kCLOCK_Root_Bus_Aon	CLOCK Root Bus_Aon.
kCLOCK_Root_Bus_Wakeup	CLOCK Root Bus_Wakeup.
kCLOCK_Root_Wakeup_Axi	CLOCK Root Wakeup_Axi.
kCLOCK_Root_Swo_Trace	CLOCK Root Swo_Trace.
kCLOCK_Root_M33_Systick	CLOCK Root M33_Systick.
kCLOCK_Root_M7_Systick	CLOCK Root M7_Systick.
kCLOCK_Root_Flexio1	CLOCK Root Flexio1.
kCLOCK_Root_Flexio2	CLOCK Root Flexio2.
kCLOCK_Root_Lpit3	CLOCK Root Lpit3.
kCLOCK_Root_Lptimer1	CLOCK Root Lptimer1.
kCLOCK_Root_Lptimer2	CLOCK Root Lptimer2.
kCLOCK_Root_Lptimer3	CLOCK Root Lptimer3.
kCLOCK_Root_Tpm2	CLOCK Root Tpm2.
kCLOCK_Root_Tpm4	CLOCK Root Tpm4.
kCLOCK_Root_Tpm5	CLOCK Root Tpm5.
kCLOCK_Root_Tpm6	CLOCK Root Tpm6.
kCLOCK_Root_Gpt1	CLOCK Root Gpt1.
kCLOCK_Root_Gpt2	CLOCK Root Gpt2.
kCLOCK_Root_Flexspi1	CLOCK Root Flexspi1.
kCLOCK_Root_Flexspi2	CLOCK Root Flexspi2.
kCLOCK_Root_Flexspi_Slv	CLOCK Root Flexspi_Slv.
kCLOCK_Root_Can1	CLOCK Root Can1.
kCLOCK_Root_Can2	CLOCK Root Can2.
kCLOCK_Root_Can3	CLOCK Root Can3.
kCLOCK_Root_Lpuart0102	CLOCK Root Lpuart0102.
kCLOCK_Root_Lpuart0304	CLOCK Root Lpuart0304.
kCLOCK_Root_Lpuart0506	CLOCK Root Lpuart0506.
kCLOCK_Root_Lpuart0708	CLOCK Root Lpuart0708.
kCLOCK_Root_Lpuart0910	CLOCK Root Lpuart0910.
kCLOCK_Root_Lpuart1112	CLOCK Root Lpuart1112.
kCLOCK_Root_Lpi2c0102	CLOCK Root Lpi2c0102.
kCLOCK_Root_Lpi2c0304	CLOCK Root Lpi2c0304.
kCLOCK_Root_Lpi2c0506	CLOCK Root Lpi2c0506.
kCLOCK_Root_Lpspi0102	CLOCK Root Lpspi0102.
kCLOCK_Root_Lpspi0304	CLOCK Root Lpspi0304.
kCLOCK_Root_Lpspi0506	CLOCK Root Lpspi0506.
kCLOCK_Root_I3c1	CLOCK Root I3c1.
kCLOCK_Root_I3c2	CLOCK Root I3c2.
kCLOCK_Root_Usdhc1	CLOCK Root Usdhc1.
kCLOCK_Root_Usdhc2	CLOCK Root Usdhc2.
kCLOCK_Root_Semc	CLOCK Root Semc.
kCLOCK_Root_Adc1	CLOCK Root Adc1.
kCLOCK_Root_Adc2	CLOCK Root Adc2.
kCLOCK_Root_Acmp	CLOCK Root Acmp.
kCLOCK_Root_Ecat	CLOCK Root Ecat.
kCLOCK_Root_Enet	CLOCK Root Enet.
kCLOCK_Root_Tmr_1588	CLOCK Root Tmr_1588.
kCLOCK_Root_Netc	CLOCK Root Netc.
kCLOCK_Root_Mac0	CLOCK Root Mac0.
kCLOCK_Root_Mac1	CLOCK Root Mac1.
kCLOCK_Root_Mac2	CLOCK Root Mac2.
kCLOCK_Root_Mac3	CLOCK Root Mac3.
kCLOCK_Root_Mac4	CLOCK Root Mac4.
kCLOCK_Root_Serdes0	CLOCK Root Serdes0.
kCLOCK_Root_Serdes1	CLOCK Root Serdes1.
kCLOCK_Root_Serdes2	CLOCK Root Serdes2.
kCLOCK_Root_Serdes0_1G	CLOCK Root Serdes0_1G.
kCLOCK_Root_Serdes1_1G	CLOCK Root Serdes1_1G.
kCLOCK_Root_Serdes2_1G	CLOCK Root Serdes2_1G.
kCLOCK_Root_Xcelbusx	CLOCK Root Xcelbusx.
kCLOCK_Root_Xriocu4	CLOCK Root Xriocu4.
kCLOCK_Root_Mctrl	CLOCK Root Mctrl.
kCLOCK_Root_Sai1	CLOCK Root Sai1.
kCLOCK_Root_Sai2	CLOCK Root Sai2.
kCLOCK_Root_Sai3	CLOCK Root Sai3.
kCLOCK_Root_Sai4	CLOCK Root Sai4.
kCLOCK_Root_Spdif	CLOCK Root Spdif.
kCLOCK_Root_Asrc	CLOCK Root Asrc.
kCLOCK_Root_Mic	CLOCK Root Mic.
kCLOCK_Root_Cko1	CLOCK Root Cko1.
kCLOCK_Root_Cko2	CLOCK Root Cko2.

enum clock_root_mux_source_t

Enumerator
kCLOCK_M7_ClockRoot_MuxOscRc24M	M7 mux from OscRc24M.
kCLOCK_M7_ClockRoot_MuxOscRc400M	M7 mux from OscRc400M.
kCLOCK_M7_ClockRoot_MuxArmPllOut	M7 mux from ArmPllOut.
kCLOCK_M7_ClockRoot_MuxSysPll3Out	M7 mux from SysPll3Out.
kCLOCK_M33_ClockRoot_MuxOscRc24M	M33 mux from OscRc24M.
kCLOCK_M33_ClockRoot_MuxOscRc400M	M33 mux from OscRc400M.
kCLOCK_M33_ClockRoot_MuxSysPll3Out	M33 mux from SysPll3Out.
kCLOCK_M33_ClockRoot_MuxArmPllOut	M33 mux from ArmPllOut.
kCLOCK_EDGELOCK_ClockRoot_MuxOscRc24M	EDGELOCK mux from OscRc24M.
kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M	EDGELOCK mux from OscRc400M.
kCLOCK_EDGELOCK_ClockRoot_MuxSysPll1Out	EDGELOCK mux from SysPll1Out.
kCLOCK_EDGELOCK_ClockRoot_MuxSysPll2Pfd1	EDGELOCK mux from SysPll2Pfd1.
kCLOCK_BUS_AON_ClockRoot_MuxOscRc24M	BUS_AON mux from OscRc24M.
kCLOCK_BUS_AON_ClockRoot_MuxOscRc400M	BUS_AON mux from OscRc400M.
kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out	BUS_AON mux from SysPll2Out.
kCLOCK_BUS_AON_ClockRoot_MuxSysPll3Pfd2	BUS_AON mux from SysPll3Pfd2.
kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc24M	BUS_WAKEUP mux from OscRc24M.
kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc400M	BUS_WAKEUP mux from OscRc400M.
kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out	BUS_WAKEUP mux from SysPll2Out.
kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll3Pfd1	BUS_WAKEUP mux from SysPll3Pfd1.
kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc24M	WAKEUP_AXI mux from OscRc24M.
kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc400M	WAKEUP_AXI mux from OscRc400M.
kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out	WAKEUP_AXI mux from SysPll3Out.
kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll2Pfd1	WAKEUP_AXI mux from SysPll2Pfd1.
kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc24M	SWO_TRACE mux from OscRc24M.
kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc400M	SWO_TRACE mux from OscRc400M.
kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2	SWO_TRACE mux from SysPll3Div2.
kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll1Div5	SWO_TRACE mux from SysPll1Div5.
kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc24M	M33_SYSTICK mux from OscRc24M.
kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc400M	M33_SYSTICK mux from OscRc400M.
kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut	M33_SYSTICK mux from Osc24MOut.
kCLOCK_M33_SYSTICK_ClockRoot_MuxSysPll3Div2	M33_SYSTICK mux from SysPll3Div2.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M	M7_SYSTICK mux from OscRc24M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M	M7_SYSTICK mux from OscRc400M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut	M7_SYSTICK mux from Osc24MOut.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2	M7_SYSTICK mux from SysPll3Div2.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc24M	FLEXIO1 mux from OscRc24M.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M	FLEXIO1 mux from OscRc400M.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2	FLEXIO1 mux from SysPll3Div2.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5	FLEXIO1 mux from SysPll1Div5.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc24M	FLEXIO2 mux from OscRc24M.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M	FLEXIO2 mux from OscRc400M.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2	FLEXIO2 mux from SysPll3Div2.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5	FLEXIO2 mux from SysPll1Div5.
kCLOCK_LPIT3_ClockRoot_MuxOscRc24M	LPIT3 mux from OscRc24M.
kCLOCK_LPIT3_ClockRoot_MuxOscRc400M	LPIT3 mux from OscRc400M.
kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2	LPIT3 mux from SysPll3Div2.
kCLOCK_LPIT3_ClockRoot_MuxSysPll2Pfd3	LPIT3 mux from SysPll2Pfd3.
kCLOCK_LPTIMER1_ClockRoot_MuxOscRc24M	LPTIMER1 mux from OscRc24M.
kCLOCK_LPTIMER1_ClockRoot_MuxOscRc400M	LPTIMER1 mux from OscRc400M.
kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2	LPTIMER1 mux from SysPll3Div2.
kCLOCK_LPTIMER1_ClockRoot_MuxSysPll2Pfd3	LPTIMER1 mux from SysPll2Pfd3.
kCLOCK_LPTIMER2_ClockRoot_MuxOscRc24M	LPTIMER2 mux from OscRc24M.
kCLOCK_LPTIMER2_ClockRoot_MuxOscRc400M	LPTIMER2 mux from OscRc400M.
kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2	LPTIMER2 mux from SysPll3Div2.
kCLOCK_LPTIMER2_ClockRoot_MuxSysPll2Pfd3	LPTIMER2 mux from SysPll2Pfd3.
kCLOCK_LPTIMER3_ClockRoot_MuxOscRc24M	LPTIMER3 mux from OscRc24M.
kCLOCK_LPTIMER3_ClockRoot_MuxOscRc400M	LPTIMER3 mux from OscRc400M.
kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2	LPTIMER3 mux from SysPll3Div2.
kCLOCK_LPTIMER3_ClockRoot_MuxSysPll2Pfd3	LPTIMER3 mux from SysPll2Pfd3.
kCLOCK_TPM2_ClockRoot_MuxOscRc24M	TPM2 mux from OscRc24M.
kCLOCK_TPM2_ClockRoot_MuxOscRc400M	TPM2 mux from OscRc400M.
kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2	TPM2 mux from SysPll3Div2.
kCLOCK_TPM2_ClockRoot_MuxSysPll2Pfd3	TPM2 mux from SysPll2Pfd3.
kCLOCK_TPM4_ClockRoot_MuxOscRc24M	TPM4 mux from OscRc24M.
kCLOCK_TPM4_ClockRoot_MuxOscRc400M	TPM4 mux from OscRc400M.
kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2	TPM4 mux from SysPll3Div2.
kCLOCK_TPM4_ClockRoot_MuxSysPll2Pfd3	TPM4 mux from SysPll2Pfd3.
kCLOCK_TPM5_ClockRoot_MuxOscRc24M	TPM5 mux from OscRc24M.
kCLOCK_TPM5_ClockRoot_MuxOscRc400M	TPM5 mux from OscRc400M.
kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2	TPM5 mux from SysPll3Div2.
kCLOCK_TPM5_ClockRoot_MuxSysPll2Pfd3	TPM5 mux from SysPll2Pfd3.
kCLOCK_TPM6_ClockRoot_MuxOscRc24M	TPM6 mux from OscRc24M.
kCLOCK_TPM6_ClockRoot_MuxOscRc400M	TPM6 mux from OscRc400M.
kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2	TPM6 mux from SysPll3Div2.
kCLOCK_TPM6_ClockRoot_MuxSysPll2Pfd3	TPM6 mux from SysPll2Pfd3.
kCLOCK_GPT1_ClockRoot_MuxOscRc24M	GPT1 mux from OscRc24M.
kCLOCK_GPT1_ClockRoot_MuxOscRc400M	GPT1 mux from OscRc400M.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2	GPT1 mux from SysPll3Div2.
kCLOCK_GPT1_ClockRoot_MuxSysPll2Pfd3	GPT1 mux from SysPll2Pfd3.
kCLOCK_GPT2_ClockRoot_MuxOscRc24M	GPT2 mux from OscRc24M.
kCLOCK_GPT2_ClockRoot_MuxOscRc400M	GPT2 mux from OscRc400M.
kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2	GPT2 mux from SysPll3Div2.
kCLOCK_GPT2_ClockRoot_MuxSysPll2Pfd3	GPT2 mux from SysPll2Pfd3.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M	FLEXSPI1 mux from OscRc24M.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M	FLEXSPI1 mux from OscRc400M.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0	FLEXSPI1 mux from SysPll3Pfd0.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd0	FLEXSPI1 mux from SysPll2Pfd0.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc24M	FLEXSPI2 mux from OscRc24M.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M	FLEXSPI2 mux from OscRc400M.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2	FLEXSPI2 mux from SysPll3Pfd2.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd1	FLEXSPI2 mux from SysPll2Pfd1.
kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc24M	FLEXSPI_SLV mux from OscRc24M.
kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc400M	FLEXSPI_SLV mux from OscRc400M.
kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out	FLEXSPI_SLV mux from SysPll2Out.
kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll1Out	FLEXSPI_SLV mux from SysPll1Out.
kCLOCK_CAN1_ClockRoot_MuxOscRc24M	CAN1 mux from OscRc24M.
kCLOCK_CAN1_ClockRoot_MuxOscRc400M	CAN1 mux from OscRc400M.
kCLOCK_CAN1_ClockRoot_MuxSysPll3Out	CAN1 mux from SysPll3Out.
kCLOCK_CAN1_ClockRoot_MuxOsc24MOut	CAN1 mux from Osc24MOut.
kCLOCK_CAN2_ClockRoot_MuxOscRc24M	CAN2 mux from OscRc24M.
kCLOCK_CAN2_ClockRoot_MuxOscRc400M	CAN2 mux from OscRc400M.
kCLOCK_CAN2_ClockRoot_MuxSysPll3Out	CAN2 mux from SysPll3Out.
kCLOCK_CAN2_ClockRoot_MuxOsc24MOut	CAN2 mux from Osc24MOut.
kCLOCK_CAN3_ClockRoot_MuxOscRc24M	CAN3 mux from OscRc24M.
kCLOCK_CAN3_ClockRoot_MuxOscRc400M	CAN3 mux from OscRc400M.
kCLOCK_CAN3_ClockRoot_MuxSysPll3Out	CAN3 mux from SysPll3Out.
kCLOCK_CAN3_ClockRoot_MuxOsc24MOut	CAN3 mux from Osc24MOut.
kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M	LPUART0102 mux from OscRc24M.
kCLOCK_LPUART0102_ClockRoot_MuxOscRc400M	LPUART0102 mux from OscRc400M.
kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2	LPUART0102 mux from SysPll3Div2.
kCLOCK_LPUART0102_ClockRoot_MuxSysPll2Pfd3	LPUART0102 mux from SysPll2Pfd3.
kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M	LPUART0304 mux from OscRc24M.
kCLOCK_LPUART0304_ClockRoot_MuxOscRc400M	LPUART0304 mux from OscRc400M.
kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2	LPUART0304 mux from SysPll3Div2.
kCLOCK_LPUART0304_ClockRoot_MuxSysPll2Pfd3	LPUART0304 mux from SysPll2Pfd3.
kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M	LPUART0506 mux from OscRc24M.
kCLOCK_LPUART0506_ClockRoot_MuxOscRc400M	LPUART0506 mux from OscRc400M.
kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2	LPUART0506 mux from SysPll3Div2.
kCLOCK_LPUART0506_ClockRoot_MuxSysPll2Pfd3	LPUART0506 mux from SysPll2Pfd3.
kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M	LPUART0708 mux from OscRc24M.
kCLOCK_LPUART0708_ClockRoot_MuxOscRc400M	LPUART0708 mux from OscRc400M.
kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2	LPUART0708 mux from SysPll3Div2.
kCLOCK_LPUART0708_ClockRoot_MuxSysPll2Pfd3	LPUART0708 mux from SysPll2Pfd3.
kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M	LPUART0910 mux from OscRc24M.
kCLOCK_LPUART0910_ClockRoot_MuxOscRc400M	LPUART0910 mux from OscRc400M.
kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2	LPUART0910 mux from SysPll3Div2.
kCLOCK_LPUART0910_ClockRoot_MuxSysPll2Pfd3	LPUART0910 mux from SysPll2Pfd3.
kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M	LPUART1112 mux from OscRc24M.
kCLOCK_LPUART1112_ClockRoot_MuxOscRc400M	LPUART1112 mux from OscRc400M.
kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2	LPUART1112 mux from SysPll3Div2.
kCLOCK_LPUART1112_ClockRoot_MuxSysPll2Pfd3	LPUART1112 mux from SysPll2Pfd3.
kCLOCK_LPI2C0102_ClockRoot_MuxOscRc24M	LPI2C0102 mux from OscRc24M.
kCLOCK_LPI2C0102_ClockRoot_MuxOscRc400M	LPI2C0102 mux from OscRc400M.
kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2	LPI2C0102 mux from SysPll3Div2.
kCLOCK_LPI2C0102_ClockRoot_MuxSysPll2Pfd3	LPI2C0102 mux from SysPll2Pfd3.
kCLOCK_LPI2C0304_ClockRoot_MuxOscRc24M	LPI2C0304 mux from OscRc24M.
kCLOCK_LPI2C0304_ClockRoot_MuxOscRc400M	LPI2C0304 mux from OscRc400M.
kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2	LPI2C0304 mux from SysPll3Div2.
kCLOCK_LPI2C0304_ClockRoot_MuxSysPll2Pfd3	LPI2C0304 mux from SysPll2Pfd3.
kCLOCK_LPI2C0506_ClockRoot_MuxOscRc24M	LPI2C0506 mux from OscRc24M.
kCLOCK_LPI2C0506_ClockRoot_MuxOscRc400M	LPI2C0506 mux from OscRc400M.
kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2	LPI2C0506 mux from SysPll3Div2.
kCLOCK_LPI2C0506_ClockRoot_MuxSysPll2Pfd3	LPI2C0506 mux from SysPll2Pfd3.
kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M	LPSPI0102 mux from OscRc24M.
kCLOCK_LPSPI0102_ClockRoot_MuxOscRc400M	LPSPI0102 mux from OscRc400M.
kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1	LPSPI0102 mux from SysPll3Pfd1.
kCLOCK_LPSPI0102_ClockRoot_MuxSysPll2Out	LPSPI0102 mux from SysPll2Out.
kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M	LPSPI0304 mux from OscRc24M.
kCLOCK_LPSPI0304_ClockRoot_MuxOscRc400M	LPSPI0304 mux from OscRc400M.
kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1	LPSPI0304 mux from SysPll3Pfd1.
kCLOCK_LPSPI0304_ClockRoot_MuxSysPll2Out	LPSPI0304 mux from SysPll2Out.
kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M	LPSPI0506 mux from OscRc24M.
kCLOCK_LPSPI0506_ClockRoot_MuxOscRc400M	LPSPI0506 mux from OscRc400M.
kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1	LPSPI0506 mux from SysPll3Pfd1.
kCLOCK_LPSPI0506_ClockRoot_MuxSysPll2Out	LPSPI0506 mux from SysPll2Out.
kCLOCK_I3C1_ClockRoot_MuxOscRc24M	I3C1 mux from OscRc24M.
kCLOCK_I3C1_ClockRoot_MuxOscRc400M	I3C1 mux from OscRc400M.
kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2	I3C1 mux from SysPll3Div2.
kCLOCK_I3C1_ClockRoot_MuxSysPll2Pfd3	I3C1 mux from SysPll2Pfd3.
kCLOCK_I3C2_ClockRoot_MuxOscRc24M	I3C2 mux from OscRc24M.
kCLOCK_I3C2_ClockRoot_MuxOscRc400M	I3C2 mux from OscRc400M.
kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2	I3C2 mux from SysPll3Div2.
kCLOCK_I3C2_ClockRoot_MuxSysPll2Pfd3	I3C2 mux from SysPll2Pfd3.
kCLOCK_USDHC1_ClockRoot_MuxOscRc24M	USDHC1 mux from OscRc24M.
kCLOCK_USDHC1_ClockRoot_MuxOscRc400M	USDHC1 mux from OscRc400M.
kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2	USDHC1 mux from SysPll2Pfd2.
kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5	USDHC1 mux from SysPll1Div5.
kCLOCK_USDHC2_ClockRoot_MuxOscRc24M	USDHC2 mux from OscRc24M.
kCLOCK_USDHC2_ClockRoot_MuxOscRc400M	USDHC2 mux from OscRc400M.
kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2	USDHC2 mux from SysPll2Pfd2.
kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5	USDHC2 mux from SysPll1Div5.
kCLOCK_SEMC_ClockRoot_MuxOscRc24M	SEMC mux from OscRc24M.
kCLOCK_SEMC_ClockRoot_MuxOscRc400M	SEMC mux from OscRc400M.
kCLOCK_SEMC_ClockRoot_MuxSysPll1Out	SEMC mux from SysPll1Out.
kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd0	SEMC mux from SysPll2Pfd0.
kCLOCK_ADC1_ClockRoot_MuxOscRc24M	ADC1 mux from OscRc24M.
kCLOCK_ADC1_ClockRoot_MuxOscRc400M	ADC1 mux from OscRc400M.
kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2	ADC1 mux from SysPll3Div2.
kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3	ADC1 mux from SysPll2Pfd3.
kCLOCK_ADC2_ClockRoot_MuxOscRc24M	ADC2 mux from OscRc24M.
kCLOCK_ADC2_ClockRoot_MuxOscRc400M	ADC2 mux from OscRc400M.
kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2	ADC2 mux from SysPll3Div2.
kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3	ADC2 mux from SysPll2Pfd3.
kCLOCK_ACMP_ClockRoot_MuxOscRc24M	ACMP mux from OscRc24M.
kCLOCK_ACMP_ClockRoot_MuxOscRc400M	ACMP mux from OscRc400M.
kCLOCK_ACMP_ClockRoot_MuxSysPll3Out	ACMP mux from SysPll3Out.
kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3	ACMP mux from SysPll2Pfd3.
kCLOCK_ECAT_ClockRoot_MuxOscRc24M	ECAT mux from OscRc24M.
kCLOCK_ECAT_ClockRoot_MuxOscRc400M	ECAT mux from OscRc400M.
kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2	ECAT mux from SysPll1Div2.
kCLOCK_ECAT_ClockRoot_MuxSysPll1Div5	ECAT mux from SysPll1Div5.
kCLOCK_ENET_ClockRoot_MuxOscRc24M	ENET mux from OscRc24M.
kCLOCK_ENET_ClockRoot_MuxOscRc400M	ENET mux from OscRc400M.
kCLOCK_ENET_ClockRoot_MuxSysPll1Div2	ENET mux from SysPll1Div2.
kCLOCK_ENET_ClockRoot_MuxSysPll1Div5	ENET mux from SysPll1Div5.
kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M	TMR_1588 mux from OscRc24M.
kCLOCK_TMR_1588_ClockRoot_MuxOscRc400M	TMR_1588 mux from OscRc400M.
kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out	TMR_1588 mux from SysPll3Out.
kCLOCK_TMR_1588_ClockRoot_MuxSysPll2Pfd3	TMR_1588 mux from SysPll2Pfd3.
kCLOCK_NETC_ClockRoot_MuxOscRc24M	NETC mux from OscRc24M.
kCLOCK_NETC_ClockRoot_MuxOscRc400M	NETC mux from OscRc400M.
kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3	NETC mux from SysPll3Pfd3.
kCLOCK_NETC_ClockRoot_MuxSysPll2Pfd1	NETC mux from SysPll2Pfd1.
kCLOCK_MAC0_ClockRoot_MuxOscRc24M	MAC0 mux from OscRc24M.
kCLOCK_MAC0_ClockRoot_MuxOscRc400M	MAC0 mux from OscRc400M.
kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2	MAC0 mux from SysPll1Div2.
kCLOCK_MAC0_ClockRoot_MuxSysPll1Div5	MAC0 mux from SysPll1Div5.
kCLOCK_MAC1_ClockRoot_MuxOscRc24M	MAC1 mux from OscRc24M.
kCLOCK_MAC1_ClockRoot_MuxOscRc400M	MAC1 mux from OscRc400M.
kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2	MAC1 mux from SysPll1Div2.
kCLOCK_MAC1_ClockRoot_MuxSysPll1Div5	MAC1 mux from SysPll1Div5.
kCLOCK_MAC2_ClockRoot_MuxOscRc24M	MAC2 mux from OscRc24M.
kCLOCK_MAC2_ClockRoot_MuxOscRc400M	MAC2 mux from OscRc400M.
kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2	MAC2 mux from SysPll1Div2.
kCLOCK_MAC2_ClockRoot_MuxSysPll1Div5	MAC2 mux from SysPll1Div5.
kCLOCK_MAC3_ClockRoot_MuxOscRc24M	MAC3 mux from OscRc24M.
kCLOCK_MAC3_ClockRoot_MuxOscRc400M	MAC3 mux from OscRc400M.
kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2	MAC3 mux from SysPll1Div2.
kCLOCK_MAC3_ClockRoot_MuxSysPll1Div5	MAC3 mux from SysPll1Div5.
kCLOCK_MAC4_ClockRoot_MuxOscRc24M	MAC4 mux from OscRc24M.
kCLOCK_MAC4_ClockRoot_MuxOscRc400M	MAC4 mux from OscRc400M.
kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2	MAC4 mux from SysPll1Div2.
kCLOCK_MAC4_ClockRoot_MuxSysPll1Div5	MAC4 mux from SysPll1Div5.
kCLOCK_SERDES0_ClockRoot_MuxOscRc24M	SERDES0 mux from OscRc24M.
kCLOCK_SERDES0_ClockRoot_MuxOscRc400M	SERDES0 mux from OscRc400M.
kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div2	SERDES0 mux from SysPll1Div2.
kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div5	SERDES0 mux from SysPll1Div5.
kCLOCK_SERDES1_ClockRoot_MuxOscRc24M	SERDES1 mux from OscRc24M.
kCLOCK_SERDES1_ClockRoot_MuxOscRc400M	SERDES1 mux from OscRc400M.
kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div2	SERDES1 mux from SysPll1Div2.
kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div5	SERDES1 mux from SysPll1Div5.
kCLOCK_SERDES2_ClockRoot_MuxOscRc24M	SERDES2 mux from OscRc24M.
kCLOCK_SERDES2_ClockRoot_MuxOscRc400M	SERDES2 mux from OscRc400M.
kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div2	SERDES2 mux from SysPll1Div2.
kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div5	SERDES2 mux from SysPll1Div5.
kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc24M	SERDES0_1G mux from OscRc24M.
kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc400M	SERDES0_1G mux from OscRc400M.
kCLOCK_SERDES0_1G_ClockRoot_MuxSysPll1Out	SERDES0_1G mux from SysPll1Out.
kCLOCK_SERDES0_1G_ClockRoot_MuxAudioPllOut	SERDES0_1G mux from AudioPllOut.
kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc24M	SERDES1_1G mux from OscRc24M.
kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc400M	SERDES1_1G mux from OscRc400M.
kCLOCK_SERDES1_1G_ClockRoot_MuxSysPll1Out	SERDES1_1G mux from SysPll1Out.
kCLOCK_SERDES1_1G_ClockRoot_MuxAudioPllOut	SERDES1_1G mux from AudioPllOut.
kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc24M	SERDES2_1G mux from OscRc24M.
kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc400M	SERDES2_1G mux from OscRc400M.
kCLOCK_SERDES2_1G_ClockRoot_MuxSysPll1Out	SERDES2_1G mux from SysPll1Out.
kCLOCK_SERDES2_1G_ClockRoot_MuxAudioPllOut	SERDES2_1G mux from AudioPllOut.
kCLOCK_XCELBUSX_ClockRoot_MuxOscRc24M	XCELBUSX mux from OscRc24M.
kCLOCK_XCELBUSX_ClockRoot_MuxOscRc400M	XCELBUSX mux from OscRc400M.
kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Out	XCELBUSX mux from SysPll3Out.
kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Pfd1	XCELBUSX mux from SysPll3Pfd1.
kCLOCK_XRIOCU4_ClockRoot_MuxOscRc24M	XRIOCU4 mux from OscRc24M.
kCLOCK_XRIOCU4_ClockRoot_MuxOscRc400M	XRIOCU4 mux from OscRc400M.
kCLOCK_XRIOCU4_ClockRoot_MuxOsc24MOut	XRIOCU4 mux from Osc24MOut.
kCLOCK_XRIOCU4_ClockRoot_MuxSysPll3Div2	XRIOCU4 mux from SysPll3Div2.
kCLOCK_MCTRL_ClockRoot_MuxOscRc24M	MCTRL mux from OscRc24M.
kCLOCK_MCTRL_ClockRoot_MuxOscRc400M	MCTRL mux from OscRc400M.
kCLOCK_MCTRL_ClockRoot_MuxSysPll1Div5	MCTRL mux from SysPll1Div5.
kCLOCK_MCTRL_ClockRoot_MuxAudioPllOut	MCTRL mux from AudioPllOut.
kCLOCK_SAI1_ClockRoot_MuxOscRc24M	SAI1 mux from OscRc24M.
kCLOCK_SAI1_ClockRoot_MuxOscRc400M	SAI1 mux from OscRc400M.
kCLOCK_SAI1_ClockRoot_MuxAudioPllOut	SAI1 mux from AudioPllOut.
kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2	SAI1 mux from SysPll3Pfd2.
kCLOCK_SAI2_ClockRoot_MuxOscRc24M	SAI2 mux from OscRc24M.
kCLOCK_SAI2_ClockRoot_MuxOscRc400M	SAI2 mux from OscRc400M.
kCLOCK_SAI2_ClockRoot_MuxAudioPllOut	SAI2 mux from AudioPllOut.
kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2	SAI2 mux from SysPll3Pfd2.
kCLOCK_SAI3_ClockRoot_MuxOscRc24M	SAI3 mux from OscRc24M.
kCLOCK_SAI3_ClockRoot_MuxOscRc400M	SAI3 mux from OscRc400M.
kCLOCK_SAI3_ClockRoot_MuxAudioPllOut	SAI3 mux from AudioPllOut.
kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2	SAI3 mux from SysPll3Pfd2.
kCLOCK_SAI4_ClockRoot_MuxOscRc24M	SAI4 mux from OscRc24M.
kCLOCK_SAI4_ClockRoot_MuxOscRc400M	SAI4 mux from OscRc400M.
kCLOCK_SAI4_ClockRoot_MuxAudioPllOut	SAI4 mux from AudioPllOut.
kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd2	SAI4 mux from SysPll3Pfd2.
kCLOCK_SPDIF_ClockRoot_MuxOscRc24M	SPDIF mux from OscRc24M.
kCLOCK_SPDIF_ClockRoot_MuxOscRc400M	SPDIF mux from OscRc400M.
kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut	SPDIF mux from AudioPllOut.
kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2	SPDIF mux from SysPll3Pfd2.
kCLOCK_ASRC_ClockRoot_MuxOscRc24M	ASRC mux from OscRc24M.
kCLOCK_ASRC_ClockRoot_MuxOscRc400M	ASRC mux from OscRc400M.
kCLOCK_ASRC_ClockRoot_MuxSysPll3Out	ASRC mux from SysPll3Out.
kCLOCK_ASRC_ClockRoot_MuxAudioPllOut	ASRC mux from AudioPllOut.
kCLOCK_MIC_ClockRoot_MuxOscRc24M	MIC mux from OscRc24M.
kCLOCK_MIC_ClockRoot_MuxOscRc400M	MIC mux from OscRc400M.
kCLOCK_MIC_ClockRoot_MuxSysPll3Div2	MIC mux from SysPll3Div2.
kCLOCK_MIC_ClockRoot_MuxAudioPllOut	MIC mux from AudioPllOut.
kCLOCK_CKO1_ClockRoot_MuxOscRc24M	CKO1 mux from OscRc24M.
kCLOCK_CKO1_ClockRoot_MuxOscRc400M	CKO1 mux from OscRc400M.
kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2	CKO1 mux from SysPll3Div2.
kCLOCK_CKO1_ClockRoot_MuxSysPll1Div2	CKO1 mux from SysPll1Div2.
kCLOCK_CKO2_ClockRoot_MuxOscRc24M	CKO2 mux from OscRc24M.
kCLOCK_CKO2_ClockRoot_MuxOscRc400M	CKO2 mux from OscRc400M.
kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5	CKO2 mux from SysPll1Div5.
kCLOCK_CKO2_ClockRoot_MuxArmPllOut	CKO2 mux from ArmPllOut.

enum clock_osc_t

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

enum clock_gate_value_t

Enumerator
kCLOCK_Off	Clock is off.
kCLOCK_On	Clock is on.

enum clock_mode_t

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

enum clock_usb_src_t

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

enum clock_usb_phy_src_t

Enumerator
kCLOCK_Usbphy480M	Use 480M.

enum _clock_pll_clk_src

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M.
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N.

enum clock_pll_post_div_t

Enumerator
kCLOCK_PllPostDiv2	Divide by 2.
kCLOCK_PllPostDiv4	Divide by 4.
kCLOCK_PllPostDiv8	Divide by 8.
kCLOCK_PllPostDiv1	Divide by 1.

enum clock_pll_t

Enumerator
kCLOCK_PllArm	ARM PLL.
kCLOCK_PllSys1	SYS1 PLL, it has a dedicated frequency of 1GHz.
kCLOCK_PllSys2	SYS2 PLL, it has a dedicated frequency of 528MHz.
kCLOCK_PllSys3	SYS3 PLL, it has a dedicated frequency of 480MHz.
kCLOCK_PllAudio	Audio PLL.
kCLOCK_PllInvalid	Invalid value.

enum clock_pfd_t

Enumerator
kCLOCK_Pfd0	PLL PFD0.
kCLOCK_Pfd1	PLL PFD1.
kCLOCK_Pfd2	PLL PFD2.
kCLOCK_Pfd3	PLL PFD3.

enum clock_control_mode_t

Enumerator
kCLOCK_SoftwareMode	Software control mode.
kCLOCK_GpcMode	GPC control mode.

enum clock_24MOsc_mode_t

Enumerator
kCLOCK_24MOscHighGainMode	24MHz crystal oscillator work as high gain mode.
kCLOCK_24MOscBypassMode	24MHz crystal oscillator work as bypass mode.
kCLOCK_24MOscLowPowerMode	24MHz crystal oscillator work as low power mode.

enum clock_1MHzOut_behavior_t

Enumerator
kCLOCK_1MHzOutDisable	Disable 1MHz output clock.
kCLOCK_1MHzOutEnableLocked1Mhz	Enable 1MHz output clock, and select locked 1MHz to output.
kCLOCK_1MHzOutEnableFreeRunning1Mhz	Enable 1MHZ output clock, and select free-running 1MHz to output.

enum clock_level_t

Enumerator
kCLOCK_Level0	Not needed in any mode.
kCLOCK_Level1	Needed in RUN mode.
kCLOCK_Level2	Needed in RUN and WAIT mode.
kCLOCK_Level3	Needed in RUN, WAIT and STOP mode.
kCLOCK_Level4	Always on in any mode.

Function Documentation

static void CLOCK_SetRootClockMux	(	clock_root_t	root,
		uint8_t	src
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
src	Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.

static uint32_t CLOCK_GetRootClockMux ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.

Returns: Clock mux value.

static clock_name_t CLOCK_GetRootClockSource	(	clock_root_t	root,
		uint32_t	src
	)

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.
src	Clock mux value to get, see clock_root_mux_source_t.

Returns: Clock source

static void CLOCK_SetRootClockDiv	(	clock_root_t	root,
		uint32_t	div
	)

inlinestatic

Parameters

root	Which root clock to set, see clock_root_t.
div	Clock div value to set, different divider has different value range.

static uint32_t CLOCK_GetRootClockDiv ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.

Returns: divider set for this root

static void CLOCK_PowerOffRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_PowerOnRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_SetRootClock	(	clock_root_t	root,
		const clock_root_config_t *	config
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
config	root clock config, see clock_root_config_t

static void CLOCK_ControlGate	(	clock_ip_name_t	name,
		clock_gate_value_t	value
	)

inlinestatic

Note: This API will not have any effect when this clock is in CPULPM or SetPoint Mode

Parameters

name	Which clock to enable, see clock_lpcg_t.
value	Clock gate value to set, see clock_gate_value_t.

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_lpcg_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_lpcg_t.

uint32_t CLOCK_GetFreq ( clock_name_t name )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

static uint32_t CLOCK_GetRootClockFreq ( clock_root_t root )

inlinestatic

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.

Parameters

root	Clock names defined in clock_root_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetM7Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetM33Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsPllBypassed ( clock_pll_t pll )

inlinestatic

Parameters

pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is bypassed.
false: The PLL is not bypassed.

static bool CLOCK_IsPllEnabled ( clock_pll_t pll )

inlinestatic

Parameters

pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is enabled.
false: The PLL is not enabled.

static uint32_t CLOCK_GetRtcFreq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

void CLOCK_SetClockSourceControlMode	(	clock_name_t	name,
		clock_control_mode_t	controlMode
	)

Parameters

name	Clock names defined in clock_name_t
controlMode	The control mode to be set, please refer to clock_control_mode_t.

static void CLOCK_OSC_EnableOscRc24M ( bool enable )

inlinestatic

Parameters

enable

Used to enable or disable the 24MHz RC oscillator.

true Enable the 24MHz RC oscillator.
false Dissable the 24MHz RC oscillator.

void CLOCK_OSC_EnableOsc24M ( void )

This function enables OSC 24Mhz.

static void CLOCK_OSC_GateOsc24M ( bool enableGate )

inlinestatic

Note: Gating the 24MHz crystal oscillator can save power.

Parameters

enableGate

Used to gate/ungate the 24MHz crystal oscillator.

true Gate the 24MHz crystal oscillator to save power.
false Ungate the 24MHz crystal oscillator.

void CLOCK_OSC_SetOsc24MWorkMode ( clock_24MOsc_mode_t workMode )

Parameters

workMode The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

void CLOCK_OSC_EnableOscRc400M ( void )

This function enables OSC RC 400Mhz.

static void CLOCK_OSC_GateOscRc400M ( bool enableGate )

inlinestatic

Parameters

enableGate

Used to gate/ungate 400MHz RC oscillator.

true Gate the 400MHz RC oscillator.
false Ungate the 400MHz RC oscillator.

void CLOCK_OSC_TrimOscRc400M	(	bool	enable,
		bool	bypass,
		uint16_t	trim
	)

Parameters

enable	Used to enable trim function.
bypass	Bypass the trim function.
trim	Trim value.

void CLOCK_OSC_SetOscRc400MRefClkDiv ( uint8_t divValue )

Note: slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters

divValue The divide value to be set, the available range is 0~63.

void CLOCK_OSC_SetOscRc400MFastClkCount ( uint16_t targetCount )

Parameters

targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

void CLOCK_OSC_SetOscRc400MHysteresisValue	(	uint8_t	negHysteresis,
		uint8_t	posHysteresis
	)

Note: The hysteresis value should be set after the clock is tuned.

Parameters

negHysteresis	The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
posHysteresis	The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

void CLOCK_OSC_BypassOscRc400MTuneLogic ( bool enableBypass )

Parameters

enableBypass

Used to control whether to bypass the turn logic.

true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
false Use the output of tune logic to run the oscillator.

void CLOCK_OSC_EnableOscRc400MTuneLogic ( bool enable )

Parameters

enable

Used to start or stop the tune logic.

true Start tuning
false Stop tuning and reset the tuning logic.

void CLOCK_OSC_FreezeOscRc400MTuneValue ( bool enableFreeze )

Parameters

enableFreeze

Used to control whether to freeze the tune value.

true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
false Unfreezes and continues the tune operation.

void CLOCK_OSC_SetOscRc400MTuneValue ( uint8_t tuneValue )

Parameters

tuneValue The tune value to determine the frequency of Oscillator.

void CLOCK_OSC_Set1MHzOutputBehavior ( clock_1MHzOut_behavior_t behavior )

Note: The 1MHz clock is divided from 400M RC Oscillator.

Parameters

behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

void CLOCK_OSC_SetLocked1MHzCount ( uint16_t count )

Parameters

count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

bool CLOCK_OSC_CheckLocked1MHzErrorFlag ( void )

Returns

The error flag for locked 1MHz clock out.

true The count value has been reached within one diviced ref clock period
false No effect.

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount ( void )

Returns: The current count for the fast clock.

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue ( void )

Returns: The current tune value.

void CLOCK_InitArmPll ( const clock_arm_pll_config_t * config )

This function initialize the ARM PLL with specific settings

Parameters

config configuration to set to PLL.

status_t CLOCK_CalcArmPllFreq	(	clock_arm_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Arm PLL

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitArmPllWithFreq ( uint32_t freqInMhz )

This function initializes the Arm PLL with specific frequency

Parameters

freqInMhz target frequency

void CLOCK_CalcPllSpreadSpectrum	(	uint32_t	factor,
		uint32_t	range,
		uint32_t	mod,
		clock_pll_ss_config_t *	ss
	)

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/syspll1), the factor is denominator.

Parameters

factor	factor to calculate step/stop
range	spread spectrum range
mod	spread spectrum modulation frequency
ss	calculated spread spectrum values

void CLOCK_InitSysPll1 ( const clock_sys_pll1_config_t * config )

This function initializes the System PLL1 with specific settings

Parameters

config Configuration to set to PLL1.

void CLOCK_InitSysPll2 ( const clock_sys_pll2_config_t * config )

This function initializes the System PLL2 with specific settings

Parameters

config Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

bool CLOCK_IsSysPll2PfdEnabled ( clock_pfd_t pfd )

Parameters

pfd	PFD control name

Returns

PFD bypass status.

true: power on.
false: power off.

Note: Only useful in software control mode.

void CLOCK_InitSysPll3 ( void )

This function initializes the System PLL3 with specific settings

bool CLOCK_IsSysPll3PfdEnabled ( clock_pfd_t pfd )

Parameters

pfd	PFD control name

Returns

PFD bypass status.

true: power on.
false: power off.

Note: Only useful in software control mode.

void CLOCK_SetPllBypass	(	clock_pll_t	pll,
		bool	bypass
	)

Parameters

pll	PLL control name (see clock_pll_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false:Not bypass the PLL.

status_t CLOCK_CalcAudioPllFreq	(	clock_audio_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Audio PLL.

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitAudioPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

This function initializes the Audio PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

void CLOCK_InitAudioPll ( const clock_audio_pll_config_t * config )

This function initializes the Audio PLL with specific settings

Parameters

config Configuration to set to PLL.

uint32_t CLOCK_GetPllFreq ( clock_pll_t pll )

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns: The PLL output frequency in hertz.

void CLOCK_InitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd,
		uint8_t	frac
	)

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.
frac	The PFD FRAC value.

Note: It is recommended that PFD settings are kept between 13-35.

void CLOCK_DeinitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.

uint32_t CLOCK_GetPfdFreq	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

This function get current output frequency of specific System PLL PFD

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	pfd name to get frequency.

Returns: The PFD output frequency in hertz.

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs1Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs0PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs0PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs1PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

static void CLOCK_OSCPLL_LockWhiteList ( clock_name_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

static void CLOCK_OSCPLL_SetWhiteList	(	clock_name_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.

void CLOCK_OSCPLL_ControlByCpuLowPowerMode	(	clock_name_t	name,
		uint32_t	domainMap,
		clock_level_t	level
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainMap	Domains that on the whitelist can change this clock.
level	Depend level of this clock.

static void CLOCK_ROOT_LockWhiteList ( clock_root_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_SetWhiteList	(	clock_root_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
domainId	Domains that on the whitelist can change this clock.

static void CLOCK_LPCG_LockWhiteList ( clock_lpcg_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

static void CLOCK_LPCG_SetWhiteList	(	clock_lpcg_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.

void CLOCK_LPCG_ControlByCpuLowPowerMode	(	clock_lpcg_t	name,
		uint32_t	domainMap,
		clock_level_t	level
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainMap	Domains that on the whitelist can change this clock.
level	Depend level of this clock.

Overview

Files

Data Structures

Macros

Enumerations

Functions

Driver version

OSC operations

PLL/PFD operations

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation