Overview

The MCUXpresso SDK provides a peripheral driver for the CACHE Controller of MCUXpresso SDK devices.

The CACHE driver is created to help the user more easily operate the cache memory. The APIs for basic operations are including the following three levels: 1L. The local cache driver API. This level provides the caches controller drivers.

2L. The unified cache driver API. This level provides many APIs for unified cache driver APIs for combined L1 and L2 cache maintain operations. This is provided for SDK drivers (DMA, ENET, USDHC, etc) which should do the cache maintenance in their transactional APIs. Because in this arch, there is no L2 cache so the unified cache driver API directly calls local driver APIs.

Function groups

CACHE Operation

There are Enable/Disable APIs for cache control and cache maintenance operations as Invalidate/Clean/CleanInvalidate by all and by address range.

Macros
#define	XCACHE_LINESIZE_BYTE (FSL_FEATURE_XCACHE_LINESIZE_BYTE)
	cache line size. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
	cache driver version. More...

cache control for XCACHE
uint32_t	XCACHE_GetInstanceByAddr (uint32_t address)
	brief Returns an instance number given physical memory address. More...

void	XCACHE_EnableCache (XCACHE_Type *base)
	Enables the cache. More...

void	XCACHE_DisableCache (XCACHE_Type *base)
	Disables the cache. More...

void	XCACHE_InvalidateCache (XCACHE_Type *base)
	Invalidates the cache. More...

void	XCACHE_InvalidateCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates cache by range. More...

void	XCACHE_CleanCache (XCACHE_Type *base)
	Cleans the cache. More...

void	XCACHE_CleanCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans cache by range. More...

void	XCACHE_CleanInvalidateCache (XCACHE_Type *base)
	Cleans and invalidates the cache. More...

void	XCACHE_CleanInvalidateCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and invalidate cache by range. More...

Unified Cache Control for all caches
static void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates instruction cache by range. More...

static void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates data cache by range. More...

static void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Clean data cache by range. More...

static void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates data cache by range. More...

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))

#define XCACHE_LINESIZE_BYTE (FSL_FEATURE_XCACHE_LINESIZE_BYTE)

Function Documentation

uint32_t XCACHE_GetInstanceByAddr ( uint32_t address )

param address The physical memory address.

Returns: XCACHE instance number starting from 0.

void XCACHE_EnableCache ( XCACHE_Type * base )

Parameters

base	XCACHE peripheral base address.

void XCACHE_DisableCache ( XCACHE_Type * base )

Parameters

base	XCACHE peripheral base address.

void XCACHE_InvalidateCache ( XCACHE_Type * base )

Parameters

base	XCACHE peripheral base address.

void XCACHE_InvalidateCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be invalidated, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to "XCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void XCACHE_CleanCache ( XCACHE_Type * base )

Parameters

base	XCACHE peripheral base address.

void XCACHE_CleanCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be cleaned, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to "XCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void XCACHE_CleanInvalidateCache ( XCACHE_Type * base )

Parameters

base	XCACHE peripheral base address.

void XCACHE_CleanInvalidateCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to "XCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void ICACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanInvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size.

Note: Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Overview

Function groups

CACHE Operation

Macros

Driver version

cache control for XCACHE

Unified Cache Control for all caches

Macro Definition Documentation

Function Documentation