Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	_clock_group_config
	The structure used to configure clock group. More...

struct	_clock_arm_pll_config
	PLL configuration for ARM. More...

struct	_clock_usb_pll_config
	PLL configuration for USB. More...

struct	_clock_pll_ss_config
	Spread specturm configure Pll. More...

struct	_clock_sys_pll2_config
	PLL configure for Sys Pll2. More...

struct	_clock_sys_pll1_config
	PLL configure for Sys Pll1. More...

struct	_clock_audio_pll_config
	PLL configuration for AUDIO and VIDEO. More...

struct	_clock_audio_pll_gpc_config
	PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. More...

struct	_clock_enet_pll_config
	PLL configuration for ENET. More...

struct	_clock_root_config_t
	Clock root configuration. More...

struct	_clock_root_setpoint_config_t
	Clock root configuration in SetPoint Mode. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CCSR_OFFSET 0x0C
	CCM registers offset.

#define	ARM_PLL_OFFSET 0x00
	CCM Analog registers offset.

#define	CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) \| (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.

#define	SYS_PLL1_FREQ (1000000000UL)
	SYS_PLL_FREQ frequency in Hz.

#define	LPADC_CLOCKS
	Clock gate name array for ADC. More...

#define	ADC_ETC_CLOCKS
	Clock gate name array for ADC. More...

#define	AOI_CLOCKS
	Clock gate name array for AOI. More...

#define	DCDC_CLOCKS
	Clock gate name array for DCDC. More...

#define	DCDC_CLOCKS
	Clock gate name array for DCDC. More...

#define	SRC_CLOCKS
	Clock gate name array for SRC. More...

#define	GPC_CLOCKS
	Clock gate name array for GPC. More...

#define	SSARC_CLOCKS
	Clock gate name array for SSARC. More...

#define	WDOG_CLOCKS
	Clock gate name array for WDOG. More...

#define	EWM_CLOCKS
	Clock gate name array for EWM. More...

#define	SEMA_CLOCKS
	Clock gate name array for Sema. More...

#define	MU_CLOCKS
	Clock gate name array for MU. More...

#define	EDMA_CLOCKS
	Clock gate name array for EDMA. More...

#define	FLEXRAM_CLOCKS
	Clock gate name array for FLEXRAM. More...

#define	LMEM_CLOCKS
	Clock gate name array for LMEM. More...

#define	FLEXSPI_CLOCKS
	Clock gate name array for FLEXSPI. More...

#define	RDC_CLOCKS
	Clock gate name array for RDC. More...

#define	SEMC_CLOCKS
	Clock ip name array for SEMC. More...

#define	XECC_CLOCKS
	Clock ip name array for XECC. More...

#define	IEE_CLOCKS
	Clock ip name array for IEE. More...

#define	KEYMANAGER_CLOCKS
	Clock ip name array for KEY_MANAGER. More...

#define	PUF_CLOCKS
	Clock ip name array for PUF. More...

#define	OCOTP_CLOCKS
	Clock ip name array for OCOTP. More...

#define	CAAM_CLOCKS
	Clock ip name array for CAAM. More...

#define	XBAR_CLOCKS
	Clock ip name array for XBAR. More...

#define	IOMUXC_CLOCKS
	Clock ip name array for IOMUXC. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	KPP_CLOCKS
	Clock ip name array for KPP. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	PIT_CLOCKS
	Clock ip name array for PIT. More...

#define	GPT_CLOCKS
	Clock ip name array for GPT. More...

#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...

#define	ENC_CLOCKS
	Clock ip name array for ENC. More...

#define	PWM_CLOCKS
	Clock ip name array for PWM. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	EMVSIM_CLOCKS
	Clock ip name array for EMVSIM. More...

#define	ENET_CLOCKS
	Clock ip name array for ENET. More...

#define	ENETQOS_CLOCKS
	Clock ip name array for ENET_QOS. More...

#define	USB_CLOCKS
	Clock ip name array for USB. More...

#define	CDOG_CLOCKS
	Clock ip name array for CDOG. More...

#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...

#define	ASRC_CLOCKS
	Clock ip name array for ASRC. More...

#define	MQS_CLOCKS
	Clock ip name array for MQS. More...

#define	PDM_CLOCKS
	Clock ip name array for PDM. More...

#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	PXP_CLOCKS
	Clock ip name array for PXP. More...

#define	GPU2D_CLOCKS
	Clock ip name array for GPU2d. More...

#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF. More...

#define	LCDIFV2_CLOCKS
	Clock ip name array for LCDIFV2. More...

#define	MIPI_DSI_HOST_CLOCKS
	Clock ip name array for MIPI_DSI. More...

#define	MIPI_CSI2RX_CLOCKS
	Clock ip name array for MIPI_CSI. More...

#define	CSI_CLOCKS
	Clock ip name array for CSI. More...

#define	DCIC_CLOCKS
	Clock ip name array for DCIC. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS. More...

#define	XBARA_CLOCKS
	Clock ip name array for XBARA. More...

#define	XBARB_CLOCKS
	Clock ip name array for XBARB. More...

#define	CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
	For compatible with other platforms without CCM. More...

Typedefs
typedef enum _clock_lpcg	clock_lpcg_t
	Clock LPCG index.

typedef enum _clock_name	clock_name_t
	Clock name.

typedef enum _clock_root	clock_root_t
	Root clock index. More...

typedef enum _clock_root_mux_source	clock_root_mux_source_t
	The enumerator of clock roots' clock source mux value.

typedef enum _clock_group	clock_group_t
	Clock group enumeration.

typedef struct _clock_group_config	clock_group_config_t
	The structure used to configure clock group.

typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select.

typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value.

typedef enum _clock_mode_t	clock_mode_t
	System clock mode.

typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...

typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY. More...

typedef enum _clock_pll_post_div	clock_pll_post_div_t
	PLL post divider enumeration.

typedef struct _clock_arm_pll_config	clock_arm_pll_config_t
	PLL configuration for ARM. More...

typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB.

typedef struct _clock_pll_ss_config	clock_pll_ss_config_t
	Spread specturm configure Pll.

typedef struct _clock_sys_pll2_config	clock_sys_pll2_config_t
	PLL configure for Sys Pll2.

typedef struct _clock_sys_pll1_config	clock_sys_pll1_config_t
	PLL configure for Sys Pll1.

typedef struct _clock_audio_pll_config	clock_av_pll_config_t
	PLL configuration for AUDIO and VIDEO.

typedef struct _clock_audio_pll_gpc_config	clock_audio_pll_gpc_config_t
	PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.

typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET.

typedef struct _clock_root_config_t	clock_root_config_t
	Clock root configuration.

typedef struct _clock_root_setpoint_config_t	clock_root_setpoint_config_t
	Clock root configuration in SetPoint Mode.

typedef enum _clock_pll	clock_pll_t
	PLL name.

typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name.

typedef enum _clock_control_mode	clock_control_mode_t
	The enumeration of control mode.

typedef enum _clock_24MOsc_mode	clock_24MOsc_mode_t
	The enumeration of 24MHz crystal oscillator mode.

typedef enum _clock_16MOsc_source	clock_16MOsc_source_t
	The enumeration of 16MHz RC oscillator clock source.

typedef enum _clock_1MHzOut_behavior	clock_1MHzOut_behavior_t
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

typedef enum _clock_level	clock_level_t
	The clock dependence level.

Enumerations
enum	_clock_lpcg { kCLOCK_M7 = 0, kCLOCK_M4 = 1, kCLOCK_Sim_M7 = 2, kCLOCK_Sim_M = 3, kCLOCK_Sim_Disp = 4, kCLOCK_Sim_Per = 5, kCLOCK_Sim_Lpsr = 6, kCLOCK_Anadig = 7, kCLOCK_Dcdc = 8, kCLOCK_Src = 9, kCLOCK_Ccm = 10, kCLOCK_Gpc = 11, kCLOCK_Ssarc = 12, kCLOCK_Sim_R = 13, kCLOCK_Wdog1 = 14, kCLOCK_Wdog2 = 15, kCLOCK_Wdog3 = 16, kCLOCK_Wdog4 = 17, kCLOCK_Ewm0 = 18, kCLOCK_Sema = 19, kCLOCK_Mu_A = 20, kCLOCK_Mu_B = 21, kCLOCK_Edma = 22, kCLOCK_Edma_Lpsr = 23, kCLOCK_Romcp = 24, kCLOCK_Ocram = 25, kCLOCK_Flexram = 26, kCLOCK_Lmem = 27, kCLOCK_Flexspi1 = 28, kCLOCK_Flexspi2 = 29, kCLOCK_Rdc = 30, kCLOCK_M7_Xrdc = 31, kCLOCK_M4_Xrdc = 32, kCLOCK_Semc = 33, kCLOCK_Xecc = 34, kCLOCK_Iee = 35, kCLOCK_Key_Manager = 36, kCLOCK_Puf = 36, kCLOCK_Ocotp = 37, kCLOCK_Snvs_Hp = 38, kCLOCK_Snvs = 39, kCLOCK_Caam = 40, kCLOCK_Jtag_Mux = 41, kCLOCK_Cstrace = 42, kCLOCK_Xbar1 = 43, kCLOCK_Xbar2 = 44, kCLOCK_Xbar3 = 45, kCLOCK_Aoi1 = 46, kCLOCK_Aoi2 = 47, kCLOCK_Adc_Etc = 48, kCLOCK_Iomuxc = 49, kCLOCK_Iomuxc_Lpsr = 50, kCLOCK_Gpio = 51, kCLOCK_Kpp = 52, kCLOCK_Flexio1 = 53, kCLOCK_Flexio2 = 54, kCLOCK_Lpadc1 = 55, kCLOCK_Lpadc2 = 56, kCLOCK_Dac = 57, kCLOCK_Acmp1 = 58, kCLOCK_Acmp2 = 59, kCLOCK_Acmp3 = 60, kCLOCK_Acmp4 = 61, kCLOCK_Pit1 = 62, kCLOCK_Pit2 = 63, kCLOCK_Gpt1 = 64, kCLOCK_Gpt2 = 65, kCLOCK_Gpt3 = 66, kCLOCK_Gpt4 = 67, kCLOCK_Gpt5 = 68, kCLOCK_Gpt6 = 69, kCLOCK_Qtimer1 = 70, kCLOCK_Qtimer2 = 71, kCLOCK_Qtimer3 = 72, kCLOCK_Qtimer4 = 73, kCLOCK_Enc1 = 74, kCLOCK_Enc2 = 75, kCLOCK_Enc3 = 76, kCLOCK_Enc4 = 77, kCLOCK_Hrtimer = 78, kCLOCK_Pwm1 = 79, kCLOCK_Pwm2 = 80, kCLOCK_Pwm3 = 81, kCLOCK_Pwm4 = 82, kCLOCK_Can1 = 83, kCLOCK_Can2 = 84, kCLOCK_Can3 = 85, kCLOCK_Lpuart1 = 86, kCLOCK_Lpuart2 = 87, kCLOCK_Lpuart3 = 88, kCLOCK_Lpuart4 = 89, kCLOCK_Lpuart5 = 90, kCLOCK_Lpuart6 = 91, kCLOCK_Lpuart7 = 92, kCLOCK_Lpuart8 = 93, kCLOCK_Lpuart9 = 94, kCLOCK_Lpuart10 = 95, kCLOCK_Lpuart11 = 96, kCLOCK_Lpuart12 = 97, kCLOCK_Lpi2c1 = 98, kCLOCK_Lpi2c2 = 99, kCLOCK_Lpi2c3 = 100, kCLOCK_Lpi2c4 = 101, kCLOCK_Lpi2c5 = 102, kCLOCK_Lpi2c6 = 103, kCLOCK_Lpspi1 = 104, kCLOCK_Lpspi2 = 105, kCLOCK_Lpspi3 = 106, kCLOCK_Lpspi4 = 107, kCLOCK_Lpspi5 = 108, kCLOCK_Lpspi6 = 109, kCLOCK_Sim1 = 110, kCLOCK_Sim2 = 111, kCLOCK_Enet = 112, kCLOCK_Enet_1g = 113, kCLOCK_Enet_Qos = 114, kCLOCK_Usb = 115, kCLOCK_Cdog = 116, kCLOCK_Usdhc1 = 117, kCLOCK_Usdhc2 = 118, kCLOCK_Asrc = 119, kCLOCK_Mqs = 120, kCLOCK_Pdm = 121, kCLOCK_Spdif = 122, kCLOCK_Sai1 = 123, kCLOCK_Sai2 = 124, kCLOCK_Sai3 = 125, kCLOCK_Sai4 = 126, kCLOCK_Pxp = 127, kCLOCK_Gpu2d = 128, kCLOCK_Lcdif = 129, kCLOCK_Lcdifv2 = 130, kCLOCK_Mipi_Dsi = 131, kCLOCK_Mipi_Csi = 132, kCLOCK_Csi = 133, kCLOCK_Dcic_Mipi = 134, kCLOCK_Dcic_Lcd = 135, kCLOCK_Video_Mux = 136, kCLOCK_Uniq_Edt_I = 137, kCLOCK_IpInvalid }
	Clock LPCG index. More...

enum	_clock_name { kCLOCK_OscRc16M = 0, kCLOCK_OscRc48M = 1, kCLOCK_OscRc48MDiv2 = 2, kCLOCK_OscRc400M = 3, kCLOCK_Osc24M = 4, kCLOCK_Osc24MOut = 5, kCLOCK_ArmPll = 6, kCLOCK_ArmPllOut = 7, kCLOCK_SysPll2 = 8, kCLOCK_SysPll2Out = 9, kCLOCK_SysPll2Pfd0 = 10, kCLOCK_SysPll2Pfd1 = 11, kCLOCK_SysPll2Pfd2 = 12, kCLOCK_SysPll2Pfd3 = 13, kCLOCK_SysPll3 = 14, kCLOCK_SysPll3Out = 15, kCLOCK_SysPll3Div2 = 16, kCLOCK_SysPll3Pfd0 = 17, kCLOCK_SysPll3Pfd1 = 18, kCLOCK_SysPll3Pfd2 = 19, kCLOCK_SysPll3Pfd3 = 20, kCLOCK_SysPll1 = 21, kCLOCK_SysPll1Out = 22, kCLOCK_SysPll1Div2 = 23, kCLOCK_SysPll1Div5 = 24, kCLOCK_AudioPll = 25, kCLOCK_AudioPllOut = 26, kCLOCK_VideoPll = 27, kCLOCK_VideoPllOut = 28, kCLOCK_CpuClk, kCLOCK_CoreSysClk }
	Clock name. More...

enum	_clock_root { kCLOCK_Root_M7 = 0, kCLOCK_Root_M4 = 1, kCLOCK_Root_Bus = 2, kCLOCK_Root_Bus_Lpsr = 3, kCLOCK_Root_Semc = 4, kCLOCK_Root_Cssys = 5, kCLOCK_Root_Cstrace = 6, kCLOCK_Root_M4_Systick = 7, kCLOCK_Root_M7_Systick = 8, kCLOCK_Root_Adc1 = 9, kCLOCK_Root_Adc2 = 10, kCLOCK_Root_Acmp = 11, kCLOCK_Root_Flexio1 = 12, kCLOCK_Root_Flexio2 = 13, kCLOCK_Root_Gpt1 = 14, kCLOCK_Root_Gpt2 = 15, kCLOCK_Root_Gpt3 = 16, kCLOCK_Root_Gpt4 = 17, kCLOCK_Root_Gpt5 = 18, kCLOCK_Root_Gpt6 = 19, kCLOCK_Root_Flexspi1 = 20, kCLOCK_Root_Flexspi2 = 21, kCLOCK_Root_Can1 = 22, kCLOCK_Root_Can2 = 23, kCLOCK_Root_Can3 = 24, kCLOCK_Root_Lpuart1 = 25, kCLOCK_Root_Lpuart2 = 26, kCLOCK_Root_Lpuart3 = 27, kCLOCK_Root_Lpuart4 = 28, kCLOCK_Root_Lpuart5 = 29, kCLOCK_Root_Lpuart6 = 30, kCLOCK_Root_Lpuart7 = 31, kCLOCK_Root_Lpuart8 = 32, kCLOCK_Root_Lpuart9 = 33, kCLOCK_Root_Lpuart10 = 34, kCLOCK_Root_Lpuart11 = 35, kCLOCK_Root_Lpuart12 = 36, kCLOCK_Root_Lpi2c1 = 37, kCLOCK_Root_Lpi2c2 = 38, kCLOCK_Root_Lpi2c3 = 39, kCLOCK_Root_Lpi2c4 = 40, kCLOCK_Root_Lpi2c5 = 41, kCLOCK_Root_Lpi2c6 = 42, kCLOCK_Root_Lpspi1 = 43, kCLOCK_Root_Lpspi2 = 44, kCLOCK_Root_Lpspi3 = 45, kCLOCK_Root_Lpspi4 = 46, kCLOCK_Root_Lpspi5 = 47, kCLOCK_Root_Lpspi6 = 48, kCLOCK_Root_Emv1 = 49, kCLOCK_Root_Emv2 = 50, kCLOCK_Root_Enet1 = 51, kCLOCK_Root_Enet2 = 52, kCLOCK_Root_Enet_Qos = 53, kCLOCK_Root_Enet_25m = 54, kCLOCK_Root_Enet_Timer1 = 55, kCLOCK_Root_Enet_Timer2 = 56, kCLOCK_Root_Enet_Timer3 = 57, kCLOCK_Root_Usdhc1 = 58, kCLOCK_Root_Usdhc2 = 59, kCLOCK_Root_Asrc = 60, kCLOCK_Root_Mqs = 61, kCLOCK_Root_Mic = 62, kCLOCK_Root_Spdif = 63, kCLOCK_Root_Sai1 = 64, kCLOCK_Root_Sai2 = 65, kCLOCK_Root_Sai3 = 66, kCLOCK_Root_Sai4 = 67, kCLOCK_Root_Gc355 = 68, kCLOCK_Root_Lcdif = 69, kCLOCK_Root_Lcdifv2 = 70, kCLOCK_Root_Mipi_Ref = 71, kCLOCK_Root_Mipi_Esc = 72, kCLOCK_Root_Csi2 = 73, kCLOCK_Root_Csi2_Esc = 74, kCLOCK_Root_Csi2_Ui = 75, kCLOCK_Root_Csi = 76, kCLOCK_Root_Cko1 = 77, kCLOCK_Root_Cko2 = 78 }
	Root clock index. More...

enum	_clock_root_mux_source { kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U, kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U, kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U, kCLOCK_M7_ClockRoot_MuxSysPll1Out = 5U, kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U, kCLOCK_M7_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U, kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U, kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U, kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U, kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U, kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U, kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U, kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U, kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U, kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U, kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U, kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U, kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U, kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U, kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U, kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U, kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U, kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U, kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U, kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U, kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U, kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U, kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U, kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U, kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U, kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U, kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U, kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U, kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U, kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U, kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U, kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U, kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U, kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U, kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U, kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U, kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2 = 4U, kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut = 5U, kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1 = 7U, kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U, kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U, kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U, kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U, kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U, kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U, kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U, kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U, kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U, kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U, kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U, kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U, kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U, kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U, kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U, kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U, kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U, kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U, kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U, kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U, kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U, kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U, kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U, kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U, kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U, kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U, kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U, kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U, kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U, kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U, kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U, kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U, kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U, kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U, kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U, kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U, kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U, kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U, kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U, kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U, kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U, kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U, kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U, kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U, kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U, kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U, kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U, kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U, kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U, kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U, kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U, kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U, kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U, kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U, kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U, kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U, kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U, kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U, kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U, kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U, kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U, kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U, kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U }
	The enumerator of clock roots' clock source mux value. More...

enum	_clock_group { kCLOCK_Group_FlexRAM = 0, kCLOCK_Group_MipiDsi = 1, kCLOCK_Group_Last }
	Clock group enumeration. More...

enum	_clock_osc { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...

enum	_clock_gate_value { kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK }
	Clock gate value. More...

enum	_clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...

enum	_clock_usb_src { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...

enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...

enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...

enum	_clock_pll_post_div { kCLOCK_PllPostDiv2 = 0U, kCLOCK_PllPostDiv4 = 1U, kCLOCK_PllPostDiv8 = 2U, kCLOCK_PllPostDiv1 = 3U }
	PLL post divider enumeration. More...

enum	_clock_pll { kCLOCK_PllArm, kCLOCK_PllSys1, kCLOCK_PllSys2, kCLOCK_PllSys3, kCLOCK_PllAudio, kCLOCK_PllVideo, kCLOCK_PllInvalid = -1 }
	PLL name. More...

enum	_clock_pfd { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...

enum	_clock_control_mode { kCLOCK_SoftwareMode = 0U, kCLOCK_GpcMode }
	The enumeration of control mode. More...

enum	_clock_24MOsc_mode { kCLOCK_24MOscHighGainMode = 0U, kCLOCK_24MOscBypassMode = 1U, kCLOCK_24MOscLowPowerMode = 2U }
	The enumeration of 24MHz crystal oscillator mode. More...

enum	_clock_16MOsc_source { kCLOCK_16MOscSourceFrom16MOsc = 0U, kCLOCK_16MOscSourceFrom24MOsc = 1U }
	The enumeration of 16MHz RC oscillator clock source. More...

enum	_clock_1MHzOut_behavior { kCLOCK_1MHzOutDisable = 0U, kCLOCK_1MHzOutEnableLocked1Mhz = 1U, kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U }
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. More...

enum	_clock_level { kCLOCK_Level0 = 0x0UL, kCLOCK_Level1 = 0x1UL, kCLOCK_Level2 = 0x2UL, kCLOCK_Level3 = 0x3UL, kCLOCK_Level4 = 0x4UL }
	The clock dependence level. More...

Functions
static void	CLOCK_SetRootClockMux (clock_root_t root, uint8_t src)
	Set CCM Root Clock MUX node to certain value. More...

static uint32_t	CLOCK_GetRootClockMux (clock_root_t root)
	Get CCM Root Clock MUX value. More...

static clock_name_t	CLOCK_GetRootClockSource (clock_root_t root, uint32_t src)
	Get CCM Root Clock Source. More...

static void	CLOCK_SetRootClockDiv (clock_root_t root, uint32_t div)
	Set CCM Root Clock DIV certain value. More...

static uint32_t	CLOCK_GetRootClockDiv (clock_root_t root)
	Get CCM DIV node value. More...

static void	CLOCK_PowerOffRootClock (clock_root_t root)
	Power Off Root Clock. More...

static void	CLOCK_PowerOnRootClock (clock_root_t root)
	Power On Root Clock. More...

static void	CLOCK_SetRootClock (clock_root_t root, const clock_root_config_t *config)
	Configure Root Clock. More...

static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...

static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

void	CLOCK_SetGroupConfig (clock_group_t group, const clock_group_config_t *config)
	Set the clock group configuration. More...

uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...

static uint32_t	CLOCK_GetRootClockFreq (clock_root_t root)
	Gets the clock frequency for a specific root clock name. More...

static uint32_t	CLOCK_GetM7Freq (void)
	Get the CCM CPU/core/system frequency. More...

static uint32_t	CLOCK_GetM4Freq (void)
	Get the CCM CPU/core/system frequency. More...

static bool	CLOCK_IsPllBypassed (clock_pll_t pll)
	Check if PLL is bypassed. More...

static bool	CLOCK_IsPllEnabled (clock_pll_t pll)
	Check if PLL is enabled. More...

void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL. More...

status_t	CLOCK_CalcArmPllFreq (clock_arm_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitArmPllWithFreq (uint32_t freqInMhz)
	Initializes the Arm PLL with Specific Frequency (in Mhz). More...

void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL.

void	CLOCK_CalcPllSpreadSpectrum (uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
	Calculate spread spectrum step and stop. More...

void	CLOCK_InitSysPll1 (const clock_sys_pll1_config_t *config)
	Initialize the System PLL1. More...

void	CLOCK_DeinitSysPll1 (void)
	De-initialize the System PLL1.

void	CLOCK_GPC_SetSysPll1OutputFreq (const clock_sys_pll1_gpc_config_t *config)
	Set System PLL1 output frequency in GPC mode. More...

void	CLOCK_InitSysPll2 (const clock_sys_pll2_config_t *config)
	Initialize the System PLL2. More...

void	CLOCK_DeinitSysPll2 (void)
	De-initialize the System PLL2.

bool	CLOCK_IsSysPll2PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL2 PFD is enabled. More...

void	CLOCK_InitSysPll3 (void)
	Initialize the System PLL3. More...

void	CLOCK_DeinitSysPll3 (void)
	De-initialize the System PLL3.

bool	CLOCK_IsSysPll3PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL3 PFD is enabled. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 5))
	CLOCK driver version. More...

#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)

OSC operations
static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...

static void	CLOCK_OSC_SetOsc48MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 48MHz RC oscillator. More...

static void	CLOCK_OSC_EnableOsc48M (bool enable)
	Enable/disable 48MHz RC oscillator. More...

static void	CLOCK_OSC_SetOsc48MDiv2ControlMode (clock_control_mode_t controlMode)
	Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator. More...

static void	CLOCK_OSC_EnableOsc48MDiv2 (bool enable)
	Enable/disable the 24MHz clock sourced from 48MHz RC oscillator. More...

static void	CLOCK_OSC_SetOsc24MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 24MHz crystal oscillator. More...

void	CLOCK_OSC_EnableOsc24M (void)
	Enable OSC 24Mhz. More...

static void	CLOCK_OSC_GateOsc24M (bool enableGate)
	Gate/ungate the 24MHz crystal oscillator output. More...

void	CLOCK_OSC_SetOsc24MWorkMode (clock_24MOsc_mode_t workMode)
	Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode. More...

static void	CLOCK_OSC_SetOscRc400MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 400MHz RC oscillator. More...

void	CLOCK_OSC_EnableOscRc400M (void)
	Enable OSC RC 400Mhz. More...

static void	CLOCK_OSC_GateOscRc400M (bool enableGate)
	Gate/ungate 400MHz RC oscillator. More...

void	CLOCK_OSC_TrimOscRc400M (bool enable, bool bypass, uint16_t trim)
	Trims OSC RC 400MHz. More...

void	CLOCK_OSC_SetOscRc400MRefClkDiv (uint8_t divValue)
	Set the divide value for ref_clk to generate slow clock. More...

void	CLOCK_OSC_SetOscRc400MFastClkCount (uint16_t targetCount)
	Set the target count for the fast clock. More...

void	CLOCK_OSC_SetOscRc400MHysteresisValue (uint8_t negHysteresis, uint8_t posHysteresis)
	Set the negative and positive hysteresis value for the tuned clock. More...

void	CLOCK_OSC_BypassOscRc400MTuneLogic (bool enableBypass)
	Bypass/un-bypass the tune logic. More...

void	CLOCK_OSC_EnableOscRc400MTuneLogic (bool enable)
	Start/Stop the tune logic. More...

void	CLOCK_OSC_FreezeOscRc400MTuneValue (bool enableFreeze)
	Freeze/Unfreeze the tuning value. More...

void	CLOCK_OSC_SetOscRc400MTuneValue (uint8_t tuneValue)
	Set the 400MHz RC oscillator tune value when the tune logic is disabled. More...

void	CLOCK_OSC_Set1MHzOutputBehavior (clock_1MHzOut_behavior_t behavior)
	Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output. More...

void	CLOCK_OSC_SetLocked1MHzCount (uint16_t count)
	Set the count for the locked 1MHz clock out. More...

bool	CLOCK_OSC_CheckLocked1MHzErrorFlag (void)
	Check the error flag for locked 1MHz clock out. More...

void	CLOCK_OSC_ClearLocked1MHzErrorFlag (void)
	Clear the error flag for locked 1MHz clock out.

uint16_t	CLOCK_OSC_GetCurrentOscRc400MFastClockCount (void)
	Get current count for the fast clock during the tune process. More...

uint8_t	CLOCK_OSC_GetCurrentOscRc400MTuneValue (void)
	Get current tune value used by oscillator during tune process. More...

static void	CLOCK_OSC_SetOsc16MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 16MHz crystal oscillator. More...

void	CLOCK_OSC_SetOsc16MConfig (clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)
	Configure the 16MHz oscillator. More...

PLL/PFD operations
void	CLOCK_SetPllBypass (clock_pll_t pll, bool bypass)
	PLL bypass setting. More...

status_t	CLOCK_CalcAvPllFreq (clock_av_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitAudioPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Audio PLL with Specific Frequency (in Mhz). More...

void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...

void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL.

void	CLOCK_GPC_SetAudioPllOutputFreq (const clock_audio_pll_gpc_config_t *config)
	Set Audio PLL output frequency in GPC mode. More...

status_t	CLOCK_InitVideoPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Video PLL with Specific Frequency (in Mhz). More...

void	CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
	Initialize the video PLL. More...

void	CLOCK_DeinitVideoPll (void)
	De-initialize the Video PLL.

void	CLOCK_GPC_SetVideoPllOutputFreq (const clock_video_pll_gpc_config_t *config)
	Set Video PLL output frequency in GPC mode. More...

uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...

void	CLOCK_InitPfd (clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
	Initialize PLL PFD. More...

void	CLOCK_DeinitPfd (clock_pll_t pll, clock_pfd_t pfd)
	De-initialize selected PLL PFD. More...

uint32_t	CLOCK_GetPfdFreq (clock_pll_t pll, clock_pfd_t pfd)
	Get current PFD output frequency. More...

uint32_t	CLOCK_GetFreqFromObs (uint32_t obsSigIndex, uint32_t obsIndex)

bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

static void	CLOCK_OSCPLL_LockControlMode (clock_name_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_OSCPLL_LockWhiteList (clock_name_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_OSCPLL_SetWhiteList (clock_name_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_OSCPLL_IsSetPointImplemented (clock_name_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_OSCPLL_ControlByUnassignedMode (clock_name_t name)
	Set this clock works in Unassigned Mode. More...

void	CLOCK_OSCPLL_ControlBySetPointMode (clock_name_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode. More...

void	CLOCK_OSCPLL_ControlByCpuLowPowerMode (clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_OSCPLL_SetCurrentClockLevel (clock_name_t name, clock_level_t level)
	Set clock depend level for current accessing domain. More...

static void	CLOCK_OSCPLL_ControlByDomainMode (clock_name_t name, uint8_t domainId)
	Set this clock works in Domain Mode. More...

static void	CLOCK_ROOT_LockControlMode (clock_root_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_ROOT_LockWhiteList (clock_root_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_ROOT_SetWhiteList (clock_root_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_ROOT_IsSetPointImplemented (clock_root_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_ROOT_ControlByUnassignedMode (clock_root_t name)
	Set this clock works in Unassigned Mode. More...

static void	CLOCK_ROOT_ConfigSetPoint (clock_root_t name, uint16_t spIndex, const clock_root_setpoint_config_t *config)
	Configure one SetPoint for this clock. More...

static void	CLOCK_ROOT_EnableSetPointControl (clock_root_t name)
	Enable SetPoint control for this clock root. More...

void	CLOCK_ROOT_ControlBySetPointMode (clock_root_t name, const clock_root_setpoint_config_t *spTable)
	Set this clock works in SetPoint controlled Mode. More...

static void	CLOCK_ROOT_ControlByDomainMode (clock_root_t name, uint8_t domainId)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_LPCG_LockControlMode (clock_lpcg_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_LPCG_LockWhiteList (clock_lpcg_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_LPCG_SetWhiteList (clock_lpcg_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_LPCG_IsSetPointImplemented (clock_lpcg_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_LPCG_ControlByUnassignedMode (clock_lpcg_t name)
	Set this clock works in Unassigned Mode. More...

void	CLOCK_LPCG_ControlBySetPointMode (clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode. More...

void	CLOCK_LPCG_ControlByCpuLowPowerMode (clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_LPCG_SetCurrentClockLevel (clock_lpcg_t name, clock_level_t level)
	Set clock depend level for current accessing domain. More...

static void	CLOCK_LPCG_ControlByDomainMode (clock_lpcg_t name, uint8_t domainId)
	Set this clock works in Domain Mode. More...

Data Structure Documentation

struct _clock_group_config

Data Fields
bool	clockOff
	Turn off the clock. More...

uint16_t	resetDiv
	resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255. More...

uint8_t	div0
	Divide root clock by div0 + 1, valid range: 0 ~ 15. More...

Field Documentation

bool _clock_group_config::clockOff

uint16_t _clock_group_config::resetDiv

uint8_t _clock_group_config::div0

struct _clock_arm_pll_config

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

Data Fields
clock_pll_post_div_t	postDivider
	Post divider. More...

uint32_t	loopDivider
	PLL loop divider. More...

Field Documentation

clock_pll_post_div_t _clock_arm_pll_config::postDivider

uint32_t _clock_arm_pll_config::loopDivider

Valid range: 104-208.

struct _clock_usb_pll_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

uint8_t _clock_usb_pll_config::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct _clock_pll_ss_config

Data Fields
uint16_t	stop
	Spread spectrum stop value to get frequency change. More...

uint16_t	step
	Spread spectrum step value to get frequency change step. More...

Field Documentation

uint16_t _clock_pll_ss_config::stop

uint16_t _clock_pll_ss_config::step

struct _clock_sys_pll2_config

Data Fields
uint32_t	mfd
	Denominator of spread spectrum.

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

struct _clock_sys_pll1_config

Data Fields
bool	pllDiv2En
	Enable Sys Pll1 divide-by-2 clock or not. More...

bool	pllDiv5En
	Enable Sys Pll1 divide-by-5 clock or not. More...

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

bool _clock_sys_pll1_config::pllDiv2En

bool _clock_sys_pll1_config::pllDiv5En

struct _clock_audio_pll_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	postDivider
	Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

uint8_t _clock_audio_pll_config::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t _clock_audio_pll_config::postDivider

uint32_t _clock_audio_pll_config::numerator

struct _clock_audio_pll_gpc_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

uint8_t _clock_audio_pll_gpc_config::loopDivider

uint32_t _clock_audio_pll_gpc_config::numerator

struct _clock_enet_pll_config

Data Fields
bool	enableClkOutput
	Power on and enable PLL clock output for ENET0 (ref_enetpll0). More...

bool	enableClkOutput25M
	Power on and enable PLL clock output for ENET2 (ref_enetpll2). More...

uint8_t	loopDivider
	Controls the frequency of the ENET0 reference clock. More...

uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

bool	enableClkOutput1
	Power on and enable PLL clock output for ENET1 (ref_enetpll1). More...

uint8_t	loopDivider1
	Controls the frequency of the ENET1 reference clock. More...

Field Documentation

bool _clock_enet_pll_config::enableClkOutput

bool _clock_enet_pll_config::enableClkOutput25M

uint8_t _clock_enet_pll_config::loopDivider

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

bool _clock_enet_pll_config::enableClkOutput1

uint8_t _clock_enet_pll_config::loopDivider1

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

struct _clock_root_config_t

Data Fields
uint8_t	mux
	See clock_root_mux_source_t for details. More...

uint8_t	div
	it's the actual divider

Field Documentation

uint8_t _clock_root_config_t::mux

struct _clock_root_setpoint_config_t

Data Fields
uint8_t	grade
	Indicate speed grade for each SetPoint.

uint8_t	mux
	See clock_root_mux_source_t for details. More...

uint8_t	div
	it's the actual divider

Field Documentation

uint8_t _clock_root_setpoint_config_t::mux

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 5))

#define LPADC_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
    }

#define ADC_ETC_CLOCKS

Value:

{                  \
        kCLOCK_Adc_Etc \
    }

#define AOI_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

#define SRC_CLOCKS

Value:

{              \
        kCLOCK_Src \
    }

#define GPC_CLOCKS

Value:

{              \
        kCLOCK_Gpc \
    }

#define SSARC_CLOCKS

Value:

{                \
        kCLOCK_Ssarc \
    }

#define WDOG_CLOCKS

Value:

{                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define SEMA_CLOCKS

Value:

{               \
        kCLOCK_Sema \
    }

#define MU_CLOCKS

Value:

{               \
        kCLOCK_Mu_B \
    }

#define EDMA_CLOCKS

Value:

{                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

#define FLEXRAM_CLOCKS

Value:

{                  \
        kCLOCK_Flexram \
    }

#define LMEM_CLOCKS

Value:

{               \
        kCLOCK_Lmem \
    }

#define FLEXSPI_CLOCKS

Value:

{                                                      \
        kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
    }

#define RDC_CLOCKS

Value:

{                                              \
        kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
    }

#define SEMC_CLOCKS

Value:

{               \
        kCLOCK_Semc \
    }

#define XECC_CLOCKS

Value:

{               \
        kCLOCK_Xecc \
    }

#define IEE_CLOCKS

Value:

{              \
        kCLOCK_Iee \
    }

#define KEYMANAGER_CLOCKS

Value:

{                      \
        kCLOCK_Key_Manager \
    }

#define PUF_CLOCKS

Value:

{              \
        kCLOCK_Puf \
    }

#define OCOTP_CLOCKS

Value:

{                \
        kCLOCK_Ocotp \
    }

#define CAAM_CLOCKS

Value:

{               \
        kCLOCK_Caam \
    }

#define XBAR_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

#define IOMUXC_CLOCKS

Value:

{                                     \
        kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
    }

#define GPIO_CLOCKS

Value:

{                                                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
            kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio,                            \
    }

#define KPP_CLOCKS

Value:

{              \
        kCLOCK_Kpp \
    }

#define FLEXIO_CLOCKS

Value:

{                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

#define DAC_CLOCKS

Value:

{              \
        kCLOCK_Dac \
    }

#define CMP_CLOCKS

Value:

{                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

#define PIT_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
    }

#define GPT_CLOCKS

Value:

{                                                                                                  \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
    }

#define TMR_CLOCKS

Value:

{                                                                                    \
        kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
    }

#define ENC_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

#define PWM_CLOCKS

Value:

{                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

#define FLEXCAN_CLOCKS

Value:

{                                                           \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
            kCLOCK_Lpuart12                                                                                   \
    }

#define LPI2C_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
    }

#define LPSPI_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
    }

#define EMVSIM_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
    }

#define ENET_CLOCKS

Value:

{                               \
        kCLOCK_Enet, kCLOCK_Enet_1g \
    }

#define ENETQOS_CLOCKS

Value:

{                   \
        kCLOCK_Enet_Qos \
    }

#define USB_CLOCKS

Value:

{              \
        kCLOCK_Usb \
    }

#define CDOG_CLOCKS

Value:

{               \
        kCLOCK_Cdog \
    }

#define USDHC_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

#define ASRC_CLOCKS

Value:

{               \
        kCLOCK_Asrc \
    }

#define MQS_CLOCKS

Value:

{              \
        kCLOCK_Mqs \
    }

#define PDM_CLOCKS

Value:

{              \
        kCLOCK_Pdm \
    }

#define SPDIF_CLOCKS

Value:

{                \
        kCLOCK_Spdif \
    }

#define SAI_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
    }

#define PXP_CLOCKS

Value:

{              \
        kCLOCK_Pxp \
    }

#define GPU2D_CLOCKS

Value:

{                \
        kCLOCK_Gpu2d \
    }

#define LCDIF_CLOCKS

Value:

{                \
        kCLOCK_Lcdif \
    }

#define LCDIFV2_CLOCKS

Value:

{                  \
        kCLOCK_Lcdifv2 \
    }

#define MIPI_DSI_HOST_CLOCKS

Value:

{                        \
        kCLOCK_Mipi_Dsi      \
    }

#define MIPI_CSI2RX_CLOCKS

Value:

{                      \
        kCLOCK_Mipi_Csi    \
    }

#define CSI_CLOCKS

Value:

{              \
        kCLOCK_Csi \
    }

#define DCIC_CLOCKS

Value:

{                                                       \
        kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
    }

#define DMAMUX_CLOCKS

Value:

{                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

#define XBARA_CLOCKS

Value:

{                                  \
        kCLOCK_IpInvalid, kCLOCK_Xbar1 \
    }

#define XBARB_CLOCKS

Value:

{                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

Typedef Documentation

typedef enum _clock_root clock_root_t

typedef enum _clock_usb_src clock_usb_src_t

typedef enum _clock_usb_phy_src clock_usb_phy_src_t

typedef struct _clock_arm_pll_config clock_arm_pll_config_t

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

Enumeration Type Documentation

enum _clock_lpcg

Enumerator
kCLOCK_M7	Clock LPCG M7.
kCLOCK_M4	Clock LPCG M4.
kCLOCK_Sim_M7	Clock LPCG SIM M7.
kCLOCK_Sim_M	Clock LPCG SIM M4.
kCLOCK_Sim_Disp	Clock LPCG SIM DISP.
kCLOCK_Sim_Per	Clock LPCG SIM PER.
kCLOCK_Sim_Lpsr	Clock LPCG SIM LPSR.
kCLOCK_Anadig	Clock LPCG Anadig.
kCLOCK_Dcdc	Clock LPCG DCDC.
kCLOCK_Src	Clock LPCG SRC.
kCLOCK_Ccm	Clock LPCG CCM.
kCLOCK_Gpc	Clock LPCG GPC.
kCLOCK_Ssarc	Clock LPCG SSARC.
kCLOCK_Sim_R	Clock LPCG SIM_R.
kCLOCK_Wdog1	Clock LPCG WDOG1.
kCLOCK_Wdog2	Clock LPCG WDOG2.
kCLOCK_Wdog3	Clock LPCG WDOG3.
kCLOCK_Wdog4	Clock LPCG WDOG4.
kCLOCK_Ewm0	Clock LPCG EWM0.
kCLOCK_Sema	Clock LPCG SEMA.
kCLOCK_Mu_A	Clock LPCG MU_A.
kCLOCK_Mu_B	Clock LPCG MU_B.
kCLOCK_Edma	Clock LPCG EDMA.
kCLOCK_Edma_Lpsr	Clock LPCG EDMA_LPSR.
kCLOCK_Romcp	Clock LPCG ROMCP.
kCLOCK_Ocram	Clock LPCG OCRAM.
kCLOCK_Flexram	Clock LPCG FLEXRAM.
kCLOCK_Lmem	Clock LPCG Lmem.
kCLOCK_Flexspi1	Clock LPCG Flexspi1.
kCLOCK_Flexspi2	Clock LPCG Flexspi2.
kCLOCK_Rdc	Clock LPCG RDC.
kCLOCK_M7_Xrdc	Clock LPCG M7 XRDC.
kCLOCK_M4_Xrdc	Clock LPCG M4 XRDC.
kCLOCK_Semc	Clock LPCG SEMC.
kCLOCK_Xecc	Clock LPCG XECC.
kCLOCK_Iee	Clock LPCG IEE.
kCLOCK_Key_Manager	Clock LPCG KEY_MANAGER.
kCLOCK_Puf	Clock LPCG PUF.
kCLOCK_Ocotp	Clock LPCG OSOTP.
kCLOCK_Snvs_Hp	Clock LPCG SNVS_HP.
kCLOCK_Snvs	Clock LPCG SNVS.
kCLOCK_Caam	Clock LPCG Caam.
kCLOCK_Jtag_Mux	Clock LPCG JTAG_MUX.
kCLOCK_Cstrace	Clock LPCG CSTRACE.
kCLOCK_Xbar1	Clock LPCG XBAR1.
kCLOCK_Xbar2	Clock LPCG XBAR2.
kCLOCK_Xbar3	Clock LPCG XBAR3.
kCLOCK_Aoi1	Clock LPCG AOI1.
kCLOCK_Aoi2	Clock LPCG AOI2.
kCLOCK_Adc_Etc	Clock LPCG ADC_ETC.
kCLOCK_Iomuxc	Clock LPCG IOMUXC.
kCLOCK_Iomuxc_Lpsr	Clock LPCG IOMUXC_LPSR.
kCLOCK_Gpio	Clock LPCG GPIO.
kCLOCK_Kpp	Clock LPCG KPP.
kCLOCK_Flexio1	Clock LPCG FLEXIO1.
kCLOCK_Flexio2	Clock LPCG FLEXIO2.
kCLOCK_Lpadc1	Clock LPCG LPADC1.
kCLOCK_Lpadc2	Clock LPCG LPADC2.
kCLOCK_Dac	Clock LPCG DAC.
kCLOCK_Acmp1	Clock LPCG ACMP1.
kCLOCK_Acmp2	Clock LPCG ACMP2.
kCLOCK_Acmp3	Clock LPCG ACMP3.
kCLOCK_Acmp4	Clock LPCG ACMP4.
kCLOCK_Pit1	Clock LPCG PIT1.
kCLOCK_Pit2	Clock LPCG PIT2.
kCLOCK_Gpt1	Clock LPCG GPT1.
kCLOCK_Gpt2	Clock LPCG GPT2.
kCLOCK_Gpt3	Clock LPCG GPT3.
kCLOCK_Gpt4	Clock LPCG GPT4.
kCLOCK_Gpt5	Clock LPCG GPT5.
kCLOCK_Gpt6	Clock LPCG GPT6.
kCLOCK_Qtimer1	Clock LPCG QTIMER1.
kCLOCK_Qtimer2	Clock LPCG QTIMER2.
kCLOCK_Qtimer3	Clock LPCG QTIMER3.
kCLOCK_Qtimer4	Clock LPCG QTIMER4.
kCLOCK_Enc1	Clock LPCG Enc1.
kCLOCK_Enc2	Clock LPCG Enc2.
kCLOCK_Enc3	Clock LPCG Enc3.
kCLOCK_Enc4	Clock LPCG Enc4.
kCLOCK_Hrtimer	Clock LPCG Hrtimer.
kCLOCK_Pwm1	Clock LPCG PWM1.
kCLOCK_Pwm2	Clock LPCG PWM2.
kCLOCK_Pwm3	Clock LPCG PWM3.
kCLOCK_Pwm4	Clock LPCG PWM4.
kCLOCK_Can1	Clock LPCG CAN1.
kCLOCK_Can2	Clock LPCG CAN2.
kCLOCK_Can3	Clock LPCG CAN3.
kCLOCK_Lpuart1	Clock LPCG LPUART1.
kCLOCK_Lpuart2	Clock LPCG LPUART2.
kCLOCK_Lpuart3	Clock LPCG LPUART3.
kCLOCK_Lpuart4	Clock LPCG LPUART4.
kCLOCK_Lpuart5	Clock LPCG LPUART5.
kCLOCK_Lpuart6	Clock LPCG LPUART6.
kCLOCK_Lpuart7	Clock LPCG LPUART7.
kCLOCK_Lpuart8	Clock LPCG LPUART8.
kCLOCK_Lpuart9	Clock LPCG LPUART9.
kCLOCK_Lpuart10	Clock LPCG LPUART10.
kCLOCK_Lpuart11	Clock LPCG LPUART11.
kCLOCK_Lpuart12	Clock LPCG LPUART12.
kCLOCK_Lpi2c1	Clock LPCG LPI2C1.
kCLOCK_Lpi2c2	Clock LPCG LPI2C2.
kCLOCK_Lpi2c3	Clock LPCG LPI2C3.
kCLOCK_Lpi2c4	Clock LPCG LPI2C4.
kCLOCK_Lpi2c5	Clock LPCG LPI2C5.
kCLOCK_Lpi2c6	Clock LPCG LPI2C6.
kCLOCK_Lpspi1	Clock LPCG LPSPI1.
kCLOCK_Lpspi2	Clock LPCG LPSPI2.
kCLOCK_Lpspi3	Clock LPCG LPSPI3.
kCLOCK_Lpspi4	Clock LPCG LPSPI4.
kCLOCK_Lpspi5	Clock LPCG LPSPI5.
kCLOCK_Lpspi6	Clock LPCG LPSPI6.
kCLOCK_Sim1	Clock LPCG SIM1.
kCLOCK_Sim2	Clock LPCG SIM2.
kCLOCK_Enet	Clock LPCG ENET.
kCLOCK_Enet_1g	Clock LPCG ENET 1G.
kCLOCK_Enet_Qos	Clock LPCG ENET QOS.
kCLOCK_Usb	Clock LPCG USB.
kCLOCK_Cdog	Clock LPCG CDOG.
kCLOCK_Usdhc1	Clock LPCG USDHC1.
kCLOCK_Usdhc2	Clock LPCG USDHC2.
kCLOCK_Asrc	Clock LPCG ASRC.
kCLOCK_Mqs	Clock LPCG MQS.
kCLOCK_Pdm	Clock LPCG PDM.
kCLOCK_Spdif	Clock LPCG SPDIF.
kCLOCK_Sai1	Clock LPCG SAI1.
kCLOCK_Sai2	Clock LPCG SAI2.
kCLOCK_Sai3	Clock LPCG SAI3.
kCLOCK_Sai4	Clock LPCG SAI4.
kCLOCK_Pxp	Clock LPCG PXP.
kCLOCK_Gpu2d	Clock LPCG GPU2D.
kCLOCK_Lcdif	Clock LPCG LCDIF.
kCLOCK_Lcdifv2	Clock LPCG LCDIFV2.
kCLOCK_Mipi_Dsi	Clock LPCG MIPI DSI.
kCLOCK_Mipi_Csi	Clock LPCG MIPI CSI.
kCLOCK_Csi	Clock LPCG CSI.
kCLOCK_Dcic_Mipi	Clock LPCG DCIC MIPI.
kCLOCK_Dcic_Lcd	Clock LPCG DCIC LCD.
kCLOCK_Video_Mux	Clock LPCG VIDEO MUX.
kCLOCK_Uniq_Edt_I	Clock LPCG Uniq_Edt_I.
kCLOCK_IpInvalid	Invalid value.

enum _clock_name

Enumerator
kCLOCK_OscRc16M	16MHz RC Oscillator.
kCLOCK_OscRc48M	48MHz RC Oscillator.
kCLOCK_OscRc48MDiv2	48MHz RC Oscillator Div2.
kCLOCK_OscRc400M	400MHz RC Oscillator.
kCLOCK_Osc24M	24MHz Oscillator.
kCLOCK_Osc24MOut	48MHz Oscillator Out.
kCLOCK_ArmPll	ARM PLL.
kCLOCK_ArmPllOut	ARM PLL Out.
kCLOCK_SysPll2	SYS PLL2.
kCLOCK_SysPll2Out	SYS PLL2 OUT.
kCLOCK_SysPll2Pfd0	SYS PLL2 PFD0.
kCLOCK_SysPll2Pfd1	SYS PLL2 PFD1.
kCLOCK_SysPll2Pfd2	SYS PLL2 PFD2.
kCLOCK_SysPll2Pfd3	SYS PLL2 PFD3.
kCLOCK_SysPll3	SYS PLL3.
kCLOCK_SysPll3Out	SYS PLL3 OUT.
kCLOCK_SysPll3Div2	SYS PLL3 DIV2.
kCLOCK_SysPll3Pfd0	SYS PLL3 PFD0.
kCLOCK_SysPll3Pfd1	SYS PLL3 PFD1.
kCLOCK_SysPll3Pfd2	SYS PLL3 PFD2.
kCLOCK_SysPll3Pfd3	SYS PLL3 PFD3.
kCLOCK_SysPll1	SYS PLL1.
kCLOCK_SysPll1Out	SYS PLL1 OUT.
kCLOCK_SysPll1Div2	SYS PLL1 DIV2.
kCLOCK_SysPll1Div5	SYS PLL1 DIV5.
kCLOCK_AudioPll	SYS AUDIO PLL.
kCLOCK_AudioPllOut	SYS AUDIO PLL OUT.
kCLOCK_VideoPll	SYS VIDEO PLL.
kCLOCK_VideoPllOut	SYS VIDEO PLL OUT.
kCLOCK_CpuClk	SYS CPU CLK.
kCLOCK_CoreSysClk	SYS CORE SYS CLK.

enum _clock_root

Enumerator
kCLOCK_Root_M7	CLOCK Root M7.
kCLOCK_Root_M4	CLOCK Root M4.
kCLOCK_Root_Bus	CLOCK Root Bus.
kCLOCK_Root_Bus_Lpsr	CLOCK Root Bus Lpsr.
kCLOCK_Root_Semc	CLOCK Root Semc.
kCLOCK_Root_Cssys	CLOCK Root Cssys.
kCLOCK_Root_Cstrace	CLOCK Root Cstrace.
kCLOCK_Root_M4_Systick	CLOCK Root M4 Systick.
kCLOCK_Root_M7_Systick	CLOCK Root M7 Systick.
kCLOCK_Root_Adc1	CLOCK Root Adc1.
kCLOCK_Root_Adc2	CLOCK Root Adc2.
kCLOCK_Root_Acmp	CLOCK Root Acmp.
kCLOCK_Root_Flexio1	CLOCK Root Flexio1.
kCLOCK_Root_Flexio2	CLOCK Root Flexio2.
kCLOCK_Root_Gpt1	CLOCK Root Gpt1.
kCLOCK_Root_Gpt2	CLOCK Root Gpt2.
kCLOCK_Root_Gpt3	CLOCK Root Gpt3.
kCLOCK_Root_Gpt4	CLOCK Root Gpt4.
kCLOCK_Root_Gpt5	CLOCK Root Gpt5.
kCLOCK_Root_Gpt6	CLOCK Root Gpt6.
kCLOCK_Root_Flexspi1	CLOCK Root Flexspi1.
kCLOCK_Root_Flexspi2	CLOCK Root Flexspi2.
kCLOCK_Root_Can1	CLOCK Root Can1.
kCLOCK_Root_Can2	CLOCK Root Can2.
kCLOCK_Root_Can3	CLOCK Root Can3.
kCLOCK_Root_Lpuart1	CLOCK Root Lpuart1.
kCLOCK_Root_Lpuart2	CLOCK Root Lpuart2.
kCLOCK_Root_Lpuart3	CLOCK Root Lpuart3.
kCLOCK_Root_Lpuart4	CLOCK Root Lpuart4.
kCLOCK_Root_Lpuart5	CLOCK Root Lpuart5.
kCLOCK_Root_Lpuart6	CLOCK Root Lpuart6.
kCLOCK_Root_Lpuart7	CLOCK Root Lpuart7.
kCLOCK_Root_Lpuart8	CLOCK Root Lpuart8.
kCLOCK_Root_Lpuart9	CLOCK Root Lpuart9.
kCLOCK_Root_Lpuart10	CLOCK Root Lpuart10.
kCLOCK_Root_Lpuart11	CLOCK Root Lpuart11.
kCLOCK_Root_Lpuart12	CLOCK Root Lpuart12.
kCLOCK_Root_Lpi2c1	CLOCK Root Lpi2c1.
kCLOCK_Root_Lpi2c2	CLOCK Root Lpi2c2.
kCLOCK_Root_Lpi2c3	CLOCK Root Lpi2c3.
kCLOCK_Root_Lpi2c4	CLOCK Root Lpi2c4.
kCLOCK_Root_Lpi2c5	CLOCK Root Lpi2c5.
kCLOCK_Root_Lpi2c6	CLOCK Root Lpi2c6.
kCLOCK_Root_Lpspi1	CLOCK Root Lpspi1.
kCLOCK_Root_Lpspi2	CLOCK Root Lpspi2.
kCLOCK_Root_Lpspi3	CLOCK Root Lpspi3.
kCLOCK_Root_Lpspi4	CLOCK Root Lpspi4.
kCLOCK_Root_Lpspi5	CLOCK Root Lpspi5.
kCLOCK_Root_Lpspi6	CLOCK Root Lpspi6.
kCLOCK_Root_Emv1	CLOCK Root Emv1.
kCLOCK_Root_Emv2	CLOCK Root Emv2.
kCLOCK_Root_Enet1	CLOCK Root Enet1.
kCLOCK_Root_Enet2	CLOCK Root Enet2.
kCLOCK_Root_Enet_Qos	CLOCK Root Enet Qos.
kCLOCK_Root_Enet_25m	CLOCK Root Enet 25M.
kCLOCK_Root_Enet_Timer1	CLOCK Root Enet Timer1.
kCLOCK_Root_Enet_Timer2	CLOCK Root Enet Timer2.
kCLOCK_Root_Enet_Timer3	CLOCK Root Enet Timer3.
kCLOCK_Root_Usdhc1	CLOCK Root Usdhc1.
kCLOCK_Root_Usdhc2	CLOCK Root Usdhc2.
kCLOCK_Root_Asrc	CLOCK Root Asrc.
kCLOCK_Root_Mqs	CLOCK Root Mqs.
kCLOCK_Root_Mic	CLOCK Root MIC.
kCLOCK_Root_Spdif	CLOCK Root Spdif.
kCLOCK_Root_Sai1	CLOCK Root Sai1.
kCLOCK_Root_Sai2	CLOCK Root Sai2.
kCLOCK_Root_Sai3	CLOCK Root Sai3.
kCLOCK_Root_Sai4	CLOCK Root Sai4.
kCLOCK_Root_Gc355	CLOCK Root Gc355.
kCLOCK_Root_Lcdif	CLOCK Root Lcdif.
kCLOCK_Root_Lcdifv2	CLOCK Root Lcdifv2.
kCLOCK_Root_Mipi_Ref	CLOCK Root Mipi Ref.
kCLOCK_Root_Mipi_Esc	CLOCK Root Mipi Esc.
kCLOCK_Root_Csi2	CLOCK Root Csi2.
kCLOCK_Root_Csi2_Esc	CLOCK Root Csi2 Esc.
kCLOCK_Root_Csi2_Ui	CLOCK Root Csi2 Ui.
kCLOCK_Root_Csi	CLOCK Root Csi.
kCLOCK_Root_Cko1	CLOCK Root CKo1.
kCLOCK_Root_Cko2	CLOCK Root CKo2.

enum _clock_root_mux_source

Enumerator
kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2	M7 mux from MuxOscRc48MDiv2.
kCLOCK_M7_ClockRoot_MuxOsc24MOut	M7 mux from MuxOsc24MOut.
kCLOCK_M7_ClockRoot_MuxOscRc400M	M7 mux from MuxOscRc400M.
kCLOCK_M7_ClockRoot_MuxOscRc16M	M7 mux from MuxOscRc16M.
kCLOCK_M7_ClockRoot_MuxArmPllOut	M7 mux from MuxArmPllOut.
kCLOCK_M7_ClockRoot_MuxSysPll1Out	M7 mux from MuxSysPll1Out.
kCLOCK_M7_ClockRoot_MuxSysPll3Out	M7 mux from MuxSysPll3Out.
kCLOCK_M7_ClockRoot_MuxVideoPllOut	M7 mux from MuxVideoPllOut.
kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2	M4 mux from MuxOscRc48MDiv2.
kCLOCK_M4_ClockRoot_MuxOsc24MOut	M4 mux from MuxOsc24MOut.
kCLOCK_M4_ClockRoot_MuxOscRc400M	M4 mux from MuxOscRc400M.
kCLOCK_M4_ClockRoot_MuxOscRc16M	M4 mux from MuxOscRc16M.
kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3	M4 mux from MuxSysPll3Pfd3.
kCLOCK_M4_ClockRoot_MuxSysPll3Out	M4 mux from MuxSysPll3Out.
kCLOCK_M4_ClockRoot_MuxSysPll2Out	M4 mux from MuxSysPll2Out.
kCLOCK_M4_ClockRoot_MuxSysPll1Div5	M4 mux from MuxSysPll1Div5.
kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2	BUS mux from MuxOscRc48MDiv2.
kCLOCK_BUS_ClockRoot_MuxOsc24MOut	BUS mux from MuxOsc24MOut.
kCLOCK_BUS_ClockRoot_MuxOscRc400M	BUS mux from MuxOscRc400M.
kCLOCK_BUS_ClockRoot_MuxOscRc16M	BUS mux from MuxOscRc16M.
kCLOCK_BUS_ClockRoot_MuxSysPll3Out	BUS mux from MuxSysPll3Out.
kCLOCK_BUS_ClockRoot_MuxSysPll1Div5	BUS mux from MuxSysPll1Div5.
kCLOCK_BUS_ClockRoot_MuxSysPll2Out	BUS mux from MuxSysPll2Out.
kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3	BUS mux from MuxSysPll2Pfd3.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2	BUS_LPSR mux from MuxOscRc48MDiv2.
kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut	BUS_LPSR mux from MuxOsc24MOut.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M	BUS_LPSR mux from MuxOscRc400M.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M	BUS_LPSR mux from MuxOscRc16M.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3	BUS_LPSR mux from MuxSysPll3Pfd3.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out	BUS_LPSR mux from MuxSysPll3Out.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out	BUS_LPSR mux from MuxSysPll2Out.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5	BUS_LPSR mux from MuxSysPll1Div5.
kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2	SEMC mux from MuxOscRc48MDiv2.
kCLOCK_SEMC_ClockRoot_MuxOsc24MOut	SEMC mux from MuxOsc24MOut.
kCLOCK_SEMC_ClockRoot_MuxOscRc400M	SEMC mux from MuxOscRc400M.
kCLOCK_SEMC_ClockRoot_MuxOscRc16M	SEMC mux from MuxOscRc16M.
kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5	SEMC mux from MuxSysPll1Div5.
kCLOCK_SEMC_ClockRoot_MuxSysPll2Out	SEMC mux from MuxSysPll2Out.
kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1	SEMC mux from MuxSysPll2Pfd1.
kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0	SEMC mux from MuxSysPll3Pfd0.
kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2	CSSYS mux from MuxOscRc48MDiv2.
kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut	CSSYS mux from MuxOsc24MOut.
kCLOCK_CSSYS_ClockRoot_MuxOscRc400M	CSSYS mux from MuxOscRc400M.
kCLOCK_CSSYS_ClockRoot_MuxOscRc16M	CSSYS mux from MuxOscRc16M.
kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2	CSSYS mux from MuxSysPll3Div2.
kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5	CSSYS mux from MuxSysPll1Div5.
kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out	CSSYS mux from MuxSysPll2Out.
kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3	CSSYS mux from MuxSysPll2Pfd3.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2	CSTRACE mux from MuxOscRc48MDiv2.
kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut	CSTRACE mux from MuxOsc24MOut.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M	CSTRACE mux from MuxOscRc400M.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M	CSTRACE mux from MuxOscRc16M.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2	CSTRACE mux from MuxSysPll3Div2.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5	CSTRACE mux from MuxSysPll1Div5.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1	CSTRACE mux from MuxSysPll2Pfd1.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out	CSTRACE mux from MuxSysPll2Out.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2	M4_SYSTICK mux from MuxOscRc48MDiv2.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut	M4_SYSTICK mux from MuxOsc24MOut.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M	M4_SYSTICK mux from MuxOscRc400M.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M	M4_SYSTICK mux from MuxOscRc16M.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3	M4_SYSTICK mux from MuxSysPll3Pfd3.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out	M4_SYSTICK mux from MuxSysPll3Out.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0	M4_SYSTICK mux from MuxSysPll2Pfd0.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5	M4_SYSTICK mux from MuxSysPll1Div5.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2	M7_SYSTICK mux from MuxOscRc48MDiv2.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut	M7_SYSTICK mux from MuxOsc24MOut.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M	M7_SYSTICK mux from MuxOscRc400M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M	M7_SYSTICK mux from MuxOscRc16M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out	M7_SYSTICK mux from MuxSysPll2Out.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2	M7_SYSTICK mux from MuxSysPll3Div2.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5	M7_SYSTICK mux from MuxSysPll1Div5.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0	M7_SYSTICK mux from MuxSysPll2Pfd0.
kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2	ADC1 mux from MuxOscRc48MDiv2.
kCLOCK_ADC1_ClockRoot_MuxOsc24MOut	ADC1 mux from MuxOsc24MOut.
kCLOCK_ADC1_ClockRoot_MuxOscRc400M	ADC1 mux from MuxOscRc400M.
kCLOCK_ADC1_ClockRoot_MuxOscRc16M	ADC1 mux from MuxOscRc16M.
kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2	ADC1 mux from MuxSysPll3Div2.
kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5	ADC1 mux from MuxSysPll1Div5.
kCLOCK_ADC1_ClockRoot_MuxSysPll2Out	ADC1 mux from MuxSysPll2Out.
kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3	ADC1 mux from MuxSysPll2Pfd3.
kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2	ADC2 mux from MuxOscRc48MDiv2.
kCLOCK_ADC2_ClockRoot_MuxOsc24MOut	ADC2 mux from MuxOsc24MOut.
kCLOCK_ADC2_ClockRoot_MuxOscRc400M	ADC2 mux from MuxOscRc400M.
kCLOCK_ADC2_ClockRoot_MuxOscRc16M	ADC2 mux from MuxOscRc16M.
kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2	ADC2 mux from MuxSysPll3Div2.
kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5	ADC2 mux from MuxSysPll1Div5.
kCLOCK_ADC2_ClockRoot_MuxSysPll2Out	ADC2 mux from MuxSysPll2Out.
kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3	ADC2 mux from MuxSysPll2Pfd3.
kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2	ACMP mux from MuxOscRc48MDiv2.
kCLOCK_ACMP_ClockRoot_MuxOsc24MOut	ACMP mux from MuxOsc24MOut.
kCLOCK_ACMP_ClockRoot_MuxOscRc400M	ACMP mux from MuxOscRc400M.
kCLOCK_ACMP_ClockRoot_MuxOscRc16M	ACMP mux from MuxOscRc16M.
kCLOCK_ACMP_ClockRoot_MuxSysPll3Out	ACMP mux from MuxSysPll3Out.
kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5	ACMP mux from MuxSysPll1Div5.
kCLOCK_ACMP_ClockRoot_MuxAudioPllOut	ACMP mux from MuxAudioPllOut.
kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3	ACMP mux from MuxSysPll2Pfd3.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2	FLEXIO1 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut	FLEXIO1 mux from MuxOsc24MOut.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M	FLEXIO1 mux from MuxOscRc400M.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M	FLEXIO1 mux from MuxOscRc16M.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2	FLEXIO1 mux from MuxSysPll3Div2.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5	FLEXIO1 mux from MuxSysPll1Div5.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out	FLEXIO1 mux from MuxSysPll2Out.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3	FLEXIO1 mux from MuxSysPll2Pfd3.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2	FLEXIO2 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut	FLEXIO2 mux from MuxOsc24MOut.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M	FLEXIO2 mux from MuxOscRc400M.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M	FLEXIO2 mux from MuxOscRc16M.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2	FLEXIO2 mux from MuxSysPll3Div2.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5	FLEXIO2 mux from MuxSysPll1Div5.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out	FLEXIO2 mux from MuxSysPll2Out.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3	FLEXIO2 mux from MuxSysPll2Pfd3.
kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2	GPT1 mux from MuxOscRc48MDiv2.
kCLOCK_GPT1_ClockRoot_MuxOsc24MOut	GPT1 mux from MuxOsc24MOut.
kCLOCK_GPT1_ClockRoot_MuxOscRc400M	GPT1 mux from MuxOscRc400M.
kCLOCK_GPT1_ClockRoot_MuxOscRc16M	GPT1 mux from MuxOscRc16M.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2	GPT1 mux from MuxSysPll3Div2.
kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5	GPT1 mux from MuxSysPll1Div5.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2	GPT1 mux from MuxSysPll3Pfd2.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3	GPT1 mux from MuxSysPll3Pfd3.
kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2	GPT2 mux from MuxOscRc48MDiv2.
kCLOCK_GPT2_ClockRoot_MuxOsc24MOut	GPT2 mux from MuxOsc24MOut.
kCLOCK_GPT2_ClockRoot_MuxOscRc400M	GPT2 mux from MuxOscRc400M.
kCLOCK_GPT2_ClockRoot_MuxOscRc16M	GPT2 mux from MuxOscRc16M.
kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2	GPT2 mux from MuxSysPll3Div2.
kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5	GPT2 mux from MuxSysPll1Div5.
kCLOCK_GPT2_ClockRoot_MuxAudioPllOut	GPT2 mux from MuxAudioPllOut.
kCLOCK_GPT2_ClockRoot_MuxVideoPllOut	GPT2 mux from MuxVideoPllOut.
kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2	GPT3 mux from MuxOscRc48MDiv2.
kCLOCK_GPT3_ClockRoot_MuxOsc24MOut	GPT3 mux from MuxOsc24MOut.
kCLOCK_GPT3_ClockRoot_MuxOscRc400M	GPT3 mux from MuxOscRc400M.
kCLOCK_GPT3_ClockRoot_MuxOscRc16M	GPT3 mux from MuxOscRc16M.
kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2	GPT3 mux from MuxSysPll3Div2.
kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5	GPT3 mux from MuxSysPll1Div5.
kCLOCK_GPT3_ClockRoot_MuxAudioPllOut	GPT3 mux from MuxAudioPllOut.
kCLOCK_GPT3_ClockRoot_MuxVideoPllOut	GPT3 mux from MuxVideoPllOut.
kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2	GPT4 mux from MuxOscRc48MDiv2.
kCLOCK_GPT4_ClockRoot_MuxOsc24MOut	GPT4 mux from MuxOsc24MOut.
kCLOCK_GPT4_ClockRoot_MuxOscRc400M	GPT4 mux from MuxOscRc400M.
kCLOCK_GPT4_ClockRoot_MuxOscRc16M	GPT4 mux from MuxOscRc16M.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2	GPT4 mux from MuxSysPll3Div2.
kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5	GPT4 mux from MuxSysPll1Div5.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2	GPT4 mux from MuxSysPll3Pfd2.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3	GPT4 mux from MuxSysPll3Pfd3.
kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2	GPT5 mux from MuxOscRc48MDiv2.
kCLOCK_GPT5_ClockRoot_MuxOsc24MOut	GPT5 mux from MuxOsc24MOut.
kCLOCK_GPT5_ClockRoot_MuxOscRc400M	GPT5 mux from MuxOscRc400M.
kCLOCK_GPT5_ClockRoot_MuxOscRc16M	GPT5 mux from MuxOscRc16M.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2	GPT5 mux from MuxSysPll3Div2.
kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5	GPT5 mux from MuxSysPll1Div5.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2	GPT5 mux from MuxSysPll3Pfd2.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3	GPT5 mux from MuxSysPll3Pfd3.
kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2	GPT6 mux from MuxOscRc48MDiv2.
kCLOCK_GPT6_ClockRoot_MuxOsc24MOut	GPT6 mux from MuxOsc24MOut.
kCLOCK_GPT6_ClockRoot_MuxOscRc400M	GPT6 mux from MuxOscRc400M.
kCLOCK_GPT6_ClockRoot_MuxOscRc16M	GPT6 mux from MuxOscRc16M.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2	GPT6 mux from MuxSysPll3Div2.
kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5	GPT6 mux from MuxSysPll1Div5.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2	GPT6 mux from MuxSysPll3Pfd2.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3	GPT6 mux from MuxSysPll3Pfd3.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2	FLEXSPI1 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut	FLEXSPI1 mux from MuxOsc24MOut.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M	FLEXSPI1 mux from MuxOscRc400M.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M	FLEXSPI1 mux from MuxOscRc16M.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0	FLEXSPI1 mux from MuxSysPll3Pfd0.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out	FLEXSPI1 mux from MuxSysPll2Out.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2	FLEXSPI1 mux from MuxSysPll2Pfd2.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out	FLEXSPI1 mux from MuxSysPll3Out.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2	FLEXSPI2 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut	FLEXSPI2 mux from MuxOsc24MOut.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M	FLEXSPI2 mux from MuxOscRc400M.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M	FLEXSPI2 mux from MuxOscRc16M.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0	FLEXSPI2 mux from MuxSysPll3Pfd0.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out	FLEXSPI2 mux from MuxSysPll2Out.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2	FLEXSPI2 mux from MuxSysPll2Pfd2.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out	FLEXSPI2 mux from MuxSysPll3Out.
kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2	CAN1 mux from MuxOscRc48MDiv2.
kCLOCK_CAN1_ClockRoot_MuxOsc24MOut	CAN1 mux from MuxOsc24MOut.
kCLOCK_CAN1_ClockRoot_MuxOscRc400M	CAN1 mux from MuxOscRc400M.
kCLOCK_CAN1_ClockRoot_MuxOscRc16M	CAN1 mux from MuxOscRc16M.
kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2	CAN1 mux from MuxSysPll3Div2.
kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5	CAN1 mux from MuxSysPll1Div5.
kCLOCK_CAN1_ClockRoot_MuxSysPll2Out	CAN1 mux from MuxSysPll2Out.
kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3	CAN1 mux from MuxSysPll2Pfd3.
kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2	CAN2 mux from MuxOscRc48MDiv2.
kCLOCK_CAN2_ClockRoot_MuxOsc24MOut	CAN2 mux from MuxOsc24MOut.
kCLOCK_CAN2_ClockRoot_MuxOscRc400M	CAN2 mux from MuxOscRc400M.
kCLOCK_CAN2_ClockRoot_MuxOscRc16M	CAN2 mux from MuxOscRc16M.
kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2	CAN2 mux from MuxSysPll3Div2.
kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5	CAN2 mux from MuxSysPll1Div5.
kCLOCK_CAN2_ClockRoot_MuxSysPll2Out	CAN2 mux from MuxSysPll2Out.
kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3	CAN2 mux from MuxSysPll2Pfd3.
kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2	CAN3 mux from MuxOscRc48MDiv2.
kCLOCK_CAN3_ClockRoot_MuxOsc24MOut	CAN3 mux from MuxOsc24MOut.
kCLOCK_CAN3_ClockRoot_MuxOscRc400M	CAN3 mux from MuxOscRc400M.
kCLOCK_CAN3_ClockRoot_MuxOscRc16M	CAN3 mux from MuxOscRc16M.
kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3	CAN3 mux from MuxSysPll3Pfd3.
kCLOCK_CAN3_ClockRoot_MuxSysPll3Out	CAN3 mux from MuxSysPll3Out.
kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3	CAN3 mux from MuxSysPll2Pfd3.
kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5	CAN3 mux from MuxSysPll1Div5.
kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2	LPUART1 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut	LPUART1 mux from MuxOsc24MOut.
kCLOCK_LPUART1_ClockRoot_MuxOscRc400M	LPUART1 mux from MuxOscRc400M.
kCLOCK_LPUART1_ClockRoot_MuxOscRc16M	LPUART1 mux from MuxOscRc16M.
kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2	LPUART1 mux from MuxSysPll3Div2.
kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5	LPUART1 mux from MuxSysPll1Div5.
kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out	LPUART1 mux from MuxSysPll2Out.
kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3	LPUART1 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2	LPUART2 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut	LPUART2 mux from MuxOsc24MOut.
kCLOCK_LPUART2_ClockRoot_MuxOscRc400M	LPUART2 mux from MuxOscRc400M.
kCLOCK_LPUART2_ClockRoot_MuxOscRc16M	LPUART2 mux from MuxOscRc16M.
kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2	LPUART2 mux from MuxSysPll3Div2.
kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5	LPUART2 mux from MuxSysPll1Div5.
kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out	LPUART2 mux from MuxSysPll2Out.
kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3	LPUART2 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2	LPUART3 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut	LPUART3 mux from MuxOsc24MOut.
kCLOCK_LPUART3_ClockRoot_MuxOscRc400M	LPUART3 mux from MuxOscRc400M.
kCLOCK_LPUART3_ClockRoot_MuxOscRc16M	LPUART3 mux from MuxOscRc16M.
kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2	LPUART3 mux from MuxSysPll3Div2.
kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5	LPUART3 mux from MuxSysPll1Div5.
kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out	LPUART3 mux from MuxSysPll2Out.
kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3	LPUART3 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2	LPUART4 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut	LPUART4 mux from MuxOsc24MOut.
kCLOCK_LPUART4_ClockRoot_MuxOscRc400M	LPUART4 mux from MuxOscRc400M.
kCLOCK_LPUART4_ClockRoot_MuxOscRc16M	LPUART4 mux from MuxOscRc16M.
kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2	LPUART4 mux from MuxSysPll3Div2.
kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5	LPUART4 mux from MuxSysPll1Div5.
kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out	LPUART4 mux from MuxSysPll2Out.
kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3	LPUART4 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2	LPUART5 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut	LPUART5 mux from MuxOsc24MOut.
kCLOCK_LPUART5_ClockRoot_MuxOscRc400M	LPUART5 mux from MuxOscRc400M.
kCLOCK_LPUART5_ClockRoot_MuxOscRc16M	LPUART5 mux from MuxOscRc16M.
kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2	LPUART5 mux from MuxSysPll3Div2.
kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5	LPUART5 mux from MuxSysPll1Div5.
kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out	LPUART5 mux from MuxSysPll2Out.
kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3	LPUART5 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2	LPUART6 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut	LPUART6 mux from MuxOsc24MOut.
kCLOCK_LPUART6_ClockRoot_MuxOscRc400M	LPUART6 mux from MuxOscRc400M.
kCLOCK_LPUART6_ClockRoot_MuxOscRc16M	LPUART6 mux from MuxOscRc16M.
kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2	LPUART6 mux from MuxSysPll3Div2.
kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5	LPUART6 mux from MuxSysPll1Div5.
kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out	LPUART6 mux from MuxSysPll2Out.
kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3	LPUART6 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2	LPUART7 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut	LPUART7 mux from MuxOsc24MOut.
kCLOCK_LPUART7_ClockRoot_MuxOscRc400M	LPUART7 mux from MuxOscRc400M.
kCLOCK_LPUART7_ClockRoot_MuxOscRc16M	LPUART7 mux from MuxOscRc16M.
kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2	LPUART7 mux from MuxSysPll3Div2.
kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5	LPUART7 mux from MuxSysPll1Div5.
kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out	LPUART7 mux from MuxSysPll2Out.
kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3	LPUART7 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2	LPUART8 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut	LPUART8 mux from MuxOsc24MOut.
kCLOCK_LPUART8_ClockRoot_MuxOscRc400M	LPUART8 mux from MuxOscRc400M.
kCLOCK_LPUART8_ClockRoot_MuxOscRc16M	LPUART8 mux from MuxOscRc16M.
kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2	LPUART8 mux from MuxSysPll3Div2.
kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5	LPUART8 mux from MuxSysPll1Div5.
kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out	LPUART8 mux from MuxSysPll2Out.
kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3	LPUART8 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2	LPUART9 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut	LPUART9 mux from MuxOsc24MOut.
kCLOCK_LPUART9_ClockRoot_MuxOscRc400M	LPUART9 mux from MuxOscRc400M.
kCLOCK_LPUART9_ClockRoot_MuxOscRc16M	LPUART9 mux from MuxOscRc16M.
kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2	LPUART9 mux from MuxSysPll3Div2.
kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5	LPUART9 mux from MuxSysPll1Div5.
kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out	LPUART9 mux from MuxSysPll2Out.
kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3	LPUART9 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2	LPUART10 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut	LPUART10 mux from MuxOsc24MOut.
kCLOCK_LPUART10_ClockRoot_MuxOscRc400M	LPUART10 mux from MuxOscRc400M.
kCLOCK_LPUART10_ClockRoot_MuxOscRc16M	LPUART10 mux from MuxOscRc16M.
kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2	LPUART10 mux from MuxSysPll3Div2.
kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5	LPUART10 mux from MuxSysPll1Div5.
kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out	LPUART10 mux from MuxSysPll2Out.
kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3	LPUART10 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2	LPUART11 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut	LPUART11 mux from MuxOsc24MOut.
kCLOCK_LPUART11_ClockRoot_MuxOscRc400M	LPUART11 mux from MuxOscRc400M.
kCLOCK_LPUART11_ClockRoot_MuxOscRc16M	LPUART11 mux from MuxOscRc16M.
kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3	LPUART11 mux from MuxSysPll3Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out	LPUART11 mux from MuxSysPll3Out.
kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3	LPUART11 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5	LPUART11 mux from MuxSysPll1Div5.
kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2	LPUART12 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut	LPUART12 mux from MuxOsc24MOut.
kCLOCK_LPUART12_ClockRoot_MuxOscRc400M	LPUART12 mux from MuxOscRc400M.
kCLOCK_LPUART12_ClockRoot_MuxOscRc16M	LPUART12 mux from MuxOscRc16M.
kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3	LPUART12 mux from MuxSysPll3Pfd3.
kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out	LPUART12 mux from MuxSysPll3Out.
kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3	LPUART12 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5	LPUART12 mux from MuxSysPll1Div5.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2	LPI2C1 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut	LPI2C1 mux from MuxOsc24MOut.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M	LPI2C1 mux from MuxOscRc400M.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M	LPI2C1 mux from MuxOscRc16M.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2	LPI2C1 mux from MuxSysPll3Div2.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5	LPI2C1 mux from MuxSysPll1Div5.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out	LPI2C1 mux from MuxSysPll2Out.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3	LPI2C1 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2	LPI2C2 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut	LPI2C2 mux from MuxOsc24MOut.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M	LPI2C2 mux from MuxOscRc400M.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M	LPI2C2 mux from MuxOscRc16M.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2	LPI2C2 mux from MuxSysPll3Div2.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5	LPI2C2 mux from MuxSysPll1Div5.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out	LPI2C2 mux from MuxSysPll2Out.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3	LPI2C2 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2	LPI2C3 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut	LPI2C3 mux from MuxOsc24MOut.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M	LPI2C3 mux from MuxOscRc400M.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M	LPI2C3 mux from MuxOscRc16M.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2	LPI2C3 mux from MuxSysPll3Div2.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5	LPI2C3 mux from MuxSysPll1Div5.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out	LPI2C3 mux from MuxSysPll2Out.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3	LPI2C3 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2	LPI2C4 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut	LPI2C4 mux from MuxOsc24MOut.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M	LPI2C4 mux from MuxOscRc400M.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M	LPI2C4 mux from MuxOscRc16M.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2	LPI2C4 mux from MuxSysPll3Div2.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5	LPI2C4 mux from MuxSysPll1Div5.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out	LPI2C4 mux from MuxSysPll2Out.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3	LPI2C4 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2	LPI2C5 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut	LPI2C5 mux from MuxOsc24MOut.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M	LPI2C5 mux from MuxOscRc400M.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M	LPI2C5 mux from MuxOscRc16M.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3	LPI2C5 mux from MuxSysPll3Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out	LPI2C5 mux from MuxSysPll3Out.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3	LPI2C5 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5	LPI2C5 mux from MuxSysPll1Div5.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2	LPI2C6 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut	LPI2C6 mux from MuxOsc24MOut.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M	LPI2C6 mux from MuxOscRc400M.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M	LPI2C6 mux from MuxOscRc16M.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3	LPI2C6 mux from MuxSysPll3Pfd3.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out	LPI2C6 mux from MuxSysPll3Out.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3	LPI2C6 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5	LPI2C6 mux from MuxSysPll1Div5.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2	LPSPI1 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut	LPSPI1 mux from MuxOsc24MOut.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M	LPSPI1 mux from MuxOscRc400M.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M	LPSPI1 mux from MuxOscRc16M.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2	LPSPI1 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5	LPSPI1 mux from MuxSysPll1Div5.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out	LPSPI1 mux from MuxSysPll2Out.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3	LPSPI1 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2	LPSPI2 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut	LPSPI2 mux from MuxOsc24MOut.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M	LPSPI2 mux from MuxOscRc400M.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M	LPSPI2 mux from MuxOscRc16M.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2	LPSPI2 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5	LPSPI2 mux from MuxSysPll1Div5.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out	LPSPI2 mux from MuxSysPll2Out.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3	LPSPI2 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2	LPSPI3 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut	LPSPI3 mux from MuxOsc24MOut.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M	LPSPI3 mux from MuxOscRc400M.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M	LPSPI3 mux from MuxOscRc16M.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2	LPSPI3 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5	LPSPI3 mux from MuxSysPll1Div5.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out	LPSPI3 mux from MuxSysPll2Out.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3	LPSPI3 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2	LPSPI4 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut	LPSPI4 mux from MuxOsc24MOut.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M	LPSPI4 mux from MuxOscRc400M.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M	LPSPI4 mux from MuxOscRc16M.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2	LPSPI4 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5	LPSPI4 mux from MuxSysPll1Div5.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out	LPSPI4 mux from MuxSysPll2Out.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3	LPSPI4 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2	LPSPI5 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut	LPSPI5 mux from MuxOsc24MOut.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M	LPSPI5 mux from MuxOscRc400M.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M	LPSPI5 mux from MuxOscRc16M.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3	LPSPI5 mux from MuxSysPll3Pfd3.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out	LPSPI5 mux from MuxSysPll3Out.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2	LPSPI5 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5	LPSPI5 mux from MuxSysPll1Div5.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2	LPSPI6 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut	LPSPI6 mux from MuxOsc24MOut.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M	LPSPI6 mux from MuxOscRc400M.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M	LPSPI6 mux from MuxOscRc16M.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3	LPSPI6 mux from MuxSysPll3Pfd3.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out	LPSPI6 mux from MuxSysPll3Out.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2	LPSPI6 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5	LPSPI6 mux from MuxSysPll1Div5.
kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2	EMV1 mux from MuxOscRc48MDiv2.
kCLOCK_EMV1_ClockRoot_MuxOsc24MOut	EMV1 mux from MuxOsc24MOut.
kCLOCK_EMV1_ClockRoot_MuxOscRc400M	EMV1 mux from MuxOscRc400M.
kCLOCK_EMV1_ClockRoot_MuxOscRc16M	EMV1 mux from MuxOscRc16M.
kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2	EMV1 mux from MuxSysPll3Div2.
kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5	EMV1 mux from MuxSysPll1Div5.
kCLOCK_EMV1_ClockRoot_MuxSysPll2Out	EMV1 mux from MuxSysPll2Out.
kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3	EMV1 mux from MuxSysPll2Pfd3.
kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2	EMV2 mux from MuxOscRc48MDiv2.
kCLOCK_EMV2_ClockRoot_MuxOsc24MOut	EMV2 mux from MuxOsc24MOut.
kCLOCK_EMV2_ClockRoot_MuxOscRc400M	EMV2 mux from MuxOscRc400M.
kCLOCK_EMV2_ClockRoot_MuxOscRc16M	EMV2 mux from MuxOscRc16M.
kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2	EMV2 mux from MuxSysPll3Div2.
kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5	EMV2 mux from MuxSysPll1Div5.
kCLOCK_EMV2_ClockRoot_MuxSysPll2Out	EMV2 mux from MuxSysPll2Out.
kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3	EMV2 mux from MuxSysPll2Pfd3.
kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2	ENET1 mux from MuxOscRc48MDiv2.
kCLOCK_ENET1_ClockRoot_MuxOsc24MOut	ENET1 mux from MuxOsc24MOut.
kCLOCK_ENET1_ClockRoot_MuxOscRc400M	ENET1 mux from MuxOscRc400M.
kCLOCK_ENET1_ClockRoot_MuxOscRc16M	ENET1 mux from MuxOscRc16M.
kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2	ENET1 mux from MuxSysPll1Div2.
kCLOCK_ENET1_ClockRoot_MuxAudioPllOut	ENET1 mux from MuxAudioPllOut.
kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5	ENET1 mux from MuxSysPll1Div5.
kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1	ENET1 mux from MuxSysPll2Pfd1.
kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2	ENET2 mux from MuxOscRc48MDiv2.
kCLOCK_ENET2_ClockRoot_MuxOsc24MOut	ENET2 mux from MuxOsc24MOut.
kCLOCK_ENET2_ClockRoot_MuxOscRc400M	ENET2 mux from MuxOscRc400M.
kCLOCK_ENET2_ClockRoot_MuxOscRc16M	ENET2 mux from MuxOscRc16M.
kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2	ENET2 mux from MuxSysPll1Div2.
kCLOCK_ENET2_ClockRoot_MuxAudioPllOut	ENET2 mux from MuxAudioPllOut.
kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5	ENET2 mux from MuxSysPll1Div5.
kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1	ENET2 mux from MuxSysPll2Pfd1.
kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2	ENET_QOS mux from MuxOscRc48MDiv2.
kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut	ENET_QOS mux from MuxOsc24MOut.
kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M	ENET_QOS mux from MuxOscRc400M.
kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M	ENET_QOS mux from MuxOscRc16M.
kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2	ENET_QOS mux from MuxSysPll1Div2.
kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut	ENET_QOS mux from MuxAudioPllOut.
kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5	ENET_QOS mux from MuxSysPll1Div5.
kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1	ENET_QOS mux from MuxSysPll2Pfd1.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2	ENET_25M mux from MuxOscRc48MDiv2.
kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut	ENET_25M mux from MuxOsc24MOut.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M	ENET_25M mux from MuxOscRc400M.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M	ENET_25M mux from MuxOscRc16M.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2	ENET_25M mux from MuxSysPll1Div2.
kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut	ENET_25M mux from MuxAudioPllOut.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5	ENET_25M mux from MuxSysPll1Div5.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1	ENET_25M mux from MuxSysPll2Pfd1.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2	ENET_TIMER1 mux from MuxOscRc48MDiv2.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut	ENET_TIMER1 mux from MuxOsc24MOut.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M	ENET_TIMER1 mux from MuxOscRc400M.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M	ENET_TIMER1 mux from MuxOscRc16M.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2	ENET_TIMER1 mux from MuxSysPll1Div2.
kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut	ENET_TIMER1 mux from MuxAudioPllOut.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5	ENET_TIMER1 mux from MuxSysPll1Div5.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1	ENET_TIMER1 mux from MuxSysPll2Pfd1.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2	ENET_TIMER2 mux from MuxOscRc48MDiv2.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut	ENET_TIMER2 mux from MuxOsc24MOut.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M	ENET_TIMER2 mux from MuxOscRc400M.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M	ENET_TIMER2 mux from MuxOscRc16M.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2	ENET_TIMER2 mux from MuxSysPll1Div2.
kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut	ENET_TIMER2 mux from MuxAudioPllOut.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5	ENET_TIMER2 mux from MuxSysPll1Div5.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1	ENET_TIMER2 mux from MuxSysPll2Pfd1.
kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2	ENET_TIMER3 mux from MuxOscRc48MDiv2.
kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut	ENET_TIMER3 mux from MuxOsc24MOut.
kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M	ENET_TIMER3 mux from MuxOscRc400M.
kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M	ENET_TIMER3 mux from MuxOscRc16M.
kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2	ENET_TIMER3 mux from MuxSysPll1Div2.
kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut	ENET_TIMER3 mux from MuxAudioPllOut.
kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5	ENET_TIMER3 mux from MuxSysPll1Div5.
kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1	ENET_TIMER3 mux from MuxSysPll2Pfd1.
kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2	USDHC1 mux from MuxOscRc48MDiv2.
kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut	USDHC1 mux from MuxOsc24MOut.
kCLOCK_USDHC1_ClockRoot_MuxOscRc400M	USDHC1 mux from MuxOscRc400M.
kCLOCK_USDHC1_ClockRoot_MuxOscRc16M	USDHC1 mux from MuxOscRc16M.
kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2	USDHC1 mux from MuxSysPll2Pfd2.
kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0	USDHC1 mux from MuxSysPll2Pfd0.
kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5	USDHC1 mux from MuxSysPll1Div5.
kCLOCK_USDHC1_ClockRoot_MuxArmPllOut	USDHC1 mux from MuxArmPllOut.
kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2	USDHC2 mux from MuxOscRc48MDiv2.
kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut	USDHC2 mux from MuxOsc24MOut.
kCLOCK_USDHC2_ClockRoot_MuxOscRc400M	USDHC2 mux from MuxOscRc400M.
kCLOCK_USDHC2_ClockRoot_MuxOscRc16M	USDHC2 mux from MuxOscRc16M.
kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2	USDHC2 mux from MuxSysPll2Pfd2.
kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0	USDHC2 mux from MuxSysPll2Pfd0.
kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5	USDHC2 mux from MuxSysPll1Div5.
kCLOCK_USDHC2_ClockRoot_MuxArmPllOut	USDHC2 mux from MuxArmPllOut.
kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2	ASRC mux from MuxOscRc48MDiv2.
kCLOCK_ASRC_ClockRoot_MuxOsc24MOut	ASRC mux from MuxOsc24MOut.
kCLOCK_ASRC_ClockRoot_MuxOscRc400M	ASRC mux from MuxOscRc400M.
kCLOCK_ASRC_ClockRoot_MuxOscRc16M	ASRC mux from MuxOscRc16M.
kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5	ASRC mux from MuxSysPll1Div5.
kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2	ASRC mux from MuxSysPll3Div2.
kCLOCK_ASRC_ClockRoot_MuxAudioPllOut	ASRC mux from MuxAudioPllOut.
kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3	ASRC mux from MuxSysPll2Pfd3.
kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2	MQS mux from MuxOscRc48MDiv2.
kCLOCK_MQS_ClockRoot_MuxOsc24MOut	MQS mux from MuxOsc24MOut.
kCLOCK_MQS_ClockRoot_MuxOscRc400M	MQS mux from MuxOscRc400M.
kCLOCK_MQS_ClockRoot_MuxOscRc16M	MQS mux from MuxOscRc16M.
kCLOCK_MQS_ClockRoot_MuxSysPll1Div5	MQS mux from MuxSysPll1Div5.
kCLOCK_MQS_ClockRoot_MuxSysPll3Div2	MQS mux from MuxSysPll3Div2.
kCLOCK_MQS_ClockRoot_MuxAudioPllOut	MQS mux from MuxAudioPllOut.
kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3	MQS mux from MuxSysPll2Pfd3.
kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2	MIC mux from MuxOscRc48MDiv2.
kCLOCK_MIC_ClockRoot_MuxOsc24MOut	MIC mux from MuxOsc24MOut.
kCLOCK_MIC_ClockRoot_MuxOscRc400M	MIC mux from MuxOscRc400M.
kCLOCK_MIC_ClockRoot_MuxOscRc16M	MIC mux from MuxOscRc16M.
kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3	MIC mux from MuxSysPll3Pfd3.
kCLOCK_MIC_ClockRoot_MuxSysPll3Out	MIC mux from MuxSysPll3Out.
kCLOCK_MIC_ClockRoot_MuxAudioPllOut	MIC mux from MuxAudioPllOut.
kCLOCK_MIC_ClockRoot_MuxSysPll1Div5	MIC mux from MuxSysPll1Div5.
kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2	SPDIF mux from MuxOscRc48MDiv2.
kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut	SPDIF mux from MuxOsc24MOut.
kCLOCK_SPDIF_ClockRoot_MuxOscRc400M	SPDIF mux from MuxOscRc400M.
kCLOCK_SPDIF_ClockRoot_MuxOscRc16M	SPDIF mux from MuxOscRc16M.
kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut	SPDIF mux from MuxAudioPllOut.
kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out	SPDIF mux from MuxSysPll3Out.
kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2	SPDIF mux from MuxSysPll3Pfd2.
kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3	SPDIF mux from MuxSysPll2Pfd3.
kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2	SAI1 mux from MuxOscRc48MDiv2.
kCLOCK_SAI1_ClockRoot_MuxOsc24MOut	SAI1 mux from MuxOsc24MOut.
kCLOCK_SAI1_ClockRoot_MuxOscRc400M	SAI1 mux from MuxOscRc400M.
kCLOCK_SAI1_ClockRoot_MuxOscRc16M	SAI1 mux from MuxOscRc16M.
kCLOCK_SAI1_ClockRoot_MuxAudioPllOut	SAI1 mux from MuxAudioPllOut.
kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2	SAI1 mux from MuxSysPll3Pfd2.
kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5	SAI1 mux from MuxSysPll1Div5.
kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3	SAI1 mux from MuxSysPll2Pfd3.
kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2	SAI2 mux from MuxOscRc48MDiv2.
kCLOCK_SAI2_ClockRoot_MuxOsc24MOut	SAI2 mux from MuxOsc24MOut.
kCLOCK_SAI2_ClockRoot_MuxOscRc400M	SAI2 mux from MuxOscRc400M.
kCLOCK_SAI2_ClockRoot_MuxOscRc16M	SAI2 mux from MuxOscRc16M.
kCLOCK_SAI2_ClockRoot_MuxAudioPllOut	SAI2 mux from MuxAudioPllOut.
kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2	SAI2 mux from MuxSysPll3Pfd2.
kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5	SAI2 mux from MuxSysPll1Div5.
kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3	SAI2 mux from MuxSysPll2Pfd3.
kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2	SAI3 mux from MuxOscRc48MDiv2.
kCLOCK_SAI3_ClockRoot_MuxOsc24MOut	SAI3 mux from MuxOsc24MOut.
kCLOCK_SAI3_ClockRoot_MuxOscRc400M	SAI3 mux from MuxOscRc400M.
kCLOCK_SAI3_ClockRoot_MuxOscRc16M	SAI3 mux from MuxOscRc16M.
kCLOCK_SAI3_ClockRoot_MuxAudioPllOut	SAI3 mux from MuxAudioPllOut.
kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2	SAI3 mux from MuxSysPll3Pfd2.
kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5	SAI3 mux from MuxSysPll1Div5.
kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3	SAI3 mux from MuxSysPll2Pfd3.
kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2	SAI4 mux from MuxOscRc48MDiv2.
kCLOCK_SAI4_ClockRoot_MuxOsc24MOut	SAI4 mux from MuxOsc24MOut.
kCLOCK_SAI4_ClockRoot_MuxOscRc400M	SAI4 mux from MuxOscRc400M.
kCLOCK_SAI4_ClockRoot_MuxOscRc16M	SAI4 mux from MuxOscRc16M.
kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3	SAI4 mux from MuxSysPll3Pfd3.
kCLOCK_SAI4_ClockRoot_MuxSysPll3Out	SAI4 mux from MuxSysPll3Out.
kCLOCK_SAI4_ClockRoot_MuxAudioPllOut	SAI4 mux from MuxAudioPllOut.
kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5	SAI4 mux from MuxSysPll1Div5.
kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2	GC355 mux from MuxOscRc48MDiv2.
kCLOCK_GC355_ClockRoot_MuxOsc24MOut	GC355 mux from MuxOsc24MOut.
kCLOCK_GC355_ClockRoot_MuxOscRc400M	GC355 mux from MuxOscRc400M.
kCLOCK_GC355_ClockRoot_MuxOscRc16M	GC355 mux from MuxOscRc16M.
kCLOCK_GC355_ClockRoot_MuxSysPll2Out	GC355 mux from MuxSysPll2Out.
kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1	GC355 mux from MuxSysPll2Pfd1.
kCLOCK_GC355_ClockRoot_MuxSysPll3Out	GC355 mux from MuxSysPll3Out.
kCLOCK_GC355_ClockRoot_MuxVideoPllOut	GC355 mux from MuxVideoPllOut.
kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2	LCDIF mux from MuxOscRc48MDiv2.
kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut	LCDIF mux from MuxOsc24MOut.
kCLOCK_LCDIF_ClockRoot_MuxOscRc400M	LCDIF mux from MuxOscRc400M.
kCLOCK_LCDIF_ClockRoot_MuxOscRc16M	LCDIF mux from MuxOscRc16M.
kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out	LCDIF mux from MuxSysPll2Out.
kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2	LCDIF mux from MuxSysPll2Pfd2.
kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0	LCDIF mux from MuxSysPll3Pfd0.
kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut	LCDIF mux from MuxVideoPllOut.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2	LCDIFV2 mux from MuxOscRc48MDiv2.
kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut	LCDIFV2 mux from MuxOsc24MOut.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M	LCDIFV2 mux from MuxOscRc400M.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M	LCDIFV2 mux from MuxOscRc16M.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out	LCDIFV2 mux from MuxSysPll2Out.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2	LCDIFV2 mux from MuxSysPll2Pfd2.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0	LCDIFV2 mux from MuxSysPll3Pfd0.
kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut	LCDIFV2 mux from MuxVideoPllOut.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2	MIPI_REF mux from MuxOscRc48MDiv2.
kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut	MIPI_REF mux from MuxOsc24MOut.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M	MIPI_REF mux from MuxOscRc400M.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M	MIPI_REF mux from MuxOscRc16M.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out	MIPI_REF mux from MuxSysPll2Out.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0	MIPI_REF mux from MuxSysPll2Pfd0.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0	MIPI_REF mux from MuxSysPll3Pfd0.
kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut	MIPI_REF mux from MuxVideoPllOut.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2	MIPI_ESC mux from MuxOscRc48MDiv2.
kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut	MIPI_ESC mux from MuxOsc24MOut.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M	MIPI_ESC mux from MuxOscRc400M.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M	MIPI_ESC mux from MuxOscRc16M.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out	MIPI_ESC mux from MuxSysPll2Out.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0	MIPI_ESC mux from MuxSysPll2Pfd0.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0	MIPI_ESC mux from MuxSysPll3Pfd0.
kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut	MIPI_ESC mux from MuxVideoPllOut.
kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2	CSI2 mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_ClockRoot_MuxOsc24MOut	CSI2 mux from MuxOsc24MOut.
kCLOCK_CSI2_ClockRoot_MuxOscRc400M	CSI2 mux from MuxOscRc400M.
kCLOCK_CSI2_ClockRoot_MuxOscRc16M	CSI2 mux from MuxOscRc16M.
kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2	CSI2 mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_ClockRoot_MuxSysPll3Out	CSI2 mux from MuxSysPll3Out.
kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0	CSI2 mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_ClockRoot_MuxVideoPllOut	CSI2 mux from MuxVideoPllOut.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2	CSI2_ESC mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut	CSI2_ESC mux from MuxOsc24MOut.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M	CSI2_ESC mux from MuxOscRc400M.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M	CSI2_ESC mux from MuxOscRc16M.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2	CSI2_ESC mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out	CSI2_ESC mux from MuxSysPll3Out.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0	CSI2_ESC mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut	CSI2_ESC mux from MuxVideoPllOut.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2	CSI2_UI mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut	CSI2_UI mux from MuxOsc24MOut.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M	CSI2_UI mux from MuxOscRc400M.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M	CSI2_UI mux from MuxOscRc16M.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2	CSI2_UI mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out	CSI2_UI mux from MuxSysPll3Out.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0	CSI2_UI mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut	CSI2_UI mux from MuxVideoPllOut.
kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2	CSI mux from MuxOscRc48MDiv2.
kCLOCK_CSI_ClockRoot_MuxOsc24MOut	CSI mux from MuxOsc24MOut.
kCLOCK_CSI_ClockRoot_MuxOscRc400M	CSI mux from MuxOscRc400M.
kCLOCK_CSI_ClockRoot_MuxOscRc16M	CSI mux from MuxOscRc16M.
kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2	CSI mux from MuxSysPll2Pfd2.
kCLOCK_CSI_ClockRoot_MuxSysPll3Out	CSI mux from MuxSysPll3Out.
kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1	CSI mux from MuxSysPll3Pfd1.
kCLOCK_CSI_ClockRoot_MuxVideoPllOut	CSI mux from MuxVideoPllOut.
kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2	CKO1 mux from MuxOscRc48MDiv2.
kCLOCK_CKO1_ClockRoot_MuxOsc24MOut	CKO1 mux from MuxOsc24MOut.
kCLOCK_CKO1_ClockRoot_MuxOscRc400M	CKO1 mux from MuxOscRc400M.
kCLOCK_CKO1_ClockRoot_MuxOscRc16M	CKO1 mux from MuxOscRc16M.
kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2	CKO1 mux from MuxSysPll2Pfd2.
kCLOCK_CKO1_ClockRoot_MuxSysPll2Out	CKO1 mux from MuxSysPll2Out.
kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1	CKO1 mux from MuxSysPll3Pfd1.
kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5	CKO1 mux from MuxSysPll1Div5.
kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2	CKO2 mux from MuxOscRc48MDiv2.
kCLOCK_CKO2_ClockRoot_MuxOsc24MOut	CKO2 mux from MuxOsc24MOut.
kCLOCK_CKO2_ClockRoot_MuxOscRc400M	CKO2 mux from MuxOscRc400M.
kCLOCK_CKO2_ClockRoot_MuxOscRc16M	CKO2 mux from MuxOscRc16M.
kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3	CKO2 mux from MuxSysPll2Pfd3.
kCLOCK_CKO2_ClockRoot_MuxOscRc48M	CKO2 mux from MuxOscRc48M.
kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1	CKO2 mux from MuxSysPll3Pfd1.
kCLOCK_CKO2_ClockRoot_MuxAudioPllOut	CKO2 mux from MuxAudioPllOut.

enum _clock_group

Enumerator
kCLOCK_Group_FlexRAM	FlexRAM clock group.
kCLOCK_Group_MipiDsi	Mipi Dsi clock group.
kCLOCK_Group_Last	Last clock group.

enum _clock_osc

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

enum _clock_gate_value

Enumerator
kCLOCK_Off	Clock is off.
kCLOCK_On	Clock is on.

enum _clock_mode_t

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

enum _clock_usb_src

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

enum _clock_usb_phy_src

Enumerator
kCLOCK_Usbphy480M	Use 480M.

enum _clock_pll_clk_src

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M.
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N.

enum _clock_pll_post_div

Enumerator
kCLOCK_PllPostDiv2	Divide by 2.
kCLOCK_PllPostDiv4	Divide by 4.
kCLOCK_PllPostDiv8	Divide by 8.
kCLOCK_PllPostDiv1	Divide by 1.

enum _clock_pll

Enumerator
kCLOCK_PllArm	ARM PLL.
kCLOCK_PllSys1	SYS1 PLL, it has a dedicated frequency of 1GHz.
kCLOCK_PllSys2	SYS2 PLL, it has a dedicated frequency of 528MHz.
kCLOCK_PllSys3	SYS3 PLL, it has a dedicated frequency of 480MHz.
kCLOCK_PllAudio	Audio PLL.
kCLOCK_PllVideo	Video PLL.
kCLOCK_PllInvalid	Invalid value.

enum _clock_pfd

Enumerator
kCLOCK_Pfd0	PLL PFD0.
kCLOCK_Pfd1	PLL PFD1.
kCLOCK_Pfd2	PLL PFD2.
kCLOCK_Pfd3	PLL PFD3.

enum _clock_control_mode

Enumerator
kCLOCK_SoftwareMode	Software control mode.
kCLOCK_GpcMode	GPC control mode.

enum _clock_24MOsc_mode

Enumerator
kCLOCK_24MOscHighGainMode	24MHz crystal oscillator work as high gain mode.
kCLOCK_24MOscBypassMode	24MHz crystal oscillator work as bypass mode.
kCLOCK_24MOscLowPowerMode	24MHz crystal oscillator work as low power mode.

enum _clock_16MOsc_source

Enumerator
kCLOCK_16MOscSourceFrom16MOsc	Source from 16MHz RC oscialltor.
kCLOCK_16MOscSourceFrom24MOsc	Source from 24MHz crystal oscillator.

enum _clock_1MHzOut_behavior

Enumerator
kCLOCK_1MHzOutDisable	Disable 1MHz output clock.
kCLOCK_1MHzOutEnableLocked1Mhz	Enable 1MHz output clock, and select locked 1MHz to output.
kCLOCK_1MHzOutEnableFreeRunning1Mhz	Enable 1MHZ output clock, and select free-running 1MHz to output.

enum _clock_level

Enumerator
kCLOCK_Level0	Not needed in any mode.
kCLOCK_Level1	Needed in RUN mode.
kCLOCK_Level2	Needed in RUN and WAIT mode.
kCLOCK_Level3	Needed in RUN, WAIT and STOP mode.
kCLOCK_Level4	Always on in any mode.

Function Documentation

static void CLOCK_SetRootClockMux	(	clock_root_t	root,
		uint8_t	src
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
src	Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.

static uint32_t CLOCK_GetRootClockMux ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.

Returns: Clock mux value.

static clock_name_t CLOCK_GetRootClockSource	(	clock_root_t	root,
		uint32_t	src
	)

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.
src	Clock mux value to get, see clock_root_mux_source_t.

Returns: Clock source

static void CLOCK_SetRootClockDiv	(	clock_root_t	root,
		uint32_t	div
	)

inlinestatic

Parameters

root	Which root clock to set, see clock_root_t.
div	Clock div value to set range is 1-256, different divider has different value range.

static uint32_t CLOCK_GetRootClockDiv ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.

Returns: divider set for this root

static void CLOCK_PowerOffRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_PowerOnRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_SetRootClock	(	clock_root_t	root,
		const clock_root_config_t *	config
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
config	root clock config, see clock_root_config_t

static void CLOCK_ControlGate	(	clock_ip_name_t	name,
		clock_gate_value_t	value
	)

inlinestatic

Note: This API will not have any effect when this clock is in CPULPM or SetPoint Mode

Parameters

name	Which clock to enable, see clock_lpcg_t.
value	Clock gate value to set, see clock_gate_value_t.

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_lpcg_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_lpcg_t.

void CLOCK_SetGroupConfig	(	clock_group_t	group,
		const clock_group_config_t *	config
	)

Parameters

group	Which group to configure, see clock_group_t.
config	Configuration to set.

uint32_t CLOCK_GetFreq ( clock_name_t name )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

static uint32_t CLOCK_GetRootClockFreq ( clock_root_t root )

inlinestatic

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.

Parameters

root	Clock names defined in clock_root_t

Returns: Clock frequency value in hertz

static uint32_t CLOCK_GetM7Freq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static uint32_t CLOCK_GetM4Freq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsPllBypassed ( clock_pll_t pll )

inlinestatic

Parameters

pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is bypassed.
false: The PLL is not bypassed.

static bool CLOCK_IsPllEnabled ( clock_pll_t pll )

inlinestatic

Parameters

pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is enabled.
false: The PLL is not enabled.

static uint32_t CLOCK_GetRtcFreq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static void CLOCK_OSC_SetOsc48MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

static void CLOCK_OSC_EnableOsc48M ( bool enable )

inlinestatic

Parameters

enable

Used to enable or disable the 48MHz RC oscillator.

true Enable the 48MHz RC oscillator.
false Dissable the 48MHz RC oscillator.

static void CLOCK_OSC_SetOsc48MDiv2ControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

static void CLOCK_OSC_EnableOsc48MDiv2 ( bool enable )

inlinestatic

Note: The 48MHz RC oscillator must be enabled before enabling this 24MHz clock.

Parameters

enable

Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator.

true Enable the 24MHz clock sourced from 48MHz.
false Disable the 24MHz clock sourced from 48MHz.

static void CLOCK_OSC_SetOsc24MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOsc24M ( void )

This function enables OSC 24Mhz.

static void CLOCK_OSC_GateOsc24M ( bool enableGate )

inlinestatic

Note: Gating the 24MHz crystal oscillator can save power.

Parameters

enableGate

Used to gate/ungate the 24MHz crystal oscillator.

true Gate the 24MHz crystal oscillator to save power.
false Ungate the 24MHz crystal oscillator.

void CLOCK_OSC_SetOsc24MWorkMode ( clock_24MOsc_mode_t workMode )

Parameters

workMode The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

static void CLOCK_OSC_SetOscRc400MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOscRc400M ( void )

This function enables OSC RC 400Mhz.

static void CLOCK_OSC_GateOscRc400M ( bool enableGate )

inlinestatic

Parameters

enableGate

Used to gate/ungate 400MHz RC oscillator.

true Gate the 400MHz RC oscillator.
false Ungate the 400MHz RC oscillator.

void CLOCK_OSC_TrimOscRc400M	(	bool	enable,
		bool	bypass,
		uint16_t	trim
	)

Parameters

enable	Used to enable trim function.
bypass	Bypass the trim function.
trim	Trim value.

void CLOCK_OSC_SetOscRc400MRefClkDiv ( uint8_t divValue )

Note: slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters

divValue The divide value to be set, the available range is 0~63.

void CLOCK_OSC_SetOscRc400MFastClkCount ( uint16_t targetCount )

Parameters

targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

void CLOCK_OSC_SetOscRc400MHysteresisValue	(	uint8_t	negHysteresis,
		uint8_t	posHysteresis
	)

Note: The hysteresis value should be set after the clock is tuned.

Parameters

negHysteresis	The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
posHysteresis	The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

void CLOCK_OSC_BypassOscRc400MTuneLogic ( bool enableBypass )

Parameters

enableBypass

Used to control whether to bypass the turn logic.

true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
false Use the output of tune logic to run the oscillator.

void CLOCK_OSC_EnableOscRc400MTuneLogic ( bool enable )

Parameters

enable

Used to start or stop the tune logic.

true Start tuning
false Stop tuning and reset the tuning logic.

void CLOCK_OSC_FreezeOscRc400MTuneValue ( bool enableFreeze )

Parameters

enableFreeze

Used to control whether to freeze the tune value.

true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
false Unfreezes and continues the tune operation.

void CLOCK_OSC_SetOscRc400MTuneValue ( uint8_t tuneValue )

Parameters

tuneValue The tune value to determine the frequency of Oscillator.

void CLOCK_OSC_Set1MHzOutputBehavior ( clock_1MHzOut_behavior_t behavior )

Note: The 1MHz clock is divided from 400M RC Oscillator.

Parameters

behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

void CLOCK_OSC_SetLocked1MHzCount ( uint16_t count )

Parameters

count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

bool CLOCK_OSC_CheckLocked1MHzErrorFlag ( void )

Returns

The error flag for locked 1MHz clock out.

true The count value has been reached within one diviced ref clock period
false No effect.

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount ( void )

Returns: The current count for the fast clock.

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue ( void )

Returns: The current tune value.

static void CLOCK_OSC_SetOsc16MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_SetOsc16MConfig	(	clock_16MOsc_source_t	source,
		bool	enablePowerSave,
		bool	enableClockOut
	)

Parameters

source	Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t.
enablePowerSave	Enable/disable power save mode function at 16MHz OSC. true Enable power save mode function at 16MHz osc. false Disable power save mode function at 16MHz osc.
enableClockOut	Enable/Disable clock output for 16MHz RCOSC. true Enable clock output for 16MHz RCOSC. false Disable clock output for 16MHz RCOSC.

void CLOCK_InitArmPll ( const clock_arm_pll_config_t * config )

This function initialize the ARM PLL with specific settings

Parameters

config configuration to set to PLL.

status_t CLOCK_CalcArmPllFreq	(	clock_arm_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Arm PLL

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitArmPllWithFreq ( uint32_t freqInMhz )

This function initializes the Arm PLL with specific frequency

Parameters

freqInMhz target frequency

void CLOCK_CalcPllSpreadSpectrum	(	uint32_t	factor,
		uint32_t	range,
		uint32_t	mod,
		clock_pll_ss_config_t *	ss
	)

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/video/syspll1), the factor is denominator.

Parameters

factor	factor to calculate step/stop
range	spread spectrum range
mod	spread spectrum modulation frequency
ss	calculated spread spectrum values

void CLOCK_InitSysPll1 ( const clock_sys_pll1_config_t * config )

This function initializes the System PLL1 with specific settings

Parameters

config Configuration to set to PLL1.

void CLOCK_GPC_SetSysPll1OutputFreq ( const clock_sys_pll1_gpc_config_t * config )

Parameters

config Pointer to System PLL1 configure structure.

void CLOCK_InitSysPll2 ( const clock_sys_pll2_config_t * config )

This function initializes the System PLL2 with specific settings

Parameters

config Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

bool CLOCK_IsSysPll2PfdEnabled ( clock_pfd_t pfd )

Parameters

pfd	PFD control name

Returns

PFD bypass status.

true: power on.
false: power off.

Note: Only useful in software control mode.

void CLOCK_InitSysPll3 ( void )

This function initializes the System PLL3 with specific settings

bool CLOCK_IsSysPll3PfdEnabled ( clock_pfd_t pfd )

Parameters

pfd	PFD control name

Returns

PFD bypass status.

true: power on.
false: power off.

Note: Only useful in software control mode.

void CLOCK_SetPllBypass	(	clock_pll_t	pll,
		bool	bypass
	)

Parameters

pll	PLL control name (see clock_pll_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false:Not bypass the PLL.

status_t CLOCK_CalcAvPllFreq	(	clock_av_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Audio/Video PLL.

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitAudioPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

This function initializes the Audio PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

void CLOCK_InitAudioPll ( const clock_audio_pll_config_t * config )

This function initializes the Audio PLL with specific settings

Parameters

config Configuration to set to PLL.

void CLOCK_GPC_SetAudioPllOutputFreq ( const clock_audio_pll_gpc_config_t * config )

Parameters

config Pointer to clock_audio_pll_gpc_config_t structure.

status_t CLOCK_InitVideoPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

This function initializes the Video PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

void CLOCK_InitVideoPll ( const clock_video_pll_config_t * config )

This function configures the Video PLL with specific settings

Parameters

config configuration to set to PLL.

void CLOCK_GPC_SetVideoPllOutputFreq ( const clock_video_pll_gpc_config_t * config )

Parameters

config Pointer to Vidoe PLL configure structure.

uint32_t CLOCK_GetPllFreq ( clock_pll_t pll )

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns: The PLL output frequency in hertz.

void CLOCK_InitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd,
		uint8_t	frac
	)

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.
frac	The PFD FRAC value.

Note: It is recommended that PFD settings are kept between 12-35.

void CLOCK_DeinitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.

uint32_t CLOCK_GetPfdFreq	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

This function get current output frequency of specific System PLL PFD

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	pfd name to get frequency.

Returns: The PFD output frequency in hertz.

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs1Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs0PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs0PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs1PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

static void CLOCK_OSCPLL_LockControlMode ( clock_name_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

static void CLOCK_OSCPLL_LockWhiteList ( clock_name_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

static void CLOCK_OSCPLL_SetWhiteList	(	clock_name_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_OSCPLL_IsSetPointImplemented ( clock_name_t name )

inlinestatic

Parameters

name	Clock source name, see clock_name_t.

Returns

Clock source SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_OSCPLL_ControlByUnassignedMode ( clock_name_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

void CLOCK_OSCPLL_ControlBySetPointMode	(	clock_name_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_OSCPLL_ControlByCpuLowPowerMode	(	clock_name_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

static void CLOCK_OSCPLL_SetCurrentClockLevel	(	clock_name_t	name,
		clock_level_t	level
	)

inlinestatic

Note: This setting only take effects in CPU Low Power Mode.

Parameters

name	Clock source name, see clock_name_t.
level	Depend level of this clock.

static void CLOCK_OSCPLL_ControlByDomainMode	(	clock_name_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.

static void CLOCK_ROOT_LockControlMode ( clock_root_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_LockWhiteList ( clock_root_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_SetWhiteList	(	clock_root_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_ROOT_IsSetPointImplemented ( clock_root_t name )

inlinestatic

Parameters

name	Clock root name, see clock_root_t.

Returns

Clock root SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_ROOT_ControlByUnassignedMode ( clock_root_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_ConfigSetPoint	(	clock_root_t	name,
		uint16_t	spIndex,
		const clock_root_setpoint_config_t *	config
	)

inlinestatic

Note: SetPoint value could only be changed in Unassigend Mode.

Parameters

name	Which clock root to set, see clock_root_t.
spIndex	Which SetPoint of this clock root to set.
config	SetPoint config, see clock_root_setpoint_config_t

static void CLOCK_ROOT_EnableSetPointControl ( clock_root_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

void CLOCK_ROOT_ControlBySetPointMode	(	clock_root_t	name,
		const clock_root_setpoint_config_t *	spTable
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
spTable	Point to the array that stores clock root settings for each setpoint. Note that the pointed array must have 16 elements.

static void CLOCK_ROOT_ControlByDomainMode	(	clock_root_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
domainId	Domains that on the whitelist can change this clock.

static void CLOCK_LPCG_LockControlMode ( clock_lpcg_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

static void CLOCK_LPCG_LockWhiteList ( clock_lpcg_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

static void CLOCK_LPCG_SetWhiteList	(	clock_lpcg_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_LPCG_IsSetPointImplemented ( clock_lpcg_t name )

inlinestatic

Parameters

name	Clock gate name, see clock_lpcg_t.

Returns

Clock gate SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_LPCG_ControlByUnassignedMode ( clock_lpcg_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

void CLOCK_LPCG_ControlBySetPointMode	(	clock_lpcg_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_LPCG_ControlByCpuLowPowerMode	(	clock_lpcg_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

static void CLOCK_LPCG_SetCurrentClockLevel	(	clock_lpcg_t	name,
		clock_level_t	level
	)

inlinestatic

Note: This setting only take effects in CPU Low Power Mode.

Parameters

name	Clock gate name, see clock_lpcg_t.
level	Depend level of this clock.

static void CLOCK_LPCG_ControlByDomainMode	(	clock_lpcg_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.

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