Overview

The MCUXpresso SDK provides a peripheral driver for the Smart External DRAM Controller block of MCUXpresso SDK devices.

SEMC: Smart External DRAM Controller Driver

SEMC Initialization Operation

The SEMC Initialize is to initialize for common configure: gate the SEMC clock, configure IOMUX, and queue weight setting. The SEMC Deinitialize is to ungate the clock and disable SEMC module.

SEMC Interrupt Operation

The interrupt and disable operation for SEMC.

SEMC Memory access Operation

This group is mainly provide NAND/NOR memory access API which is through IP bus/ IP command access. Since the AXI access is directly read/write is so easy, so the AXI read/write part is not provided in SEMC.

Typical use case

Data Structures
struct	_semc_sdram_config
	SEMC SDRAM configuration structure. More...

struct	_semc_nand_timing_config
	SEMC NAND device timing configuration structure. More...

struct	_semc_nand_config
	SEMC NAND configuration structure. More...

struct	_semc_nor_config
	SEMC NOR configuration structure. More...

struct	_semc_sram_config
	SEMC SRAM configuration structure. More...

struct	_semc_dbi_config
	SEMC DBI configuration structure. More...

struct	_semc_queuea_weight_struct
	SEMC AXI queue a weight setting structure. More...

union	_semc_queuea_weight
	SEMC AXI queue a weight setting union. More...

struct	_semc_queueb_weight_struct
	SEMC AXI queue b weight setting structure. More...

union	_semc_queueb_weight
	SEMC AXI queue b weight setting union. More...

struct	_semc_axi_queueweight
	SEMC AXI queue weight setting. More...

struct	_semc_config_t
	SEMC configuration structure. More...

Typedefs
typedef enum _semc_mem_type	semc_mem_type_t
	SEMC memory device type. More...

typedef enum _semc_waitready_polarity	semc_waitready_polarity_t
	SEMC WAIT/RDY polarity. More...

typedef enum _semc_sdram_cs	semc_sdram_cs_t
	SEMC SDRAM Chip selection . More...

typedef enum _semc_sram_cs	semc_sram_cs_t
	SEMC SRAM Chip selection . More...

typedef enum _semc_nand_access_type	semc_nand_access_type_t
	SEMC NAND device type. More...

typedef enum _semc_interrupt_enable	semc_interrupt_enable_t
	SEMC interrupts . More...

typedef enum _semc_ipcmd_datasize	semc_ipcmd_datasize_t
	SEMC IP command data size in bytes. More...

typedef enum _semc_refresh_time	semc_refresh_time_t
	SEMC auto-refresh timing. More...

typedef enum _semc_caslatency	semc_caslatency_t
	CAS latency.

typedef enum _semc_sdram_column_bit_num	semc_sdram_column_bit_num_t
	SEMC sdram column address bit number. More...

typedef enum _semc_sdram_burst_len	sem_sdram_burst_len_t
	SEMC sdram burst length. More...

typedef enum _semc_nand_column_bit_num	semc_nand_column_bit_num_t
	SEMC nand column address bit number. More...

typedef enum _semc_nand_burst_len	sem_nand_burst_len_t
	SEMC nand burst length. More...

typedef enum _semc_norsram_column_bit_num	semc_norsram_column_bit_num_t
	SEMC nor/sram column address bit number. More...

typedef enum _semc_norsram_burst_len	sem_norsram_burst_len_t
	SEMC nor/sram burst length. More...

typedef enum _semc_dbi_column_bit_num	semc_dbi_column_bit_num_t
	SEMC dbi column address bit number. More...

typedef enum _semc_dbi_burst_len	sem_dbi_burst_len_t
	SEMC dbi burst length. More...

typedef enum _semc_iomux_pin	semc_iomux_pin
	SEMC IOMUXC. More...

typedef enum _semc_iomux_nora27_pin	semc_iomux_nora27_pin
	SEMC NOR/PSRAM Address bit 27 A27. More...

typedef enum _semc_port_size	smec_port_size_t
	SEMC port size. More...

typedef enum _semc_addr_mode	semc_addr_mode_t
	SEMC address mode. More...

typedef enum _semc_dqs_mode	semc_dqs_mode_t
	SEMC DQS read strobe mode. More...

typedef enum _semc_adv_polarity	semc_adv_polarity_t
	SEMC ADV signal active polarity. More...

typedef enum _semc_sync_mode	semc_sync_mode_t
	SEMC sync mode. More...

typedef enum _semc_adv_level_control	semc_adv_level_control_t
	SEMC ADV signal level control. More...

typedef enum _semc_rdy_polarity	semc_rdy_polarity_t
	SEMC RDY signal active polarity. More...

typedef enum _semc_ipcmd_nand_addrmode	semc_ipcmd_nand_addrmode_t
	SEMC IP command for NAND: address mode. More...

typedef enum _semc_ipcmd_nand_cmdmode	semc_ipcmd_nand_cmdmode_t
	SEMC IP command for NAND： command mode. More...

typedef enum _semc_nand_address_option	semc_nand_address_option_t
	SEMC NAND address option. More...

typedef enum _semc_ipcmd_nor_dbi	semc_ipcmd_nor_dbi_t
	SEMC IP command for NOR. More...

typedef enum _semc_ipcmd_sram	semc_ipcmd_sram_t
	SEMC IP command for SRAM. More...

typedef enum _semc_ipcmd_sdram	semc_ipcmd_sdram_t
	SEMC IP command for SDARM. More...

typedef struct _semc_sdram_config	semc_sdram_config_t
	SEMC SDRAM configuration structure. More...

typedef struct _semc_nand_timing_config	semc_nand_timing_config_t
	SEMC NAND device timing configuration structure. More...

typedef struct _semc_nand_config	semc_nand_config_t
	SEMC NAND configuration structure. More...

typedef struct _semc_nor_config	semc_nor_config_t
	SEMC NOR configuration structure. More...

typedef struct _semc_sram_config	semc_sram_config_t
	SEMC SRAM configuration structure. More...

typedef struct _semc_dbi_config	semc_dbi_config_t
	SEMC DBI configuration structure. More...

typedef struct _semc_queuea_weight_struct	semc_queuea_weight_struct_t
	SEMC AXI queue a weight setting structure. More...

typedef union _semc_queuea_weight	semc_queuea_weight_t
	SEMC AXI queue a weight setting union. More...

typedef struct _semc_queueb_weight_struct	semc_queueb_weight_struct_t
	SEMC AXI queue b weight setting structure. More...

typedef union _semc_queueb_weight	semc_queueb_weight_t
	SEMC AXI queue b weight setting union. More...

typedef struct _semc_axi_queueweight	semc_axi_queueweight_t
	SEMC AXI queue weight setting. More...

typedef struct _semc_config_t	semc_config_t
	SEMC configuration structure. More...

Enumerations
enum	{ kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11) }
	SEMC status, _semc_status. More...

enum	_semc_mem_type { kSEMC_MemType_SDRAM = 0, kSEMC_MemType_SRAM, kSEMC_MemType_NOR, kSEMC_MemType_NAND, kSEMC_MemType_8080 }
	SEMC memory device type. More...

enum	_semc_waitready_polarity { kSEMC_LowActive = 0, kSEMC_HighActive }
	SEMC WAIT/RDY polarity. More...

enum	_semc_sdram_cs { kSEMC_SDRAM_CS0 = 0, kSEMC_SDRAM_CS1, kSEMC_SDRAM_CS2, kSEMC_SDRAM_CS3 }
	SEMC SDRAM Chip selection . More...

enum	_semc_sram_cs { kSEMC_SRAM_CS0 = 0, kSEMC_SRAM_CS1, kSEMC_SRAM_CS2, kSEMC_SRAM_CS3 }
	SEMC SRAM Chip selection . More...

enum	_semc_nand_access_type { kSEMC_NAND_ACCESS_BY_AXI = 0, kSEMC_NAND_ACCESS_BY_IPCMD }
	SEMC NAND device type. More...

enum	_semc_interrupt_enable { kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK }
	SEMC interrupts . More...

enum	_semc_ipcmd_datasize { kSEMC_IPcmdDataSize_1bytes = 1, kSEMC_IPcmdDataSize_2bytes, kSEMC_IPcmdDataSize_3bytes, kSEMC_IPcmdDataSize_4bytes }
	SEMC IP command data size in bytes. More...

enum	_semc_refresh_time { kSEMC_RefreshThreeClocks = 0x0U, kSEMC_RefreshSixClocks, kSEMC_RefreshNineClocks }
	SEMC auto-refresh timing. More...

enum	_semc_caslatency { kSEMC_LatencyOne = 1, kSEMC_LatencyTwo, kSEMC_LatencyThree }
	CAS latency. More...

enum	_semc_sdram_column_bit_num { kSEMC_SdramColunm_12bit = 0x0U, kSEMC_SdramColunm_11bit, kSEMC_SdramColunm_10bit, kSEMC_SdramColunm_9bit, kSEMC_SdramColunm_8bit }
	SEMC sdram column address bit number. More...

enum	_semc_sdram_burst_len { kSEMC_Sdram_BurstLen1 = 0, kSEMC_Sdram_BurstLen2, kSEMC_Sdram_BurstLen4, kSEMC_Sdram_BurstLen8 }
	SEMC sdram burst length. More...

enum	_semc_nand_column_bit_num { kSEMC_NandColum_16bit = 0x0U, kSEMC_NandColum_15bit, kSEMC_NandColum_14bit, kSEMC_NandColum_13bit, kSEMC_NandColum_12bit, kSEMC_NandColum_11bit, kSEMC_NandColum_10bit, kSEMC_NandColum_9bit }
	SEMC nand column address bit number. More...

enum	_semc_nand_burst_len { kSEMC_Nand_BurstLen1 = 0, kSEMC_Nand_BurstLen2, kSEMC_Nand_BurstLen4, kSEMC_Nand_BurstLen8, kSEMC_Nand_BurstLen16, kSEMC_Nand_BurstLen32, kSEMC_Nand_BurstLen64 }
	SEMC nand burst length. More...

enum	_semc_norsram_column_bit_num { kSEMC_NorColum_12bit = 0x0U, kSEMC_NorColum_11bit, kSEMC_NorColum_10bit, kSEMC_NorColum_9bit, kSEMC_NorColum_8bit, kSEMC_NorColum_7bit, kSEMC_NorColum_6bit, kSEMC_NorColum_5bit, kSEMC_NorColum_4bit, kSEMC_NorColum_3bit, kSEMC_NorColum_2bit }
	SEMC nor/sram column address bit number. More...

enum	_semc_norsram_burst_len { kSEMC_Nor_BurstLen1 = 0, kSEMC_Nor_BurstLen2, kSEMC_Nor_BurstLen4, kSEMC_Nor_BurstLen8, kSEMC_Nor_BurstLen16, kSEMC_Nor_BurstLen32, kSEMC_Nor_BurstLen64 }
	SEMC nor/sram burst length. More...

enum	_semc_dbi_column_bit_num { kSEMC_Dbi_Colum_12bit = 0x0U, kSEMC_Dbi_Colum_11bit, kSEMC_Dbi_Colum_10bit, kSEMC_Dbi_Colum_9bit, kSEMC_Dbi_Colum_8bit, kSEMC_Dbi_Colum_7bit, kSEMC_Dbi_Colum_6bit, kSEMC_Dbi_Colum_5bit, kSEMC_Dbi_Colum_4bit, kSEMC_Dbi_Colum_3bit, kSEMC_Dbi_Colum_2bit }
	SEMC dbi column address bit number. More...

enum	_semc_dbi_burst_len { kSEMC_Dbi_BurstLen1 = 0, kSEMC_Dbi_BurstLen2, kSEMC_Dbi_Dbi_BurstLen4, kSEMC_Dbi_BurstLen8, kSEMC_Dbi_BurstLen16, kSEMC_Dbi_BurstLen32, kSEMC_Dbi_BurstLen64 }
	SEMC dbi burst length. More...

enum	_semc_iomux_pin { kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT }
	SEMC IOMUXC. More...

enum	_semc_iomux_nora27_pin { kSEMC_MORA27_NONE = 0, kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT }
	SEMC NOR/PSRAM Address bit 27 A27. More...

enum	_semc_port_size { kSEMC_PortSize8Bit = 0, kSEMC_PortSize16Bit, kSEMC_PortSize32Bit }
	SEMC port size. More...

enum	_semc_addr_mode { kSEMC_AddrDataMux = 0, kSEMC_AdvAddrdataMux, kSEMC_AddrDataNonMux }
	SEMC address mode. More...

enum	_semc_dqs_mode { kSEMC_Loopbackinternal = 0, kSEMC_Loopbackdqspad }
	SEMC DQS read strobe mode. More...

enum	_semc_adv_polarity { kSEMC_AdvActiveLow = 0, kSEMC_AdvActiveHigh }
	SEMC ADV signal active polarity. More...

enum	_semc_sync_mode { kSEMC_AsyncMode = 0, kSEMC_SyncMode }
	SEMC sync mode. More...

enum	_semc_adv_level_control { kSEMC_AdvHigh = 0, kSEMC_AdvLow }
	SEMC ADV signal level control. More...

enum	_semc_rdy_polarity { kSEMC_RdyActiveLow = 0, kSEMC_RdyActivehigh }
	SEMC RDY signal active polarity. More...

enum	_semc_ipcmd_nand_addrmode { kSEMC_NANDAM_ColumnRow = 0x0U, kSEMC_NANDAM_ColumnCA0, kSEMC_NANDAM_ColumnCA0CA1, kSEMC_NANDAM_RawRA0, kSEMC_NANDAM_RawRA0RA1, kSEMC_NANDAM_RawRA0RA1RA2 }
	SEMC IP command for NAND: address mode. More...

enum	_semc_ipcmd_nand_cmdmode { kSEMC_NANDCM_Command = 0x2U, kSEMC_NANDCM_CommandHold, kSEMC_NANDCM_CommandAddress, kSEMC_NANDCM_CommandAddressHold, kSEMC_NANDCM_CommandAddressRead, kSEMC_NANDCM_CommandAddressWrite, kSEMC_NANDCM_CommandRead, kSEMC_NANDCM_CommandWrite, kSEMC_NANDCM_Read, kSEMC_NANDCM_Write }
	SEMC IP command for NAND： command mode. More...

enum	_semc_nand_address_option { kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, kSEMC_NandAddrOption_2byte_CA1RA1 = 7U }
	SEMC NAND address option. More...

enum	_semc_ipcmd_nor_dbi { kSEMC_NORDBICM_Read = 0x2U, kSEMC_NORDBICM_Write }
	SEMC IP command for NOR. More...

enum	_semc_ipcmd_sram { kSEMC_SRAMCM_ArrayRead = 0x2U, kSEMC_SRAMCM_ArrayWrite, kSEMC_SRAMCM_RegRead, kSEMC_SRAMCM_RegWrite }
	SEMC IP command for SRAM. More...

enum	_semc_ipcmd_sdram { kSEMC_SDRAMCM_Read = 0x8U, kSEMC_SDRAMCM_Write, kSEMC_SDRAMCM_Modeset, kSEMC_SDRAMCM_Active, kSEMC_SDRAMCM_AutoRefresh, kSEMC_SDRAMCM_SelfRefresh, kSEMC_SDRAMCM_Precharge, kSEMC_SDRAMCM_Prechargeall }
	SEMC IP command for SDARM. More...

Driver version
#define	FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))
	SEMC driver version. More...

SEMC Initialization and De-initialization
void	SEMC_GetDefaultConfig (semc_config_t *config)
	Gets the SEMC default basic configuration structure. More...

void	SEMC_Init (SEMC_Type base, semc_config_t configure)
	Initializes SEMC. More...

void	SEMC_Deinit (SEMC_Type *base)
	Deinitializes the SEMC module and gates the clock. More...

SEMC Configuration Operation For Each Memory Type
status_t	SEMC_ConfigureSDRAM (SEMC_Type base, semc_sdram_cs_t cs, semc_sdram_config_t config, uint32_t clkSrc_Hz)
	Configures SDRAM controller in SEMC. More...

status_t	SEMC_ConfigureNAND (SEMC_Type base, semc_nand_config_t config, uint32_t clkSrc_Hz)
	Configures NAND controller in SEMC. More...

status_t	SEMC_ConfigureNOR (SEMC_Type base, semc_nor_config_t config, uint32_t clkSrc_Hz)
	Configures NOR controller in SEMC. More...

status_t	SEMC_ConfigureSRAMWithChipSelection (SEMC_Type base, semc_sram_cs_t cs, semc_sram_config_t config, uint32_t clkSrc_Hz)
	Configures SRAM controller in SEMC. More...

status_t	SEMC_ConfigureSRAM (SEMC_Type base, semc_sram_config_t config, uint32_t clkSrc_Hz)
	Configures SRAM controller in SEMC. More...

status_t	SEMC_ConfigureDBI (SEMC_Type base, semc_dbi_config_t config, uint32_t clkSrc_Hz)
	Configures DBI controller in SEMC. More...

SEMC Interrupt Operation
static void	SEMC_EnableInterrupts (SEMC_Type *base, uint32_t mask)
	Enables the SEMC interrupt. More...

static void	SEMC_DisableInterrupts (SEMC_Type *base, uint32_t mask)
	Disables the SEMC interrupt. More...

static bool	SEMC_GetStatusFlag (SEMC_Type *base)
	Gets the SEMC status. More...

static void	SEMC_ClearStatusFlags (SEMC_Type *base, uint32_t mask)
	Clears the SEMC status flag state. More...

SEMC Memory Access Operation
static bool	SEMC_IsInIdle (SEMC_Type *base)
	Check if SEMC is in idle. More...

status_t	SEMC_SendIPCommand (SEMC_Type base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t read)
	SEMC IP command access. More...

static uint16_t	SEMC_BuildNandIPCommand (uint8_t userCommand, semc_ipcmd_nand_addrmode_t addrMode, semc_ipcmd_nand_cmdmode_t cmdMode)
	Build SEMC IP command for NAND. More...

static bool	SEMC_IsNandReady (SEMC_Type *base)
	Check if the NAND device is ready. More...

status_t	SEMC_IPCommandNandWrite (SEMC_Type base, uint32_t address, uint8_t data, uint32_t size_bytes)
	SEMC NAND device memory write through IP command. More...

status_t	SEMC_IPCommandNandRead (SEMC_Type base, uint32_t address, uint8_t data, uint32_t size_bytes)
	SEMC NAND device memory read through IP command. More...

status_t	SEMC_IPCommandNorWrite (SEMC_Type base, uint32_t address, uint8_t data, uint32_t size_bytes)
	SEMC NOR device memory write through IP command. More...

status_t	SEMC_IPCommandNorRead (SEMC_Type base, uint32_t address, uint8_t data, uint32_t size_bytes)
	SEMC NOR device memory read through IP command. More...

Data Structure Documentation

struct _semc_sdram_config

The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

Data Fields
semc_iomux_pin	csxPinMux
	CS pin mux. More...

uint32_t	address
	The base address. More...

uint32_t	memsize_kbytes
	The memory size in unit of kbytes. More...

smec_port_size_t	portSize
	Port size. More...

sem_sdram_burst_len_t	burstLen
	Burst length. More...

semc_sdram_column_bit_num_t	columnAddrBitNum
	Column address bit number. More...

semc_caslatency_t	casLatency
	CAS latency. More...

uint8_t	tPrecharge2Act_Ns
	Precharge to active wait time in unit of nanosecond. More...

uint8_t	tAct2ReadWrite_Ns
	Act to read/write wait time in unit of nanosecond. More...

uint8_t	tRefreshRecovery_Ns
	Refresh recovery time in unit of nanosecond. More...

uint8_t	tWriteRecovery_Ns
	write recovery time in unit of nanosecond. More...

uint8_t	tCkeOff_Ns
	CKE off minimum time in unit of nanosecond. More...

uint8_t	tAct2Prechage_Ns
	Active to precharge in unit of nanosecond. More...

uint8_t	tSelfRefRecovery_Ns
	Self refresh recovery time in unit of nanosecond. More...

uint8_t	tRefresh2Refresh_Ns
	Refresh to refresh wait time in unit of nanosecond. More...

uint8_t	tAct2Act_Ns
	Active to active wait time in unit of nanosecond. More...

uint32_t	tPrescalePeriod_Ns
	Prescaler timer period should not be larger than 256 * 16 * clock cycle. More...

uint32_t	tIdleTimeout_Ns
	Idle timeout in unit of prescale time period. More...

uint32_t	refreshPeriod_nsPerRow
	Refresh timer period like 64ms * 1000000/8192 . More...

uint32_t	refreshUrgThreshold
	Refresh urgent threshold. More...

uint8_t	refreshBurstLen
	Refresh burst length. More...

uint8_t	delayChain
	Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data. More...

uint8_t	autofreshTimes
	Auto Refresh cycles times. More...

Field Documentation

semc_iomux_pin _semc_sdram_config::csxPinMux

The kSEMC_MUXA8 is not valid in sdram pin mux setting.

uint32_t _semc_sdram_config::address

uint32_t _semc_sdram_config::memsize_kbytes

smec_port_size_t _semc_sdram_config::portSize

sem_sdram_burst_len_t _semc_sdram_config::burstLen

semc_sdram_column_bit_num_t _semc_sdram_config::columnAddrBitNum

semc_caslatency_t _semc_sdram_config::casLatency

uint8_t _semc_sdram_config::tPrecharge2Act_Ns

uint8_t _semc_sdram_config::tAct2ReadWrite_Ns

uint8_t _semc_sdram_config::tRefreshRecovery_Ns

uint8_t _semc_sdram_config::tWriteRecovery_Ns

uint8_t _semc_sdram_config::tCkeOff_Ns

uint8_t _semc_sdram_config::tAct2Prechage_Ns

uint8_t _semc_sdram_config::tSelfRefRecovery_Ns

uint8_t _semc_sdram_config::tRefresh2Refresh_Ns

uint8_t _semc_sdram_config::tAct2Act_Ns

uint32_t _semc_sdram_config::tPrescalePeriod_Ns

uint32_t _semc_sdram_config::tIdleTimeout_Ns

uint32_t _semc_sdram_config::refreshPeriod_nsPerRow

uint32_t _semc_sdram_config::refreshUrgThreshold

uint8_t _semc_sdram_config::refreshBurstLen

uint8_t _semc_sdram_config::delayChain

uint8_t _semc_sdram_config::autofreshTimes

struct _semc_nand_timing_config

Data Fields
uint8_t	tCeSetup_Ns
	CE setup time: tCS. More...

uint8_t	tCeHold_Ns
	CE hold time: tCH. More...

uint8_t	tCeInterval_Ns
	CE interval time:tCEITV. More...

uint8_t	tWeLow_Ns
	WE low time: tWP. More...

uint8_t	tWeHigh_Ns
	WE high time: tWH. More...

uint8_t	tReLow_Ns
	RE low time: tRP. More...

uint8_t	tReHigh_Ns
	RE high time: tREH. More...

uint8_t	tTurnAround_Ns
	Turnaround time for async mode: tTA. More...

uint8_t	tWehigh2Relow_Ns
	WE# high to RE# wait time: tWHR. More...

uint8_t	tRehigh2Welow_Ns
	RE# high to WE# low wait time: tRHW. More...

uint8_t	tAle2WriteStart_Ns
	ALE to write start wait time: tADL. More...

uint8_t	tReady2Relow_Ns
	Ready to RE# low min wait time: tRR. More...

uint8_t	tWehigh2Busy_Ns
	WE# high to busy wait time: tWB. More...

Field Documentation

uint8_t _semc_nand_timing_config::tCeSetup_Ns

uint8_t _semc_nand_timing_config::tCeHold_Ns

uint8_t _semc_nand_timing_config::tCeInterval_Ns

uint8_t _semc_nand_timing_config::tWeLow_Ns

uint8_t _semc_nand_timing_config::tWeHigh_Ns

uint8_t _semc_nand_timing_config::tReLow_Ns

uint8_t _semc_nand_timing_config::tReHigh_Ns

uint8_t _semc_nand_timing_config::tTurnAround_Ns

uint8_t _semc_nand_timing_config::tWehigh2Relow_Ns

uint8_t _semc_nand_timing_config::tRehigh2Welow_Ns

uint8_t _semc_nand_timing_config::tAle2WriteStart_Ns

uint8_t _semc_nand_timing_config::tReady2Relow_Ns

uint8_t _semc_nand_timing_config::tWehigh2Busy_Ns

struct _semc_nand_config

Data Fields
semc_iomux_pin	cePinMux
	The CE pin mux setting. More...

uint32_t	axiAddress
	The base address for AXI nand. More...

uint32_t	axiMemsize_kbytes
	The memory size in unit of kbytes for AXI nand. More...

uint32_t	ipgAddress
	The base address for IPG nand . More...

uint32_t	ipgMemsize_kbytes
	The memory size in unit of kbytes for IPG nand. More...

semc_rdy_polarity_t	rdyactivePolarity
	Wait ready polarity. More...

bool	edoModeEnabled
	EDO mode enabled. More...

semc_nand_column_bit_num_t	columnAddrBitNum
	Column address bit number. More...

semc_nand_address_option_t	arrayAddrOption
	Address option. More...

sem_nand_burst_len_t	burstLen
	Burst length. More...

smec_port_size_t	portSize
	Port size. More...

semc_nand_timing_config_t *	timingConfig
	SEMC nand timing configuration. More...

Field Documentation

semc_iomux_pin _semc_nand_config::cePinMux

The kSEMC_MUXRDY is not valid for CE pin setting.

uint32_t _semc_nand_config::axiAddress

uint32_t _semc_nand_config::axiMemsize_kbytes

uint32_t _semc_nand_config::ipgAddress

uint32_t _semc_nand_config::ipgMemsize_kbytes

semc_rdy_polarity_t _semc_nand_config::rdyactivePolarity

bool _semc_nand_config::edoModeEnabled

semc_nand_column_bit_num_t _semc_nand_config::columnAddrBitNum

semc_nand_address_option_t _semc_nand_config::arrayAddrOption

sem_nand_burst_len_t _semc_nand_config::burstLen

smec_port_size_t _semc_nand_config::portSize

semc_nand_timing_config_t* _semc_nand_config::timingConfig

struct _semc_nor_config

Data Fields
semc_iomux_pin	cePinMux
	The CE# pin mux setting. More...

semc_iomux_nora27_pin	addr27
	The Addr bit 27 pin mux setting. More...

uint32_t	address
	The base address. More...

uint32_t	memsize_kbytes
	The memory size in unit of kbytes. More...

uint8_t	addrPortWidth
	The address port width. More...

semc_rdy_polarity_t	rdyactivePolarity
	Wait ready polarity. More...

semc_adv_polarity_t	advActivePolarity
	ADV# polarity. More...

semc_norsram_column_bit_num_t	columnAddrBitNum
	Column address bit number. More...

semc_addr_mode_t	addrMode
	Address mode. More...

sem_norsram_burst_len_t	burstLen
	Burst length. More...

smec_port_size_t	portSize
	Port size. More...

uint8_t	tCeSetup_Ns
	The CE setup time. More...

uint8_t	tCeHold_Ns
	The CE hold time. More...

uint8_t	tCeInterval_Ns
	CE interval minimum time. More...

uint8_t	tAddrSetup_Ns
	The address setup time. More...

uint8_t	tAddrHold_Ns
	The address hold time. More...

uint8_t	tWeLow_Ns
	WE low time for async mode. More...

uint8_t	tWeHigh_Ns
	WE high time for async mode. More...

uint8_t	tReLow_Ns
	RE low time for async mode. More...

uint8_t	tReHigh_Ns
	RE high time for async mode. More...

uint8_t	tTurnAround_Ns
	Turnaround time for async mode. More...

uint8_t	tAddr2WriteHold_Ns
	Address to write data hold time for async mode. More...

uint8_t	latencyCount
	Latency count for sync mode. More...

uint8_t	readCycle
	Read cycle time for sync mode. More...

uint8_t	delayChain
	Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data. More...

Field Documentation

semc_iomux_pin _semc_nor_config::cePinMux

semc_iomux_nora27_pin _semc_nor_config::addr27

uint32_t _semc_nor_config::address

uint32_t _semc_nor_config::memsize_kbytes

uint8_t _semc_nor_config::addrPortWidth

semc_rdy_polarity_t _semc_nor_config::rdyactivePolarity

semc_adv_polarity_t _semc_nor_config::advActivePolarity

semc_norsram_column_bit_num_t _semc_nor_config::columnAddrBitNum

semc_addr_mode_t _semc_nor_config::addrMode

sem_norsram_burst_len_t _semc_nor_config::burstLen

smec_port_size_t _semc_nor_config::portSize

uint8_t _semc_nor_config::tCeSetup_Ns

uint8_t _semc_nor_config::tCeHold_Ns

uint8_t _semc_nor_config::tCeInterval_Ns

uint8_t _semc_nor_config::tAddrSetup_Ns

uint8_t _semc_nor_config::tAddrHold_Ns

uint8_t _semc_nor_config::tWeLow_Ns

uint8_t _semc_nor_config::tWeHigh_Ns

uint8_t _semc_nor_config::tReLow_Ns

uint8_t _semc_nor_config::tReHigh_Ns

uint8_t _semc_nor_config::tTurnAround_Ns

uint8_t _semc_nor_config::tAddr2WriteHold_Ns

uint8_t _semc_nor_config::latencyCount

uint8_t _semc_nor_config::readCycle

uint8_t _semc_nor_config::delayChain

struct _semc_sram_config

Data Fields
semc_iomux_pin	cePinMux
	The CE# pin mux setting. More...

semc_iomux_nora27_pin	addr27
	The Addr bit 27 pin mux setting. More...

uint32_t	address
	The base address. More...

uint32_t	memsize_kbytes
	The memory size in unit of kbytes. More...

uint8_t	addrPortWidth
	The address port width. More...

semc_adv_polarity_t	advActivePolarity
	ADV# polarity 1: active high, 0: active low. More...

semc_addr_mode_t	addrMode
	Address mode. More...

sem_norsram_burst_len_t	burstLen
	Burst length. More...

smec_port_size_t	portSize
	Port size. More...

semc_sync_mode_t	syncMode
	Sync mode. More...

bool	waitEnable
	Wait enable. More...

uint8_t	waitSample
	Wait sample. More...

semc_adv_level_control_t	advLevelCtrl
	ADV# level control during address hold state, 1: low, 0: high. More...

uint8_t	tCeSetup_Ns
	The CE setup time. More...

uint8_t	tCeHold_Ns
	The CE hold time. More...

uint8_t	tCeInterval_Ns
	CE interval minimum time. More...

uint8_t	readHoldTime_Ns
	read hold time. More...

uint8_t	tAddrSetup_Ns
	The address setup time. More...

uint8_t	tAddrHold_Ns
	The address hold time. More...

uint8_t	tWeLow_Ns
	WE low time for async mode. More...

uint8_t	tWeHigh_Ns
	WE high time for async mode. More...

uint8_t	tReLow_Ns
	RE low time for async mode. More...

uint8_t	tReHigh_Ns
	RE high time for async mode. More...

uint8_t	tTurnAround_Ns
	Turnaround time for async mode. More...

uint8_t	tAddr2WriteHold_Ns
	Address to write data hold time for async mode. More...

uint8_t	tWriteSetup_Ns
	Write data setup time for sync mode. More...

uint8_t	tWriteHold_Ns
	Write hold time for sync mode. More...

uint8_t	latencyCount
	Latency count for sync mode. More...

uint8_t	readCycle
	Read cycle time for sync mode. More...

uint8_t	delayChain
	Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data. More...

Field Documentation

semc_iomux_pin _semc_sram_config::cePinMux

semc_iomux_nora27_pin _semc_sram_config::addr27

uint32_t _semc_sram_config::address

uint32_t _semc_sram_config::memsize_kbytes

uint8_t _semc_sram_config::addrPortWidth

semc_adv_polarity_t _semc_sram_config::advActivePolarity

semc_addr_mode_t _semc_sram_config::addrMode

sem_norsram_burst_len_t _semc_sram_config::burstLen

smec_port_size_t _semc_sram_config::portSize

semc_sync_mode_t _semc_sram_config::syncMode

bool _semc_sram_config::waitEnable

uint8_t _semc_sram_config::waitSample

semc_adv_level_control_t _semc_sram_config::advLevelCtrl

uint8_t _semc_sram_config::tCeSetup_Ns

uint8_t _semc_sram_config::tCeHold_Ns

uint8_t _semc_sram_config::tCeInterval_Ns

uint8_t _semc_sram_config::readHoldTime_Ns

uint8_t _semc_sram_config::tAddrSetup_Ns

uint8_t _semc_sram_config::tAddrHold_Ns

uint8_t _semc_sram_config::tWeLow_Ns

uint8_t _semc_sram_config::tWeHigh_Ns

uint8_t _semc_sram_config::tReLow_Ns

uint8_t _semc_sram_config::tReHigh_Ns

uint8_t _semc_sram_config::tTurnAround_Ns

uint8_t _semc_sram_config::tAddr2WriteHold_Ns

uint8_t _semc_sram_config::tWriteSetup_Ns

uint8_t _semc_sram_config::tWriteHold_Ns

uint8_t _semc_sram_config::latencyCount

uint8_t _semc_sram_config::readCycle

uint8_t _semc_sram_config::delayChain

struct _semc_dbi_config

Data Fields
semc_iomux_pin	csxPinMux
	The CE# pin mux. More...

uint32_t	address
	The base address. More...

uint32_t	memsize_kbytes
	The memory size in unit of 4kbytes. More...

semc_dbi_column_bit_num_t	columnAddrBitNum
	Column address bit number. More...

sem_dbi_burst_len_t	burstLen
	Burst length. More...

smec_port_size_t	portSize
	Port size. More...

uint8_t	tCsxSetup_Ns
	The CSX setup time. More...

uint8_t	tCsxHold_Ns
	The CSX hold time. More...

uint8_t	tWexLow_Ns
	WEX low time. More...

uint8_t	tWexHigh_Ns
	WEX high time. More...

uint8_t	tRdxLow_Ns
	RDX low time. More...

uint8_t	tRdxHigh_Ns
	RDX high time. More...

uint8_t	tCsxInterval_Ns
	Write data setup time. More...

Field Documentation

semc_iomux_pin _semc_dbi_config::csxPinMux

uint32_t _semc_dbi_config::address

uint32_t _semc_dbi_config::memsize_kbytes

semc_dbi_column_bit_num_t _semc_dbi_config::columnAddrBitNum

sem_dbi_burst_len_t _semc_dbi_config::burstLen

smec_port_size_t _semc_dbi_config::portSize

uint8_t _semc_dbi_config::tCsxSetup_Ns

uint8_t _semc_dbi_config::tCsxHold_Ns

uint8_t _semc_dbi_config::tWexLow_Ns

uint8_t _semc_dbi_config::tWexHigh_Ns

uint8_t _semc_dbi_config::tRdxLow_Ns

uint8_t _semc_dbi_config::tRdxHigh_Ns

uint8_t _semc_dbi_config::tCsxInterval_Ns

struct _semc_queuea_weight_struct

Data Fields
uint32_t	qos: 4
	weight of qos for queue 0 . More...

uint32_t	aging: 4
	weight of aging for queue 0. More...

uint32_t	slaveHitNoswitch: 8
	weight of read/write no switch for queue 0 . More...

uint32_t	slaveHitSwitch: 8
	weight of read/write switch for queue 0. More...

Field Documentation

uint32_t _semc_queuea_weight_struct::qos

uint32_t _semc_queuea_weight_struct::aging

uint32_t _semc_queuea_weight_struct::slaveHitNoswitch

uint32_t _semc_queuea_weight_struct::slaveHitSwitch

union _semc_queuea_weight

Data Fields
semc_queuea_weight_struct_t	queueaConfig
	Structure configuration for queueA. More...

uint32_t	queueaValue
	Configuration value for queueA which could directly write to the reg. More...

Field Documentation

semc_queuea_weight_struct_t _semc_queuea_weight::queueaConfig

uint32_t _semc_queuea_weight::queueaValue

struct _semc_queueb_weight_struct

Data Fields
uint32_t	qos: 4
	weight of qos for queue 1. More...

uint32_t	aging: 4
	weight of aging for queue 1. More...

uint32_t	weightPagehit: 8
	weight of page hit for queue 1 only . More...

uint32_t	slaveHitNoswitch: 8
	weight of read/write no switch for queue 1. More...

uint32_t	bankRotation: 8
	weight of bank rotation for queue 1 only . More...

Field Documentation

uint32_t _semc_queueb_weight_struct::qos

uint32_t _semc_queueb_weight_struct::aging

uint32_t _semc_queueb_weight_struct::weightPagehit

uint32_t _semc_queueb_weight_struct::slaveHitNoswitch

uint32_t _semc_queueb_weight_struct::bankRotation

union _semc_queueb_weight

Data Fields
semc_queueb_weight_struct_t	queuebConfig
	Structure configuration for queueB. More...

uint32_t	queuebValue
	Configuration value for queueB which could directly write to the reg. More...

Field Documentation

semc_queueb_weight_struct_t _semc_queueb_weight::queuebConfig

uint32_t _semc_queueb_weight::queuebValue

struct _semc_axi_queueweight

Data Fields
bool	queueaEnable
	Enable queue a. More...

semc_queuea_weight_t	queueaWeight
	Weight settings for queue a. More...

bool	queuebEnable
	Enable queue b. More...

semc_queueb_weight_t	queuebWeight
	Weight settings for queue b. More...

Field Documentation

bool _semc_axi_queueweight::queueaEnable

semc_queuea_weight_t _semc_axi_queueweight::queueaWeight

bool _semc_axi_queueweight::queuebEnable

semc_queueb_weight_t _semc_axi_queueweight::queuebWeight

struct _semc_config_t

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it's similar to the busTimeoutCycles.

Data Fields
semc_dqs_mode_t	dqsMode
	Dummy read strobe mode: use enum in "semc_dqs_mode_t". More...

uint8_t	cmdTimeoutCycles
	Command execution timeout cycles. More...

uint8_t	busTimeoutCycles
	Bus timeout cycles. More...

semc_axi_queueweight_t	queueWeight
	AXI queue weight. More...

Field Documentation

semc_dqs_mode_t _semc_config_t::dqsMode

uint8_t _semc_config_t::cmdTimeoutCycles

uint8_t _semc_config_t::busTimeoutCycles

semc_axi_queueweight_t _semc_config_t::queueWeight

Macro Definition Documentation

#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))

Typedef Documentation

typedef enum _semc_mem_type semc_mem_type_t

typedef enum _semc_waitready_polarity semc_waitready_polarity_t

typedef enum _semc_sdram_cs semc_sdram_cs_t

typedef enum _semc_sram_cs semc_sram_cs_t

typedef enum _semc_nand_access_type semc_nand_access_type_t

typedef enum _semc_interrupt_enable semc_interrupt_enable_t

typedef enum _semc_ipcmd_datasize semc_ipcmd_datasize_t

typedef enum _semc_refresh_time semc_refresh_time_t

typedef enum _semc_sdram_column_bit_num semc_sdram_column_bit_num_t

typedef enum _semc_sdram_burst_len sem_sdram_burst_len_t

typedef enum _semc_nand_column_bit_num semc_nand_column_bit_num_t

typedef enum _semc_nand_burst_len sem_nand_burst_len_t

typedef enum _semc_norsram_column_bit_num semc_norsram_column_bit_num_t

typedef enum _semc_norsram_burst_len sem_norsram_burst_len_t

typedef enum _semc_dbi_column_bit_num semc_dbi_column_bit_num_t

typedef enum _semc_dbi_burst_len sem_dbi_burst_len_t

typedef enum _semc_iomux_pin semc_iomux_pin

typedef enum _semc_iomux_nora27_pin semc_iomux_nora27_pin

typedef enum _semc_port_size smec_port_size_t

typedef enum _semc_addr_mode semc_addr_mode_t

typedef enum _semc_dqs_mode semc_dqs_mode_t

typedef enum _semc_adv_polarity semc_adv_polarity_t

typedef enum _semc_sync_mode semc_sync_mode_t

typedef enum _semc_adv_level_control semc_adv_level_control_t

typedef enum _semc_rdy_polarity semc_rdy_polarity_t

typedef enum _semc_ipcmd_nand_addrmode semc_ipcmd_nand_addrmode_t

typedef enum _semc_ipcmd_nand_cmdmode semc_ipcmd_nand_cmdmode_t

typedef enum _semc_nand_address_option semc_nand_address_option_t

typedef enum _semc_ipcmd_nor_dbi semc_ipcmd_nor_dbi_t

typedef enum _semc_ipcmd_sram semc_ipcmd_sram_t

typedef enum _semc_ipcmd_sdram semc_ipcmd_sdram_t

typedef struct _semc_sdram_config semc_sdram_config_t

The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

typedef struct _semc_nand_timing_config semc_nand_timing_config_t

typedef struct _semc_nand_config semc_nand_config_t

typedef struct _semc_nor_config semc_nor_config_t

typedef struct _semc_sram_config semc_sram_config_t

typedef struct _semc_dbi_config semc_dbi_config_t

typedef struct _semc_queuea_weight_struct semc_queuea_weight_struct_t

typedef union _semc_queuea_weight semc_queuea_weight_t

typedef struct _semc_queueb_weight_struct semc_queueb_weight_struct_t

typedef union _semc_queueb_weight semc_queueb_weight_t

typedef struct _semc_axi_queueweight semc_axi_queueweight_t

typedef struct _semc_config_t semc_config_t

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it's similar to the busTimeoutCycles.

Enumeration Type Documentation

anonymous enum

Enumerator
kStatus_SEMC_InvalidDeviceType	Invalid device type.
kStatus_SEMC_IpCommandExecutionError	IP command execution error.
kStatus_SEMC_AxiCommandExecutionError	AXI command execution error.
kStatus_SEMC_InvalidMemorySize	Invalid memory sie.
kStatus_SEMC_InvalidIpcmdDataSize	Invalid IP command data size.
kStatus_SEMC_InvalidAddressPortWidth	Invalid address port width.
kStatus_SEMC_InvalidDataPortWidth	Invalid data port width.
kStatus_SEMC_InvalidSwPinmuxSelection	Invalid SW pinmux selection.
kStatus_SEMC_InvalidBurstLength	Invalid burst length.
kStatus_SEMC_InvalidColumnAddressBitWidth	Invalid column address bit width.
kStatus_SEMC_InvalidBaseAddress	Invalid base address.
kStatus_SEMC_InvalidTimerSetting	Invalid timer setting.

enum _semc_mem_type

Enumerator
kSEMC_MemType_SDRAM	SDRAM.
kSEMC_MemType_SRAM	SRAM.
kSEMC_MemType_NOR	NOR.
kSEMC_MemType_NAND	NAND.
kSEMC_MemType_8080

enum _semc_waitready_polarity

Enumerator
kSEMC_LowActive	Low active.
kSEMC_HighActive	High active.

enum _semc_sdram_cs

Enumerator
kSEMC_SDRAM_CS0	SEMC SDRAM CS0.
kSEMC_SDRAM_CS1	SEMC SDRAM CS1.
kSEMC_SDRAM_CS2	SEMC SDRAM CS2.
kSEMC_SDRAM_CS3	SEMC SDRAM CS3.

enum _semc_sram_cs

Enumerator
kSEMC_SRAM_CS0	SEMC SRAM CS0.
kSEMC_SRAM_CS1	SEMC SRAM CS1.
kSEMC_SRAM_CS2	SEMC SRAM CS2.
kSEMC_SRAM_CS3	SEMC SRAM CS3.

enum _semc_nand_access_type

Enumerator
kSEMC_NAND_ACCESS_BY_AXI	Access to NAND flash by AXI bus.
kSEMC_NAND_ACCESS_BY_IPCMD	Access to NAND flash by IP bus.

enum _semc_interrupt_enable

Enumerator
kSEMC_IPCmdDoneInterrupt	Ip command done interrupt.
kSEMC_IPCmdErrInterrupt	Ip command error interrupt.
kSEMC_AXICmdErrInterrupt	AXI command error interrupt.
kSEMC_AXIBusErrInterrupt	AXI bus error interrupt.

enum _semc_ipcmd_datasize

Enumerator
kSEMC_IPcmdDataSize_1bytes	The IP command data size 1 byte.
kSEMC_IPcmdDataSize_2bytes	The IP command data size 2 byte.
kSEMC_IPcmdDataSize_3bytes	The IP command data size 3 byte.
kSEMC_IPcmdDataSize_4bytes	The IP command data size 4 byte.

enum _semc_refresh_time

Enumerator
kSEMC_RefreshThreeClocks	The refresh timing with three bus clocks.
kSEMC_RefreshSixClocks	The refresh timing with six bus clocks.
kSEMC_RefreshNineClocks	The refresh timing with nine bus clocks.

enum _semc_caslatency

Enumerator
kSEMC_LatencyOne	Latency 1.
kSEMC_LatencyTwo	Latency 2.
kSEMC_LatencyThree	Latency 3.

enum _semc_sdram_column_bit_num

Enumerator
kSEMC_SdramColunm_12bit	12 bit.
kSEMC_SdramColunm_11bit	11 bit.
kSEMC_SdramColunm_10bit	10 bit.
kSEMC_SdramColunm_9bit	9 bit.
kSEMC_SdramColunm_8bit	8 bit.

enum _semc_sdram_burst_len

Enumerator
kSEMC_Sdram_BurstLen1	According to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. Burst length 1
kSEMC_Sdram_BurstLen2	Burst length 2.
kSEMC_Sdram_BurstLen4	Burst length 4.
kSEMC_Sdram_BurstLen8	Burst length 8.

enum _semc_nand_column_bit_num

Enumerator
kSEMC_NandColum_16bit	16 bit.
kSEMC_NandColum_15bit	15 bit.
kSEMC_NandColum_14bit	14 bit.
kSEMC_NandColum_13bit	13 bit.
kSEMC_NandColum_12bit	12 bit.
kSEMC_NandColum_11bit	11 bit.
kSEMC_NandColum_10bit	10 bit.
kSEMC_NandColum_9bit	9 bit.

enum _semc_nand_burst_len

Enumerator
kSEMC_Nand_BurstLen1	Burst length 1.
kSEMC_Nand_BurstLen2	Burst length 2.
kSEMC_Nand_BurstLen4	Burst length 4.
kSEMC_Nand_BurstLen8	Burst length 8.
kSEMC_Nand_BurstLen16	Burst length 16.
kSEMC_Nand_BurstLen32	Burst length 32.
kSEMC_Nand_BurstLen64	Burst length 64.

enum _semc_norsram_column_bit_num

Enumerator
kSEMC_NorColum_12bit	12 bit.
kSEMC_NorColum_11bit	11 bit.
kSEMC_NorColum_10bit	10 bit.
kSEMC_NorColum_9bit	9 bit.
kSEMC_NorColum_8bit	8 bit.
kSEMC_NorColum_7bit	7 bit.
kSEMC_NorColum_6bit	6 bit.
kSEMC_NorColum_5bit	5 bit.
kSEMC_NorColum_4bit	4 bit.
kSEMC_NorColum_3bit	3 bit.
kSEMC_NorColum_2bit	2 bit.

enum _semc_norsram_burst_len

Enumerator
kSEMC_Nor_BurstLen1	Burst length 1.
kSEMC_Nor_BurstLen2	Burst length 2.
kSEMC_Nor_BurstLen4	Burst length 4.
kSEMC_Nor_BurstLen8	Burst length 8.
kSEMC_Nor_BurstLen16	Burst length 16.
kSEMC_Nor_BurstLen32	Burst length 32.
kSEMC_Nor_BurstLen64	Burst length 64.

enum _semc_dbi_column_bit_num

Enumerator
kSEMC_Dbi_Colum_12bit	12 bit.
kSEMC_Dbi_Colum_11bit	11 bit.
kSEMC_Dbi_Colum_10bit	10 bit.
kSEMC_Dbi_Colum_9bit	9 bit.
kSEMC_Dbi_Colum_8bit	8 bit.
kSEMC_Dbi_Colum_7bit	7 bit.
kSEMC_Dbi_Colum_6bit	6 bit.
kSEMC_Dbi_Colum_5bit	5 bit.
kSEMC_Dbi_Colum_4bit	4 bit.
kSEMC_Dbi_Colum_3bit	3 bit.
kSEMC_Dbi_Colum_2bit	2 bit.

enum _semc_dbi_burst_len

Enumerator
kSEMC_Dbi_BurstLen1	Burst length 1.
kSEMC_Dbi_BurstLen2	Burst length 2.
kSEMC_Dbi_Dbi_BurstLen4	Burst length 4.
kSEMC_Dbi_BurstLen8	Burst length 8.
kSEMC_Dbi_BurstLen16	Burst length 16.
kSEMC_Dbi_BurstLen32	Burst length 32.
kSEMC_Dbi_BurstLen64	Burst length 64.

enum _semc_iomux_pin

Enumerator
kSEMC_MUXA8	MUX A8 pin.
kSEMC_MUXCSX0	MUX CSX0 pin.
kSEMC_MUXCSX1	MUX CSX1 Pin.
kSEMC_MUXCSX2	MUX CSX2 Pin.
kSEMC_MUXCSX3	MUX CSX3 Pin.
kSEMC_MUXRDY	MUX RDY pin.

enum _semc_iomux_nora27_pin

Enumerator
kSEMC_MORA27_NONE	No NOR/SRAM A27 pin.
kSEMC_NORA27_MUXCSX3	MUX CSX3 Pin.
kSEMC_NORA27_MUXRDY	MUX RDY pin.

enum _semc_port_size

Enumerator
kSEMC_PortSize8Bit	8-Bit port size.
kSEMC_PortSize16Bit	16-Bit port size.
kSEMC_PortSize32Bit	32-Bit port size.

enum _semc_addr_mode

Enumerator
kSEMC_AddrDataMux	SEMC address/data mux mode.
kSEMC_AdvAddrdataMux	Advanced address/data mux mode.
kSEMC_AddrDataNonMux	Address/data non-mux mode.

enum _semc_dqs_mode

Enumerator
kSEMC_Loopbackinternal	Dummy read strobe loopbacked internally.
kSEMC_Loopbackdqspad	Dummy read strobe loopbacked from DQS pad.

enum _semc_adv_polarity

Enumerator
kSEMC_AdvActiveLow	Adv active low.
kSEMC_AdvActiveHigh	Adv active high.

enum _semc_sync_mode

Enumerator
kSEMC_AsyncMode	Async mode.
kSEMC_SyncMode	Sync mode.

enum _semc_adv_level_control

Enumerator
kSEMC_AdvHigh	Adv is high during address hold state.
kSEMC_AdvLow	Adv is low during address hold state.

enum _semc_rdy_polarity

Enumerator
kSEMC_RdyActiveLow	Adv active low.
kSEMC_RdyActivehigh	Adv active low.

enum _semc_ipcmd_nand_addrmode

Enumerator
kSEMC_NANDAM_ColumnRow	Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2).
kSEMC_NANDAM_ColumnCA0	Address mode: column address only(1 Byte-CA0).
kSEMC_NANDAM_ColumnCA0CA1	Address mode: column address only(2 Byte-CA0/CA1).
kSEMC_NANDAM_RawRA0	Address mode: row address only(1 Byte-RA0).
kSEMC_NANDAM_RawRA0RA1	Address mode: row address only(2 Byte-RA0/RA1).
kSEMC_NANDAM_RawRA0RA1RA2	Address mode: row address only(3 Byte-RA0).

enum _semc_ipcmd_nand_cmdmode

Enumerator
kSEMC_NANDCM_Command	command.
kSEMC_NANDCM_CommandHold	Command hold.
kSEMC_NANDCM_CommandAddress	Command address.
kSEMC_NANDCM_CommandAddressHold	Command address hold.
kSEMC_NANDCM_CommandAddressRead	Command address read.
kSEMC_NANDCM_CommandAddressWrite	Command address write.
kSEMC_NANDCM_CommandRead	Command read.
kSEMC_NANDCM_CommandWrite	Command write.
kSEMC_NANDCM_Read	Read.
kSEMC_NANDCM_Write	Write.

enum _semc_nand_address_option

Enumerator
kSEMC_NandAddrOption_5byte_CA2RA3	CA0+CA1+RA0+RA1+RA2.
kSEMC_NandAddrOption_4byte_CA2RA2	CA0+CA1+RA0+RA1.
kSEMC_NandAddrOption_3byte_CA2RA1	CA0+CA1+RA0.
kSEMC_NandAddrOption_4byte_CA1RA3	CA0+RA0+RA1+RA2.
kSEMC_NandAddrOption_3byte_CA1RA2	CA0+RA0+RA1.
kSEMC_NandAddrOption_2byte_CA1RA1	CA0+RA0.

enum _semc_ipcmd_nor_dbi

Enumerator
kSEMC_NORDBICM_Read	NOR read.
kSEMC_NORDBICM_Write	NOR write.

enum _semc_ipcmd_sram

Enumerator
kSEMC_SRAMCM_ArrayRead	SRAM memory array read.
kSEMC_SRAMCM_ArrayWrite	SRAM memory array write.
kSEMC_SRAMCM_RegRead	SRAM memory register read.
kSEMC_SRAMCM_RegWrite	SRAM memory register write.

enum _semc_ipcmd_sdram

Enumerator
kSEMC_SDRAMCM_Read	SDRAM memory read.
kSEMC_SDRAMCM_Write	SDRAM memory write.
kSEMC_SDRAMCM_Modeset	SDRAM MODE SET.
kSEMC_SDRAMCM_Active	SDRAM active.
kSEMC_SDRAMCM_AutoRefresh	SDRAM auto-refresh.
kSEMC_SDRAMCM_SelfRefresh	SDRAM self-refresh.
kSEMC_SDRAMCM_Precharge	SDRAM precharge.
kSEMC_SDRAMCM_Prechargeall	SDRAM precharge all.

Function Documentation

void SEMC_GetDefaultConfig ( semc_config_t * config )

The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example:

semc_config_t config;

SEMC_GetDefaultConfig(&config);

Parameters

config The SEMC configuration structure pointer.

void SEMC_Init	(	SEMC_Type *	base,
		semc_config_t *	configure
	)

This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.

Parameters

base	SEMC peripheral base address.
configure	The SEMC configuration structure pointer.

void SEMC_Deinit ( SEMC_Type * base )

This function gates the SEMC clock. As a result, the SEMC module doesn't work after calling this function, for some IDE, calling this API may cause the next downloading operation failed. so, please call this API cautiously. Additional, users can using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control operation in drivers.

Parameters

base	SEMC peripheral base address.

status_t SEMC_ConfigureSDRAM	(	SEMC_Type *	base,
		semc_sdram_cs_t	cs,
		semc_sdram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Parameters

base	SEMC peripheral base address.
cs	The chip selection.
config	The sdram configuration.
clkSrc_Hz	The SEMC clock frequency.

status_t SEMC_ConfigureNAND	(	SEMC_Type *	base,
		semc_nand_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Parameters

base	SEMC peripheral base address.
config	The nand configuration.
clkSrc_Hz	The SEMC clock frequency.

status_t SEMC_ConfigureNOR	(	SEMC_Type *	base,
		semc_nor_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Parameters

base	SEMC peripheral base address.
config	The nor configuration.
clkSrc_Hz	The SEMC clock frequency.

status_t SEMC_ConfigureSRAMWithChipSelection	(	SEMC_Type *	base,
		semc_sram_cs_t	cs,
		semc_sram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Parameters

base	SEMC peripheral base address.
cs	The chip selection.
config	The sram configuration.
clkSrc_Hz	The SEMC clock frequency.

status_t SEMC_ConfigureSRAM	(	SEMC_Type *	base,
		semc_sram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Deprecated:: Do not use this function. It has been superceded by SEMC_ConfigureSRAMWithChipSelection.

Parameters

base	SEMC peripheral base address.
config	The sram configuration.
clkSrc_Hz	The SEMC clock frequency.

status_t SEMC_ConfigureDBI	(	SEMC_Type *	base,
		semc_dbi_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Parameters

base	SEMC peripheral base address.
config	The dbi configuration.
clkSrc_Hz	The SEMC clock frequency.

static void SEMC_EnableInterrupts	(	SEMC_Type *	base,
		uint32_t	mask
	)

inlinestatic

This function enables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to enable the IP command done and error interrupt, do the following.

* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);

*

Parameters

base	SEMC peripheral base address.
mask	SEMC interrupts to enable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.

static void SEMC_DisableInterrupts	(	SEMC_Type *	base,
		uint32_t	mask
	)

inlinestatic

This function disables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to disable the IP command done and error interrupt, do the following.

* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);

*

Parameters

base	SEMC peripheral base address.
mask	SEMC interrupts to disable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.

static bool SEMC_GetStatusFlag ( SEMC_Type * base )

inlinestatic

This function gets the SEMC interrupts event status. User can use the a logical OR of enumeration member as a mask. See semc_interrupt_enable_t.

Parameters

base	SEMC peripheral base address.

Returns: status flag, use status flag in semc_interrupt_enable_t to get the related status.

static void SEMC_ClearStatusFlags	(	SEMC_Type *	base,
		uint32_t	mask
	)

inlinestatic

The following status register flags can be cleared SEMC interrupt status.

Parameters

base	SEMC base pointer
mask	The status flag mask, a logical OR of enumeration member semc_interrupt_enable_t.

static bool SEMC_IsInIdle ( SEMC_Type * base )

inlinestatic

Parameters

base	SEMC peripheral base address.

Returns: True SEMC is in idle, false is not in idle.

status_t SEMC_SendIPCommand	(	SEMC_Type *	base,
		semc_mem_type_t	memType,
		uint32_t	address,
		uint32_t	command,
		uint32_t	write,
		uint32_t *	read
	)

Parameters

base	SEMC peripheral base address.
memType	SEMC memory type. refer to "semc_mem_type_t"
address	SEMC device address.
command	SEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". For SRAM device, take refer to "semc_ipcmd_sram_t". For SDRAM device, take refer to "semc_ipcmd_sdram_t".
write	Data for write access.
read	Data pointer for read data out.

static uint16_t SEMC_BuildNandIPCommand	(	uint8_t	userCommand,
		semc_ipcmd_nand_addrmode_t	addrMode,
		semc_ipcmd_nand_cmdmode_t	cmdMode
	)

inlinestatic

This function build SEMC NAND IP command. The command is build of user command code, SEMC address mode and SEMC command mode.

Parameters

userCommand	NAND device normal command.
addrMode	NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
cmdMode	NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".

static bool SEMC_IsNandReady ( SEMC_Type * base )

inlinestatic

Parameters

base	SEMC peripheral base address.

Returns: True NAND is ready, false NAND is not ready.

status_t SEMC_IPCommandNandWrite	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

Parameters

base	SEMC peripheral base address.
address	SEMC NAND device address.
data	Data for write access.
size_bytes	Data length.

status_t SEMC_IPCommandNandRead	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

Parameters

base	SEMC peripheral base address.
address	SEMC NAND device address.
data	Data pointer for data read out.
size_bytes	Data length.

status_t SEMC_IPCommandNorWrite	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

Parameters

base	SEMC peripheral base address.
address	SEMC NOR device address.
data	Data for write access.
size_bytes	Data length.

status_t SEMC_IPCommandNorRead	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

Parameters

base	SEMC peripheral base address.
address	SEMC NOR device address.
data	Data pointer for data read out.
size_bytes	Data length.

Overview

SEMC: Smart External DRAM Controller Driver

SEMC Initialization Operation

SEMC Interrupt Operation

SEMC Memory access Operation

Typical use case

Data Structures

Typedefs

Enumerations

Driver version

SEMC Initialization and De-initialization

SEMC Configuration Operation For Each Memory Type

SEMC Interrupt Operation

SEMC Memory Access Operation

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation