Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

The MCUXpresso SDK provides a peripheral clock driver for the SYSCON module of MCUXpresso SDK devices.

Function description

Clock driver provides these functions:

Functions to initialize the Core clock to given frequency
Functions to configure the clock selection muxes.
Functions to setup peripheral clock dividers
Functions to set the flash wait states for the input freuqency
Functions to get the frequency of the selected clock
Functions to set PLL frequency

SYSCON Clock frequency functions

SYSCON clock module provides clocks, such as MCLKCLK, ADCCLK, DMICCLK, MCGFLLCLK, FXCOMCLK, WDTOSC, RTCOSC, USBCLK, and SYSPLL. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. CLOCK_SetupFROClocking() initializes the FRO to 12 MHz, 48 MHz, or 96 MHz frequency. CLOCK_SetupPLLData(), CLOCK_SetupSystemPLLPrec(), and CLOCK_SetPLLFreq() functions are used to setup the PLL. The SYSCON clock driver provides functions to get the frequency of these clocks, such as CLOCK_GetFreq(), CLOCK_GetFro12MFreq(), CLOCK_GetExtClkFreq(), CLOCK_GetWdtOscFreq(), CLOCK_GetFroHfFreq(), CLOCK_GetPllOutFreq(), CLOCK_GetOsc32KFreq(), CLOCK_GetCoreSysClkFreq(), CLOCK_GetI2SMClkFreq(), CLOCK_GetFlexCommClkFreq, and CLOCK_GetAsyncApbClkFreq.

SYSCON clock Selection Muxes

The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC, and PLL.

SYSCON clock dividers

The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, I2S, SYSTICK, AHB, ADC, and also CLKOUT and TRACE functions.

SYSCON flash wait states

The SYSCON clock driver provides the function CLOCK_SetFLASHAccessCyclesForFreq() that configures FLASHCFG register with a selected FLASHTIM value.

Typical use case

POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on so that we can switch to its 12MHz mode temporarily

Files
file	fsl_clock.h

Data Structures
struct	_clock_sys_pll
	PLL configuration structure. More...

Macros
#define	ADC_CLOCKS
	Clock ip name array for ADC. More...

#define	ACMP_CLOCKS
	Clock ip name array for ACMP. More...

#define	SWM_CLOCKS
	Clock ip name array for SWM. More...

#define	ROM_CLOCKS
	Clock ip name array for ROM. More...

#define	SRAM_CLOCKS
	Clock ip name array for SRAM. More...

#define	IOCON_CLOCKS
	Clock ip name array for IOCON. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	GPIO_INT_CLOCKS
	Clock ip name array for GPIO_INT. More...

#define	DMA_CLOCKS
	Clock ip name array for DMA. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	WWDT_CLOCKS
	Clock ip name array for WWDT. More...

#define	SCT_CLOCKS
	Clock ip name array for SCT0. More...

#define	I2C_CLOCKS
	Clock ip name array for I2C. More...

#define	USART_CLOCKS
	Clock ip name array for I2C. More...

#define	SPI_CLOCKS
	Clock ip name array for SPI. More...

#define	MTB_CLOCKS
	Clock ip name array for MTB. More...

#define	MRT_CLOCKS
	Clock ip name array for MRT. More...

#define	WKT_CLOCKS
	Clock ip name array for WKT. More...

#define	CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) \| ((bit)&0xFFU))
	Internal used Clock definition only. More...

Typedefs
typedef enum _clock_ip_name	clock_ip_name_t
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...

typedef enum _clock_select	clock_select_t
	Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value. More...

typedef enum _clock_divider	clock_divider_t
	Clock divider.

typedef enum _clock_wdt_analog_freq	clock_wdt_analog_freq_t
	watch dog analog output frequency

typedef enum _clock_sys_pll_src	clock_sys_pll_src
	PLL clock definition. More...

typedef enum _clock_main_clk_src	clock_main_clk_src_t
	Main clock source definition.

typedef struct _clock_sys_pll	clock_sys_pll_t
	PLL configuration structure.

Enumerations
enum	_clock_ip_name { kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U), kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U), kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U), kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U), kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U), kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U), kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U), kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U), kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U), kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U), kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U), kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U), kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U), kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U), kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U), kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U), kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U), kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U), kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U), kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U), kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 21U), kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 22U), kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 23U), kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 24U), kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 26U), kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 29U) }
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

enum	_clock_name { kCLOCK_CoreSysClk, kCLOCK_MainClk, kCLOCK_SysOsc, kCLOCK_Irc, kCLOCK_ExtClk, kCLOCK_PllOut, kCLOCK_Pllin, kCLOCK_WdtOsc }
	Clock name used to get clock frequency. More...

enum	_clock_select { kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U), kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U), kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U), kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U), kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U), kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U), kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U), kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U), kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U), kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U), kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U) }
	Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value. More...

enum	_clock_divider { kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV), kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV), kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6), kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5), kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4), kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3), kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2), kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1), kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0) }
	Clock divider. More...

enum	_clock_wdt_analog_freq { kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U), kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U), kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u), kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U), kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U), kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U), kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U), kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U), kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U), kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U), kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U), kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U), kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U), kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U), kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U), kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U) }
	watch dog analog output frequency More...

enum	_clock_sys_pll_src { kCLOCK_SysPllSrcIrc = 0U, kCLOCK_SysPllSrcSysosc = 1U, kCLOCK_SysPllSrcExtClk = 3U }
	PLL clock definition. More...

enum	_clock_main_clk_src { kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U) }
	Main clock source definition. More...

Variables
volatile uint32_t	g_Wdt_Osc_Freq
	watchdog oscilltor clock frequency. More...

volatile uint32_t	g_Ext_Clk_Freq
	external clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))
	CLOCK driver version 2.4.4. More...

Clock gate, mux, and divider.
static void	CLOCK_EnableClock (clock_ip_name_t clk)

static void	CLOCK_DisableClock (clock_ip_name_t clk)

static void	CLOCK_Select (clock_select_t sel)

static void	CLOCK_SetClkDivider (clock_divider_t name, uint32_t value)

static uint32_t	CLOCK_GetClkDivider (clock_divider_t name)

static void	CLOCK_SetCoreSysClkDiv (uint32_t value)

void	CLOCK_SetMainClkSrc (clock_main_clk_src_t src)
	Set main clock reference source. More...

static void	CLOCK_SetFRGClkMul (uint32_t mul)

Get frequency
uint32_t	CLOCK_GetMainClkFreq (void)
	Return Frequency of Main Clock. More...

static uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Return Frequency of core. More...

uint32_t	CLOCK_GetClockOutClkFreq (void)
	Return Frequency of ClockOut. More...

uint32_t	CLOCK_GetIrcFreq (void)
	Return Frequency of IRC. More...

uint32_t	CLOCK_GetSysOscFreq (void)
	Return Frequency of SYSOSC. More...

uint32_t	CLOCK_GetUartClkFreq (void)
	Get UART0 frequency. More...

uint32_t	CLOCK_GetUart0ClkFreq (void)
	Get UART0 frequency. More...

uint32_t	CLOCK_GetUart1ClkFreq (void)
	Get UART1 frequency. More...

uint32_t	CLOCK_GetUart2ClkFreq (void)
	Get UART2 frequency. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Return Frequency of selected clock. More...

uint32_t	CLOCK_GetSystemPLLInClockRate (void)
	Return System PLL input clock rate. More...

static uint32_t	CLOCK_GetSystemPLLFreq (void)
	Return Frequency of System PLL. More...

static uint32_t	CLOCK_GetWdtOscFreq (void)
	Get watch dog OSC frequency. More...

static uint32_t	CLOCK_GetExtClkFreq (void)
	Get external clock frequency. More...

PLL operations
void	CLOCK_InitSystemPll (const clock_sys_pll_t *config)
	System PLL initialize. More...

static void	CLOCK_DenitSystemPll (void)
	System PLL Deinitialize. More...

External/internal oscillator clock operations
void	CLOCK_InitExtClkin (uint32_t clkInFreq)
	Init external CLK IN, select the CLKIN as the external clock source. More...

void	CLOCK_InitSysOsc (uint32_t oscFreq)
	Init SYS OSC. More...

void	CLOCK_InitXtalin (uint32_t xtalInFreq)
	XTALIN init function system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN. More...

static void	CLOCK_DeinitSysOsc (void)
	Deinit SYS OSC.

void	CLOCK_InitWdtOsc (clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv)
	Init watch dog OSC Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the listed frequency value. More...

static void	CLOCK_DeinitWdtOsc (void)
	Deinit watch dog OSC.

bool	CLOCK_SetUARTFRGClkFreq (uint32_t freq)
	Set UARTFRG. More...

void	CLOCK_UpdateClkOUTsrc (void)
	updates the clock source of the CLKOUT

static void	CLOCK_SetUARTFRGMULT (uint32_t mul)
	Set UARTFRGMULT. More...

Data Structure Documentation

struct _clock_sys_pll

Data Fields
uint32_t	targetFreq
	System pll fclk output frequency, the output frequency should be lower than 100MHZ.

clock_sys_pll_src	src
	System pll clock source.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))

#define ADC_CLOCKS

Value:

{               \
        kCLOCK_Adc, \
    }

#define ACMP_CLOCKS

Value:

{                \
        kCLOCK_Acmp, \
    }

#define SWM_CLOCKS

Value:

{               \
        kCLOCK_Swm, \
    }

#define ROM_CLOCKS

Value:

{               \
        kCLOCK_Rom, \
    }

#define SRAM_CLOCKS

Value:

{                  \
        kCLOCK_Ram0_1, \
    }

#define IOCON_CLOCKS

Value:

{                 \
        kCLOCK_Iocon, \
    }

#define GPIO_CLOCKS

Value:

{                 \
        kCLOCK_Gpio0, \
    }

#define GPIO_INT_CLOCKS

Value:

{                   \
        kCLOCK_GpioInt, \
    }

#define DMA_CLOCKS

Value:

{               \
        kCLOCK_Dma, \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc, \
    }

#define WWDT_CLOCKS

Value:

{                \
        kCLOCK_Wwdt, \
    }

#define SCT_CLOCKS

Value:

{               \
        kCLOCK_Sct, \
    }

#define I2C_CLOCKS

Value:

{                                                       \
        kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, \
    }

#define USART_CLOCKS

Value:

{                                             \
        kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
    }

#define SPI_CLOCKS

Value:

{                             \
        kCLOCK_Spi0, kCLOCK_Spi1, \
    }

#define MTB_CLOCKS

Value:

{               \
        kCLOCK_Mtb, \
    }

#define MRT_CLOCKS

Value:

{               \
        kCLOCK_Mrt, \
    }

#define WKT_CLOCKS

Value:

{               \
        kCLOCK_Wkt, \
    }

#define CLK_GATE_DEFINE	(	reg,
		bit
	)	((((reg)&0xFFU) << 8U) \| ((bit)&0xFFU))

Typedef Documentation

typedef enum _clock_ip_name clock_ip_name_t

typedef enum _clock_name clock_name_t

typedef enum _clock_select clock_select_t

typedef enum _clock_sys_pll_src clock_sys_pll_src

Enumeration Type Documentation

enum _clock_ip_name

Enumerator
kCLOCK_Sys	Clock gate name: Sys.
kCLOCK_Rom	Clock gate name: Rom.
kCLOCK_Ram0_1	Clock gate name: Ram0_1.
kCLOCK_Flashreg	Clock gate name: Flashreg.
kCLOCK_Flash	Clock gate name: Flash.
kCLOCK_I2c0	Clock gate name: I2c0.
kCLOCK_Gpio0	Clock gate name: Gpio0.
kCLOCK_Swm	Clock gate name: Swm.
kCLOCK_Sct	Clock gate name: Sct.
kCLOCK_Wkt	Clock gate name: Wkt.
kCLOCK_Mrt	Clock gate name: Mrt.
kCLOCK_Spi0	Clock gate name: Spi0.
kCLOCK_Spi1	Clock gate name: Spi1.
kCLOCK_Crc	Clock gate name: Crc.
kCLOCK_Uart0	Clock gate name: Uart0.
kCLOCK_Uart1	Clock gate name: Uart1.
kCLOCK_Uart2	Clock gate name: Uart2.
kCLOCK_Wwdt	Clock gate name: Wwdt.
kCLOCK_Iocon	Clock gate name: Iocon.
kCLOCK_Acmp	Clock gate name: Acmp.
kCLOCK_I2c1	Clock gate name: I2c1.
kCLOCK_I2c2	Clock gate name: I2c2.
kCLOCK_I2c3	Clock gate name: I2c3.
kCLOCK_Adc	Clock gate name: Adc.
kCLOCK_Mtb	Clock gate name: Mtb.
kCLOCK_Dma	Clock gate name: Dma.

enum _clock_name

Enumerator
kCLOCK_CoreSysClk	Cpu/AHB/AHB matrix/Memories,etc.
kCLOCK_MainClk	Main clock.
kCLOCK_SysOsc	Crystal Oscillator.
kCLOCK_Irc	IRC12M.
kCLOCK_ExtClk	External Clock.
kCLOCK_PllOut	PLL Output.
kCLOCK_Pllin	PLL Input.
kCLOCK_WdtOsc	Watchdog Oscillator.

enum _clock_select

Enumerator
kSYSPLL_From_Irc	Mux SYSPLL from Irc.
kSYSPLL_From_SysOsc	Mux SYSPLL from SysOsc.
kSYSPLL_From_ExtClk	Mux SYSPLL from ExtClk.
kMAINCLK_From_Irc	Mux MAINCLK from Irc.
kMAINCLK_From_SysPllIn	Mux MAINCLK from SysPllIn.
kMAINCLK_From_WdtOsc	Mux MAINCLK from WdtOsc.
kMAINCLK_From_SysPll	Mux MAINCLK from SysPll.
kCLKOUT_From_Irc	Mux CLKOUT from Irc.
kCLKOUT_From_SysOsc	Mux CLKOUT from SysOsc.
kCLKOUT_From_WdtOsc	Mux CLKOUT from WdtOsc.
kCLKOUT_From_MainClk	Mux clock out from Main clock.

enum _clock_divider

Enumerator
kCLOCK_DivUsartClk	Usart Clock Divider.
kCLOCK_DivClkOut	Clk Out Divider.
kCLOCK_DivUartFrg	Uart Frg Divider.
kCLOCK_IOCONCLKDiv6	IOCON Clock Div6 Divider.
kCLOCK_IOCONCLKDiv5	IOCON Clock Div5 Divider.
kCLOCK_IOCONCLKDiv4	IOCON Clock Div4 Divider.
kCLOCK_IOCONCLKDiv3	IOCON Clock Div3 Divider.
kCLOCK_IOCONCLKDiv2	IOCON Clock Div2 Divider.
kCLOCK_IOCONCLKDiv1	IOCON Clock Div1 Divider.
kCLOCK_IOCONCLKDiv0	IOCON Clock Div0 Divider.

enum _clock_wdt_analog_freq

Enumerator
kCLOCK_WdtAnaFreq0HZ	Watch dog analog output frequency is 0HZ.
kCLOCK_WdtAnaFreq600KHZ	Watch dog analog output frequency is 600KHZ.
kCLOCK_WdtAnaFreq1050KHZ	Watch dog analog output frequency is 1050KHZ.
kCLOCK_WdtAnaFreq1400KHZ	Watch dog analog output frequency is 1400KHZ.
kCLOCK_WdtAnaFreq1750KHZ	Watch dog analog output frequency is 1750KHZ.
kCLOCK_WdtAnaFreq2100KHZ	Watch dog analog output frequency is 2100KHZ.
kCLOCK_WdtAnaFreq2400KHZ	Watch dog analog output frequency is 2400KHZ.
kCLOCK_WdtAnaFreq2700KHZ	Watch dog analog output frequency is 2700KHZ.
kCLOCK_WdtAnaFreq3000KHZ	Watch dog analog output frequency is 3000KHZ.
kCLOCK_WdtAnaFreq3250KHZ	Watch dog analog output frequency is 3250KHZ.
kCLOCK_WdtAnaFreq3500KHZ	Watch dog analog output frequency is 3500KHZ.
kCLOCK_WdtAnaFreq3750KHZ	Watch dog analog output frequency is 3750KHZ.
kCLOCK_WdtAnaFreq4000KHZ	Watch dog analog output frequency is 4000KHZ.
kCLOCK_WdtAnaFreq4200KHZ	Watch dog analog output frequency is 4200KHZ.
kCLOCK_WdtAnaFreq4400KHZ	Watch dog analog output frequency is 4400KHZ.
kCLOCK_WdtAnaFreq4600KHZ	Watch dog analog output frequency is 4600KHZ.

enum _clock_sys_pll_src

Enumerator
kCLOCK_SysPllSrcIrc	system pll source from FRO
kCLOCK_SysPllSrcSysosc	system pll source from system osc
kCLOCK_SysPllSrcExtClk	system pll source from ext clkin

enum _clock_main_clk_src

Enumerator
kCLOCK_MainClkSrcIrc	main clock source from FRO
kCLOCK_MainClkSrcSysPllin	main clock source from pll input
kCLOCK_MainClkSrcWdtOsc	main clock source from watchdog oscillator
kCLOCK_MainClkSrcSysPll	main clock source from system pll

Function Documentation

void CLOCK_SetMainClkSrc ( clock_main_clk_src_t src )

Parameters

src	Refer to clock_main_clk_src_t to set the main clock source.

uint32_t CLOCK_GetMainClkFreq ( void )

Returns: Frequency of Main Clock.

static uint32_t CLOCK_GetCoreSysClkFreq ( void )

inlinestatic

Returns: Frequency of core.

uint32_t CLOCK_GetClockOutClkFreq ( void )

Returns: Frequency of ClockOut

uint32_t CLOCK_GetIrcFreq ( void )

Returns: Frequency of IRC

uint32_t CLOCK_GetSysOscFreq ( void )

Returns: Frequency of SYSOSC

uint32_t CLOCK_GetUartClkFreq ( void )

Return values

UART0 frequency value.

uint32_t CLOCK_GetUart0ClkFreq ( void )

Return values

UART0 frequency value.

uint32_t CLOCK_GetUart1ClkFreq ( void )

Return values

UART1 frequency value.

uint32_t CLOCK_GetUart2ClkFreq ( void )

Return values

UART2 frequency value.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

Returns: Frequency of selected clock

uint32_t CLOCK_GetSystemPLLInClockRate ( void )

Returns: System PLL input clock rate

static uint32_t CLOCK_GetSystemPLLFreq ( void )

inlinestatic

Returns: Frequency of PLL

static uint32_t CLOCK_GetWdtOscFreq ( void )

inlinestatic

Return values

watch dog OSC frequency value.

static uint32_t CLOCK_GetExtClkFreq ( void )

inlinestatic

Return values

external clock frequency value.

void CLOCK_InitSystemPll ( const clock_sys_pll_t * config )

Parameters

config System PLL configurations.

static void CLOCK_DenitSystemPll ( void )

inlinestatic

void CLOCK_InitExtClkin ( uint32_t clkInFreq )

Parameters

clkInFreq external clock in frequency.

void CLOCK_InitSysOsc ( uint32_t oscFreq )

Parameters

oscFreq oscillator frequency value.

void CLOCK_InitXtalin ( uint32_t xtalInFreq )

Parameters

xtalInFreq XTALIN frequency value

Returns: Frequency of PLL

void CLOCK_InitWdtOsc	(	clock_wdt_analog_freq_t	wdtOscFreq,
		uint32_t	wdtOscDiv
	)

The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the FRO or system oscillator. The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator. Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.

Parameters

wdtOscFreq	watch dog analog part output frequency, reference _wdt_analog_output_freq.
wdtOscDiv	watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2

bool CLOCK_SetUARTFRGClkFreq ( uint32_t freq )

Deprecated:: Do not use this function. Refer to CLOCK_SetFRGClkMul().

Parameters

freq	UART clock src.

static void CLOCK_SetUARTFRGMULT ( uint32_t mul )

inlinestatic

Parameters

mul	UARTFRGMULT.

Variable Documentation

volatile uint32_t g_Wdt_Osc_Freq

This variable is used to store the watchdog oscillator frequency which is set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.

volatile uint32_t g_Ext_Clk_Freq

This variable is used to store the external clock frequency which is include external oscillator clock and external clk in clock frequency value, it is set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc when external oscillator is used as external clock ,and it is returned by CLOCK_GetExtClkFreq.

Overview

Function description

SYSCON Clock frequency functions

SYSCON clock Selection Muxes

SYSCON clock dividers

SYSCON flash wait states

Typical use case

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Driver version

Clock gate, mux, and divider.

Get frequency

PLL operations

External/internal oscillator clock operations

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