Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (SOSC, FRO, PLL and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Modules
	System Clock Generator (SCG)

Files
file	fsl_clock.h

Data Structures
struct	_cgc_rtd_sys_clk_config
	CGC system clock configuration for RTD. More...

struct	_cgc_hifi_sys_clk_config
	CGC system clock configuration for HIFI4 DSP. More...

struct	_cgc_lpav_sys_clk_config
	CGC system clock configuration for LPAV. More...

struct	_cgc_ddr_sys_clk_config
	CGC system clock configuration for DDR in LPAV. More...

struct	_cgc_sosc_config
	CGC system OSC configuration. More...

struct	_cgc_fro_config
	CGC FRO clock configuration. More...

struct	_cgc_lposc_config
	CGC LPOSC clock configuration. More...

struct	_cgc_pll0_config
	CGC PLL0 configuration. More...

struct	_cgc_rosc_config
	CGC RTC OSC configuration. More...

struct	_cgc_pll1_config
	CGC PLL1 configuration. More...

struct	_cgc_pll4_config
	CGC PLL4 configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CGC_PLLPFD_PFD_VAL(pfdClkout, fracValue) ((uint32_t)((uint32_t)(fracValue) << (uint32_t)(pfdClkout)))
	CGC (A/S)PLLPFD[PFDx] value.

#define	CGC_PLLPFD_PFD_MASK(pfdClkout) ((uint32_t)((uint32_t)(CGC_PLL0PFDCFG_PFD0_MASK) << (uint32_t)(pfdClkout)))
	CGC (A/S)PLLPFD[PFD] mask.

#define	CGC_PLLPFD_PFD_VALID_MASK(pfdClkout) ((uint32_t)((uint32_t)CGC_PLL0PFDCFG_PFD0_VALID_MASK << (uint32_t)(pfdClkout)))
	CGC (A/S)PLLPFD[PFDx_VALID] mask.

#define	CGC_PLLPFD_PFD_CLKGATE_MASK(pfdClkout) ((uint32_t)((uint32_t)CGC_PLL0PFDCFG_PFD0_CLKGATE_MASK << (uint32_t)(pfdClkout)))
	CGC (A/S)PLLPFD[PFDx_CLKGATE] mask.

#define	PCC_CLKCFG_PCD_MASK (0x7U)
	Re-define PCC register masks and bitfield operations to unify the different namings in the soc header file.

#define	PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
	Bitfield values for general PCC registers. More...

#define	CLOCK_IP_SOURCE_PCC_INDEX(idx) ((idx) << 8U)
	Clock source index macros for clock_ip_src_t.

#define	PCC_PCS_AVAIL_MASK (0x2U)
	Define PCC bit available mask for clock_ip_name_t.

#define	IP_NAME_NON_PCC_FLAG_MASK ((uint32_t)1U << 30)
	Define Non-PCC register flag mask for clock_ip_name_t.

#define	PCC_REG(name) ((volatile uint32_t )((uint32_t)(name) & ~(PCC_PCS_AVAIL_MASK \| PCC_PCD_FRAC_AVAIL_MASK)))
	Define PCC register content for clock_ip_name_t.

#define	RGPIO_CLOCKS
	Clock ip name array for RGPIO2P. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	PCTL_CLOCKS
	Clock ip name array for PCTL. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	I3C_CLOCKS
	Clock ip name array for I3C. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	PDM_CLOCKS
	Clock ip name array for PDM. More...

#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF/DCNANO. More...

#define	MIPI_DSI_HOST_CLOCKS
	Clock ip name array for MIPI DSI. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	EDMA_CHAN_CLOCKS
	Clock ip name array for EDMA Channels. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	LPTMR_CLOCKS
	Clock ip name array for LPTMR. More...

#define	LPADC_CLOCKS
	Clock ip name array for LPADC. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	TPM_CLOCKS
	Clock ip name array for TPM. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	WDOG_CLOCKS
	Clock ip name array for MU. More...

#define	SEMA42_CLOCKS
	Clock ip name array for SEMA42. More...

#define	TPIU_CLOCKS
	Clock ip name array for TPIU. More...

#define	FLEXSPI_CLOCKS
	Clock ip name array for QSPI. More...

#define	MRT_CLOCKS
	Clock ip name array for MRT. More...

#define	BBNSM_CLOCKS
	Clock ip name array for BBNSM. More...

#define	PXP_CLOCKS
	Clock ip name array for PXP. More...

#define	EPDC_CLOCKS
	Clock ip name array for EPDC. More...

Typedefs
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...

typedef enum _clock_ip_src	clock_ip_src_t
	Clock source for peripherals that support various clock selections.

typedef enum _clock_lptmr_src	clock_lptmr_src_t
	Clock source for LPTMR.

typedef enum _clock_ip_name	clock_ip_name_t
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. More...

typedef enum _cgc_sys_clk	cgc_sys_clk_t
	CGC system clock type.

typedef enum _cgc_rtd_sys_clk_src	cgc_rtd_sys_clk_src_t
	CGC system clock source for RTD.

typedef enum _cgc_nic_sys_clk_src	cgc_nic_sys_clk_src_t
	CGC system clock source for NIC in AD.

typedef enum _cgc_hifi_sys_clk_src	cgc_hifi_sys_clk_src_t
	CGC system clock source for HIFI4 in LPAV.

typedef enum _cgc_lpav_sys_clk_src	cgc_lpav_sys_clk_src_t
	CGC system clock source for LPAV.

typedef enum _cgc_ddr_sys_clk_src	cgc_ddr_sys_clk_src_t
	CGC system clock source for DDR.

typedef struct _cgc_rtd_sys_clk_config	cgc_rtd_sys_clk_config_t
	CGC system clock configuration for RTD.

typedef struct _cgc_hifi_sys_clk_config	cgc_hifi_sys_clk_config_t
	CGC system clock configuration for HIFI4 DSP.

typedef struct _cgc_lpav_sys_clk_config	cgc_lpav_sys_clk_config_t
	CGC system clock configuration for LPAV.

typedef struct _cgc_ddr_sys_clk_config	cgc_ddr_sys_clk_config_t
	CGC system clock configuration for DDR in LPAV.

typedef enum _clock_rtd_clkout_src	clock_rtd_clkout_src_t
	CGC clock out configuration (CLKOUTCFG) in RTD.

typedef enum _clock_lpav_clkout_src	clock_lpav_clkout_src_t
	CGC clock out configuration (CLKOUTCFG) in LPAV.

typedef enum _cgc_async_clk	cgc_async_clk_t
	CGC asynchronous clock type.

typedef enum _cgc_sosc_monitor_mode	cgc_sosc_monitor_mode_t
	CGC system OSC monitor mode.

typedef enum _cgc_sosc_mode	cgc_sosc_mode_t
	OSC work mode. More...

typedef struct _cgc_sosc_config	cgc_sosc_config_t
	CGC system OSC configuration.

typedef struct _cgc_fro_config	cgc_fro_config_t
	CGC FRO clock configuration.

typedef struct _cgc_lposc_config	cgc_lposc_config_t
	CGC LPOSC clock configuration.

typedef enum _cgc_pll_src	cgc_pll_src_t
	CGC PLL clock source.

typedef enum _cgc_pll_pfd_clkout	cgc_pll_pfd_clkout_t
	CGC PLL PFD clouk out select.

typedef enum _cgc_pll0_mult	cgc_pll0_mult_t
	PLL0 Multiplication Factor.

typedef struct _cgc_pll0_config	cgc_pll0_config_t
	CGC PLL0 configuration.

typedef enum _cgc_rosc_monitor_mode	cgc_rosc_monitor_mode_t
	CGC RTC OSC monitor mode.

typedef struct _cgc_rosc_config	cgc_rosc_config_t
	CGC RTC OSC configuration.

typedef enum _cgc_pll1_mult	cgc_pll1_mult_t
	PLL1 Multiplication Factor.

typedef struct _cgc_pll1_config	cgc_pll1_config_t
	CGC PLL1 configuration.

typedef enum _cgc_pll4_mult	cgc_pll4_mult_t
	PLL4 Multiplication Factor.

typedef struct _cgc_pll4_config	cgc_pll4_config_t
	CGC PLL4 configuration.

typedef enum _cgc_rtd_audclk_src	cgc_rtd_audclk_src_t
	AUD_CLK0 source in RTD.

typedef enum _cgc_ad_audclk_src	cgc_ad_audclk_src_t
	AUD_CLK1 source in AD.

typedef enum _cgc_lpav_audclk_src	cgc_lpav_audclk_src_t
	AUD_CLK2 source in LPAV.

Enumerations
enum	_clock_name { kCLOCK_Cm33CorePlatClk, kCLOCK_Cm33BusClk, kCLOCK_Cm33SlowClk, kCLOCK_FusionDspCorePlatClk, kCLOCK_FusionDspBusClk, kCLOCK_FusionDspSlowClk, kCLOCK_XbarBusClk, kCLOCK_HifiDspClk, kCLOCK_HifiNicPlatClk, kCLOCK_NicLpavAxiClk, kCLOCK_NicLpavAhbClk, kCLOCK_NicLpavBusClk, kCLOCK_DdrClk, kCLOCK_SysOscClk, kCLOCK_FroClk, kCLOCK_LpOscClk, kCLOCK_RtcOscClk, kCLOCK_LvdsClk, kCLOCK_RtdFroDiv1Clk, kCLOCK_RtdFroDiv2Clk, kCLOCK_RtdFroDiv3Clk, kCLOCK_RtdSysOscDiv1Clk, kCLOCK_RtdSysOscDiv2Clk, kCLOCK_RtdSysOscDiv3Clk, kCLOCK_AdFroDiv1Clk, kCLOCK_AdFroDiv2Clk, kCLOCK_AdFroDiv3Clk, kCLOCK_AdSysOscDiv1Clk, kCLOCK_AdSysOscDiv2Clk, kCLOCK_AdSysOscDiv3Clk, kCLOCK_LpavFroDiv1Clk, kCLOCK_LpavFroDiv2Clk, kCLOCK_LpavFroDiv3Clk, kCLOCK_LpavSysOscDiv1Clk, kCLOCK_LpavSysOscDiv2Clk, kCLOCK_LpavSysOscDiv3Clk, kCLOCK_Pll0Clk, kCLOCK_Pll1Clk, kCLOCK_Pll3Clk, kCLOCK_Pll4Clk, kCLOCK_Pll0Pfd0Clk, kCLOCK_Pll0Pfd1Clk, kCLOCK_Pll0Pfd2Clk, kCLOCK_Pll0Pfd3Clk, kCLOCK_Pll1Pfd0Clk, kCLOCK_Pll1Pfd1Clk, kCLOCK_Pll1Pfd2Clk, kCLOCK_Pll1Pfd3Clk, kCLOCK_Pll3Pfd0Clk, kCLOCK_Pll3Pfd1Clk, kCLOCK_Pll3Pfd2Clk, kCLOCK_Pll3Pfd3Clk, kCLOCK_Pll4Pfd0Clk, kCLOCK_Pll4Pfd1Clk, kCLOCK_Pll4Pfd2Clk, kCLOCK_Pll4Pfd3Clk, kCLOCK_Pll0VcoDivClk, kCLOCK_Pll0Pfd1DivClk, kCLOCK_Pll0Pfd2DivClk, kCLOCK_Pll1VcoDivClk, kCLOCK_Pll1Pfd1DivClk, kCLOCK_Pll1Pfd2DivClk, kCLOCK_Pll3VcoDivClk, kCLOCK_Pll3Pfd0Div1Clk, kCLOCK_Pll3Pfd0Div2Clk, kCLOCK_Pll3Pfd1Div1Clk, kCLOCK_Pll3Pfd1Div2Clk, kCLOCK_Pll3Pfd2Div1Clk, kCLOCK_Pll3Pfd2Div2Clk, kCLOCK_Pll3Pfd3Div1Clk, kCLOCK_Pll3Pfd3Div2Clk, kCLOCK_Pll4VcoDivClk, kCLOCK_Pll4Pfd0Div1Clk, kCLOCK_Pll4Pfd0Div2Clk, kCLOCK_Pll4Pfd1Div1Clk, kCLOCK_Pll4Pfd1Div2Clk, kCLOCK_Pll4Pfd2Div1Clk, kCLOCK_Pll4Pfd2Div2Clk, kCLOCK_Pll4Pfd3Div1Clk, kCLOCK_Pll4Pfd3Div2Clk }
	Clock name used to get clock frequency. More...

enum	_clock_ip_src { kCLOCK_IpSrcNone = 0U, kCLOCK_Pcc0PlatIpSrcSysOscDiv1, kCLOCK_Pcc0PlatIpSrcFroDiv1, kCLOCK_Pcc0PlatIpSrcCm33Plat, kCLOCK_Pcc0PlatIpSrcFro, kCLOCK_Pcc0PlatIpSrcPll0Pfd3, kCLOCK_Pcc0BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(0U) \| 1U, kCLOCK_Pcc0BusIpSrcSysOscDiv2, kCLOCK_Pcc0BusIpSrcFroDiv2, kCLOCK_Pcc0BusIpSrcCm33Bus, kCLOCK_Pcc0BusIpSrcPll1Pfd1Div, kCLOCK_Pcc0BusIpSrcPll0Pfd2Div, kCLOCK_Pcc0BusIpSrcPll0Pfd1Div, kCLOCK_Pcc1PlatIpSrcSysOscDiv1, kCLOCK_Pcc1PlatIpSrcFroDiv1, kCLOCK_Pcc1PlatIpSrcCm33Plat, kCLOCK_Pcc1PlatIpSrcFro, kCLOCK_Pcc1PlatIpSrcPll0Pfd3, kCLOCK_Pcc1BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(1U) \| 1U, kCLOCK_Pcc1BusIpSrcSysOscDiv2, kCLOCK_Pcc1BusIpSrcFroDiv2, kCLOCK_Pcc1BusIpSrcCm33Bus, kCLOCK_Pcc1BusIpSrcPll1VcoDiv, kCLOCK_Pcc1BusIpSrcPll0Pfd2Div, kCLOCK_Pcc1BusIpSrcPll0Pfd1Div, kCLOCK_Pcc2BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(2U) \| 1U, kCLOCK_Pcc2BusIpSrcSysOscDiv3, kCLOCK_Pcc2BusIpSrcFroDiv3, kCLOCK_Pcc2BusIpSrcFusionDspBus, kCLOCK_Pcc2BusIpSrcPll1VcoDiv, kCLOCK_Pcc2BusIpSrcPll0Pfd2Div, kCLOCK_Pcc2BusIpSrcPll0Pfd1Div, kCLOCK_Pcc3BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(3U) \| 1U, kCLOCK_Pcc3BusIpSrcSysOscDiv2, kCLOCK_Pcc3BusIpSrcFroDiv2, kCLOCK_Pcc3BusIpSrcXbarBus = CLOCK_IP_SOURCE_PCC_INDEX(3U) \| 4U, kCLOCK_Pcc3BusIpSrcPll3Pfd1Div1, kCLOCK_Pcc3BusIpSrcPll3Pfd0Div2, kCLOCK_Pcc3BusIpSrcPll3Pfd0Div1, kCLOCK_Pcc4PlatIpSrcSysOscDiv1, kCLOCK_Pcc4PlatIpSrcFroDiv1, kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div2, kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div1, kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div2, kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div1, kCLOCK_Pcc4PlatIpSrcPll3Pfd1Div2, kCLOCK_Pcc4BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(4U) \| 2U, kCLOCK_Pcc4BusIpSrcSysOscDiv2, kCLOCK_Pcc4BusIpSrcFroDiv2, kCLOCK_Pcc4BusIpSrcXbarBus = CLOCK_IP_SOURCE_PCC_INDEX(4U) \| 5U, kCLOCK_Pcc4BusIpSrcPll3VcoDiv, kCLOCK_Pcc4BusIpSrcPll3Pfd0Div1, kCLOCK_Pcc5PlatIpSrcPll4Pfd3Div2, kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div2, kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div1, kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div2, kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div1, kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div2, kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div1, kCLOCK_Pcc5BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(5U) \| 2U, kCLOCK_Pcc5BusIpSrcSysOscDiv2, kCLOCK_Pcc5BusIpSrcFroDiv2, kCLOCK_Pcc5BusIpSrcLpavBus, kCLOCK_Pcc5BusIpSrcPll4VcoDiv, kCLOCK_Pcc5BusIpSrcPll4Pfd3Div1, kCLOCK_Cm33SaiClkSrcPll1Pfd2Div, kCLOCK_Cm33SaiClkSrcRtdAudClk, kCLOCK_Cm33SaiClkSrcLpavAudClk, kCLOCK_Cm33SaiClkSrcSysOsc, kCLOCK_FusionSaiClkSrcPll1Pfd2Div, kCLOCK_FusionSaiClkSrcExtMclk1, kCLOCK_FusionSaiClkSrcSai3Rx, kCLOCK_FusionSaiClkSrcSai2Tx, kCLOCK_FusionSaiClkSrcSysOsc, kCLOCK_FusionMicfilClkSrcPll1Pfd2Div, kCLOCK_FusionMicfilClkSrcFro24 = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) \| 1U, kCLOCK_FusionMicfilClkSrcSysOsc, kCLOCK_FusionMicfilClkSrcExtMclk1, kCLOCK_FusionMicfilClkSrcRtcOsc = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) \| 4U, kCLOCK_FusionMicfilClkSrcLpo = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) \| 5U, kCLOCK_FusionTpm2ClkSrcPll1Pfd2Div, kCLOCK_FusionTpm2ClkSrcExtMclk1, kCLOCK_FusionTpm2ClkSrcLpo, kCLOCK_FusionTpm2ClkSrcSysOscDiv3, kCLOCK_FusionTpm2ClkSrcFroDiv3, kCLOCK_FusionTpm2ClkSrcFusionDspBus, kCLOCK_FusionTpm2ClkSrcPll1VcoDiv, kCLOCK_FusionTpm2ClkSrcPll0Pfd2Div, kCLOCK_FusionTpm2ClkSrcPll0Pfd1Div, kCLOCK_FusionTpm3ClkSrcPll1Pfd2Div, kCLOCK_FusionTpm3ClkSrcRtdAudClk, kCLOCK_FusionTpm3ClkSrcLpavAudClk, kCLOCK_FusionTpm3ClkSrcLpo, kCLOCK_FusionTpm3ClkSrcSysOscDiv3, kCLOCK_FusionTpm3ClkSrcFroDiv3, kCLOCK_FusionTpm3ClkSrcFusionDspBus, kCLOCK_FusionTpm3ClkSrcPll1VcoDiv, kCLOCK_FusionTpm3ClkSrcPll0Pfd2Div, kCLOCK_FusionTpm3ClkSrcPll0Pfd1Div, kCLOCK_AdSaiClkSrcPll3Pfd1Div1, kCLOCK_AdSaiClkSrcAdAudClk, kCLOCK_AdSaiClkSrcLpavAudClk, kCLOCK_AdSaiClkSrcSysOsc, kCLOCK_AdTpm67ClkSrcPll3Pfd1Div1, kCLOCK_AdTpm67ClkSrcAdAudClk, kCLOCK_AdTpm67ClkSrcLpavAudClk, kCLOCK_AdTpm67ClkSrcLpo, kCLOCK_AdTpm67ClkSrcSysOscDiv2, kCLOCK_AdTpm67ClkSrcFroDiv2, kCLOCK_AdTpm67ClkSrcXbarBus, kCLOCK_AdTpm67ClkSrcPll3VcoDiv, kCLOCK_AdTpm67ClkSrcPll3Pfd0Div1, kCLOCK_LpavSaiClkSrcPll1Pfd2Div, kCLOCK_LpavSaiClkSrcPll3Pfd1Div1, kCLOCK_LpavSaiClkSrcRtdAudClk, kCLOCK_LpavSaiClkSrcAdAudClk, kCLOCK_LpavSaiClkSrcLpavAudClk, kCLOCK_LpavSaiClkSrcSysOsc, kCLOCK_LpavTpm8ClkSrcPll1Pfd2Div, kCLOCK_LpavTpm8ClkSrcPll3Pfd1Div1, kCLOCK_LpavTpm8ClkSrcRtdAudClk, kCLOCK_LpavTpm8ClkSrcAdAudClk, kCLOCK_LpavTpm8ClkSrcLpavAudClk, kCLOCK_LpavTpm8ClkSrcLpo, kCLOCK_LpavTpm8ClkSrcSysOscDiv2, kCLOCK_LpavTpm8ClkSrcFroDiv2, kCLOCK_LpavTpm8ClkSrcLpavBus, kCLOCK_LpavTpm8ClkSrcPll4VcoDiv, kCLOCK_LpavTpm8ClkSrcPll4Pfd3Div1 }
	Clock source for peripherals that support various clock selections. More...

enum	_clock_lptmr_src { kCLOCK_LptmrSrcLPO1M = 0U, kCLOCK_LptmrSrcRtc1K = 1U, kCLOCK_LptmrSrcRtc32K = 2U, kCLOCK_LptmrSrcSysOsc = 3U }
	Clock source for LPTMR. More...

enum	_clock_ip_name
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. More...

enum	{ kStatus_CGC_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), kStatus_CGC_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) }
	CGC status return codes. More...

enum	_cgc_sys_clk { kCGC_SysClkSlow, kCGC_SysClkBus, kCGC_SysClkCorePlat, kCGC_SysClkHifi4, kCGC_SysClkNicHifi, kCGC_SysClkLpavAxi, kCGC_SysClkLpavAhb, kCGC_SysClkLpavBus }
	CGC system clock type. More...

enum	_cgc_rtd_sys_clk_src { kCGC_RtdSysClkSrcFro = 0U, kCGC_RtdSysClkSrcPll0Pfd0 = 1U, kCGC_RtdSysClkSrcPll1Pfd0 = 2U, kCGC_RtdSysClkSrcSysOsc = 3U, kCGC_RtdSysClkSrcRtcOsc = 4U, kCGC_RtdSysClkSrcLvds = 5U, kCGC_RtdSysClkSrcPll0 = 6U }
	CGC system clock source for RTD. More...

enum	_cgc_nic_sys_clk_src { kCGC_NicSysClkSrcFro = 0U, kCGC_NicSysClkSrcPll3Pfd0 = 1U, kCGC_NicSysClkSrcSysOsc = 2U, kCGC_NicSysClkSrcLvds = 3U }
	CGC system clock source for NIC in AD. More...

enum	_cgc_hifi_sys_clk_src { kCGC_HifiSysClkSrcFro = 0U, kCGC_HifiSysClkSrcPll4 = 1U, kCGC_HifiSysClkSrcPll4Pfd0 = 2U, kCGC_HifiSysClkSrcSysOsc = 3U, kCGC_HifiSysClkSrcLvds = 4U }
	CGC system clock source for HIFI4 in LPAV. More...

enum	_cgc_lpav_sys_clk_src { kCGC_LpavSysClkSrcFro = 0U, kCGC_LpavSysClkSrcPll4Pfd1 = 1U, kCGC_LpavSysClkSrcSysOsc = 2U, kCGC_LpavSysClkSrcLvds = 3U }
	CGC system clock source for LPAV. More...

enum	_cgc_ddr_sys_clk_src { kCGC_DdrSysClkSrcFro = 0U, kCGC_DdrSysClkSrcPll4Pfd1 = 1U, kCGC_DdrSysClkSrcSysOsc = 2U, kCGC_DdrSysClkSrcLvds = 3U }
	CGC system clock source for DDR. More...

enum	_clock_rtd_clkout_src { kClockRtdClkoutSelCm33Core = 0U, kClockRtdClkoutSelCm33Bus = 1U, kClockRtdClkoutSelCm33Slow = 2U, kClockRtdClkoutSelFusionDspCore = 3U, kClockRtdClkoutSelFusionDspBus = 4U, kClockRtdClkoutSelFusionDspSlow = 5U, kClockRtdClkoutSelFro48 = 6U, kClockRtdClkoutSelPll0VcoDiv = 7U, kClockRtdClkoutSelPll1VcoDiv = 8U, kClockRtdClkoutSelSysOsc = 9U, kClockRtdClkoutSelLpOsc = 10U }
	CGC clock out configuration (CLKOUTCFG) in RTD. More...

enum	_clock_lpav_clkout_src { kClockLpavClkoutSelHifi4 = 0U, kClockLpavClkoutSelNicHifi = 1U, kClockLpavClkoutSelLpavAxi = 2U, kClockLpavClkoutSelLpavAhb = 3U, kClockLpavClkoutSelLpavBus = 4U, kClockLpavClkoutSelDdr = 5U, kClockLpavClkoutSelFro48 = 6U, kClockLpavClkoutSelPll4VcoDiv = 7U, kClockLpavClkoutSelSysOsc = 9U, kClockLpavClkoutSelLpOsc = 10U }
	CGC clock out configuration (CLKOUTCFG) in LPAV. More...

enum	_cgc_async_clk { kCGC_AsyncDiv1Clk = 1U, kCGC_AsyncDiv2Clk = 2U, kCGC_AsyncDiv3Clk = 3U, kCGC_AsyncVcoClk = 4U, kCGC_AsyncPfd0Div1Clk = 5U, kCGC_AsyncPfd0Div2Clk = 6U, kCGC_AsyncPfd1Div1Clk = 7U, kCGC_AsyncPfd1Div2Clk = 8U, kCGC_AsyncPfd2Div1Clk = 9U, kCGC_AsyncPfd2Div2Clk = 10U, kCGC_AsyncPfd3Div1Clk = 11U, kCGC_AsyncPfd3Div2Clk = 12U }
	CGC asynchronous clock type. More...

enum	_cgc_sosc_monitor_mode { kCGC_SysOscMonitorDisable = 0U, kCGC_SysOscMonitorInt = CGC_SOSCCSR_SOSCCM_MASK, kCGC_SysOscMonitorReset }
	CGC system OSC monitor mode. More...

enum	_cgc_sosc_mode { kCGC_SysOscModeExt = CGC_SOSCCFG_SYSOSC_BYPASS_EN_MASK, kCGC_SysOscModeOscLowPower = 0, kCGC_SysOscModeOscHighGain = CGC_SOSCCFG_HGO_MASK }
	OSC work mode. More...

enum	_cgc_sosc_enable_mode { kCGC_SysOscEnableInDeepSleep = CGC_SOSCCSR_SOSCDSEN_MASK, kCGC_SysOscEnableInPowerDown = CGC_SOSCCSR_SOSCPDEN_MASK }
	OSC enable mode. More...

enum	_cgc_fro_enable_mode { kCGC_FroEnableInDeepSleep = CGC_FROCSR_FRODSEN_MASK }
	FRO enable mode. More...

enum	_cgc_lposc_enable_mode { kCGC_LposcEnableInDeepSleep = CGC_LPOSCCSR_LPOSCDSEN_MASK, kCGC_LposcEnableInPowerDown = CGC_LPOSCCSR_LPOSCPDEN_MASK }
	LPOSC enable mode. More...

enum	_cgc_pll_src { kCGC_PllSrcSysOsc, kCGC_PllSrcFro24M }
	CGC PLL clock source. More...

enum	_cgc_pll_enable_mode { kCGC_PllEnable = CGC_PLL0CSR_PLL0EN_MASK, kCGC_PllEnableInDeepSleep = CGC_PLL0CSR_PLL0DSEN_MASK }
	PLL enable mode. More...

enum	_cgc_pll_pfd_clkout { kCGC_PllPfd0Clk = 0U, kCGC_PllPfd1Clk = 8U, kCGC_PllPfd2Clk = 16U, kCGC_PllPfd3Clk = 24U }
	CGC PLL PFD clouk out select. More...

enum	_cgc_pll0_mult { kCGC_Pll0Mult15 = 1U, kCGC_Pll0Mult16 = 2U, kCGC_Pll0Mult20 = 3U, kCGC_Pll0Mult22 = 4U, kCGC_Pll0Mult25 = 5U, kCGC_Pll0Mult30 = 6U }
	PLL0 Multiplication Factor. More...

enum	_cgc_rosc_monitor_mode { kCGC_RtcOscMonitorDisable = 0U, kCGC_RtcOscMonitorInt = CGC_ROSCCTRL_ROSCCM_MASK, kCGC_RtcOscMonitorReset }
	CGC RTC OSC monitor mode. More...

enum	_cgc_pll1_mult { kCGC_Pll1Mult16 = 16U, kCGC_Pll1Mult17 = 17U, kCGC_Pll1Mult20 = 20U, kCGC_Pll1Mult22 = 22U, kCGC_Pll1Mult27 = 27U, kCGC_Pll1Mult33 = 33U }
	PLL1 Multiplication Factor. More...

enum	_cgc_pll4_mult { kCGC_Pll4Mult16 = 16U, kCGC_Pll4Mult17 = 17U, kCGC_Pll4Mult20 = 20U, kCGC_Pll4Mult22 = 22U, kCGC_Pll4Mult27 = 27U, kCGC_Pll4Mult33 = 33U }
	PLL4 Multiplication Factor. More...

enum	_cgc_rtd_audclk_src { kCGC_RtdAudClkSrcExtMclk0 = 0, kCGC_RtdAudClkSrcExtMclk1 = 1, kCGC_RtdAudClkSrcSai0RxBclk = 2, kCGC_RtdAudClkSrcSai0TxBclk = 3, kCGC_RtdAudClkSrcSai1RxBclk = 4, kCGC_RtdAudClkSrcSai1TxBclk = 5, kCGC_RtdAudClkSrcSai2RxBclk = 6, kCGC_RtdAudClkSrcSai2TxBclk = 7, kCGC_RtdAudClkSrcSai3RxBclk = 8, kCGC_RtdAudClkSrcSai3TxBclk = 9 }
	AUD_CLK0 source in RTD. More...

enum	_cgc_ad_audclk_src { kCGC_AdAudClkSrcExtMclk2 = 0, kCGC_AdAudClkSrcSai4RxBclk = 1, kCGC_AdAudClkSrcSai4TxBclk = 2, kCGC_AdAudClkSrcSai5RxBclk = 3, kCGC_AdAudClkSrcSai5TxBclk = 4 }
	AUD_CLK1 source in AD. More...

enum	_cgc_lpav_audclk_src { kCGC_LpavAudClkSrcExtMclk3 = 0, kCGC_LpavAudClkSrcSai6RxBclk = 1, kCGC_LpavAudClkSrcSai6TxBclk = 2, kCGC_LpavAudClkSrcSai7RxBclk = 3, kCGC_LpavAudClkSrcSai7TxBclk = 4, kCGC_LpavAudClkSrcSpdifRx = 5 }
	AUD_CLK2 source in LPAV. More...

Functions
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static bool	CLOCK_IsEnabledByOtherCore (clock_ip_name_t name)
	Check whether the clock is already enabled and configured by any other core. More...

void	CLOCK_SetIpSrc (clock_ip_name_t name, clock_ip_src_t src)
	Set the clock source for specific IP module. More...

void	CLOCK_SetIpSrcDiv (clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue)
	Set the clock source and divider for specific IP module. More...

static void	CLOCK_SetRtdAudClkSrc (cgc_rtd_audclk_src_t src)
	Set the AUD_CLK0 source in RTD. More...

static void	CLOCK_SetAdAudClkSrc (cgc_ad_audclk_src_t src)
	Set the AUD_CLK1 source in AD. More...

static void	CLOCK_SetLpavAudClkSrc (cgc_lpav_audclk_src_t src)
	Set the AUD_CLK2 source in LPAV. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCm33CorePlatClkFreq (void)
	Get the CM33 core/platform clock frequency. More...

uint32_t	CLOCK_GetCm33BusClkFreq (void)
	Get the CM33 bus clock frequency. More...

uint32_t	CLOCK_GetCm33SlowClkFreq (void)
	Get the CM33 slow clock frequency. More...

uint32_t	CLOCK_GetFusionDspCorePlatClkFreq (void)
	Get the Fusion DSP core/platform clock frequency. More...

uint32_t	CLOCK_GetFusionDspBusClkFreq (void)
	Get the Fusion DSP bus clock frequency. More...

uint32_t	CLOCK_GetFusionDspSlowClkFreq (void)
	Get the Fusion DSP slow clock frequency. More...

uint32_t	CLOCK_GetLvdsClkFreq (void)
	Get the external LVDS pad clock frequency (LVDS). More...

uint32_t	CLOCK_GetIpFreq (clock_ip_name_t name)
	Gets the clock frequency for a specific IP module. More...

uint32_t	CLOCK_GetRtdSysClkFreq (uint32_t config, cgc_sys_clk_t type)
	Gets the CGC system clock frequency in RTD. More...

Variables
volatile uint32_t	g_xtal0Freq
	External XTAL (SYSOSC) clock frequency. More...

volatile uint32_t	g_xtal32Freq
	External XTAL32/EXTAL32 clock frequency. More...

volatile uint32_t	g_lvdsFreq
	External LVDS pad clock frequency. More...

volatile uint32_t	g_mclkFreq [4]
	External MCLK pad clock frequency. More...

volatile uint32_t	g_rxBclkFreq [8]
	External RX_BCLK pad clock frequency. More...

volatile uint32_t	g_txBclkFreq [8]
	External TX_BCLK pad clock frequency. More...

volatile uint32_t	g_spdifRxFreq
	Recovered SPDIF_RX clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
	CLOCK driver version 2.0.5. More...

MCU System Clock.
uint32_t	CLOCK_GetCm33SysClkFreq (cgc_sys_clk_t type)
	Gets the CGC CM33 system clock frequency. More...

static void	CLOCK_SetCm33SysClkConfig (cgc_rtd_sys_clk_config_t *config)
	Sets the system clock configuration for CM33 domain. More...

uint32_t	CLOCK_GetFusionDspSysClkFreq (cgc_sys_clk_t type)
	Gets the CGC Fusion DSP system clock frequency. More...

static void	CLOCK_SetFusionSysClkConfig (const cgc_rtd_sys_clk_config_t *config)
	Sets the system clock configuration for FusionF1 DSP domain. More...

static void	CLOCK_GetCm33SysClkConfig (cgc_rtd_sys_clk_config_t *config)
	Gets the system clock configuration for CM33 domain. More...

static void	CLOCK_GetFusionDspSysClkConfig (cgc_rtd_sys_clk_config_t *config)
	Gets the system clock configuration for FusionF1 DSP domain. More...

static void	CLOCK_SetRtdClkOutConfig (clock_rtd_clkout_src_t setting, uint8_t div, bool enable)
	Sets the clock out configuration in RTD. More...

static void	CLOCK_SetRtcClkOutConfig (uint8_t div)
	Sets the RTC_CLOCKOUT configuration. More...

uint32_t	CLOCK_GetXbarBusClkFreq (void)
	Gets the CGC XBAR bus clock frequency in AD. More...

uint32_t	CLOCK_GetHifiDspSysClkFreq (cgc_sys_clk_t type)
	Gets the CGC HIFI DSP system clock frequency in LPAV. More...

static void	CLOCK_SetHifiDspSysClkConfig (const cgc_hifi_sys_clk_config_t *config)
	Sets the system clock configuration for HIFI4 DSP domain. More...

static void	CLOCK_GetHifiDspSysClkConfig (cgc_hifi_sys_clk_config_t *config)
	Gets the system clock configuration for HIFI4 DSP domain. More...

uint32_t	CLOCK_GetLpavSysClkFreq (cgc_sys_clk_t type)
	Gets the CGC NIC LPAV system clock frequency in LPAV. More...

static void	CLOCK_SetLpavSysClkConfig (const cgc_lpav_sys_clk_config_t *config)
	Sets the system clock configuration for NIC LPAV domain. More...

static void	CLOCK_GetLpavSysClkConfig (cgc_lpav_sys_clk_config_t *config)
	Gets the system clock configuration for NIC LPAV domain. More...

uint32_t	CLOCK_GetDdrClkFreq (void)
	Gets the CGC DDR clock frequency in LPAV. More...

static void	CLOCK_SetLpavClkOutConfig (clock_lpav_clkout_src_t setting, uint8_t div, bool enable)
	Sets the clock out configuration in LPAV. More...

CGC System OSC Clock.
status_t	CLOCK_InitSysOsc (const cgc_sosc_config_t *config)
	Initializes the CGC system OSC. More...

status_t	CLOCK_DeinitSysOsc (void)
	De-initializes the CGC system OSC. More...

void	CLOCK_SetRtdSysOscAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in RTD. More...

void	CLOCK_SetAdSysOscAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in AD. More...

void	CLOCK_SetLpavSysOscAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in LPAV. More...

uint32_t	CLOCK_GetSysOscFreq (void)
	Gets the CGC system OSC clock frequency (SYSOSC). More...

uint32_t	CLOCK_GetRtdSysOscAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the system OSC in RTD. More...

uint32_t	CLOCK_GetAdSysOscAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the system OSC in AD. More...

uint32_t	CLOCK_GetLpavSysOscAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the system OSC in LPAV. More...

static bool	CLOCK_IsSysOscErr (void)
	Checks whether the system OSC clock error occurs. More...

static void	CLOCK_ClearSysOscErr (void)
	Clears the system OSC clock error.

static void	CLOCK_SetSysOscMonitorMode (cgc_sosc_monitor_mode_t mode)
	Sets the system OSC monitor mode. More...

static bool	CLOCK_IsSysOscSelected (void)
	Checks whether the system OSC clock is used as clock source. More...

static bool	CLOCK_IsSysOscValid (void)
	Checks whether the system OSC clock is valid. More...

CGC FRO Clock.
status_t	CLOCK_InitFro (const cgc_fro_config_t *config)
	Initializes the CGC FRO clock. More...

status_t	CLOCK_DeinitFro (void)
	De-initializes the CGC FRO. More...

void	CLOCK_SetRtdFroAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in RTD. More...

void	CLOCK_SetAdFroAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in AD. More...

void	CLOCK_SetLpavFroAsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider in LPAV. More...

void	CLOCK_EnableFroTuning (bool enable)
	Enable/Disable FRO tuning. More...

uint32_t	CLOCK_GetFroFreq (void)
	Gets the CGC FRO clock frequency. More...

uint32_t	CLOCK_GetRtdFroAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the FRO in RTD. More...

uint32_t	CLOCK_GetAdFroAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the FRO in AD. More...

uint32_t	CLOCK_GetLpavFroAsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the FRO in LPAV. More...

static bool	CLOCK_IsFroSelected (void)
	Checks whether the FRO clock is used as clock source. More...

static bool	CLOCK_IsFroValid (void)
	Checks whether the FRO clock is valid. More...

CGC LPOSC Clock.
status_t	CLOCK_InitLposc (const cgc_lposc_config_t *config)
	Initializes the CGC LPOSC clock. More...

status_t	CLOCK_DeinitLposc (void)
	De-initializes the CGC LPOSC. More...

static bool	CLOCK_IsLpOscValid (void)
	Checks whether the LPOSC clock is valid. More...

uint32_t	CLOCK_GetLpOscFreq (void)
	Gets the CGC LPOSC clock frequency. More...

CGC RTCOSC Clock.
uint32_t	CLOCK_GetRtcOscFreq (void)
	Gets the CGC RTC OSC clock frequency. More...

static bool	CLOCK_IsRtcOscErr (void)
	Checks whether the RTC OSC clock error occurs. More...

static void	CLOCK_ClearRtcOscErr (void)
	Clears the RTC OSC clock error.

void	CLOCK_SetRtcOscMonitorMode (cgc_rosc_monitor_mode_t mode)
	Sets the RTC OSC monitor mode. More...

static bool	CLOCK_IsRtcOscSelected (void)
	Checks whether the RTCOSC clock is used as clock source. More...

static bool	CLOCK_IsRtcOscValid (void)
	Checks whether the RTC OSC clock is valid. More...

CGC PLL0 Clock.
status_t	CLOCK_InitPll0 (const cgc_pll0_config_t *config)
	Initializes the CGC PLL0. More...

status_t	CLOCK_DeinitPll0 (void)
	De-initializes the CGC PLL0. More...

void	CLOCK_SetPll0AsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetPll0Freq (void)
	Gets the CGC PLL0 clock frequency. More...

uint32_t	CLOCK_GetPll0AsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the PLL0. More...

uint32_t	CLOCK_GetPll0PfdFreq (cgc_pll_pfd_clkout_t pfdClkout)
	Gets the CGC PLL0 PFD clock frequency. More...

void	CLOCK_EnablePll0PfdClkout (cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue)
	Enables the CGC PLL0 Fractional Divide (PFD) clock out with configurations. More...

static void	CLOCK_DisablePll0PfdClkout (cgc_pll_pfd_clkout_t pfdClkout)
	Disables the CGC PLL0 Fractional Divide (PFD) clock out.

static void	CLOCK_SetPll0LockTime (uint16_t lockTime)
	Sets the CGC PLL0 lock time. More...

static bool	CLOCK_IsPll0Selected (void)
	Checks whether the PLL0 clock is used as clock source. More...

static bool	CLOCK_IsPll0Valid (void)
	Checks whether the PLL0 clock is valid. More...

CGC PLL1 Clock.
status_t	CLOCK_InitPll1 (const cgc_pll1_config_t *config)
	Initializes the CGC PLL1. More...

status_t	CLOCK_DeinitPll1 (void)
	De-initializes the CGC PLL1. More...

void	CLOCK_SetPll1AsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetPll1Freq (void)
	Gets the CGC PLL1 clock frequency. More...

uint32_t	CLOCK_GetPll1AsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the PLL1. More...

uint32_t	CLOCK_GetPll1PfdFreq (cgc_pll_pfd_clkout_t pfdClkout)
	Gets the CGC PLL1 PFD clock frequency. More...

void	CLOCK_EnablePll1PfdClkout (cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue)
	Enables the CGC PLL1 Fractional Divide (PFD) clock out with configurations. More...

static void	CLOCK_DisablePll1PfdClkout (cgc_pll_pfd_clkout_t pfdClkout)
	Disables the CGC PLL1 Fractional Divide (PFD) clock out.

static void	CLOCK_EnablePll1SpectrumModulation (uint16_t step, uint16_t stop)
	Enables the CGC PLL1 spread spectrum modulation feature with configurations. More...

static void	CLOCK_DisablePll1SpectrumModulation (void)
	Disables the CGC PLL1 spread spectrum modulation.

static void	CLOCK_SetPll1LockTime (uint16_t lockTime)
	Sets the CGC PLL1 lock time. More...

static bool	CLOCK_IsPll1Selected (void)
	Checks whether the PLL1 clock is used as clock source. More...

static bool	CLOCK_IsPll1Valid (void)
	Checks whether the PLL1 clock is valid. More...

CGC PLL3 Clock.
uint32_t	CLOCK_GetPll3Freq (void)
	Gets the CGC PLL3 clock frequency. More...

uint32_t	CLOCK_GetPll3AsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the PLL3. More...

uint32_t	CLOCK_GetPll3PfdFreq (cgc_pll_pfd_clkout_t pfdClkout)
	Gets the CGC PLL3 PFD clock frequency. More...

CGC PLL4 Clock.
status_t	CLOCK_InitPll4 (const cgc_pll4_config_t *config)
	Initializes the CGC PLL4. More...

status_t	CLOCK_DeinitPll4 (void)
	De-initializes the CGC PLL4. More...

void	CLOCK_SetPll4AsyncClkDiv (cgc_async_clk_t asyncClk, uint8_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetPll4Freq (void)
	Gets the CGC PLL4 clock frequency. More...

uint32_t	CLOCK_GetPll4AsyncFreq (cgc_async_clk_t type)
	Gets the CGC asynchronous clock frequency from the PLL4. More...

uint32_t	CLOCK_GetPll4PfdFreq (cgc_pll_pfd_clkout_t pfdClkout)
	Gets the CGC PLL4 PFD clock frequency. More...

void	CLOCK_EnablePll4PfdClkout (cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue)
	Enables the CGC PLL4 Fractional Divide (PFD) clock out with configurations. More...

static void	CLOCK_DisablePll4PfdClkout (cgc_pll_pfd_clkout_t pfdClkout)
	Disables the CGC PLL4 Fractional Divide (PFD) clock out.

static void	CLOCK_EnablePll4SpectrumModulation (uint16_t step, uint16_t stop)
	Enables the CGC PLL4 spread spectrum modulation feature with configurations. More...

static void	CLOCK_SetPll4LockTime (uint16_t lockTime)
	Sets the CGC PLL4 lock time. More...

static bool	CLOCK_IsPll4Selected (void)
	Checks whether the PLL4 clock is used as clock source. More...

static bool	CLOCK_IsPll4Valid (void)
	Checks whether the PLL4 clock is valid. More...

External clock frequency
static void	CLOCK_SetXtal0Freq (uint32_t freq)
	Sets the XTAL0 frequency based on board settings. More...

static void	CLOCK_SetXtal32Freq (uint32_t freq)
	Sets the XTAL32 frequency based on board settings. More...

static void	CLOCK_SetLvdsFreq (uint32_t freq)
	Sets the LVDS pad frequency based on board settings. More...

static void	CLOCK_SetMclkFreq (uint32_t index, uint32_t freq)
	Sets the MCLK pad frequency based on Audio settings. More...

static void	CLOCK_SetRxBclkFreq (uint32_t instance, uint32_t freq)
	Sets the RX_BCLK pad frequency based on Audio settings. More...

static void	CLOCK_SetTxBclkFreq (uint32_t instance, uint32_t freq)
	Sets the TX_BCLK pad frequency based on Audio settings. More...

static void	CLOCK_SetSpdifRxFreq (uint32_t freq)
	Sets the SPDIF_RX frequency based on Audio settings. More...

Get peripheral frequency
uint32_t	CLOCK_GetWdogClkFreq (uint32_t instance)
	Gets the WDOG clock frequency in RTD and LPAV. More...

uint32_t	CLOCK_GetFlexspiClkFreq (uint32_t instance)
	Gets the FlexSPI clock frequency in RTD. More...

uint32_t	CLOCK_GetLpitClkFreq (void)
	Gets the LPIT clock frequency in RTD. More...

uint32_t	CLOCK_GetFlexioClkFreq (void)
	Gets the FlexIO clock frequency in RTD. More...

uint32_t	CLOCK_GetI3cClkFreq (uint32_t instance)
	Gets the I3C clock frequency in RTD and LPAV. More...

uint32_t	CLOCK_GetLpspiClkFreq (uint32_t instance)
	Gets the LPSPI clock frequency in RTD. More...

uint32_t	CLOCK_GetAdcClkFreq (uint32_t instance)
	Gets the ADC clock frequency. More...

uint32_t	CLOCK_GetDacClkFreq (uint32_t instance)
	Gets the DAC clock frequency. More...

uint32_t	CLOCK_GetTpiuClkFreq (void)
	Gets the TPIU clock frequency. More...

uint32_t	CLOCK_GetSwoClkFreq (void)
	Gets the SWO clock frequency. More...

uint32_t	CLOCK_GetTpmClkFreq (uint32_t instance)
	Gets the TPM clock frequency. More...

uint32_t	CLOCK_GetLpi2cClkFreq (uint32_t instance)
	Gets the LPI2C clock frequency in RTD. More...

uint32_t	CLOCK_GetLpuartClkFreq (uint32_t instance)
	Gets the LPUART clock frequency in RTD. More...

uint32_t	CLOCK_GetFlexcanClkFreq (void)
	Gets the FlexCAN clock frequency. More...

uint32_t	CLOCK_GetCsiClkFreq (void)
	Gets the CSI clock frequency. More...

uint32_t	CLOCK_GetDsiClkFreq (void)
	Gets the DSI clock frequency. More...

uint32_t	CLOCK_GetEpdcClkFreq (void)
	Gets the EPDC clock frequency. More...

uint32_t	CLOCK_GetGpu2dClkFreq (void)
	Gets the GPU2D clock frequency. More...

uint32_t	CLOCK_GetGpu3dClkFreq (void)
	Gets the GPU3D clock frequency. More...

uint32_t	CLOCK_GetDcnanoClkFreq (void)
	Gets the DC Nano clock frequency. More...

uint32_t	CLOCK_GetCsiUiClkFreq (void)
	Gets the CSI clk_ui clock frequency. More...

uint32_t	CLOCK_GetCsiEscClkFreq (void)
	Gets the CSI clk_esc clock frequency. More...

uint32_t	CLOCK_GetRtdAudClkFreq (void)
	Gets the audio clock frequency in RTD. More...

uint32_t	CLOCK_GetAdAudClkFreq (void)
	Gets the audio clock frequency in AD. More...

uint32_t	CLOCK_GetLpavAudClkFreq (void)
	Gets the audio clock frequency in LPAV. More...

uint32_t	CLOCK_GetSaiFreq (uint32_t instance)
	Gets the SAI clock frequency. More...

uint32_t	CLOCK_GetSpdifFreq (void)
	Gets the SPDIF clock frequency. More...

uint32_t	CLOCK_GetMqsFreq (uint32_t instance)
	Gets the MQS clock frequency. More...

uint32_t	CLOCK_GetMicfilFreq (void)
	Gets the EMICFIL clock frequency. More...

uint32_t	CLOCK_GetMrtFreq (void)
	Gets the MRT clock frequency. More...

Data Structure Documentation

struct _cgc_rtd_sys_clk_config

Data Fields
uint32_t	divSlow: 6
	Slow clock divider, selected division is the value of the field + 1.

uint32_t	__pad0__: 1
	Reserved. More...

uint32_t	divBus: 6
	Bus clock divider, selected division is the value of the field + 1. More...

uint32_t	__pad1__: 8
	Reserved. More...

uint32_t	divCore: 6
	Core/Platform clock divider, selected division is the value of the field + 1. More...

uint32_t	switchFin: 1
	1: Clock is running. More...

uint32_t	src: 3
	System clock source, see cgc_rtd_sys_clk_src_t. More...

uint32_t	locked: 1
	Clock register locked. More...

Field Documentation

uint32_t _cgc_rtd_sys_clk_config::__pad0__

uint32_t _cgc_rtd_sys_clk_config::divBus

uint32_t _cgc_rtd_sys_clk_config::__pad1__

uint32_t _cgc_rtd_sys_clk_config::divCore

uint32_t _cgc_rtd_sys_clk_config::switchFin

0: Clock is not running.

uint32_t _cgc_rtd_sys_clk_config::src

uint32_t _cgc_rtd_sys_clk_config::locked

struct _cgc_hifi_sys_clk_config

Data Fields
uint32_t	__pad0__: 14
	Reserved. More...

uint32_t	divPlat: 6
	Platform clock divider, selected division is the value of the field + 1. More...

uint32_t	__pad1__: 1
	Reserved. More...

uint32_t	divCore: 6
	Core clock divider, selected division is the value of the field + 1. More...

uint32_t	switchFin: 1
	1: Clock is running. More...

uint32_t	src: 3
	System clock source, see cgc_hifi_sys_clk_src_t. More...

uint32_t	locked: 1
	Clock register locked. More...

Field Documentation

uint32_t _cgc_hifi_sys_clk_config::__pad0__

uint32_t _cgc_hifi_sys_clk_config::divPlat

uint32_t _cgc_hifi_sys_clk_config::__pad1__

uint32_t _cgc_hifi_sys_clk_config::divCore

uint32_t _cgc_hifi_sys_clk_config::switchFin

0: Clock is not running.

uint32_t _cgc_hifi_sys_clk_config::src

uint32_t _cgc_hifi_sys_clk_config::locked

struct _cgc_lpav_sys_clk_config

Data Fields
uint32_t	__pad0__: 7
	Reserved. More...

uint32_t	divBus: 6
	Platform clock divider, selected division is the value of the field + 1. More...

uint32_t	__pad1__: 1
	Reserved. More...

uint32_t	divAhb: 6
	Platform clock divider, selected division is the value of the field + 1. More...

uint32_t	__pad2__: 1
	Reserved. More...

uint32_t	divAxi: 6
	Core clock divider, selected division is the value of the field + 1. More...

uint32_t	switchFin: 1
	1: Clock is running. More...

uint32_t	src: 2
	System clock source, see cgc_lpav_sys_clk_src_t. More...

uint32_t	__pad3__: 1
	Reserved. More...

uint32_t	locked: 1
	Clock register locked. More...

Field Documentation

uint32_t _cgc_lpav_sys_clk_config::__pad0__

uint32_t _cgc_lpav_sys_clk_config::divBus

uint32_t _cgc_lpav_sys_clk_config::__pad1__

uint32_t _cgc_lpav_sys_clk_config::divAhb

uint32_t _cgc_lpav_sys_clk_config::__pad2__

uint32_t _cgc_lpav_sys_clk_config::divAxi

uint32_t _cgc_lpav_sys_clk_config::switchFin

0: Clock is not running.

uint32_t _cgc_lpav_sys_clk_config::src

uint32_t _cgc_lpav_sys_clk_config::__pad3__

uint32_t _cgc_lpav_sys_clk_config::locked

struct _cgc_ddr_sys_clk_config

Data Fields
uint32_t	__pad0__: 21
	Reserved. More...

uint32_t	divDdr: 6
	DDR clock divider, selected division is the value of the field + 1. More...

uint32_t	switchFin: 1
	1: Clock is running. More...

uint32_t	src: 3
	System clock source, see cgc_lpav_sys_clk_src_t. More...

uint32_t	locked: 1
	Clock register locked. More...

Field Documentation

uint32_t _cgc_ddr_sys_clk_config::__pad0__

uint32_t _cgc_ddr_sys_clk_config::divDdr

uint32_t _cgc_ddr_sys_clk_config::switchFin

0: Clock is not running.

uint32_t _cgc_ddr_sys_clk_config::src

uint32_t _cgc_ddr_sys_clk_config::locked

struct _cgc_sosc_config

Data Fields
uint32_t	freq
	System OSC frequency. More...

cgc_sosc_monitor_mode_t	monitorMode
	Clock monitor mode selected. More...

uint8_t	enableMode
	Enable mode, OR'ed value of _cgc_sosc_enable_mode. More...

cgc_sosc_mode_t	workMode
	OSC work mode. More...

Field Documentation

uint32_t _cgc_sosc_config::freq

cgc_sosc_monitor_mode_t _cgc_sosc_config::monitorMode

uint8_t _cgc_sosc_config::enableMode

cgc_sosc_mode_t _cgc_sosc_config::workMode

struct _cgc_fro_config

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _cgc_fro_enable_mode. More...

Field Documentation

uint32_t _cgc_fro_config::enableMode

struct _cgc_lposc_config

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _cgc_lposc_enable_mode. More...

Field Documentation

uint32_t _cgc_lposc_config::enableMode

struct _cgc_pll0_config

Data Fields
uint8_t	enableMode
	Enable mode, OR'ed value of _cgc_pll_enable_mode.

uint8_t	div1
	PLLDIV_VCO divider value. More...

uint8_t	pfd1Div
	PLLDIV_PFD_0 DIV1 divider value. More...

uint8_t	pfd2Div
	PLLDIV_PFD_0 DIV2 divider value. More...

cgc_pll_src_t	src
	Clock source. More...

cgc_pll0_mult_t	mult
	PLL multiplier. More...

Field Documentation

uint8_t _cgc_pll0_config::div1

Disabled when div1 == 0.

uint8_t _cgc_pll0_config::pfd1Div

Disabled when pfd1Div == 0.

uint8_t _cgc_pll0_config::pfd2Div

Disabled when pfd2Div == 0.

cgc_pll_src_t _cgc_pll0_config::src

cgc_pll0_mult_t _cgc_pll0_config::mult

struct _cgc_rosc_config

Data Fields
cgc_rosc_monitor_mode_t	monitorMode
	Clock monitor mode selected. More...

Field Documentation

cgc_rosc_monitor_mode_t _cgc_rosc_config::monitorMode

struct _cgc_pll1_config

Data Fields
uint8_t	enableMode
	Enable mode, OR'ed value of _cgc_pll_enable_mode.

uint8_t	div1
	PLLDIV_VCO divider value. More...

uint8_t	pfd1Div
	PLLDIV_PFD_0 DIV1 divider value. More...

uint8_t	pfd2Div
	PLLDIV_PFD_0 DIV2 divider value. More...

cgc_pll_src_t	src
	Clock source. More...

cgc_pll1_mult_t	mult
	PLL1 multiplier. More...

uint32_t	num: 30
	30-bit numerator of the PLL1 Fractional-Loop divider. More...

uint32_t	denom: 30
	30-bit denominator of the PLL1 Fractional-Loop divider. More...

Field Documentation

uint8_t _cgc_pll1_config::div1

Disabled when div1 == 0.

uint8_t _cgc_pll1_config::pfd1Div

Disabled when pfd1Div == 0.

uint8_t _cgc_pll1_config::pfd2Div

Disabled when pfd2Div == 0.

cgc_pll_src_t _cgc_pll1_config::src

cgc_pll1_mult_t _cgc_pll1_config::mult

uint32_t _cgc_pll1_config::num

uint32_t _cgc_pll1_config::denom

struct _cgc_pll4_config

Data Fields
uint8_t	enableMode
	Enable mode, OR'ed value of _cgc_pll_enable_mode.

uint8_t	div1
	PLLDIV_VCO divider value. More...

uint8_t	pfd0Div1
	PLLDIV_PFD_0 DIV1 divider value. More...

uint8_t	pfd0Div2
	PLLDIV_PFD_0 DIV2 divider value. More...

uint8_t	pfd1Div1
	PLLDIV_PFD_0 DIV3 divider value. More...

uint8_t	pfd1Div2
	PLLDIV_PFD_0 DIV4 divider value. More...

uint8_t	pfd2Div1
	PLLDIV_PFD_1 DIV1 divider value. More...

uint8_t	pfd2Div2
	PLLDIV_PFD_1 DIV2 divider value. More...

uint8_t	pfd3Div1
	PLLDIV_PFD_2 DIV3 divider value. More...

uint8_t	pfd3Div2
	PLLDIV_PFD_2 DIV4 divider value. More...

cgc_pll_src_t	src
	Clock source. More...

cgc_pll4_mult_t	mult
	PLL4 multiplier. More...

uint32_t	num: 30
	30-bit numerator of the PLL4 Fractional-Loop divider. More...

uint32_t	denom: 30
	30-bit denominator of the PLL4 Fractional-Loop divider. More...

Field Documentation

uint8_t _cgc_pll4_config::div1

Disabled when div1 == 0.

uint8_t _cgc_pll4_config::pfd0Div1

Disabled when pfd0Div1 == 0.

uint8_t _cgc_pll4_config::pfd0Div2

Disabled when pfd0Div2 == 0.

uint8_t _cgc_pll4_config::pfd1Div1

Disabled when pfd1Div1 == 0.

uint8_t _cgc_pll4_config::pfd1Div2

Disabled when pfd1Div2 == 0.

uint8_t _cgc_pll4_config::pfd2Div1

Disabled when pfd2Div1 == 0.

uint8_t _cgc_pll4_config::pfd2Div2

Disabled when pfd2Div2 == 0.

uint8_t _cgc_pll4_config::pfd3Div1

Disabled when pfd3Div1 == 0.

uint8_t _cgc_pll4_config::pfd3Div2

Disabled when pfd3Div2 == 0.

cgc_pll_src_t _cgc_pll4_config::src

cgc_pll4_mult_t _cgc_pll4_config::mult

uint32_t _cgc_pll4_config::num

uint32_t _cgc_pll4_config::denom

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))

#define PCC_PCS_VAL ( reg ) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)

#define RGPIO_CLOCKS

Value:

{                                                                                            \
        kCLOCK_RgpioA, kCLOCK_RgpioB, kCLOCK_RgpioC, kCLOCK_RgpioD, kCLOCK_RgpioE, kCLOCK_RgpioF \
    }

#define SAI_CLOCKS

Value:

{                                                                                                          \
        kCLOCK_Sai0, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, kCLOCK_Sai7 \
    }

#define PCTL_CLOCKS

Value:

{                                                                                              \
        kCLOCK_PctlA, kCLOCK_PctlB, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_PctlE, kCLOCK_PctlF \
    }

#define LPI2C_CLOCKS

Value:

{                                                                                                            \
        kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6, \
            kCLOCK_Lpi2c7                                                                                        \
    }

#define I3C_CLOCKS

Value:

{                                         \
        kCLOCK_I3c0, kCLOCK_I3c1, kCLOCK_I3c2 \
    }

#define FLEXIO_CLOCKS

Value:

{                                  \
        kCLOCK_Flexio0, kCLOCK_Flexio1 \
    }

#define FLEXCAN_CLOCKS

Value:

{                  \
        kCLOCK_Flexcan \
    }

#define PDM_CLOCKS

Value:

{                 \
        kCLOCK_Micfil \
    }

#define LCDIF_CLOCKS

Value:

{                 \
        kCLOCK_Dcnano \
    }

#define MIPI_DSI_HOST_CLOCKS

Value:

{                        \
        kCLOCK_Dsi           \
    }

#define EDMA_CLOCKS

Value:

{                                         \
        kCLOCK_Dma0, kCLOCK_Dma1, kCLOCK_Dma2 \
    }

#define EDMA_CHAN_CLOCKS

Value:

{                                                  \
        kCLOCK_Dma0Ch0, kCLOCK_Dma1Ch0, kCLOCK_Dma2Ch0 \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                   \
        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7                                                              \
    }

#define DAC_CLOCKS

Value:

{                            \
        kCLOCK_Dac0, kCLOCK_Dac1 \
    }

#define LPTMR_CLOCKS

Value:

{                                \
        kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
    }

#define LPADC_CLOCKS

Value:

{                            \
        kCLOCK_Adc0, kCLOCK_Adc1 \
    }

#define LPSPI_CLOCKS

Value:

{                                                                                            \
        kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5 \
    }

#define TPM_CLOCKS

Value:

{                                                                                                           \
        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, kCLOCK_Tpm7, \
            kCLOCK_Tpm8                                                                                         \
    }

#define LPIT_CLOCKS

Value:

{                              \
        kCLOCK_Lpit0, kCLOCK_Lpit1 \
    }

#define CMP_CLOCKS

Value:

{                            \
        kCLOCK_Cmp0, kCLOCK_Cmp1 \
    }

#define WDOG_CLOCKS

Value:

{                                                                                      \
        kCLOCK_Wdog0, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4, kCLOCK_Wdog5 \
    }

Clock ip name array for WDOG.

#define SEMA42_CLOCKS

Value:

{                                                  \
        kCLOCK_Sema420, kCLOCK_Sema421, kCLOCK_Sema422 \
    }

#define TPIU_CLOCKS

Value:

{               \
        kCLOCK_Tpiu \
    }

#define FLEXSPI_CLOCKS

Value:

{                                                     \
        kCLOCK_Flexspi0, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
    }

#define MRT_CLOCKS

Value:

{              \
        kCLOCK_Mrt \
    }

#define BBNSM_CLOCKS

Value:

{                \
        kCLOCK_Bbnsm \
    }

#define PXP_CLOCKS

Value:

{              \
        kCLOCK_Pxp \
    }

#define EPDC_CLOCKS

Value:

{               \
        kCLOCK_Epdc \
    }

Typedef Documentation

typedef enum _clock_name clock_name_t

typedef enum _clock_ip_name clock_ip_name_t

[31:2] is defined as the corresponding register address. [ 1:1] is used as indicator of existing of PCS. [ 0:0] is used as indicator of existing of PCD/FRAC.

typedef enum _cgc_sosc_mode cgc_sosc_mode_t

Enumeration Type Documentation

enum _clock_name

Enumerator
kCLOCK_Cm33CorePlatClk	RTD : CM33 Core/Platform clock.
kCLOCK_Cm33BusClk	RTD : CM33 Bus clock.
kCLOCK_Cm33SlowClk	RTD : CM33 Slow clock.
kCLOCK_FusionDspCorePlatClk	RTD : FusionF1 DSP Core/Platform clock.
kCLOCK_FusionDspBusClk	RTD : FusionF1 DSP Bus clock.
kCLOCK_FusionDspSlowClk	RTD : FusionF1 DSP Slow clock.
kCLOCK_XbarBusClk	AD : XBAR Bus clock.
kCLOCK_HifiDspClk	LPAV: HIFI4 clock.
kCLOCK_HifiNicPlatClk	LPAV: NIC HIFI clock.
kCLOCK_NicLpavAxiClk	LPAV: NIC LPAV AXI clock.
kCLOCK_NicLpavAhbClk	LPAV: NIC LPAV AHB clock.
kCLOCK_NicLpavBusClk	LPAV: LPAV Bus clock.
kCLOCK_DdrClk	LPAV: DDR clock.
kCLOCK_SysOscClk	CGC system OSC clock. (SYSOSC)
kCLOCK_FroClk	CGC FRO 192MHz clock.
kCLOCK_LpOscClk	CGC LPOSC clock. (LPOSC)
kCLOCK_RtcOscClk	CGC RTC OSC clock. (RTCOSC)
kCLOCK_LvdsClk	LVDS pad input clock frequency.
kCLOCK_RtdFroDiv1Clk	FRODIV1_CLK in RTD.
kCLOCK_RtdFroDiv2Clk	FRODIV2_CLK in RTD.
kCLOCK_RtdFroDiv3Clk	FRODIV3_CLK in RTD.
kCLOCK_RtdSysOscDiv1Clk	SOSCDIV1_CLK in RTD.
kCLOCK_RtdSysOscDiv2Clk	SOSCDIV2_CLK in RTD.
kCLOCK_RtdSysOscDiv3Clk	SOSCDIV3_CLK in RTD.
kCLOCK_AdFroDiv1Clk	FRODIV1_CLK in AD.
kCLOCK_AdFroDiv2Clk	FRODIV2_CLK in AD.
kCLOCK_AdFroDiv3Clk	FRODIV3_CLK in AD.
kCLOCK_AdSysOscDiv1Clk	SOSCDIV1_CLK in AD.
kCLOCK_AdSysOscDiv2Clk	SOSCDIV2_CLK in AD.
kCLOCK_AdSysOscDiv3Clk	SOSCDIV3_CLK in AD.
kCLOCK_LpavFroDiv1Clk	FRODIV1_CLK in LPAV.
kCLOCK_LpavFroDiv2Clk	FRODIV2_CLK in LPAV.
kCLOCK_LpavFroDiv3Clk	FRODIV3_CLK in LPAV.
kCLOCK_LpavSysOscDiv1Clk	SOSCDIV1_CLK in LPAV.
kCLOCK_LpavSysOscDiv2Clk	SOSCDIV2_CLK in LPAV.
kCLOCK_LpavSysOscDiv3Clk	SOSCDIV3_CLK in LPAV.
kCLOCK_Pll0Clk	CGC PLL0 clock. (PLL0CLK)
kCLOCK_Pll1Clk	CGC PLL1 clock. (PLL1CLK)
kCLOCK_Pll3Clk	CGC PLL3 clock. (PLL3CLK)
kCLOCK_Pll4Clk	CGC PLL4 clock. (PLL4CLK)
kCLOCK_Pll0Pfd0Clk	pll0 pfd0.
kCLOCK_Pll0Pfd1Clk	pll0 pfd1.
kCLOCK_Pll0Pfd2Clk	pll0 pfd2.
kCLOCK_Pll0Pfd3Clk	pll0 pfd3.
kCLOCK_Pll1Pfd0Clk	pll1 pfd0.
kCLOCK_Pll1Pfd1Clk	pll1 pfd1.
kCLOCK_Pll1Pfd2Clk	pll1 pfd2.
kCLOCK_Pll1Pfd3Clk	pll1 pfd3.
kCLOCK_Pll3Pfd0Clk	pll3 pfd0.
kCLOCK_Pll3Pfd1Clk	pll3 pfd1.
kCLOCK_Pll3Pfd2Clk	pll3 pfd2.
kCLOCK_Pll3Pfd3Clk	pll3 pfd3.
kCLOCK_Pll4Pfd0Clk	pll4 pfd0.
kCLOCK_Pll4Pfd1Clk	pll4 pfd1.
kCLOCK_Pll4Pfd2Clk	pll4 pfd2.
kCLOCK_Pll4Pfd3Clk	pll4 pfd3.
kCLOCK_Pll0VcoDivClk	PLL0VCODIV.
kCLOCK_Pll0Pfd1DivClk	PLL0PFD1DIV.
kCLOCK_Pll0Pfd2DivClk	PLL0PFD2DIV.
kCLOCK_Pll1VcoDivClk	PLL1VCODIV.
kCLOCK_Pll1Pfd1DivClk	PLL1PFD1DIV.
kCLOCK_Pll1Pfd2DivClk	PLL1PFD2DIV.
kCLOCK_Pll3VcoDivClk	PLL3VCODIV.
kCLOCK_Pll3Pfd0Div1Clk	PLL3PFD0DIV1.
kCLOCK_Pll3Pfd0Div2Clk	PLL3PFD0DIV2.
kCLOCK_Pll3Pfd1Div1Clk	PLL3PFD1DIV1.
kCLOCK_Pll3Pfd1Div2Clk	PLL3PFD1DIV2.
kCLOCK_Pll3Pfd2Div1Clk	PLL3PFD2DIV1.
kCLOCK_Pll3Pfd2Div2Clk	PLL3PFD2DIV2.
kCLOCK_Pll3Pfd3Div1Clk	PLL3PFD3DIV1.
kCLOCK_Pll3Pfd3Div2Clk	PLL3PFD3DIV2.
kCLOCK_Pll4VcoDivClk	PLL4VCODIV.
kCLOCK_Pll4Pfd0Div1Clk	PLL4PFD0DIV1.
kCLOCK_Pll4Pfd0Div2Clk	PLL4PFD0DIV2.
kCLOCK_Pll4Pfd1Div1Clk	PLL4PFD1DIV1.
kCLOCK_Pll4Pfd1Div2Clk	PLL4PFD1DIV2.
kCLOCK_Pll4Pfd2Div1Clk	PLL4PFD2DIV1.
kCLOCK_Pll4Pfd2Div2Clk	PLL4PFD2DIV2.
kCLOCK_Pll4Pfd3Div1Clk	PLL4PFD3DIV1.
kCLOCK_Pll4Pfd3Div2Clk	PLL4PFD3DIV2.

enum _clock_ip_src

Enumerator
kCLOCK_IpSrcNone	Clock is off.
kCLOCK_Pcc0PlatIpSrcSysOscDiv1	PCC0, PCC1 Platform clock selection: kCLOCK_RtdSysOscDiv1Clk.
kCLOCK_Pcc0PlatIpSrcFroDiv1	PCC0, PCC1 Platform clock selection: kCLOCK_RtdFroDiv1Clk.
kCLOCK_Pcc0PlatIpSrcCm33Plat	PCC0, PCC1 Platform clock selection: kCLOCK_Cm33CorePlatClk.
kCLOCK_Pcc0PlatIpSrcFro	PCC0, PCC1 Platform clock selection: kCLOCK_FroClk.
kCLOCK_Pcc0PlatIpSrcPll0Pfd3	PCC0, PCC1 Platform clock selection: kCLOCK_Pll0Pfd3Clk.
kCLOCK_Pcc0BusIpSrcLpo	PCC0, PCC1 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc0BusIpSrcSysOscDiv2	PCC0, PCC1 Bus clock selection: kCLOCK_RtdSysOscDiv2Clk.
kCLOCK_Pcc0BusIpSrcFroDiv2	PCC0, PCC1 Bus clock selection: kCLOCK_RtdFroDiv2Clk.
kCLOCK_Pcc0BusIpSrcCm33Bus	PCC0, PCC1 Bus clock selection: kCLOCK_Cm33BusClk.
kCLOCK_Pcc0BusIpSrcPll1Pfd1Div	PCC0 Bus clock selection: kCLOCK_Pll1Pfd1DivClk.
kCLOCK_Pcc0BusIpSrcPll0Pfd2Div	PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd2DivClk.
kCLOCK_Pcc0BusIpSrcPll0Pfd1Div	PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd1DivClk.
kCLOCK_Pcc1PlatIpSrcSysOscDiv1	PCC0, PCC1 Platform clock selection: kCLOCK_RtdSysOscDiv1Clk.
kCLOCK_Pcc1PlatIpSrcFroDiv1	PCC0, PCC1 Platform clock selection: kCLOCK_RtdFroDiv1Clk.
kCLOCK_Pcc1PlatIpSrcCm33Plat	PCC0, PCC1 Platform clock selection: kCLOCK_Cm33CorePlatClk.
kCLOCK_Pcc1PlatIpSrcFro	PCC0, PCC1 Platform clock selection: kCLOCK_FroClk.
kCLOCK_Pcc1PlatIpSrcPll0Pfd3	PCC0, PCC1 Platform clock selection: kCLOCK_Pll0Pfd3Clk.
kCLOCK_Pcc1BusIpSrcLpo	PCC0, PCC1 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc1BusIpSrcSysOscDiv2	PCC0, PCC1 Bus clock selection: kCLOCK_RtdSysOscDiv2Clk.
kCLOCK_Pcc1BusIpSrcFroDiv2	PCC0, PCC1 Bus clock selection: kCLOCK_RtdFroDiv2Clk.
kCLOCK_Pcc1BusIpSrcCm33Bus	PCC0, PCC1 Bus clock selection: kCLOCK_Cm33BusClk.
kCLOCK_Pcc1BusIpSrcPll1VcoDiv	PCC1 Bus clock selection: kCLOCK_Pll1VcoDivClk.
kCLOCK_Pcc1BusIpSrcPll0Pfd2Div	PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd2DivClk.
kCLOCK_Pcc1BusIpSrcPll0Pfd1Div	PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd1DivClk.
kCLOCK_Pcc2BusIpSrcLpo	PCC2 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc2BusIpSrcSysOscDiv3	PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk.
kCLOCK_Pcc2BusIpSrcFroDiv3	PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk.
kCLOCK_Pcc2BusIpSrcFusionDspBus	PCC2 Bus clock selection: kCLOCK_FusionDspBusClk.
kCLOCK_Pcc2BusIpSrcPll1VcoDiv	PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk.
kCLOCK_Pcc2BusIpSrcPll0Pfd2Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk.
kCLOCK_Pcc2BusIpSrcPll0Pfd1Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk.
kCLOCK_Pcc3BusIpSrcLpo	PCC3 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc3BusIpSrcSysOscDiv2	PCC3 Bus clock selection: kCLOCK_AdSysOscDiv2Clk.
kCLOCK_Pcc3BusIpSrcFroDiv2	PCC3 Bus clock selection: kCLOCK_AdFroDiv2Clk.
kCLOCK_Pcc3BusIpSrcXbarBus	PCC3 Bus clock selection: kCLOCK_XbarBusClk.
kCLOCK_Pcc3BusIpSrcPll3Pfd1Div1	PCC3 Bus clock selection: kCLOCK_Pll3Pfd1Div1Clk.
kCLOCK_Pcc3BusIpSrcPll3Pfd0Div2	PCC3 Bus clock selection: kCLOCK_Pll3Pfd0Div2Clk.
kCLOCK_Pcc3BusIpSrcPll3Pfd0Div1	PCC3 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk.
kCLOCK_Pcc4PlatIpSrcSysOscDiv1	PCC4 Platform clock selection: kCLOCK_AdSysOscDiv1Clk.
kCLOCK_Pcc4PlatIpSrcFroDiv1	PCC4 Platform clock selection: kCLOCK_AdFroDiv1Clk.
kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div2	PCC4 Platform clock selection: kCLOCK_Pll3Pfd3Div2Clk.
kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div1	PCC4 Platform clock selection: kCLOCK_Pll3Pfd3Div1Clk.
kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div2	PCC4 Platform clock selection: kCLOCK_Pll3Pfd2Div2Clk.
kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div1	PCC4 Platform clock selection: kCLOCK_Pll3Pfd2Div1Clk.
kCLOCK_Pcc4PlatIpSrcPll3Pfd1Div2	PCC4 Platform clock selection: kCLOCK_Pll3Pfd1Div2Clk.
kCLOCK_Pcc4BusIpSrcLpo	PCC4 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc4BusIpSrcSysOscDiv2	PCC4 Bus clock selection: kCLOCK_AdSysOscDiv2Clk.
kCLOCK_Pcc4BusIpSrcFroDiv2	PCC4 Bus clock selection: kCLOCK_AdFroDiv2Clk.
kCLOCK_Pcc4BusIpSrcXbarBus	PCC4 Bus clock selection: kCLOCK_XbarBusClk.
kCLOCK_Pcc4BusIpSrcPll3VcoDiv	PCC4 Bus clock selection: kCLOCK_Pll3VcoDivClk.
kCLOCK_Pcc4BusIpSrcPll3Pfd0Div1	PCC4 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd3Div2	PCC5 Platform clock selection: kCLOCK_Pll4Pfd3Div2Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div2	PCC5 Platform clock selection: kCLOCK_Pll4Pfd2Div2Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div1	PCC5 Platform clock selection: kCLOCK_Pll4Pfd2Div1Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div2	PCC5 Platform clock selection: kCLOCK_Pll4Pfd1Div2Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div1	PCC5 Platform clock selection: kCLOCK_Pll4Pfd1Div1Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div2	PCC5 Platform clock selection: kCLOCK_Pll4Pfd0Div2Clk.
kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div1	PCC5 Platform clock selection: kCLOCK_Pll4Pfd0Div1Clk.
kCLOCK_Pcc5BusIpSrcLpo	PCC5 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_Pcc5BusIpSrcSysOscDiv2	PCC5 Bus clock selection: kCLOCK_LpavSysOscDiv2Clk.
kCLOCK_Pcc5BusIpSrcFroDiv2	PCC5 Bus clock selection: kCLOCK_LpavFroDiv2Clk.
kCLOCK_Pcc5BusIpSrcLpavBus	PCC5 Bus clock selection: kCLOCK_NicLpavBusClk.
kCLOCK_Pcc5BusIpSrcPll4VcoDiv	PCC5 Bus clock selection: kCLOCK_Pll4VcoDivClk.
kCLOCK_Pcc5BusIpSrcPll4Pfd3Div1	PCC5 Bus clock selection: kCLOCK_Pll4Pfd3Div1Clk.
kCLOCK_Cm33SaiClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_Cm33SaiClkSrcRtdAudClk	Common audio clock in RTD, see cgc_rtd_audclk_src_t.
kCLOCK_Cm33SaiClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_Cm33SaiClkSrcSysOsc	SYSOSC main reference clock to the chip: kCLOCK_SysOscClk.
kCLOCK_FusionSaiClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_FusionSaiClkSrcExtMclk1	External audio master clock input 1.
kCLOCK_FusionSaiClkSrcSai3Rx	SAI3 receiver serial bit clock. Only for SAI2.
kCLOCK_FusionSaiClkSrcSai2Tx	SAI2 transmitter serial bit clock. Only for SAI3.
kCLOCK_FusionSaiClkSrcSysOsc	SYSOSC main reference clock to the chip: kCLOCK_SysOscClk.
kCLOCK_FusionMicfilClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_FusionMicfilClkSrcFro24	FRO24: kCLOCK_FroClk/8.
kCLOCK_FusionMicfilClkSrcSysOsc	SYSOSC main reference clock to the chip: kCLOCK_SysOscClk.
kCLOCK_FusionMicfilClkSrcExtMclk1	External audio master clock input 1.
kCLOCK_FusionMicfilClkSrcRtcOsc	kCLOCK_RtcOscClk.
kCLOCK_FusionMicfilClkSrcLpo	kCLOCK_LpOscClk.
kCLOCK_FusionTpm2ClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_FusionTpm2ClkSrcExtMclk1	External audio master clock input 1.
kCLOCK_FusionTpm2ClkSrcLpo	PCC2 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_FusionTpm2ClkSrcSysOscDiv3	PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk.
kCLOCK_FusionTpm2ClkSrcFroDiv3	PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk.
kCLOCK_FusionTpm2ClkSrcFusionDspBus	PCC2 Bus clock selection: kCLOCK_FusionDspBusClk.
kCLOCK_FusionTpm2ClkSrcPll1VcoDiv	PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk.
kCLOCK_FusionTpm2ClkSrcPll0Pfd2Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk.
kCLOCK_FusionTpm2ClkSrcPll0Pfd1Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk.
kCLOCK_FusionTpm3ClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_FusionTpm3ClkSrcRtdAudClk	Common audio clock in RTD, see cgc_rtd_audclk_src_t.
kCLOCK_FusionTpm3ClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_FusionTpm3ClkSrcLpo	PCC2 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_FusionTpm3ClkSrcSysOscDiv3	PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk.
kCLOCK_FusionTpm3ClkSrcFroDiv3	PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk.
kCLOCK_FusionTpm3ClkSrcFusionDspBus	PCC2 Bus clock selection: kCLOCK_FusionDspBusClk.
kCLOCK_FusionTpm3ClkSrcPll1VcoDiv	PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk.
kCLOCK_FusionTpm3ClkSrcPll0Pfd2Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk.
kCLOCK_FusionTpm3ClkSrcPll0Pfd1Div	PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk.
kCLOCK_AdSaiClkSrcPll3Pfd1Div1	PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div2Clk.
kCLOCK_AdSaiClkSrcAdAudClk	Common audio clock in AD, see cgc_ad_audclk_src_t.
kCLOCK_AdSaiClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_AdSaiClkSrcSysOsc	SYSOSC main reference clock to the chip: kCLOCK_SysOscClk.
kCLOCK_AdTpm67ClkSrcPll3Pfd1Div1	PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div2Clk.
kCLOCK_AdTpm67ClkSrcAdAudClk	Common audio clock in AD, see cgc_ad_audclk_src_t.
kCLOCK_AdTpm67ClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_AdTpm67ClkSrcLpo	PCC4 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_AdTpm67ClkSrcSysOscDiv2	PCC4 Bus clock selection: kCLOCK_AdSysOscDiv2Clk.
kCLOCK_AdTpm67ClkSrcFroDiv2	PCC4 Bus clock selection: kCLOCK_AdFroDiv2Clk.
kCLOCK_AdTpm67ClkSrcXbarBus	PCC4 Bus clock selection: kCLOCK_XbarBusClk.
kCLOCK_AdTpm67ClkSrcPll3VcoDiv	PCC4 Bus clock selection: kCLOCK_Pll3VcoDivClk.
kCLOCK_AdTpm67ClkSrcPll3Pfd0Div1	PCC4 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk.
kCLOCK_LpavSaiClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_LpavSaiClkSrcPll3Pfd1Div1	PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div1Clk.
kCLOCK_LpavSaiClkSrcRtdAudClk	Common audio clock in RTD, see cgc_rtd_audclk_src_t.
kCLOCK_LpavSaiClkSrcAdAudClk	Common audio clock in AD, see cgc_ad_audclk_src_t.
kCLOCK_LpavSaiClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_LpavSaiClkSrcSysOsc	SYSOSC main reference clock to the chip.
kCLOCK_LpavTpm8ClkSrcPll1Pfd2Div	PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk.
kCLOCK_LpavTpm8ClkSrcPll3Pfd1Div1	PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div1Clk.
kCLOCK_LpavTpm8ClkSrcRtdAudClk	Common audio clock in RTD, see cgc_rtd_audclk_src_t.
kCLOCK_LpavTpm8ClkSrcAdAudClk	Common audio clock in AD, see cgc_ad_audclk_src_t.
kCLOCK_LpavTpm8ClkSrcLpavAudClk	Common audio clock in LPAV, see cgc_lpav_audclk_src_t.
kCLOCK_LpavTpm8ClkSrcLpo	PCC5 Bus clock selection: kCLOCK_LpOscClk.
kCLOCK_LpavTpm8ClkSrcSysOscDiv2	PCC5 Bus clock selection: kCLOCK_LpavSysOscDiv2Clk.
kCLOCK_LpavTpm8ClkSrcFroDiv2	PCC5 Bus clock selection: kCLOCK_LpavFroDiv2Clk.
kCLOCK_LpavTpm8ClkSrcLpavBus	PCC5 Bus clock selection: kCLOCK_NicLpavBusClk.
kCLOCK_LpavTpm8ClkSrcPll4VcoDiv	PCC5 Bus clock selection: kCLOCK_Pll4VcoDivClk.
kCLOCK_LpavTpm8ClkSrcPll4Pfd3Div1	PCC5 Bus clock selection: kCLOCK_Pll4Pfd3Div1Clk.

enum _clock_lptmr_src

Enumerator
kCLOCK_LptmrSrcLPO1M	LPO 1MHz clock.
kCLOCK_LptmrSrcRtc1K	RTC 1KHz clock.
kCLOCK_LptmrSrcRtc32K	RTC 32KHz clock.
kCLOCK_LptmrSrcSysOsc	system OSC clock.

enum _clock_ip_name

[31:2] is defined as the corresponding register address. [ 1:1] is used as indicator of existing of PCS. [ 0:0] is used as indicator of existing of PCD/FRAC.

anonymous enum

Enumerator
kStatus_CGC_Busy	Clock is busy.
kStatus_CGC_InvalidSrc	Invalid source.

enum _cgc_sys_clk

Enumerator
kCGC_SysClkSlow	System slow clock.
kCGC_SysClkBus	Bus clock.
kCGC_SysClkCorePlat	Core/Platform clock.
kCGC_SysClkHifi4	Hifi4 core clock.
kCGC_SysClkNicHifi	Hifi4 platform clock.
kCGC_SysClkLpavAxi	LPAV AXI clock.
kCGC_SysClkLpavAhb	LPAV AHB clock.
kCGC_SysClkLpavBus	LPAV Bus clock.

enum _cgc_rtd_sys_clk_src

Enumerator
kCGC_RtdSysClkSrcFro	FRO192.
kCGC_RtdSysClkSrcPll0Pfd0	PLL0 PFD0.
kCGC_RtdSysClkSrcPll1Pfd0	PLL1 PFD0.
kCGC_RtdSysClkSrcSysOsc	System OSC.
kCGC_RtdSysClkSrcRtcOsc	RTC OSC.
kCGC_RtdSysClkSrcLvds	LVDS XCVR.
kCGC_RtdSysClkSrcPll0	PLL0.

enum _cgc_nic_sys_clk_src

Enumerator
kCGC_NicSysClkSrcFro	FRO192.
kCGC_NicSysClkSrcPll3Pfd0	PLL0 PFD0.
kCGC_NicSysClkSrcSysOsc	System OSC.
kCGC_NicSysClkSrcLvds	LVDS XCVR.

enum _cgc_hifi_sys_clk_src

Enumerator
kCGC_HifiSysClkSrcFro	FRO192.
kCGC_HifiSysClkSrcPll4	PLL4.
kCGC_HifiSysClkSrcPll4Pfd0	PLL4 PFD0.
kCGC_HifiSysClkSrcSysOsc	System OSC.
kCGC_HifiSysClkSrcLvds	LVDS XCVR.

enum _cgc_lpav_sys_clk_src

Enumerator
kCGC_LpavSysClkSrcFro	FRO192.
kCGC_LpavSysClkSrcPll4Pfd1	PLL4 PFD1.
kCGC_LpavSysClkSrcSysOsc	System OSC.
kCGC_LpavSysClkSrcLvds	LVDS XCVR.

enum _cgc_ddr_sys_clk_src

Enumerator
kCGC_DdrSysClkSrcFro	FRO192.
kCGC_DdrSysClkSrcPll4Pfd1	PLL4 PFD1.
kCGC_DdrSysClkSrcSysOsc	System OSC.
kCGC_DdrSysClkSrcLvds	LVDS XCVR.

enum _clock_rtd_clkout_src

Enumerator
kClockRtdClkoutSelCm33Core	CGC CM33 Core/Platform clock.
kClockRtdClkoutSelCm33Bus	CGC CM33 Bus clock.
kClockRtdClkoutSelCm33Slow	CGC CM33 Slow clock.
kClockRtdClkoutSelFusionDspCore	CGC Fusion DSP Core/Platform clock.
kClockRtdClkoutSelFusionDspBus	CGC Fusion DSP Bus clock.
kClockRtdClkoutSelFusionDspSlow	CGC Fusion DSP Slow clock.
kClockRtdClkoutSelFro48	FRO48: kCLOCK_FroClk/4.
kClockRtdClkoutSelPll0VcoDiv	PLL0 VCO DIV: kCLOCK_Pll0VcoDivClk.
kClockRtdClkoutSelPll1VcoDiv	PLL1 VCO DIV: kCLOCK_Pll1VcoDivClk.
kClockRtdClkoutSelSysOsc	System OSC.
kClockRtdClkoutSelLpOsc	CGC LPOSC clock.

enum _clock_lpav_clkout_src

Enumerator
kClockLpavClkoutSelHifi4	CGC HIFI4 core clock.
kClockLpavClkoutSelNicHifi	CGC HIFI4 platform clock.
kClockLpavClkoutSelLpavAxi	CGC NIC LPAV AXI clock.
kClockLpavClkoutSelLpavAhb	CGC NIC LPAV AHB clock.
kClockLpavClkoutSelLpavBus	CGC LPAV Bus clock.
kClockLpavClkoutSelDdr	CGC DDR clock.
kClockLpavClkoutSelFro48	FRO48: kCLOCK_FroClk/4.
kClockLpavClkoutSelPll4VcoDiv	PLL4 VCO DIV: kCLOCK_Pll4VcoDivClk.
kClockLpavClkoutSelSysOsc	System OSC.
kClockLpavClkoutSelLpOsc	CGC LPOSC clock.

enum _cgc_async_clk

Enumerator
kCGC_AsyncDiv1Clk	The async clock by DIV1, e.g. SOSCDIV1_CLK, FRODIV1_CLK.
kCGC_AsyncDiv2Clk	The async clock by DIV2, e.g. SOSCDIV2_CLK, FRODIV2_CLK.
kCGC_AsyncDiv3Clk	The async clock by DIV3, e.g. SOSCDIV3_CLK, FRODIV3_CLK.
kCGC_AsyncVcoClk	The async clock by PLL VCO DIV.
kCGC_AsyncPfd0Div1Clk	The async clock by PLL PFD0 DIV1.
kCGC_AsyncPfd0Div2Clk	The async clock by PLL PFD0 DIV2.
kCGC_AsyncPfd1Div1Clk	The async clock by PLL PFD1 DIV or DIV1.
kCGC_AsyncPfd1Div2Clk	The async clock by PLL PFD1 DIV2.
kCGC_AsyncPfd2Div1Clk	The async clock by PLL PFD2 DIV or DIV1.
kCGC_AsyncPfd2Div2Clk	The async clock by PLL PFD2 DIV2.
kCGC_AsyncPfd3Div1Clk	The async clock by PLL PFD3 DIV1.
kCGC_AsyncPfd3Div2Clk	The async clock by PLL PFD3 DIV2.

enum _cgc_sosc_monitor_mode

Enumerator
kCGC_SysOscMonitorDisable	Monitor disabled.
kCGC_SysOscMonitorInt	Interrupt when the system OSC error is detected.
kCGC_SysOscMonitorReset	Reset when the system OSC error is detected.

enum _cgc_sosc_mode

Enumerator
kCGC_SysOscModeExt	Use external clock.
kCGC_SysOscModeOscLowPower	Oscillator low power.
kCGC_SysOscModeOscHighGain	Oscillator high gain.

enum _cgc_sosc_enable_mode

Enumerator
kCGC_SysOscEnableInDeepSleep	Enable OSC in deep sleep mode.
kCGC_SysOscEnableInPowerDown	Enable OSC in low power mode.

enum _cgc_fro_enable_mode

Enumerator
kCGC_FroEnableInDeepSleep	Enable FRO in deep sleep mode.

enum _cgc_lposc_enable_mode

Enumerator
kCGC_LposcEnableInDeepSleep	Enable OSC in deep sleep mode.
kCGC_LposcEnableInPowerDown	Enable OSC in low power mode.

enum _cgc_pll_src

Enumerator
kCGC_PllSrcSysOsc	PLL clock source is system OSC.
kCGC_PllSrcFro24M	PLL clock source is FRO 24M.

enum _cgc_pll_enable_mode

Enumerator
kCGC_PllEnable	Enable PLL clock.
kCGC_PllEnableInDeepSleep	Enable PLL in deep sleep mode.

enum _cgc_pll_pfd_clkout

Enumerator
kCGC_PllPfd0Clk	PFD0 output clock selected.
kCGC_PllPfd1Clk	PFD1 output clock selected.
kCGC_PllPfd2Clk	PFD2 output clock selected.
kCGC_PllPfd3Clk	PFD3 output clock selected.

enum _cgc_pll0_mult

Enumerator
kCGC_Pll0Mult15	Divide by 15.
kCGC_Pll0Mult16	Divide by 16.
kCGC_Pll0Mult20	Divide by 20.
kCGC_Pll0Mult22	Divide by 22.
kCGC_Pll0Mult25	Divide by 25.
kCGC_Pll0Mult30	Divide by 30.

enum _cgc_rosc_monitor_mode

Enumerator
kCGC_RtcOscMonitorDisable	Monitor disabled.
kCGC_RtcOscMonitorInt	Interrupt when the RTC OSC error is detected.
kCGC_RtcOscMonitorReset	Reset when the RTC OSC error is detected.

enum _cgc_pll1_mult

Enumerator
kCGC_Pll1Mult16	Divide by 16.
kCGC_Pll1Mult17	Divide by 17.
kCGC_Pll1Mult20	Divide by 20.
kCGC_Pll1Mult22	Divide by 22.
kCGC_Pll1Mult27	Divide by 27.
kCGC_Pll1Mult33	Divide by 33.

enum _cgc_pll4_mult

Enumerator
kCGC_Pll4Mult16	Divide by 16.
kCGC_Pll4Mult17	Divide by 17.
kCGC_Pll4Mult20	Divide by 20.
kCGC_Pll4Mult22	Divide by 22.
kCGC_Pll4Mult27	Divide by 27.
kCGC_Pll4Mult33	Divide by 33.

enum _cgc_rtd_audclk_src

Enumerator
kCGC_RtdAudClkSrcExtMclk0	External audio master clock input 0 from pin.
kCGC_RtdAudClkSrcExtMclk1	External audio master clock input 1 from pin.
kCGC_RtdAudClkSrcSai0RxBclk	SAI0 receiver serial bit clock.
kCGC_RtdAudClkSrcSai0TxBclk	SAI0 transmitter serial bit clock.
kCGC_RtdAudClkSrcSai1RxBclk	SAI1 receiver serial bit clock.
kCGC_RtdAudClkSrcSai1TxBclk	SAI1 transmitter serial bit clock.
kCGC_RtdAudClkSrcSai2RxBclk	SAI2 receiver serial bit clock.
kCGC_RtdAudClkSrcSai2TxBclk	SAI2 transmitter serial bit clock.
kCGC_RtdAudClkSrcSai3RxBclk	SAI3 receiver serial bit clock.
kCGC_RtdAudClkSrcSai3TxBclk	SAI3 transmitter serial bit clock.

enum _cgc_ad_audclk_src

Enumerator
kCGC_AdAudClkSrcExtMclk2	External audio master clock input 2 from pin.
kCGC_AdAudClkSrcSai4RxBclk	SAI4 receiver serial bit clock.
kCGC_AdAudClkSrcSai4TxBclk	SAI4 transmitter serial bit clock.
kCGC_AdAudClkSrcSai5RxBclk	SAI5 receiver serial bit clock.
kCGC_AdAudClkSrcSai5TxBclk	SAI5 transmitter serial bit clock.

enum _cgc_lpav_audclk_src

Enumerator
kCGC_LpavAudClkSrcExtMclk3	External audio master clock input 3 from pin.
kCGC_LpavAudClkSrcSai6RxBclk	SAI6 receiver serial bit clock.
kCGC_LpavAudClkSrcSai6TxBclk	SAI6 transmitter serial bit clock.
kCGC_LpavAudClkSrcSai7RxBclk	SAI7 receiver serial bit clock.
kCGC_LpavAudClkSrcSai7TxBclk	SAI7 transmitter serial bit clock.
kCGC_LpavAudClkSrcSpdifRx	SPDIF receiver clock.

Function Documentation

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

static bool CLOCK_IsEnabledByOtherCore ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which peripheral to check, see clock_ip_name_t.

Returns: True if clock is already enabled, otherwise false.

void CLOCK_SetIpSrc	(	clock_ip_name_t	name,
		clock_ip_src_t	src
	)

Set the clock source for specific IP, not all modules need to set the clock source, should only use this function for the modules need source setting.

Parameters

name	Which peripheral to check, see clock_ip_name_t.
src	Clock source to set.

void CLOCK_SetIpSrcDiv	(	clock_ip_name_t	name,
		clock_ip_src_t	src,
		uint8_t	divValue,
		uint8_t	fracValue
	)

Set the clock source and divider for specific IP, not all modules need to set the clock source and divider, should only use this function for the modules need source and divider setting.

Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]).

Parameters

name	Which peripheral to check, see clock_ip_name_t.
src	Clock source to set.
divValue	The divider value.
fracValue	The fraction multiply value.

static void CLOCK_SetRtdAudClkSrc ( cgc_rtd_audclk_src_t src )

inlinestatic

NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK frequencies if other modules use the AUD_CLK0 source and need to get correct frequency.

Parameters

src	Clock source to set.

static void CLOCK_SetAdAudClkSrc ( cgc_ad_audclk_src_t src )

inlinestatic

NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK frequencies if other modules use the AUD_CLK1 source and need to get correct frequency.

Parameters

src	Clock source to set.

static void CLOCK_SetLpavAudClkSrc ( cgc_lpav_audclk_src_t src )

inlinestatic

NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK frequencies if other modules use the AUD_CLK2 source and need to get correct frequency.

Parameters

src	Clock source to set.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCm33CorePlatClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetCm33BusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetCm33SlowClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFusionDspCorePlatClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFusionDspBusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFusionDspSlowClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetLvdsClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetIpFreq ( clock_ip_name_t name )

This function gets the IP module clock frequency. It is only used for the IP modules which could select clock source by CLOCK_SetIpSrc().

Parameters

name	Which peripheral to get, see clock_ip_name_t.

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCm33SysClkFreq ( cgc_sys_clk_t type )

This function gets the CGC CM33 system clock frequency. These clocks are used for core, platform, bus and slow clock domains.

Parameters

type	Which type of clock to get.

Returns: Clock frequency.

static void CLOCK_SetCm33SysClkConfig ( cgc_rtd_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for CM33 domain.

Parameters

config Pointer to the configuration.

uint32_t CLOCK_GetFusionDspSysClkFreq ( cgc_sys_clk_t type )

This function gets the CGC Fusion DSP system clock frequency. These clocks are used for core, platform, bus and slow clock domains.

Parameters

type	Which type of clock to get.

Returns: Clock frequency.

static void CLOCK_SetFusionSysClkConfig ( const cgc_rtd_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for FusionF1 DSP domain.

Parameters

config Pointer to the configuration.

static void CLOCK_GetCm33SysClkConfig ( cgc_rtd_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration for CM33 domain.

Parameters

config Pointer to the configuration.

static void CLOCK_GetFusionDspSysClkConfig ( cgc_rtd_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration for FusionF1 DSP domain.

Parameters

config Pointer to the configuration.

static void CLOCK_SetRtdClkOutConfig	(	clock_rtd_clkout_src_t	setting,
		uint8_t	div,
		bool	enable
	)

inlinestatic

This function sets the clock out configuration.

Parameters

setting	The selection to set.
div	The divider to set (div > 0).
enable	Enable clock out.

static void CLOCK_SetRtcClkOutConfig ( uint8_t div )

inlinestatic

This function sets the RTC_CLOCKOUT configuration.

Parameters

div	The divider to set (div > 0).

uint32_t CLOCK_GetXbarBusClkFreq ( void )

This function gets the CGC XBAR bus clock frequency.

Returns: Clock frequency.

uint32_t CLOCK_GetHifiDspSysClkFreq ( cgc_sys_clk_t type )

This function gets the CGC HIFI DSP system clock frequency. These clocks are used for core, platform domains.

Parameters

type	Which type of clock to get.

Returns: Clock frequency.

static void CLOCK_SetHifiDspSysClkConfig ( const cgc_hifi_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for HIFI4 DSP domain.

Parameters

config Pointer to the configuration.

static void CLOCK_GetHifiDspSysClkConfig ( cgc_hifi_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration for HIFI4 DSP domain.

Parameters

config Pointer to the configuration.

uint32_t CLOCK_GetLpavSysClkFreq ( cgc_sys_clk_t type )

This function gets the CGC NIC LPAV system clock frequency. These clocks are used for AXI, AHB, Bus domains.

Parameters

type	Which type of clock to get.

Returns: Clock frequency.

static void CLOCK_SetLpavSysClkConfig ( const cgc_lpav_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for NIC LPAV domain.

Parameters

config Pointer to the configuration.

static void CLOCK_GetLpavSysClkConfig ( cgc_lpav_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration for NIC LPAV domain.

Parameters

config Pointer to the configuration.

uint32_t CLOCK_GetDdrClkFreq ( void )

This function gets the CGC DDR clock frequency.

Returns: Clock frequency.

static void CLOCK_SetLpavClkOutConfig	(	clock_lpav_clkout_src_t	setting,
		uint8_t	div,
		bool	enable
	)

inlinestatic

This function sets the clock out configuration.

Parameters

setting	The selection to set.
div	The divider to set (div > 0).
enable	Enable clock out.

status_t CLOCK_InitSysOsc ( const cgc_sosc_config_t * config )

This function enables the CGC system OSC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	System OSC is initialized.
kStatus_CGC_Busy	System OSC has been enabled and is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note: This function can't detect whether the system OSC has been enabled and used by an IP.

status_t CLOCK_DeinitSysOsc ( void )

This function disables the CGC system OSC clock.

Return values

kStatus_Success	System OSC is deinitialized.
kStatus_CGC_Busy	System OSC is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note: This function can't detect whether the system OSC is used by an IP.

void CLOCK_SetRtdSysOscAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

void CLOCK_SetAdSysOscAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

void CLOCK_SetLpavSysOscAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetSysOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtdSysOscAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAdSysOscAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpavSysOscAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsSysOscErr ( void )

inlinestatic

Returns: True if the error occurs, false if not.

static void CLOCK_SetSysOscMonitorMode ( cgc_sosc_monitor_mode_t mode )

inlinestatic

This function sets the system OSC monitor mode. The mode can be disabled, it can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

static bool CLOCK_IsSysOscSelected ( void )

inlinestatic

Returns: True if system OSC is used as clock source, false if not.

static bool CLOCK_IsSysOscValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

status_t CLOCK_InitFro ( const cgc_fro_config_t * config )

This function initializes the CGC FRO clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	FRO is initialized.
kStatus_CGC_Busy	FRO has been enabled and is used by system clock.
kStatus_ReadOnly	FRO control register is locked.

Note: This function can't detect whether the FRO has been enabled and used by an IP.

status_t CLOCK_DeinitFro ( void )

This function deinitializes the CGC FRO.

Return values

kStatus_Success	FRO is deinitialized.
kStatus_CGC_Busy	FRO is used by system clock.
kStatus_ReadOnly	FRO control register is locked.

Note: This function can't detect whether the FRO is used by an IP.

void CLOCK_SetRtdFroAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

void CLOCK_SetAdFroAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

void CLOCK_SetLpavFroAsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

void CLOCK_EnableFroTuning ( bool enable )

On enable, the function will wait until FRO is close to the target frequency.

uint32_t CLOCK_GetFroFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtdFroAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAdFroAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpavFroAsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsFroSelected ( void )

inlinestatic

Returns: True if FRO is used as clock source, false if not.

static bool CLOCK_IsFroValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

status_t CLOCK_InitLposc ( const cgc_lposc_config_t * config )

This function initializes the CGC LPOSC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	LPOSC is initialized.
kStatus_ReadOnly	FRO control register is locked.

Note: This function can't detect whether the LPOSC has been enabled and used by an IP.

status_t CLOCK_DeinitLposc ( void )

This function deinitializes the CGC LPOSC.

Return values

kStatus_Success	LPOSC is deinitialized.
kStatus_ReadOnly	LPOSC control register is locked.

Note: This function can't detect whether the LPOSC is used by an IP.

static bool CLOCK_IsLpOscValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

uint32_t CLOCK_GetLpOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtcOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsRtcOscErr ( void )

inlinestatic

Returns: True if error occurs, false if not.

void CLOCK_SetRtcOscMonitorMode ( cgc_rosc_monitor_mode_t mode )

This function sets the RTC OSC monitor mode. The mode can be disabled. It can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

static bool CLOCK_IsRtcOscSelected ( void )

inlinestatic

Returns: True if RTCOSC is used as clock source, false if not.

static bool CLOCK_IsRtcOscValid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

status_t CLOCK_InitPll0 ( const cgc_pll0_config_t * config )

This function enables the CGC PLL0 clock according to the configuration. The PLL0 can use the OSC or FRO as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing PLL0 clock output:

* const cgc_pll0_config_t g_cgcPll0Config = {.enableMode = kCGC_PllEnable,
*                                            .div1 = 1U,
*                                            .pfd1Div = 2U,
*                                            .pfd2Div = 0U,
*                                            .src = kCGC_PllSrcSysOsc,
*                                            .mult = kCGC_Pll0Mult20};
* CLOCK_InitPll0(&g_cgcPll0Config);
* 

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	PLL0 is initialized.
kStatus_CGC_Busy	PLL0 has been enabled and is used by the system clock.
kStatus_ReadOnly	PLL0 control register is locked.

Note: This function can't detect whether the PLL0 has been enabled and used by an IP.

status_t CLOCK_DeinitPll0 ( void )

This function disables the CGC PLL0.

Return values

kStatus_Success	PLL0 is deinitialized.
kStatus_CGC_Busy	PLL0 is used by the system clock.
kStatus_ReadOnly	PLL0 control register is locked.

Note: This function can't detect whether the PLL0 is used by an IP.

void CLOCK_SetPll0AsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetPll0Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll0AsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll0PfdFreq ( cgc_pll_pfd_clkout_t pfdClkout )

Parameters

pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".

Returns: Clock frequency; If the clock is invalid, returns 0.

void CLOCK_EnablePll0PfdClkout	(	cgc_pll_pfd_clkout_t	pfdClkout,
		uint8_t	fracValue
	)

PLL Frequency = Fref * MULT PFD Clock Frequency = PLL output frequency * 18/frac value

* Example code for configuring PLL0 PFD0 clock output:
* const cgc_pll0_config_t g_cgcPll0Config = {.enableMode = kCGC_PllEnable,
*                                           .div1 = 1U,
*                                           .pfd1Div = 2U,
*                                           .pfd2Div = 0U,
*                                           .src = kCGC_PllSrcSysOsc,
*                                           .mult = kCGC_Pll0Mult20};
* CLOCK_InitPll0(&g_cgcPll0Config);
* CLOCK_EnablePll0PfdClkout(kCGC_PllPfd0Clk, 15U);
* 

Parameters

pfdClkout	PLL0 PFD clock out select.
fracValue	Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.

static void CLOCK_SetPll0LockTime ( uint16_t lockTime )

inlinestatic

Parameters

lockTime Reference clocks to count before PLL0 is considered locked and valid.

static bool CLOCK_IsPll0Selected ( void )

inlinestatic

Returns: True if PLL0 is used as clock source, false if not.

static bool CLOCK_IsPll0Valid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

status_t CLOCK_InitPll1 ( const cgc_pll1_config_t * config )

This function enables the CGC PLL1 clock according to the configuration. The PLL1 can use the system OSC or FRO as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing PLL1 clock output:

* const cgc_pll1_config_t g_cgcPll1Config = {.enableMode = kCGC_PllEnable,
*                                            .div1 = 0U,
*                                            .pfd1Div = 0U,
*                                            .pfd2Div = 0U,
*                                            .src = kCGC_PllSrcFro24M,
*                                            .mult = kCGC_Pll1Mult22,
*                                            .num = 578,
*                                            .denom = 1000};
* CLOCK_InitPll1(&g_cgcPll1Config);
* 

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	PLL1 is initialized.
kStatus_CGC_Busy	PLL1 has been enabled and is used by the system clock.
kStatus_ReadOnly	PLL1 control register is locked.

Note: This function can't detect whether the PLL1 has been enabled and is used by an IP.

status_t CLOCK_DeinitPll1 ( void )

This function disables the CGC PLL1.

Return values

kStatus_Success	PLL1 is deinitialized.
kStatus_CGC_Busy	PLL1 is used by the system clock.
kStatus_ReadOnly	PLL1 control register is locked.

Note: This function can't detect whether the PLL1 is used by an IP.

void CLOCK_SetPll1AsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetPll1Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll1AsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll1PfdFreq ( cgc_pll_pfd_clkout_t pfdClkout )

Parameters

pfdClkout The selected PFD clocks out. See "cgc_pll_pfd_clkout_t".

Returns: Clock frequency; If the clock is invalid, returns 0.

void CLOCK_EnablePll1PfdClkout	(	cgc_pll_pfd_clkout_t	pfdClkout,
		uint8_t	fracValue
	)

PLL1 Frequency = Fref * (MULT + NUM/DENOM) PFD Clock Frequency = PLL output frequency * 18/frac value

Example code for configuring PLL1 as PLL1 PFD clock output:

* const cgc_pll1_config_t g_cgcPll1Config = {.enableMode = kCGC_PllEnable,
*                                            .div1 = 0U,
*                                            .pfd1Div = 0U,
*                                            .pfd2Div = 0U,
*                                            .src = kCGC_PllSrcFro24M,
*                                            .mult = kCGC_Pll1Mult22,
*                                            .num = 578,
*                                            .denom = 1000};
* CLOCK_InitPll1(&g_cgcPll1Config);
* CLOCK_EnablePll1PfdClkout(kCGC_PllPfd0Clk, 15U);
* 

Parameters

pfdClkout	PLL1 PFD clock out select.
fracValue	Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.

static void CLOCK_EnablePll1SpectrumModulation	(	uint16_t	step,
		uint16_t	stop
	)

inlinestatic

This function sets the CGC PLL1 spread spectrum modulation configurations. STOP and STEP together control the modulation depth (maximum frequency change) and modulation frequency.

Modulation Depth = (STOP/MFD)*Fref where MFD is the DENOM field value in DENOM register. Modulation Frequency = (STEP/(2*STOP))*Fref.

Parameters

step	PLL1 Spread Spectrum STEP.
stop	PLL1 Spread Spectrum STOP.

static void CLOCK_SetPll1LockTime ( uint16_t lockTime )

inlinestatic

Parameters

lockTime Reference clocks to count before PLL1 is considered locked and valid.

static bool CLOCK_IsPll1Selected ( void )

inlinestatic

Returns: True if PLL1 is used as clock source, false if not.

static bool CLOCK_IsPll1Valid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

uint32_t CLOCK_GetPll3Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll3AsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll3PfdFreq ( cgc_pll_pfd_clkout_t pfdClkout )

Parameters

pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".

Returns: Clock frequency; If the clock is invalid, returns 0.

status_t CLOCK_InitPll4 ( const cgc_pll4_config_t * config )

This function enables the CGC PLL4 clock according to the configuration. The PLL4 can use the OSC or FRO as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing PLL4 clock output:

* const cgc_pll4_config_t g_cgcPll4Config = {.enableMode = kCGC_PllEnable,
*                                            .div1 = 0U,
*                                            .pfd0Div1 = 0U,
*                                            .pfd0Div2 = 0U,
*                                            .pfd1Div1 = 0U,
*                                            .pfd1Div2 = 0U,
*                                            .pfd2Div1 = 0U,
*                                            .pfd2Div2 = 0U,
*                                            .pfd3Div1 = 0U,
*                                            .pfd3Div2 = 0U,
*                                            .src = kCGC_PllSrcFro24M,
*                                            .mult = kCGC_Pll4Mult22,
*                                            .num = 578,
*                                            .denom = 1000};
* CLOCK_InitPll4(&g_cgcPll4Config);
* 

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	PLL4 is initialized.
kStatus_CGC_Busy	PLL4 has been enabled and is used by the system clock.
kStatus_ReadOnly	PLL4 control register is locked.

Note: This function can't detect whether the PLL4 has been enabled and used by an IP.

status_t CLOCK_DeinitPll4 ( void )

This function disables the CGC PLL4.

Return values

kStatus_Success	PLL4 is deinitialized.
kStatus_CGC_Busy	PLL4 is used by the system clock.
kStatus_ReadOnly	PLL4 control register is locked.

Note: This function can't detect whether the PLL4 is used by an IP.

void CLOCK_SetPll4AsyncClkDiv	(	cgc_async_clk_t	asyncClk,
		uint8_t	divider
	)

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set. Disabled when divider == 0.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetPll4Freq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll4AsyncFreq ( cgc_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetPll4PfdFreq ( cgc_pll_pfd_clkout_t pfdClkout )

Parameters

pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".

Returns: Clock frequency; If the clock is invalid, returns 0.

void CLOCK_EnablePll4PfdClkout	(	cgc_pll_pfd_clkout_t	pfdClkout,
		uint8_t	fracValue
	)

PLL Frequency = Fref * MULT PFD Clock Frequency = PLL output frequency * 18/frac value

* Example code for configuring PLL4 PFD0 clock output:
* const cgc_pll4_config_t g_cgcPll4Config = {.enableMode = kCGC_PllEnable,
*                                            .div1 = 0U,
*                                            .pfd0Div1 = 0U,
*                                            .pfd0Div2 = 0U,
*                                            .pfd1Div1 = 0U,
*                                            .pfd1Div2 = 0U,
*                                            .pfd2Div1 = 0U,
*                                            .pfd2Div2 = 0U,
*                                            .pfd3Div1 = 0U,
*                                            .pfd3Div2 = 0U,
*                                            .src = kCGC_PllSrcFro24M,
*                                            .mult = kCGC_Pll4Mult22,
*                                            .num = 578,
*                                            .denom = 1000};
* CLOCK_InitPll4(&g_cgcPll4Config);
* CLOCK_EnablePll4PfdClkout(kCGC_PllPfd0Clk, 15U);
* 

Parameters

pfdClkout	PLL4 PFD clock out select.
fracValue	Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.

static void CLOCK_EnablePll4SpectrumModulation	(	uint16_t	step,
		uint16_t	stop
	)

inlinestatic

This function sets the CGC PLL4 spread spectrum modulation configurations. STOP and STEP together control the modulation depth (maximum frequency change) and modulation frequency.

Modulation Depth = (STOP/MFD)*Fref where MFD is the DENOM field value in DENOM register. Modulation Frequency = (STEP/(2*STOP))*Fref.

Parameters

step	PLL4 Spread Spectrum STEP.
stop	PLL4 Spread Spectrum STOP.

static void CLOCK_SetPll4LockTime ( uint16_t lockTime )

inlinestatic

Parameters

lockTime Reference clocks to count before PLL4 is considered locked and valid.

static bool CLOCK_IsPll4Selected ( void )

inlinestatic

Returns: True if PLL4 is used as clock source, false if not.

static bool CLOCK_IsPll4Valid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

static void CLOCK_SetXtal0Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL0/EXTAL0 input clock frequency in Hz.

static void CLOCK_SetXtal32Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL32/EXTAL32 input clock frequency in Hz.

static void CLOCK_SetLvdsFreq ( uint32_t freq )

inlinestatic

Parameters

freq	The LVDS pad input clock frequency in Hz.

static void CLOCK_SetMclkFreq	(	uint32_t	index,
		uint32_t	freq
	)

inlinestatic

Parameters

index	The MCLK index.
freq	The MCLK pad input clock frequency in Hz.

static void CLOCK_SetRxBclkFreq	(	uint32_t	instance,
		uint32_t	freq
	)

inlinestatic

Parameters

instance	The SAI instance to contribute to this RX_BCLK pad.
freq	The RX_BCLK pad input clock frequency in Hz.

static void CLOCK_SetTxBclkFreq	(	uint32_t	instance,
		uint32_t	freq
	)

inlinestatic

Parameters

instance	The SAI instance to contribute to this TX_BCLK pad.
freq	The TX_BCLK pad input clock frequency in Hz.

static void CLOCK_SetSpdifRxFreq ( uint32_t freq )

inlinestatic

Parameters

freq	The SPDIF_RX input clock frequency in Hz.

uint32_t CLOCK_GetWdogClkFreq ( uint32_t instance )

Parameters

instance The WDOG instance (0-2,5).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFlexspiClkFreq ( uint32_t instance )

Parameters

instance The FlexSPI instance (0-1).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpitClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFlexioClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetI3cClkFreq ( uint32_t instance )

Parameters

instance The I3C instance (0-1).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpspiClkFreq ( uint32_t instance )

Parameters

instance The LPSPI instance (0-3).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAdcClkFreq ( uint32_t instance )

Parameters

instance The ADC instance (0-1).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetDacClkFreq ( uint32_t instance )

Parameters

instance The DAC instance (0-1).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetTpiuClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSwoClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetTpmClkFreq ( uint32_t instance )

Parameters

instance The TPM instance (0-8).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpi2cClkFreq ( uint32_t instance )

Parameters

instance The LPI2C instance (0-3).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpuartClkFreq ( uint32_t instance )

Parameters

instance The LPUART instance (0-3).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFlexcanClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetCsiClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetDsiClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetEpdcClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetGpu2dClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetGpu3dClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetDcnanoClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetCsiUiClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetCsiEscClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtdAudClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAdAudClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetLpavAudClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSaiFreq ( uint32_t instance )

Parameters

instance The SAI instance (0-7).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSpdifFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetMqsFreq ( uint32_t instance )

Parameters

instance The MQS instance (0-1).

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetMicfilFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetMrtFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtdSysClkFreq	(	uint32_t	config,
		cgc_sys_clk_t	type
	)

This function gets the CGC system clock frequency. These clocks are used for core, platform, bus and slow clock domains.

Parameters

config	Config value from CGC register.
type	Which type of clock to get.

Returns: Clock frequency.

Variable Documentation

volatile uint32_t g_xtal0Freq

The XTAL (SYSOSC) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtalFreq to set the value in the clock driver. For example, if XTAL is 24 MHz:

* CLOCK_InitSysOsc(...);
* CLOCK_SetXtalFreq(24000000);
* 

This is important for the multicore platforms where only one core needs to set up the OSC/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtalFreq to get a valid clock frequency.

volatile uint32_t g_xtal32Freq

The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.

volatile uint32_t g_lvdsFreq

The LVDS pad clock frequency in Hz. When the clock is set up, use the function CLOCK_SetLvdsFreq to set the value in the clock driver.

volatile uint32_t g_mclkFreq[4]

The MCLK pad clock frequency in Hz. When the clock is set up, use the function CLOCK_SetMclkFreq to set the value in the clock driver.

volatile uint32_t g_rxBclkFreq[8]

The RX_BCLK pad clock frequency in Hz. When the clock is set up, use the function CLOCK_SetRxBclkFreq to set the value in the clock driver.

volatile uint32_t g_txBclkFreq[8]

The TX_BCLK pad clock frequency in Hz. When the clock is set up, use the function CLOCK_SetTxBclkFreq to set the value in the clock driver.

volatile uint32_t g_spdifRxFreq

The SPDIF_RX clock frequency in Hz. When the clock is sampled, use the function CLOCK_SetSpdifRxFreq to set the value in the clock driver.

Overview

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Driver version

MCU System Clock.

CGC System OSC Clock.

CGC FRO Clock.

CGC LPOSC Clock.

CGC RTCOSC Clock.

CGC PLL0 Clock.

CGC PLL1 Clock.

CGC PLL3 Clock.

CGC PLL4 Clock.

External clock frequency

Get peripheral frequency

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