Clock Driver

Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

• Clock generator (PLL, FLL, and so on) configuration
• Clock mux and divider configuration
• Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	_pll_config
	PLL configuration structure. More...
struct	_pll_setup
	PLL setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...

Macros
#define	CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT   2U
	User-defined the size of cache for CLOCK_PllGetConfig() function. More...
#define	FLEXCOMM_CLOCKS
	Clock ip name array for FLEXCOMM. More...
#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...
#define	BI2C_CLOCKS
	Clock ip name array for BI2C. More...
#define	LPSI_CLOCKS
	Clock ip name array for LSPI. More...
#define	FLEXI2S_CLOCKS
	Clock ip name array for FLEXI2S. More...
#define	UTICK_CLOCKS
	Clock ip name array for UTICK. More...
#define	DMA_CLOCKS
	Clock ip name array for DMA. More...
#define	CTIMER_CLOCKS
	Clock ip name array for CT32B. More...
#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...
#define	ADC_CLOCKS
	Clock ip name array for ADC. More...
#define	MRT_CLOCKS
	Clock ip name array for MRT. More...
#define	SCT_CLOCKS
	Clock ip name array for MRT. More...
#define	RTC_CLOCKS
	Clock ip name array for RTC. More...
#define	WWDT_CLOCKS
	Clock ip name array for WWDT. More...
#define	CRC_CLOCKS
	Clock ip name array for CRC. More...
#define	USBD_CLOCKS
	Clock ip name array for USBD. More...
#define	GINT_CLOCKS
	Clock ip name array for GINT. More...
#define	CLK_GATE_REG_OFFSET_SHIFT   8U
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
#define	CLK_ATTACH_ID(mux, sel, pos)   ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
	Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards. More...
#define	PLL_CONFIGFLAG_USEINRATE   (1U << 0U)
	PLL configuration structure flags for 'flags' field These flags control how the PLL configuration function sets up the PLL setup structure. More...
#define	PLL_CONFIGFLAG_FORCENOFRACT   (1U << 2U)
	Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \ SS hardware.
#define	PLL_SETUPFLAG_POWERUP   (1U << 0U)
	PLL setup structure flags for 'flags' field These flags control how the PLL setup function sets up the PLL. More...
#define	PLL_SETUPFLAG_WAITLOCK   (1U << 1U)
	Setup will wait for PLL lock, implies the PLL will be pwoered on.
#define	PLL_SETUPFLAG_ADGVOLT   (1U << 2U)
	Optimize system voltage for the new PLL rate.
#define	PLL_SETUPFLAG_USEFEEDBACKDIV2   (1U << 3U)
	Use feedback divider by 2 in divider path.

Typedefs
typedef enum _clock_ip_name	clock_ip_name_t
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...
typedef enum _async_clock_src	async_clock_src_t
	Clock source selections for the asynchronous APB clock.
typedef enum _clock_attach_id	clock_attach_id_t
	The enumerator of clock attach Id.
typedef enum _clock_div_name	clock_div_name_t
	Clock dividers. More...
typedef enum _clock_flashtim	clock_flashtim_t
	FLASH Access time definitions.
typedef enum _ss_progmodfm	ss_progmodfm_t
	PLL Spread Spectrum (SS) Programmable modulation frequency See (MF) field in the SYSPLLSSCTRL1 register in the UM.
typedef enum _ss_progmoddp	ss_progmoddp_t
	PLL Spread Spectrum (SS) Programmable frequency modulation depth See (MR) field in the SYSPLLSSCTRL1 register in the UM.
typedef enum _ss_modwvctrl	ss_modwvctrl_t
	PLL Spread Spectrum (SS) Modulation waveform control See (MC) field in the SYSPLLSSCTRL1 register in the UM. More...
typedef struct _pll_config	pll_config_t
	PLL configuration structure. More...
typedef struct _pll_setup	pll_setup_t
	PLL setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...
typedef enum _pll_error	pll_error_t
	PLL status definitions.
typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...

Enumerations
enum	_clock_ip_name {   kCLOCK_IpInvalid = 0U,   kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),   kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),   kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),   kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),   kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),   kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),   kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),   kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),   kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),   kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),   kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),   kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),   kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),   kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),   kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),   kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),   kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),   kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),   kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),   kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),   kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),   kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),   kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),   kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),   kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),   kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),   kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),   kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),   kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),   kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),   kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),   kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),   kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),   kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),   kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),   kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),   kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),   kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),   kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),   kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),   kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),   kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),   kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),   kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),   kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),   kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),   kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),   kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),   kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),   kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),   kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),   kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),   kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),   kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),   kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),   kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),   kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),   kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),   kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),   kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),   kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),   kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13) }
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
enum	_clock_name {   kCLOCK_CoreSysClk,   kCLOCK_BusClk,   kCLOCK_ClockOut,   kCLOCK_FroHf,   kCLOCK_Fro12M,   kCLOCK_ExtClk,   kCLOCK_PllOut,   kCLOCK_WdtOsc,   kCLOCK_Frg,   kCLOCK_AsyncApbClk,   kCLOCK_FlexI2S }
	Clock name used to get clock frequency. More...
enum	_async_clock_src {   kCLOCK_AsyncMainClk = 0,   kCLOCK_AsyncFro12Mhz }
	Clock source selections for the asynchronous APB clock. More...
enum	_clock_attach_id {   kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),   kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),   kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),   kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),   kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),   kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),   kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),   kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),   kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),   kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),   kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),   kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),   kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),   kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),   kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),   kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),   kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),   kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),   kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),   kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),   kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),   kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),   kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),   kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),   kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),   kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),   kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),   kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),   kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),   kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),   kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),   kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),   kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),   kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),   kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),   kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),   kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),   kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),   kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),   kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),   kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),   kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),   kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),   kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),   kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),   kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),   kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),   kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),   kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),   kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),   kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),   kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),   kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),   kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),   kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),   kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),   kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),   kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),   kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),   kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),   kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),   kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),   kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),   kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),   kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),   kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),   kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),   kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),   kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),   kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),   kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),   kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),   kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2),   kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),   kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),   kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),   kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2),   kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),   kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),   kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),   kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),   kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),   kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),   kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),   kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),   kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),   kNONE_to_NONE = (int)0x80000000U }
	The enumerator of clock attach Id. More...
enum	_clock_div_name {   kCLOCK_DivSystickClk = 0,   kCLOCK_DivTraceClk = 1,   kCLOCK_DivAhbClk = 32,   kCLOCK_DivClkOut = 33,   kCLOCK_DivAdcAsyncClk = 37,   kCLOCK_DivUsbClk = 38,   kCLOCK_DivFrg = 40,   kCLOCK_DivFxI2s0MClk = 43 }
	Clock dividers. More...
enum	_clock_flashtim {   kCLOCK_Flash1Cycle = 0,   kCLOCK_Flash2Cycle,   kCLOCK_Flash3Cycle,   kCLOCK_Flash4Cycle,   kCLOCK_Flash5Cycle,   kCLOCK_Flash6Cycle,   kCLOCK_Flash7Cycle }
	FLASH Access time definitions. More...
enum	_ss_progmodfm {   kSS_MF_512 = (0 << 20),   kSS_MF_384 = (1 << 20),   kSS_MF_256 = (2 << 20),   kSS_MF_128 = (3 << 20),   kSS_MF_64 = (4 << 20),   kSS_MF_32 = (5 << 20),   kSS_MF_24 = (6 << 20),   kSS_MF_16 = (7 << 20) }
	PLL Spread Spectrum (SS) Programmable modulation frequency See (MF) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	_ss_progmoddp {   kSS_MR_K0 = (0 << 23),   kSS_MR_K1 = (1 << 23),   kSS_MR_K1_5 = (2 << 23),   kSS_MR_K2 = (3 << 23),   kSS_MR_K3 = (4 << 23),   kSS_MR_K4 = (5 << 23),   kSS_MR_K6 = (6 << 23),   kSS_MR_K8 = (7 << 23) }
	PLL Spread Spectrum (SS) Programmable frequency modulation depth See (MR) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	_ss_modwvctrl {   kSS_MC_NOC = (0 << 26),   kSS_MC_RECC = (2 << 26),   kSS_MC_MAXC = (3 << 26) }
	PLL Spread Spectrum (SS) Modulation waveform control See (MC) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	_pll_error {   kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),   kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),   kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),   kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),   kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),   kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) }
	PLL status definitions. More...
enum	_clock_usb_src {   kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,   kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,   kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk,   kCLOCK_UsbSrcNone }
	USB clock source definition. More...

Functions
static void	CLOCK_SetFLASHAccessCycles (clock_flashtim_t clks)
	Set FLASH memory access time in clocks. More...
status_t	CLOCK_SetupFROClocking (uint32_t iFreq)
	Initialize the Core clock to given frequency (12, 48 or 96 MHz). Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is enabled. More...
void	CLOCK_AttachClk (clock_attach_id_t connection)
	Configure the clock selection muxes. More...
clock_attach_id_t	CLOCK_GetClockAttachId (clock_attach_id_t attachId)
	Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id. More...
void	CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
	Setup peripheral clock dividers. More...
void	CLOCK_SetFLASHAccessCyclesForFreq (uint32_t iFreq)
	Set the flash wait states for the input freuqency. More...
uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Return Frequency of selected clock. More...
uint32_t	CLOCK_GetFRGInputClock (void)
	Return Input frequency for the Fractional baud rate generator. More...
uint32_t	CLOCK_SetFRGClock (uint32_t freq)
	Set output of the Fractional baud rate generator. More...
uint32_t	CLOCK_GetFro12MFreq (void)
	Return Frequency of FRO 12MHz. More...
uint32_t	CLOCK_GetExtClkFreq (void)
	Return Frequency of External Clock. More...
uint32_t	CLOCK_GetWdtOscFreq (void)
	Return Frequency of Watchdog Oscillator. More...
uint32_t	CLOCK_GetFroHfFreq (void)
	Return Frequency of High-Freq output of FRO. More...
uint32_t	CLOCK_GetPllOutFreq (void)
	Return Frequency of PLL. More...
uint32_t	CLOCK_GetOsc32KFreq (void)
	Return Frequency of 32kHz osc. More...
uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Return Frequency of Core System. More...
uint32_t	CLOCK_GetI2SMClkFreq (void)
	Return Frequency of I2S MCLK Clock. More...
uint32_t	CLOCK_GetFlexCommClkFreq (uint32_t id)
	Return Frequency of Flexcomm functional Clock. More...
uint32_t	CLOCK_GetUsbClkFreq (void)
	brief Return Frequency of Usb Clock return Frequency of Usb Clock.
uint32_t	CLOCK_GetAdcClkFreq (void)
	Return Frequency of Adc Clock. More...
uint32_t	CLOCK_GetClockOutClkFreq (void)
	Return Frequency of ClockOut. More...
__STATIC_INLINE async_clock_src_t	CLOCK_GetAsyncApbClkSrc (void)
	Return Asynchronous APB Clock source. More...
uint32_t	CLOCK_GetAsyncApbClkFreq (void)
	Return Frequency of Asynchronous APB Clock. More...
uint32_t	CLOCK_GetSystemPLLInClockRate (void)
	Return System PLL input clock rate. More...
uint32_t	CLOCK_GetSystemPLLOutClockRate (bool recompute)
	Return System PLL output clock rate. More...
__STATIC_INLINE void	CLOCK_SetBypassPLL (bool bypass)
	Enables and disables PLL bypass mode. More...
__STATIC_INLINE bool	CLOCK_IsSystemPLLLocked (void)
	Check if PLL is locked or not. More...
void	CLOCK_SetStoredPLLClockRate (uint32_t rate)
	Store the current PLL rate. More...
uint32_t	CLOCK_GetSystemPLLOutFromSetup (pll_setup_t *pSetup)
	Return System PLL output clock rate from setup structure. More...
pll_error_t	CLOCK_SetupPLLData (pll_config_t *pControl, pll_setup_t *pSetup)
	Set PLL output based on the passed PLL setup data. More...
pll_error_t	CLOCK_SetupSystemPLLPrec (pll_setup_t *pSetup, uint32_t flagcfg)
	Set PLL output from PLL setup structure (precise frequency) More...
pll_error_t	CLOCK_SetPLLFreq (const pll_setup_t *pSetup)
	Set PLL output from PLL setup structure (precise frequency) More...
void	CLOCK_SetupSystemPLLMult (uint32_t multiply_by, uint32_t input_freq)
	Set PLL output based on the multiplier and input frequency. More...
static void	CLOCK_DisableUsbfs0Clock (void)
	Disable USB FS clock. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 4, 2))
	CLOCK driver version 2.4.2. More...

---

Data Structure Documentation

struct _pll_config

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

Data Fields
uint32_t	desiredRate
	Desired PLL rate in Hz.
uint32_t	inputRate
	PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set.
uint32_t	flags
	PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions.
ss_progmodfm_t	ss_mf
	SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
ss_progmoddp_t	ss_mr
	SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
ss_modwvctrl_t	ss_mc
	SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
bool	mfDither
	false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag

struct _pll_setup

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

Data Fields
uint32_t	syspllctrl
	PLL control register SYSPLLCTRL.
uint32_t	syspllndec
	PLL NDEC register SYSPLLNDEC.
uint32_t	syspllpdec
	PLL PDEC register SYSPLLPDEC.
uint32_t	syspllssctrl [2]
	PLL SSCTL registers SYSPLLSSCTRL.
uint32_t	pllRate
	Acutal PLL rate.
uint32_t	flags
	PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 4, 2))

#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT   2U

Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function would cache the recent calulation and accelerate the execution to get the right settings.

#define FLEXCOMM_CLOCKS

Value:

{                                                                                                               \
        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
            kCLOCK_FlexComm6, kCLOCK_FlexComm7                                                                      \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
            kCLOCK_MinUart6, kCLOCK_MinUart7                                                                  \
    }

#define BI2C_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
    }

#define LPSI_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
    }

#define FLEXI2S_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7                                                                  \
    }

#define UTICK_CLOCKS

Value:

{                \
        kCLOCK_Utick \
    }

#define DMA_CLOCKS

Value:

{              \
        kCLOCK_Dma \
    }

#define CTIMER_CLOCKS

Value:

{                                                                    \
        kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_IpInvalid, kCLOCK_Ctimer3 \
    }

#define GPIO_CLOCKS

Value:

{                              \
        kCLOCK_Gpio0, kCLOCK_Gpio1 \
    }

#define ADC_CLOCKS

Value:

{               \
        kCLOCK_Adc0 \
    }

#define MRT_CLOCKS

Value:

{              \
        kCLOCK_Mrt \
    }

#define SCT_CLOCKS

Value:

{               \
        kCLOCK_Sct0 \
    }

#define RTC_CLOCKS

Value:

{              \
        kCLOCK_Rtc \
    }

#define WWDT_CLOCKS

Value:

{               \
        kCLOCK_Wwdt \
    }

#define CRC_CLOCKS

Value:

{              \
        kCLOCK_Crc \
    }

#define USBD_CLOCKS

Value:

{                \
        kCLOCK_Usbd0 \
    }

#define GINT_CLOCKS

Value:

{                            \
        kCLOCK_Gint, kCLOCK_Gint \
    }

GINT0 & GINT1 share same slot

#define CLK_GATE_REG_OFFSET_SHIFT   8U

#define CLK_ATTACH_ID	(		mux,
			sel,
			pos
	)		((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

#define PLL_CONFIGFLAG_USEINRATE   (1U << 0U)

When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the configuration structure must be assigned with the expected PLL frequency. If the PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration function and the driver will determine the PLL rate from the currently selected PLL source. This flag might be used to configure the PLL input clock more accurately when using the WDT oscillator or a more dyanmic CLKIN source.

When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider are not used.
Flag to use InputRate in PLL configuration structure for setup

#define PLL_SETUPFLAG_POWERUP   (1U << 0U)

Setup will power on the PLL after setup

Typedef Documentation

typedef enum _clock_ip_name clock_ip_name_t

typedef enum _clock_name clock_name_t

typedef enum _clock_div_name clock_div_name_t

typedef enum _ss_modwvctrl ss_modwvctrl_t

Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

typedef struct _pll_config pll_config_t

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

typedef struct _pll_setup pll_setup_t

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

typedef enum _clock_usb_src clock_usb_src_t

Enumeration Type Documentation

enum _clock_ip_name

Enumerator
kCLOCK_IpInvalid	Invalid Ip Name.
kCLOCK_Rom	Clock gate name: Rom.
kCLOCK_Flash	Clock gate name: Flash.
kCLOCK_Fmc	Clock gate name: Fmc.
kCLOCK_InputMux	Clock gate name: InputMux.
kCLOCK_Iocon	Clock gate name: Iocon.
kCLOCK_Gpio0	Clock gate name: Gpio0.
kCLOCK_Gpio1	Clock gate name: Gpio1.
kCLOCK_Pint	Clock gate name: Pint.
kCLOCK_Gint	Clock gate name: Gint, GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot.
kCLOCK_Dma	Clock gate name: Dma.
kCLOCK_Crc	Clock gate name: Crc.
kCLOCK_Wwdt	Clock gate name: Wwdt.
kCLOCK_Rtc	Clock gate name: Rtc.
kCLOCK_Adc0	Clock gate name: Adc0.
kCLOCK_Mrt	Clock gate name: Mrt.
kCLOCK_Sct0	Clock gate name: Sct0.
kCLOCK_Utick	Clock gate name: Utick.
kCLOCK_FlexComm0	Clock gate name: FlexComm0.
kCLOCK_FlexComm1	Clock gate name: FlexComm1.
kCLOCK_FlexComm2	Clock gate name: FlexComm2.
kCLOCK_FlexComm3	Clock gate name: FlexComm3.
kCLOCK_FlexComm4	Clock gate name: FlexComm4.
kCLOCK_FlexComm5	Clock gate name: FlexComm5.
kCLOCK_FlexComm6	Clock gate name: FlexComm6.
kCLOCK_FlexComm7	Clock gate name: FlexComm7.
kCLOCK_MinUart0	Clock gate name: MinUart0.
kCLOCK_MinUart1	Clock gate name: MinUart1.
kCLOCK_MinUart2	Clock gate name: MinUart2.
kCLOCK_MinUart3	Clock gate name: MinUart3.
kCLOCK_MinUart4	Clock gate name: MinUart4.
kCLOCK_MinUart5	Clock gate name: MinUart5.
kCLOCK_MinUart6	Clock gate name: MinUart6.
kCLOCK_MinUart7	Clock gate name: MinUart7.
kCLOCK_LSpi0	Clock gate name: LSpi0.
kCLOCK_LSpi1	Clock gate name: LSpi1.
kCLOCK_LSpi2	Clock gate name: LSpi2.
kCLOCK_LSpi3	Clock gate name: LSpi3.
kCLOCK_LSpi4	Clock gate name: LSpi4.
kCLOCK_LSpi5	Clock gate name: LSpi5.
kCLOCK_LSpi6	Clock gate name: LSpi6.
kCLOCK_LSpi7	Clock gate name: LSpi7.
kCLOCK_BI2c0	Clock gate name: BI2c0.
kCLOCK_BI2c1	Clock gate name: BI2c1.
kCLOCK_BI2c2	Clock gate name: BI2c2.
kCLOCK_BI2c3	Clock gate name: BI2c3.
kCLOCK_BI2c4	Clock gate name: BI2c4.
kCLOCK_BI2c5	Clock gate name: BI2c5.
kCLOCK_BI2c6	Clock gate name: BI2c6.
kCLOCK_BI2c7	Clock gate name: BI2c7.
kCLOCK_FlexI2s0	Clock gate name: FlexI2s0.
kCLOCK_FlexI2s1	Clock gate name: FlexI2s1.
kCLOCK_FlexI2s2	Clock gate name: FlexI2s2.
kCLOCK_FlexI2s3	Clock gate name: FlexI2s3.
kCLOCK_FlexI2s4	Clock gate name: FlexI2s4.
kCLOCK_FlexI2s5	Clock gate name: FlexI2s5.
kCLOCK_FlexI2s6	Clock gate name: FlexI2s6.
kCLOCK_FlexI2s7	Clock gate name: FlexI2s7.
kCLOCK_Ct32b2	Clock gate name: Ct32b2.
kCLOCK_Usbd0	Clock gate name: Usbd0.
kCLOCK_Ctimer0	Clock gate name: Ctimer0.
kCLOCK_Ctimer1	Clock gate name: Ctimer1.
kCLOCK_Ctimer3	Clock gate name: Ctimer3.

enum _clock_name

Enumerator
kCLOCK_CoreSysClk	Core/system clock (aka MAIN_CLK)
kCLOCK_BusClk	Bus clock (AHB clock)
kCLOCK_ClockOut	CLOCKOUT.
kCLOCK_FroHf	FRO48/96.
kCLOCK_Fro12M	FRO12M.
kCLOCK_ExtClk	External Clock.
kCLOCK_PllOut	PLL Output.
kCLOCK_WdtOsc	Watchdog Oscillator.
kCLOCK_Frg	Frg Clock.
kCLOCK_AsyncApbClk	Async APB clock.
kCLOCK_FlexI2S	FlexI2S clock.

enum _async_clock_src

Enumerator
kCLOCK_AsyncMainClk	Main System clock.
kCLOCK_AsyncFro12Mhz	12MHz FRO

enum _clock_attach_id

Enumerator
kFRO12M_to_MAIN_CLK	Attach FRO12M to MAIN_CLK.
kEXT_CLK_to_MAIN_CLK	Attach EXT_CLK to MAIN_CLK.
kWDT_OSC_to_MAIN_CLK	Attach WDT_OSC to MAIN_CLK.
kFRO_HF_to_MAIN_CLK	Attach FRO_HF to MAIN_CLK.
kSYS_PLL_to_MAIN_CLK	Attach SYS_PLL to MAIN_CLK.
kOSC32K_to_MAIN_CLK	Attach OSC32K to MAIN_CLK.
kFRO12M_to_SYS_PLL	Attach FRO12M to SYS_PLL.
kEXT_CLK_to_SYS_PLL	Attach EXT_CLK to SYS_PLL.
kWDT_OSC_to_SYS_PLL	Attach WDT_OSC to SYS_PLL.
kOSC32K_to_SYS_PLL	Attach OSC32K to SYS_PLL.
kNONE_to_SYS_PLL	Attach NONE to SYS_PLL.
kMAIN_CLK_to_ASYNC_APB	Attach MAIN_CLK to ASYNC_APB.
kFRO12M_to_ASYNC_APB	Attach FRO12M to ASYNC_APB.
kMAIN_CLK_to_ADC_CLK	Attach MAIN_CLK to ADC_CLK.
kSYS_PLL_to_ADC_CLK	Attach SYS_PLL to ADC_CLK.
kFRO_HF_to_ADC_CLK	Attach FRO_HF to ADC_CLK.
kNONE_to_ADC_CLK	Attach NONE to ADC_CLK.
kFRO12M_to_FLEXCOMM0	Attach FRO12M to FLEXCOMM0.
kFRO_HF_to_FLEXCOMM0	Attach FRO_HF to FLEXCOMM0.
kSYS_PLL_to_FLEXCOMM0	Attach SYS_PLL to FLEXCOMM0.
kMCLK_to_FLEXCOMM0	Attach MCLK to FLEXCOMM0.
kFRG_to_FLEXCOMM0	Attach FRG to FLEXCOMM0.
kNONE_to_FLEXCOMM0	Attach NONE to FLEXCOMM0.
kFRO12M_to_FLEXCOMM1	Attach FRO12M to FLEXCOMM1.
kFRO_HF_to_FLEXCOMM1	Attach FRO_HF to FLEXCOMM1.
kSYS_PLL_to_FLEXCOMM1	Attach SYS_PLL to FLEXCOMM1.
kMCLK_to_FLEXCOMM1	Attach MCLK to FLEXCOMM1.
kFRG_to_FLEXCOMM1	Attach FRG to FLEXCOMM1.
kNONE_to_FLEXCOMM1	Attach NONE to FLEXCOMM1.
kFRO12M_to_FLEXCOMM2	Attach FRO12M to FLEXCOMM2.
kFRO_HF_to_FLEXCOMM2	Attach FRO_HF to FLEXCOMM2.
kSYS_PLL_to_FLEXCOMM2	Attach SYS_PLL to FLEXCOMM2.
kMCLK_to_FLEXCOMM2	Attach MCLK to FLEXCOMM2.
kFRG_to_FLEXCOMM2	Attach FRG to FLEXCOMM2.
kNONE_to_FLEXCOMM2	Attach NONE to FLEXCOMM2.
kFRO12M_to_FLEXCOMM3	Attach FRO12M to FLEXCOMM3.
kFRO_HF_to_FLEXCOMM3	Attach FRO_HF to FLEXCOMM3.
kSYS_PLL_to_FLEXCOMM3	Attach SYS_PLL to FLEXCOMM3.
kMCLK_to_FLEXCOMM3	Attach MCLK to FLEXCOMM3.
kFRG_to_FLEXCOMM3	Attach FRG to FLEXCOMM3.
kNONE_to_FLEXCOMM3	Attach NONE to FLEXCOMM3.
kFRO12M_to_FLEXCOMM4	Attach FRO12M to FLEXCOMM4.
kFRO_HF_to_FLEXCOMM4	Attach FRO_HF to FLEXCOMM4.
kSYS_PLL_to_FLEXCOMM4	Attach SYS_PLL to FLEXCOMM4.
kMCLK_to_FLEXCOMM4	Attach MCLK to FLEXCOMM4.
kFRG_to_FLEXCOMM4	Attach FRG to FLEXCOMM4.
kNONE_to_FLEXCOMM4	Attach NONE to FLEXCOMM4.
kFRO12M_to_FLEXCOMM5	Attach FRO12M to FLEXCOMM5.
kFRO_HF_to_FLEXCOMM5	Attach FRO_HF to FLEXCOMM5.
kSYS_PLL_to_FLEXCOMM5	Attach SYS_PLL to FLEXCOMM5.
kMCLK_to_FLEXCOMM5	Attach MCLK to FLEXCOMM5.
kFRG_to_FLEXCOMM5	Attach FRG to FLEXCOMM5.
kNONE_to_FLEXCOMM5	Attach NONE to FLEXCOMM5.
kFRO12M_to_FLEXCOMM6	Attach FRO12M to FLEXCOMM6.
kFRO_HF_to_FLEXCOMM6	Attach FRO_HF to FLEXCOMM6.
kSYS_PLL_to_FLEXCOMM6	Attach SYS_PLL to FLEXCOMM6.
kMCLK_to_FLEXCOMM6	Attach MCLK to FLEXCOMM6.
kFRG_to_FLEXCOMM6	Attach FRG to FLEXCOMM6.
kNONE_to_FLEXCOMM6	Attach NONE to FLEXCOMM6.
kFRO12M_to_FLEXCOMM7	Attach FRO12M to FLEXCOMM7.
kFRO_HF_to_FLEXCOMM7	Attach FRO_HF to FLEXCOMM7.
kSYS_PLL_to_FLEXCOMM7	Attach SYS_PLL to FLEXCOMM7.
kMCLK_to_FLEXCOMM7	Attach MCLK to FLEXCOMM7.
kFRG_to_FLEXCOMM7	Attach FRG to FLEXCOMM7.
kNONE_to_FLEXCOMM7	Attach NONE to FLEXCOMM7.
kMAIN_CLK_to_FRG	Attach MAIN_CLK to FRG.
kSYS_PLL_to_FRG	Attach SYS_PLL to FRG.
kFRO12M_to_FRG	Attach FRO12M to FRG.
kFRO_HF_to_FRG	Attach FRO_HF to FRG.
kNONE_to_FRG	Attach NONE to FRG.
kFRO_HF_to_MCLK	Attach FRO_HF to MCLK.
kSYS_PLL_to_MCLK	Attach SYS_PLL to MCLK.
kMAIN_CLK_to_MCLK	Attach MAIN_CLK to MCLK.
kNONE_to_MCLK	Attach NONE to MCLK.
kFRO_HF_to_USB_CLK	Attach FRO_HF to USB_CLK.
kSYS_PLL_to_USB_CLK	Attach SYS_PLL to USB_CLK.
kMAIN_CLK_to_USB_CLK	Attach MAIN_CLK to USB_CLK.
kNONE_to_USB_CLK	Attach NONE to USB_CLK.
kMAIN_CLK_to_CLKOUT	Attach MAIN_CLK to CLKOUT.
kEXT_CLK_to_CLKOUT	Attach EXT_CLK to CLKOUT.
kWDT_OSC_to_CLKOUT	Attach WDT_OSC to CLKOUT.
kFRO_HF_to_CLKOUT	Attach FRO_HF to CLKOUT.
kSYS_PLL_to_CLKOUT	Attach SYS_PLL to CLKOUT.
kFRO12M_to_CLKOUT	Attach FRO12M to CLKOUT.
kOSC32K_to_CLKOUT	Attach OSC32K to CLKOUT.
kNONE_to_CLKOUT	Attach NONE to CLKOUT.
kNONE_to_NONE	Attach NONE to NONE.

enum _clock_div_name

Enumerator
kCLOCK_DivSystickClk	Systick clock divider.
kCLOCK_DivTraceClk	Trace clock divider.
kCLOCK_DivAhbClk	Ahb clock divider.
kCLOCK_DivClkOut	Clock out divider.
kCLOCK_DivAdcAsyncClk	Adc Async clock divider.
kCLOCK_DivUsbClk	Usb clock divier.
kCLOCK_DivFrg	Frg clock divider.
kCLOCK_DivFxI2s0MClk	FxI2S0 clock divider.

enum _clock_flashtim

Enumerator
kCLOCK_Flash1Cycle	Flash accesses use 1 CPU clock.
kCLOCK_Flash2Cycle	Flash accesses use 2 CPU clocks.
kCLOCK_Flash3Cycle	Flash accesses use 3 CPU clocks.
kCLOCK_Flash4Cycle	Flash accesses use 4 CPU clocks.
kCLOCK_Flash5Cycle	Flash accesses use 5 CPU clocks.
kCLOCK_Flash6Cycle	Flash accesses use 6 CPU clocks.
kCLOCK_Flash7Cycle	Flash accesses use 7 CPU clocks.

enum _ss_progmodfm

Enumerator
kSS_MF_512	Nss = 512 (fm ? 3.9 - 7.8 kHz)
kSS_MF_384	Nss ?= 384 (fm ? 5.2 - 10.4 kHz)
kSS_MF_256	Nss = 256 (fm ? 7.8 - 15.6 kHz)
kSS_MF_128	Nss = 128 (fm ? 15.6 - 31.3 kHz)
kSS_MF_64	Nss = 64 (fm ? 32.3 - 64.5 kHz)
kSS_MF_32	Nss = 32 (fm ? 62.5- 125 kHz)
kSS_MF_24	Nss ?= 24 (fm ? 83.3- 166.6 kHz)
kSS_MF_16	Nss = 16 (fm ? 125- 250 kHz)

enum _ss_progmoddp

Enumerator
kSS_MR_K0	k = 0 (no spread spectrum)
kSS_MR_K1	k = 1
kSS_MR_K1_5	k = 1.5
kSS_MR_K2	k = 2
kSS_MR_K3	k = 3
kSS_MR_K4	k = 4
kSS_MR_K6	k = 6
kSS_MR_K8	k = 8

enum _ss_modwvctrl

Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

Enumerator
kSS_MC_NOC	no compensation
kSS_MC_RECC	recommended setting
kSS_MC_MAXC	max. compensation

enum _pll_error

Enumerator
kStatus_PLL_Success	PLL operation was successful.
kStatus_PLL_OutputTooLow	PLL output rate request was too low.
kStatus_PLL_OutputTooHigh	PLL output rate request was too high.
kStatus_PLL_InputTooLow	PLL input rate is too low.
kStatus_PLL_InputTooHigh	PLL input rate is too high.
kStatus_PLL_OutsideIntLimit	Requested output rate isn't possible.

enum _clock_usb_src

Enumerator
kCLOCK_UsbSrcFro	Use FRO 96 or 48 MHz.
kCLOCK_UsbSrcSystemPll	Use System PLL output.
kCLOCK_UsbSrcMainClock	Use Main clock.
kCLOCK_UsbSrcNone	Use None, this may be selected in order to reduce power when no output is needed.

Function Documentation

static void CLOCK_SetFLASHAccessCycles ( clock_flashtim_t  clks )

inlinestatic

Parameters

clks	: Clock cycles for FLASH access

Returns

Nothing

status_t CLOCK_SetupFROClocking

(

uint32_t

iFreq

)

Parameters

iFreq

: Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)

Returns

returns success or fail status.

void CLOCK_AttachClk

(

clock_attach_id_t

connection

)

Parameters

connection

: Clock to be configured.

Returns

Nothing

clock_attach_id_t CLOCK_GetClockAttachId

(

clock_attach_id_t

attachId

)

Parameters

attachId

: Clock attach id to get.

Returns

Clock source value.

void CLOCK_SetClkDiv	(	clock_div_name_t	div_name,
		uint32_t	divided_by_value,
		bool	reset
	)

Parameters

div_name	: Clock divider name
divided_by_value,:	Value to be divided
reset	: Whether to reset the divider counter.

Returns

Nothing

void CLOCK_SetFLASHAccessCyclesForFreq

(

uint32_t

iFreq

)

Parameters

iFreq

: Input frequency

Returns

Nothing

uint32_t CLOCK_GetFreq

(

clock_name_t

clockName

)

Returns

Frequency of selected clock

uint32_t CLOCK_GetFRGInputClock

(

void

)

Returns

Input Frequency for FRG

uint32_t CLOCK_SetFRGClock

(

uint32_t

freq

)

Parameters

freq	: Desired output frequency

Returns

Error Code 0 - fail 1 - success

uint32_t CLOCK_GetFro12MFreq

(

void

)

Returns

Frequency of FRO 12MHz

uint32_t CLOCK_GetExtClkFreq

(

void

)

Returns

Frequency of External Clock. If no external clock is used returns 0.

uint32_t CLOCK_GetWdtOscFreq

(

void

)

Returns

Frequency of Watchdog Oscillator

uint32_t CLOCK_GetFroHfFreq

(

void

)

Returns

Frequency of High-Freq output of FRO

uint32_t CLOCK_GetPllOutFreq

(

void

)

Returns

Frequency of PLL

uint32_t CLOCK_GetOsc32KFreq

(

void

)

Returns

Frequency of 32kHz osc

uint32_t CLOCK_GetCoreSysClkFreq

(

void

)

Returns

Frequency of Core System

uint32_t CLOCK_GetI2SMClkFreq

(

void

)

Returns

Frequency of I2S MCLK Clock

uint32_t CLOCK_GetFlexCommClkFreq

(

uint32_t

id

)

Returns

Frequency of Flexcomm functional Clock

uint32_t CLOCK_GetAdcClkFreq

(

void

)

Returns

Frequency of Adc Clock.

uint32_t CLOCK_GetClockOutClkFreq

(

void

)

Returns

Frequency of ClockOut

__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc

(

void

)

Returns

Asynchronous APB CLock source

uint32_t CLOCK_GetAsyncApbClkFreq

(

void

)

Returns

Frequency of Asynchronous APB Clock Clock

uint32_t CLOCK_GetSystemPLLInClockRate

(

void

)

Returns

System PLL input clock rate

uint32_t CLOCK_GetSystemPLLOutClockRate

(

bool

recompute

)

Parameters

recompute

: Forces a PLL rate recomputation if true

Returns

System PLL output clock rate

Note

The PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

__STATIC_INLINE void CLOCK_SetBypassPLL

(

bool

bypass

)

bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass

Returns

System PLL output clock rate

__STATIC_INLINE bool CLOCK_IsSystemPLLLocked

(

void

)

Returns

true if the PLL is locked, false if not locked

void CLOCK_SetStoredPLLClockRate

(

uint32_t

rate

)

Parameters

rate,:

Current rate of the PLL

Returns

Nothing

uint32_t CLOCK_GetSystemPLLOutFromSetup

(

pll_setup_t *

pSetup

)

Parameters

pSetup

: Pointer to a PLL setup structure

Returns

System PLL output clock rate calculated from the setup structure

pll_error_t CLOCK_SetupPLLData	(	pll_config_t *	pControl,
		pll_setup_t *	pSetup
	)

Parameters

pControl	: Pointer to populated PLL control structure to generate setup with
pSetup	: Pointer to PLL setup structure to be filled

Returns

PLL_ERROR_SUCCESS on success, or PLL setup error code

Note

Actual frequency for setup may vary from the desired frequency based on the accuracy of input clocks, rounding, non-fractional PLL mode, etc.

pll_error_t CLOCK_SetupSystemPLLPrec	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns

PLL_ERROR_SUCCESS on success, or PLL setup error code

Note

This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetPLLFreq

(

const pll_setup_t *

pSetup

)

Parameters

pSetup

: Pointer to populated PLL setup structure

Returns

kStatus_PLL_Success on success, or PLL setup error code

Note

This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

void CLOCK_SetupSystemPLLMult	(	uint32_t	multiply_by,
		uint32_t	input_freq
	)

Parameters

multiply_by	: multiplier
input_freq	: Clock input frequency of the PLL

Returns

Nothing

Note

Unlike the Chip_Clock_SetupSystemPLLPrec() function, this function does not disable or enable PLL power, wait for PLL lock, or adjust system voltages. These must be done in the application. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

static void CLOCK_DisableUsbfs0Clock ( void  )

inlinestatic

Disable USB FS clock.