![]() |
MCUXpresso SDK API Reference Manual
Rev 2.16.000
NXP Semiconductors
|
The MCUXpresso SDK provides a driver for the common module of MCUXpresso SDK devices.
Macros | |
#define | FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 |
Macro to use the default weak IRQ handler in drivers. More... | |
#define | MAKE_STATUS(group, code) ((((group)*100L) + (code))) |
Construct a status code value from a group and code number. More... | |
#define | MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) |
Construct the version number for drivers. More... | |
#define | ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
Computes the number of elements in an array. More... | |
#define | UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) |
Macro to get upper 32 bits of a 64-bit value. | |
#define | UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) |
Macro to get lower 32 bits of a 64-bit value. | |
#define | SUPPRESS_FALL_THROUGH_WARNING() |
For switch case code block, if case section ends without "break;" statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. More... | |
Typedefs | |
typedef int32_t | status_t |
Type used for all status and error return values. More... | |
Functions | |
void * | SDK_Malloc (size_t size, size_t alignbytes) |
Allocate memory with given alignment and aligned size. More... | |
void | SDK_Free (void *ptr) |
Free memory. More... | |
void | SDK_DelayAtLeastUs (uint32_t delayTime_us, uint32_t coreClock_Hz) |
Delay at least for some time. More... | |
static status_t | EnableIRQ (IRQn_Type interrupt) |
Enable specific interrupt. More... | |
static status_t | DisableIRQ (IRQn_Type interrupt) |
Disable specific interrupt. More... | |
static status_t | EnableIRQWithPriority (IRQn_Type interrupt, uint8_t priNum) |
Enable the IRQ, and also set the interrupt priority. More... | |
static status_t | IRQ_SetPriority (IRQn_Type interrupt, uint8_t priNum) |
Set the IRQ priority. More... | |
static status_t | IRQ_ClearPendingIRQ (IRQn_Type interrupt) |
Clear the pending IRQ flag. More... | |
static uint32_t | DisableGlobalIRQ (void) |
Disable the global IRQ. More... | |
static void | EnableGlobalIRQ (uint32_t primask) |
Enable the global IRQ. More... | |
void | EnableDeepSleepIRQ (IRQn_Type interrupt) |
Enable specific interrupt for wake-up from deep-sleep mode. More... | |
void | DisableDeepSleepIRQ (IRQn_Type interrupt) |
Disable specific interrupt for wake-up from deep-sleep mode. More... | |
Driver version | |
#define | FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) |
common driver version. More... | |
Debug console type definition. | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U |
No debug console. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_UART 1U |
Debug console based on UART. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U |
Debug console based on LPUART. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U |
Debug console based on LPSCI. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U |
Debug console based on USBCDC. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U |
Debug console based on FLEXCOMM. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U |
Debug console based on i.MX UART. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U |
Debug console based on LPC_VUSART. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U |
Debug console based on LPC_USART. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U |
Debug console based on SWO. More... | |
#define | DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U |
Debug console based on QSCI. More... | |
Min/max macros | |
#define | MIN(a, b) (((a) < (b)) ? (a) : (b)) |
Computes the minimum of a and b. More... | |
#define | MAX(a, b) (((a) > (b)) ? (a) : (b)) |
Computes the maximum of a and b. More... | |
UINT16_MAX/UINT32_MAX value | |
#define | UINT16_MAX ((uint16_t)-1) |
Max value of uint16_t type. More... | |
#define | UINT32_MAX ((uint32_t)-1) |
Max value of uint32_t type. More... | |
Atomic modification | |
These macros are used for atomic access, such as read-modify-write to the peripheral registers. Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, register bit1:bit0 = 0b10.
| |
#define | SDK_ATOMIC_LOCAL_ADD(addr, val) |
Add value val from the variable at address address. | |
#define | SDK_ATOMIC_LOCAL_SUB(addr, val) |
Subtract value val to the variable at address address. | |
#define | SDK_ATOMIC_LOCAL_SET(addr, bits) |
Set the bits specifiled by bits to the variable at address address. | |
#define | SDK_ATOMIC_LOCAL_CLEAR(addr, bits) |
Clear the bits specifiled by bits to the variable at address address. | |
#define | SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) |
Toggle the bits specifiled by bits to the variable at address address. | |
#define | SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) |
For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits. | |
Timer utilities | |
#define | USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) |
Macro to convert a microsecond period to raw count value. | |
#define | COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) |
Macro to convert a raw count value to microsecond. | |
#define | MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) |
Macro to convert a millisecond period to raw count value. | |
#define | COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) |
Macro to convert a raw count value to millisecond. | |
Alignment variable definition macros | |
#define | SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) |
Macro to define a variable with alignbytes alignment. | |
#define | SDK_SIZEALIGN(var, alignbytes) ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) |
Macro to define a variable with L1 d-cache line size alignment. More... | |
Non-cacheable region definition macros | |
For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables will be initialized to zero in system startup.
| |
#define | AT_NONCACHEABLE_SECTION(var) var |
Define a variable var, and place it in non-cacheable section. | |
#define | AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) |
Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. | |
#define | AT_NONCACHEABLE_SECTION_INIT(var) var |
Define a variable var with initial value, and place it in non-cacheable section. | |
#define | AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) |
Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. | |
Time sensitive region | |
#define | AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func |
Place function in a section which can be accessed quickly by core. | |
#define | AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var |
Place data in a section which can be accessed quickly by core. | |
#define | AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) |
Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes. | |
Ram Function | |
#define | RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func |
Place function in ram. | |
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 |
#define MAKE_STATUS | ( | group, | |
code | |||
) | ((((group)*100L) + (code))) |
#define MAKE_VERSION | ( | major, | |
minor, | |||
bugfix | |||
) | (((major)*65536L) + ((minor)*256L) + (bugfix)) |
The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).
| Unused || Major Version || Minor Version || Bug Fix | 31 25 24 17 16 9 8 0
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) |
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U |
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U |
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U |
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U |
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U |
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U |
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U |
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U |
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U |
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U |
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U |
#define MIN | ( | a, | |
b | |||
) | (((a) < (b)) ? (a) : (b)) |
#define MAX | ( | a, | |
b | |||
) | (((a) > (b)) ? (a) : (b)) |
#define ARRAY_SIZE | ( | x | ) | (sizeof(x) / sizeof((x)[0])) |
#define UINT16_MAX ((uint16_t)-1) |
#define UINT32_MAX ((uint32_t)-1) |
#define SUPPRESS_FALL_THROUGH_WARNING | ( | ) |
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each case section which misses "break;"statement.
#define SDK_SIZEALIGN | ( | var, | |
alignbytes | |||
) | ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) |
Macro to define a variable with L2 cache line size alignment
Macro to change a value to a given size aligned value
typedef int32_t status_t |
enum _status_groups |
anonymous enum |
void* SDK_Malloc | ( | size_t | size, |
size_t | alignbytes | ||
) |
This is provided to support the dynamically allocated memory used in cache-able region.
size | The length required to malloc. |
alignbytes | The alignment size. |
The | allocated memory. |
void SDK_Free | ( | void * | ptr | ) |
ptr | The memory to be release. |
void SDK_DelayAtLeastUs | ( | uint32_t | delayTime_us, |
uint32_t | coreClock_Hz | ||
) |
Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.
delayTime_us | Delay time in unit of microsecond. |
coreClock_Hz | Core clock frequency with Hz. |
|
inlinestatic |
Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
interrupt | The IRQ number. |
kStatus_Success | Interrupt enabled successfully |
kStatus_Fail | Failed to enable the interrupt |
|
inlinestatic |
Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
interrupt | The IRQ number. |
kStatus_Success | Interrupt disabled successfully |
kStatus_Fail | Failed to disable the interrupt |
|
inlinestatic |
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
interrupt | The IRQ to Enable. |
priNum | Priority number set to interrupt controller register. |
kStatus_Success | Interrupt priority set successfully |
kStatus_Fail | Failed to set the interrupt priority. |
|
inlinestatic |
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
interrupt | The IRQ to set. |
priNum | Priority number set to interrupt controller register. |
kStatus_Success | Interrupt priority set successfully |
kStatus_Fail | Failed to set the interrupt priority. |
|
inlinestatic |
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
interrupt | The flag which IRQ to clear. |
kStatus_Success | Interrupt priority set successfully |
kStatus_Fail | Failed to set the interrupt priority. |
|
inlinestatic |
Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().
|
inlinestatic |
Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
primask | value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ(). |
void EnableDeepSleepIRQ | ( | IRQn_Type | interrupt | ) |
Enable the interrupt for wake-up from deep sleep mode. Some interrupts are typically used in sleep mode only and will not occur during deep-sleep mode because relevant clocks are stopped. However, it is possible to enable those clocks (significantly increasing power consumption in the reduced power mode), making these wake-ups possible.
interrupt | The IRQ number. |
void DisableDeepSleepIRQ | ( | IRQn_Type | interrupt | ) |
Disable the interrupt for wake-up from deep sleep mode. Some interrupts are typically used in sleep mode only and will not occur during deep-sleep mode because relevant clocks are stopped. However, it is possible to enable those clocks (significantly increasing power consumption in the reduced power mode), making these wake-ups possible.
interrupt | The IRQ number. |