Reset driver supports peripheral reset and system reset.
|
| enum | _SYSCON_RSTn {
kFLASH_RST_N_SHIFT_RSTn = 0 | 4U,
kI2C0_RST_N_SHIFT_RSTn = 0 | 5U,
kGPIO0_RST_N_SHIFT_RSTn = 0 | 6U,
kSWM_RST_N_SHIFT_RSTn = 0 | 7U,
kSCT_RST_N_SHIFT_RSTn = 0 | 8U,
kWKT_RST_N_SHIFT_RSTn = 0 | 9U,
kMRT_RST_N_SHIFT_RSTn = 0 | 10U,
kSPI0_RST_N_SHIFT_RSTn = 0 | 11U,
kSPI1_RST_N_SHIFT_RSTn = 0 | 12U,
kCRC_RST_SHIFT_RSTn = 0 | 13U,
kUART0_RST_N_SHIFT_RSTn = 0 | 14U,
kUART1_RST_N_SHIFT_RSTn = 0 | 15U,
kUART2_RST_N_SHIFT_RSTn = 0 | 16U,
kIOCON_RST_N_SHIFT_RSTn = 0 | 18U,
kACMP_RST_N_SHIFT_RSTn = 0 | 19U,
kGPIO1_RST_N_SHIFT_RSTn = 0 | 20U,
kI2C1_RST_N_SHIFT_RSTn = 0 | 21U,
kI2C2_RST_N_SHIFT_RSTn = 0 | 22U,
kI2C3_RST_N_SHIFT_RSTn = 0 | 23U,
kADC_RST_N_SHIFT_RSTn = 0 | 24U,
kCTIMER0_RST_N_SHIFT_RSTn = 0 | 25U,
kDAC0_RST_N_SHIFT_RSTn = 0 | 27U,
kGPIOINT_RST_N_SHIFT_RSTn = 0 | 28U,
kDMA_RST_N_SHIFT_RSTn = 0 | 29U,
kUART3_RST_N_SHIFT_RSTn = 0 | 30U,
kUART4_RST_N_SHIFT_RSTn = 0 | 31U,
kCAPT_RST_N_SHIFT_RSTn = 65536 | 0U,
kDAC1_RST_N_SHIFT_RSTn = 65536 | 1U,
kFRG0_RST_N_SHIFT_RSTn = 65536 | 3U,
kFRG1_RST_N_SHIFT_RSTn = 65536 | 4U
} |
| | Enumeration for peripheral reset control bits. More...
|
| |
Value:
}
Definition: fsl_reset.h:39
Array initializers with peripheral reset bits
Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
| Enumerator |
|---|
| kFLASH_RST_N_SHIFT_RSTn |
Flash controller reset control
|
| kI2C0_RST_N_SHIFT_RSTn |
I2C0 reset control
|
| kGPIO0_RST_N_SHIFT_RSTn |
GPIO0 reset control
|
| kSWM_RST_N_SHIFT_RSTn |
SWM reset control
|
| kSCT_RST_N_SHIFT_RSTn |
SCT reset control
|
| kWKT_RST_N_SHIFT_RSTn |
Self-wake-up timer(WKT) reset control
|
| kMRT_RST_N_SHIFT_RSTn |
Multi-rate timer(MRT) reset control
|
| kSPI0_RST_N_SHIFT_RSTn |
SPI0 reset control.
|
| kSPI1_RST_N_SHIFT_RSTn |
SPI1 reset control
|
| kCRC_RST_SHIFT_RSTn |
CRC reset control
|
| kUART0_RST_N_SHIFT_RSTn |
UART0 reset control
|
| kUART1_RST_N_SHIFT_RSTn |
UART1 reset control
|
| kUART2_RST_N_SHIFT_RSTn |
UART2 reset control
|
| kIOCON_RST_N_SHIFT_RSTn |
IOCON reset control
|
| kACMP_RST_N_SHIFT_RSTn |
Analog comparator reset control
|
| kGPIO1_RST_N_SHIFT_RSTn |
GPIO1 reset control
|
| kI2C1_RST_N_SHIFT_RSTn |
I2C1 reset control
|
| kI2C2_RST_N_SHIFT_RSTn |
I2C2 reset control
|
| kI2C3_RST_N_SHIFT_RSTn |
I2C3 reset control
|
| kADC_RST_N_SHIFT_RSTn |
ADC reset control
|
| kCTIMER0_RST_N_SHIFT_RSTn |
CTIMER0 reset control
|
| kDAC0_RST_N_SHIFT_RSTn |
DAC0 reset control
|
| kGPIOINT_RST_N_SHIFT_RSTn |
GPIOINT reset control
|
| kDMA_RST_N_SHIFT_RSTn |
DMA reset control
|
| kUART3_RST_N_SHIFT_RSTn |
UART3 reset control
|
| kUART4_RST_N_SHIFT_RSTn |
UART4 reset control
|
| kCAPT_RST_N_SHIFT_RSTn |
Capacitive Touch reset control
|
| kDAC1_RST_N_SHIFT_RSTn |
DAC1 reset control
|
| kFRG0_RST_N_SHIFT_RSTn |
Fractional baud rate generator 0 reset control
|
| kFRG1_RST_N_SHIFT_RSTn |
Fractional baud rate generator 1 reset control
|
| void RESET_SetPeripheralReset |
( |
reset_ip_name_t |
peripheral | ) |
|
Asserts reset signal to specified peripheral module.
- Parameters
-
| peripheral | Assert reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register. |
| void RESET_ClearPeripheralReset |
( |
reset_ip_name_t |
peripheral | ) |
|
Clears reset signal to specified peripheral module, allows it to operate.
- Parameters
-
| peripheral | Clear reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register. |
| void RESET_PeripheralReset |
( |
reset_ip_name_t |
peripheral | ) |
|
Reset peripheral module.
- Parameters
-
| peripheral | Peripheral to reset. The enum argument contains encoding of reset register and reset bit position in the reset register. |
| static void RESET_ReleasePeripheralReset |
( |
reset_ip_name_t |
peripheral | ) |
|
|
inlinestatic |
Release peripheral module.
- Parameters
-
| peripheral | Peripheral to release. The enum argument contains encoding of reset register and reset bit position in the reset register. |