Clock Driver

Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

• Clock generator (PLL, FLL, and so on) configuration
• Clock mux and divider configuration
• Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	_clock_usb_pll_config
	PLL configuration for USB. More...
struct	_clock_sys_pll_config
	PLL configuration for System. More...
struct	_clock_audio_pll_config
	PLL configuration for AUDIO and VIDEO. More...
struct	_clock_enet_pll_config
	PLL configuration for ENET. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
	Configure whether driver controls clock. More...
#define	CCSR_OFFSET   0x0C
	CCM registers offset.
#define	PLL_SYS_OFFSET   0x30
	CCM Analog registers offset.
#define	CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFU) << 16U) | (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.
#define	CLKPN_FREQ   0U
	clock1PN frequency.
#define	ADC_CLOCKS
	Clock ip name array for ADC. More...
#define	AOI_CLOCKS
	Clock ip name array for AOI. More...
#define	BEE_CLOCKS
	Clock ip name array for BEE. More...
#define	DCDC_CLOCKS
	Clock ip name array for DCDC. More...
#define	DCP_CLOCKS
	Clock ip name array for DCP. More...
#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS. More...
#define	EDMA_CLOCKS
	Clock ip name array for DMA. More...
#define	ENC_CLOCKS
	Clock ip name array for ENC. More...
#define	EWM_CLOCKS
	Clock ip name array for EWM. More...
#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...
#define	FLEXRAM_CLOCKS
	Clock ip name array for FLEXRAM. More...
#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI. More...
#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...
#define	GPT_CLOCKS
	Clock ip name array for GPT. More...
#define	KPP_CLOCKS
	Clock ip name array for KPP. More...
#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...
#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...
#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...
#define	OCRAM_EXSC_CLOCKS
	Clock ip name array for OCRAM EXSC. More...
#define	PIT_CLOCKS
	Clock ip name array for PIT. More...
#define	PWM_CLOCKS
	Clock ip name array for PWM. More...
#define	RTWDOG_CLOCKS
	Clock ip name array for RTWDOG. More...
#define	SAI_CLOCKS
	Clock ip name array for SAI. More...
#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...
#define	TRNG_CLOCKS
	Clock ip name array for TRNG. More...
#define	WDOG_CLOCKS
	Clock ip name array for WDOG. More...
#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...
#define	XBARA_CLOCKS
	Clock ip name array for XBARA. More...
#define	XBARB_CLOCKS
	Clock ip name array for XBARB. More...
#define	kCLOCK_CoreSysClk   kCLOCK_CpuClk
	For compatible with other platforms without CCM. More...
#define	CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
	For compatible with other platforms without CCM. More...

Typedefs
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...
typedef enum _clock_ip_name	clock_ip_name_t
	CCM CCGR gate control for each module independently.
typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select.
typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value.
typedef enum _clock_mode_t	clock_mode_t
	System clock mode.
typedef enum _clock_mux	clock_mux_t
	MUX control names for clock mux setting. More...
typedef enum _clock_div	clock_div_t
	DIV control names for clock div setting. More...
typedef enum _clock_div_value	clock_div_value_t
	Clock divider value.
typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...
typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY. More...
typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB.
typedef struct _clock_sys_pll_config	clock_sys_pll_config_t
	PLL configuration for System.
typedef struct _clock_audio_pll_config	clock_audio_pll_config_t
	PLL configuration for AUDIO and VIDEO.
typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET.
typedef enum _clock_pll	clock_pll_t
	PLL name.
typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name.
typedef enum _clock_output1_selection	clock_output1_selection_t
	The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
typedef enum _clock_output2_selection	clock_output2_selection_t
	The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
typedef enum _clock_output_divider	clock_output_divider_t
	The enumerator of clock output's divider.
typedef enum _clock_root	clock_root_t
	The enumerator of clock root.

Enumerations
enum	_clock_name {   kCLOCK_CpuClk = 0x0U,   kCLOCK_AhbClk = 0x1U,   kCLOCK_SemcClk = 0x2U,   kCLOCK_IpgClk = 0x3U,   kCLOCK_PerClk = 0x4U,   kCLOCK_OscClk = 0x5U,   kCLOCK_RtcClk = 0x6U,   kCLOCK_Usb1PllClk = 0x7U,   kCLOCK_Usb1PllPfd0Clk = 0x8U,   kCLOCK_Usb1PllPfd1Clk = 0x9U,   kCLOCK_Usb1PllPfd2Clk = 0xAU,   kCLOCK_Usb1PllPfd3Clk = 0xBU,   kCLOCK_Usb1SwClk = 0x15U,   kCLOCK_Usb1Sw60MClk = 0x16U,   kCLOCK_Usb1Sw80MClk = 0x1BU,   kCLOCK_SysPllClk = 0xCU,   kCLOCK_SysPllPfd0Clk = 0xDU,   kCLOCK_SysPllPfd1Clk = 0xEU,   kCLOCK_SysPllPfd2Clk = 0xFU,   kCLOCK_SysPllPfd3Clk = 0x10U,   kCLOCK_EnetPllClk = 0x11U,   kCLOCK_EnetPll25MClk = 0x12U,   kCLOCK_EnetPll500MClk = 0x13U,   kCLOCK_AudioPllClk = 0x14U,   kCLOCK_NoneName = CLOCK_SOURCE_NONE }
	Clock name used to get clock frequency. More...
enum	_clock_ip_name { ,   kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,   kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,   kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,   kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,   kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,   kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,   kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT,   kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT,   kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT,   kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT,   kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT,   kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,   kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,   kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,   kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,   kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT,   kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT,   kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT,   kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT,   kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT,   kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT,   kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,   kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,   kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,   kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,   kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,   kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT,   kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT,   kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT,   kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,   kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,   kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,   kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,   kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT,   kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT,   kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,   kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT,   kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,   kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,   kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,   kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,   kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,   kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT,   kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,   kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,   kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,   kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,   kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,   kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,   kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT,   kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,   kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,   kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT,   kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT,   kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT,   kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT,   kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT,   kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,   kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,   kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,   kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,   kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT,   kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT,   kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT,   kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT }
	CCM CCGR gate control for each module independently. More...
enum	_clock_osc {   kCLOCK_RcOsc = 0U,   kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...
enum	_clock_gate_value {   kCLOCK_ClockNotNeeded = 0U,   kCLOCK_ClockNeededRun = 1U,   kCLOCK_ClockNeededRunWait = 3U }
	Clock gate value. More...
enum	_clock_mode_t {   kCLOCK_ModeRun = 0U,   kCLOCK_ModeWait = 1U,   kCLOCK_ModeStop = 2U }
	System clock mode. More...
enum	_clock_mux {   kCLOCK_Pll3SwMux,   kCLOCK_PeriphMux,   kCLOCK_SemcAltMux,   kCLOCK_SemcMux,   kCLOCK_PrePeriphMux,   kCLOCK_TraceMux,   kCLOCK_PeriphClk2Mux,   kCLOCK_LpspiMux,   kCLOCK_FlexspiMux,   kCLOCK_Sai3Mux,   kCLOCK_Sai2Mux,   kCLOCK_Sai1Mux,   kCLOCK_PerclkMux,   kCLOCK_Flexio1Mux,   kCLOCK_UartMux,   kCLOCK_SpdifMux,   kCLOCK_Lpi2cMux }
	MUX control names for clock mux setting. More...
enum	_clock_div {   kCLOCK_ArmDiv,   kCLOCK_PeriphClk2Div,   kCLOCK_SemcDiv,   kCLOCK_AhbDiv,   kCLOCK_IpgDiv,   kCLOCK_LpspiDiv,   kCLOCK_FlexspiDiv,   kCLOCK_PerclkDiv,   kCLOCK_TraceDiv,   kCLOCK_UartDiv,   kCLOCK_Flexio1Div,   kCLOCK_Sai3PreDiv,   kCLOCK_Sai3Div,   kCLOCK_Flexio1PreDiv,   kCLOCK_Sai1PreDiv,   kCLOCK_Sai1Div,   kCLOCK_Sai2PreDiv,   kCLOCK_Sai2Div,   kCLOCK_Spdif0PreDiv,   kCLOCK_Spdif0Div,   kCLOCK_Lpi2cDiv,   kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV }
	DIV control names for clock div setting. More...
enum	_clock_div_value {   kCLOCK_ArmDivBy1 = 0,   kCLOCK_ArmDivBy2 = 1,   kCLOCK_ArmDivBy3 = 2,   kCLOCK_ArmDivBy4 = 3,   kCLOCK_ArmDivBy5 = 4,   kCLOCK_ArmDivBy6 = 5,   kCLOCK_ArmDivBy7 = 6,   kCLOCK_ArmDivBy8 = 7,   kCLOCK_PeriphClk2DivBy1 = 0,   kCLOCK_PeriphClk2DivBy2 = 1,   kCLOCK_PeriphClk2DivBy3 = 2,   kCLOCK_PeriphClk2DivBy4 = 3,   kCLOCK_PeriphClk2DivBy5 = 4,   kCLOCK_PeriphClk2DivBy6 = 5,   kCLOCK_PeriphClk2DivBy7 = 6,   kCLOCK_PeriphClk2DivBy8 = 7,   kCLOCK_SemcDivBy1 = 0,   kCLOCK_SemcDivBy2 = 1,   kCLOCK_SemcDivBy3 = 2,   kCLOCK_SemcDivBy4 = 3,   kCLOCK_SemcDivBy5 = 4,   kCLOCK_SemcDivBy6 = 5,   kCLOCK_SemcDivBy7 = 6,   kCLOCK_SemcDivBy8 = 7,   kCLOCK_AhbDivBy1 = 0,   kCLOCK_AhbDivBy2 = 1,   kCLOCK_AhbDivBy3 = 2,   kCLOCK_AhbDivBy4 = 3,   kCLOCK_AhbDivBy5 = 4,   kCLOCK_AhbDivBy6 = 5,   kCLOCK_AhbDivBy7 = 6,   kCLOCK_AhbDivBy8 = 7,   kCLOCK_IpgDivBy1 = 0,   kCLOCK_IpgDivBy2 = 1,   kCLOCK_IpgDivBy3 = 2,   kCLOCK_IpgDivBy4 = 3,   kCLOCK_LpspiDivBy1 = 0,   kCLOCK_LpspiDivBy2 = 1,   kCLOCK_LpspiDivBy3 = 2,   kCLOCK_LpspiDivBy4 = 3,   kCLOCK_LpspiDivBy5 = 4,   kCLOCK_LpspiDivBy6 = 5,   kCLOCK_LpspiDivBy7 = 6,   kCLOCK_LpspiDivBy8 = 7,   kCLOCK_FlexspiDivBy1 = 0,   kCLOCK_FlexspiDivBy2 = 1,   kCLOCK_FlexspiDivBy3 = 2,   kCLOCK_FlexspiDivBy4 = 3,   kCLOCK_FlexspiDivBy5 = 4,   kCLOCK_FlexspiDivBy6 = 5,   kCLOCK_FlexspiDivBy7 = 6,   kCLOCK_FlexspiDivBy8 = 7,   kCLOCK_TraceDivBy1 = 0,   kCLOCK_TraceDivBy2 = 1,   kCLOCK_TraceDivBy3 = 2,   kCLOCK_TraceDivBy4 = 3,   kCLOCK_Flexio1DivBy1 = 0,   kCLOCK_Flexio1DivBy2 = 1,   kCLOCK_Flexio1DivBy3 = 2,   kCLOCK_Flexio1DivBy4 = 3,   kCLOCK_Flexio1DivBy5 = 4,   kCLOCK_Flexio1DivBy6 = 5,   kCLOCK_Flexio1DivBy7 = 6,   kCLOCK_Flexio1DivBy8 = 7,   kCLOCK_Sai3PreDivBy1 = 0,   kCLOCK_Sai3PreDivBy2 = 1,   kCLOCK_Sai3PreDivBy3 = 2,   kCLOCK_Sai3PreDivBy4 = 3,   kCLOCK_Sai3PreDivBy5 = 4,   kCLOCK_Sai3PreDivBy6 = 5,   kCLOCK_Sai3PreDivBy7 = 6,   kCLOCK_Sai3PreDivBy8 = 7,   kCLOCK_Flexio1PreDivBy1 = 0,   kCLOCK_Flexio1PreDivBy2 = 1,   kCLOCK_Flexio1PreDivBy3 = 2,   kCLOCK_Flexio1PreDivBy4 = 3,   kCLOCK_Flexio1PreDivBy5 = 4,   kCLOCK_Flexio1PreDivBy6 = 5,   kCLOCK_Flexio1PreDivBy7 = 6,   kCLOCK_Flexio1PreDivBy8 = 7,   kCLOCK_Sai1PreDivBy1 = 0,   kCLOCK_Sai1PreDivBy2 = 1,   kCLOCK_Sai1PreDivBy3 = 2,   kCLOCK_Sai1PreDivBy4 = 3,   kCLOCK_Sai1PreDivBy5 = 4,   kCLOCK_Sai1PreDivBy6 = 5,   kCLOCK_Sai1PreDivBy7 = 6,   kCLOCK_Sai1PreDivBy8 = 7,   kCLOCK_Sai2PreDivBy1 = 0,   kCLOCK_Sai2PreDivBy2 = 1,   kCLOCK_Sai2PreDivBy3 = 2,   kCLOCK_Sai2PreDivBy4 = 3,   kCLOCK_Sai2PreDivBy5 = 4,   kCLOCK_Sai2PreDivBy6 = 5,   kCLOCK_Sai2PreDivBy7 = 6,   kCLOCK_Sai2PreDivBy8 = 7,   kCLOCK_Spdif0PreDivBy1 = 0,   kCLOCK_Spdif0PreDivBy2 = 1,   kCLOCK_Spdif0PreDivBy3 = 2,   kCLOCK_Spdif0PreDivBy4 = 3,   kCLOCK_Spdif0PreDivBy5 = 4,   kCLOCK_Spdif0PreDivBy6 = 5,   kCLOCK_Spdif0PreDivBy7 = 6,   kCLOCK_Spdif0PreDivBy8 = 7,   kCLOCK_Spdif0DivBy1 = 0,   kCLOCK_Spdif0DivBy2 = 1,   kCLOCK_Spdif0DivBy3 = 2,   kCLOCK_Spdif0DivBy4 = 3,   kCLOCK_Spdif0DivBy5 = 4,   kCLOCK_Spdif0DivBy6 = 5,   kCLOCK_Spdif0DivBy7 = 6,   kCLOCK_Spdif0DivBy8 = 7,   kCLOCK_MiscDivBy1 = 0,   kCLOCK_MiscDivBy2 = 1,   kCLOCK_MiscDivBy3 = 2,   kCLOCK_MiscDivBy4 = 3,   kCLOCK_MiscDivBy5 = 4,   kCLOCK_MiscDivBy6 = 5,   kCLOCK_MiscDivBy7 = 6,   kCLOCK_MiscDivBy8 = 7,   kCLOCK_MiscDivBy9 = 8,   kCLOCK_MiscDivBy10 = 9,   kCLOCK_MiscDivBy11 = 10,   kCLOCK_MiscDivBy12 = 11,   kCLOCK_MiscDivBy13 = 12,   kCLOCK_MiscDivBy14 = 13,   kCLOCK_MiscDivBy15 = 14,   kCLOCK_MiscDivBy16 = 15,   kCLOCK_MiscDivBy17 = 16,   kCLOCK_MiscDivBy18 = 17,   kCLOCK_MiscDivBy19 = 18,   kCLOCK_MiscDivBy20 = 19,   kCLOCK_MiscDivBy21 = 20,   kCLOCK_MiscDivBy22 = 21,   kCLOCK_MiscDivBy23 = 22,   kCLOCK_MiscDivBy24 = 23,   kCLOCK_MiscDivBy25 = 24,   kCLOCK_MiscDivBy26 = 25,   kCLOCK_MiscDivBy27 = 26,   kCLOCK_MiscDivBy28 = 27,   kCLOCK_MiscDivBy29 = 28,   kCLOCK_MiscDivBy30 = 29,   kCLOCK_MiscDivBy31 = 30,   kCLOCK_MiscDivBy32 = 31,   kCLOCK_MiscDivBy33 = 32,   kCLOCK_MiscDivBy34 = 33,   kCLOCK_MiscDivBy35 = 34,   kCLOCK_MiscDivBy36 = 35,   kCLOCK_MiscDivBy37 = 36,   kCLOCK_MiscDivBy38 = 37,   kCLOCK_MiscDivBy39 = 38,   kCLOCK_MiscDivBy40 = 39,   kCLOCK_MiscDivBy41 = 40,   kCLOCK_MiscDivBy42 = 41,   kCLOCK_MiscDivBy43 = 42,   kCLOCK_MiscDivBy44 = 43,   kCLOCK_MiscDivBy45 = 44,   kCLOCK_MiscDivBy46 = 45,   kCLOCK_MiscDivBy47 = 46,   kCLOCK_MiscDivBy48 = 47,   kCLOCK_MiscDivBy49 = 48,   kCLOCK_MiscDivBy50 = 49,   kCLOCK_MiscDivBy51 = 50,   kCLOCK_MiscDivBy52 = 51,   kCLOCK_MiscDivBy53 = 52,   kCLOCK_MiscDivBy54 = 53,   kCLOCK_MiscDivBy55 = 54,   kCLOCK_MiscDivBy56 = 55,   kCLOCK_MiscDivBy57 = 56,   kCLOCK_MiscDivBy58 = 57,   kCLOCK_MiscDivBy59 = 58,   kCLOCK_MiscDivBy60 = 59,   kCLOCK_MiscDivBy61 = 60,   kCLOCK_MiscDivBy62 = 61,   kCLOCK_MiscDivBy63 = 62,   kCLOCK_MiscDivBy64 = 63 }
	Clock divider value. More...
enum	_clock_usb_src {   kCLOCK_Usb480M = 0,   kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...
enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...
enum	_clock_pll_clk_src {   kCLOCK_PllClkSrc24M = 0U,   kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...
enum	_clock_pll {   kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),   kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),   kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT),   kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT) }
	PLL name. More...
enum	_clock_pfd {   kCLOCK_Pfd0 = 0U,   kCLOCK_Pfd1 = 1U,   kCLOCK_Pfd2 = 2U,   kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...
enum	_clock_output1_selection {   kCLOCK_OutputPllUsb1Sw = 0U,   kCLOCK_OutputPllSys = 1U,   kCLOCK_OutputPllENET = 2U,   kCLOCK_OutputAhbClk = 0xBU,   kCLOCK_OutputIpgClk = 0xCU,   kCLOCK_OutputPerClk = 0xDU,   kCLOCK_OutputPll4MainClk = 0xFU,   kCLOCK_DisableClockOutput1 = 0x10U }
	The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on. More...
enum	_clock_output2_selection {   kCLOCK_OutputLpi2cClk = 6U,   kCLOCK_OutputOscClk = 0xEU,   kCLOCK_OutputLpspiClk = 0x10U,   kCLOCK_OutputSai1Clk = 0x12U,   kCLOCK_OutputSai2Clk = 0x13U,   kCLOCK_OutputSai3Clk = 0x14U,   kCLOCK_OutputTraceClk = 0x16U,   kCLOCK_OutputFlexspiClk = 0x1BU,   kCLOCK_OutputUartClk = 0x1CU,   kCLOCK_OutputSpdif0Clk = 0x1DU,   kCLOCK_DisableClockOutput2 = 0x1FU }
	The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on. More...
enum	_clock_output_divider {   kCLOCK_DivideBy1 = 0U,   kCLOCK_DivideBy2,   kCLOCK_DivideBy3,   kCLOCK_DivideBy4,   kCLOCK_DivideBy5,   kCLOCK_DivideBy6,   kCLOCK_DivideBy7,   kCLOCK_DivideBy8 }
	The enumerator of clock output's divider. More...
enum	_clock_root {   kCLOCK_FlexspiClkRoot = 0U,   kCLOCK_LpspiClkRoot,   kCLOCK_TraceClkRoot,   kCLOCK_Sai1ClkRoot,   kCLOCK_Sai2ClkRoot,   kCLOCK_Sai3ClkRoot,   kCLOCK_Lpi2cClkRoot,   kCLOCK_UartClkRoot,   kCLOCK_SpdifClkRoot,   kCLOCK_Flexio1ClkRoot }
	The enumerator of clock root. More...

Functions
static void	CLOCK_SetMux (clock_mux_t mux, uint32_t value)
	Set CCM MUX node to certain value. More...
static uint32_t	CLOCK_GetMux (clock_mux_t mux)
	Get CCM MUX value. More...
static void	CLOCK_SetDiv (clock_div_t divider, uint32_t value)
	Set clock divider value. More...
static uint32_t	CLOCK_GetDiv (clock_div_t divider)
	Get CCM DIV node value. More...
static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...
static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...
static void	CLOCK_SetMode (clock_mode_t mode)
	Setting the low power mode that system will enter on next assertion of dsm_request signal. More...
static uint32_t	CLOCK_GetOscFreq (void)
	Gets the OSC clock frequency. More...
uint32_t	CLOCK_GetAhbFreq (void)
	Gets the AHB clock frequency. More...
uint32_t	CLOCK_GetSemcFreq (void)
	Gets the SEMC clock frequency. More...
uint32_t	CLOCK_GetIpgFreq (void)
	Gets the IPG clock frequency. More...
uint32_t	CLOCK_GetPerClkFreq (void)
	Gets the PER clock frequency. More...
uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...
static uint32_t	CLOCK_GetCpuClkFreq (void)
	Get the CCM CPU/core/system frequency. More...
uint32_t	CLOCK_GetClockRootFreq (clock_root_t clockRoot)
	Gets the frequency of selected clock root. More...
bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

Variables
volatile uint32_t	g_xtalFreq
	External XTAL (24M OSC/SYSOSC) clock frequency. More...
volatile uint32_t	g_rtcXtalFreq
	External RTC XTAL (32K OSC) clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 3))
	CLOCK driver version 2.5.3. More...
#define	CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
#define	CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY   (500000000UL)

OSC operations
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock. More...
void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock. More...
void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC. More...
static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...
static void	CLOCK_SetXtalFreq (uint32_t freq)
	Set the XTAL (24M OSC) frequency based on board setting. More...
static void	CLOCK_SetRtcXtalFreq (uint32_t freq)
	Set the RTC XTAL (32K OSC) frequency based on board setting. More...
void	CLOCK_InitRcOsc24M (void)
	Initialize the RC oscillator 24MHz clock.
void	CLOCK_DeinitRcOsc24M (void)
	Power down the RCOSC 24M clock.

---

Data Structure Documentation

struct _clock_usb_pll_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...
uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

uint8_t _clock_usb_pll_config::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct _clock_sys_pll_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...
uint32_t	numerator
	30 bit numerator of fractional loop divider. More...
uint32_t	denominator
	30 bit denominator of fractional loop divider
uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.
uint16_t	ss_stop
	Stop value to get frequency change. More...
uint8_t	ss_enable
	Enable spread spectrum modulation.
uint16_t	ss_step
	Step value to get frequency change step. More...

Field Documentation

uint8_t _clock_sys_pll_config::loopDivider

Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22

uint32_t _clock_sys_pll_config::numerator

uint16_t _clock_sys_pll_config::ss_stop

uint16_t _clock_sys_pll_config::ss_step

struct _clock_audio_pll_config

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...
uint8_t	postDivider
	Divider after the PLL, should only be 1, 2, 4, 8, 16. More...
uint32_t	numerator
	30 bit numerator of fractional loop divider. More...
uint32_t	denominator
	30 bit denominator of fractional loop divider
uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

uint8_t _clock_audio_pll_config::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t _clock_audio_pll_config::postDivider

uint32_t _clock_audio_pll_config::numerator

struct _clock_enet_pll_config

Data Fields
bool	enableClkOutput
	Power on and enable PLL clock output for ENET0 (ref_enetpll0). More...
bool	enableClkOutput500M
	Power on and enable PLL clock output for ENET (ref_enetpll500M). More...
bool	enableClkOutput25M
	Power on and enable PLL clock output for ENET1 (ref_enetpll1). More...
uint8_t	loopDivider
	Controls the frequency of the ENET0 reference clock. More...
uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

bool _clock_enet_pll_config::enableClkOutput

bool _clock_enet_pll_config::enableClkOutput500M

bool _clock_enet_pll_config::enableClkOutput25M

uint8_t _clock_enet_pll_config::loopDivider

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 3))

#define ADC_CLOCKS

Value:

{                                 \
        kCLOCK_IpInvalid, kCLOCK_Adc1 \
    }

#define AOI_CLOCKS

Value:

{              \
        kCLOCK_Aoi \
    }

#define BEE_CLOCKS

Value:

{              \
        kCLOCK_Bee \
    }

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

#define DCP_CLOCKS

Value:

{              \
        kCLOCK_Dcp \
    }

#define DMAMUX_CLOCKS

Value:

{                 \
        kCLOCK_Dma    \
    }

#define EDMA_CLOCKS

Value:

{               \
        kCLOCK_Dma  \
    }

#define ENC_CLOCKS

Value:

{                                 \
        kCLOCK_IpInvalid, kCLOCK_Enc1 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define FLEXIO_CLOCKS

Value:

{                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1 \
    }

#define FLEXRAM_CLOCKS

Value:

{                  \
        kCLOCK_FlexRam \
    }

#define FLEXSPI_CLOCKS

Value:

{                  \
        kCLOCK_FlexSpi \
    }

#define GPIO_CLOCKS

Value:

{                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
    }

#define GPT_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
    }

#define KPP_CLOCKS

Value:

{              \
        kCLOCK_Kpp \
    }

#define LPI2C_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \
    }

#define LPSPI_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \
    }

#define LPUART_CLOCKS

Value:

{                                                                                    \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
    }

#define OCRAM_EXSC_CLOCKS

Value:

{                     \
        kCLOCK_OcramExsc  \
    }

#define PIT_CLOCKS

Value:

{              \
        kCLOCK_Pit \
    }

#define PWM_CLOCKS

Value:

{                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
        {                                                                         \
            kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1                    \
        }                                                                         \
    }

#define RTWDOG_CLOCKS

Value:

{                 \
        kCLOCK_Wdog3  \
    }

#define SAI_CLOCKS

Value:

{                                                           \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
    }

#define TMR_CLOCKS

Value:

{                                   \
        kCLOCK_IpInvalid, kCLOCK_Timer1 \
    }

#define TRNG_CLOCKS

Value:

{               \
        kCLOCK_Trng \
    }

#define WDOG_CLOCKS

Value:

{                                                \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
    }

#define SPDIF_CLOCKS

Value:

{                \
        kCLOCK_Spdif \
    }

#define XBARA_CLOCKS

Value:

{                \
        kCLOCK_Xbar1 \
    }

#define XBARB_CLOCKS

Value:

{                \
        kCLOCK_Xbar2 \
    }

#define kCLOCK_CoreSysClk   kCLOCK_CpuClk

#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq

Typedef Documentation

typedef enum _clock_name clock_name_t

typedef enum _clock_mux clock_mux_t

These constants define the mux control names for clock mux setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

typedef enum _clock_div clock_div_t

These constants define div control names for clock div setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

typedef enum _clock_usb_src clock_usb_src_t

typedef enum _clock_usb_phy_src clock_usb_phy_src_t

Enumeration Type Documentation

enum _clock_name

Enumerator
kCLOCK_CpuClk	CPU clock.
kCLOCK_AhbClk	AHB clock.
kCLOCK_SemcClk	SEMC clock.
kCLOCK_IpgClk	IPG clock.
kCLOCK_PerClk	PER clock.
kCLOCK_OscClk	OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL].
kCLOCK_RtcClk	RTC clock. (RTCCLK)
kCLOCK_Usb1PllClk	USB1PLLCLK.
kCLOCK_Usb1PllPfd0Clk	USB1PLLPDF0CLK.
kCLOCK_Usb1PllPfd1Clk	USB1PLLPFD1CLK.
kCLOCK_Usb1PllPfd2Clk	USB1PLLPFD2CLK.
kCLOCK_Usb1PllPfd3Clk	USB1PLLPFD3CLK.
kCLOCK_Usb1SwClk	USB1PLLSWCLK.
kCLOCK_Usb1Sw60MClk	USB1PLLSw60MCLK.
kCLOCK_Usb1Sw80MClk	USB1PLLSw80MCLK.
kCLOCK_SysPllClk	SYSPLLCLK.
kCLOCK_SysPllPfd0Clk	SYSPLLPDF0CLK.
kCLOCK_SysPllPfd1Clk	SYSPLLPFD1CLK.
kCLOCK_SysPllPfd2Clk	SYSPLLPFD2CLK.
kCLOCK_SysPllPfd3Clk	SYSPLLPFD3CLK.
kCLOCK_EnetPllClk	Enet PLLCLK ref_enetpll.
kCLOCK_EnetPll25MClk	Enet PLLCLK ref_enetpll25M.
kCLOCK_EnetPll500MClk	Enet PLLCLK ref_enetpll500M.
kCLOCK_AudioPllClk	Audio PLLCLK.
kCLOCK_NoneName	None Clock Name.

enum _clock_ip_name

Enumerator
kCLOCK_Aips_tz1	CCGR0, CG0.
kCLOCK_Aips_tz2	CCGR0, CG1.
kCLOCK_Mqs	CCGR0, CG2.
kCLOCK_Sim_m_clk_r	CCGR0, CG4.
kCLOCK_Dcp	CCGR0, CG5.
kCLOCK_Lpuart3	CCGR0, CG6.
kCLOCK_Trace	CCGR0, CG11.
kCLOCK_Gpt2	CCGR0, CG12.
kCLOCK_Gpt2S	CCGR0, CG13.
kCLOCK_Lpuart2	CCGR0, CG14.
kCLOCK_Gpio2	CCGR0, CG15.
kCLOCK_Lpspi1	CCGR1, CG0.
kCLOCK_Lpspi2	CCGR1, CG1.
kCLOCK_Pit	CCGR1, CG6.
kCLOCK_Adc1	CCGR1, CG8.
kCLOCK_Gpt1	CCGR1, CG10.
kCLOCK_Gpt1S	CCGR1, CG11.
kCLOCK_Lpuart4	CCGR1, CG12.
kCLOCK_Gpio1	CCGR1, CG13.
kCLOCK_Csu	CCGR1, CG14.
kCLOCK_Gpio5	CCGR1, CG15.
kCLOCK_OcramExsc	CCGR2, CG0.
kCLOCK_IomuxcSnvs	CCGR2, CG2.
kCLOCK_Lpi2c1	CCGR2, CG3.
kCLOCK_Lpi2c2	CCGR2, CG4.
kCLOCK_Ocotp	CCGR2, CG6.
kCLOCK_Xbar1	CCGR2, CG11.
kCLOCK_Xbar2	CCGR2, CG12.
kCLOCK_Gpio3	CCGR2, CG13.
kCLOCK_Aoi	CCGR3, CG4.
kCLOCK_Ewm0	CCGR3, CG7.
kCLOCK_Wdog1	CCGR3, CG8.
kCLOCK_FlexRam	CCGR3, CG9.
kCLOCK_IomuxcSnvsGpr	CCGR3, CG15.
kCLOCK_Sim_m7_clk_r	CCGR4, CG0.
kCLOCK_Iomuxc	CCGR4, CG1.
kCLOCK_IomuxcGpr	CCGR4, CG2.
kCLOCK_Bee	CCGR4, CG3.
kCLOCK_SimM7	CCGR4, CG4.
kCLOCK_SimM	CCGR4, CG6.
kCLOCK_SimEms	CCGR4, CG7.
kCLOCK_Pwm1	CCGR4, CG8.
kCLOCK_Enc1	CCGR4, CG12.
kCLOCK_Rom	CCGR5, CG0.
kCLOCK_Flexio1	CCGR5, CG1.
kCLOCK_Wdog3	CCGR5, CG2.
kCLOCK_Dma	CCGR5, CG3.
kCLOCK_Kpp	CCGR5, CG4.
kCLOCK_Wdog2	CCGR5, CG5.
kCLOCK_Aips_tz4	CCGR5, CG6.
kCLOCK_Spdif	CCGR5, CG7.
kCLOCK_Sai1	CCGR5, CG9.
kCLOCK_Sai2	CCGR5, CG10.
kCLOCK_Sai3	CCGR5, CG11.
kCLOCK_Lpuart1	CCGR5, CG12.
kCLOCK_SnvsHp	CCGR5, CG14.
kCLOCK_SnvsLp	CCGR5, CG15.
kCLOCK_UsbOh3	CCGR6, CG0.
kCLOCK_Dcdc	CCGR6, CG3.
kCLOCK_FlexSpi	CCGR6, CG5.
kCLOCK_Trng	CCGR6, CG6.
kCLOCK_Aips_tz3	CCGR6, CG9.
kCLOCK_SimPer	CCGR6, CG10.
kCLOCK_Anadig	CCGR6, CG11.
kCLOCK_Timer1	CCGR6, CG13.

enum _clock_osc

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

enum _clock_gate_value

Enumerator
kCLOCK_ClockNotNeeded	Clock is off during all modes.
kCLOCK_ClockNeededRun	Clock is on in run mode, but off in WAIT and STOP modes.
kCLOCK_ClockNeededRunWait	Clock is on during all modes, except STOP mode.

enum _clock_mode_t

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

enum _clock_mux

These constants define the mux control names for clock mux setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

Enumerator
kCLOCK_Pll3SwMux	pll3_sw_clk mux name
kCLOCK_PeriphMux	periph mux name
kCLOCK_SemcAltMux	semc mux name
kCLOCK_SemcMux	semc mux name
kCLOCK_PrePeriphMux	pre-periph mux name
kCLOCK_TraceMux	trace mux name
kCLOCK_PeriphClk2Mux	periph clock2 mux name
kCLOCK_LpspiMux	lpspi mux name
kCLOCK_FlexspiMux	flexspi mux name
kCLOCK_Sai3Mux	sai3 mux name
kCLOCK_Sai2Mux	sai2 mux name
kCLOCK_Sai1Mux	sai1 mux name
kCLOCK_PerclkMux	perclk mux name
kCLOCK_Flexio1Mux	flexio1 mux name
kCLOCK_UartMux	uart mux name
kCLOCK_SpdifMux	spdif mux name
kCLOCK_Lpi2cMux	lpi2c mux name

enum _clock_div

These constants define div control names for clock div setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

Enumerator
kCLOCK_ArmDiv	core div name
kCLOCK_PeriphClk2Div	periph clock2 div name
kCLOCK_SemcDiv	semc div name
kCLOCK_AhbDiv	ahb div name
kCLOCK_IpgDiv	ipg div name
kCLOCK_LpspiDiv	lpspi div name
kCLOCK_FlexspiDiv	flexspi div name
kCLOCK_PerclkDiv	perclk div name
kCLOCK_TraceDiv	trace div name
kCLOCK_UartDiv	uart div name
kCLOCK_Flexio1Div	flexio1 pre div name
kCLOCK_Sai3PreDiv	sai3 pre div name
kCLOCK_Sai3Div	sai3 div name
kCLOCK_Flexio1PreDiv	flexio1 pre div name
kCLOCK_Sai1PreDiv	sai1 pre div name
kCLOCK_Sai1Div	sai1 div name
kCLOCK_Sai2PreDiv	sai2 pre div name
kCLOCK_Sai2Div	sai2 div name
kCLOCK_Spdif0PreDiv	spdif pre div name
kCLOCK_Spdif0Div	spdif div name
kCLOCK_Lpi2cDiv	lpi2c div name
kCLOCK_NonePreDiv	None Pre div.

enum _clock_div_value

Enumerator
kCLOCK_ArmDivBy1	ARM clock divider set to divided by 1.
kCLOCK_ArmDivBy2	ARM clock divider set to divided by 2.
kCLOCK_ArmDivBy3	ARM clock divider set to divided by 3.
kCLOCK_ArmDivBy4	ARM clock divider set to divided by 4.
kCLOCK_ArmDivBy5	ARM clock divider set to divided by 5.
kCLOCK_ArmDivBy6	ARM clock divider set to divided by 6.
kCLOCK_ArmDivBy7	ARM clock divider set to divided by 7.
kCLOCK_ArmDivBy8	ARM clock divider set to divided by 8.
kCLOCK_PeriphClk2DivBy1	periph clock2 divider set to divided by 1.
kCLOCK_PeriphClk2DivBy2	periph clock2 divider set to divided by 2.
kCLOCK_PeriphClk2DivBy3	periph clock2 divider set to divided by 3.
kCLOCK_PeriphClk2DivBy4	periph clock2 divider set to divided by 4.
kCLOCK_PeriphClk2DivBy5	periph clock2 divider set to divided by 5.
kCLOCK_PeriphClk2DivBy6	periph clock2 divider set to divided by 6.
kCLOCK_PeriphClk2DivBy7	periph clock2 divider set to divided by 7.
kCLOCK_PeriphClk2DivBy8	periph clock2 divider set to divided by 8.
kCLOCK_SemcDivBy1	semc clock divider set to divided by 1.
kCLOCK_SemcDivBy2	semc clock divider set to divided by 2.
kCLOCK_SemcDivBy3	semc clock divider set to divided by 3.
kCLOCK_SemcDivBy4	semc clock divider set to divided by 4.
kCLOCK_SemcDivBy5	semc clock divider set to divided by 5.
kCLOCK_SemcDivBy6	semc clock divider set to divided by 6.
kCLOCK_SemcDivBy7	semc clock divider set to divided by 7.
kCLOCK_SemcDivBy8	semc clock divider set to divided by 8.
kCLOCK_AhbDivBy1	Ahb clock divider set to divided by 1.
kCLOCK_AhbDivBy2	Ahb clock divider set to divided by 2.
kCLOCK_AhbDivBy3	Ahb clock divider set to divided by 3.
kCLOCK_AhbDivBy4	Ahb clock divider set to divided by 4.
kCLOCK_AhbDivBy5	Ahb clock divider set to divided by 5.
kCLOCK_AhbDivBy6	Ahb clock divider set to divided by 6.
kCLOCK_AhbDivBy7	Ahb clock divider set to divided by 7.
kCLOCK_AhbDivBy8	Ahb clock divider set to divided by 8.
kCLOCK_IpgDivBy1	ipg clock divider set to divided by 1.
kCLOCK_IpgDivBy2	ipg clock divider set to divided by 2.
kCLOCK_IpgDivBy3	ipg clock divider set to divided by 3.
kCLOCK_IpgDivBy4	ipg clock divider set to divided by 4.
kCLOCK_LpspiDivBy1	lpspi clock divider set to divided by 1.
kCLOCK_LpspiDivBy2	lpspi clock divider set to divided by 2.
kCLOCK_LpspiDivBy3	lpspi clock divider set to divided by 3.
kCLOCK_LpspiDivBy4	lpspi clock divider set to divided by 4.
kCLOCK_LpspiDivBy5	lpspi clock divider set to divided by 5.
kCLOCK_LpspiDivBy6	lpspi clock divider set to divided by 6.
kCLOCK_LpspiDivBy7	lpspi clock divider set to divided by 7.
kCLOCK_LpspiDivBy8	lpspi clock divider set to divided by 8.
kCLOCK_FlexspiDivBy1	flexspi clock divider set to divided by 1.
kCLOCK_FlexspiDivBy2	flexspi clock divider set to divided by 2.
kCLOCK_FlexspiDivBy3	flexspi clock divider set to divided by 3.
kCLOCK_FlexspiDivBy4	flexspi clock divider set to divided by 4.
kCLOCK_FlexspiDivBy5	flexspi clock divider set to divided by 5.
kCLOCK_FlexspiDivBy6	flexspi clock divider set to divided by 6.
kCLOCK_FlexspiDivBy7	flexspi clock divider set to divided by 7.
kCLOCK_FlexspiDivBy8	flexspi clock divider set to divided by 8.
kCLOCK_TraceDivBy1	trace clock divider set to divided by 1.
kCLOCK_TraceDivBy2	trace clock divider set to divided by 2.
kCLOCK_TraceDivBy3	trace clock divider set to divided by 3.
kCLOCK_TraceDivBy4	trace clock divider set to divided by 4.
kCLOCK_Flexio1DivBy1	flexio1 clock divider set to divided by 1.
kCLOCK_Flexio1DivBy2	flexio1 clock divider set to divided by 2.
kCLOCK_Flexio1DivBy3	flexio1 clock divider set to divided by 3.
kCLOCK_Flexio1DivBy4	flexio1 clock divider set to divided by 4.
kCLOCK_Flexio1DivBy5	flexio1 clock divider set to divided by 5.
kCLOCK_Flexio1DivBy6	flexio1 clock divider set to divided by 6.
kCLOCK_Flexio1DivBy7	flexio1 clock divider set to divided by 7.
kCLOCK_Flexio1DivBy8	flexio1 clock divider set to divided by 8.
kCLOCK_Sai3PreDivBy1	sai3 pre clock divider set to divided by 1.
kCLOCK_Sai3PreDivBy2	sai3 pre clock divider set to divided by 2.
kCLOCK_Sai3PreDivBy3	sai3 pre clock divider set to divided by 3.
kCLOCK_Sai3PreDivBy4	sai3 pre clock divider set to divided by 4.
kCLOCK_Sai3PreDivBy5	sai3 pre clock divider set to divided by 5.
kCLOCK_Sai3PreDivBy6	sai3 pre clock divider set to divided by 6.
kCLOCK_Sai3PreDivBy7	sai3 pre clock divider set to divided by 7.
kCLOCK_Sai3PreDivBy8	sai3 pre clock divider set to divided by 8.
kCLOCK_Flexio1PreDivBy1	flexio1 pre clock divider set to divided by 1.
kCLOCK_Flexio1PreDivBy2	flexio1 pre clock divider set to divided by 2.
kCLOCK_Flexio1PreDivBy3	flexio1 pre clock divider set to divided by 3.
kCLOCK_Flexio1PreDivBy4	flexio1 pre clock divider set to divided by 4.
kCLOCK_Flexio1PreDivBy5	flexio1 pre clock divider set to divided by 5.
kCLOCK_Flexio1PreDivBy6	flexio1 pre clock divider set to divided by 6.
kCLOCK_Flexio1PreDivBy7	flexio1 pre clock divider set to divided by 7.
kCLOCK_Flexio1PreDivBy8	flexio1 pre clock divider set to divided by 8.
kCLOCK_Sai1PreDivBy1	sai1 pre clock divider set to divided by 1.
kCLOCK_Sai1PreDivBy2	sai1 pre clock divider set to divided by 2.
kCLOCK_Sai1PreDivBy3	sai1 pre clock divider set to divided by 3.
kCLOCK_Sai1PreDivBy4	sai1 pre clock divider set to divided by 4.
kCLOCK_Sai1PreDivBy5	sai1 pre clock divider set to divided by 5.
kCLOCK_Sai1PreDivBy6	sai1 pre clock divider set to divided by 6.
kCLOCK_Sai1PreDivBy7	sai1 pre clock divider set to divided by 7.
kCLOCK_Sai1PreDivBy8	sai1 pre clock divider set to divided by 8.
kCLOCK_Sai2PreDivBy1	sai2 pre clock divider set to divided by 1.
kCLOCK_Sai2PreDivBy2	sai2 pre clock divider set to divided by 2.
kCLOCK_Sai2PreDivBy3	sai2 pre clock divider set to divided by 3.
kCLOCK_Sai2PreDivBy4	sai2 pre clock divider set to divided by 4.
kCLOCK_Sai2PreDivBy5	sai2 pre clock divider set to divided by 5.
kCLOCK_Sai2PreDivBy6	sai2 pre clock divider set to divided by 6.
kCLOCK_Sai2PreDivBy7	sai2 pre clock divider set to divided by 7.
kCLOCK_Sai2PreDivBy8	sai2 pre clock divider set to divided by 8.
kCLOCK_Spdif0PreDivBy1	spdif pre clock divider set to divided by 1.
kCLOCK_Spdif0PreDivBy2	spdif pre clock divider set to divided by 2.
kCLOCK_Spdif0PreDivBy3	spdif pre clock divider set to divided by 3.
kCLOCK_Spdif0PreDivBy4	spdif pre clock divider set to divided by 4.
kCLOCK_Spdif0PreDivBy5	spdif pre clock divider set to divided by 5.
kCLOCK_Spdif0PreDivBy6	spdif pre clock divider set to divided by 6.
kCLOCK_Spdif0PreDivBy7	spdif pre clock divider set to divided by 7.
kCLOCK_Spdif0PreDivBy8	spdif pre clock divider set to divided by 8.
kCLOCK_Spdif0DivBy1	spdif clock divider set to divided by 1.
kCLOCK_Spdif0DivBy2	spdif clock divider set to divided by 2.
kCLOCK_Spdif0DivBy3	spdif clock divider set to divided by 3.
kCLOCK_Spdif0DivBy4	spdif clock divider set to divided by 4.
kCLOCK_Spdif0DivBy5	spdif clock divider set to divided by 5.
kCLOCK_Spdif0DivBy6	spdif clock divider set to divided by 6.
kCLOCK_Spdif0DivBy7	spdif clock divider set to divided by 7.
kCLOCK_Spdif0DivBy8	spdif clock divider set to divided by 8.
kCLOCK_MiscDivBy1	Misc divider like LPI2C set to divided by 1.
kCLOCK_MiscDivBy2	Misc divider like LPI2C set to divided by 2.
kCLOCK_MiscDivBy3	Misc divider like LPI2C set to divided by 3.
kCLOCK_MiscDivBy4	Misc divider like LPI2C set to divided by 4.
kCLOCK_MiscDivBy5	Misc divider like LPI2C set to divided by 5.
kCLOCK_MiscDivBy6	Misc divider like LPI2C set to divided by 6.
kCLOCK_MiscDivBy7	Misc divider like LPI2C set to divided by 7.
kCLOCK_MiscDivBy8	Misc divider like LPI2C set to divided by 8.
kCLOCK_MiscDivBy9	Misc divider like LPI2C set to divided by 9.
kCLOCK_MiscDivBy10	Misc divider like LPI2C set to divided by 10.
kCLOCK_MiscDivBy11	Misc divider like LPI2C set to divided by 11.
kCLOCK_MiscDivBy12	Misc divider like LPI2C set to divided by 12.
kCLOCK_MiscDivBy13	Misc divider like LPI2C set to divided by 13.
kCLOCK_MiscDivBy14	Misc divider like LPI2C set to divided by 14.
kCLOCK_MiscDivBy15	Misc divider like LPI2C set to divided by 15.
kCLOCK_MiscDivBy16	Misc divider like LPI2C set to divided by 16.
kCLOCK_MiscDivBy17	Misc divider like LPI2C set to divided by 17.
kCLOCK_MiscDivBy18	Misc divider like LPI2C set to divided by 18.
kCLOCK_MiscDivBy19	Misc divider like LPI2C set to divided by 19.
kCLOCK_MiscDivBy20	Misc divider like LPI2C set to divided by 20.
kCLOCK_MiscDivBy21	Misc divider like LPI2C set to divided by 21.
kCLOCK_MiscDivBy22	Misc divider like LPI2C set to divided by 22.
kCLOCK_MiscDivBy23	Misc divider like LPI2C set to divided by 23.
kCLOCK_MiscDivBy24	Misc divider like LPI2C set to divided by 24.
kCLOCK_MiscDivBy25	Misc divider like LPI2C set to divided by 25.
kCLOCK_MiscDivBy26	Misc divider like LPI2C set to divided by 26.
kCLOCK_MiscDivBy27	Misc divider like LPI2C set to divided by 27.
kCLOCK_MiscDivBy28	Misc divider like LPI2C set to divided by 28.
kCLOCK_MiscDivBy29	Misc divider like LPI2C set to divided by 29.
kCLOCK_MiscDivBy30	Misc divider like LPI2C set to divided by 30.
kCLOCK_MiscDivBy31	Misc divider like LPI2C set to divided by 31.
kCLOCK_MiscDivBy32	Misc divider like LPI2C set to divided by 32.
kCLOCK_MiscDivBy33	Misc divider like LPI2C set to divided by 33.
kCLOCK_MiscDivBy34	Misc divider like LPI2C set to divided by 34.
kCLOCK_MiscDivBy35	Misc divider like LPI2C set to divided by 35.
kCLOCK_MiscDivBy36	Misc divider like LPI2C set to divided by 36.
kCLOCK_MiscDivBy37	Misc divider like LPI2C set to divided by 37.
kCLOCK_MiscDivBy38	Misc divider like LPI2C set to divided by 38.
kCLOCK_MiscDivBy39	Misc divider like LPI2C set to divided by 39.
kCLOCK_MiscDivBy40	Misc divider like LPI2C set to divided by 40.
kCLOCK_MiscDivBy41	Misc divider like LPI2C set to divided by 41.
kCLOCK_MiscDivBy42	Misc divider like LPI2C set to divided by 42.
kCLOCK_MiscDivBy43	Misc divider like LPI2C set to divided by 43.
kCLOCK_MiscDivBy44	Misc divider like LPI2C set to divided by 44.
kCLOCK_MiscDivBy45	Misc divider like LPI2C set to divided by 45.
kCLOCK_MiscDivBy46	Misc divider like LPI2C set to divided by 46.
kCLOCK_MiscDivBy47	Misc divider like LPI2C set to divided by 47.
kCLOCK_MiscDivBy48	Misc divider like LPI2C set to divided by 48.
kCLOCK_MiscDivBy49	Misc divider like LPI2C set to divided by 49.
kCLOCK_MiscDivBy50	Misc divider like LPI2C set to divided by 50.
kCLOCK_MiscDivBy51	Misc divider like LPI2C set to divided by 51.
kCLOCK_MiscDivBy52	Misc divider like LPI2C set to divided by 52.
kCLOCK_MiscDivBy53	Misc divider like LPI2C set to divided by 53.
kCLOCK_MiscDivBy54	Misc divider like LPI2C set to divided by 54.
kCLOCK_MiscDivBy55	Misc divider like LPI2C set to divided by 55.
kCLOCK_MiscDivBy56	Misc divider like LPI2C set to divided by 56.
kCLOCK_MiscDivBy57	Misc divider like LPI2C set to divided by 57.
kCLOCK_MiscDivBy58	Misc divider like LPI2C set to divided by 58.
kCLOCK_MiscDivBy59	Misc divider like LPI2C set to divided by 59.
kCLOCK_MiscDivBy60	Misc divider like LPI2C set to divided by 60.
kCLOCK_MiscDivBy61	Misc divider like LPI2C set to divided by 61.
kCLOCK_MiscDivBy62	Misc divider like LPI2C set to divided by 62.
kCLOCK_MiscDivBy63	Misc divider like LPI2C set to divided by 63.
kCLOCK_MiscDivBy64	Misc divider like LPI2C set to divided by 64.

enum _clock_usb_src

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

enum _clock_usb_phy_src

Enumerator
kCLOCK_Usbphy480M	Use 480M.

enum _clock_pll_clk_src

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M.
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N.

enum _clock_pll

Enumerator
kCLOCK_PllSys	PLL SYS.
kCLOCK_PllUsb1	PLL USB1.
kCLOCK_PllAudio	PLL Audio.
kCLOCK_PllEnet500M	PLL ENET.

enum _clock_pfd

Enumerator
kCLOCK_Pfd0	PLL PFD0.
kCLOCK_Pfd1	PLL PFD1.
kCLOCK_Pfd2	PLL PFD2.
kCLOCK_Pfd3	PLL PFD3.

enum _clock_output1_selection

Enumerator
kCLOCK_OutputPllUsb1Sw	Selects USB1 PLL SW clock(Divided by 2) output.
kCLOCK_OutputPllSys	Selects SYS PLL clock(Divided by 2) output.
kCLOCK_OutputPllENET	Selects ENET PLL clock(Divided by 2) output.
kCLOCK_OutputAhbClk	Selects AHB clock root output.
kCLOCK_OutputIpgClk	Selects IPG clock root output.
kCLOCK_OutputPerClk	Selects PERCLK clock root output.
kCLOCK_OutputPll4MainClk	Selects PLL4 main clock output.
kCLOCK_DisableClockOutput1	Disables CLKO1.

enum _clock_output2_selection

Enumerator
kCLOCK_OutputLpi2cClk	Selects LPI2C clock root output.
kCLOCK_OutputOscClk	Selects OSC output.
kCLOCK_OutputLpspiClk	Selects LPSPI clock root output.
kCLOCK_OutputSai1Clk	Selects SAI1 clock root output.
kCLOCK_OutputSai2Clk	Selects SAI2 clock root output.
kCLOCK_OutputSai3Clk	Selects SAI3 clock root output.
kCLOCK_OutputTraceClk	Selects Trace clock root output.
kCLOCK_OutputFlexspiClk	Selects FLEXSPI clock root output.
kCLOCK_OutputUartClk	Selects UART clock root output.
kCLOCK_OutputSpdif0Clk	Selects SPDIF0 clock root output.
kCLOCK_DisableClockOutput2	Disables CLKO2.

enum _clock_output_divider

Enumerator
kCLOCK_DivideBy1	Output clock divided by 1.
kCLOCK_DivideBy2	Output clock divided by 2.
kCLOCK_DivideBy3	Output clock divided by 3.
kCLOCK_DivideBy4	Output clock divided by 4.
kCLOCK_DivideBy5	Output clock divided by 5.
kCLOCK_DivideBy6	Output clock divided by 6.
kCLOCK_DivideBy7	Output clock divided by 7.
kCLOCK_DivideBy8	Output clock divided by 8.

enum _clock_root

Enumerator
kCLOCK_FlexspiClkRoot	FLEXSPI clock root.
kCLOCK_LpspiClkRoot	LPSPI clock root.
kCLOCK_TraceClkRoot	Trace clock root.
kCLOCK_Sai1ClkRoot	SAI1 clock root.
kCLOCK_Sai2ClkRoot	SAI2 clock root.
kCLOCK_Sai3ClkRoot	SAI3 clock root.
kCLOCK_Lpi2cClkRoot	LPI2C clock root.
kCLOCK_UartClkRoot	UART clock root.
kCLOCK_SpdifClkRoot	SPDIF clock root.
kCLOCK_Flexio1ClkRoot	FLEXIO1 clock root.

Function Documentation

static void CLOCK_SetMux ( clock_mux_t  mux, uint32_t  value  )

inlinestatic

Parameters

mux	Which mux node to set, see clock_mux_t.
value	Clock mux value to set, different mux has different value range.

static uint32_t CLOCK_GetMux ( clock_mux_t  mux )

inlinestatic

Parameters

mux	Which mux node to get, see clock_mux_t.

Returns

Clock mux value.

static void CLOCK_SetDiv ( clock_div_t  divider, uint32_t  value  )

inlinestatic

Example, set the ARM clock divider to divide by 2:

CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2);

Example, set the LPI2C clock divider to divide by 5.

CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5);

Only kCLOCK_PerclkDiv, kCLOCK_UartDiv, kCLOCK_Sai3Div, kCLOCK_Sai1Div, kCLOCK_Sai2Div, kCLOCK_Lpi2cDiv can use the divider kCLOCK_MiscDivByxxx.

Parameters

divider	Which divider node to set.
value	Clock div value to set, different divider has different value range. See clock_div_value_t for details. Divided clock frequency = Undivided clock frequency / (value + 1)

static uint32_t CLOCK_GetDiv ( clock_div_t  divider )

inlinestatic

Parameters

divider

Which div node to get, see clock_div_t.

static void CLOCK_ControlGate ( clock_ip_name_t  name, clock_gate_value_t  value  )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.
value	Clock gate value to set, see clock_gate_value_t.

static void CLOCK_EnableClock ( clock_ip_name_t  name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t  name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

static void CLOCK_SetMode ( clock_mode_t  mode )

inlinestatic

Parameters

mode	Which mode to enter, see clock_mode_t.

static uint32_t CLOCK_GetOscFreq ( void  )

inlinestatic

This function will return the external XTAL OSC frequency if it is selected as the source of OSC, otherwise internal 24MHz RC OSC frequency will be returned.

Returns

Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAhbFreq

(

void

)

Returns

The AHB clock frequency value in hertz.

uint32_t CLOCK_GetSemcFreq

(

void

)

Returns

The SEMC clock frequency value in hertz.

uint32_t CLOCK_GetIpgFreq

(

void

)

Returns

The IPG clock frequency value in hertz.

uint32_t CLOCK_GetPerClkFreq

(

void

)

Returns

The PER clock frequency value in hertz.

uint32_t CLOCK_GetFreq

(

clock_name_t

name

)

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

static uint32_t CLOCK_GetCpuClkFreq ( void  )

inlinestatic

Returns

Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetClockRootFreq

(

clock_root_t

clockRoot

)

Parameters

clockRoot

The clock root used to get the frequency, please refer to clock_root_t.

Returns

The frequency of selected clock root.

void CLOCK_InitExternalClk

(

bool

bypassXtalOsc

)

This function supports two modes:

1. Use external crystal oscillator.
2. Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters

bypassXtalOsc

Pass in true to bypass the external crystal oscillator.

Note

This device does not support bypass external crystal oscillator, so the input parameter should always be false.

void CLOCK_DeinitExternalClk

(

void

)

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

void CLOCK_SwitchOsc

(

clock_osc_t

osc

)

This function switches the OSC source for SoC.

Parameters

osc	OSC source to switch to.

static uint32_t CLOCK_GetRtcFreq ( void  )

inlinestatic

Returns

Clock frequency; If the clock is invalid, returns 0.

static void CLOCK_SetXtalFreq ( uint32_t  freq )

inlinestatic

Parameters

freq	The XTAL input clock frequency in Hz.

static void CLOCK_SetRtcXtalFreq ( uint32_t  freq )

inlinestatic

Parameters

freq	The RTC XTAL input clock frequency in Hz.

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

Variable Documentation

volatile uint32_t g_xtalFreq

The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 24MHz,

* CLOCK_InitExternalClk(false);
* CLOCK_SetXtalFreq(240000000);
* 

volatile uint32_t g_rtcXtalFreq

The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetRtcXtalFreq to set the value in to clock driver.