This document consists of sections titled with Driver Overview, Data Structures, Enumerations, Functions, etc., each with an overview list and detailed documentation. It is recommended to read the Driver Overview first for it includes a comprehensive description of the peripheral, driver and driver changes. Other sections give detailed information for APIs, enums, macros, etc., for your further reference.
|
| #define | INTC_DisableIRQ(x) INTC_SetIRQPriorityLevel(x, 0U) |
| | Macro to disable the IRQ. More...
|
| |
| #define | INTC_PEND_REG_INDEX(x) ((((uint16_t)(x)) - 1U) >> 4U) |
| | Helper Macro function to extract IRQ pending register index comparing to INTC_IRQP0. More...
|
| |
| #define | INTC_PEND_BIT_INDEX(x) ((((uint16_t)(x)) - 1U) & 0x0FU) |
| | Helper Macro function to extract pending IRQs bit index. More...
|
| |
| #define | INTC_TYPE_REG_INDEX(x) (((uint8_t)(x)) >> 3U) |
| | Helper Macro function to extract IRQ priority register index comparing to INTC_IRP0. More...
|
| |
| #define | INTC_TYPE_BIT_INDEX(x) ((((uint8_t)(x)) & 0x7U) << 1U) |
| | Helper Macro function to extract IRQs priority bit index. More...
|
| |
| #define INTC_DisableIRQ |
( |
|
x | ) |
INTC_SetIRQPriorityLevel(x, 0U) |
| #define INTC_PEND_REG_INDEX |
( |
|
x | ) |
((((uint16_t)(x)) - 1U) >> 4U) |
| #define INTC_PEND_BIT_INDEX |
( |
|
x | ) |
((((uint16_t)(x)) - 1U) & 0x0FU) |
| #define INTC_TYPE_REG_INDEX |
( |
|
x | ) |
(((uint8_t)(x)) >> 3U) |
| #define INTC_TYPE_BIT_INDEX |
( |
|
x | ) |
((((uint8_t)(x)) & 0x7U) << 1U) |
| typedef void(* fast_irq_handler)(void) |
Normally this function should be guarded by: #pragma interrupt fast and #pragma interrupt off.
| static void INTC_SetIRQPriorityNum |
( |
IRQn_Type |
eIrq, |
|
|
uint8_t |
u8PriorityNum |
|
) |
| |
|
inlinestatic |
There are similar function in fsl_common:
- EnableIRQWithPriority,
- DisableIRQ,
- EnableIRQ,
- IRQ_SetPriority.
This function is faster and simpler than those in fsl_common. Generally, this function and IRQ functions in fsl_common are either-or, don't use them together for same IRQn type, but feasible that different IRQn type use them simultaneously, for example: It is OK OCCS_IRQn use INTC_SetIRQPriorityLevel, and ADC12_CC1_IRQn use EnableIRQWithPriority. It is NOT OK that OCCS_IRQn use INTC_SetIRQPriorityLevel and EnableIRQWithPriority simultaneously.
- Parameters
-
| eIrq | The IRQ number. |
| u8PriorityNum | IRQ interrupt priority number.
- 0: disable IRQ.
- 1-3: enable IRQ and set its priority, 3 is the highest priority for this IRQ and 1 is the lowest priority.
|
- Note
- Please note a none-zero priority number does directly map to priority level, simple summary is as below, you could check RM INTC chapter for more details.
- Some IPs have priority level 1~3, maps priority number 1 to priority 1, 2 to priority 2, 3 to priority 3.
- Some IPs have priority level 0~2, maps priority number 1 to priority 0, 2 to priority 1, 3 to priority 2.
| static void INTC_SetVectorBaseAddress |
( |
uint32_t |
u32VectorBaseAddr | ) |
|
|
inlinestatic |
The value in INTC_VBA is used as the upper 13 bits of the interrupt vector VAB[20:0].
- Parameters
-
| u32VectorBaseAddr | Vector table base address. The address requires 256 words (512 bytes) aligned. Take the vector table in MC56F83xxx_Vectors.c as example for how to implement this table. |
| static void INTC_SetFastIRQVectorHandler0 |
( |
vector_type_t |
eVector, |
|
|
fast_irq_handler |
pfHandler |
|
) |
| |
|
inlinestatic |
The INTC takes the vector address from the appropriate FIVAL0 and FIVAH0 registers, instead of generating an address that is an offset from the vector base address (VBA).
- Parameters
-
| eVector | The vector number. |
| pfHandler | Pointer to the fast IRQ handler function, see fast_irq_handler definition for more info. |
| static void INTC_SetFastIRQVectorHandler1 |
( |
vector_type_t |
eVector, |
|
|
fast_irq_handler |
pfHandler |
|
) |
| |
|
inlinestatic |
The INTC takes the vector address from the appropriate FIVAL1 and FIVAH1 registers, instead of generating an address that is an offset from the vector base address (VBA).
- Parameters
-
| eVector | The eVector number. |
| pfHandler | Pointer to the fast IRQ handler function, see @ ref fast_irq_handler definition for more info. |
| static uint8_t INTC_GetIRQPermittedPriorityLevel |
( |
void |
| ) |
|
|
inlinestatic |
Interrupt exceptions may be nested to allow the servicing of an IRQ with higher priority than the current exception.
The return value indicate the priority level needed for a new IRQ to interrupt the current interrupt being sent to the Core.
- Return values
-
| 0 | Required nested exception priority levels are 0, 1, 2, or 3. |
| 1 | Required nested exception priority levels are 1, 2, or 3. |
| 2 | Required nested exception priority levels are 2 or 3. |
| 3 | Required nested exception priority level is 3. |
| static bool INTC_GetPendingIRQ |
( |
vector_type_t |
eVector | ) |
|
|
inlinestatic |
Before the ISR is entered, IRQ is pending. After the ISR is entered, the IRQ is not pending.
- Parameters
-
| eVector | The IRQ vector number. |
- Return values
-
| True | if interrupt is pending, otherwise return false. |
| static uint16_t INTC_GetLatestRespondedVectorNumber |
( |
void |
| ) |
|
|
inlinestatic |
It shows the Vector Address Bus used at the time the last IRQ was taken.
- Note
- Return value of the function call could be different according to where the function call is invoked.
- when called in normal ISR handler, it returns current ISR's vector number defined in vector_type_t.
- when called in fast IRQ handler, it returns the lower address bits of the jump address.
- when called in none ISR handler code, it returns previous responded IRQ vector number defined in vector_type_t or fast IRQ low address bits.
- Returns
- The latest vector number.
