Overview

The MCUXpresso SDK provides a driver for the MECC module of MCUXpresso SDK devices.

The MECC64 module supports Single Error Correction and Double Error Detection(SECDED) ECC function to provide reliability for 4 banks On-Chip RAM(OCRAM) access.

This example code shows how to correct single error and detect multiple error using the MECC driver.

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mecc

Data Structures
struct	_mecc_config
	MECC user configuration. More...

struct	_mecc_single_error_info
	MECC ocram single error information, including single error address, ECC code, error data and error bit position. More...

struct	_mecc_multi_error_info
	MECC ocram multiple error information, including multiple error address, ECC code, error data. More...

Typedefs
typedef struct _mecc_config	mecc_config_t
	MECC user configuration. More...

typedef struct _mecc_single_error_info	mecc_single_error_info_t
	MECC ocram single error information, including single error address, ECC code, error data and error bit position.

typedef struct _mecc_multi_error_info	mecc_multi_error_info_t
	MECC ocram multiple error information, including multiple error address, ECC code, error data.

Enumerations
enum	{ kStatus_MECC_BankMiss = MAKE_STATUS(kStatusGroup_MECC, 0) }
	Error codes for the MECC driver. More...

enum	{ kMECC_SingleError0InterruptEnable = MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK, kMECC_SingleError1InterruptEnable = MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK, kMECC_SingleError2InterruptEnable = MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK, kMECC_SingleError3InterruptEnable = MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK, kMECC_MultiError0InterruptEnable = MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK, kMECC_MultiError1InterruptEnable = MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK, kMECC_MultiError2InterruptEnable = MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK, kMECC_MultiError3InterruptEnable = MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK, kMECC_StrobeError0InterruptEnable = MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK, kMECC_StrobeError1InterruptEnable = MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK, kMECC_StrobeError2InterruptEnable = MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK, kMECC_StrobeError3InterruptEnable = MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK, kMECC_AccessError0InterruptEnable = MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK, kMECC_AccessError1InterruptEnable = MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK, kMECC_AccessError2InterruptEnable = MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK, kMECC_AccessError3InterruptEnable = MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK, kMECC_AllInterruptsEnable = 0xFFFF }
	MECC interrupt configuration structure, default settings all disabled. More...

enum	{ kMECC_SingleError0InterruptStatusEnable = MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK, kMECC_SingleError1InterruptStatusEnable = MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK, kMECC_SingleError2InterruptStatusEnable = MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK, kMECC_SingleError3InterruptStatusEnable = MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK, kMECC_MultiError0InterruptStatusEnable = MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK, kMECC_MultiError1InterruptStatusEnable = MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK, kMECC_MultiError2InterruptStatusEnable = MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK, kMECC_MultiError3InterruptStatusEnable = MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK, kMECC_StrobeError0InterruptStatusEnable = MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK, kMECC_StrobeError1InterruptStatusEnable = MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK, kMECC_StrobeError2InterruptStatusEnable = MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK, kMECC_StrobeError3InterruptStatusEnable = MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK, kMECC_AccessError0InterruptStatusEnable = MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK, kMECC_AccessError1InterruptStatusEnable = MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK, kMECC_AccessError2InterruptStatusEnable = MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK, kMECC_AccessError3InterruptStatusEnable = MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK, kMECC_AllInterruptsStatusEnable = 0xFFFF }
	MECC interrupt status configuration structure, default settings all disabled. More...

enum	{ kMECC_SingleError0InterruptFlag = MECC_ERR_STATUS_SINGLE_ERR0_MASK, kMECC_SingleError1InterruptFlag = MECC_ERR_STATUS_SINGLE_ERR1_MASK, kMECC_SingleError2InterruptFlag = MECC_ERR_STATUS_SINGLE_ERR2_MASK, kMECC_SingleError3InterruptFlag = MECC_ERR_STATUS_SINGLE_ERR3_MASK, kMECC_MultiError0InterruptFlag = MECC_ERR_STATUS_MULTI_ERR0_MASK, kMECC_MultiError1InterruptFlag = MECC_ERR_STATUS_MULTI_ERR1_MASK, kMECC_MultiError2InterruptFlag = MECC_ERR_STATUS_MULTI_ERR2_MASK, kMECC_MultiError3InterruptFlag = MECC_ERR_STATUS_MULTI_ERR3_MASK, kMECC_StrobeError0InterruptFlag = MECC_ERR_STATUS_STRB_ERR0_MASK, kMECC_StrobeError1InterruptFlag = MECC_ERR_STATUS_STRB_ERR1_MASK, kMECC_StrobeError2InterruptFlag = MECC_ERR_STATUS_STRB_ERR2_MASK, kMECC_StrobeError3InterruptFlag = MECC_ERR_STATUS_STRB_ERR3_MASK, kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK, kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK, kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK, kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK, kMECC_AllInterruptsFlag = 0xFFFF }
	MECC status flags. More...

enum	{ kMECC_OcramBank0 = 0U, kMECC_OcramBank1 = 1U, kMECC_OcramBank2 = 2U, kMECC_OcramBank3 = 3U }
	MECC ocram bank number. More...

enum	_mecc_pending_flag { kMECC_ReadDataWaitPendingFlag = 0x1U, kMECC_ReadAddrPipelinePendingFlag = 0x2U, kMECC_WriteDataPipelinePendingFlag = 0x4U, kMECC_WriteAddrPipelinePendingFlag = 0x8U, kMECC_AllPendingFlags = 0xFU }
	Pending flags for OCRAM wait and pipeline enable. More...

Driver version
#define	FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
	Driver version 2.1.0. More...

Initialization and deinitialization
void	MECC_Init (MECC_Type base, mecc_config_t config)
	MECC module initialization function. More...

void	MECC_Deinit (MECC_Type *base)
	Deinitializes the MECC. More...

void	MECC_GetDefaultConfig (mecc_config_t *config)
	Sets the MECC configuration structure to default values. More...

Status
static uint32_t	MECC_GetStatusFlags (MECC_Type *base)
	Gets MECC status flags. More...

static void	MECC_ClearStatusFlags (MECC_Type *base, uint32_t mask)
	MECC module clear interrupt status. More...

static void	MECC_EnableInterruptStatus (MECC_Type *base, uint32_t mask)
	MECC module enable interrupt status. More...

static void	MECC_DisableInterruptStatus (MECC_Type *base, uint32_t mask)
	MECC module disable interrupt status. More...

Interrupts
static void	MECC_EnableInterrupts (MECC_Type *base, uint32_t mask)
	MECC module enable interrupt. More...

static void	MECC_DisableInterrupts (MECC_Type *base, uint32_t mask)
	MECC module disable interrupt. More...

functional
status_t	MECC_ErrorInjection (MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)
	MECC module error injection. More...

status_t	MECC_GetSingleErrorInfo (MECC_Type base, mecc_single_error_info_t info, uint8_t banknumber)
	MECC module get single error information. More...

status_t	MECC_GetMultiErrorInfo (MECC_Type base, mecc_multi_error_info_t info, uint8_t banknumber)
	MECC module get multiple error information. More...

static uint32_t	MECC_GetPendingFlags (MECC_Type *base)
	Get pending flags for OCRAM wait and pipeline enable. More...

Data Structure Documentation

struct _mecc_config

Note: Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

Data Fields
bool	enableMecc
	Enable the MECC function. More...

uint32_t	startAddress
	Start address of corresponding OCRAM memory region to enable ECC. More...

uint32_t	endAddress
	end address of corresponding OCRAM memory region to enable ECC. More...

bool	enableReadDataWait
	uint32_t Ocram1StartAddress; Ocram 1 start address, deprecated since 2.1.0 More...

bool	enableReadAddrPipeline
	If enabled, the read address will be registered before can be applied to memory cell: More...

bool	enableWriteDataPipeline
	If enabled, the write data will be registered before can be applied to memory cell: More...

bool	enableWriteAddrPipeline
	If enabled, write address will be registered before can be applied to memory cell: More...

Field Documentation

bool _mecc_config::enableMecc

uint32_t _mecc_config::startAddress

uint32_t _mecc_config::endAddress

bool _mecc_config::enableReadDataWait

uint32_t Ocram1EndAddress; Ocram 1 end address, deprecated since 2.1.0

uint32_t Ocram2StartAddress; Ocram 2 start address, deprecated since 2.1.0.

uint32_t Ocram2EndAddress; Ocram 2 end address, deprecated since 2.1.0 If enabled, 1-cycle wait state will be inserted into each read access:

true Enable read data wait;
false Disable read data wait.

bool _mecc_config::enableReadAddrPipeline

true Enable Read address pipeline;
false Disable Read address pipeline.

bool _mecc_config::enableWriteDataPipeline

true Enable write data pipeline;
false Disable write data pipeline.

bool _mecc_config::enableWriteAddrPipeline

true Enable write address pipeline;
false Disable write address pipeline.

struct _mecc_single_error_info

Data Fields
uint32_t	singleErrorAddress
	Single error address on Ocram bank n.

uint32_t	singleErrorDataLow
	Single error low 32 bits uncorrected read data on Ocram bank n.

uint32_t	singleErrorDataHigh
	Single error high 32 bits uncorrected read data on Ocram bank n.

uint32_t	singleErrorPosLow
	Single error bit postion of low 32 bits read data on Ocram bank n.

uint32_t	singleErrorPosHigh
	Single error bit postion of high 32 bits read data on Ocram bank n.

uint8_t	singleErrorEccCode
	Single error ECC code on Ocram bank n.

struct _mecc_multi_error_info

Data Fields
uint32_t	multiErrorAddress
	Multiple error address on Ocram bank n.

uint32_t	multiErrorDataLow
	Multiple error low 32 bits read data on Ocram bank n.

uint32_t	multiErrorDataHigh
	Multiple error high 32 bits read data on Ocram bank n.

uint8_t	multiErrorEccCode
	Multiple error ECC code on Ocram bank n.

Macro Definition Documentation

#define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))

Typedef Documentation

typedef struct _mecc_config mecc_config_t

Note: Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

Enumeration Type Documentation

anonymous enum

Enumerator
kStatus_MECC_BankMiss	Ocram bank miss.

anonymous enum

This structure contains the settings for all of the MECC interrupt configurations.

Enumerator
kMECC_SingleError0InterruptEnable	Single Bit Error On Ocram Bank0 interrupt enable.
kMECC_SingleError1InterruptEnable	Single Bit Error On Ocram Bank1 interrupt enable.
kMECC_SingleError2InterruptEnable	Single Bit Error On Ocram Bank2 interrupt enable.
kMECC_SingleError3InterruptEnable	Single Bit Error On Ocram Bank3 interrupt enable.
kMECC_MultiError0InterruptEnable	Multiple Bits Error On Ocram Bank0 interrupt enable.
kMECC_MultiError1InterruptEnable	Multiple Bits Error On Ocram Bank1 interrupt enable.
kMECC_MultiError2InterruptEnable	Multiple Bits Error On Ocram Bank2 interrupt enable.
kMECC_MultiError3InterruptEnable	Multiple Bits Error On Ocram Bank3 interrupt enable.
kMECC_StrobeError0InterruptEnable	AXI Strobe Error On Ocram Bank0 interrupt enable.
kMECC_StrobeError1InterruptEnable	AXI Strobe Error On Ocram Bank1 interrupt enable.
kMECC_StrobeError2InterruptEnable	AXI Strobe Error On Ocram Bank2 interrupt enable.
kMECC_StrobeError3InterruptEnable	AXI Strobe Error On Ocram Bank3 interrupt enable.
kMECC_AccessError0InterruptEnable	Ocram Access Error On Bank0 interrupt enable.
kMECC_AccessError1InterruptEnable	Ocram Access Error On Bank1 interrupt enable.
kMECC_AccessError2InterruptEnable	Ocram Access Error On Bank2 interrupt enable.
kMECC_AccessError3InterruptEnable	Ocram Access Error On Bank3 interrupt enable.
kMECC_AllInterruptsEnable	all interrupts enable

anonymous enum

This structure contains the settings for all of the MECC interrupt status configurations.

Enumerator
kMECC_SingleError0InterruptStatusEnable	Single Bit Error On Ocram Bank0 interrupt status enable.
kMECC_SingleError1InterruptStatusEnable	Single Bit Error On Ocram Bank1 interrupt status enable.
kMECC_SingleError2InterruptStatusEnable	Single Bit Error On Ocram Bank2 interrupt status enable.
kMECC_SingleError3InterruptStatusEnable	Single Bit Error On Ocram Bank3 interrupt status enable.
kMECC_MultiError0InterruptStatusEnable	Multiple Bits Error On Ocram Bank0 interrupt status enable.
kMECC_MultiError1InterruptStatusEnable	Multiple Bits Error On Ocram Bank1 interrupt status enable.
kMECC_MultiError2InterruptStatusEnable	Multiple Bits Error On Ocram Bank2 interrupt status enable.
kMECC_MultiError3InterruptStatusEnable	Multiple Bits Error On Ocram Bank3 interrupt status enable.
kMECC_StrobeError0InterruptStatusEnable	AXI Strobe Error On Ocram Bank0 interrupt status enable.
kMECC_StrobeError1InterruptStatusEnable	AXI Strobe Error On Ocram Bank1 interrupt status enable.
kMECC_StrobeError2InterruptStatusEnable	AXI Strobe Error On Ocram Bank2 interrupt status enable.
kMECC_StrobeError3InterruptStatusEnable	AXI Strobe Error On Ocram Bank3 interrupt status enable.
kMECC_AccessError0InterruptStatusEnable	Ocram Access Error On Bank0 interrupt status enable.
kMECC_AccessError1InterruptStatusEnable	Ocram Access Error On Bank1 interrupt status enable.
kMECC_AccessError2InterruptStatusEnable	Ocram Access Error On Bank2 interrupt status enable.
kMECC_AccessError3InterruptStatusEnable	Ocram Access Error On Bank3 interrupt status enable.
kMECC_AllInterruptsStatusEnable	all interrupts enable

anonymous enum

This provides constants for the MECC status flags for use in the MECC functions.

Enumerator
kMECC_SingleError0InterruptFlag	Single Bit Error On Ocram Bank0 interrupt flag.
kMECC_SingleError1InterruptFlag	Single Bit Error On Ocram Bank1 interrupt flag.
kMECC_SingleError2InterruptFlag	Single Bit Error On Ocram Bank2 interrupt flag.
kMECC_SingleError3InterruptFlag	Single Bit Error On Ocram Bank3 interrupt flag.
kMECC_MultiError0InterruptFlag	Multiple Bits Error On Ocram Bank0 interrupt flag.
kMECC_MultiError1InterruptFlag	Multiple Bits Error On Ocram Bank1 interrupt flag.
kMECC_MultiError2InterruptFlag	Multiple Bits Error On Ocram Bank2 interrupt flag.
kMECC_MultiError3InterruptFlag	Multiple Bits Error On Ocram Bank3 interrupt flag.
kMECC_StrobeError0InterruptFlag	AXI Strobe Error On Ocram Bank0 interrupt flag.
kMECC_StrobeError1InterruptFlag	AXI Strobe Error On Ocram Bank1 interrupt flag.
kMECC_StrobeError2InterruptFlag	AXI Strobe Error On Ocram Bank2 interrupt flag.
kMECC_StrobeError3InterruptFlag	AXI Strobe Error On Ocram Bank3 interrupt flag.
kMECC_AccessError0InterruptFlag	Ocram Access Error On Bank0 interrupt flag.
kMECC_AccessError1InterruptFlag	Ocram Access Error On Bank1 interrupt flag.
kMECC_AccessError2InterruptFlag	Ocram Access Error On Bank2 interrupt flag.
kMECC_AccessError3InterruptFlag	Ocram Access Error On Bank3 interrupt flag.
kMECC_AllInterruptsFlag	all interrupts interrupt flag

anonymous enum

Enumerator
kMECC_OcramBank0	ocram bank number 0: ocram_base_address+0x20*i
kMECC_OcramBank1	ocram bank number 1: ocram_base_address+0x20*i+0x8
kMECC_OcramBank2	ocram bank number 2: ocram_base_address+0x20*i+0x10
kMECC_OcramBank3	ocram bank number 3: ocram_base_address+0x20*i+0x18

enum _mecc_pending_flag

.

Enumerator
kMECC_ReadDataWaitPendingFlag	Indicate an update pending status for read data wait.
kMECC_ReadAddrPipelinePendingFlag	Indicate an update pending status for read address pipeline.
kMECC_WriteDataPipelinePendingFlag	Indicate an update pending status for write data pipeline.
kMECC_WriteAddrPipelinePendingFlag	Indicate an update pending status for write address pipeline.
kMECC_AllPendingFlags	Indicate all pending status flags.

Function Documentation

void MECC_Init	(	MECC_Type *	base,
		mecc_config_t *	config
	)

Parameters

base	MECC base address.
config	pointer to the MECC configuration structure.

void MECC_Deinit ( MECC_Type * base )

Parameters

base	MECC base address.

void MECC_GetDefaultConfig ( mecc_config_t * config )

Parameters

config pointer to the MECC configuration structure.

static uint32_t MECC_GetStatusFlags ( MECC_Type * base )

inlinestatic

Parameters

base	MECC peripheral base address.

Returns: MECC status flags.

static void MECC_ClearStatusFlags	(	MECC_Type *	base,
		uint32_t	mask
	)

inlinestatic

Parameters

base	MECC base address.
mask	status to clear.

static void MECC_EnableInterruptStatus	(	MECC_Type *	base,
		uint32_t	mask
	)

inlinestatic

Parameters

base	MECC base address.
mask	status to enable.

static void MECC_DisableInterruptStatus	(	MECC_Type *	base,
		uint32_t	mask
	)

inlinestatic

Parameters

base	MECC base address.
mask	status to disable.

static void MECC_EnableInterrupts	(	MECC_Type *	base,
		uint32_t	mask
	)

inlinestatic

Parameters

base	MECC base address.
mask	The interrupts to enable.

static void MECC_DisableInterrupts	(	MECC_Type *	base,
		uint32_t	mask
	)

inlinestatic

Parameters

base	MECC base address.
mask	The interrupts to disable.

status_t MECC_ErrorInjection	(	MECC_Type *	base,
		uint32_t	lowerrordata,
		uint32_t	higherrordata,
		uint8_t	eccdata,
		uint8_t	banknumber
	)

Parameters

base	MECC base address.
lowerrordata	low 32 bits data.
higherrordata	high 32 bits data.
eccdata	ecc code.
banknumber	ocram bank number.

Return values

kStatus_Success. Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4.....

status_t MECC_GetSingleErrorInfo	(	MECC_Type *	base,
		mecc_single_error_info_t *	info,
		uint8_t	banknumber
	)

Parameters

base	MECC base address.
info	single error information.
banknumber	ocram bank number.

Return values

kStatus_Success.
kStatus_MECC_BankMiss.	Bank0: ocram_base_address+0x20i Bank1: ocram_base_address+0x20i+0x8 Bank2: ocram_base_address+0x20i+0x10 Bank3: ocram_base_address+0x20i+0x18 i = 0,1,2,3,4.....

status_t MECC_GetMultiErrorInfo	(	MECC_Type *	base,
		mecc_multi_error_info_t *	info,
		uint8_t	banknumber
	)

Parameters

base	MECC base address.
info	multiple error information.
banknumber	ocram bank number.

Return values

kStatus_Success.
kStatus_MECC_BankMiss.	Bank0: ocram_base_address+0x20i Bank1: ocram_base_address+0x20i+0x8 Bank2: ocram_base_address+0x20i+0x10 Bank3: ocram_base_address+0x20i+0x18 i = 0,1,2,3,4.....

static uint32_t MECC_GetPendingFlags ( MECC_Type * base )

inlinestatic

Parameters

base	MECC base address.

Returns: Pending flags, should be the OR'ed value of mecc_pending_flag_t.

Overview

Data Structures

Typedefs

Enumerations

Driver version

Initialization and deinitialization

Status

Interrupts

functional

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Data Fields

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation