Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

Get frequency

A centralized function CLOCK_GetFreq gets different clock type frequencies by passing a clock name. For example, pass a kCLOCK_CoreSysClk to get the core clock and pass a kCLOCK_BusClk to get the bus clock. Additionally, there are separate functions to get the frequency. For example, use CLOCK_GetCoreSysClkFreq to get the core clock frequency and CLOCK_GetBusClkFreq to get the bus clock frequency. Using these functions reduces the image size.

External clock frequency

The external clocks EXTAL0/EXTAL1/EXTAL32 are decided by the board level design. The Clock driver uses variables g_xtal0Freq/g_xtal1Freq/g_xtal32Freq to save clock frequencies. Likewise, the APIs CLOCK_SetXtal0Freq, CLOCK_SetXtal1Freq, and CLOCK_SetXtal32Freq are used to set these variables.
The upper layer must set these values correctly. For example, after OSC0(SYSOSC) is initialized using CLOCK_InitOsc0 or CLOCK_InitSysOsc, the upper layer should call the CLOCK_SetXtal0Freq. Otherwise, the clock frequency get functions may not receive valid values. This is useful for multicore platforms where only one core calls CLOCK_InitOsc0 to initialize OSC0 and other cores call CLOCK_SetXtal0Freq.

Data Structures
struct	clock_usb_pll_config_t
	PLL configuration for USB. More...

struct	clock_sys_pll_config_t
	PLL configuration for System Fout = Fref * (loopDivider + (float)Numerator/Denominator) More...

struct	clock_audio_pll_config_t
	PLL configuration for AUDIO. More...

struct	clock_enet_pll_config_t
	PLL configuration for ENET. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	ENET_CLOCKS
	Clock ip name array for ENET. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	SNVS_HP_CLOCKS
	Clock ip name array for SNVS HP. More...

#define	SNVS_LP_CLOCKS
	Clock ip name array for SNVS LP. More...

#define	CAAM_CLOCKS
	Clock ip name array for CAAM. More...

#define	PCTL_CLOCKS
	Clock ip name array for PCTL. More...

#define	MIPFIL_CLOCKS
	Clock ip name array for MICFIL. More...

#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	SJC_CLOCKS
	Clock ip name array for SJC. More...

#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...

#define	ROMC_CLOCKS
	Clock ip name array for ROMC. More...

#define	IIM_CLOCKS
	Clock ip name array for IIM. More...

#define	LPSPI_PERIPH_CLOCKS
	Clock array for LPSPI Peripheral clock. More...

#define	LPUART_PERIPH_CLOCKS
	Clock array for LPUART Peripheral clock. More...

#define	LPI2C_PERIPH_CLOCKS
	Clock array for LPI2C Peripheral clock. More...

#define	TPSMP_CLOCKS
	Clock ip name array for TPSMP. More...

#define	ESAI_CLOCKS
	Clock ip name array for ESAI. More...

#define	TPM_CLOCKS
	Clock ip name array for TPM. More...

#define	FLEXCAN_PERIPH_CLOCKS
	Clock array for FLEXCAN Peripheral clock. More...

#define	LPTMR_PERIPH_CLOCKS
	Clock array for LPTMR Peripheral clock. More...

#define	LPTMR_CLOCKS
	Clock ip name array for LPTMR. More...

#define	LPIT_PERIPH_CLOCKS
	Clock array for LPIT Peripheral clock. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	WDOG_CLOCKS
	Clock ip name array for WDOG. More...

#define	USDHC_CLOCKS
	Clock ip name array for uSDHC. More...

#define	EMVSIM_CLOCKS
	Clock ip name array for EMVSIM. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	CAAM_MEM_CLOCKS
	Clock array for CAAM Memory. More...

#define	CAAM_CTRL_CLOCKS
	Clock array for CAAM controller. More...

#define	LPDAC_CLOCKS
	Clock ip name array for DAC. More...

#define	ADC_CLOCKS
	Clock ip name array for ADC. More...

#define	TRGMUX_CLOCKS
	Clock ip name array for TRGMUX. More...

#define	IEE_CLOCKS
	Clock ip name array for IEE. More...

#define	TPIU_CLOCKS
	Clock ip name array for TPIU. More...

#define	IOMUXC_CLOCKS
	Clock ip name array for IOMUXC. More...

#define	FSL_CLOCK_MMDC_IPG_GATE_COUNT 1U
	MMDC IPG clock. More...

#define	MMDC_ACLK_CLOCKS
	MMDC ACLK. More...

#define	RGPIO_CLOCKS
	Clock ip name array for RGPIO. More...

#define	SIM_CLOCKS
	Clock ip name array for SIM. More...

#define	FLEXBUS_CLOCKS
	Clock ip name array for FLEXBUS. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX. More...

#define	SDRAM_CLOCKS
	Clock ip name array for SDRAM. More...

#define	FSL_CLOCK_XRDC_GATE_COUNT 0U
	XRDC clock gate number. More...

#define	IRC_CLK_FREQ 24000000U
	IRC clock frequency.

#define	RTC_CLK_FREQ 32768U
	RTC clock frequency.

#define	kCLOCK_CoreSysClk kCLOCK_CpuClk
	For compatible with other platforms without CCM. More...

#define	CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
	For compatible with other platforms without CCM. More...

Enumerations
enum	clock_name_t { kCLOCK_CpuClk, kCLOCK_AxiClk, kCLOCK_AhbClk, kCLOCK_IpgClk, kCLOCK_FlexBusClk, kCLOCK_RcOscClk, kCLOCK_XtalOscClk, kCLOCK_OscClk, kCLOCK_RtcClk, kCLOCK_Usb1PllClk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_Usb2PllClk, kCLOCK_SysPllClk, kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd3Clk, kCLOCK_EnetPll0Clk, kCLOCK_EnetPll1Clk, kCLOCK_EnetPll2Clk, kCLOCK_AudioPllClk }
	Clock name used to get clock frequency. More...

enum	clock_ip_name_t { , kCLOCK_Dma1 = (0U << 8U) \| CCM_CCGR0_DMA1_CLK_ENABLE_SHIFT, kCLOCK_Dma0 = (0U << 8U) \| CCM_CCGR0_DMA0_CLK_ENABLE_SHIFT, kCLOCK_Enet0 = (0U << 8U) \| CCM_CCGR0_ENET_CLK_ENABLE_SHIFT, kCLOCK_Lpuart3 = (1U << 8U) \| CCM_CCGR1_LPUART3_CLK_ENABLE_SHIFT, kCLOCK_Lpuart2 = (1U << 8U) \| CCM_CCGR1_LPUART2_CLK_ENABLE_SHIFT, kCLOCK_Lpuart1 = (1U << 8U) \| CCM_CCGR1_LPUART1_CLK_ENABLE_SHIFT, kCLOCK_Lpuart0 = (1U << 8U) \| CCM_CCGR1_LPUART0_CLK_ENABLE_SHIFT, kCLOCK_Lpspi3 = (1U << 8U) \| CCM_CCGR1_LPSPI3_CLK_ENABLE_SHIFT, kCLOCK_Lpspi2 = (1U << 8U) \| CCM_CCGR1_LPSPI2_CLK_ENABLE_SHIFT, kCLOCK_Lpspi1 = (1U << 8U) \| CCM_CCGR1_LPSPI1_CLK_ENABLE_SHIFT, kCLOCK_Lpspi0 = (1U << 8U) \| CCM_CCGR1_LPSPI0_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c3 = (1U << 8U) \| CCM_CCGR1_LPI2C3_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c2 = (1U << 8U) \| CCM_CCGR1_LPI2C2_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c1 = (1U << 8U) \| CCM_CCGR1_LPI2C1_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c0 = (1U << 8U) \| CCM_CCGR1_LPI2C0_CLK_ENABLE_SHIFT, kCLOCK_SnvsHp0 = (1U << 8U) \| CCM_CCGR1_SNVS_HP_CLK_ENABLE_SHIFT, kCLOCK_MmdcAClk = (1U << 8U) \| CCM_CCGR1_MMDC_CORE_ACLK_FAST_CORE_P0_CLK_ENABLE_SHIFT, kCLOCK_Caam0 = (2U << 8U) \| CCM_CCGR2_CAAM_WRAPPER_IPG_CLK_ENABLE_SHIFT, kCLOCK_Pctl5 = (2U << 8U) \| CCM_CCGR2_PCTL5_CLK_ENABLE_SHIFT, kCLOCK_Pctl4 = (2U << 8U) \| CCM_CCGR2_PCTL4_CLK_ENABLE_SHIFT, kCLOCK_Pctl3 = (2U << 8U) \| CCM_CCGR2_PCTL3_CLK_ENABLE_SHIFT, kCLOCK_Pctl2 = (2U << 8U) \| CCM_CCGR2_PCTL2_CLK_ENABLE_SHIFT, kCLOCK_Pctl1 = (2U << 8U) \| CCM_CCGR2_PCTL1_CLK_ENABLE_SHIFT, kCLOCK_Pctl0 = (2U << 8U) \| CCM_CCGR2_PCTL0_CLK_ENABLE_SHIFT, kCLOCK_Flexspi1 = (2U << 8U) \| CCM_CCGR2_FLEXSPI1_CLK_ENABLE_SHIFT, kCLOCK_Flexspi0 = (2U << 8U) \| CCM_CCGR2_FLEXSPI0_CLK_ENABLE_SHIFT, kCLOCK_Flexio1 = (2U << 8U) \| CCM_CCGR2_FLEXIO1_CLK_ENABLE_SHIFT, kCLOCK_Flexio0 = (2U << 8U) \| CCM_CCGR2_FLEXIO0_CLK_ENABLE_SHIFT, kCLOCK_Sai1 = (2U << 8U) \| CCM_CCGR2_SAI1_CLK_ENABLE_SHIFT, kCLOCK_Sai0 = (2U << 8U) \| CCM_CCGR2_SAI0_CLK_ENABLE_SHIFT, kCLOCK_Sjc0 = (3U << 8U) \| CCM_CCGR3_SJC_CLK_ENABLE_SHIFT, kCLOCK_Romc0 = (3U << 8U) \| CCM_CCGR3_ROMC_CLK_ENABLE_SHIFT, kCLOCK_Iim0 = (3U << 8U) \| CCM_CCGR3_IIM_CLK_ENABLE_SHIFT, kCLOCK_Lpspi3Periph = (3U << 8U) \| CCM_CCGR3_LPSPI3_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpspi2Periph = (3U << 8U) \| CCM_CCGR3_LPSPI2_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpspi1Periph = (3U << 8U) \| CCM_CCGR3_LPSPI1_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpspi0Periph = (3U << 8U) \| CCM_CCGR3_LPSPI0_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpuart3Periph = (3U << 8U) \| CCM_CCGR3_LPUART3_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpuart2Periph = (3U << 8U) \| CCM_CCGR3_LPUART2_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpuart1Periph = (3U << 8U) \| CCM_CCGR3_LPUART1_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpuart0Periph = (3U << 8U) \| CCM_CCGR3_LPUART0_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c3Periph = (3U << 8U) \| CCM_CCGR3_LPI2C3_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c2Periph = (3U << 8U) \| CCM_CCGR3_LPI2C2_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c1Periph = (3U << 8U) \| CCM_CCGR3_LPI2C1_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpi2c0Periph = (3U << 8U) \| CCM_CCGR3_LPI2C0_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Tpsmp0 = (4U << 8U) \| CCM_CCGR4_TPSMP_CLK_ENABLE_SHIFT, kCLOCK_Esai0 = (4U << 8U) \| CCM_CCGR4_ESAI_CLK_ENABLE_SHIFT, kCLOCK_Tpm3 = (4U << 8U) \| CCM_CCGR4_TPM3_CLK_ENABLE_SHIFT, kCLOCK_Tpm2 = (4U << 8U) \| CCM_CCGR4_TPM2_CLK_ENABLE_SHIFT, kCLOCK_Tpm1 = (4U << 8U) \| CCM_CCGR4_TPM1_CLK_ENABLE_SHIFT, kCLOCK_Tpm0 = (4U << 8U) \| CCM_CCGR4_TPM0_CLK_ENABLE_SHIFT, kCLOCK_Lptmr1Periph = (4U << 8U) \| CCM_CCGR4_LPTMR1_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lptmr1 = (4U << 8U) \| CCM_CCGR4_LPTMR1_CLK_ENABLE_SHIFT, kCLOCK_Lptmr0Periph = (4U << 8U) \| CCM_CCGR4_LPTMR0_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lptmr0 = (4U << 8U) \| CCM_CCGR4_LPTMR0_CLK_ENABLE_SHIFT, kCLOCK_Lpit1Periph = (4U << 8U) \| CCM_CCGR4_LPIT1_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpit1 = (4U << 8U) \| CCM_CCGR4_LPIT1_CLK_ENABLE_SHIFT, kCLOCK_Lpit0Periph = (4U << 8U) \| CCM_CCGR4_LPIT0_SERIAL_CLK_ENABLE_SHIFT, kCLOCK_Lpit0 = (4U << 8U) \| CCM_CCGR4_LPIT0_CLK_ENABLE_SHIFT, kCLOCK_Wdog0 = (5U << 8U) \| CCM_CCGR5_WDOG_CLK_ENABLE_SHIFT, kCLOCK_Usdhc1 = (5U << 8U) \| CCM_CCGR5_USDHC1_CLK_ENABLE_SHIFT, kCLOCK_Usdhc0 = (5U << 8U) \| CCM_CCGR5_USDHC0_CLK_ENABLE_SHIFT, kCLOCK_Emvsim1 = (5U << 8U) \| CCM_CCGR5_EMVSIM1_CLK_ENABLE_SHIFT, kCLOCK_Emvsim0 = (5U << 8U) \| CCM_CCGR5_EMVSIM0_CLK_ENABLE_SHIFT, kCLOCK_Crc0 = (5U << 8U) \| CCM_CCGR5_CRC_CLK_ENABLE_SHIFT, kCLOCK_Usbhs0 = (5U << 8U) \| CCM_CCGR5_USBOH3_CLK_ENABLE_SHIFT, kCLOCK_CaamController0 = (5U << 8U) \| CCM_CCGR5_CAAM_WRAPPER_CLK_ENABLE_SHIFT, kCLOCK_CaamMemory0 = (5U << 8U) \| CCM_CCGR5_CAAM_SECURE_MEM_CLK_ENABLE_SHIFT, kCLOCK_Lpdac1 = (5U << 8U) \| CCM_CCGR5_DAC1_CLK_ENABLE_SHIFT, kCLOCK_Lpdac0 = (5U << 8U) \| CCM_CCGR5_DAC0_CLK_ENABLE_SHIFT, kCLOCK_Adc1 = (5U << 8U) \| CCM_CCGR5_ADC1_CLK_ENABLE_SHIFT, kCLOCK_Adc0 = (5U << 8U) \| CCM_CCGR5_ADC0_CLK_ENABLE_SHIFT, kCLOCK_Trgmux0 = (5U << 8U) \| CCM_CCGR5_TRGMUX_CLK_ENABLE_SHIFT, kCLOCK_Iee0 = (5U << 8U) \| CCM_CCGR5_IEE_CLK_ENABLE_SHIFT, kCLOCK_Tpiu0 = (5U << 8U) \| CCM_CCGR5_TPIU_CLK_ENABLE_SHIFT, kCLOCK_Mmdc0 = (6U << 8U) \| CCM_CCGR6_MMDC_CORE_IPG_CLK_P0_CLK_ENABLE_SHIFT, kCLOCK_Iomuxc1 = (6U << 8U) \| CCM_CCGR6_IOMUXC1_CLK_ENABLE_SHIFT, kCLOCK_Iomuxc0 = (6U << 8U) \| CCM_CCGR6_IOMUXC0_CLK_ENABLE_SHIFT, kCLOCK_Sdramc0 = (7U << 8U) \| CCM_CCGR7_SDRAMC_CLK_ENABLE_SHIFT, kCLOCK_Flexbus0 = (7U << 8U) \| CCM_CCGR7_FLEXBUS_CLK_ENABLE_SHIFT, kCLOCK_Sim0 = (7U << 8U) \| CCM_CCGR7_SIM_CLK_ENABLE_SHIFT, kCLOCK_Dmamux1 = (7U << 8U) \| CCM_CCGR7_DMAMUX1_CLK_ENABLE_SHIFT, kCLOCK_Dmamux0 = (7U << 8U) \| CCM_CCGR7_DMAMUX0_CLK_ENABLE_SHIFT, kCLOCK_SnvsLp0 = (7U << 8U) \| CCM_CCGR7_SNVS_LP_CLK_ENABLE_SHIFT, kCLOCK_Rgpio0 = (7U << 8U) \| CCM_CCGR7_RGPIO_CLK_ENABLE_SHIFT }
	CCM CCGR gate control for each module independently. More...

enum	clock_osc_t { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...

enum	clock_gate_value_t { kCLOCK_ClockNotNeeded = 0U, kCLOCK_ClockNeededRun = 1U, kCLOCK_ClockNeededAll = 2U, kCLOCK_ClockNeededRunWait = 3U }
	Clock gate value. More...

enum	clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...

enum	_clock_interrupt { kCLOCK_MmdcPodfUpdateInterrupt = CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK, kCLOCK_MmdcClkSelUpdateInterrupt = CCM_CIMR_MASK_MMDC_CLK_SEL_LOADED_MASK, kCLOCK_OnChipOscReadyInterrupt = CCM_CIMR_MASK_COSC_READY_MASK, kCLOCK_PllLrfInterrupt = CCM_CIMR_MASK_LRF_PLL_MASK }
	CCM interrupt source. More...

enum	clock_mux_t { kCLOCK_SysPllMux = CCM_TUPLE(CCSR, CCM_CCSR_SYS_PLL_SW_CLK_SEL_SHIFT, CCM_CCSR_SYS_PLL_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Usb1PllMux = CCM_TUPLE(CCSR, CCM_CCSR_USB1_PLL_SW_CLK_SEL_SHIFT, CCM_CCSR_USB1_PLL_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_OscIrcMux = CCM_TUPLE(CSYSCMR, CCM_CSYSCMR_OSC_FIR_CLK_SEL_SHIFT, CCM_CSYSCMR_OSC_FIR_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_SysClkMux = CCM_TUPLE(CSYSCMR, CCM_CSYSCMR_SYS_CLK_SEL_SHIFT, CCM_CSYSCMR_SYS_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Enet1588Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ENET_1588_CLK_SEL_SHIFT, CCM_CSCMR1_ENET_1588_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpspi23Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_LPSPI23_CLK_SEL_SHIFT, CCM_CSCMR1_LPSPI23_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpspi01Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_LPSPI01_CLK_SEL_SHIFT, CCM_CSCMR1_LPSPI01_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Flexspi1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI1_CLK_SEL_SHIFT, CCM_CSCMR1_FLEXSPI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Flexspi0Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_FLEXSPI0_CLK_SEL_SHIFT, CCM_CSCMR1_FLEXSPI0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EnetRmiiMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ENET_RMII_CLK_SEL_SHIFT, CCM_CSCMR1_ENET_RMII_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Usdhc0Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC0_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_MmdcMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_MMDC_CH0_CLK_SEL_SHIFT, CCM_CSCMR1_MMDC_CH0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Tpm23Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_TPM23_CLK_SEL_SHIFT, CCM_CSCMR2_TPM23_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Tpm01Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_TPM01_CLK_SEL_SHIFT, CCM_CSCMR2_TPM01_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_LpitMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LPIT_CLK_SEL_SHIFT, CCM_CSCMR2_LPIT_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_FlexioMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_FLEXIO_CLK_SEL_SHIFT, CCM_CSCMR2_FLEXIO_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EmvsimMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_EMVSIM_CLK_SEL_SHIFT, CCM_CSCMR2_EMVSIM_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpi2c23Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LPI2C23_CLK_SEL_SHIFT, CCM_CSCMR2_LPI2C23_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpi2c01Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LPI2C01_CLK_SEL_SHIFT, CCM_CSCMR2_LPI2C01_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpuart23Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LPUART23_CLK_SEL_SHIFT, CCM_CSCMR2_LPUART23_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpuart01Mux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LPUART01_CLK_SEL_SHIFT, CCM_CSCMR2_LPUART01_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_TpiuMux = CCM_TUPLE(CSCMR3, CCM_CSCMR3_TPIU_CLK_SEL_SHIFT, CCM_CSCMR3_TPIU_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR3, CCM_CSCMR3_SAI1_CLK_SEL_SHIFT, CCM_CSCMR3_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Sai0Mux = CCM_TUPLE(CSCMR3, CCM_CSCMR3_SAI0_CLK_SEL_SHIFT, CCM_CSCMR3_SAI0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EsaiMux = CCM_TUPLE(CSCMR3, CCM_CSCMR3_ESAI_CLK_SEL_SHIFT, CCM_CSCMR3_ESAI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT) }
	MUX control names for clock mux setting. More...

enum	clock_div_t { kCLOCK_ArmDiv = CCM_TUPLE(CSYSCDR, CCM_CSYSCDR_CPU_PODF_SHIFT, CCM_CSYSCDR_CPU_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_AxiDiv = CCM_TUPLE(CSYSCDR, CCM_CSYSCDR_AXI_PODF_SHIFT, CCM_CSYSCDR_AXI_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_AhbDiv = CCM_TUPLE(CSYSCDR, CCM_CSYSCDR_AHB_PODF_SHIFT, CCM_CSYSCDR_AHB_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_IpgDiv = CCM_TUPLE(CSYSCDR, CCM_CSYSCDR_IPG_PODF_SHIFT, CCM_CSYSCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_FlexBusDiv = CCM_TUPLE(CSYSCDR, CCM_CSYSCDR_FB_PODF_SHIFT, CCM_CSYSCDR_FB_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EnetRmiiDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_ENET_RMII_PODF_SHIFT, CCM_CSCDR1_ENET_RMII_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_TpiuDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_TPIU_PODF_SHIFT, CCM_CSCDR1_TPIU_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Flexspi1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_FLEXSPI1_PODF_SHIFT, CCM_CSCDR1_FLEXSPI1_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Flexspi0Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_FLEXSPI0_PODF_SHIFT, CCM_CSCDR1_FLEXSPI0_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Usdhc0Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC0_PODF_SHIFT, CCM_CSCDR1_USDHC0_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_MmdcDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_MMDC_PODF_SHIFT, CCM_CSCDR1_MMDC_PODF_MASK, CCM_CDHIPR_MMDC_CH0_PODF_CHANGED_SHIFT), kCLOCK_Lpuart23Div = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPUART23_PODF_SHIFT, CCM_CSCDR2_LPUART23_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpuart01Div = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPUART01_PODF_SHIFT, CCM_CSCDR2_LPUART01_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpspi23Div = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPSPI23_PODF_SHIFT, CCM_CSCDR2_LPSPI23_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpspi01Div = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LPSPI01_PODF_SHIFT, CCM_CSCDR2_LPSPI01_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_LptmrDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_LPTMR_PODF_SHIFT, CCM_CSCDR3_LPTMR_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_LpitDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_LPIT_PODF_SHIFT, CCM_CSCDR3_LPIT_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpi2c23Div = CCM_TUPLE(CSCDR3, CCM_CSCDR3_LPI2C23_PODF_SHIFT, CCM_CSCDR3_LPI2C23_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Lpi2c01Div = CCM_TUPLE(CSCDR3, CCM_CSCDR3_LPI2C01_PODF_SHIFT, CCM_CSCDR3_LPI2C01_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EmvsimDiv = CCM_TUPLE(CSCDR4, CCM_CSCDR4_EMVSIM_PODF_SHIFT, CCM_CSCDR4_EMVSIM_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_FlexioDiv = CCM_TUPLE(CSCDR4, CCM_CSCDR4_FLEXIO_PODF_SHIFT, CCM_CSCDR4_FLEXIO_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Tpm23Div = CCM_TUPLE(CSCDR5, CCM_CSCDR5_TPM23_PODF_SHIFT, CCM_CSCDR5_TPM23_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Tpm01Div = CCM_TUPLE(CSCDR5, CCM_CSCDR5_TPM01_PODF_SHIFT, CCM_CSCDR5_TPM01_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_EsaiDiv = CCM_TUPLE(CSCDR6, CCM_CSCDR6_ESAI_PODF_SHIFT, CCM_CSCDR6_ESAI_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Sai1Div = CCM_TUPLE(CSCDR7, CCM_CSCDR7_SAI1_PODF_SHIFT, CCM_CSCDR7_SAI1_PODF_MASK, CCM_NO_BUSY_WAIT), kCLOCK_Sai0Div = CCM_TUPLE(CSCDR7, CCM_CSCDR7_SAI0_PODF_SHIFT, CCM_CSCDR7_SAI0_PODF_MASK, CCM_NO_BUSY_WAIT) }
	DIV control names for clock div setting. More...

enum	clock_pll_t { kCLOCK_PllSys, kCLOCK_PllUsb1, kCLOCK_PllAudio, kCLOCK_PllEnet0, kCLOCK_PllEnet1, kCLOCK_PllEnet2, kCLOCK_PllUsb2 }
	PLL name. More...

enum	clock_pfd_t { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...

enum	clock_usb_src_t { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = 0xFFFFFFFFU }
	USB clock source definition. More...

enum	clock_usb_phy_src_t { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...

Variables
uint32_t	g_xtal0Freq
	External XTAL (24M OSC/SYSOSC) clock frequency. More...

uint32_t	g_xtal32Freq
	External RTC XTAL (32K OSC) clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
	CLOCK driver version 2.0.0. More...

Clock gate, mux, and divider.
static void	CLOCK_SetMux (clock_mux_t mux, uint32_t value)
	Set CCM MUX node to certain value. More...

static uint32_t	CLOCK_GetMux (clock_mux_t mux)
	Get CCM MUX value. More...

static void	CLOCK_SetDiv (clock_div_t divider, uint32_t value)
	Set CCM DIV node to certain value. More...

static uint32_t	CLOCK_GetDiv (clock_div_t divider)
	Get CCM DIV node value. More...

static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...

static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static void	CLOCK_SetMode (clock_mode_t mode)
	Setting the low power mode that system will enter on next assertion of dsm_request signal. More...

CCM Interrupts
static void	CLOCK_EnableInterrupts (uint32_t mask)
	Enable/not mask CCM interrupts. More...

static void	CLOCK_DisableInterrupts (uint32_t mask)
	Disable/mask CCM interrupts. More...

static uint32_t	CLOCK_GetInterruptStatus (void)
	Get CCM interrupt status flags. More...

static void	CLOCK_ClearInterruptStatus (uint32_t mask)
	Clear interrupt status flags. More...

CCM Get frequency
uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCpuClkFreq (void)
	Get the CCM CPU/core/system frequency. More...

uint32_t	CLOCK_GetAxiBusClkFreq (void)
	Get the CCM AXI bus frequency. More...

uint32_t	CLOCK_GetAhbBusClkFreq (void)
	Get the CCM AHB bus frequency. More...

uint32_t	CLOCK_GetIpgBusClkFreq (void)
	Get the CCM IPG bus frequency. More...

uint32_t	CLOCK_GetFlexBusClkFreq (void)
	Get the CCM FlexBus frequency. More...

static uint32_t	CLOCK_GetRcOscFreq (void)
	Get the RCOSC (internel IRC) clock frequency. More...

static uint32_t	CLOCK_GetXtalOscFreq (void)
	Get the external IRC clock frequency. More...

uint32_t	CLOCK_GetOscFreq (void)
	Get the OSC clock frequency selected by ANATOP HW_ANADIG_LOWPWR_CTRL[OSC_SEL]. More...

uint32_t	CLOCK_GetRtcFreq (void)
	Get the RTC clock frequency. More...

OSC operations
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock. More...

void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock. More...

void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC. More...

static void	CLOCK_InitRtcRingOsc (void)
	Initializes the ANATOP RTC ring OSC. More...

static void	CLOCK_DeinitRtcRingOsc (void)
	De-initializes the ANATOP RTC ring OSC. More...

static void	CLOCK_SetXtal0Freq (uint32_t freq)
	Set the XTAL0 frequency based on board setting. More...

static void	CLOCK_SetXtal32Freq (uint32_t freq)
	Set the XTAL32 frequency based on board setting. More...

void	CLOCK_InitRcOsc24M (void)
	Initialize the RC oscillator 24MHz clock.

void	CLOCK_DeinitRcOsc24M (void)
	Power down the RCOSC 24M clock.

PLL/PFD operations
void	CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
	Initialize the System PLL. More...

void	CLOCK_DeinitSysPll (void)
	De-initialize the System PLL.

void	CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
	Initialize the USB1 PLL. More...

void	CLOCK_DeinitUsb1Pll (void)
	Deinitialize the USB1 PLL.

void	CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
	Initialize the USB2 PLL. More...

void	CLOCK_DeinitUsb2Pll (void)
	Deinitialize the USB2 PLL.

void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...

void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL.

void	CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
	Initialize the ENET PLL. More...

void	CLOCK_DeinitEnetPll (void)
	Deinitialize the ENET PLL. More...

uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...

void	CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the System PLL PFD. More...

void	CLOCK_DeinitSysPfd (clock_pfd_t pfd)
	De-initialize the System PLL PFD. More...

void	CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the USB1 PLL PFD. More...

void	CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
	De-initialize the USB1 PLL PFD. More...

uint32_t	CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
	Get current System PLL PFD output frequency. More...

uint32_t	CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
	Get current USB1 PLL PFD output frequency. More...

bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

Data Structure Documentation

struct clock_usb_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

Field Documentation

uint8_t clock_usb_pll_config_t::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct clock_sys_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

Field Documentation

uint8_t clock_sys_pll_config_t::loopDivider

Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22

uint32_t clock_sys_pll_config_t::numerator

struct clock_audio_pll_config_t

Fout = Fref * (loopDivider + (float)Numerator/Denominator) / postDivider.

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	postDivider
	Divider after the PLL, should only be 1, 2, 4, 8, 16. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

Field Documentation

uint8_t clock_audio_pll_config_t::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t clock_audio_pll_config_t::postDivider

uint32_t clock_audio_pll_config_t::numerator

struct clock_enet_pll_config_t

Data Fields
bool	enableClkOutput0
	Power on and enable PLL clock output for ENET0 (ref_enetpll0). More...

bool	enableClkOutput1
	Power on and enable PLL clock output for ENET1 (ref_enetpll1). More...

bool	enableClkOutput2
	Power on and enable PLL clock output for ENET2 (ref_enetpll2). More...

uint8_t	loopDivider0
	Controls the frequency of the ENET0 reference clock. More...

uint8_t	loopDivider1
	Controls the frequency of the ENET1 reference clock. More...

Field Documentation

bool clock_enet_pll_config_t::enableClkOutput0

bool clock_enet_pll_config_t::enableClkOutput1

bool clock_enet_pll_config_t::enableClkOutput2

uint8_t clock_enet_pll_config_t::loopDivider0

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

uint8_t clock_enet_pll_config_t::loopDivider1

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))

#define EDMA_CLOCKS

Value:

{                            \
        kCLOCK_Dma0, kCLOCK_Dma1 \
    }

#define ENET_CLOCKS

Value:

{                \
        kCLOCK_Enet0 \
    }

#define LPUART_CLOCKS

Value:

{                                                                  \
        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3 \
    }

#define LPSPI_CLOCKS

Value:

{                                                              \
        kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3 \
    }

#define LPI2C_CLOCKS

Value:

{                                                              \
        kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3 \
    }

#define SNVS_HP_CLOCKS

Value:

{                  \
        kCLOCK_SnvsHp0 \
    }

#define SNVS_LP_CLOCKS

Value:

{                  \
        kCLOCK_SnvsLp0 \
    }

#define CAAM_CLOCKS

Value:

{                \
        kCLOCK_Caam0 \
    }

#define PCTL_CLOCKS

Value:

{                                                                                       \
        kCLOCK_Pctl0, kCLOCK_Pctl1, kCLOCK_Pctl2, kCLOCK_Pctl3, kCLOCK_Pctl4, kCLOCK_Pctl5, \
    }

#define MIPFIL_CLOCKS

Value:

{                  \
        kCLOCK_Micfil0 \
    }

#define FLEXSPI_CLOCKS

Value:

{                                    \
        kCLOCK_Flexspi0, kCLOCK_Flexspi1 \
    }

#define FLEXIO_CLOCKS

Value:

{                                   \
        kCLOCK_Flexio0, kCLOCK_Flexio1, \
    }

#define FLEXCAN_CLOCKS

Value:

{                                    \
        kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
    }

#define SAI_CLOCKS

Value:

{                            \
        kCLOCK_Sai0, kCLOCK_Sai1 \
    }

#define SJC_CLOCKS

Value:

{               \
        kCLOCK_Sjc0 \
    }

#define SPDIF_CLOCKS

Value:

{                 \
        kCLOCK_Spdif0 \
    }

#define ROMC_CLOCKS

Value:

{                \
        kCLOCK_Romc0 \
    }

#define IIM_CLOCKS

Value:

{               \
        kCLOCK_Iim0 \
    }

#define LPSPI_PERIPH_CLOCKS

Value:

{                                                                                       \
        kCLOCK_Lpspi0Periph, kCLOCK_Lpspi1Periph, kCLOCK_Lpspi2Periph, kCLOCK_Lpspi3Periph, \
    }

#define LPUART_PERIPH_CLOCKS

Value:

{                                                                                           \
        kCLOCK_Lpuart0Periph, kCLOCK_Lpuart1Periph, kCLOCK_Lpuart2Periph, kCLOCK_Lpuart3Periph, \
    }

#define LPI2C_PERIPH_CLOCKS

Value:

{                                                                                       \
        kCLOCK_Lpi2c0Periph, kCLOCK_Lpi2c1Periph, kCLOCK_Lpi2c2Periph, kCLOCK_Lpi2c3Periph, \
    }

#define TPSMP_CLOCKS

Value:

{                 \
        kCLOCK_Tpsmp0 \
    }

#define ESAI_CLOCKS

Value:

{                \
        kCLOCK_Esai0 \
    }

#define TPM_CLOCKS

Value:

{                                                       \
        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, \
    }

#define FLEXCAN_PERIPH_CLOCKS

Value:

{                                                 \
        kCLOCK_Flexcan0Periph, kCLOCK_Flexcan1Periph, \
    }

#define LPTMR_PERIPH_CLOCKS

Value:

{                                             \
        kCLOCK_Lptmr0Periph, kCLOCK_Lptmr1Periph, \
    }

#define LPTMR_CLOCKS

Value:

{                                 \
        kCLOCK_Lptmr0, kCLOCK_Lptmr1, \
    }

#define LPIT_PERIPH_CLOCKS

Value:

{                                           \
        kCLOCK_Lpit0Periph, kCLOCK_Lpit1Periph, \
    }

#define LPIT_CLOCKS

Value:

{                               \
        kCLOCK_Lpit0, kCLOCK_Lpit1, \
    }

#define WDOG_CLOCKS

Value:

{                \
        kCLOCK_Wdog0 \
    }

#define USDHC_CLOCKS

Value:

{                                 \
        kCLOCK_Usdhc0, kCLOCK_Usdhc1, \
    }

#define EMVSIM_CLOCKS

Value:

{                                  \
        kCLOCK_Emvsim0, kCLOCK_Emvsim1 \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define CAAM_MEM_CLOCKS

Value:

{                      \
        kCLOCK_CaamMemory0 \
    }

#define CAAM_CTRL_CLOCKS

Value:

{                          \
        kCLOCK_CaamController0 \
    }

#define LPDAC_CLOCKS

Value:

{                             \
        kCLOCK_Lpdac0, kCLOCK_Lpdac1, \
    }

#define ADC_CLOCKS

Value:

{                             \
        kCLOCK_Adc0, kCLOCK_Adc1, \
    }

#define TRGMUX_CLOCKS

Value:

{                   \
        kCLOCK_Trgmux0, \
    }

#define IEE_CLOCKS

Value:

{                \
        kCLOCK_Iee0, \
    }

#define TPIU_CLOCKS

Value:

{                 \
        kCLOCK_Tpiu0, \
    }

#define IOMUXC_CLOCKS

Value:

{                                   \
        kCLOCK_Iomuxc0, kCLOCK_Iomuxc1, \
    }

#define FSL_CLOCK_MMDC_IPG_GATE_COUNT 1U

#define MMDC_ACLK_CLOCKS

Value:

{                     \
        kCLOCK_MmdcAClk   \
    }

#define RGPIO_CLOCKS

Value:

{                  \
        kCLOCK_Rgpio0, \
    }

#define SIM_CLOCKS

Value:

{               \
        kCLOCK_Sim0 \
    }

#define FLEXBUS_CLOCKS

Value:

{                   \
        kCLOCK_Flexbus0 \
    }

#define DMAMUX_CLOCKS

Value:

{                                   \
        kCLOCK_Dmamux0, kCLOCK_Dmamux1, \
    }

#define SDRAM_CLOCKS

Value:

{                  \
        kCLOCK_Sdramc0 \
    }

#define FSL_CLOCK_XRDC_GATE_COUNT 0U

#define kCLOCK_CoreSysClk kCLOCK_CpuClk

#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

Enumeration Type Documentation

enum clock_name_t

Enumerator
kCLOCK_CpuClk	CPU clock.
kCLOCK_AxiClk	AXI bus clock.
kCLOCK_AhbClk	AHB bus clock.
kCLOCK_IpgClk	IPG bus clock.
kCLOCK_FlexBusClk	FlexBus clock.
kCLOCK_RcOscClk	RCOSC clock (internal IRC).
kCLOCK_XtalOscClk	External OSC clock.
kCLOCK_OscClk	OSC clock selected by ANATOP HW_ANADIG_LOWPWR_CTRL[OSC_SEL].
kCLOCK_RtcClk	RTC clock. (RTCCLK)
kCLOCK_Usb1PllClk	USB1PLLCLK.
kCLOCK_Usb1PllPfd0Clk	USB1PLLPDF0CLK.
kCLOCK_Usb1PllPfd1Clk	USB1PLLPFD1CLK.
kCLOCK_Usb1PllPfd2Clk	USB1PLLPFD2CLK.
kCLOCK_Usb1PllPfd3Clk	USB1PLLPFD3CLK.
kCLOCK_Usb2PllClk	USB2PLLCLK.
kCLOCK_SysPllClk	SYSPLLCLK.
kCLOCK_SysPllPfd0Clk	SYSPLLPDF0CLK.
kCLOCK_SysPllPfd1Clk	SYSPLLPFD1CLK.
kCLOCK_SysPllPfd2Clk	SYSPLLPFD2CLK.
kCLOCK_SysPllPfd3Clk	SYSPLLPFD3CLK.
kCLOCK_EnetPll0Clk	Enet PLLCLK ref_enetpll0.
kCLOCK_EnetPll1Clk	Enet PLLCLK ref_enetpll1.
kCLOCK_EnetPll2Clk	Enet PLLCLK ref_enetpll2.
kCLOCK_AudioPllClk	Audio PLLCLK.

enum clock_ip_name_t

Enumerator
kCLOCK_Dma1	DMA1 Clock Gate.
kCLOCK_Dma0	DMA0 Clock Gate.
kCLOCK_Enet0	ENET Clock Gate.
kCLOCK_Lpuart3	LPUART3 Clock Gate.
kCLOCK_Lpuart2	LPUART2 Clock Gate.
kCLOCK_Lpuart1	LPUART1 Clock Gate.
kCLOCK_Lpuart0	LPUART0 Clock Gate.
kCLOCK_Lpspi3	LPSPI3 Clock Gate.
kCLOCK_Lpspi2	LPSPI2 Clock Gate.
kCLOCK_Lpspi1	LPSPI1 Clock Gate.
kCLOCK_Lpspi0	LPSPI0 Clock Gate.
kCLOCK_Lpi2c3	LPI2C3 Debug Clock Gate.
kCLOCK_Lpi2c2	LPI2C2 Debug Clock Gate.
kCLOCK_Lpi2c1	LPI2C1 Debug Clock Gate.
kCLOCK_Lpi2c0	LPI2C0 Debug Clock Gate.
kCLOCK_SnvsHp0	SNVS HP Clock Gate.
kCLOCK_MmdcAClk	MMDC ACLK.
kCLOCK_Caam0	CAAM Clock Gate.
kCLOCK_Pctl5	PCTL5 Clock Gate.
kCLOCK_Pctl4	PCTL4 Clock Gate.
kCLOCK_Pctl3	PCTL3 Clock Gate.
kCLOCK_Pctl2	PCTL2 Clock Gate.
kCLOCK_Pctl1	PCTL1 Clock Gate.
kCLOCK_Pctl0	PCTL0 Clock Gate.
kCLOCK_Flexspi1	FLEXSPI1 Clock Gate.
kCLOCK_Flexspi0	FLEXSPI0 Clock Gate.
kCLOCK_Flexio1	FLEXIO1 Clock Gate.
kCLOCK_Flexio0	FLEXIO0 Clock Gate.
kCLOCK_Sai1	SAI1 Clock Gate.
kCLOCK_Sai0	SAI0 Clock Gate.
kCLOCK_Sjc0	SJC Clock Gate.
kCLOCK_Romc0	ROMC Clock Gate.
kCLOCK_Iim0	IIM Clock Gate.
kCLOCK_Lpspi3Periph	LPSPI3 Peripheral Clock Gate.
kCLOCK_Lpspi2Periph	LPSPI2 Peripheral Clock Gate.
kCLOCK_Lpspi1Periph	LPSPI1 Peripheral Clock Gate.
kCLOCK_Lpspi0Periph	LPSPI0 Peripheral Clock Gate.
kCLOCK_Lpuart3Periph	LPUART3 Peripheral Clock Gate.
kCLOCK_Lpuart2Periph	LPUART2 Peripheral Clock Gate.
kCLOCK_Lpuart1Periph	LPUART1 Peripheral Clock Gate.
kCLOCK_Lpuart0Periph	LPUART0 Peripheral Clock Gate.
kCLOCK_Lpi2c3Periph	LPI2C3 Peripheral Clock Gate.
kCLOCK_Lpi2c2Periph	LPI2C2 Peripheral Clock Gate.
kCLOCK_Lpi2c1Periph	LPI2C1 Peripheral Clock Gate.
kCLOCK_Lpi2c0Periph	LPI2C0 Peripheral Clock Gate.
kCLOCK_Tpsmp0	TPSMP Clock Gate.
kCLOCK_Esai0	ESAI Clock Gate.
kCLOCK_Tpm3	TPM3 Clock Gate.
kCLOCK_Tpm2	TPM2 Clock Gate.
kCLOCK_Tpm1	TPM1 Clock Gate.
kCLOCK_Tpm0	TPM0 Clock Gate.
kCLOCK_Lptmr1Periph	LPTMR1 Peripheral Clock Gate.
kCLOCK_Lptmr1	LPTMR1 Bus Clock Gate.
kCLOCK_Lptmr0Periph	LPTMR0 Peripheral Clock Gate.
kCLOCK_Lptmr0	LPTMR0 Bus Clock Gate.
kCLOCK_Lpit1Periph	LPIT1 Peripheral Clock Gate.
kCLOCK_Lpit1	LPIT1 Bus Clock Gate.
kCLOCK_Lpit0Periph	LPIT0 Peripheral Clock Gate.
kCLOCK_Lpit0	LPIT0 Bus Clock Gate.
kCLOCK_Wdog0	WDOG Clock Gate.
kCLOCK_Usdhc1	USDHC1 Clock Gate.
kCLOCK_Usdhc0	USDHC0 Clock Gate.
kCLOCK_Emvsim1	EMVSIM1 Clock Gate.
kCLOCK_Emvsim0	EMVSIM0 Clock Gate.
kCLOCK_Crc0	CRC Clock Gate.
kCLOCK_Usbhs0	USB Clock Gate.
kCLOCK_CaamController0	CAAM controller Clock Gate.
kCLOCK_CaamMemory0	CAAM memory Clock Gate.
kCLOCK_Lpdac1	DAC1 Clock Gate.
kCLOCK_Lpdac0	DAC0 Clock Gate.
kCLOCK_Adc1	ADC1 Clock Gate.
kCLOCK_Adc0	ADC0 Clock Gate.
kCLOCK_Trgmux0	Trigger MUX Clock Gate.
kCLOCK_Iee0	IEE Clock Gate.
kCLOCK_Tpiu0	TPIU Clock Gate.
kCLOCK_Mmdc0	MMDC channel0 ipg Clock Gate.
kCLOCK_Iomuxc1	IOMUXC1 Clock Gate.
kCLOCK_Iomuxc0	IOMUXC0 Clock Gate.
kCLOCK_Sdramc0	SDRAMC Clock Gate.
kCLOCK_Flexbus0	FLEXBUS Clock Gate.
kCLOCK_Sim0	SIM Clock Gate.
kCLOCK_Dmamux1	DMAMUX1 Clock Gate.
kCLOCK_Dmamux0	DMAMUX0 Clock Gate.
kCLOCK_SnvsLp0	SNVS LP Clock Gate.
kCLOCK_Rgpio0	RGPIO Clock Gate.

enum clock_osc_t

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

enum clock_gate_value_t

Enumerator
kCLOCK_ClockNotNeeded	Clock is off during all modes.
kCLOCK_ClockNeededRun	Clock is on in run mode, but off in WAIT and STOP modes.
kCLOCK_ClockNeededAll	Clock is on in all modes.
kCLOCK_ClockNeededRunWait	Clock is on during all modes, except STOP mode.

enum clock_mode_t

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

enum _clock_interrupt

Enumerator
kCLOCK_MmdcPodfUpdateInterrupt	Interrupt due to update of mask_mmdc_podf.
kCLOCK_MmdcClkSelUpdateInterrupt	Interrupt due to update of mask_mmdc_clk_sel.
kCLOCK_OnChipOscReadyInterrupt	On board oscillator ready.
kCLOCK_PllLrfInterrupt	Interrupt due to lrf of PLLs.

enum clock_mux_t

These constants define the mux control names for clock mux setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

Enumerator
kCLOCK_SysPllMux	SYSTEM PLL SW Clock mux.
kCLOCK_Usb1PllMux	USB1 PLL SW Clock mux.
kCLOCK_OscIrcMux	IRC or external OSC Clock.
kCLOCK_SysClkMux	System Clock mux.
kCLOCK_Enet1588Mux	ENET 1588 Clock mux.
kCLOCK_Lpspi23Mux	LPSPI2 and LPSPI3 Clock mux.
kCLOCK_Lpspi01Mux	LPSPI0 and LPSPI1 Clock mux.
kCLOCK_Flexspi1Mux	FLEXSPI1 Clock2 mux.
kCLOCK_Flexspi0Mux	FLEXSPI0 Clock mux.
kCLOCK_EnetRmiiMux	ENET RMII Clock mux.
kCLOCK_Usdhc1Mux	USDHC1 Clock mux.
kCLOCK_Usdhc0Mux	USDHC0 Clock mux.
kCLOCK_MmdcMux	MMDC Clock mux.
kCLOCK_Tpm23Mux	TPM2 and TPM3 Clock mux.
kCLOCK_Tpm01Mux	TPM0 and TPM1 Clock mux.
kCLOCK_LpitMux	LPIT Clock mux.
kCLOCK_FlexioMux	FLEXIO Clock mux.
kCLOCK_EmvsimMux	EMVSIM Clock mux.
kCLOCK_Lpi2c23Mux	LPI2C2 and LPI2C3 Clock mux.
kCLOCK_Lpi2c01Mux	LPI2C0 and LPI2C1 Clock mux.
kCLOCK_Lpuart23Mux	LPUART2 and LPUART3 Clock mux.
kCLOCK_Lpuart01Mux	LPUART0 and LPUART1 Clock mux.
kCLOCK_TpiuMux	TPIU Clock mux.
kCLOCK_Sai1Mux	SAI1 Clock mux.
kCLOCK_Sai0Mux	SAI0 Pre Clock mux.
kCLOCK_EsaiMux	ESAI Clock mux.

enum clock_div_t

These constants define div control names for clock div setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

Enumerator
kCLOCK_ArmDiv	core div name
kCLOCK_AxiDiv	axi div name
kCLOCK_AhbDiv	ahb div name
kCLOCK_IpgDiv	ipg div name
kCLOCK_FlexBusDiv	FB Clock post divider.
kCLOCK_EnetRmiiDiv	ENET RMII Clock post divider.
kCLOCK_TpiuDiv	TPIU post divider.
kCLOCK_Flexspi1Div	FLEXSPI1 Clock post divider.
kCLOCK_Flexspi0Div	FLEXSPI0 Clock post divider.
kCLOCK_Usdhc1Div	USDHC1 Clock post divider.
kCLOCK_Usdhc0Div	USDHC0 Clock post divider.
kCLOCK_MmdcDiv	MMDC Clock post divider.
kCLOCK_Lpuart23Div	LPUART2 and LPUART3 Clock post divider.
kCLOCK_Lpuart01Div	LPUART0 and LPUART1 Clock post divider.
kCLOCK_Lpspi23Div	LPSPI2 and LPSPI3 Clock post divider .
kCLOCK_Lpspi01Div	LPSPI0 and LPSPI1 Clock post divider .
kCLOCK_LptmrDiv	LPTMR Clock post divider .
kCLOCK_LpitDiv	LPIT Clock post divider.
kCLOCK_Lpi2c23Div	LPI2C2 and LPI2C3 Clock post divider.
kCLOCK_Lpi2c01Div	LPI2C0 and LPI2C1 Clock post divider.
kCLOCK_EmvsimDiv	EMVSIM Clock post divider .
kCLOCK_FlexioDiv	FLEXIO Clock post divider .
kCLOCK_Tpm23Div	TPM2 and TPM3 Clock post divider.
kCLOCK_Tpm01Div	TPM0 and TPM1 Clock post divider.
kCLOCK_EsaiDiv	ESAI Clock post divider.
kCLOCK_Sai1Div	SAI1 Clock post divider.
kCLOCK_Sai0Div	SAI0 Clock post divider.

enum clock_pll_t

Enumerator
kCLOCK_PllSys	PLL SYS.
kCLOCK_PllUsb1	PLL USB1.
kCLOCK_PllAudio	PLL Audio.
kCLOCK_PllEnet0	PLL Enet0.
kCLOCK_PllEnet1	PLL Enet1.
kCLOCK_PllEnet2	PLL Enet2.
kCLOCK_PllUsb2	PLL USB2.

enum clock_pfd_t

Enumerator
kCLOCK_Pfd0	PLL PFD0.
kCLOCK_Pfd1	PLL PFD1.
kCLOCK_Pfd2	PLL PFD2.
kCLOCK_Pfd3	PLL PFD3.

enum clock_usb_src_t

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

enum clock_usb_phy_src_t

Enumerator
kCLOCK_Usbphy480M	Use 480M.

Function Documentation

static void CLOCK_SetMux	(	clock_mux_t	mux,
		uint32_t	value
	)

inlinestatic

Parameters

mux	Which mux node to set, see clock_mux_t.
value	Clock mux value to set, different mux has different value range.

static uint32_t CLOCK_GetMux ( clock_mux_t mux )

inlinestatic

Parameters

mux	Which mux node to get, see clock_mux_t.

Returns: Clock mux value.

static void CLOCK_SetDiv	(	clock_div_t	divider,
		uint32_t	value
	)

inlinestatic

Parameters

divider	Which div node to set, see clock_div_t.
value	Clock div value to set, different divider has different value range.

static uint32_t CLOCK_GetDiv ( clock_div_t divider )

inlinestatic

Parameters

divider Which div node to get, see clock_div_t.

static void CLOCK_ControlGate	(	clock_ip_name_t	name,
		clock_gate_value_t	value
	)

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.
value	Clock gate value to set, see clock_gate_value_t.

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

static void CLOCK_SetMode ( clock_mode_t mode )

inlinestatic

Parameters

mode	Which mode to enter, see clock_mode_t.

static void CLOCK_EnableInterrupts ( uint32_t mask )

inlinestatic

The mask is a logical OR of enumeration members. See _clock_interrupt. This example shows how to enable/not mask the on-chip OSC ready and PLL LRF interrupts:

*     CLOCK_EnableInterrupts(kCLOCK_OnChipOscReadyInterrupt |
* kCLOCK_PllLrfInterrupt);
* 

Parameters

mask	The interrupts to enable. Logical OR of _clock_interrupt.

static void CLOCK_DisableInterrupts ( uint32_t mask )

inlinestatic

The mask is a logical OR of enumeration members. See _clock_interrupt. This example shows how to disable/mask the on-chip OSC ready and PLL LRF interrupts:

*     CLOCK_DisableInterrupts(kCLOCK_OnChipOscReadyInterrupt |
* kCLOCK_PllLrfInterrupt);
* 

Parameters

mask	The interrupts to disable. Logical OR of _clock_interrupt.

static uint32_t CLOCK_GetInterruptStatus ( void )

inlinestatic

The interrupt status flags are returned as the logical OR value of the enumerators _clock_interrupt. To check a specific interrupt enable status, compare the return value with enumerators in _clock_interrupt. For example, to check whether the on-chip OSC ready interrupt is enabled:

*     uint32_t interruptStatus = CLOCK_GetInterruptStatus();
*
*     if (kCLOCK_OnChipOscReadyInterrupt & interruptStatus)
*     {
*         ...
*     }
*
* 

Returns: The interrupts status flags to get. Logical OR of _clock_interrupt.

static void CLOCK_ClearInterruptStatus ( uint32_t mask )

inlinestatic

The interrupt status flags are input as the logical OR value of the enumerators _clock_interrupt.

Parameters

mask	The interrupts status flags to get. Logical OR of _clock_interrupt.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCpuClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAxiBusClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAhbBusClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetIpgBusClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFlexBusClkFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

static uint32_t CLOCK_GetRcOscFreq ( void )

inlinestatic

Returns: Clock frequency.

static uint32_t CLOCK_GetXtalOscFreq ( void )

inlinestatic

Returns: Clock frequency.

uint32_t CLOCK_GetOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetRtcFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

void CLOCK_InitExternalClk ( bool bypassXtalOsc )

This function supports two modes:

Use external crystal oscillator.
Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters

bypassXtalOsc Pass in true to bypass the external crystal oscillator.

void CLOCK_DeinitExternalClk ( void )

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

void CLOCK_SwitchOsc ( clock_osc_t osc )

This function switches the OSC source for SoC.

Parameters

osc	OSC source to switch to.

static void CLOCK_InitRtcRingOsc ( void )

inlinestatic

This function enables the internal ring oscillator that can be used in lieu of an external 32k crystal. The accuracy is relatively poor ~(10-40KHz) over process and environmental conditions. The crystal oscillator is automatically chosen to source the rtc clock if present. The choice is made based on the output of the clock monitor block.

static void CLOCK_DeinitRtcRingOsc ( void )

inlinestatic

This function disables the ANATOP RTC ring OSC.

static void CLOCK_SetXtal0Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL0/EXTAL0 input clock frequency in Hz.

static void CLOCK_SetXtal32Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL32/EXTAL32 input clock frequency in Hz.

void CLOCK_InitSysPll ( const clock_sys_pll_config_t * config )

This function initializes the System PLL with specific settings

Parameters