MCUXpresso SDK API Reference Manual  Rev. 0
NXP Semiconductors
 All Data Structures Functions Variables Typedefs Enumerations Enumerator Groups Pages
Files
Iomuxc_driver

Overview

Files

file  fsl_iomuxc.h
 

Driver version

#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))
 IOMUXC driver version 2.0.0. More...
 

Pin function ID

#define IOMUXC_BOOT_MODE0   0x40064010U, 0, 0, 0, 0x400640DCU
 The pin function ID is a tuple of <muxRegister muxmode="" inputregister="" inputdaisy="" configregister>="">
 
#define IOMUXC_BOOT_MODE1   0x40064014U, 0, 0, 0, 0x400640E0U
 
#define IOMUXC_PTA0_JTAG_TMS_SWD_DIO   0x40064018U, 0xAU, 0, 0, 0x400640E4U
 
#define IOMUXC_PTA0_GPIOA0   0x40064018U, 0x1U, 0, 0, 0x400640E4U
 
#define IOMUXC_PTA0_LPSPI0_PCS1   0x40064018U, 0x3U, 0x400641D4U, 0x0U, 0x400640E4U
 
#define IOMUXC_PTA1_JTAG_TDO   0x4006401CU, 0xAU, 0, 0, 0x400640E8U
 
#define IOMUXC_PTA1_GPIOA1   0x4006401CU, 0x1U, 0, 0, 0x400640E8U
 
#define IOMUXC_PTA1_LPSPI0_PCS2   0x4006401CU, 0x3U, 0x400641D8U, 0x0U, 0x400640E8U
 
#define IOMUXC_PTA2_JTAG_TDI   0x40064020U, 0xAU, 0, 0, 0x400640ECU
 
#define IOMUXC_PTA2_GPIOA2   0x40064020U, 0x1U, 0, 0, 0x400640ECU
 
#define IOMUXC_PTA2_LPSPI0_PCS3   0x40064020U, 0x3U, 0x400641DCU, 0x0U, 0x400640ECU
 
#define IOMUXC_PTA3_JTAG_TCLK_SWD_CLK   0x40064024U, 0xAU, 0, 0, 0x400640F0U
 
#define IOMUXC_PTA3_GPIOA3   0x40064024U, 0x1U, 0, 0, 0x400640F0U
 
#define IOMUXC_PTA3_LPI2C0_SCLS   0x40064024U, 0x5U, 0x400641B0U, 0x0U, 0x400640F0U
 
#define IOMUXC_PTA4_JTAG_TRST_B   0x40064028U, 0xAU, 0, 0, 0x400640F4U
 
#define IOMUXC_PTA4_GPIOA4   0x40064028U, 0x1U, 0, 0, 0x400640F4U
 
#define IOMUXC_PTA4_LPUART0_CTS_B   0x40064028U, 0x4U, 0x40064208U, 0x0U, 0x400640F4U
 
#define IOMUXC_PTA4_LPI2C0_SDAS   0x40064028U, 0x5U, 0x400641B8U, 0x0U, 0x400640F4U
 
#define IOMUXC_PTA5_GPIOA5   0x4006402CU, 0x1U, 0, 0, 0x400640F8U
 
#define IOMUXC_PTA5_LPSPI0_SIN   0x4006402CU, 0x3U, 0x400641E4U, 0x0U, 0x400640F8U
 
#define IOMUXC_PTA5_LPUART0_RTS_B   0x4006402CU, 0x4U, 0, 0, 0x400640F8U
 
#define IOMUXC_PTA5_LPI2C0_SCL   0x4006402CU, 0x5U, 0x400641ACU, 0x0U, 0x400640F8U
 
#define IOMUXC_PTA5_ESAI_RXD3_TXD2   0x4006402CU, 0x7U, 0, 0, 0x400640F8U
 
#define IOMUXC_PTA5_JTAG_MOD   0x4006402CU, 0xAU, 0, 0, 0x400640F8U
 
#define IOMUXC_PTA6_ADC0_IN0   0x40064030U, 0x0U, 0, 0, 0x400640FCU
 
#define IOMUXC_PTA6_GPIOA6   0x40064030U, 0x1U, 0, 0, 0x400640FCU
 
#define IOMUXC_PTA6_LPSPI0_SOUT   0x40064030U, 0x3U, 0x400641E8U, 0x0U, 0x400640FCU
 
#define IOMUXC_PTA6_LPUART0_TX   0x40064030U, 0x4U, 0x40064210U, 0x0U, 0x400640FCU
 
#define IOMUXC_PTA6_LPI2C0_SDA   0x40064030U, 0x5U, 0x400641B4U, 0x0U, 0x400640FCU
 
#define IOMUXC_PTA6_TPM0_CH2   0x40064030U, 0x6U, 0x40064244U, 0x0U, 0x400640FCU
 
#define IOMUXC_PTA6_ESAI_HCKT   0x40064030U, 0x7U, 0x400641A0U, 0x0U, 0x400640FCU
 
#define IOMUXC_PTA6_TRACE_CLKOUT   0x40064030U, 0xAU, 0, 0, 0x400640FCU
 
#define IOMUXC_PTA7_ADC0_IN1   0x40064034U, 0x0U, 0, 0, 0x40064100U
 
#define IOMUXC_PTA7_GPIOA7   0x40064034U, 0x1U, 0, 0, 0x40064100U
 
#define IOMUXC_PTA7_LPSPI0_SCK   0x40064034U, 0x3U, 0x400641E0U, 0x0U, 0x40064100U
 
#define IOMUXC_PTA7_LPUART0_RX   0x40064034U, 0x4U, 0x4006420CU, 0x0U, 0x40064100U
 
#define IOMUXC_PTA7_LPI2C0_HREQ   0x40064034U, 0x5U, 0x400641A8U, 0x0U, 0x40064100U
 
#define IOMUXC_PTA7_TPM0_CH3   0x40064034U, 0x6U, 0, 0, 0x40064100U
 
#define IOMUXC_PTA7_ESAI_HCKR   0x40064034U, 0x7U, 0x4006419CU, 0x0U, 0x40064100U
 
#define IOMUXC_PTA7_TRACE_D0   0x40064034U, 0xAU, 0, 0, 0x40064100U
 
#define IOMUXC_PTA8_ADC0_IN2   0x40064038U, 0x0U, 0, 0, 0x40064104U
 
#define IOMUXC_PTA8_GPIOA8   0x40064038U, 0x1U, 0, 0, 0x40064104U
 
#define IOMUXC_PTA8_LPSPI0_PCS0   0x40064038U, 0x3U, 0x400641D0U, 0x0U, 0x40064104U
 
#define IOMUXC_PTA8_LPUART1_CTS_B   0x40064038U, 0x4U, 0x40064214U, 0x0U, 0x40064104U
 
#define IOMUXC_PTA8_LPI2C1_SCL   0x40064038U, 0x5U, 0x400641C0U, 0x0U, 0x40064104U
 
#define IOMUXC_PTA8_TPM0_CH4   0x40064038U, 0x6U, 0, 0, 0x40064104U
 
#define IOMUXC_PTA8_ESAI_SCKR   0x40064038U, 0x7U, 0x400641A4U, 0x0U, 0x40064104U
 
#define IOMUXC_PTA8_TRACE_D1   0x40064038U, 0xAU, 0, 0, 0x40064104U
 
#define IOMUXC_PTA9_ADC0_IN3   0x4006403CU, 0x0U, 0, 0, 0x40064108U
 
#define IOMUXC_PTA9_GPIOA9   0x4006403CU, 0x1U, 0, 0, 0x40064108U
 
#define IOMUXC_PTA9_LPSPI1_PCS1   0x4006403CU, 0x3U, 0x400641F0U, 0x0U, 0x40064108U
 
#define IOMUXC_PTA9_LPUART1_RTS_B   0x4006403CU, 0x4U, 0, 0, 0x40064108U
 
#define IOMUXC_PTA9_LPI2C1_SDA   0x4006403CU, 0x5U, 0x400641C8U, 0x0U, 0x40064108U
 
#define IOMUXC_PTA9_TPM0_CH5   0x4006403CU, 0x6U, 0, 0, 0x40064108U
 
#define IOMUXC_PTA9_ESAI_FSR   0x4006403CU, 0x7U, 0x40064198U, 0x0U, 0x40064108U
 
#define IOMUXC_PTA9_TRACE_D2   0x4006403CU, 0xAU, 0, 0, 0x40064108U
 
#define IOMUXC_PTA10_TRACE_D3   0x40064040U, 0xAU, 0, 0, 0x4006410CU
 
#define IOMUXC_PTA10_ADC1_IN0   0x40064040U, 0x0U, 0, 0, 0x4006410CU
 
#define IOMUXC_PTA10_GPIOA10   0x40064040U, 0x1U, 0, 0, 0x4006410CU
 
#define IOMUXC_PTA10_LPSPI1_PCS2   0x40064040U, 0x3U, 0x400641F4U, 0x0U, 0x4006410CU
 
#define IOMUXC_PTA10_LPUART1_TX   0x40064040U, 0x4U, 0x4006421CU, 0x0U, 0x4006410CU
 
#define IOMUXC_PTA10_LPI2C1_HREQ   0x40064040U, 0x5U, 0x400641BCU, 0x0U, 0x4006410CU
 
#define IOMUXC_PTA10_TPM0_CLKIN   0x40064040U, 0x6U, 0x40064248U, 0x0U, 0x4006410CU
 
#define IOMUXC_PTA10_ESAI_RXD2_TXD3   0x40064040U, 0x7U, 0, 0, 0x4006410CU
 
#define IOMUXC_PTA11_TRACE_D4   0x40064044U, 0xAU, 0, 0, 0x40064110U
 
#define IOMUXC_PTA11_ADC1_IN1   0x40064044U, 0x0U, 0, 0, 0x40064110U
 
#define IOMUXC_PTA11_GPIOA11   0x40064044U, 0x1U, 0, 0, 0x40064110U
 
#define IOMUXC_PTA11_LPSPI1_PCS3   0x40064044U, 0x3U, 0x400641F8U, 0x0U, 0x40064110U
 
#define IOMUXC_PTA11_LPUART1_RX   0x40064044U, 0x4U, 0x40064218U, 0x0U, 0x40064110U
 
#define IOMUXC_PTA11_LPI2C1_SCLS   0x40064044U, 0x5U, 0x400641C4U, 0x0U, 0x40064110U
 
#define IOMUXC_PTA11_TPM0_CH0   0x40064044U, 0x6U, 0x4006423CU, 0x0U, 0x40064110U
 
#define IOMUXC_PTA11_ESAI_SCKT   0x40064044U, 0x7U, 0, 0, 0x40064110U
 
#define IOMUXC_PTA12_ADC1_IN2   0x40064048U, 0x0U, 0, 0, 0x40064114U
 
#define IOMUXC_PTA12_GPIOA12   0x40064048U, 0x1U, 0, 0, 0x40064114U
 
#define IOMUXC_PTA12_LPSPI1_SIN   0x40064048U, 0x3U, 0x40064200U, 0x0U, 0x40064114U
 
#define IOMUXC_PTA12_TPM0_CH1   0x40064048U, 0x6U, 0x40064240U, 0x0U, 0x40064114U
 
#define IOMUXC_PTA12_ESAI_FST   0x40064048U, 0x7U, 0, 0, 0x40064114U
 
#define IOMUXC_PTA12_TRACE_D5   0x40064048U, 0xAU, 0, 0, 0x40064114U
 
#define IOMUXC_PTA13_ADC1_IN3   0x4006404CU, 0x0U, 0, 0, 0x40064118U
 
#define IOMUXC_PTA13_GPIOA13   0x4006404CU, 0x1U, 0, 0, 0x40064118U
 
#define IOMUXC_PTA13_LPSPI1_SOUT   0x4006404CU, 0x3U, 0x40064204U, 0x0U, 0x40064118U
 
#define IOMUXC_PTA13_TPM1_CH1   0x4006404CU, 0x6U, 0x40064250U, 0x0U, 0x40064118U
 
#define IOMUXC_PTA13_ESAI_TXD0   0x4006404CU, 0x7U, 0, 0, 0x40064118U
 
#define IOMUXC_PTA14_TRACE_D6   0x40064050U, 0xAU, 0, 0, 0x4006411CU
 
#define IOMUXC_PTA14_NMI0_B   0x40064050U, 0xBU, 0x40064238U, 0x0U, 0x4006411CU
 
#define IOMUXC_PTA14_GPIOA14   0x40064050U, 0x1U, 0, 0, 0x4006411CU
 
#define IOMUXC_PTA14_LPSPI1_SCK   0x40064050U, 0x3U, 0x400641FCU, 0x0U, 0x4006411CU
 
#define IOMUXC_PTA14_TPM1_CLKIN   0x40064050U, 0x6U, 0x40064254U, 0x0U, 0x4006411CU
 
#define IOMUXC_PTA14_ESAI_TXD1   0x40064050U, 0x7U, 0, 0, 0x4006411CU
 
#define IOMUXC_PTA15_GPIOA15   0x40064054U, 0x1U, 0, 0, 0x40064120U
 
#define IOMUXC_PTA15_LPSPI1_PCS0   0x40064054U, 0x3U, 0x400641ECU, 0x0U, 0x40064120U
 
#define IOMUXC_PTA15_LPI2C1_SDAS   0x40064054U, 0x5U, 0x400641CCU, 0x0U, 0x40064120U
 
#define IOMUXC_PTA15_TPM1_CH0   0x40064054U, 0x6U, 0x4006424CU, 0x0U, 0x40064120U
 
#define IOMUXC_PTA15_ESAI_HCKR   0x40064054U, 0x7U, 0x4006419CU, 0x1U, 0x40064120U
 
#define IOMUXC_PTA15_ESAI_HCKT   0x40064054U, 0x8U, 0x400641A0U, 0x1U, 0x40064120U
 
#define IOMUXC_PTA15_LGPIOMR0_ALT1   0x40064054U, 0xBU, 0, 0, 0x40064120U
 
#define IOMUXC_PTA16_ADC0_IN4   0x40064058U, 0x0U, 0, 0, 0x40064124U
 
#define IOMUXC_PTA16_GPIOA16   0x40064058U, 0x1U, 0, 0, 0x40064124U
 
#define IOMUXC_PTA16_LPSPI0_PCS1   0x40064058U, 0x3U, 0x400641D4U, 0x1U, 0x40064124U
 
#define IOMUXC_PTA16_LPUART0_CTS_B   0x40064058U, 0x4U, 0x40064208U, 0x1U, 0x40064124U
 
#define IOMUXC_PTA16_LPI2C0_SCL   0x40064058U, 0x5U, 0x400641ACU, 0x1U, 0x40064124U
 
#define IOMUXC_PTA16_ESAI_SCKR   0x40064058U, 0x7U, 0x400641A4U, 0x1U, 0x40064124U
 
#define IOMUXC_PTA17_ADC0_IN5   0x4006405CU, 0x0U, 0, 0, 0x40064128U
 
#define IOMUXC_PTA17_GPIOA17   0x4006405CU, 0x1U, 0, 0, 0x40064128U
 
#define IOMUXC_PTA17_LPSPI0_PCS2   0x4006405CU, 0x3U, 0x400641D8U, 0x1U, 0x40064128U
 
#define IOMUXC_PTA17_LPUART0_RTS_B   0x4006405CU, 0x4U, 0, 0, 0x40064128U
 
#define IOMUXC_PTA17_LPI2C0_SDA   0x4006405CU, 0x5U, 0x400641B4U, 0x1U, 0x40064128U
 
#define IOMUXC_PTA17_ESAI_FSR   0x4006405CU, 0x7U, 0x40064198U, 0x1U, 0x40064128U
 
#define IOMUXC_PTA18_ADC0_IN6   0x40064060U, 0x0U, 0, 0, 0x4006412CU
 
#define IOMUXC_PTA18_GPIOA18   0x40064060U, 0x1U, 0, 0, 0x4006412CU
 
#define IOMUXC_PTA18_LPSPI0_PCS3   0x40064060U, 0x3U, 0x400641DCU, 0x1U, 0x4006412CU
 
#define IOMUXC_PTA18_LPUART0_TX   0x40064060U, 0x4U, 0x40064210U, 0x1U, 0x4006412CU
 
#define IOMUXC_PTA18_LPI2C0_HREQ   0x40064060U, 0x5U, 0x400641A8U, 0x1U, 0x4006412CU
 
#define IOMUXC_PTA18_ESAI_RXD0_TXD5   0x40064060U, 0x7U, 0, 0, 0x4006412CU
 
#define IOMUXC_PTA19_TRACE_D7   0x40064064U, 0xAU, 0, 0, 0x40064130U
 
#define IOMUXC_PTA19_LGPIOMR0_ALT2   0x40064064U, 0xBU, 0, 0, 0x40064130U
 
#define IOMUXC_PTA19_WDOG_B   0x40064064U, 0xCU, 0, 0, 0x40064130U
 
#define IOMUXC_PTA19_ADC0_IN7   0x40064064U, 0x0U, 0, 0, 0x40064130U
 
#define IOMUXC_PTA19_GPIOA19   0x40064064U, 0x1U, 0, 0, 0x40064130U
 
#define IOMUXC_PTA19_LPUART0_RX   0x40064064U, 0x4U, 0x4006420CU, 0x1U, 0x40064130U
 
#define IOMUXC_PTA19_ESAI_RXD1_TXD4   0x40064064U, 0x7U, 0, 0, 0x40064130U
 
#define IOMUXC_PTA20_GPIOA20   0x40064068U, 0x1U, 0, 0, 0x40064134U
 
#define IOMUXC_PTA20_LPSPI0_SIN   0x40064068U, 0x3U, 0x400641E4U, 0x1U, 0x40064134U
 
#define IOMUXC_PTA20_LPUART1_CTS_B   0x40064068U, 0x4U, 0x40064214U, 0x1U, 0x40064134U
 
#define IOMUXC_PTA20_LPI2C0_SCLS   0x40064068U, 0x5U, 0x400641B0U, 0x1U, 0x40064134U
 
#define IOMUXC_PTA20_TPM0_CLKIN   0x40064068U, 0x6U, 0x40064248U, 0x1U, 0x40064134U
 
#define IOMUXC_PTA20_SAI0_TX_BCLK   0x40064068U, 0x7U, 0x40064230U, 0x0U, 0x40064134U
 
#define IOMUXC_PTA20_ESAI_HCKR   0x40064068U, 0x8U, 0x4006419CU, 0x2U, 0x40064134U
 
#define IOMUXC_PTA21_SEC_VIO_IN_5_B   0x4006406CU, 0xCU, 0, 0, 0x40064138U
 
#define IOMUXC_PTA21_GPIOA21   0x4006406CU, 0x1U, 0, 0, 0x40064138U
 
#define IOMUXC_PTA21_LPSPI0_SOUT   0x4006406CU, 0x3U, 0x400641E8U, 0x1U, 0x40064138U
 
#define IOMUXC_PTA21_LPUART1_RTS_B   0x4006406CU, 0x4U, 0, 0, 0x40064138U
 
#define IOMUXC_PTA21_LPI2C0_SDAS   0x4006406CU, 0x5U, 0x400641B8U, 0x1U, 0x40064138U
 
#define IOMUXC_PTA21_TPM0_CH0   0x4006406CU, 0x6U, 0x4006423CU, 0x1U, 0x40064138U
 
#define IOMUXC_PTA21_SAI0_TX_FS   0x4006406CU, 0x7U, 0x40064234U, 0x0U, 0x40064138U
 
#define IOMUXC_PTA22_GPIOA22   0x40064070U, 0x1U, 0, 0, 0x4006413CU
 
#define IOMUXC_PTA22_LPSPI0_SCK   0x40064070U, 0x3U, 0x400641E0U, 0x1U, 0x4006413CU
 
#define IOMUXC_PTA22_LPUART1_TX   0x40064070U, 0x4U, 0x4006421CU, 0x1U, 0x4006413CU
 
#define IOMUXC_PTA22_TPM0_CH1   0x40064070U, 0x6U, 0x40064240U, 0x1U, 0x4006413CU
 
#define IOMUXC_PTA22_SAI0_TXD0   0x40064070U, 0x7U, 0, 0, 0x4006413CU
 
#define IOMUXC_PTA22_SEC_VIO_IN_5_EN   0x40064070U, 0xCU, 0, 0, 0x4006413CU
 
#define IOMUXC_PTA23_PMIC_RDY   0x40064074U, 0xAU, 0, 0, 0x40064140U
 
#define IOMUXC_PTA23_LGPIOMR0_ALT3   0x40064074U, 0xBU, 0, 0, 0x40064140U
 
#define IOMUXC_PTA23_GPIOA23   0x40064074U, 0x1U, 0, 0, 0x40064140U
 
#define IOMUXC_PTA23_LPSPI0_PCS0   0x40064074U, 0x3U, 0x400641D0U, 0x1U, 0x40064140U
 
#define IOMUXC_PTA23_LPUART1_RX   0x40064074U, 0x4U, 0x40064218U, 0x1U, 0x40064140U
 
#define IOMUXC_PTA23_TPM0_CH2   0x40064074U, 0x6U, 0x40064244U, 0x1U, 0x40064140U
 
#define IOMUXC_PTA23_SAI0_TXD1   0x40064074U, 0x7U, 0, 0, 0x40064140U
 
#define IOMUXC_PTB0_GPIOB0   0x40064078U, 0x1U, 0, 0, 0x40064144U
 
#define IOMUXC_PTB0_LPSPI0_SIN   0x40064078U, 0x3U, 0x400641E4U, 0x2U, 0x40064144U
 
#define IOMUXC_PTB0_LPUART0_CTS_B   0x40064078U, 0x4U, 0x40064208U, 0x2U, 0x40064144U
 
#define IOMUXC_PTB0_LPI2C0_HREQ   0x40064078U, 0x5U, 0x400641A8U, 0x2U, 0x40064144U
 
#define IOMUXC_PTB0_SAI0_MCLK   0x40064078U, 0x7U, 0x40064220U, 0x0U, 0x40064144U
 
#define IOMUXC_PTB0_WDOG_B   0x40064078U, 0xCU, 0, 0, 0x40064144U
 
#define IOMUXC_PTB1_GPIOB1   0x4006407CU, 0x1U, 0, 0, 0x40064148U
 
#define IOMUXC_PTB1_LPSPI0_SOUT   0x4006407CU, 0x3U, 0x400641E8U, 0x2U, 0x40064148U
 
#define IOMUXC_PTB1_LPUART0_RX   0x4006407CU, 0x4U, 0x4006420CU, 0x2U, 0x40064148U
 
#define IOMUXC_PTB1_LPI2C0_SDA   0x4006407CU, 0x5U, 0x400641B4U, 0x2U, 0x40064148U
 
#define IOMUXC_PTB1_SAI0_RX_BCLK   0x4006407CU, 0x7U, 0x40064224U, 0x0U, 0x40064148U
 
#define IOMUXC_PTB2_GPIOB2   0x40064080U, 0x1U, 0, 0, 0x4006414CU
 
#define IOMUXC_PTB2_LPSPI0_SCK   0x40064080U, 0x3U, 0x400641E0U, 0x2U, 0x4006414CU
 
#define IOMUXC_PTB2_LPUART0_TX   0x40064080U, 0x4U, 0x40064210U, 0x2U, 0x4006414CU
 
#define IOMUXC_PTB2_LPI2C0_SCL   0x40064080U, 0x5U, 0x400641ACU, 0x2U, 0x4006414CU
 
#define IOMUXC_PTB2_SAI0_RX_FS   0x40064080U, 0x7U, 0x4006422CU, 0x0U, 0x4006414CU
 
#define IOMUXC_PTB3_GPIOB3   0x40064084U, 0x1U, 0, 0, 0x40064150U
 
#define IOMUXC_PTB3_LPSPI0_PCS0   0x40064084U, 0x3U, 0x400641D0U, 0x2U, 0x40064150U
 
#define IOMUXC_PTB3_LPUART0_RTS_B   0x40064084U, 0x4U, 0, 0, 0x40064150U
 
#define IOMUXC_PTB3_SAI0_RXD0   0x40064084U, 0x7U, 0x40064228U, 0x0U, 0x40064150U
 
#define IOMUXC_PTB3_LGPIOMR1_ALT0   0x40064084U, 0xBU, 0, 0, 0x40064150U
 
#define IOMUXC_PTB4_ADC1_IN8   0x40064088U, 0x0U, 0, 0, 0x40064154U
 
#define IOMUXC_PTB4_GPIOB4   0x40064088U, 0x1U, 0, 0, 0x40064154U
 
#define IOMUXC_PTB4_LPSPI0_PCS1   0x40064088U, 0x3U, 0x400641D4U, 0x2U, 0x40064154U
 
#define IOMUXC_PTB4_LPUART1_TX   0x40064088U, 0x4U, 0x4006421CU, 0x2U, 0x40064154U
 
#define IOMUXC_PTB4_LPI2C0_SCLS   0x40064088U, 0x5U, 0x400641B0U, 0x2U, 0x40064154U
 
#define IOMUXC_PTB4_SAI0_RXD1   0x40064088U, 0x7U, 0, 0, 0x40064154U
 
#define IOMUXC_PTB5_ADC1_IN9   0x4006408CU, 0x0U, 0, 0, 0x40064158U
 
#define IOMUXC_PTB5_GPIOB5   0x4006408CU, 0x1U, 0, 0, 0x40064158U
 
#define IOMUXC_PTB5_LPSPI0_PCS2   0x4006408CU, 0x3U, 0x400641D8U, 0x2U, 0x40064158U
 
#define IOMUXC_PTB5_LPUART1_RX   0x4006408CU, 0x4U, 0x40064218U, 0x2U, 0x40064158U
 
#define IOMUXC_PTB5_LPI2C0_SDAS   0x4006408CU, 0x5U, 0x400641B8U, 0x2U, 0x40064158U
 
#define IOMUXC_PTB5_SAI0_TX_BCLK   0x4006408CU, 0x7U, 0x40064230U, 0x1U, 0x40064158U
 
#define IOMUXC_PTB6_ADC0_IN8   0x40064090U, 0x0U, 0, 0, 0x4006415CU
 
#define IOMUXC_PTB6_GPIOB6   0x40064090U, 0x1U, 0, 0, 0x4006415CU
 
#define IOMUXC_PTB6_LPSPI0_PCS3   0x40064090U, 0x3U, 0x400641DCU, 0x2U, 0x4006415CU
 
#define IOMUXC_PTB6_LPUART1_CTS_B   0x40064090U, 0x4U, 0x40064214U, 0x2U, 0x4006415CU
 
#define IOMUXC_PTB6_LPI2C1_SCL   0x40064090U, 0x5U, 0x400641C0U, 0x1U, 0x4006415CU
 
#define IOMUXC_PTB6_SAI0_TX_FS   0x40064090U, 0x7U, 0x40064234U, 0x1U, 0x4006415CU
 
#define IOMUXC_PTB6_LGPIOMR0_ALT0   0x40064090U, 0xBU, 0, 0, 0x4006415CU
 
#define IOMUXC_PTB7_ADC0_IN9   0x40064094U, 0x0U, 0, 0, 0x40064160U
 
#define IOMUXC_PTB7_GPIOB7   0x40064094U, 0x1U, 0, 0, 0x40064160U
 
#define IOMUXC_PTB7_LPUART1_RTS_B   0x40064094U, 0x4U, 0, 0, 0x40064160U
 
#define IOMUXC_PTB7_LPI2C1_SDA   0x40064094U, 0x5U, 0x400641C8U, 0x1U, 0x40064160U
 
#define IOMUXC_PTB7_SAI0_TXD0   0x40064094U, 0x7U, 0, 0, 0x40064160U
 
#define IOMUXC_PTB7_FLEXSPI0A_SS1_B   0x40064094U, 0x8U, 0, 0, 0x40064160U
 
#define IOMUXC_PTB8_ADC1_IN4   0x40064098U, 0x0U, 0, 0, 0x40064164U
 
#define IOMUXC_PTB8_GPIOB8   0x40064098U, 0x1U, 0, 0, 0x40064164U
 
#define IOMUXC_PTB8_LPSPI1_SIN   0x40064098U, 0x3U, 0x40064200U, 0x1U, 0x40064164U
 
#define IOMUXC_PTB8_LPI2C1_HREQ   0x40064098U, 0x5U, 0x400641BCU, 0x1U, 0x40064164U
 
#define IOMUXC_PTB8_TPM0_CLKIN   0x40064098U, 0x6U, 0x40064248U, 0x2U, 0x40064164U
 
#define IOMUXC_PTB8_SAI0_MCLK   0x40064098U, 0x7U, 0x40064220U, 0x1U, 0x40064164U
 
#define IOMUXC_PTB8_FLEXSPI0A_DATA7   0x40064098U, 0x8U, 0, 0, 0x40064164U
 
#define IOMUXC_PTB8_LGPIOMR1_ALT2   0x40064098U, 0xBU, 0, 0, 0x40064164U
 
#define IOMUXC_PTB9_ADC1_IN5   0x4006409CU, 0x0U, 0, 0, 0x40064168U
 
#define IOMUXC_PTB9_GPIOB9   0x4006409CU, 0x1U, 0, 0, 0x40064168U
 
#define IOMUXC_PTB9_LPSPI1_SOUT   0x4006409CU, 0x3U, 0x40064204U, 0x1U, 0x40064168U
 
#define IOMUXC_PTB9_LPI2C1_SCLS   0x4006409CU, 0x5U, 0x400641C4U, 0x1U, 0x40064168U
 
#define IOMUXC_PTB9_TPM0_CH0   0x4006409CU, 0x6U, 0x4006423CU, 0x2U, 0x40064168U
 
#define IOMUXC_PTB9_SAI0_RX_BCLK   0x4006409CU, 0x7U, 0x40064224U, 0x1U, 0x40064168U
 
#define IOMUXC_PTB9_FLEXSPI0A_DATA6   0x4006409CU, 0x8U, 0, 0, 0x40064168U
 
#define IOMUXC_PTB9_LGPIOMR1_ALT3   0x4006409CU, 0xBU, 0, 0, 0x40064168U
 
#define IOMUXC_PTB10_NMI0_B   0x400640A0U, 0xBU, 0x40064238U, 0x1U, 0x4006416CU
 
#define IOMUXC_PTB10_GPIOB10   0x400640A0U, 0x1U, 0, 0, 0x4006416CU
 
#define IOMUXC_PTB10_LPSPI1_SCK   0x400640A0U, 0x3U, 0x400641FCU, 0x1U, 0x4006416CU
 
#define IOMUXC_PTB10_LPI2C1_SDA   0x400640A0U, 0x5U, 0x400641C8U, 0x2U, 0x4006416CU
 
#define IOMUXC_PTB10_TPM0_CH1   0x400640A0U, 0x6U, 0x40064240U, 0x2U, 0x4006416CU
 
#define IOMUXC_PTB10_SAI0_RX_FS   0x400640A0U, 0x7U, 0x4006422CU, 0x1U, 0x4006416CU
 
#define IOMUXC_PTB10_FLEXSPI0A_DATA5   0x400640A0U, 0x8U, 0, 0, 0x4006416CU
 
#define IOMUXC_PTB11_GPIOB11   0x400640A4U, 0x1U, 0, 0, 0x40064170U
 
#define IOMUXC_PTB11_LPSPI1_PCS0   0x400640A4U, 0x3U, 0x400641ECU, 0x1U, 0x40064170U
 
#define IOMUXC_PTB11_LPI2C1_SCL   0x400640A4U, 0x5U, 0x400641C0U, 0x2U, 0x40064170U
 
#define IOMUXC_PTB11_TPM1_CLKIN   0x400640A4U, 0x6U, 0x40064254U, 0x1U, 0x40064170U
 
#define IOMUXC_PTB11_SAI0_RXD0   0x400640A4U, 0x7U, 0x40064228U, 0x1U, 0x40064170U
 
#define IOMUXC_PTB11_FLEXSPI0A_DATA4   0x400640A4U, 0x8U, 0, 0, 0x40064170U
 
#define IOMUXC_PTB12_ADC1_IN6   0x400640A8U, 0x0U, 0, 0, 0x40064174U
 
#define IOMUXC_PTB12_GPIOB12   0x400640A8U, 0x1U, 0, 0, 0x40064174U
 
#define IOMUXC_PTB12_LPSPI1_PCS1   0x400640A8U, 0x3U, 0x400641F0U, 0x1U, 0x40064174U
 
#define IOMUXC_PTB12_LPI2C1_SDAS   0x400640A8U, 0x5U, 0x400641CCU, 0x1U, 0x40064174U
 
#define IOMUXC_PTB12_TPM1_CH0   0x400640A8U, 0x6U, 0x4006424CU, 0x1U, 0x40064174U
 
#define IOMUXC_PTB12_FLEXSPI0A_SS1_B   0x400640A8U, 0x8U, 0, 0, 0x40064174U
 
#define IOMUXC_PTB12_FLEXSPI0A_SCLK_B   0x400640A8U, 0x9U, 0, 0, 0x40064174U
 
#define IOMUXC_PTB13_GPIOB13   0x400640ACU, 0x1U, 0, 0, 0x40064178U
 
#define IOMUXC_PTB13_LPSPI1_PCS2   0x400640ACU, 0x3U, 0x400641F4U, 0x1U, 0x40064178U
 
#define IOMUXC_PTB13_LPI2C1_HREQ   0x400640ACU, 0x5U, 0x400641BCU, 0x2U, 0x40064178U
 
#define IOMUXC_PTB13_TPM1_CH1   0x400640ACU, 0x6U, 0x40064250U, 0x1U, 0x40064178U
 
#define IOMUXC_PTB13_FLEXSPI0A_SS0_B   0x400640ACU, 0x8U, 0, 0, 0x40064178U
 
#define IOMUXC_PTB14_GPIOB14   0x400640B0U, 0x1U, 0, 0, 0x4006417CU
 
#define IOMUXC_PTB14_LPSPI1_PCS3   0x400640B0U, 0x3U, 0x400641F8U, 0x1U, 0x4006417CU
 
#define IOMUXC_PTB14_LPI2C1_SCLS   0x400640B0U, 0x5U, 0x400641C4U, 0x2U, 0x4006417CU
 
#define IOMUXC_PTB14_FLEXSPI0A_SCLK   0x400640B0U, 0x8U, 0, 0, 0x4006417CU
 
#define IOMUXC_PTB15_ADC1_IN7   0x400640B4U, 0x0U, 0, 0, 0x40064180U
 
#define IOMUXC_PTB15_GPIOB15   0x400640B4U, 0x1U, 0, 0, 0x40064180U
 
#define IOMUXC_PTB15_LPI2C1_SDAS   0x400640B4U, 0x5U, 0x400641CCU, 0x2U, 0x40064180U
 
#define IOMUXC_PTB15_FLEXSPI0A_DQS   0x400640B4U, 0x8U, 0, 0, 0x40064180U
 
#define IOMUXC_PTB16_GPIOB16   0x400640B8U, 0x1U, 0, 0, 0x40064184U
 
#define IOMUXC_PTB16_FLEXSPI0A_DATA3   0x400640B8U, 0x8U, 0, 0, 0x40064184U
 
#define IOMUXC_PTB17_GPIOB17   0x400640BCU, 0x1U, 0, 0, 0x40064188U
 
#define IOMUXC_PTB17_FLEXSPI0A_DATA2   0x400640BCU, 0x8U, 0, 0, 0x40064188U
 
#define IOMUXC_PTB18_FLEXSPI0A_DATA1   0x400640C0U, 0x8U, 0, 0, 0x4006418CU
 
#define IOMUXC_PTB18_GPIOB18   0x400640C0U, 0x1U, 0, 0, 0x4006418CU
 
#define IOMUXC_PTB19_GPIOB19   0x400640C4U, 0x1U, 0, 0, 0x40064190U
 
#define IOMUXC_PTB19_FLEXSPI0A_DATA0   0x400640C4U, 0x8U, 0, 0, 0x40064190U
 
#define IOMUXC_TEST_MODE   0, 0, 0, 0, 0x400640C8U
 
#define IOMUXC_POR_B   0, 0, 0, 0, 0x400640CCU
 
#define IOMUXC_ONOFF   0, 0, 0, 0, 0x400640D0U
 
#define IOMUXC_PMIC_ON_REQ   0, 0, 0, 0, 0x400640D4U
 
#define IOMUXC_STANDBY_REQ   0, 0, 0, 0, 0x400640D8U
 
#define IOMUXC_PTC0_GPIOC0   0x40065000U, 0x1U, 0, 0, 0x400651E8U
 
#define IOMUXC_PTC0_FXIO1_D0   0x40065000U, 0x2U, 0, 0, 0x400651E8U
 
#define IOMUXC_PTC0_SDHC0_D1   0x40065000U, 0x7U, 0x40065480U, 0x0U, 0x400651E8U
 
#define IOMUXC_PTC1_GPIOC1   0x40065004U, 0x1U, 0, 0, 0x400651ECU
 
#define IOMUXC_PTC1_FXIO1_D1   0x40065004U, 0x2U, 0, 0, 0x400651ECU
 
#define IOMUXC_PTC1_LPSPI2_PCS1   0x40065004U, 0x3U, 0x400653BCU, 0x0U, 0x400651ECU
 
#define IOMUXC_PTC1_SDHC0_D0   0x40065004U, 0x7U, 0x4006547CU, 0x0U, 0x400651ECU
 
#define IOMUXC_PTC2_GPIOC2   0x40065008U, 0x1U, 0, 0, 0x400651F0U
 
#define IOMUXC_PTC2_FXIO1_D2   0x40065008U, 0x2U, 0, 0, 0x400651F0U
 
#define IOMUXC_PTC2_LPSPI2_PCS2   0x40065008U, 0x3U, 0x400653C0U, 0x0U, 0x400651F0U
 
#define IOMUXC_PTC2_LPUART2_CTS_B   0x40065008U, 0x4U, 0x400653F0U, 0x0U, 0x400651F0U
 
#define IOMUXC_PTC2_SDHC0_CLK   0x40065008U, 0x7U, 0x40065474U, 0x0U, 0x400651F0U
 
#define IOMUXC_PTC3_GPIOC3   0x4006500CU, 0x1U, 0, 0, 0x400651F4U
 
#define IOMUXC_PTC3_FXIO1_D3   0x4006500CU, 0x2U, 0, 0, 0x400651F4U
 
#define IOMUXC_PTC3_LPSPI2_PCS3   0x4006500CU, 0x3U, 0x400653C4U, 0x0U, 0x400651F4U
 
#define IOMUXC_PTC3_LPUART2_RTS_B   0x4006500CU, 0x4U, 0, 0, 0x400651F4U
 
#define IOMUXC_PTC3_SDHC0_CMD   0x4006500CU, 0x7U, 0x40065478U, 0x0U, 0x400651F4U
 
#define IOMUXC_PTC4_GPIOC4   0x40065010U, 0x1U, 0, 0, 0x400651F8U
 
#define IOMUXC_PTC4_EMVSIM1_PD   0x40065010U, 0xAU, 0x40065358U, 0x0U, 0x400651F8U
 
#define IOMUXC_PTC4_FXIO1_D4   0x40065010U, 0x2U, 0, 0, 0x400651F8U
 
#define IOMUXC_PTC4_LPSPI2_SIN   0x40065010U, 0x3U, 0x400653CCU, 0x0U, 0x400651F8U
 
#define IOMUXC_PTC4_LPUART2_TX   0x40065010U, 0x4U, 0x400653F8U, 0x0U, 0x400651F8U
 
#define IOMUXC_PTC4_LPI2C0_SCL   0x40065010U, 0x5U, 0x400641ACU, 0x3U, 0x400651F8U
 
#define IOMUXC_PTC4_SDHC0_D3   0x40065010U, 0x7U, 0x40065488U, 0x0U, 0x400651F8U
 
#define IOMUXC_PTC5_GPIOC5   0x40065014U, 0x1U, 0, 0, 0x400651FCU
 
#define IOMUXC_PTC5_FXIO1_D5   0x40065014U, 0x2U, 0, 0, 0x400651FCU
 
#define IOMUXC_PTC5_LPSPI2_SOUT   0x40065014U, 0x3U, 0x400653D0U, 0x0U, 0x400651FCU
 
#define IOMUXC_PTC5_LPUART2_RX   0x40065014U, 0x4U, 0x400653F4U, 0x0U, 0x400651FCU
 
#define IOMUXC_PTC5_LPI2C0_SDA   0x40065014U, 0x5U, 0x400641B4U, 0x3U, 0x400651FCU
 
#define IOMUXC_PTC5_SDHC0_D2   0x40065014U, 0x7U, 0x40065484U, 0x0U, 0x400651FCU
 
#define IOMUXC_PTC5_EMVSIM1_PF   0x40065014U, 0xAU, 0x4006535CU, 0x0U, 0x400651FCU
 
#define IOMUXC_PTC6_GPIOC6   0x40065018U, 0x1U, 0, 0, 0x40065200U
 
#define IOMUXC_PTC6_FXIO1_D6   0x40065018U, 0x2U, 0, 0, 0x40065200U
 
#define IOMUXC_PTC6_LPI2C0_HREQ   0x40065018U, 0x5U, 0x400641A8U, 0x3U, 0x40065200U
 
#define IOMUXC_PTC6_SAI1_TX_FS   0x40065018U, 0x6U, 0x40065438U, 0x0U, 0x40065200U
 
#define IOMUXC_PTC6_SDHC0_D4   0x40065018U, 0x7U, 0x4006548CU, 0x0U, 0x40065200U
 
#define IOMUXC_PTC6_USB1_OC   0x40065018U, 0xBU, 0x4006546CU, 0x1U, 0x40065200U
 
#define IOMUXC_PTC7_USB1_PWR   0x4006501CU, 0xBU, 0, 0, 0x40065204U
 
#define IOMUXC_PTC7_GPIOC7   0x4006501CU, 0x1U, 0, 0, 0x40065204U
 
#define IOMUXC_PTC7_FXIO1_D7   0x4006501CU, 0x2U, 0, 0, 0x40065204U
 
#define IOMUXC_PTC7_LPI2C0_SCLS   0x4006501CU, 0x5U, 0x400641B0U, 0x3U, 0x40065204U
 
#define IOMUXC_PTC7_SAI1_TXD0   0x4006501CU, 0x6U, 0, 0, 0x40065204U
 
#define IOMUXC_PTC7_SDHC0_D5   0x4006501CU, 0x7U, 0x40065490U, 0x0U, 0x40065204U
 
#define IOMUXC_PTC7_FLEXSPI1A_SS0_B   0x4006501CU, 0x8U, 0, 0, 0x40065204U
 
#define IOMUXC_PTC8_GPIOC8   0x40065020U, 0x1U, 0, 0, 0x40065208U
 
#define IOMUXC_PTC8_FXIO1_D8   0x40065020U, 0x2U, 0, 0, 0x40065208U
 
#define IOMUXC_PTC8_LPI2C0_SDAS   0x40065020U, 0x5U, 0x400641B8U, 0x3U, 0x40065208U
 
#define IOMUXC_PTC8_SAI1_TXD1   0x40065020U, 0x6U, 0, 0, 0x40065208U
 
#define IOMUXC_PTC8_SDHC0_D6   0x40065020U, 0x7U, 0x40065494U, 0x0U, 0x40065208U
 
#define IOMUXC_PTC8_FLEXSPI1A_SS1_B   0x40065020U, 0x8U, 0, 0, 0x40065208U
 
#define IOMUXC_PTC8_USB1_ID   0x40065020U, 0xBU, 0x40065344U, 0x1U, 0x40065208U
 
#define IOMUXC_PTC9_GPIOC9   0x40065024U, 0x1U, 0, 0, 0x4006520CU
 
#define IOMUXC_PTC9_FXIO1_D9   0x40065024U, 0x2U, 0, 0, 0x4006520CU
 
#define IOMUXC_PTC9_SAI1_TX_BCLK   0x40065024U, 0x6U, 0x40065434U, 0x0U, 0x4006520CU
 
#define IOMUXC_PTC9_SDHC0_D7   0x40065024U, 0x7U, 0x40065498U, 0x0U, 0x4006520CU
 
#define IOMUXC_PTC9_FLEXSPI1A_DQS   0x40065024U, 0x8U, 0x40065368U, 0x0U, 0x4006520CU
 
#define IOMUXC_PTC9_USB_PWR_WAKE   0x40065024U, 0xBU, 0, 0, 0x4006520CU
 
#define IOMUXC_PTC10_GPIOC10   0x40065028U, 0x1U, 0, 0, 0x40065210U
 
#define IOMUXC_PTC10_FXIO1_D10   0x40065028U, 0x2U, 0, 0, 0x40065210U
 
#define IOMUXC_PTC10_LPUART3_TX   0x40065028U, 0x4U, 0x40065404U, 0x0U, 0x40065210U
 
#define IOMUXC_PTC10_SAI1_RX_BCLK   0x40065028U, 0x6U, 0x4006541CU, 0x0U, 0x40065210U
 
#define IOMUXC_PTC10_SDHC0_DQS   0x40065028U, 0x7U, 0x4006549CU, 0x0U, 0x40065210U
 
#define IOMUXC_PTC10_FLEXSPI1A_DATA7   0x40065028U, 0x8U, 0x40065388U, 0x0U, 0x40065210U
 
#define IOMUXC_PTC10_EMVSIM1_CLK   0x40065028U, 0xAU, 0, 0, 0x40065210U
 
#define IOMUXC_PTC10_USB_HOST_MODE   0x40065028U, 0xBU, 0, 0, 0x40065210U
 
#define IOMUXC_PTC11_GPIOC11   0x4006502CU, 0x1U, 0, 0, 0x40065214U
 
#define IOMUXC_PTC11_FXIO1_D11   0x4006502CU, 0x2U, 0, 0, 0x40065214U
 
#define IOMUXC_PTC11_LPSPI2_SCK   0x4006502CU, 0x3U, 0x400653C8U, 0x0U, 0x40065214U
 
#define IOMUXC_PTC11_LPUART3_RX   0x4006502CU, 0x4U, 0x40065400U, 0x0U, 0x40065214U
 
#define IOMUXC_PTC11_LPI2C1_SCL   0x4006502CU, 0x5U, 0x400641C0U, 0x3U, 0x40065214U
 
#define IOMUXC_PTC11_SAI1_RX_FS   0x4006502CU, 0x6U, 0x40065430U, 0x0U, 0x40065214U
 
#define IOMUXC_PTC11_SDHC0_RESET   0x4006502CU, 0x7U, 0, 0, 0x40065214U
 
#define IOMUXC_PTC11_FLEXSPI1A_DATA6   0x4006502CU, 0x8U, 0x40065384U, 0x0U, 0x40065214U
 
#define IOMUXC_PTC11_EMVSIM1_RST   0x4006502CU, 0xAU, 0, 0, 0x40065214U
 
#define IOMUXC_PTC11_USB0_OC   0x4006502CU, 0xBU, 0x40065470U, 0x1U, 0x40065214U
 
#define IOMUXC_PTC12_GPIOC12   0x40065030U, 0x1U, 0, 0, 0x40065218U
 
#define IOMUXC_PTC12_FXIO1_D12   0x40065030U, 0x2U, 0, 0, 0x40065218U
 
#define IOMUXC_PTC12_LPSPI2_PCS0   0x40065030U, 0x3U, 0x400653B8U, 0x0U, 0x40065218U
 
#define IOMUXC_PTC12_LPUART3_CTS_B   0x40065030U, 0x4U, 0x400653FCU, 0x0U, 0x40065218U
 
#define IOMUXC_PTC12_LPI2C1_SDA   0x40065030U, 0x5U, 0x400641C8U, 0x3U, 0x40065218U
 
#define IOMUXC_PTC12_SAI1_RXD0   0x40065030U, 0x6U, 0x40065420U, 0x0U, 0x40065218U
 
#define IOMUXC_PTC12_SDHC0_WP   0x40065030U, 0x7U, 0, 0, 0x40065218U
 
#define IOMUXC_PTC12_FLEXSPI1A_DATA5   0x40065030U, 0x8U, 0x40065380U, 0x0U, 0x40065218U
 
#define IOMUXC_PTC12_EMVSIM1_VCCEN   0x40065030U, 0xAU, 0, 0, 0x40065218U
 
#define IOMUXC_PTC12_USB0_PWR   0x40065030U, 0xBU, 0, 0, 0x40065218U
 
#define IOMUXC_PTC13_GPIOC13   0x40065034U, 0x1U, 0, 0, 0x4006521CU
 
#define IOMUXC_PTC13_FXIO1_D13   0x40065034U, 0x2U, 0, 0, 0x4006521CU
 
#define IOMUXC_PTC13_LPSPI3_PCS1   0x40065034U, 0x3U, 0x400653D8U, 0x0U, 0x4006521CU
 
#define IOMUXC_PTC13_LPUART3_RTS_B   0x40065034U, 0x4U, 0, 0, 0x4006521CU
 
#define IOMUXC_PTC13_LPI2C1_HREQ   0x40065034U, 0x5U, 0x400641BCU, 0x3U, 0x4006521CU
 
#define IOMUXC_PTC13_SAI1_RXD1   0x40065034U, 0x6U, 0x40065424U, 0x0U, 0x4006521CU
 
#define IOMUXC_PTC13_SDHC0_CD   0x40065034U, 0x7U, 0, 0, 0x4006521CU
 
#define IOMUXC_PTC13_FLEXSPI1A_DATA4   0x40065034U, 0x8U, 0x4006537CU, 0x0U, 0x4006521CU
 
#define IOMUXC_PTC13_EMVSIM1_IO   0x40065034U, 0xAU, 0x40065354U, 0x0U, 0x4006521CU
 
#define IOMUXC_PTC13_USB0_ID   0x40065034U, 0xBU, 0x40065340U, 0x1U, 0x4006521CU
 
#define IOMUXC_PTC14_GPIOC14   0x40065038U, 0x1U, 0, 0, 0x40065220U
 
#define IOMUXC_PTC14_FXIO1_D14   0x40065038U, 0x2U, 0, 0, 0x40065220U
 
#define IOMUXC_PTC14_LPSPI3_PCS2   0x40065038U, 0x3U, 0x400653DCU, 0x0U, 0x40065220U
 
#define IOMUXC_PTC14_LPI2C1_SCLS   0x40065038U, 0x5U, 0x400641C4U, 0x3U, 0x40065220U
 
#define IOMUXC_PTC14_SAI1_MCLK   0x40065038U, 0x6U, 0x40065418U, 0x0U, 0x40065220U
 
#define IOMUXC_PTC14_SDHC0_VS   0x40065038U, 0x7U, 0, 0, 0x40065220U
 
#define IOMUXC_PTC14_FLEXSPI1A_SS0_B   0x40065038U, 0x8U, 0, 0, 0x40065220U
 
#define IOMUXC_PTC14_FLEXSPI1A_SCLK_B   0x40065038U, 0x9U, 0, 0, 0x40065220U
 
#define IOMUXC_PTC14_EMVSIM0_CLK   0x40065038U, 0xAU, 0, 0, 0x40065220U
 
#define IOMUXC_PTC15_GPIOC15   0x4006503CU, 0x1U, 0, 0, 0x40065224U
 
#define IOMUXC_PTC15_FXIO1_D15   0x4006503CU, 0x2U, 0, 0, 0x40065224U
 
#define IOMUXC_PTC15_LPSPI3_PCS3   0x4006503CU, 0x3U, 0x400653E0U, 0x0U, 0x40065224U
 
#define IOMUXC_PTC15_LPI2C1_SDAS   0x4006503CU, 0x5U, 0x400641CCU, 0x3U, 0x40065224U
 
#define IOMUXC_PTC15_FLEXSPI1A_SCLK   0x4006503CU, 0x8U, 0x4006538CU, 0x0U, 0x40065224U
 
#define IOMUXC_PTC15_EMVSIM0_RST   0x4006503CU, 0xAU, 0, 0, 0x40065224U
 
#define IOMUXC_PTC16_GPIOC16   0x40065040U, 0x1U, 0, 0, 0x40065228U
 
#define IOMUXC_PTC16_LPSPI3_SIN   0x40065040U, 0x3U, 0x400653E8U, 0x0U, 0x40065228U
 
#define IOMUXC_PTC16_SAI1_TXD2   0x40065040U, 0x7U, 0, 0, 0x40065228U
 
#define IOMUXC_PTC16_FLEXSPI1A_DATA3   0x40065040U, 0x8U, 0x40065378U, 0x0U, 0x40065228U
 
#define IOMUXC_PTC16_EMVSIM0_VCCEN   0x40065040U, 0xAU, 0, 0, 0x40065228U
 
#define IOMUXC_PTC17_GPIOC17   0x40065044U, 0x1U, 0, 0, 0x4006522CU
 
#define IOMUXC_PTC17_LPSPI3_SOUT   0x40065044U, 0x3U, 0x400653ECU, 0x0U, 0x4006522CU
 
#define IOMUXC_PTC17_SAI1_TXD3   0x40065044U, 0x7U, 0, 0, 0x4006522CU
 
#define IOMUXC_PTC17_FLEXSPI1A_DATA2   0x40065044U, 0x8U, 0x40065374U, 0x0U, 0x4006522CU
 
#define IOMUXC_PTC17_EMVSIM0_IO   0x40065044U, 0xAU, 0x40065348U, 0x0U, 0x4006522CU
 
#define IOMUXC_PTC18_EMVSIM0_PD   0x40065048U, 0xAU, 0x4006534CU, 0x0U, 0x40065230U
 
#define IOMUXC_PTC18_GPIOC18   0x40065048U, 0x1U, 0, 0, 0x40065230U
 
#define IOMUXC_PTC18_LPSPI3_SCK   0x40065048U, 0x3U, 0x400653E4U, 0x0U, 0x40065230U
 
#define IOMUXC_PTC18_SAI1_RXD2   0x40065048U, 0x7U, 0x40065428U, 0x0U, 0x40065230U
 
#define IOMUXC_PTC18_FLEXSPI1A_DATA1   0x40065048U, 0x8U, 0x40065370U, 0x0U, 0x40065230U
 
#define IOMUXC_PTC19_GPIOC19   0x4006504CU, 0x1U, 0, 0, 0x40065234U
 
#define IOMUXC_PTC19_LPSPI3_PCS0   0x4006504CU, 0x3U, 0x400653D4U, 0x0U, 0x40065234U
 
#define IOMUXC_PTC19_SAI1_RXD3   0x4006504CU, 0x7U, 0x4006542CU, 0x0U, 0x40065234U
 
#define IOMUXC_PTC19_FLEXSPI1A_DATA0   0x4006504CU, 0x8U, 0x4006536CU, 0x0U, 0x40065234U
 
#define IOMUXC_PTC19_EMVSIM0_PF   0x4006504CU, 0xAU, 0x40065350U, 0x0U, 0x40065234U
 
#define IOMUXC_PTD0_GPIOD0   0x40065050U, 0x1U, 0, 0, 0x40065238U
 
#define IOMUXC_PTD0_FB_AD0   0x40065050U, 0x9U, 0, 0, 0x40065238U
 
#define IOMUXC_PTD0_ENET_RXD1   0x40065050U, 0xBU, 0, 0, 0x40065238U
 
#define IOMUXC_PTD1_ENET_RXD0   0x40065054U, 0xBU, 0, 0, 0x4006523CU
 
#define IOMUXC_PTD1_GPIOD1   0x40065054U, 0x1U, 0, 0, 0x4006523CU
 
#define IOMUXC_PTD1_FB_AD1_SDRAM_A9   0x40065054U, 0x9U, 0, 0, 0x4006523CU
 
#define IOMUXC_PTD2_GPIOD2   0x40065058U, 0x1U, 0, 0, 0x40065240U
 
#define IOMUXC_PTD2_FB_AD2_SDRAM_A10   0x40065058U, 0x9U, 0, 0, 0x40065240U
 
#define IOMUXC_PTD2_ENET_TXD1   0x40065058U, 0xBU, 0, 0, 0x40065240U
 
#define IOMUXC_PTD3_GPIOD3   0x4006505CU, 0x1U, 0, 0, 0x40065244U
 
#define IOMUXC_PTD3_FB_AD3_SDRAM_A11   0x4006505CU, 0x9U, 0, 0, 0x40065244U
 
#define IOMUXC_PTD3_ENET_TXD0   0x4006505CU, 0xBU, 0, 0, 0x40065244U
 
#define IOMUXC_PTD4_ENET_TXEN   0x40065060U, 0xBU, 0, 0, 0x40065248U
 
#define IOMUXC_PTD4_GPIOD4   0x40065060U, 0x1U, 0, 0, 0x40065248U
 
#define IOMUXC_PTD4_FB_AD4_SDRAM_A12   0x40065060U, 0x9U, 0, 0, 0x40065248U
 
#define IOMUXC_PTD5_GPIOD5   0x40065064U, 0x1U, 0, 0, 0x4006524CU
 
#define IOMUXC_PTD5_LPSPI2_PCS1   0x40065064U, 0x3U, 0x400653BCU, 0x1U, 0x4006524CU
 
#define IOMUXC_PTD5_FB_AD5_SDRAM_A13   0x40065064U, 0x9U, 0, 0, 0x4006524CU
 
#define IOMUXC_PTD5_ENET_RXER   0x40065064U, 0xBU, 0, 0, 0x4006524CU
 
#define IOMUXC_PTD6_GPIOD6   0x40065068U, 0x1U, 0, 0, 0x40065250U
 
#define IOMUXC_PTD6_LPSPI2_PCS2   0x40065068U, 0x3U, 0x400653C0U, 0x1U, 0x40065250U
 
#define IOMUXC_PTD6_FB_AD6_SDRAM_A14   0x40065068U, 0x9U, 0, 0, 0x40065250U
 
#define IOMUXC_PTD6_ENET_CRS_DV   0x40065068U, 0xBU, 0, 0, 0x40065250U
 
#define IOMUXC_PTD7_ENET_REFCLK   0x4006506CU, 0xBU, 0, 0, 0x40065254U
 
#define IOMUXC_PTD7_GPIOD7   0x4006506CU, 0x1U, 0, 0, 0x40065254U
 
#define IOMUXC_PTD7_LPSPI2_PCS3   0x4006506CU, 0x3U, 0x400653C4U, 0x1U, 0x40065254U
 
#define IOMUXC_PTD7_FB_AD7_SDRAM_A15   0x4006506CU, 0x9U, 0, 0, 0x40065254U
 
#define IOMUXC_PTD8_GPIOD8   0x40065070U, 0x1U, 0, 0, 0x40065258U
 
#define IOMUXC_PTD8_FXIO0_D0   0x40065070U, 0x2U, 0, 0, 0x40065258U
 
#define IOMUXC_PTD8_SAI1_TX_BCLK   0x40065070U, 0x5U, 0x40065434U, 0x1U, 0x40065258U
 
#define IOMUXC_PTD8_FB_AD8_SDRAM_A16   0x40065070U, 0x9U, 0, 0, 0x40065258U
 
#define IOMUXC_PTD8_ENET_MDIO   0x40065070U, 0xBU, 0, 0, 0x40065258U
 
#define IOMUXC_PTD9_GPIOD9   0x40065074U, 0x1U, 0, 0, 0x4006525CU
 
#define IOMUXC_PTD9_FXIO0_D1   0x40065074U, 0x2U, 0, 0, 0x4006525CU
 
#define IOMUXC_PTD9_LPSPI3_PCS1   0x40065074U, 0x3U, 0x400653D8U, 0x1U, 0x4006525CU
 
#define IOMUXC_PTD9_SAI1_TX_FS   0x40065074U, 0x5U, 0x40065438U, 0x1U, 0x4006525CU
 
#define IOMUXC_PTD9_FB_AD9_SDRAM_A17   0x40065074U, 0x9U, 0, 0, 0x4006525CU
 
#define IOMUXC_PTD9_ENET_MDC   0x40065074U, 0xBU, 0, 0, 0x4006525CU
 
#define IOMUXC_PTD10_GPIOD10   0x40065078U, 0x1U, 0, 0, 0x40065260U
 
#define IOMUXC_PTD10_FXIO0_D2   0x40065078U, 0x2U, 0, 0, 0x40065260U
 
#define IOMUXC_PTD10_LPSPI3_PCS2   0x40065078U, 0x3U, 0x400653DCU, 0x1U, 0x40065260U
 
#define IOMUXC_PTD10_SAI1_TXD0   0x40065078U, 0x5U, 0, 0, 0x40065260U
 
#define IOMUXC_PTD10_TPM3_CH2   0x40065078U, 0x6U, 0x40065458U, 0x0U, 0x40065260U
 
#define IOMUXC_PTD10_FB_AD10_SDRAM_A18   0x40065078U, 0x9U, 0, 0, 0x40065260U
 
#define IOMUXC_PTD10_ENET_COL   0x40065078U, 0xBU, 0, 0, 0x40065260U
 
#define IOMUXC_PTD11_GPIOD11   0x4006507CU, 0x1U, 0, 0, 0x40065264U
 
#define IOMUXC_PTD11_FXIO0_D3   0x4006507CU, 0x2U, 0, 0, 0x40065264U
 
#define IOMUXC_PTD11_LPSPI3_PCS3   0x4006507CU, 0x3U, 0x400653E0U, 0x1U, 0x40065264U
 
#define IOMUXC_PTD11_SAI1_TXD1   0x4006507CU, 0x5U, 0, 0, 0x40065264U
 
#define IOMUXC_PTD11_TPM3_CH3   0x4006507CU, 0x6U, 0x4006545CU, 0x0U, 0x40065264U
 
#define IOMUXC_PTD11_FB_AD11_SDRAM_A19   0x4006507CU, 0x9U, 0, 0, 0x40065264U
 
#define IOMUXC_PTD11_TRACE_D7   0x4006507CU, 0xAU, 0, 0, 0x40065264U
 
#define IOMUXC_PTD11_ENET_TXER   0x4006507CU, 0xBU, 0, 0, 0x40065264U
 
#define IOMUXC_PTD12_GPIOD12   0x40065080U, 0x1U, 0, 0, 0x40065268U
 
#define IOMUXC_PTD12_TRACE_D6   0x40065080U, 0xAU, 0, 0, 0x40065268U
 
#define IOMUXC_PTD12_FXIO0_D4   0x40065080U, 0x2U, 0, 0, 0x40065268U
 
#define IOMUXC_PTD12_ENET_CRS   0x40065080U, 0xBU, 0, 0, 0x40065268U
 
#define IOMUXC_PTD12_LPSPI2_SIN   0x40065080U, 0x3U, 0x400653CCU, 0x1U, 0x40065268U
 
#define IOMUXC_PTD12_SAI1_TXD2   0x40065080U, 0x5U, 0, 0, 0x40065268U
 
#define IOMUXC_PTD12_TPM3_CH4   0x40065080U, 0x6U, 0x40065460U, 0x0U, 0x40065268U
 
#define IOMUXC_PTD12_FB_AD12_SDRAM_A20   0x40065080U, 0x9U, 0, 0, 0x40065268U
 
#define IOMUXC_PTD13_GPIOD13   0x40065084U, 0x1U, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD13_FXIO0_D5   0x40065084U, 0x2U, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD13_LPSPI2_SOUT   0x40065084U, 0x3U, 0x400653D0U, 0x1U, 0x4006526CU
 
#define IOMUXC_PTD13_SAI1_TXD3   0x40065084U, 0x5U, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD13_TPM3_CH5   0x40065084U, 0x6U, 0x40065464U, 0x0U, 0x4006526CU
 
#define IOMUXC_PTD13_FB_AD13_SDRAM_A21   0x40065084U, 0x9U, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD13_TRACE_D5   0x40065084U, 0xAU, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD13_ENET_TXCLK   0x40065084U, 0xBU, 0, 0, 0x4006526CU
 
#define IOMUXC_PTD14_GPIOD14   0x40065088U, 0x1U, 0, 0, 0x40065270U
 
#define IOMUXC_PTD14_FXIO0_D6   0x40065088U, 0x2U, 0, 0, 0x40065270U
 
#define IOMUXC_PTD14_LPSPI2_SCK   0x40065088U, 0x3U, 0x400653C8U, 0x1U, 0x40065270U
 
#define IOMUXC_PTD14_SAI1_MCLK   0x40065088U, 0x5U, 0x40065418U, 0x1U, 0x40065270U
 
#define IOMUXC_PTD14_TPM3_CLKIN   0x40065088U, 0x6U, 0x40065468U, 0x0U, 0x40065270U
 
#define IOMUXC_PTD14_FB_AD14_SDRAM_A22   0x40065088U, 0x9U, 0, 0, 0x40065270U
 
#define IOMUXC_PTD14_TRACE_D4   0x40065088U, 0xAU, 0, 0, 0x40065270U
 
#define IOMUXC_PTD14_ENET_TXD3   0x40065088U, 0xBU, 0, 0, 0x40065270U
 
#define IOMUXC_PTD15_TRACE_D3   0x4006508CU, 0xAU, 0, 0, 0x40065274U
 
#define IOMUXC_PTD15_ENET_TXD2   0x4006508CU, 0xBU, 0, 0, 0x40065274U
 
#define IOMUXC_PTD15_GPIOD15   0x4006508CU, 0x1U, 0, 0, 0x40065274U
 
#define IOMUXC_PTD15_FXIO0_D7   0x4006508CU, 0x2U, 0, 0, 0x40065274U
 
#define IOMUXC_PTD15_LPSPI2_PCS0   0x4006508CU, 0x3U, 0x400653B8U, 0x1U, 0x40065274U
 
#define IOMUXC_PTD15_SAI1_RX_BCLK   0x4006508CU, 0x5U, 0x4006541CU, 0x1U, 0x40065274U
 
#define IOMUXC_PTD15_TPM3_CH0   0x4006508CU, 0x6U, 0x40065450U, 0x0U, 0x40065274U
 
#define IOMUXC_PTD15_FB_AD15_SDRAM_A23   0x4006508CU, 0x9U, 0, 0, 0x40065274U
 
#define IOMUXC_PTD16_GPIOD16   0x40065090U, 0x1U, 0, 0, 0x40065278U
 
#define IOMUXC_PTD16_FXIO0_D8   0x40065090U, 0x2U, 0, 0, 0x40065278U
 
#define IOMUXC_PTD16_LPSPI3_SIN   0x40065090U, 0x3U, 0x400653E8U, 0x1U, 0x40065278U
 
#define IOMUXC_PTD16_SAI1_RX_FS   0x40065090U, 0x5U, 0x40065430U, 0x1U, 0x40065278U
 
#define IOMUXC_PTD16_TPM3_CH1   0x40065090U, 0x6U, 0x40065454U, 0x0U, 0x40065278U
 
#define IOMUXC_PTD16_FB_ALE_FB_CS1_B_FB_TS_B   0x40065090U, 0x9U, 0, 0, 0x40065278U
 
#define IOMUXC_PTD16_TRACE_D2   0x40065090U, 0xAU, 0, 0, 0x40065278U
 
#define IOMUXC_PTD16_ENET_RXCLK   0x40065090U, 0xBU, 0, 0, 0x40065278U
 
#define IOMUXC_PTD17_GPIOD17   0x40065094U, 0x1U, 0, 0, 0x4006527CU
 
#define IOMUXC_PTD17_FXIO0_D9   0x40065094U, 0x2U, 0, 0, 0x4006527CU
 
#define IOMUXC_PTD17_LPSPI3_SOUT   0x40065094U, 0x3U, 0x400653ECU, 0x1U, 0x4006527CU
 
#define IOMUXC_PTD17_SAI1_RXD0   0x40065094U, 0x5U, 0x40065420U, 0x1U, 0x4006527CU
 
#define IOMUXC_PTD17_TPM2_CLKIN   0x40065094U, 0x6U, 0x4006544CU, 0x0U, 0x4006527CU
 
#define IOMUXC_PTD17_USB1_OC   0x40065094U, 0x7U, 0x4006546CU, 0x2U, 0x4006527CU
 
#define IOMUXC_PTD17_FB_CS0_B   0x40065094U, 0x9U, 0, 0, 0x4006527CU
 
#define IOMUXC_PTD17_TRACE_D1   0x40065094U, 0xAU, 0, 0, 0x4006527CU
 
#define IOMUXC_PTD17_ENET_RXD3   0x40065094U, 0xBU, 0, 0, 0x4006527CU
 
#define IOMUXC_PTD18_TRACE_D0   0x40065098U, 0xAU, 0, 0, 0x40065280U
 
#define IOMUXC_PTD18_ENET_RXD2   0x40065098U, 0xBU, 0, 0, 0x40065280U
 
#define IOMUXC_PTD18_GPIOD18   0x40065098U, 0x1U, 0, 0, 0x40065280U
 
#define IOMUXC_PTD18_FXIO0_D10   0x40065098U, 0x2U, 0, 0, 0x40065280U
 
#define IOMUXC_PTD18_LPSPI3_SCK   0x40065098U, 0x3U, 0x400653E4U, 0x1U, 0x40065280U
 
#define IOMUXC_PTD18_SAI1_RXD1   0x40065098U, 0x5U, 0x40065424U, 0x1U, 0x40065280U
 
#define IOMUXC_PTD18_TPM2_CH0   0x40065098U, 0x6U, 0x40065444U, 0x0U, 0x40065280U
 
#define IOMUXC_PTD18_USB1_PWR   0x40065098U, 0x7U, 0, 0, 0x40065280U
 
#define IOMUXC_PTD18_FB_OE_B   0x40065098U, 0x9U, 0, 0, 0x40065280U
 
#define IOMUXC_PTD19_GPIOD19   0x4006509CU, 0x1U, 0, 0, 0x40065284U
 
#define IOMUXC_PTD19_FXIO0_D11   0x4006509CU, 0x2U, 0, 0, 0x40065284U
 
#define IOMUXC_PTD19_LPSPI3_PCS0   0x4006509CU, 0x3U, 0x400653D4U, 0x1U, 0x40065284U
 
#define IOMUXC_PTD19_SAI1_RXD2   0x4006509CU, 0x5U, 0x40065428U, 0x1U, 0x40065284U
 
#define IOMUXC_PTD19_TPM2_CH1   0x4006509CU, 0x6U, 0x40065448U, 0x0U, 0x40065284U
 
#define IOMUXC_PTD19_USB1_ID   0x4006509CU, 0x7U, 0x40065344U, 0x2U, 0x40065284U
 
#define IOMUXC_PTD19_FB_A16   0x4006509CU, 0x9U, 0, 0, 0x40065284U
 
#define IOMUXC_PTD19_TRACE_CLKOUT   0x4006509CU, 0xAU, 0, 0, 0x40065284U
 
#define IOMUXC_PTD19_ENET_1588_CLKIN   0x4006509CU, 0xBU, 0, 0, 0x40065284U
 
#define IOMUXC_PTE0_GPIOE0   0x400650A0U, 0x1U, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_FXIO0_D12   0x400650A0U, 0x2U, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_SAI1_RXD3   0x400650A0U, 0x5U, 0x4006542CU, 0x1U, 0x40065288U
 
#define IOMUXC_PTE0_TPM2_CLKIN   0x400650A0U, 0x6U, 0x4006544CU, 0x1U, 0x40065288U
 
#define IOMUXC_PTE0_FLEXSPI1A_SCLK_B   0x400650A0U, 0x7U, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_FLEXSPI1A_SS1_B   0x400650A0U, 0x8U, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_FB_RW_B   0x400650A0U, 0x9U, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_ENET_1588_TIMER0   0x400650A0U, 0xBU, 0, 0, 0x40065288U
 
#define IOMUXC_PTE0_RESET_OUT   0x400650A0U, 0xCU, 0, 0, 0x40065288U
 
#define IOMUXC_PTE1_ENET_1588_TIMER1   0x400650A4U, 0xBU, 0, 0, 0x4006528CU
 
#define IOMUXC_PTE1_GPIOE1   0x400650A4U, 0x1U, 0, 0, 0x4006528CU
 
#define IOMUXC_PTE1_FXIO0_D13   0x400650A4U, 0x2U, 0, 0, 0x4006528CU
 
#define IOMUXC_PTE1_TPM2_CH0   0x400650A4U, 0x6U, 0x40065444U, 0x1U, 0x4006528CU
 
#define IOMUXC_PTE1_FLEXSPI1A_SS0_B   0x400650A4U, 0x8U, 0, 0, 0x4006528CU
 
#define IOMUXC_PTE1_SDRAM_CS0_B   0x400650A4U, 0x9U, 0, 0, 0x4006528CU
 
#define IOMUXC_PTE2_GPIOE2   0x400650A8U, 0x1U, 0, 0, 0x40065290U
 
#define IOMUXC_PTE2_FXIO0_D14   0x400650A8U, 0x2U, 0, 0, 0x40065290U
 
#define IOMUXC_PTE2_TPM2_CH1   0x400650A8U, 0x6U, 0x40065448U, 0x1U, 0x40065290U
 
#define IOMUXC_PTE2_FLEXSPI1A_SCLK   0x400650A8U, 0x8U, 0x4006538CU, 0x1U, 0x40065290U
 
#define IOMUXC_PTE2_SDRAM_WE   0x400650A8U, 0x9U, 0, 0, 0x40065290U
 
#define IOMUXC_PTE2_EMVSIM1_PD   0x400650A8U, 0xAU, 0x40065358U, 0x1U, 0x40065290U
 
#define IOMUXC_PTE2_ENET_1588_TIMER2   0x400650A8U, 0xBU, 0, 0, 0x40065290U
 
#define IOMUXC_PTE3_GPIOE3   0x400650ACU, 0x1U, 0, 0, 0x40065294U
 
#define IOMUXC_PTE3_FXIO0_D15   0x400650ACU, 0x2U, 0, 0, 0x40065294U
 
#define IOMUXC_PTE3_TPM3_CLKIN   0x400650ACU, 0x6U, 0x40065468U, 0x1U, 0x40065294U
 
#define IOMUXC_PTE3_FLEXSPI1A_DQS   0x400650ACU, 0x8U, 0x40065368U, 0x1U, 0x40065294U
 
#define IOMUXC_PTE3_SDRAM_RAS_B   0x400650ACU, 0x9U, 0, 0, 0x40065294U
 
#define IOMUXC_PTE3_EMVSIM1_PF   0x400650ACU, 0xAU, 0x4006535CU, 0x1U, 0x40065294U
 
#define IOMUXC_PTE3_ENET_1588_TIMER3   0x400650ACU, 0xBU, 0, 0, 0x40065294U
 
#define IOMUXC_PTE4_EMVSIM1_CLK   0x400650B0U, 0xAU, 0, 0, 0x40065298U
 
#define IOMUXC_PTE4_BOOT_CFG16   0x400650B0U, 0xCU, 0, 0, 0x40065298U
 
#define IOMUXC_PTE4_GPIOE4   0x400650B0U, 0x1U, 0, 0, 0x40065298U
 
#define IOMUXC_PTE4_FXIO0_D16   0x400650B0U, 0x2U, 0, 0, 0x40065298U
 
#define IOMUXC_PTE4_TPM3_CH0   0x400650B0U, 0x6U, 0x40065450U, 0x1U, 0x40065298U
 
#define IOMUXC_PTE4_FLEXSPI1A_DATA3   0x400650B0U, 0x8U, 0x40065378U, 0x1U, 0x40065298U
 
#define IOMUXC_PTE4_SDRAM_CAS_B   0x400650B0U, 0x9U, 0, 0, 0x40065298U
 
#define IOMUXC_PTE5_GPIOE5   0x400650B4U, 0x1U, 0, 0, 0x4006529CU
 
#define IOMUXC_PTE5_FXIO0_D17   0x400650B4U, 0x2U, 0, 0, 0x4006529CU
 
#define IOMUXC_PTE5_TPM3_CH1   0x400650B4U, 0x6U, 0x40065454U, 0x1U, 0x4006529CU
 
#define IOMUXC_PTE5_FLEXSPI1A_DATA2   0x400650B4U, 0x8U, 0x40065374U, 0x1U, 0x4006529CU
 
#define IOMUXC_PTE5_SDRAM_CKE   0x400650B4U, 0x9U, 0, 0, 0x4006529CU
 
#define IOMUXC_PTE5_EMVSIM1_RST   0x400650B4U, 0xAU, 0, 0, 0x4006529CU
 
#define IOMUXC_PTE5_BOOT_CFG17   0x400650B4U, 0xCU, 0, 0, 0x4006529CU
 
#define IOMUXC_PTE6_GPIOE6   0x400650B8U, 0x1U, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE6_FXIO0_D18   0x400650B8U, 0x2U, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE6_TPM3_CH2   0x400650B8U, 0x6U, 0x40065458U, 0x1U, 0x400652A0U
 
#define IOMUXC_PTE6_USB_PWR_WAKE   0x400650B8U, 0x7U, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE6_FLEXSPI1A_DATA1   0x400650B8U, 0x8U, 0x40065370U, 0x1U, 0x400652A0U
 
#define IOMUXC_PTE6_FB_A17   0x400650B8U, 0x9U, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE6_EMVSIM1_VCCEN   0x400650B8U, 0xAU, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE6_BOOT_CFG18   0x400650B8U, 0xCU, 0, 0, 0x400652A0U
 
#define IOMUXC_PTE7_EMVSIM1_IO   0x400650BCU, 0xAU, 0x40065354U, 0x1U, 0x400652A4U
 
#define IOMUXC_PTE7_BOOT_CFG19   0x400650BCU, 0xCU, 0, 0, 0x400652A4U
 
#define IOMUXC_PTE7_GPIOE7   0x400650BCU, 0x1U, 0, 0, 0x400652A4U
 
#define IOMUXC_PTE7_FXIO0_D19   0x400650BCU, 0x2U, 0, 0, 0x400652A4U
 
#define IOMUXC_PTE7_TPM3_CH3   0x400650BCU, 0x6U, 0x4006545CU, 0x1U, 0x400652A4U
 
#define IOMUXC_PTE7_USB_HOST_MODE   0x400650BCU, 0x7U, 0, 0, 0x400652A4U
 
#define IOMUXC_PTE7_FLEXSPI1A_DATA0   0x400650BCU, 0x8U, 0x4006536CU, 0x1U, 0x400652A4U
 
#define IOMUXC_PTE7_FB_A18   0x400650BCU, 0x9U, 0, 0, 0x400652A4U
 
#define IOMUXC_PTE8_GPIOE8   0x400650C0U, 0x1U, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_FXIO0_D20   0x400650C0U, 0x2U, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_FB_TA_B   0x400650C0U, 0x3U, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_LPUART2_CTS_B   0x400650C0U, 0x4U, 0x400653F0U, 0x1U, 0x400652A8U
 
#define IOMUXC_PTE8_LPI2C2_SCL   0x400650C0U, 0x5U, 0x40065394U, 0x0U, 0x400652A8U
 
#define IOMUXC_PTE8_TPM3_CH4   0x400650C0U, 0x6U, 0x40065460U, 0x1U, 0x400652A8U
 
#define IOMUXC_PTE8_SDHC0_RESET   0x400650C0U, 0x7U, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_FLEXSPI1A_DATA7   0x400650C0U, 0x8U, 0x40065388U, 0x1U, 0x400652A8U
 
#define IOMUXC_PTE8_FB_CS3_B_FB_BE7_0_BLS31_24_B_SDRAM_DQM0   0x400650C0U, 0x9U, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_EMVSIM1_PD   0x400650C0U, 0xAU, 0x40065358U, 0x2U, 0x400652A8U
 
#define IOMUXC_PTE8_USB1_ULPI_STP   0x400650C0U, 0xBU, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE8_BOOT_CFG20   0x400650C0U, 0xCU, 0, 0, 0x400652A8U
 
#define IOMUXC_PTE9_GPIOE9   0x400650C4U, 0x1U, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE9_FXIO0_D21   0x400650C4U, 0x2U, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE9_LPSPI2_SIN   0x400650C4U, 0x3U, 0x400653CCU, 0x2U, 0x400652ACU
 
#define IOMUXC_PTE9_LPUART2_RTS_B   0x400650C4U, 0x4U, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE9_LPI2C2_SDA   0x400650C4U, 0x5U, 0x4006539CU, 0x0U, 0x400652ACU
 
#define IOMUXC_PTE9_TPM3_CH5   0x400650C4U, 0x6U, 0x40065464U, 0x1U, 0x400652ACU
 
#define IOMUXC_PTE9_SDHC0_D7   0x400650C4U, 0x7U, 0x40065498U, 0x1U, 0x400652ACU
 
#define IOMUXC_PTE9_FLEXSPI1A_DATA6   0x400650C4U, 0x8U, 0x40065384U, 0x1U, 0x400652ACU
 
#define IOMUXC_PTE9_FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B_SDRAM_DQM1   0x400650C4U, 0x9U, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE9_EMVSIM1_PF   0x400650C4U, 0xAU, 0x4006535CU, 0x2U, 0x400652ACU
 
#define IOMUXC_PTE9_USB1_ULPI_NXT   0x400650C4U, 0xBU, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE9_BOOT_CFG21   0x400650C4U, 0xCU, 0, 0, 0x400652ACU
 
#define IOMUXC_PTE10_GPIOE10   0x400650C8U, 0x1U, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE10_FXIO0_D22   0x400650C8U, 0x2U, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE10_LPSPI2_SOUT   0x400650C8U, 0x3U, 0x400653D0U, 0x2U, 0x400652B0U
 
#define IOMUXC_PTE10_LPUART2_TX   0x400650C8U, 0x4U, 0x400653F8U, 0x1U, 0x400652B0U
 
#define IOMUXC_PTE10_LPI2C2_HREQ   0x400650C8U, 0x5U, 0x40065390U, 0x0U, 0x400652B0U
 
#define IOMUXC_PTE10_TPM3_CH2   0x400650C8U, 0x6U, 0x40065458U, 0x2U, 0x400652B0U
 
#define IOMUXC_PTE10_SDHC0_D6   0x400650C8U, 0x7U, 0x40065494U, 0x1U, 0x400652B0U
 
#define IOMUXC_PTE10_FLEXSPI1A_DATA5   0x400650C8U, 0x8U, 0x40065380U, 0x1U, 0x400652B0U
 
#define IOMUXC_PTE10_FB_A19   0x400650C8U, 0x9U, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE10_EMVSIM1_CLK   0x400650C8U, 0xAU, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE10_USB1_ULPI_CLK   0x400650C8U, 0xBU, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE10_BOOT_CFG22   0x400650C8U, 0xCU, 0, 0, 0x400652B0U
 
#define IOMUXC_PTE11_EMVSIM1_RST   0x400650CCU, 0xAU, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE11_USB1_ULPI_DIR   0x400650CCU, 0xBU, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE11_BOOT_CFG23   0x400650CCU, 0xCU, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE11_GPIOE11   0x400650CCU, 0x1U, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE11_FXIO0_D23   0x400650CCU, 0x2U, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE11_LPSPI2_SCK   0x400650CCU, 0x3U, 0x400653C8U, 0x2U, 0x400652B4U
 
#define IOMUXC_PTE11_LPUART2_RX   0x400650CCU, 0x4U, 0x400653F4U, 0x1U, 0x400652B4U
 
#define IOMUXC_PTE11_LPI2C2_SCLS   0x400650CCU, 0x5U, 0x40065398U, 0x0U, 0x400652B4U
 
#define IOMUXC_PTE11_TPM3_CH3   0x400650CCU, 0x6U, 0x4006545CU, 0x2U, 0x400652B4U
 
#define IOMUXC_PTE11_SDHC0_D5   0x400650CCU, 0x7U, 0x40065490U, 0x1U, 0x400652B4U
 
#define IOMUXC_PTE11_FLEXSPI1A_DATA4   0x400650CCU, 0x8U, 0x4006537CU, 0x1U, 0x400652B4U
 
#define IOMUXC_PTE11_FB_A20   0x400650CCU, 0x9U, 0, 0, 0x400652B4U
 
#define IOMUXC_PTE12_EMVSIM1_VCCEN   0x400650D0U, 0xAU, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_USB1_ULPI_DATA0   0x400650D0U, 0xBU, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_BOOT_CFG24   0x400650D0U, 0xCU, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_GPIOE12   0x400650D0U, 0x1U, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_FXIO0_D24   0x400650D0U, 0x2U, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_LPSPI2_PCS0   0x400650D0U, 0x3U, 0x400653B8U, 0x2U, 0x400652B8U
 
#define IOMUXC_PTE12_LPUART3_TX   0x400650D0U, 0x4U, 0x40065404U, 0x1U, 0x400652B8U
 
#define IOMUXC_PTE12_LPI2C2_SDAS   0x400650D0U, 0x5U, 0x400653A0U, 0x0U, 0x400652B8U
 
#define IOMUXC_PTE12_TPM3_CH4   0x400650D0U, 0x6U, 0x40065460U, 0x2U, 0x400652B8U
 
#define IOMUXC_PTE12_SDHC0_D4   0x400650D0U, 0x7U, 0x4006548CU, 0x1U, 0x400652B8U
 
#define IOMUXC_PTE12_FLEXSPI1A_SS1_B   0x400650D0U, 0x8U, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE12_FB_A21   0x400650D0U, 0x9U, 0, 0, 0x400652B8U
 
#define IOMUXC_PTE13_GPIOE13   0x400650D4U, 0x1U, 0, 0, 0x400652BCU
 
#define IOMUXC_PTE13_FXIO0_D25   0x400650D4U, 0x2U, 0, 0, 0x400652BCU
 
#define IOMUXC_PTE13_LPSPI2_PCS1   0x400650D4U, 0x3U, 0x400653BCU, 0x2U, 0x400652BCU
 
#define IOMUXC_PTE13_LPUART3_RX   0x400650D4U, 0x4U, 0x40065400U, 0x1U, 0x400652BCU
 
#define IOMUXC_PTE13_LPI2C3_SCL   0x400650D4U, 0x5U, 0x400653A8U, 0x0U, 0x400652BCU
 
#define IOMUXC_PTE13_TPM3_CH5   0x400650D4U, 0x6U, 0x40065464U, 0x2U, 0x400652BCU
 
#define IOMUXC_PTE13_SDHC0_DQS   0x400650D4U, 0x7U, 0x4006549CU, 0x1U, 0x400652BCU
 
#define IOMUXC_PTE13_USB0_OC   0x400650D4U, 0x8U, 0x40065470U, 0x2U, 0x400652BCU
 
#define IOMUXC_PTE13_FB_A22   0x400650D4U, 0x9U, 0, 0, 0x400652BCU
 
#define IOMUXC_PTE13_EMVSIM1_IO   0x400650D4U, 0xAU, 0x40065354U, 0x2U, 0x400652BCU
 
#define IOMUXC_PTE13_USB1_ULPI_DATA1   0x400650D4U, 0xBU, 0, 0, 0x400652BCU
 
#define IOMUXC_PTE13_BOOT_CFG25   0x400650D4U, 0xCU, 0, 0, 0x400652BCU
 
#define IOMUXC_PTE14_EMVSIM0_CLK   0x400650D8U, 0xAU, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_USB1_ULPI_DATA2   0x400650D8U, 0xBU, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_BOOT_CFG26   0x400650D8U, 0xCU, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_GPIOE14   0x400650D8U, 0x1U, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_FXIO0_D26   0x400650D8U, 0x2U, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_LPSPI2_PCS2   0x400650D8U, 0x3U, 0x400653C0U, 0x2U, 0x400652C0U
 
#define IOMUXC_PTE14_LPUART3_CTS_B   0x400650D8U, 0x4U, 0x400653FCU, 0x1U, 0x400652C0U
 
#define IOMUXC_PTE14_LPI2C3_SDA   0x400650D8U, 0x5U, 0x400653B0U, 0x0U, 0x400652C0U
 
#define IOMUXC_PTE14_TPM3_CLKIN   0x400650D8U, 0x6U, 0x40065468U, 0x2U, 0x400652C0U
 
#define IOMUXC_PTE14_SDHC0_CMD   0x400650D8U, 0x7U, 0x40065478U, 0x1U, 0x400652C0U
 
#define IOMUXC_PTE14_USB0_PWR   0x400650D8U, 0x8U, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE14_FB_A23   0x400650D8U, 0x9U, 0, 0, 0x400652C0U
 
#define IOMUXC_PTE15_EMVSIM0_RST   0x400650DCU, 0xAU, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_USB1_ULPI_DATA3   0x400650DCU, 0xBU, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_BOOT_CFG27   0x400650DCU, 0xCU, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_GPIOE15   0x400650DCU, 0x1U, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_FXIO0_D27   0x400650DCU, 0x2U, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_LPSPI2_PCS3   0x400650DCU, 0x3U, 0x400653C4U, 0x2U, 0x400652C4U
 
#define IOMUXC_PTE15_LPUART3_RTS_B   0x400650DCU, 0x4U, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE15_LPI2C3_HREQ   0x400650DCU, 0x5U, 0x400653A4U, 0x0U, 0x400652C4U
 
#define IOMUXC_PTE15_TPM3_CH0   0x400650DCU, 0x6U, 0x40065450U, 0x2U, 0x400652C4U
 
#define IOMUXC_PTE15_SDHC0_D3   0x400650DCU, 0x7U, 0x40065488U, 0x1U, 0x400652C4U
 
#define IOMUXC_PTE15_USB0_ID   0x400650DCU, 0x8U, 0x40065340U, 0x2U, 0x400652C4U
 
#define IOMUXC_PTE15_FB_A24   0x400650DCU, 0x9U, 0, 0, 0x400652C4U
 
#define IOMUXC_PTE16_GPIOE16   0x400650E0U, 0x1U, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE16_FXIO0_D28   0x400650E0U, 0x2U, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE16_LPI2C3_SCLS   0x400650E0U, 0x5U, 0x400653ACU, 0x0U, 0x400652C8U
 
#define IOMUXC_PTE16_TPM3_CH1   0x400650E0U, 0x6U, 0x40065454U, 0x2U, 0x400652C8U
 
#define IOMUXC_PTE16_SDHC0_D2   0x400650E0U, 0x7U, 0x40065484U, 0x1U, 0x400652C8U
 
#define IOMUXC_PTE16_FB_A25   0x400650E0U, 0x9U, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE16_EMVSIM0_VCCEN   0x400650E0U, 0xAU, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE16_USB1_ULPI_DATA4   0x400650E0U, 0xBU, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE16_BOOT_CFG28   0x400650E0U, 0xCU, 0, 0, 0x400652C8U
 
#define IOMUXC_PTE17_EMVSIM0_IO   0x400650E4U, 0xAU, 0x40065348U, 0x1U, 0x400652CCU
 
#define IOMUXC_PTE17_USB1_ULPI_DATA5   0x400650E4U, 0xBU, 0, 0, 0x400652CCU
 
#define IOMUXC_PTE17_BOOT_CFG29   0x400650E4U, 0xCU, 0, 0, 0x400652CCU
 
#define IOMUXC_PTE17_GPIOE17   0x400650E4U, 0x1U, 0, 0, 0x400652CCU
 
#define IOMUXC_PTE17_FXIO0_D29   0x400650E4U, 0x2U, 0, 0, 0x400652CCU
 
#define IOMUXC_PTE17_LPI2C3_SDAS   0x400650E4U, 0x5U, 0x400653B4U, 0x0U, 0x400652CCU
 
#define IOMUXC_PTE17_TPM2_CLKIN   0x400650E4U, 0x6U, 0x4006544CU, 0x2U, 0x400652CCU
 
#define IOMUXC_PTE17_SDHC0_D1   0x400650E4U, 0x7U, 0x40065480U, 0x1U, 0x400652CCU
 
#define IOMUXC_PTE17_CLKOUT   0x400650E4U, 0x9U, 0, 0, 0x400652CCU
 
#define IOMUXC_PTE18_EMVSIM0_PD   0x400650E8U, 0xAU, 0x4006534CU, 0x1U, 0x400652D0U
 
#define IOMUXC_PTE18_USB1_ULPI_DATA6   0x400650E8U, 0xBU, 0, 0, 0x400652D0U
 
#define IOMUXC_PTE18_BOOT_CFG30   0x400650E8U, 0xCU, 0, 0, 0x400652D0U
 
#define IOMUXC_PTE18_GPIOE18   0x400650E8U, 0x1U, 0, 0, 0x400652D0U
 
#define IOMUXC_PTE18_FXIO0_D30   0x400650E8U, 0x2U, 0, 0, 0x400652D0U
 
#define IOMUXC_PTE18_TPM2_CH0   0x400650E8U, 0x6U, 0x40065444U, 0x2U, 0x400652D0U
 
#define IOMUXC_PTE18_SDHC0_D0   0x400650E8U, 0x7U, 0x4006547CU, 0x1U, 0x400652D0U
 
#define IOMUXC_PTE18_FB_CS5_B_FB_TSIZ1_FB_BE23_16_BLS15_8_B_SDRAM_DQM2   0x400650E8U, 0x9U, 0, 0, 0x400652D0U
 
#define IOMUXC_PTE19_GPIOE19   0x400650ECU, 0x1U, 0, 0, 0x400652D4U
 
#define IOMUXC_PTE19_FXIO0_D31   0x400650ECU, 0x2U, 0, 0, 0x400652D4U
 
#define IOMUXC_PTE19_TPM2_CH1   0x400650ECU, 0x6U, 0x40065448U, 0x2U, 0x400652D4U
 
#define IOMUXC_PTE19_SDHC0_CLK   0x400650ECU, 0x7U, 0x40065474U, 0x1U, 0x400652D4U
 
#define IOMUXC_PTE19_FB_AD16_SDRAM_D16   0x400650ECU, 0x9U, 0, 0, 0x400652D4U
 
#define IOMUXC_PTE19_EMVSIM0_PF   0x400650ECU, 0xAU, 0x40065350U, 0x1U, 0x400652D4U
 
#define IOMUXC_PTE19_USB1_ULPI_DATA7   0x400650ECU, 0xBU, 0, 0, 0x400652D4U
 
#define IOMUXC_PTE19_BOOT_CFG31   0x400650ECU, 0xCU, 0, 0, 0x400652D4U
 
#define IOMUXC_PTF0_GPIOF0   0x400650F0U, 0x1U, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF0_FXIO1_D31   0x400650F0U, 0x2U, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF0_SDHC1_D1   0x400650F0U, 0x7U, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF0_FB_AD17_SDRAM_D17   0x400650F0U, 0x9U, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF0_EMVSIM0_CLK   0x400650F0U, 0xAU, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF0_BOOT_CFG0   0x400650F0U, 0xCU, 0, 0, 0x400652D8U
 
#define IOMUXC_PTF1_EMVSIM0_RST   0x400650F4U, 0xAU, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF1_BOOT_CFG1   0x400650F4U, 0xCU, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF1_GPIOF1   0x400650F4U, 0x1U, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF1_FXIO1_D30   0x400650F4U, 0x2U, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF1_SDHC1_D0   0x400650F4U, 0x7U, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF1_FB_AD18_SDRAM_D18   0x400650F4U, 0x9U, 0, 0, 0x400652DCU
 
#define IOMUXC_PTF2_GPIOF2   0x400650F8U, 0x1U, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF2_FXIO1_D29   0x400650F8U, 0x2U, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF2_SDHC1_CLK   0x400650F8U, 0x7U, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF2_EMVSIM0_VCCEN   0x400650F8U, 0xAU, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF2_FB_AD19_SDRAM_D19   0x400650F8U, 0x9U, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF2_BOOT_CFG2   0x400650F8U, 0xCU, 0, 0, 0x400652E0U
 
#define IOMUXC_PTF3_GPIOF3   0x400650FCU, 0x1U, 0, 0, 0x400652E4U
 
#define IOMUXC_PTF3_FXIO1_D28   0x400650FCU, 0x2U, 0, 0, 0x400652E4U
 
#define IOMUXC_PTF3_LPI2C2_SCLS   0x400650FCU, 0x5U, 0x40065398U, 0x1U, 0x400652E4U
 
#define IOMUXC_PTF3_SDHC1_CMD   0x400650FCU, 0x7U, 0, 0, 0x400652E4U
 
#define IOMUXC_PTF3_FB_AD20_SDRAM_D20   0x400650FCU, 0x9U, 0, 0, 0x400652E4U
 
#define IOMUXC_PTF3_EMVSIM0_IO   0x400650FCU, 0xAU, 0x40065348U, 0x2U, 0x400652E4U
 
#define IOMUXC_PTF3_BOOT_CFG3   0x400650FCU, 0xCU, 0, 0, 0x400652E4U
 
#define IOMUXC_PTF4_EMVSIM0_PD   0x40065100U, 0xAU, 0x4006534CU, 0x2U, 0x400652E8U
 
#define IOMUXC_PTF4_BOOT_CFG4   0x40065100U, 0xCU, 0, 0, 0x400652E8U
 
#define IOMUXC_PTF4_GPIOF4   0x40065100U, 0x1U, 0, 0, 0x400652E8U
 
#define IOMUXC_PTF4_FXIO1_D27   0x40065100U, 0x2U, 0, 0, 0x400652E8U
 
#define IOMUXC_PTF4_LPI2C2_SDAS   0x40065100U, 0x5U, 0x400653A0U, 0x1U, 0x400652E8U
 
#define IOMUXC_PTF4_SDHC1_D3   0x40065100U, 0x7U, 0, 0, 0x400652E8U
 
#define IOMUXC_PTF4_FB_AD21_SDRAM_D21   0x40065100U, 0x9U, 0, 0, 0x400652E8U
 
#define IOMUXC_PTF5_EMVSIM0_PF   0x40065104U, 0xAU, 0x40065350U, 0x2U, 0x400652ECU
 
#define IOMUXC_PTF5_BOOT_CFG5   0x40065104U, 0xCU, 0, 0, 0x400652ECU
 
#define IOMUXC_PTF5_GPIOF5   0x40065104U, 0x1U, 0, 0, 0x400652ECU
 
#define IOMUXC_PTF5_FXIO1_D26   0x40065104U, 0x2U, 0, 0, 0x400652ECU
 
#define IOMUXC_PTF5_LPI2C2_HREQ   0x40065104U, 0x5U, 0x40065390U, 0x1U, 0x400652ECU
 
#define IOMUXC_PTF5_SDHC1_D2   0x40065104U, 0x7U, 0, 0, 0x400652ECU
 
#define IOMUXC_PTF5_FB_AD22_SDRAM_D22   0x40065104U, 0x9U, 0, 0, 0x400652ECU
 
#define IOMUXC_PTF6_GPIOF6   0x40065108U, 0x1U, 0, 0, 0x400652F0U
 
#define IOMUXC_PTF6_FXIO1_D25   0x40065108U, 0x2U, 0, 0, 0x400652F0U
 
#define IOMUXC_PTF6_LPI2C2_SCL   0x40065108U, 0x5U, 0x40065394U, 0x1U, 0x400652F0U
 
#define IOMUXC_PTF6_SDHC1_D4   0x40065108U, 0x7U, 0, 0, 0x400652F0U
 
#define IOMUXC_PTF6_FB_AD23_SDRAM_D23   0x40065108U, 0x9U, 0, 0, 0x400652F0U
 
#define IOMUXC_PTF6_BOOT_CFG6   0x40065108U, 0xCU, 0, 0, 0x400652F0U
 
#define IOMUXC_PTF7_TRACE_D7   0x4006510CU, 0xAU, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF7_BOOT_CFG7   0x4006510CU, 0xCU, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF7_GPIOF7   0x4006510CU, 0x1U, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF7_FXIO1_D24   0x4006510CU, 0x2U, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF7_LPI2C2_SDA   0x4006510CU, 0x5U, 0x4006539CU, 0x1U, 0x400652F4U
 
#define IOMUXC_PTF7_SDHC1_D5   0x4006510CU, 0x7U, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF7_FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B_SDRAM_DQM3   0x4006510CU, 0x9U, 0, 0, 0x400652F4U
 
#define IOMUXC_PTF8_TRACE_D6   0x40065110U, 0xAU, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF8_BOOT_CFG8   0x40065110U, 0xCU, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF8_GPIOF8   0x40065110U, 0x1U, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF8_FXIO1_D23   0x40065110U, 0x2U, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF8_LPSPI3_SIN   0x40065110U, 0x3U, 0x400653E8U, 0x2U, 0x400652F8U
 
#define IOMUXC_PTF8_LPUART2_TX   0x40065110U, 0x4U, 0x400653F8U, 0x2U, 0x400652F8U
 
#define IOMUXC_PTF8_SDHC1_WP   0x40065110U, 0x6U, 0x400654A4U, 0x0U, 0x400652F8U
 
#define IOMUXC_PTF8_SDHC1_D6   0x40065110U, 0x7U, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF8_FB_AD24_SDRAM_D24   0x40065110U, 0x9U, 0, 0, 0x400652F8U
 
#define IOMUXC_PTF9_GPIOF9   0x40065114U, 0x1U, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF9_FXIO1_D22   0x40065114U, 0x2U, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF9_LPSPI3_SOUT   0x40065114U, 0x3U, 0x400653ECU, 0x2U, 0x400652FCU
 
#define IOMUXC_PTF9_LPUART2_RX   0x40065114U, 0x4U, 0x400653F4U, 0x2U, 0x400652FCU
 
#define IOMUXC_PTF9_SDHC1_CD   0x40065114U, 0x6U, 0x400654A0U, 0x0U, 0x400652FCU
 
#define IOMUXC_PTF9_SDHC1_D7   0x40065114U, 0x7U, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF9_FB_AD25_SDRAM_D25   0x40065114U, 0x9U, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF9_TRACE_D5   0x40065114U, 0xAU, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF9_BOOT_CFG9   0x40065114U, 0xCU, 0, 0, 0x400652FCU
 
#define IOMUXC_PTF10_GPIOF10   0x40065118U, 0x1U, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_FXIO1_D21   0x40065118U, 0x2U, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_LPSPI3_SCK   0x40065118U, 0x3U, 0x400653E4U, 0x2U, 0x40065300U
 
#define IOMUXC_PTF10_LPUART2_CTS_B   0x40065118U, 0x4U, 0x400653F0U, 0x2U, 0x40065300U
 
#define IOMUXC_PTF10_LPI2C3_SCL   0x40065118U, 0x5U, 0x400653A8U, 0x1U, 0x40065300U
 
#define IOMUXC_PTF10_SDHC1_VS   0x40065118U, 0x6U, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_SDHC1_DQS   0x40065118U, 0x7U, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_FB_AD26_SDRAM_D26   0x40065118U, 0x9U, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_TRACE_D4   0x40065118U, 0xAU, 0, 0, 0x40065300U
 
#define IOMUXC_PTF10_BOOT_CFG10   0x40065118U, 0xCU, 0, 0, 0x40065300U
 
#define IOMUXC_PTF11_TRACE_D3   0x4006511CU, 0xAU, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_BOOT_CFG11   0x4006511CU, 0xCU, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_GPIOF11   0x4006511CU, 0x1U, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_FXIO1_D20   0x4006511CU, 0x2U, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_LPSPI3_PCS0   0x4006511CU, 0x3U, 0x400653D4U, 0x2U, 0x40065304U
 
#define IOMUXC_PTF11_LPUART2_RTS_B   0x4006511CU, 0x4U, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_LPI2C3_SDA   0x4006511CU, 0x5U, 0x400653B0U, 0x1U, 0x40065304U
 
#define IOMUXC_PTF11_SDHC1_RESET   0x4006511CU, 0x7U, 0, 0, 0x40065304U
 
#define IOMUXC_PTF11_FB_AD27_SDRAM_D27   0x4006511CU, 0x9U, 0, 0, 0x40065304U
 
#define IOMUXC_PTF12_TRACE_D2   0x40065120U, 0xAU, 0, 0, 0x40065308U
 
#define IOMUXC_PTF12_BOOT_CFG12   0x40065120U, 0xCU, 0, 0, 0x40065308U
 
#define IOMUXC_PTF12_GPIOF12   0x40065120U, 0x1U, 0, 0, 0x40065308U
 
#define IOMUXC_PTF12_FXIO1_D19   0x40065120U, 0x2U, 0, 0, 0x40065308U
 
#define IOMUXC_PTF12_LPSPI3_PCS1   0x40065120U, 0x3U, 0x400653D8U, 0x2U, 0x40065308U
 
#define IOMUXC_PTF12_LPUART3_TX   0x40065120U, 0x4U, 0x40065404U, 0x2U, 0x40065308U
 
#define IOMUXC_PTF12_LPI2C3_HREQ   0x40065120U, 0x5U, 0x400653A4U, 0x1U, 0x40065308U
 
#define IOMUXC_PTF12_SDHC1_WP   0x40065120U, 0x7U, 0x400654A4U, 0x1U, 0x40065308U
 
#define IOMUXC_PTF12_FB_AD28_SDRAM_D28   0x40065120U, 0x9U, 0, 0, 0x40065308U
 
#define IOMUXC_PTF13_GPIOF13   0x40065124U, 0x1U, 0, 0, 0x4006530CU
 
#define IOMUXC_PTF13_FXIO1_D18   0x40065124U, 0x2U, 0, 0, 0x4006530CU
 
#define IOMUXC_PTF13_LPSPI3_PCS2   0x40065124U, 0x3U, 0x400653DCU, 0x2U, 0x4006530CU
 
#define IOMUXC_PTF13_LPUART3_RX   0x40065124U, 0x4U, 0x40065400U, 0x2U, 0x4006530CU
 
#define IOMUXC_PTF13_LPI2C3_SCLS   0x40065124U, 0x5U, 0x400653ACU, 0x1U, 0x4006530CU
 
#define IOMUXC_PTF13_SDHC1_CD   0x40065124U, 0x7U, 0x400654A0U, 0x1U, 0x4006530CU
 
#define IOMUXC_PTF13_FB_AD29_SDRAM_D29   0x40065124U, 0x9U, 0, 0, 0x4006530CU
 
#define IOMUXC_PTF13_TRACE_D1   0x40065124U, 0xAU, 0, 0, 0x4006530CU
 
#define IOMUXC_PTF13_BOOT_CFG13   0x40065124U, 0xCU, 0, 0, 0x4006530CU
 
#define IOMUXC_PTF14_TRACE_D0   0x40065128U, 0xAU, 0, 0, 0x40065310U
 
#define IOMUXC_PTF14_BOOT_CFG14   0x40065128U, 0xCU, 0, 0, 0x40065310U
 
#define IOMUXC_PTF14_GPIOF14   0x40065128U, 0x1U, 0, 0, 0x40065310U
 
#define IOMUXC_PTF14_FXIO1_D17   0x40065128U, 0x2U, 0, 0, 0x40065310U
 
#define IOMUXC_PTF14_LPSPI3_PCS3   0x40065128U, 0x3U, 0x400653E0U, 0x2U, 0x40065310U
 
#define IOMUXC_PTF14_LPUART3_CTS_B   0x40065128U, 0x4U, 0x400653FCU, 0x2U, 0x40065310U
 
#define IOMUXC_PTF14_LPI2C3_SDAS   0x40065128U, 0x5U, 0x400653B4U, 0x1U, 0x40065310U
 
#define IOMUXC_PTF14_SDHC1_VS   0x40065128U, 0x7U, 0, 0, 0x40065310U
 
#define IOMUXC_PTF14_FB_AD30_SDRAM_D30   0x40065128U, 0x9U, 0, 0, 0x40065310U
 
#define IOMUXC_PTF15_TRACE_CLKOUT   0x4006512CU, 0xAU, 0, 0, 0x40065314U
 
#define IOMUXC_PTF15_BOOT_CFG15   0x4006512CU, 0xCU, 0, 0, 0x40065314U
 
#define IOMUXC_PTF15_GPIOF15   0x4006512CU, 0x1U, 0, 0, 0x40065314U
 
#define IOMUXC_PTF15_FXIO1_D16   0x4006512CU, 0x2U, 0, 0, 0x40065314U
 
#define IOMUXC_PTF15_LPUART3_RTS_B   0x4006512CU, 0x4U, 0, 0, 0x40065314U
 
#define IOMUXC_PTF15_FB_AD31_SDRAM_D31   0x4006512CU, 0x9U, 0, 0, 0x40065314U
 
#define IOMUXC_DDR_CA0   0, 0, 0, 0, 0x40065130U
 
#define IOMUXC_DDR_CA1   0, 0, 0, 0, 0x40065134U
 
#define IOMUXC_DDR_CA2   0, 0, 0, 0, 0x40065138U
 
#define IOMUXC_DDR_CA3   0, 0, 0, 0, 0x4006513CU
 
#define IOMUXC_DDR_CA4   0, 0, 0, 0, 0x40065140U
 
#define IOMUXC_DDR_CA5   0, 0, 0, 0, 0x40065144U
 
#define IOMUXC_DDR_CA6   0, 0, 0, 0, 0x40065148U
 
#define IOMUXC_DDR_CA7   0, 0, 0, 0, 0x4006514CU
 
#define IOMUXC_DDR_CA8   0, 0, 0, 0, 0x40065150U
 
#define IOMUXC_DDR_CA9   0, 0, 0, 0, 0x40065154U
 
#define IOMUXC_DDR_DQM0   0, 0, 0, 0, 0x40065170U
 
#define IOMUXC_DDR_DQM1   0, 0, 0, 0, 0x40065174U
 
#define IOMUXC_DDR_CS0_B   0, 0, 0, 0, 0x40065180U
 
#define IOMUXC_DDR_CKE0   0, 0, 0, 0, 0x400651A0U
 
#define IOMUXC_DDR_CLK0   0, 0, 0, 0, 0x400651A8U
 
#define IOMUXC_DDR_DQS0   0, 0, 0, 0, 0x400651ACU
 
#define IOMUXC_DDR_DQS1   0, 0, 0, 0, 0x400651B0U
 
#define IOMUXC_TAMPER0   0, 0, 0, 0, 0x400651B8U
 
#define IOMUXC_TAMPER1   0, 0, 0, 0, 0x400651BCU
 
#define IOMUXC_TAMPER2   0, 0, 0, 0, 0x400651C0U
 
#define IOMUXC_TAMPER3   0, 0, 0, 0, 0x400651C4U
 
#define IOMUXC_TAMPER4   0, 0, 0, 0, 0x400651C8U
 
#define IOMUXC_TAMPER5   0, 0, 0, 0, 0x400651CCU
 
#define IOMUXC_TAMPER6   0, 0, 0, 0, 0x400651D0U
 
#define IOMUXC_TAMPER7   0, 0, 0, 0, 0x400651D4U
 
#define IOMUXC_TAMPER8   0, 0, 0, 0, 0x400651D8U
 
#define IOMUXC_TAMPER9   0, 0, 0, 0, 0x400651DCU
 
#define IOMUXC_TAMPER10   0, 0, 0, 0, 0x400651E0U
 
#define IOMUXC_TAMPER11   0, 0, 0, 0, 0x400651E4U
 
#define IOMUXC_GRP_ADDDS   0, 0, 0, 0, 0x40065318U
 
#define IOMUXC_GRP_DDRMODE_CTL   0, 0, 0, 0, 0x4006531CU
 
#define IOMUXC_GRP_B0DS   0, 0, 0, 0, 0x40065320U
 
#define IOMUXC_GRP_DDRPK   0, 0, 0, 0, 0x40065324U
 
#define IOMUXC_GRP_CTLDS   0, 0, 0, 0, 0x40065328U
 
#define IOMUXC_GRP_B1DS   0, 0, 0, 0, 0x4006532CU
 
#define IOMUXC_GRP_DDRHYS   0, 0, 0, 0, 0x40065330U
 
#define IOMUXC_GRP_DDRPKE   0, 0, 0, 0, 0x40065334U
 
#define IOMUXC_GRP_DDRMODE   0, 0, 0, 0, 0x40065338U
 
#define IOMUXC_GRP_DDR_TYPE   0, 0, 0, 0, 0x4006533CU
 

Configuration

static void IOMUXC_SetPinMux (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)
 Sets the IOMUXC pin mux mode. More...
 
static void IOMUXC_SetPinConfig (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)
 Sets the IOMUXC pin configuration. More...
 

Macro Definition Documentation

#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))

Function Documentation

static void IOMUXC_SetPinMux ( uint32_t  muxRegister,
uint32_t  muxMode,
uint32_t  inputRegister,
uint32_t  inputDaisy,
uint32_t  configRegister,
uint32_t  inputOnfield 
)
inlinestatic
Note
The first five parameters can be filled with the pin function ID macros.

This is an example to set the PTA6 as the lpuart0_tx:

* IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
*

This is an example to set the PTA0 as GPIOA0:

* IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
*
Parameters
muxRegisterThe pin mux register.
muxModeThe pin mux mode.
inputRegisterThe select input register.
inputDaisyThe input daisy.
configRegisterThe config register.
inputOnfieldSoftware input on field.
static void IOMUXC_SetPinConfig ( uint32_t  muxRegister,
uint32_t  muxMode,
uint32_t  inputRegister,
uint32_t  inputDaisy,
uint32_t  configRegister,
uint32_t  configValue 
)
inlinestatic
Note
The previous five parameters can be filled with the pin function ID macros.

This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:

* IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC0_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC0_SW_PAD_CTL_PAD_PUS(2U))
*
Parameters
muxRegisterThe pin mux register.
muxModeThe pin mux mode.
inputRegisterThe select input register.
inputDaisyThe input daisy.
configRegisterThe config register.
configValueThe pin config value.