Overview

The MCUXpresso SDK provides a peripheral driver for the Multi Mode DDR Controller block of MCUXpresso SDK devices.

The MMDC is configurable high performance and optimized DDR controller that support LPDDR2 x16 memory type. The MMDC driver provide function API to config the MMDC core and PHY register.

Typical use case

This example shows how to use the MMDC driver to initialize the external 16 bit DDR device. Initialize the MMDC controller and run the initialization sequence. The external DDR device is initialized and the DDR read and write is available.

Initialize the LPDDR2 Controller and external device.

mmdc_device_timing_t timing = 
{
    .tCKE_Clocks = 3U,
    .tCKSRE_Clocks = 2U,
    .tCKSRX_Clocks = 2U,
    .tRFC_Clocks = 40U,
    .tXSR_Clocks = 43U,
    .tXP_Clocks = 3U,
    .tFAW_Clocks = 16U,
    .tCL_Clocks = 3U,
    .tMRD_Clocks = 3U, 
    .tRAS_Clocks = 13U,
    .tWR_Clocks = 5U,
    .tRTP_Clocks = 3U,
    .tWTR_Clocks = 4U,
    .tRRD_Clocks = 4U,
    .ralat_Clocks = 5U,
    .walat_Clocks = 0U,
    .tRC_Clocks = 19U,
    .tRCD_Clocks = 6U,
    .tRP_Clocks = 6U,
    .tRPA_Clocks = 7U,
    .tCWL_Clocks = 1U,
    .tRSTtoCKE_Clocks = 14U,
    .tXPR_Clocks = 159U,
    .tRTWSAME_Clocks = 2U,
    .tWTRDIFF_Clocks = 3U,
    .tWTWDIFF_Clocks = 3U,
    .tRTWDIFF_Clocks = 2U,
    .tRTRDIFF_Clocks = 2U,
    .tDAI_Clocks = 3001U,    
};
mmdc_fine_tuning_config_t tuning = 
{
    .caDelay = 0x47U,
    .rDQOffset0 = 0x33333333U,
    .rDQOffset1 = 0x33333333U,
    .wDQOffset0 = 0xf3333333U,
    .wDQOffset1 = 0xf3333333U,
    .rDQDuty0 =  kMMDC_DutyHighPercent50,
    .rDQDuty1 =  kMMDC_DutyHighPercent50,
    .ddrCKDutyCtl0 = kMMDC_DutyHighPercent50,
    .ddrCKDutyCtl1 = kMMDC_DutyHighPercent50,
    .wDQDuty0 =  kMMDC_DutyHighPercent50,
    .wDQDuty1 =  kMMDC_DutyHighPercent50,    
};
mmdc_zq_config_t zqCal = 
{
    .mode = kMMDC_ZQCaltoIODeviceLongShort,
    .earlyCompTimer = 21U,
    .hwZQFreq = kMMDC_ZQCalFreq1ms,
    .cmpOutSample = 15U,
    .tZQCl_Clocks = 144U,
    .tZQCs_Clocks = 112U,
    .tZQInit_Clocks = 400U,
    .cmpOutSample = 7,
    .hwPullDownOffset = 0U,
    .hwPullUpOffset = 0U,    
};
    mmdc_config_t userConfig;
    mmdc_zq_config_t zqCal;
    mmdc_read_calibration_config_t readCal;
    mmdc_write_calibration_config_t writeCal;
    mmdc_device_config_t config;
    mmdc_auto_refresh_t autoRefresh;
    readCal.mode = kMMDC_CalWithMPR;
    readCal.readDelay0 = 0x40U;
    readCal.readDelay1 = 0x40U;
    writeCal.mode = kMMDC_CalWithPreDefine;
    writeCal.writeDelay0 = 0x40U;
    writeCal.writeDelay1 = 0x40U;
    config.MR1 = 0x82U;
    config.MR2 = 0x01U;
    config.MR3 = 0x01U;
    autoRefresh.refreshCnt = 0;
    autoRefresh.refreshRate = 4;
    autoRefresh.refreshTrigSrc = kMMDC_RefreshTrigBy64K;
    /* 
    *  config->bankInterleave = true;
    *  config->secondDDRClock = true;
    *  config->enableOnlyCS0 = true;
    *  config->devType = kMMDC_DDR3;
    *  config->devSize = 0x40000000U;
    *  config->devBank = kMMDC_Bank8;
    *  config->rowWidth = kMMDC_Row16Bits;
    *  config->colWidth = kMMDC_Col10Bits;
    *  config->burstLen = kMMDC_BurstLen8;
    *  config->odtByte1Config = kMMDC_RttNom60ohm;
    *  config->odtByte0Config = kMMDC_RttNom60ohm;    
    *  config->enableActiveReadOdt = false;
    *  config->enableInactiveReadOdt = true;
    *  config->enableActiveWriteOdt = true;
    *  config->enableInactiveWriteOdt = true;
    */
    MMDC_GetDefaultConfig(&userConfig);
    userConfig.devType = kMMDC_LPDDR2_S4;
    userConfig.devSize = EXAMPLE_DDR_SIZE;
    userConfig.rowWidth = EXAMPLE_DDR_ROW_WIDTH;
    userConfig.colWidth = EXAMPLE_DDR_COL_WIDTH;
    userConfig.burstLen = EXAMPLE_DDR_BURST_LEN;
    userConfig.timing = &timing;
    userConfig.deviceConfig[0] = &config;
    userConfig.readCalibration[0] = &readCal;
    userConfig.writeCalibration[0] = &writeCal;
    userConfig.tuning = &tuning;
    userConfig.autoRefresh = &autoRefresh;
    userConfig.zqCalibration = &zqCal;
    /* MMDC Initialization. */
    if (MMDC_Init(EXAMPLE_MMDC, &userConfig) != kStatus_Success)
    {
        PRINTF("\r\n MMDC Init Failed. \r\n");
    }

Data Structures
struct	mmdc_readDQS_calibration_config_t
	MMDC read DQS gating calibration configuration collection. More...

struct	mmdc_writeLeveling_calibration_config_t
	MMDC write leveling calibration configuration collection. More...

struct	mmdc_read_calibration_config_t
	MMDC read calibration configuration collection. More...

struct	mmdc_fine_tuning_config_t
	MMDC write calibration configuration collection. More...

struct	mmdc_odt_config_t
	MMDC odt configuration collection. More...

struct	mmdc_power_config_t
	MMDC power configutation collection. More...

struct	mmdc_zq_config_t
	MMDC ZQ configuration collection. More...

struct	mmdc_cmd_config_t
	MMDC cmd configuration collection. More...

struct	mmdc_device_timing_t
	MMDC device device timing configuration collection. More...

struct	mmdc_auto_refresh_t
	MMDC auto refresh configuration collection. More...

struct	mmdc_exaccess_config_t
	MMDC exclusive access configuration collection. More...

struct	mmdc_profiling_config_t
	MMDC module profiling configuration collection. More...

struct	mmdc_performance_config_t
	MMDC performance configuration collection. More...

struct	mmdc_device_config_t
	MMDC module relate configuration collection. More...

struct	mmdc_config_t
	MMDC module relate configuration collection. More...

Typedefs
typedef void(*	MMDC_SwitchFrequency )(MMDC_Type , void , void *, uint32_t)
	MMDC switch frequency api prototype. More...

Enumerations
enum	_mmdc_status { kStatus_MMDC_ErrorDGCalibration = MAKE_STATUS(kStatusGroup_MMDC, 1), kStatus_MMDC_ErrorReadCalibration = MAKE_STATUS(kStatusGroup_MMDC, 2), kStatus_MMDC_ErrorWriteCalibration = MAKE_STATUS(kStatusGroup_MMDC, 3), kStatus_MMDC_ErrorWriteLevelingCalibration = MAKE_STATUS(kStatusGroup_MMDC, 4), kStatus_MMDC_WaitFlagTimeout = MAKE_STATUS(kStatusGroup_MMDC, 5) }
	MMDC status return codes. More...

enum	mmdc_device_type_t { kMMDC_LPDDR2_S4 = 0x0U, kMMDC_LPDDR2_S2 = 0x1U, kMMDC_DDR3 = 0x2U }
	LPDDR2 device list. More...

enum	mmdc_device_bank_num_t { kMMDC_Bank8 = 0U, kMMDC_Bank4 = 1U }
	LPDDR2 device bank number. More...

enum	mmdc_row_addr_width_t { kMMDC_Row11Bits = 0U, kMMDC_Row12Bits = 1U, kMMDC_Row13Bits = 2U, kMMDC_Row14Bits = 3U, kMMDC_Row15Bits = 4U, kMMDC_Row16Bits = 5U }
	define for row addr width More...

enum	mmdc_col_addr_width_t { kMMDC_Col9Bits = 0U, kMMDC_Col10Bits = 1U, kMMDC_Col11Bits = 2U, kMMDC_Col8Bits = 3U, kMMDC_Col12Bits = 4U }
	define for col addr width More...

enum	mmdc_burst_len_t { kMMDC_BurstLen4 = 0U, kMMDC_BurstLen8, kMMDC_BurstLen16 }
	define for burst length More...

enum	mmdc_cmd_type_t { kMMDC_NormalOperation = 0x0U, kMMDC_AutoRefresh = 0x2U, kMMDC_WriteModeRegister = 0x3U, kMMDC_ZQCalibration = 0x04U, kMMDC_PreChargeAll = 0x05U, kMMDC_ReadModeRegister = 0x6U }
	define for command type auto refresh cmd: select correct CMD_CS before issue this cmd write mode register cmd: DDR2/DDR3: CMD_CS,CMD_BA,CMD_ADDR_LSB,CMD_ADDR_MSB LPDDR2: CMD_CS,MR_OP,MR_ADDR ZQ calibration cmd: DDR2/DDR3: CMD_CS,{CMD_ADDR_MSB,CMD_ADDR_LSB}=0x400,or 0x0 LPDDR2: through MRW cmd PreChargeAll cmd: selecet correct CMD_CS MRR cmd: only for LPDDR2/LPDDR3 device,must set correct CMD_CS,MR_ADDR More...

enum	mmdc_zq_calmode_t { kMMDC_ZQCaltoIOHW = 0x4U, kMMDC_ZQCaltoIODeviceLong = 0x01U, kMMDC_ZQCaltoDeviceOnly = 0x02U, kMMDC_ZQCaltoIODeviceLongShort, kMMDC_ZQFinetuning = 0x0AU, kMMDC_DisZQFinetuning = 0x0BU }
	MMDC ZQ calibration type. More...

enum	mmdc_zq_calfreq_t { kMMDC_ZQCalFreq1ms = 0x0U, kMMDC_ZQCalFreq2ms = 0x1U, kMMDC_ZQCalFreq4ms = 0x2U, kMMDC_ZQCalFreq1s = 0x6U, kMMDC_ZQCalFreq16s = 0xEU, kMMDC_ZQCalFreq32s = 0xFU }
	MMDC ZQ calibration frequency. More...

enum	mmdc_refresh_sel_t { kMMDC_RefreshTrigBy64K = 0U, kMMDC_RefreshTrigBy32K, kMMDC_RefreshTrigDDRCycles, kMMDC_RefreshTrigNone }
	define MMDC refresh selector-select source of the clock that will trigger each refresh cycle. More...

enum	mmdc_profiling_action_t { kMMDC_EnProfilingWithID, kMMDC_FreezeProfiling, kMMDC_CheckOverFlow }
	define MMDC profiling action define . More...

enum	mmdc_calibration_type_t { kMMDC_CalWithPreSetValue, kMMDC_CalWithMPR, kMMDC_CalWithPreDefine }
	MMDC calibration type define . More...

enum	mmdc_calibaration_waitcycles_t { kMMDC_Wait16DDRCycles = 0U, kMMDC_Wait32DDRCycles = 0x01U }
	define MMDC wait cycles before comparing data during calibration. More...

enum	mmdc_fine_tuning_dutycycle_t { kMMDC_DutyHighPercent48_5 = 0x1U, kMMDC_DutyHighPercent50 = 0x2U, kMMDC_DutyHighPercent51_5 = 0x4U }
	define MMDC parameter fine tuning duty cyle. More...

enum	mmdc_termination_config_t { kMMDC_RttNomDisabled = 0x0U, kMMDC_RttNom120ohm = 0x1U, kMMDC_RttNom60ohm = 0x2U, kMMDC_RttNom40ohm = 0x3U, kMMDC_RttNom30ohm = 0x4U, kMMDC_RttNom24ohm = 0x5U, kMMDC_RttNom20ohm = 0x6U, kMMDC_RttNom17ohm = 0x7U }
	define MMDC on chip termination configurations. More...

enum	_mmdc_lpddr2_derate { kMMDC_NoUpdateDerate = 0U, kMMDC_UpdateRefreshRate = 0x01U, kMMDC_DerateTiming = 0x02U, kMMDC_DisableDerate = 0x04U }
	define LPDDR2 device derating type. More...

enum	_mmdc_exaccess_type { kMMDC_ExMonitorID0 = 0x01U, kMMDC_ExMonitorID1 = 0x02U, kMMDC_ExMonitorID2 = 0x04U, kMMDC_ExMonitorID3 = 0x08U, kMMDC_ExAccessResponse = 0x10U }
	MMDC exclusive acess config type. More...

Driver version
#define	FSL_MMDC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U))
	MMDC driver Version 2.1.2.

#define	MMDC_TIMEOUT (500U)
	MMDC retry times.

#define	MMDC_READ_DQS_FINE_TUNING_MASK (0x77777777U)
	< More...

#define	MMDC_WRITE_DQS_FINE_TUNING_MASK (0xF3333333U)
	< More...

#define	MMDC_PRE_DEFINE_VALUE_DEFAULT (0xCCU)
	< More...

#define	MMDC_MEASUREUNIT_ERR_FREQ (100000000U)
	< More...

Initialization and deinitialization
void	MMDC_GetDefaultConfig (mmdc_config_t *config)
	MMDC module get the default configutation get timing/power/zq configuration. More...

status_t	MMDC_Init (MMDC_Type base, mmdc_config_t config)
	MMDC module initialization function. More...

void	MMDC_Deinit (MMDC_Type *base)
	MMDC module deinit function. More...

device operation
void	MMDC_HandleCommand (MMDC_Type base, mmdc_cmd_config_t config)
	MMDC module process the command,support transfer multi cmd in once function call. More...

status_t	MMDC_GetReadData (MMDC_Type base, uint32_t data)
	MMDC get the read data. More...

void	MMDC_EnhancePerformance (MMDC_Type base, const mmdc_performance_config_t config)
	MMDC module enhance performance function. More...

void	MMDC_EnableAutoRefresh (MMDC_Type base, mmdc_auto_refresh_t config)
	Enable MMDC module periodic refresh scheme config. More...

static void	MMDC_DisableAutoRefresh (MMDC_Type *base)
	Disable MMDC module periodic refresh scheme. More...

void	MMDC_EnablePowerSaving (MMDC_Type base, mmdc_power_config_t config)
	MMDC enable automatic power saving. More...

static void	MMDC_DisablePowerSaving (MMDC_Type *base)
	uint8_t targetCS, More...

void	MMDC_Profiling (MMDC_Type base, mmdc_profiling_config_t config)
	MMDC profiling mechanism. More...

status_t	MMDC_LPDDR2UpdateDerate (MMDC_Type base, mmdc_auto_refresh_t config, uint32_t type)
	MMDC update device refresh rate and derate timing for LPDDR2 device only. More...

status_t	MMDC_MonitorLPDDR2OperationTemp (MMDC_Type base, uint32_t mr4)
	MMDC device operation temp monitor function. More...

status_t	MMDC_ReadDQSGatingCalibration (MMDC_Type base, mmdc_readDQS_calibration_config_t config)
	MMDC module read DQS gating calibration function. More...

status_t	MMDC_WriteLevelingCalibration (MMDC_Type base, mmdc_writeLeveling_calibration_config_t config)
	MMDC module write leveling calibration function. More...

status_t	MMDC_WriteCalibration (MMDC_Type base, mmdc_write_calibration_config_t config)
	MMDC module write calibration function. More...

status_t	MMDC_ReadCalibration (MMDC_Type base, mmdc_read_calibration_config_t config)
	MMDC module read calibration function. More...

void	MMDC_DoFineTuning (MMDC_Type base, mmdc_device_type_t devType, mmdc_fine_tuning_config_t config)
	MMDC module read calibration function. More...

void	MMDC_SetTiming (MMDC_Type base, mmdc_device_type_t devType, mmdc_device_timing_t timing)
	set timing parameter More...

void	MMDC_DeviceInit (MMDC_Type base, mmdc_device_type_t devType, uint8_t targetCS, mmdc_device_config_t devConfig)
	Initialize MMDC controlled device. More...

status_t	MMDC_EnterConfigurationMode (MMDC_Type *base, bool enable)
	MMDC module enter/exit configuration mode function. More...

void	MMDC_DoZQCalibration (MMDC_Type base, mmdc_device_type_t devType, mmdc_zq_config_t zqCal)
	MMDC do ZQ calibration function. More...

status_t	MMDC_EnableLowPowerMode (MMDC_Type *base, bool enable)
	MMDC enable/disable low power mode Once enable device will enter self-refresh mode. More...

status_t	MMDC_EnableDVFSMode (MMDC_Type *base, bool enable)
	MMDC enable/disable dynamic frequency change mode Once enable device will enter self-refresh mode. More...

void	MMDC_Reset (MMDC_Type *base)
	MMDC module reset function when you call this function will reset all internal register user need bo module init function bue do not need to do device init. More...

static void	MMDC_SwitchDeviceFrequency (MMDC_Type base, void ccm, void *iomux, uint32_t param, uint32_t codeAddr)
	define the mmdc switch frequency. More...

debug
static void	MMDC_EnableSBS (MMDC_Type *base, bool enable)
	MMDC enable/disable the SBS-step by step debug feature. More...

static void	MMDC_TriggerSBS (MMDC_Type *base)
	MMDC trigger the MMDC dispatch the one pending request to device. More...

static uint32_t	MMDC_GetAXIAddrBySBS (MMDC_Type *base)
	MMDC get AXI ddr which was dispatched by MMDC in SBS mode. More...

static uint32_t	MMDC_GetAXIAttributeBySBS (MMDC_Type *base)
	MMDC get AXI attribute which was dispatched by MMDC in SBS mode. More...

static void	MMDC_EnableProfiling (MMDC_Type *base, bool enable)
	MMDC enable/disable profiling feature. More...

static void	MMDC_ResumeProfiling (MMDC_Type *base)
	MMDC resume profiling. More...

static void	MMDC_ResetProfiling (MMDC_Type *base)
	MMDC reset profiling. More...

void	MMDC_ExclusiveAccess (MMDC_Type base, mmdc_exaccess_config_t config, uint32_t type)
	MMDC exclusive access config function,config the monitor ID and response. More...

Data Structure Documentation

struct mmdc_readDQS_calibration_config_t

Data Fields
mmdc_calibration_type_t	mode
	select calibration mode. More...

mmdc_calibaration_waitcycles_t	waitCycles
	MMDC wait cycles before comparing sample data. More...

uint8_t	dqsGatingHalfDelay0
	Read DQS gating half cycles delay count for Byte0. More...

uint8_t	dqsGatingAbsDelay0
	Absolute read DQS gating delay offset for Byte0, So the total read DQS gating delay is (dqsGatingHalfDelay0)0.5cycle + (dqsGatingAbsDelay0)1/256cycle. More...

uint8_t	dqsGatingHalfDelay1
	Read DQS gating half cycles delay count for Byte1. More...

uint8_t	dqsGatingAbsDelay1
	Absolute read DQS gating delay offset for Byte1, So the total read DQS gating delay is (dqsGatingHalfDelay1)0.5cycle + (dqsGatingAbsDelay1)1/256cycle. More...

uint8_t	readDelay0
	When using hardware calibration(MPR/Predefined mode), user should input RD_DL_ABS_OFFSET to place read DQS inside the read DQ window. More...

uint8_t	readDelay1
	When using hardware calibration(MPR/Predefined mode), user should input RD_DL_ABS_OFFSET to place read DQS inside the read DQ window. More...

Field Documentation

mmdc_calibration_type_t mmdc_readDQS_calibration_config_t::mode

mmdc_calibaration_waitcycles_t mmdc_readDQS_calibration_config_t::waitCycles

uint8_t mmdc_readDQS_calibration_config_t::dqsGatingHalfDelay0

uint8_t mmdc_readDQS_calibration_config_t::dqsGatingAbsDelay0

uint8_t mmdc_readDQS_calibration_config_t::dqsGatingHalfDelay1

uint8_t mmdc_readDQS_calibration_config_t::dqsGatingAbsDelay1

uint8_t mmdc_readDQS_calibration_config_t::readDelay0

uint8_t mmdc_readDQS_calibration_config_t::readDelay1

struct mmdc_writeLeveling_calibration_config_t

Data Fields
mmdc_calibration_type_t	mode
	select calibration mode. More...

uint8_t	wLevelingOneDelay0
	Write leveling one cycles delay count for Byte0.

uint8_t	wLevelingHalfDelay0
	Write leveling half cycles delay count for Byte0.

uint8_t	wLevelingAbsDelay0
	Absolute Write leveling delay offset for Byte0, So the total delay is the sum of (wLevelingAbsDelay0/256cycle) + (wLevelingHalfDelay0halfcycle) + (wLevelingOneDelay0*cycle). More...

uint8_t	wLevelingOneDelay1
	Write leveling one cycles delay count for Byte1.

uint8_t	wLevelingHalfDelay1
	Write leveling half cycles delay count for Byte1.

uint8_t	wLevelingAbsDelay1
	Absolute Write leveling delay offset for Byte1, So the total delay is the sum of (wLevelingAbsDelay1/256cycle) + (wLevelingHalfDelay1halfcycle) + (wLevelingOneDelay1*cycle). More...

Field Documentation

mmdc_calibration_type_t mmdc_writeLeveling_calibration_config_t::mode

uint8_t mmdc_writeLeveling_calibration_config_t::wLevelingAbsDelay0

uint8_t mmdc_writeLeveling_calibration_config_t::wLevelingAbsDelay1

struct mmdc_read_calibration_config_t

Data Fields
mmdc_calibration_type_t	mode
	select calibration mode. More...

uint8_t	readDelay0
	delay between read DQS strobe and read data of Byte0, RD_DL_ABS_OFFSET0. More...

uint8_t	readDelay1
	delay between read DQS strobe and read data of Byte1, RD_DL_ABS_OFFSET1. More...

Field Documentation

mmdc_calibration_type_t mmdc_read_calibration_config_t::mode

uint8_t mmdc_read_calibration_config_t::readDelay0

The delay of the delay-line would be (RD_DL_ABS_OFFSET0 / 256) * MMDC AXIclock (fast clock). when using hardware calibration(MPR/Predefined mode), user should input RD_DL_ABS_OFFSET0 to place read DQS inside the read DQ window.

uint8_t mmdc_read_calibration_config_t::readDelay1

The delay of the delay-line would be (RD_DL_ABS_OFFSET1 / 256) * MMDC AXIclock (fast clock). when using hardware calibration(MPR/Predefined mode), user should input RD_DL_ABS_OFFSET1 to place read DQS inside the read DQ window.

struct mmdc_fine_tuning_config_t

Data Fields
uint32_t	rDQOffset0
	fine-tuning adjustment to every bit in the read DQ byte0 relative to the read DQS, max dealy units can be add is 7

uint32_t	rDQOffset1
	fine-tuning adjustment to every bit in the read DQ byte1 relative to the read DQS, max dealy units can be add is 7

uint32_t	wDQOffset0
	fine-tuning adjustment to every bit in the write DQ byte0 relative to the write DQS, max dealy units can be add is 7

uint32_t	wDQOffset1
	fine-tuning adjustment to every bit in the write DQ byte1 relative to the write DQS, max dealy units can be add is 7

uint32_t	caDelay
	CA delay line fine tuning parameter. More...

mmdc_fine_tuning_dutycycle_t	rDQDuty0
	Read DQS duty cycle fine tuning control of Byte1.

mmdc_fine_tuning_dutycycle_t	rDQDuty1
	Read DQS duty cycle fine tuning control of Byte0.

mmdc_fine_tuning_dutycycle_t	ddrCKDutyCtl0
	Primary duty cycle fine tuning control of DDR clock.

mmdc_fine_tuning_dutycycle_t	ddrCKDutyCtl1
	Secondary duty cycle fine tuning control of DDR clock.

mmdc_fine_tuning_dutycycle_t	wDQDuty0
	Write DQS duty cycle fine tuning control of Byte0.

mmdc_fine_tuning_dutycycle_t	wDQDuty1
	Write DQS duty cycle fine tuning control of Byte1.

Field Documentation

uint32_t mmdc_fine_tuning_config_t::caDelay

struct mmdc_odt_config_t

Data Fields
mmdc_termination_config_t	odtByte0Config
	On chip ODT byte1 resistor. More...

bool	enableActiveReadOdt
	On chip ODT byte0 resistor. More...

bool	enableInactiveReadOdt
	Active read CS ODT enable. More...

bool	enableActiveWriteOdt
	Inactive read CS ODT enable. More...

bool	enableInactiveWriteOdt
	Active write CS ODT enable. More...

Field Documentation

mmdc_termination_config_t mmdc_odt_config_t::odtByte0Config

bool mmdc_odt_config_t::enableActiveReadOdt

bool mmdc_odt_config_t::enableInactiveReadOdt

bool mmdc_odt_config_t::enableActiveWriteOdt

bool mmdc_odt_config_t::enableInactiveWriteOdt

struct mmdc_power_config_t

Data Fields
bool	wIdle
	get write request buffer Idle status

bool	rIdle
	get read request buffer Idle status

bool	isInAutoPS
	indicate mmdc if in a automatic power saving mode

uint8_t	idleClockToPS
	define the idle clock which device will automatically enter auto self-refresh mode ,default is 1024 clock cycles, max is 16320 cycles,calucate formula is idleClockToPS * 64 = idle clock note: idleClockToPS = 0 is forbidden

uint8_t	idleClockToPrecharge0
	define the idle clock which device will automatically precharged. More...

uint8_t	idleClockToPD0
	define the idle clock which device will enter power down, default is disable ,max clock is 32768 clocks, calucate formula idleClockToPD *16 = idle clock

uint8_t	idleClockToPrecharge1
	define the idle clock which device will automatically precharged. More...

uint8_t	idleClockToPD1
	define the idle clock which device will enter power down, default is disable ,max clock is 32768 clocks, calucate formula idleClockToPD *16 = idle clock

Field Documentation

uint8_t mmdc_power_config_t::idleClockToPrecharge0

default is disable ,max clock is 128 clocks, calucate formula 2^idleClockToPrecharge = idle clock

uint8_t mmdc_power_config_t::idleClockToPrecharge1

default is disable ,max clock is 128 clocks, calucate formula 2^idleClockToPrecharge = idle clock

struct mmdc_zq_config_t

Data Fields
mmdc_zq_calmode_t	mode
	zq calibration mode. More...

uint8_t	earlyCompTimer
	this field define the interval between the warming up of the comp of the ultra cal pad and the begining of the ZQ cal process with pads

uint16_t	tZQCl_Clocks
	This is the period of time that the MMDC has to wait after sending a short ZQ calibration and before sending other commands,max value 112 cycles,see RM for more detail ,lpddr2 device default is 360ns.

uint16_t	tZQCs_Clocks
	This is the period of time that the MMDC has to wait after sending a long ZQ calibration and before sending other commands.

uint16_t	tZQInit_Clocks
	This is the period of time that the MMDC has to wait after sending a init ZQ calibration and before sending other commands.lpddr2 device default is 1us.

mmdc_zq_calfreq_t	hwZQFreq
	ZQ periodic calibration freq.

uint8_t	cmpOutSample
	define the amount of cycle between driving the ZQ signal to pad and till sampling the cmp enable output

uint8_t	hwPullDownOffset
	define ZQ hardware pull down offset, used for fine tuning

uint8_t	hwPullUpOffset
	define ZQ hardware pull up offset, used for fine tuning

Field Documentation

mmdc_zq_calmode_t mmdc_zq_config_t::mode

struct mmdc_cmd_config_t

Data Fields
uint8_t	argMsb
	define the CMD_ADDR_MSB_MR_OP, for lpddr2 device this field is mode register oprand

uint8_t	argLsb
	define the CMD_ADDR_LSB_MR_ADDR,for lpddr2 device this field is mode register addr

uint8_t	bankAddr
	define the bank address,this field not relate with lpddr2 device

uint8_t	targetCS
	select which CS to drive low. More...

mmdc_cmd_type_t	cmd
	define the cmd to be send

Field Documentation

uint8_t mmdc_cmd_config_t::targetCS

struct mmdc_device_timing_t

clocks is ddr clock,(a+b), a is the value write to reigster,b is offset

Data Fields
uint8_t	tRFC_Clocks
	Refresh cmd to active or refresh cmd time default is (0x32+1) clocks,max is (255+1) clocks

uint8_t	tCKSRX_Clocks
	Valid clock before self-refresh exit,self-refresh timing default is 2 clocks,max is 7 clocks

uint8_t	tCKSRE_Clocks
	Valid clock after self-refresh entry,self-refresh timing default is 2 clocks.max is 7 clocks

uint8_t	tXSR_Clocks
	exit self refresh to a valid cmd,self-refresh timing min value should set to 0x16,represent 23 clocks,max is 256 clocks

uint8_t	tCKE_Clocks
	CKE minimum pulse width,default is (3+1) clocks,max is (7+1) clocks.

uint8_t	tCL_Clocks
	CAS read latency,default is(3+3) clocks, max is (8+3) clocks.

uint8_t	tCWL_Clocks
	CAS write latency, default is (3+1)clocks, max is (6+1) clocks.

uint8_t	ralat_Clocks
	define write additional latency in misc, default is disable, max is (7+2)clocks

uint8_t	walat_Clocks
	define read additional latency in misc, default is disable, max is 3 clocks

uint8_t	tFAW_Clocks
	Four bank active window,all bank,default is (6+1) clocks,max is (31+1)clocks.

uint8_t	tRAS_Clocks
	row active time,Active to Precharge cmd period,same bank,default is (9+1) clocks ,max is (30+1)clocks

uint8_t	tRC_Clocks
	Active to active or refresh cmd period,default is (0+1)clocks,max is (62+1)clocks.

uint8_t	tRCD_Clocks
	Active cmd to internal read/write delay time,default is 0+1 clocks,max is 14+1 clocks.

uint8_t	tRP_Clocks
	Precharge cmd period-per bank,default is 0+1 clock,max is 14+1 clocks.

uint8_t	tRPA_Clocks
	Precharge cmd period-all bank,default is 0+1 clock,max is 14+1 clocks.

uint8_t	tWR_Clocks
	Write recovery time,default is 0+1 clock,max is 7+1 clocks.

uint8_t	tMRD_Clocks
	Mode register set cmd cycle,should set to max(tMRR,tMRW), default is 1+1 clock,max is 15+1 clocks.

uint8_t	tRTP_Clocks
	Internal read cmd to pre-charge cmd delay,default is 2+1 clock,max is 7+1 clocks.

uint8_t	tWTR_Clocks
	Internal write cmd to read cmd delay,default is 2+1 clock,max is 7+1 clocks.

uint8_t	tRRD_Clocks
	active bankA to active bankB ,Internal read cmd to pre-charge cmd, default is 0+1 clock,max is 6+1 clocks

uint8_t	tXP_Clocks
	exit power down to any cmd, default (1+1) clocks, max is (7 +1) clocks

uint8_t	tRSTtoCKE_Clocks
	idle time until first reset is assert,default is 14-2 clock,max is 0X3f-2 clocks,for LPDDR2 device default is 200us

uint32_t	tDAI_Clocks
	Maximum device auto initialization period for LPDDR2, not relavant to DDR3. More...

uint8_t	tRTWSAME_Clocks
	Read to write commands delay for same chip select, total delay is calculated according to: BL/2 + RTW_SAME + (tCL-tCWL) + RALAT

uint8_t	tWTRDIFF_Clocks
	Write to read commands delay for different chip select, total delay is calculated according to: BL/2 + WTR_DIFF + (tCL-tCWL) + RALAT

uint8_t	tWTWDIFF_Clocks
	Write to write commands delay for different chip select, total delay is calculated according to: BL/2 + WTW_DIFF

uint8_t	tRTWDIFF_Clocks
	Read to write commands delay for different chip select, total delay is calculated according to: BL/2 + RTW_DIFF + (tCL - tCWL) + RALAT

uint8_t	tRTRDIFF_Clocks
	Read to read commands delay for different chip select. More...

uint8_t	tXPDLL_Clocks
	Exit precharge power down with DLL frozen to commands requiring DLL, not relavant to LPDDR2. More...

uint16_t	tDLLK_Clocks
	DLL locking time, not relavant to LPDDR2. More...

uint8_t	tXPR_Clocks
	CLKE High to a valid command, not relevant to LPDDR2. More...

uint8_t	tSDEtoRST_Clocks
	Time from SDE enable until DDR #reset is high, not relavant to LPDDR2. More...

uint8_t	tAOFPD_Clocks
	Asynchronous RTT turn-off delay, not relavant to LPDDR2. More...

uint8_t	tAONPD_Clocks
	Asynchronous RTT turn-on delay, not relavant to LPDDR2. More...

uint8_t	tODTIdleOff_Clocks
	ODT turn off latency, not relavant to LPDDR2. More...

Field Documentation

uint32_t mmdc_device_timing_t::tDAI_Clocks

uint8_t mmdc_device_timing_t::tRTRDIFF_Clocks

total delay is calculated according to: BL/2 + RTR_DIFF

uint8_t mmdc_device_timing_t::tXPDLL_Clocks

uint16_t mmdc_device_timing_t::tDLLK_Clocks

uint8_t mmdc_device_timing_t::tXPR_Clocks

uint8_t mmdc_device_timing_t::tSDEtoRST_Clocks

uint8_t mmdc_device_timing_t::tAOFPD_Clocks

uint8_t mmdc_device_timing_t::tAONPD_Clocks

uint8_t mmdc_device_timing_t::tODTIdleOff_Clocks

struct mmdc_auto_refresh_t

Data Fields
uint16_t	refreshCnt
	define refresh counter which is how many DDR clock cycles arrive will trigger auto refresh, only applied when choose refreshTrigSrc as kMMDC_RefreshTrigDDRCycles

uint16_t	refreshRate
	refresh rate-means how much cmd will send once auto refresh being trigger

mmdc_refresh_sel_t	refreshTrigSrc
	select refresh trigger clock source

struct mmdc_exaccess_config_t

Data Fields
uint16_t	excMonitorID0
	exclusive monitor ID 0

uint16_t	excMonitorID1
	exclusive monitor ID 1

uint16_t	excMonitorID2
	exclusive monitor ID 2

uint16_t	excMonitorID3
	exclusive monitor ID 3

bool	secErrLock
	define if lock ARCR_SEC_ERR_EN this bit can't update if locked

bool	secErrEn
	This bit defines whether security read/write access violation result in SLV Error response or in OKAY response.

bool	excErrEn
	This bit defines whether exclusive read/write access violation of AXI 6.2.4 rule result in SLV Error response or in OKAY response . More...

Field Documentation

bool mmdc_exaccess_config_t::excErrEn

Default value is 0x1 response is SLV Error

struct mmdc_profiling_config_t

Data Fields
mmdc_profiling_action_t	type
	profiling action

bool	overFlowCount
	profiling cycle counter over flag

uint16_t	axiIDMask
	profiling AXI ID mask

uint16_t	axiID
	profiling AXI ID

uint32_t	totalCount
	total cycle count-readonly

uint32_t	busyCount
	busy count-readonly

uint32_t	readCount
	total read count-readonly

uint32_t	writeCount
	total write count-readonly

uint32_t	readByteCount
	read byte count-readonly

uint32_t	writeByteCount
	total write byte count-readonly

struct mmdc_performance_config_t

Data Fields
bool	enArbitration
	define if enable arbitration in MAARCR

bool	enReordering
	define if enable reordering in MAARCR

bool	enRCH
	define if enable real time channel in MAARCR

uint32_t	ratePageHit
	static score taken into account in case the pending access has a page hit in MAARCR

uint32_t	rateAccessHit
	static score taken into account in case the pending access is same as before in MAARCR

uint32_t	dynJump
	dynamic score give to any pending access in case it was not chosen in arbitration in MAARCR

uint32_t	dynMax
	dynamic score max value in MAARCR

uint32_t	guard
	use to prevent a starvation of access

uint32_t	cmdPredict
	define cmd prediction work mode in misc

struct mmdc_device_config_t

struct mmdc_config_t

Data Fields
mmdc_device_type_t	devType
	define device type

uint32_t	devSize
	define the size of the device

mmdc_device_bank_num_t	devBank
	define device total bank number

mmdc_row_addr_width_t	rowWidth
	define row width in MDCTL

mmdc_col_addr_width_t	colWidth
	define col width in MDCTL

mmdc_burst_len_t	burstLen
	define burst length MDCTL

bool	bankInterleave
	define indicate bank interleave on/off in misc

bool	secondDDRClock
	define gating the secondary DDR clock in misc

bool	enableOnlyCS0
	Only enable CS0.

mmdc_odt_config_t *	ODTConfig
	Pointer to on die termination config, NULL means disable, for LPDDR2, pass NULL. More...

mmdc_zq_config_t *	zqCalibration
	Pointer to device timing structure. More...

mmdc_device_config_t *	deviceConfig [2]
	Pointer to ZQ calibration config, NULL means do not need. More...

mmdc_readDQS_calibration_config_t *	readDQSCalibration [2]
	Pointer to device configuration CS0/CS1, NULL means do not need. More...

mmdc_writeLeveling_calibration_config_t *	wLevelingCalibration [2]
	Pointer to read DQS calibration config CS0/CS1, NULL meansdo not need, for LPDDR2, pass NULL. More...

mmdc_read_calibration_config_t *	readCalibration [2]
	Pointer to write leveling calibration config, NULL means do not need, for LPDDR2, pass NULL. More...

mmdc_write_calibration_config_t *	writeCalibration [2]
	Pointer to read calibration config CS0/CS1, NULL means do not need. More...

mmdc_fine_tuning_config_t *	tuning
	Pointer to write calibration config CS0/CS1, NULL means do not need. More...

mmdc_auto_refresh_t *	autoRefresh
	Pointer to fine tuning config, NULL means do not need. More...

mmdc_power_config_t *	powerConfig
	Pointer to auto refresh config structure, NULL means do not need. More...

Field Documentation

mmdc_odt_config_t* mmdc_config_t::ODTConfig

mmdc_zq_config_t* mmdc_config_t::zqCalibration

mmdc_device_config_t* mmdc_config_t::deviceConfig[2]

mmdc_readDQS_calibration_config_t* mmdc_config_t::readDQSCalibration[2]

mmdc_writeLeveling_calibration_config_t* mmdc_config_t::wLevelingCalibration[2]

mmdc_read_calibration_config_t* mmdc_config_t::readCalibration[2]

mmdc_write_calibration_config_t* mmdc_config_t::writeCalibration[2]

mmdc_fine_tuning_config_t* mmdc_config_t::tuning

mmdc_auto_refresh_t* mmdc_config_t::autoRefresh

mmdc_power_config_t* mmdc_config_t::powerConfig

Macro Definition Documentation

#define MMDC_READ_DQS_FINE_TUNING_MASK (0x77777777U)

define the read DQS fine tuning mask value

#define MMDC_WRITE_DQS_FINE_TUNING_MASK (0xF3333333U)

define the write DQS fine tuning mask value

#define MMDC_PRE_DEFINE_VALUE_DEFAULT (0xCCU)

define the calibration predefine value

#define MMDC_MEASUREUNIT_ERR_FREQ (100000000U)

according to ERR005778 description

Typedef Documentation

typedef void(* MMDC_SwitchFrequency)(MMDC_Type *, void *, void *, uint32_t)

Enumeration Type Documentation

enum _mmdc_status

Enumerator
kStatus_MMDC_ErrorDGCalibration	MMDC error DG calibration.
kStatus_MMDC_ErrorReadCalibration	MMDC error read calibration.
kStatus_MMDC_ErrorWriteCalibration	MMDC error write calibration.
kStatus_MMDC_ErrorWriteLevelingCalibration	MMDC error write leveling calibration.
kStatus_MMDC_WaitFlagTimeout	MMDC wait flag timeout.

enum mmdc_device_type_t

Enumerator
kMMDC_LPDDR2_S4	LPDDR2-S4.
kMMDC_LPDDR2_S2	LPDDR2-S2.
kMMDC_DDR3	DDR3 device.

enum mmdc_device_bank_num_t

Enumerator
kMMDC_Bank8	bank number 8
kMMDC_Bank4	bank number 4

enum mmdc_row_addr_width_t

Enumerator
kMMDC_Row11Bits	row addr 11 bits
kMMDC_Row12Bits	row addr 12 bits
kMMDC_Row13Bits	row addr 13 bits
kMMDC_Row14Bits	row addr 14 bits
kMMDC_Row15Bits	row addr 15 bits
kMMDC_Row16Bits	row addr 16 bits

enum mmdc_col_addr_width_t

Enumerator
kMMDC_Col9Bits	col addr 9 bits
kMMDC_Col10Bits	col addr 10 bits
kMMDC_Col11Bits	col addr 11 bits
kMMDC_Col8Bits	col addr 8 bits
kMMDC_Col12Bits	col addr 12 bits

enum mmdc_burst_len_t

Enumerator
kMMDC_BurstLen4	brust len 4
kMMDC_BurstLen8	burst len 8
kMMDC_BurstLen16	reserved

enum mmdc_cmd_type_t

Enumerator
kMMDC_NormalOperation	normal operation cmd
kMMDC_AutoRefresh	auto refresh cmd
kMMDC_WriteModeRegister	load mode register for DDR2/DDR3,MRW for LPDDR2
kMMDC_ZQCalibration	ZQ calibration cmd.
kMMDC_PreChargeAll	Precharge all cmd.
kMMDC_ReadModeRegister	mode register read cmd

enum mmdc_zq_calmode_t

Enumerator
kMMDC_ZQCaltoIOHW	ZQ calibration to IO pads only through HW.
kMMDC_ZQCaltoIODeviceLong	ZQ calibration to IO pads together with ZQ long cmd to device.
kMMDC_ZQCaltoDeviceOnly	ZQ calibration to device with long/short cmd.
kMMDC_ZQCaltoIODeviceLongShort	ZQ calibration to IO pads together with ZQ calibration cmd long/short to device.
kMMDC_ZQFinetuning	HW ZQ res offset fine tuning.
kMMDC_DisZQFinetuning	disable HW ZQ res offset

enum mmdc_zq_calfreq_t

Enumerator
kMMDC_ZQCalFreq1ms	ZQ calibration is peformed every 1ms.
kMMDC_ZQCalFreq2ms	ZQ calibration is peformed every 2ms.
kMMDC_ZQCalFreq4ms	ZQ calibration is peformed every 4ms.
kMMDC_ZQCalFreq1s	ZQ calibration is peformed every 1s.
kMMDC_ZQCalFreq16s	ZQ calibration is peformed every 16s.
kMMDC_ZQCalFreq32s	ZQ calibration is peformed every 32s.

enum mmdc_refresh_sel_t

Enumerator
kMMDC_RefreshTrigBy64K	refresh trigger frequency 64K
kMMDC_RefreshTrigBy32K	refresh trigger frequency 32K
kMMDC_RefreshTrigDDRCycles	refresh trigger every amount of cycles that are configured in REF_CNT field
kMMDC_RefreshTrigNone	auto refresh disable

enum mmdc_profiling_action_t

Enumerator
kMMDC_EnProfilingWithID	enable profiling with special ID
kMMDC_FreezeProfiling	freeze profiling
kMMDC_CheckOverFlow	check the counter overflow

enum mmdc_calibration_type_t

Enumerator
kMMDC_CalWithPreSetValue	calibration with preset value
kMMDC_CalWithMPR	HW calibration with the MPR.
kMMDC_CalWithPreDefine	calibration with Pre-defined value

enum mmdc_calibaration_waitcycles_t

Enumerator
kMMDC_Wait16DDRCycles	wait 16 DDR cycles before comparing sample data
kMMDC_Wait32DDRCycles	wait 32 DDR cycles before comparing sample data

enum mmdc_fine_tuning_dutycycle_t

Enumerator
kMMDC_DutyHighPercent48_5	51.5% low 48.5% high
kMMDC_DutyHighPercent50	50% duty cycle
kMMDC_DutyHighPercent51_5	48.5% low 51.5% high

enum mmdc_termination_config_t

Enumerator
kMMDC_RttNomDisabled	Rtt_Nom Disabled.
kMMDC_RttNom120ohm	Rtt_Nom 120 Ohm.
kMMDC_RttNom60ohm	Rtt_Nom 60 Ohm.
kMMDC_RttNom40ohm	Rtt_Nom 40 Ohm.
kMMDC_RttNom30ohm	Rtt_Nom 30 Ohm.
kMMDC_RttNom24ohm	Rtt_Nom 24 Ohm.
kMMDC_RttNom20ohm	Rtt_Nom 20 Ohm.
kMMDC_RttNom17ohm	Rtt_Nom 17 Ohm.

enum _mmdc_lpddr2_derate

Enumerator
kMMDC_NoUpdateDerate	no derate
kMMDC_UpdateRefreshRate	refresh rate derate
kMMDC_DerateTiming	derating relate timing
kMMDC_DisableDerate	derating disable

enum _mmdc_exaccess_type

Enumerator
kMMDC_ExMonitorID0	config the exclusive access ID0
kMMDC_ExMonitorID1	config the exclusive access ID1
kMMDC_ExMonitorID2	config the exclusive access ID2
kMMDC_ExMonitorID3	config the exclusive access ID3
kMMDC_ExAccessResponse	config the exclusive access reponse

Function Documentation

void MMDC_GetDefaultConfig ( mmdc_config_t * config )

Parameters

base MMDC peripheral base address

mmdc config collection pointer config->bankInterleave = true; config->secondDDRClock = true; config->enableOnlyCS0 = true; config->devType = kMMDC_DDR3; config->devSize = 0x40000000U; config->devBank = kMMDC_Bank8; config->rowWidth = kMMDC_Row16Bits; config->colWidth = kMMDC_Col10Bits; config->burstLen = kMMDC_BurstLen8; config->ODTConfig = NULL; config->timing = NULL; config->zqCalibration = NULL; config->deviceConfig[0] = NULL; config->deviceConfig[1] = NULL; config->readDQSCalibration[0] = NULL; config->readDQSCalibration[1] = NULL; config->wLevelingCalibration[0] = NULL; config->wLevelingCalibration[1] = NULL; config->readCalibration[0] = NULL; config->readCalibration[1] = NULL; config->writeCalibration[0] = NULL; config->writeCalibration[1] = NULL; config->tuning = NULL; config->autoRefresh = NULL; config->powerConfig = NULL;

status_t MMDC_Init	(	MMDC_Type *	base,
		mmdc_config_t *	config
	)

Parameters

base	MMDC peripheral base address
mmdc	config collection pointer

Return values

kStatus_Success	Initialization succeed
kStatus_MMDC_ErrorDGCalibration	Error happened during hardware DQS gate calibration
kStatus_MMDC_ErrorReadCalibration	Error happened during hardware read calibration
kStatus_MMDC_ErrorWriteCalibration	Error happened during hardware write calibration
kStatus_MMDC_ErrorWriteLevelingCalibration	Error happened during hardware write leveling calibration

void MMDC_Deinit ( MMDC_Type * base )

Parameters

base	MMDC peripheral base address

void MMDC_HandleCommand	(	MMDC_Type *	base,
		mmdc_cmd_config_t *	config
	)

Parameters

base	MMDC peripheral base address
cmd	configuration collection

status_t MMDC_GetReadData	(	MMDC_Type *	base,
		uint32_t *	data
	)

Parameters

base	MMDC peripheral base address
the	pointer which used to store read data

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	Read data flag wait timeout

void MMDC_EnhancePerformance	(	MMDC_Type *	base,
		const mmdc_performance_config_t *	config
	)

Parameters

base	MMDC peripheral base address
performance	configuration collection

void MMDC_EnableAutoRefresh	(	MMDC_Type *	base,
		mmdc_auto_refresh_t *	config
	)

Parameters

base	MMDC peripheral base address
mmdc	auto refresh configuration collection

static void MMDC_DisableAutoRefresh ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

void MMDC_EnablePowerSaving	(	MMDC_Type *	base,
		mmdc_power_config_t *	config
	)

Parameters

base	MMDC peripheral base address
mmdc	device configuration collection, pointer for the configuration.

static void MMDC_DisablePowerSaving ( MMDC_Type * base )

inlinestatic

MMDC disable automatic power saving.

Parameters

base	MMDC peripheral base address

void MMDC_Profiling	(	MMDC_Type *	base,
		mmdc_profiling_config_t *	config
	)

Parameters

base	MMDC peripheral base address
mmdc	profiling status and control

status_t MMDC_LPDDR2UpdateDerate	(	MMDC_Type *	base,
		mmdc_auto_refresh_t *	config,
		uint32_t	type
	)

Parameters

base	MMDC peripheral base address
auto	refresh configuration collection,can set to NULL,when do not change refresh rate
derating	type

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	LPDDR2 AC timing/refresh derate wait flag timeout

status_t MMDC_MonitorLPDDR2OperationTemp	(	MMDC_Type *	base,
		uint32_t *	mr4
	)

Parameters

base	MMDC peripheral base address
MR4	pointer,use to store the mode register4 value

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	Get MR4 data flag timeout

status_t MMDC_ReadDQSGatingCalibration	(	MMDC_Type *	base,
		mmdc_readDQS_calibration_config_t *	config
	)

Parameters

base	MMDC peripheral base address
config	calibration configuration collection

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_ErrorDGCalibration	Read DQS data gate hardware calibration error

status_t MMDC_WriteLevelingCalibration	(	MMDC_Type *	base,
		mmdc_writeLeveling_calibration_config_t *	config
	)

Parameters

base	MMDC peripheral base address
config	calibration configuration collection

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_ErrorWriteLevelingCalibration	write leveling hardware calibration error

status_t MMDC_WriteCalibration	(	MMDC_Type *	base,
		mmdc_write_calibration_config_t *	config
	)

Parameters

base	MMDC peripheral base address
config	calibration configuration collection

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_ErrorWriteCalibration	write hardware calibration error

status_t MMDC_ReadCalibration	(	MMDC_Type *	base,
		mmdc_read_calibration_config_t *	config
	)

Parameters

base	MMDC peripheral base address
config	calibration configuration collection

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_ErrorReadCalibration	read hardware calibration error

void MMDC_DoFineTuning	(	MMDC_Type *	base,
		mmdc_device_type_t	devType,
		mmdc_fine_tuning_config_t *	config
	)

Parameters

base	MMDC peripheral base address
devType	MMDC device type
config	fine tuning configuration collection

void MMDC_SetTiming	(	MMDC_Type *	base,
		mmdc_device_type_t	devType,
		mmdc_device_timing_t *	timing
	)

Parameters

MMDC	peripheral base address
timing	pointer to timing structure

void MMDC_DeviceInit	(	MMDC_Type *	base,
		mmdc_device_type_t	devType,
		uint8_t	targetCS,
		mmdc_device_config_t *	devConfig
	)

Parameters

MMDC	base address
device	basic config info pointer

status_t MMDC_EnterConfigurationMode	(	MMDC_Type *	base,
		bool	enable
	)

Parameters

base	MMDC peripheral base address
enable	enter/exit flag

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	Enter configuration mode time out

void MMDC_DoZQCalibration	(	MMDC_Type *	base,
		mmdc_device_type_t	devType,
		mmdc_zq_config_t *	zqCal
	)

Parameters

base	MMDC peripheral base address
devType	device type
zqCal	info pointer

status_t MMDC_EnableLowPowerMode	(	MMDC_Type *	base,
		bool	enable
	)

Parameters

base	MMDC peripheral base address
enable	enable/disable flag

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	Enter low power mode timeout

status_t MMDC_EnableDVFSMode	(	MMDC_Type *	base,
		bool	enable
	)

Parameters

base	MMDC peripheral base address
enable	enable/disable flag

Return values

kStatus_Success	Read data succeed
kStatus_MMDC_WaitFlagTimeout	Enter DVFS mode timeout

void MMDC_Reset ( MMDC_Type * base )

Parameters

base	MMDC peripheral base address

static void MMDC_SwitchDeviceFrequency	(	MMDC_Type *	base,
		void *	ccm,
		void *	iomux,
		uint32_t	param,
		uint32_t	codeAddr
	)

inlinestatic

Parameters

MMDC	base address
CCM	base address
iomux	base address
target	frequency value for LPDDR2 and parameter address for DDR3
assembly	switch frequency code address

static void MMDC_EnableSBS	(	MMDC_Type *	base,
		bool	enable
	)

inlinestatic

Parameters

base	MMDC peripheral base address

static void MMDC_TriggerSBS ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

static uint32_t MMDC_GetAXIAddrBySBS ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

static uint32_t MMDC_GetAXIAttributeBySBS ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

static void MMDC_EnableProfiling	(	MMDC_Type *	base,
		bool	enable
	)

inlinestatic

Parameters

base	MMDC peripheral base address
enable	or disable flag

static void MMDC_ResumeProfiling ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

static void MMDC_ResetProfiling ( MMDC_Type * base )

inlinestatic

Parameters

base	MMDC peripheral base address

void MMDC_ExclusiveAccess	(	MMDC_Type *	base,
		mmdc_exaccess_config_t *	config,
		uint32_t	type
	)

Parameters

base	MMDC peripheral base address
exclusive	access config collection
exclusive	access config type

Overview

Typical use case

Data Structures

Typedefs

Enumerations

Driver version

Initialization and deinitialization

device operation

debug

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Data Fields

Field Documentation

Data Fields

Data Fields

Data Fields

Field Documentation

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation