MCUXpresso SDK Changelog
LPC_ADC
[2.6.0]
New Features
Added new feature macro to distinguish whether the GPADC_CTRL0_GPADC_TSAMP control bit is on the device.
Added new variable extendSampleTimeNumber to indicate the ADC extend sample time.
Bugfix
Fixed the bug that incorrectly sets the PASS_ENABLE bit based on the sample time setting.
[2.5.3]
Improvements
Release peripheral from reset if necessary in init function.
[2.5.2]
Improvements
Integrated different sequence’s sample time numbers into one variable.
Bug Fixes
Fixed violation of MISRA C-2012 rule 20.9 .
[2.5.1]
Bug Fixes
Fixed ADC conversion sequence priority misconfiguration issue in the ADC_SetConvSeqAHighPriority() and ADC_SetConvSeqBHighPriority() APIs.
Improvements
Supported configuration ADC conversion sequence sampling time.
[2.5.0]
Improvements
Add missing parameter tag of ADC_DoOffsetCalibration().
Bug Fixes
Removed a duplicated API with typo in name: ADC_EnableShresholdCompareInterrupt().
[2.4.1]
Bug Fixes
Enabled self-calibration after clock divider be changed to make sure the frequency update be taken.
[2.4.0]
New Features
Added new API ADC_DoOffsetCalibration() which supports a specific operation frequency.
Other Changes
Marked the ADC_DoSelfCalibration(ADC_Type *base) as deprecated.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.1 10.3 10.4 10.7 10.8 17.7.
[2.3.2]
Improvements
Added delay after enabling using the ADC GPADC_CTRL0 LDO_POWER_EN bit for JN5189/QN9090.
New Features
Added support for platforms which have only one ADC sequence control/result register.
[2.3.1]
Bug Fixes
Avoided writing ADC STARTUP register in ADC_Init().
Fixed Coverity zero divider error in ADC_DoSelfCalibration().
[2.3.0]
Improvements
Updated “ADC_Init()””ADC_GetChannelConversionResult()” API and “adc_resolution_t” structure to match QN9090.
Added “ADC_EnableTemperatureSensor” API.
[2.2.1]
Improvements
Added a brief delay in uSec after ADC calibration start.
[2.2.0]
Improvements
Updated “ADC_DoSelfCalibration” API and “adc_config_t” structure to match LPC845.
[2.1.0]
Improvements
Renamed “ADC_EnableShresholdCompareInterrupt” to “ADC_EnableThresholdCompareInterrupt”.
[2.0.0]
Initial version.
AES
[2.0.3]
Edit aes_one_block() function to be interrupt safe.
[2.0.2]
Fix MISRA-2012 issues.
[2.0.1]
Improvements
GCM constant time tag comparison.
[2.0.0]
Initial version.
CLOCK
[2.3.3]
Improvements
Added lost comments for some enumerations.
[2.3.2]
Bug Fixes
Fixed violation of MISRA C-2012 rule 5.7
[2.3.1]
Bug Fixes
Fixed MISRA C-2012 rule 10.1, rule 10.4, rule 10.8, rule 15.5 and so on.
Fixed IAR warning Pa082 for the clock driver.
[2.3.0]
New feature:
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.2.0]
New Feature:
add new APIs including CLOCK_GetEmcClkFreq and CLOCK_GetMCanClkFreq due to removing some variables in enum clock_name_t
[2.1.0]
Bug Fix:
Fix flexcomm0-9 clock calculation.
Correct the return frequency of CLOCK_GetFrgClkFreq.
Fix the bug in function CLOCK_GetPllConfig() to refine the cache feature.
Update the code to suppress the incorrect configuration in CLOCK_GetUsbPLLOutFromSetup().
Fix C++ build errors in CLOCK_GetClockAttachId() and CLOCK_AttachClk().
New feature
Adding new API CLOCK_DelayAtLeastUs() implemented by DWT to allow users set delay in unit of microsecond.
[2.0.4]
Bug Fix:
Fix attach incorrect attach_id.
[2.0.3]
New Feature:
add get actual clock attach id api to allow users to obtain the actual clock source in target register.
Bug Fix:
The attach clock and get actual clock attach id apis should check combination of two clock source.
Optimization:
Make the judgement statments more clear.
Strengthen the compatibility of clock attatch id.
Remove some unmeaningful definitions and add some useful ones to enhance readability.
[2.0.2]
Change CLOCK_SetupFROClocking from a macro to a function for different FRO setting address per different ROM version.
[2.0.1]
some minor fixes.
[2.0.0]
initial version.
COMMON
[2.5.0]
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]
New Features
Added NETC into status group.
[2.3.2]
Improvements
Make driver aarch64 compatible
[2.3.1]
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]
Other Change
Added MECC status group definition.
[2.2.6]
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]
New Features
Added OTFAD into status group.
[2.1.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]
Initial version.
CRC
[2.1.1]
Fix MISRA issue.
[2.1.0]
Add CRC_WriteSeed function.
[2.0.2]
Fix MISRA issue.
[2.0.1]
Fixed KPSDK-13362. MDK compiler issue when writing to WR_DATA with -O3 optimize for time.
[2.0.0]
Initial version.
CTIMER
[2.3.3]
Bug Fixes
Fix CERT INT30-C INT31-C issue.
Make API CTIMER_SetupPwm and CTIMER_UpdatePwmDutycycle return fail if pulse width register overflow.
[2.3.2]
Bug Fixes
Clear unexpected DMA request generated by RESET_PeripheralReset in API CTIMER_Init to avoid trigger DMA by mistake.
[2.3.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.7 and 12.2.
[2.3.0]
Improvements
Added the CTIMER_SetPrescale(), CTIMER_GetCaptureValue(), CTIMER_EnableResetMatchChannel(), CTIMER_EnableStopMatchChannel(), CTIMER_EnableRisingEdgeCapture(), CTIMER_EnableFallingEdgeCapture(), CTIMER_SetShadowValue(),APIs Interface to reduce code complexity.
[2.2.2]
Bug Fixes
Fixed SetupPwm() API only can use match 3 as period channel issue.
[2.2.1]
Bug Fixes
Fixed use specified channel to setting the PWM period in SetupPwmPeriod() API.
Fixed Coverity Out-of-bounds issue.
[2.2.0]
Improvements
Updated three API Interface to support Users to flexibly configure the PWM period and PWM output.
Bug Fixes
MISRA C-2012 issue fixed: rule 8.4.
[2.1.0]
Improvements
Added the CTIMER_GetOutputMatchStatus() API Interface.
Added feature macro for FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 and FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7 and 11.9.
[2.0.2]
New Features
Added new API “CTIMER_GetTimerCountValue” to get the current timer count value.
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
Added a new feature macro to update the API of CTimer driver for lpc8n04.
[2.0.1]
Improvements
API Interface Change
Changed API interface by adding CTIMER_SetupPwmPeriod API and CTIMER_UpdatePwmPulsePeriod API, which both can set up the right PWM with high resolution.
[2.0.0]
Initial version.
LPC_DMA
[2.5.3]
Improvements
Add assert in DMA_SetChannelXferConfig to prevent XFERCOUNT value overflow.
[2.5.2]
Bug Fixes
Use separate “SET” and “CLR” registers to modify shared registers for all channels, in case of thread-safe issue.
[2.5.1]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 11.6.
[2.5.0]
Improvements
Added a new api DMA_SetChannelXferConfig to set DMA xfer config.
[2.4.4]
Bug Fixes
Fixed the issue that DMA_IRQHandle might generate redundant callbacks.
Fixed the issue that DMA driver cannot support channel bigger then 32.
Fixed violation of the MISRA C-2012 rule 13.5.
[2.4.3]
Improvements
Added features FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn/FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE/FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE to support the descriptor align size not constant in the two instances.
[2.4.2]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 8.4.
[2.4.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 5.7, 8.3.
[2.4.0]
Improvements
Added new APIs DMA_LoadChannelDescriptor/DMA_ChannelIsBusy to support polling transfer case.
Bug Fixes
Added address alignment check for descriptor source and destination address.
Added DMA_ALLOCATE_DATA_TRANSFER_BUFFER for application buffer allocation.
Fixed the sign-compare warning.
Fixed violations of the MISRA C-2012 rules 18.1, 10.4, 11.6, 10.7, 14.4, 16.3, 20.7, 10.8, 16.1, 17.7, 10.3, 3.1, 18.1.
[2.3.0]
Bug Fixes
Removed DMA_HandleIRQ prototype definition from header file.
Added DMA_IRQHandle prototype definition in header file.
[2.2.5]
Improvements
Added new API DMA_SetupChannelDescriptor to support configuring wrap descriptor.
Added wrap support in function DMA_SubmitChannelTransfer.
[2.2.4]
Bug Fixes
Fixed the issue that macro DMA_CHANNEL_CFER used wrong parameter to calculate DSTINC.
[2.2.3]
Bug Fixes
Improved DMA driver Deinit function for correct logic order.
Improvements
Added API DMA_SubmitChannelTransferParameter to support creating head descriptor directly.
Added API DMA_SubmitChannelDescriptor to support ping pong transfer.
Added macro DMA_ALLOCATE_HEAD_DESCRIPTOR/DMA_ALLOCATE_LINK_DESCRIPTOR to simplify DMA descriptor allocation.
[2.2.2]
Bug Fixes
Do not use software trigger when hardware trigger is enabled.
[2.2.1]
Bug Fixes
Fixed Coverity issue.
[2.2.0]
Improvements
Changed API DMA_SetupDMADescriptor to non-static.
Marked APIs below as deprecated.
DMA_PrepareTransfer.
DMA_Submit transfer.
Added new APIs as below:
DMA_SetChannelConfig.
DMA_PrepareChannelTransfer.
DMA_InstallDescriptorMemory.
DMA_SubmitChannelTransfer.
DMA_SetChannelConfigValid.
DMA_DoChannelSoftwareTrigger.
DMA_LoadChannelTransferConfig.
[2.0.1]
Improvements
Added volatile for DMA descriptor member xfercfg to avoid optimization.
[2.0.0]
Initial version.
DMIC
[2.3.2]
New Features
Supported 4 channels in driver.
[2.3.1]
Bug Fixes
Fixed the issue that DMIC_EnableChannelDma and DMIC_EnableChannelFifo did not clean relevant bits.
[2.3.0]
Improvements
Added new apis DMIC_ResetChannelDecimator/DMIC_EnableChannelGlobalSync/DMIC_DisableChannelGlobalSync.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 14.4, 17.7, 10.4, 10.3, 10.8, 14.3.
[2.2.0]
Bug Fixes
Corrected the usage of feature FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS.
[2.1.1]
Improvements
Added feature FSL_FEATURE_DMIC_HAS_NO_IOCFG for IOCFG register.
[2.1.0]
New Features
Added API DMIC_EnbleChannelInterrupt/DMIC_EnbleChannelDma to replace API DMIC_SetOperationMode.
Added API DMIC_SetIOCFG and marked DMIC_ConfigIO as deprecated.
Added API DMIC_EnableChannelSignExtend to support sign extend feature.
[2.0.5]
Improvements
Changed some parameters’ value of DMIC_FifoChannel API, such as enable, resetn, and trig_level. This is not possible for the current code logic, so it improves the DMIC_FifoChannel logic and fixes incorrect math logic.
[2.0.4]
Bug Fixes
Fixed the issue that DMIC DMA driver(ver2.0.3) did not support calling DMIC_TransferReceiveDMA in DMA callback as it did before version 2.0.3. But calling DMIC_TransferReceiveDMA in callback is not recommended.
[2.0.3]
New Features
Supported linked transfer in DMIC DMA driver.
Added new API DMIC_EnableChannelFifo/DMIC_DoFifoReset/DMIC_InstallDMADescriptor.
[2.0.2]
New Features
Supported more channels in driver.
[2.0.1]
New Features
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
DMIC_DMA
[2.4.0]
Bug Fixes
Fixed the issue that DMIC_TransferAbortReceiveDMA can not disable dmic and dma request issue.
[2.3.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.3.0]
Refer DMIC driver change log 2.0.1 to 2.3.0
EMC
[2.0.4]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.8, 11.9, 14.2, 14.3, 14.4.
[2.0.3]
Improvements
Used SDK_DelayAtLeastUs instead of for loop during the dynamic memory initialization.
[2.0.3]
Improvements
Replaced deprecated enumerator CLOCK_GetFreq(kCLOCK_EMC) with CLOCK_GetEmcClkFreq().
[2.0.2]
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.1]
Improvements
Added const for two BASE values.
[2.0.0]
Initial version.
LPC_ENET
[2.3.5]
Bug Fixes
Fixed ENET_GetMacAddr address byte order not matching ENET_SetMacAddr.
[2.3.4]
Bug Fixes
Fixed the issue that free wrong buffer address when one frame stores in multiple buffers and memory pool is not enough to allocate these buffers to receive one complete frame.
Fixed the issue that ENET_DropFrame checks the buffer descriptor flag after it has been re-initialized.
Fixed the ENET_GetRxFrame FCS calculation issue.
Fixed the issue that there’s no valid error type in the return structure when Rx error bit is set.
[2.3.3]
Bug Fixes
Fixed the issue that ENET_SetSMI uses wrong clock source to calculate the divisor.
[2.3.2]
New features
Added hardware checksum acceleration support.
Bug Fixes
Fixed the issue that enable/disable interrupt APIs miss part of configuration.
[2.3.1]
Improvements
update ENET_SetSYSControl to support mcx family.
[2.3.0]
Improvements
Added MDIO access wrapper APIs for ease of use.
[2.2.0]
Bug Fixes
Corrected the timestamp retrieving code in ReadFrame.
New Features
Supported zero copy Rx with new APIs.
Improvements
Removed 4 bytes CRC data in ReadFrame function, not give them to user.
Deleted previous timestamp rings which store Tx/Rx timestamp temporarily for further retrieving. Now get Rx timestamp directly with receiving frame API, and get Tx timestamp in Tx over interrupt handler callback.
Added channel parameter for the SendFrame function, let user to decide which kind of frame can be sent from specified channel.
Supported scattered Tx buffers and more Tx configurations in SendFrame which aren’t integrated.
Adjusted the callback location in Tx reclaim function. When use multiple BDs for Tx, only last BD transmit over interrupt event calls the callback. It simplifies the usage of Tx reclaiming.
Added interrupt configuration in config parameter for ENET_Init() to simplify the interrupt enable.
Changed the Tx/Rx descriptor name to common name rather than previous read format name which make user confused when driver uses it as write-back format.
[2.1.5]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 3.1,5.8,8.4,8.6,10.1,10.3,10.4,10.6,10.8,11.6,11.9,12.2,14.4,15.6,17.7,21.15.
[2.1.4]
Bug Fixes
Fixed the MDC clock divider setting issue occurring when core clock range exceeds 150M.
[2.1.3]
In ENET_StartRxTx, updated to enable TX and RX at the same time to avoid issue where ENET module could not work under 10 M.
Changed to use CLOCK_GetCoreSysClkFreq() instead of SystemCoreClock to get accurate core clock.
[2.1.2]
Bug Fixes
Fixed ENET receive issue where it sometimes lost some unicast packets. The issue is caused by the program timing issue for writing MAC_ADDR_LOW and MAC_ADDR_HIGH.
[2.1.1]
New Features
Added a control macro to enable/disable the CLOCK code in current driver.
[2.1.0]
New Features
Added two APIs to set the ENET to ACCPET or reject the multicast frames.
[2.0.0]
Initial version.
FLEXCOMM
[2.0.2]
Bug Fixes
Fixed typos in FLEXCOMM15_DriverIRQHandler().
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
Improvements
Added instance calculation in FLEXCOMM16_DriverIRQHandler() to align with Flexcomm 14 and 15.
[2.0.1]
Improvements
Added more IRQHandler code in drivers to adapt new devices.
[2.0.0]
Initial version.
FMEAS
[2.1.1]
Bug Fixes
MISRA C-2012 issues fixed: rule 10.4, rule 10.8.
[2.1.0]
Updated “FMEAS_GetFrequency”,”FMEAS_StartMeasure”,”FMEAS_IsMeasureComplete” API and add definition to match ASYNC_SYSCON.
[2.0.0]
Initial version ported from LPCOpen.
GINT
[2.1.1]
Improvements
Added support for platforms with PORT_POL and PORT_ENA registers without arrays.
[2.1.0]
Improvements
Updated for platforms which only has one port.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8.
[2.0.2]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule 17.7.
[2.0.1]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
GPIO
[2.1.7]
Improvements
Enhanced GPIO_PinInit to enable clock internally.
[2.1.6]
Bug Fixes
Clear bit before set it within GPIO_SetPinInterruptConfig() API.
[2.1.5]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 3.1, 10.6, 10.7, 17.7.
[2.1.4]
Improvements
Added API GPIO_PortGetInterruptStatus to retrieve interrupt status for whole port.
Corrected typos in header file.
[2.1.3]
Improvements
Updated “GPIO_PinInit” API. If it has DIRCLR and DIRSET registers, use them at set 1 or clean 0.
[2.1.2]
Improvements
Removed deprecated APIs.
[2.1.1]
Improvements
API interface changes:
Refined naming of APIs while keeping all original APIs, marking them as deprecated. Original APIs will be removed in next release. The mainin change is updating APIs with prefix of _PinXXX() and _PorortXXX
[2.1.0]
New Features
Added GPIO initialize API.
[2.0.0]
Initial version.
I2C
[2.3.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
Fixed issue that if master only sends address without data during I2C interrupt transfer, address nack cannot be detected.
[2.3.2]
Improvement
Enable or disable timeout option according to enableTimeout.
Bug Fixes
Fixed timeout value calculation error.
Fixed bug that the interrupt transfer cannot recover from the timeout error.
[2.3.1]
Improvement
Before master transfer with transactional APIs, enable master function while disable slave function and vise versa for slave transfer to avoid the one affecting the other.
Bug Fixes
Fixed bug in I2C_SlaveEnable that the slave enable/disable should not affect the other register bits.
[2.3.0]
Improvement
Added new return codes kStatus_I2C_EventTimeout and kStatus_I2C_SclLowTimeout, and added the check for event timeout and SCL timeout in I2C master transfer.
Fixed bug in slave transfer that the address match event should be invoked before not after slave transmit/receive event.
[2.2.0]
New Features
Added enumeration _i2c_status_flags to include all previous master and slave status flags, and added missing status flags.
Modified I2C_GetStatusFlags to get all I2C flags.
Added API I2C_ClearStatusFlags to clear all clearable flags not just master flags.
Modified master transactional APIs to enable bus event timeout interrupt during transfer, to avoid glitch on bus causing transfer hangs indefinitely.
Bug Fixes
Fixed bug that status flags and interrupt enable masks share the same enumerations by adding enumeration _i2c_interrupt_enable for all master and slave interrupt sources.
[2.1.0]
Bug Fixes
Fixed bug that during master transfer, when master is nacked during slave probing or sending subaddress, the return status should be kStatus_I2C_Addr_Nak rather than kStatus_I2C_Nak.
Bug Fixes
Fixed MISRA issues.
Fixed rules 10.1, 10.4, 13.5.
New Features
Added macro I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK, so that user can configure whether to ignore the last byte being nacked by slave during master transfer.
[2.0.8]
Bug Fixes
Fixed I2C_MasterSetBaudRate issue that MSTSCLLOW and MSTSCLHIGH are incorrect when MSTTIME is odd.
[2.0.7]
Bug Fixes
Two dividers, CLKDIV and MSTTIME are used to configure baudrate. According to reference manual, in order to generate 400kHz baudrate, the clock frequency after CLKDIV must be less than 2mHz. Fixed the bug that, the clock frequency after CLKDIV may be larger than 2mHz using the previous calculation method.
Fixed MISRA 10.1 issues.
Fixed wrong baudrate calculation when feature FSL_FEATURE_I2C_PREPCLKFRG_8MHZ is enabled.
[2.0.6]
New Features
Added master timeout self-recovery support for feature FSL_FEATURE_I2C_TIMEOUT_RECOVERY.
Bug Fixes
Eliminated IAR Pa082 warning.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
[2.0.5]
Bug Fixes
Fixed wrong assignment for datasize in I2C_InitTransferStateMachineDMA.
Fixed wrong working flow in I2C_RunTransferStateMachineDMA to ensure master can work in no start flag and no stop flag mode.
Fixed wrong working flow in I2C_RunTransferStateMachine and added kReceiveDataBeginState in _i2c_transfer_states to ensure master can work in no start flag and no stop flag mode.
Fixed wrong handle state in I2C_MasterTransferDMAHandleIRQ. After all the data has been transfered or nak is returned, handle state should be changed to idle.
Improvements
Rounded up the calculated divider value in I2C_MasterSetBaudRate.
[2.0.4]
Improvements
Updated the I2C_WATI_TIMEOUT macro to unified name I2C_RETRY_TIMES
Updated the “I2C_MasterSetBaudRate” API to support baudrate configuration for feature QN9090.
Bug Fixes
Fixed build warnning caused by uninitialized variable.
Fixed COVERITY issue of unchecked return value in I2C_RTOS_Transfer.
[2.0.3]
Improvements
Unified the component full name to FLEXCOMM I2C(DMA/FREERTOS) driver.
[2.0.2]
Improvements
In slave IRQ:
Changed slave receive process to first set the I2C_SLVCTL_SLVCONTINUE_MASK to acknowledge the received data, then do data receive.
Improved slave transmit process to set the I2C_SLVCTL_SLVCONTINUE_MASK immediately after writing the data.
[2.0.1]
Improvements
Added I2C_WATI_TIMEOUT macro to allow users to specify the timeout times for waiting flags in functional API and blocking transfer API.
[2.0.0]
Initial version.
I2S
[2.3.2]
Bug Fixes
Fixed warning for comparison between pointer and integer.
[2.3.1]
Bug Fixes
Updated the value of TX/RX software transfer state machine after transfer contents are submitted to avoid race condition.
[2.3.0]
Improvements
Added api I2S_InstallDMADescriptorMemory/I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA to support loop transfer.
Added api I2S_EmptyTxFifo to support blocking flush tx fifo.
Updated api I2S_TransferAbortDMA by removed the blocking flush tx fifo from this function.
Bug Fixes
Removed the while loop in abort transfer function to fix the dead loop issue under specific user case.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4.
[2.2.1]
Improvements
Added feature FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn for the SOC has parts of instance support secondary channel.
Bug Fixes
Added volatile statement for the state variable of i2s_handle and enable the mainline channel pair before enable interrupt to avoid the issue of code excution reordering which may cause the interrupt generated unexpectedly.
[2.2.0]
Improvements
Added 8/16/24 bits mono data format transfer support in I2S driver.
Added new apis I2S_SetBitClockRate.
Bug Fixes
Fixed the PA082 build warning.
Fixed the sign-compare warning.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8, 11.9, 10.1, 11.3, 13.5, 11.8, 10.3, 10.7.
Fixed the Operand don’t affect result Coverity issue.
[2.1.0]
Improvements
Added a feature for the FLEXCOMM which supports I2S and has interconnection with DMIC.
Used a feature to control PDMDATA instead of I2S_CFG1_PDMDATA.
Added member bytesPerFrame in i2s_dma_handle_t, used for DMA transfer width configure, instead of using sizeof(uint32_t) hardcode.
Used the macro provided by DMA driver to define the I2S DMA descriptor.
Bug Fixes
Fixed the issue that I2S DMA driver always generated duplicate callback.
[2.0.3]
New Features
Added a feature to remove configuration for the second channel on LPC51U68.
[2.0.2]
New Features
Added ENABLE_IRQ handle after register I2S interrupt handle.
[2.0.1]
Improvements
Unified the component full name to FLEXCOMM I2S (DMA) driver.
[2.0.0]
Initial version.
I2S_DMA
[2.3.3]
Bug Fixes
Fixed data size limit does not match the macro DMA_MAX_TRANSFER_BYTES issue.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.3.1]
Refer I2S driver change log 2.0.1 to 2.3.1
IAP
[2.0.7]
Bug Fixes
Fixed IAP_ReinvokeISP bug that can’t support UART ISP auto baud detection.
[2.0.6]
Bug Fixes
Fixed IAP_ReinvokeISP wrong parameter setting.
[2.0.5]
New Feature
Added support config flash memory access time.
[2.0.4]
Bug Fixes
Fixed the violations of MISRA 2012 rules 9.1
[2.0.3]
New Features
Added support for LPC 845’s FAIM operation.
Added support for LPC 80x’s fixed reference clock for flash controller.
Added support for LPC 5411x’s Read UID command useless situation.
Improvements
Improved the document and code structure.
Bug Fixes
Fixed the violations of MISRA 2012 rules:
Rule 10.1 10.3 10.4 17.7
[2.0.2]
New Features
Added an API to read generated signature.
Bug Fixes
Fixed the incorrect board support of IAP_ExtendedFlashSignatureRead().
[2.0.1]
New Features
Added an API to read factory settings for some calibration registers.
Improvements
Updated the size of result array in part APIs.
[2.0.0]
Initial version.
INPUTMUX
[2.0.8]
Improvements
Updated a feature macro usage for function INPUTMUX_EnableSignal.
[2.0.7]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.6]
Bug Fixes
Fixed the documentation wrong in API INPUTMUX_AttachSignal.
[2.0.5]
Bug Fixes
Fixed build error because some devices has no sct.
[2.0.4]
Bug Fixes
Fixed violations of the MISRA C-2012 rule 10.4, 12.2 in INPUTMUX_EnableSignal() function.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 10.7, 12.2.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 12.2.
[2.0.1]
Support channel mux setting in INPUTMUX_EnableSignal().
[2.0.0]
Initial version.
IOCON
[2.2.0]
Improvements
Removed duplicate macro defintions.
Renamed ‘IOCON_I2C_SLEW’ macro to ‘IOCON_I2C_MODE’ to match its companion ‘IOCON_GPIO_MODE’. The original is kept as a deprecated symbol.
[2.1.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.1.1]
Updated left shift format with mask value instead of a constant value to automatically adapt to all platforms.
[2.1.0]
Added a new IOCON_PinMuxSet() function with a feature IOCON_ONE_DIMENSION for LPC845MAX board.
[2.0.0]
Initial version.
LPC_LCDC
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 3.1, 10.3, 10.4, 10.6, 10.7, 10.8, 14.4, 17.7.
[2.0.1]
New Features
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
MCAN
[2.4.2]
Bug Fixes
Fixed MISRA issue rule-10.3, rule-10.6, rule-10.7 and rule-15.7.
[2.4.1]
Bug Fixes
Fixed incorrect fifo1 status on message lost.
[2.4.0]
Improvements
Add MCAN_CalculateSpecifiedTimingValues() API to get CAN bit timing parameter with user-defined settings.
Add MCAN_FDCalculateSpecifiedTimingValues() API to get CANFD bit timing parameter with user-defined settings.
[2.3.2]
Bug Fixes
Fix MISRA C-2012 issue 10.1 and 10.4.
[2.3.1]
Bug Fixes
Fixed the issue that MCAN_TransferSendNonBlocking() API can’t send remote frame.
[2.3.0]
Improvements
Add MCAN_SetMessageRamConfig() API to perform global message RAM configure.
Add MCAN_EnterInitialMode() API.
[2.2.0]
Improvements
Add MCAN_SetBaudRate/MCAN_SetBaudRateFD APIs to make users easy to set CAN baud rate.
[2.1.8]
Bug Fixes
Add check FIFO status code in MCAN_ReadRxFifo() to avoid read back empty frame and wrong trigger the FIFO index increase.
[2.1.7]
Bug Fixes
Fixed the clear error flags issue in MCAN_TransferHandleIRQ() API.
Fixed the Solve Tx interrupt issue in MCAN_TransferHandleIRQ() API which may abort the unhandled transfers.
Remove disable global tx interrupt from MCAN_TransferAbortSend API.
[2.1.6]
Bug Fixes
Fixed the issue of writing 1 in the following functions.
MCAN_TransmitAddRequest
MCAN_TransmitCancelRequest
MCAN_ClearRxBufferStatusFlag
[2.1.5]
Bug Fixes
Fix MISRA C-2012 issue.
[2.1.4]
Improvements
Updated improve timing APIs to make it can calculate the CiA recommended timing configuration.
Implement Transmitter Delay Compensation feature.
Modify the default baudRateFD value to 2M.
Bug Fixes
Fixed the code error issue in MCAN_ClearStatusFlag() to avoid clear all flags.
[2.1.3]
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
MCAN_CalculateImprovedTimingValues
MCAN_FDCalculateImprovedTimingValues
[2.1.2]
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
MCAN_CalculateImprovedTimingValues
MCAN_FDCalculateImprovedTimingValues
[2.1.1]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.6, rule-10.7, rule-10.8, rule-11.9, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-17.7, rule-18.4, rule-2.2, rule-21.15, rule-5.8, rule-8.3.
Fixed the Coverity issue of BAD_SHIFT in MCAN.
Fixed the issue of Pa082 warning.
Fixed the issue of dropping interrupt flags in handler function.
[2.1.0]
Bug Fixes
Fixed Coverity issue FORWARD_NULL.
Fixed Clang issue.
Fixed legacy issue in the driver and changed default bus data baud rate for CANFD.
Improvements
Implemented feature for improved timing configuration.
[2.0.3]
Improvements
Used memset to initialize the structure before using.
Added function definition comment in c file.
Updated source file license to SPDX BSD_3.
Corrected capital mistake of Fifo and fifo.
Reset the MCAN module in LPC drivers after clock enable.
[2.0.2]
Bug Fixes
Picked MISRA fixed in release 8 branch.
MISRA C 2012 fixed regarding FlexCAN and MCAN address update.
Improvements
Implemented for delay/retry in MCAN driver.
[2.0.1]
Improvements
LPC54608 chip did not support the FD feature, so added a feature macro for it.
[2.0.0]
Initial version.
MRT
[2.0.4]
Improvements
Don’t reset MRT when there is not system level MRT reset functions.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1 and 10.4.
Fixed the wrong count value assertion in MRT_StartTimer API.
[2.0.2]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.0.1]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
OTP
[2.0.1]
Bug Fixes
Fixed MISRA-C 2012 violations.
[2.0.0]
Initial version.
PINT
[2.1.13]
Improvements
Added instance array for PINT to adapt more devices.
Used release reset instead of reset PINT which may clear other related registers out of PINT.
[2.1.12]
Bug Fixes
Fixed coverity issue.
[2.1.11]
Bug Fixes
Fixed MISRA C-2012 rule 10.7 violation.
[2.1.10]
New Features
Added the driver support for MCXN10 platform with combined interrupt handler.
[2.1.9]
Bug Fixes
Fixed MISRA-2012 rule 8.4.
[2.1.8]
Bug Fixes
Fixed MISRA-2012 rule 10.1 rule 10.4 rule 10.8 rule 18.1 rule 20.9.
[2.1.7]
Improvements
Added fully support for the SECPINT, making it can be used just like PINT.
[2.1.6]
Bug Fixes
Fixed the bug of not enabling common pint clock when enabling security pint clock.
[2.1.5]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule 10.1 rule 10.3 rule 10.4 rule 10.8 rule 14.4.
Changed interrupt init order to make pin interrupt configuration more reasonable.
[2.1.4]
Improvements
Added feature to control distinguish PINT/SECPINT relevant interrupt/clock configurations for PINT_Init and PINT_Deinit API.
Swapped the order of clearing PIN interrupt status flag and clearing pending NVIC interrupt in PINT_EnableCallback and PINT_EnableCallbackByIndex function.
Bug Fixes
Fixed build issue caused by incorrect macro definitions.
[2.1.3]
Bug fix:
Updated PINT_PinInterruptClrStatus to clear PINT interrupt status when the bit is asserted and check whether was triggered by edge-sensitive mode.
Write 1 to IST corresponding bit will clear interrupt status only in edge-sensitive mode and will switch the active level for this pin in level-sensitive mode.
Fixed MISRA c-2012 rule 10.1, rule 10.6, rule 10.7.
Added FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS to distinguish IRQ relevant array definitions for SECPINT/PINT on lpc55s69 board.
Fixed PINT driver c++ build error and remove index offset operation.
[2.1.2]
Improvement:
Improved way of initialization for SECPINT/PINT in PINT_Init API.
[2.1.1]
Improvement:
Enabled secure pint interrupt and add secure interrupt handle.
[2.1.0]
Added PINT_EnableCallbackByIndex/PINT_DisableCallbackByIndex APIs to enable/disable callback by index.
[2.0.2]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.1]
Bug fix:
Updated PINT driver to clear interrupt only in Edge sensitive.
[2.0.0]
Initial version.
POWER
[2.1.0]
New features
Added BOD control APIs.
[2.0.0]
initial version.
PUF
[2.1.6]
Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If this shorter time will also fail, initialization will be tried with worst case time as before.
[2.1.5]
Use common SDK delay in puf_wait_usec().
[2.1.4]
Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization out delay loop.
[2.1.3]
Fix MISRA C-2012 issue.
[2.1.2]
Update: Add automatic big to little endian swap for user (pre-shared) keys destinated to secret hardware bus (PUF key index 0).
[2.1.1]
Fix ARMGCC build warning .
[2.1.0]
Align driver with PUF SRAM controller registers on LPCXpresso55s16.
Update initizalition logic .
[2.0.3]
Fix MISRA C-2012 issue.
[2.0.2]
New feature:
Add PUF configuration structure and support for PUF SRAM controller.
Improvements:
Remove magic constants.
[2.0.1]
Bug Fixes:
Fixed puf_wait_usec function optimization issue.
[2.0.0]
Initial version.
RESET
[2.4.0]
Improvements
Add RESET_ReleasePeripheralReset API.
[2.0.1]
Update component full_name to “Reset Driver”.
[2.0.0]
initial version.
RIT
[2.1.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 11.9, 17.7.
[2.1.0]
Bug Fixes
Fixed issue for wrong implementation of clearing counter API in RIT driver.
[2.0.2]
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.1]
Bug Fixes
Fixed incorrect comments of some APIs.
[2.0.0]
Initial version.
RNG
[2.1.0]
Renamed function RNG_GetRandomData() to RNG_GetRandomDataWord(). Added function RNG_GetRandomData() which discarding next 32 words after reading RNG register which results into better entropy, as is recommended in UM.
API is aligned with other RNG driver, having similar functionality as other RNG/TRNG drivers.
[2.0.0]
Initial version.
RTC
[2.2.0]
New Features
Created new APIs for the RTC driver.
RTC_EnableSubsecCounter
RTC_GetSubsecValue
[2.1.3]
Bug Fixes
Fixed issue that RTC_GetWakeupCount may return wrong value.
[2.1.2]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.1, 10.4 and 10.7.
[2.1.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3 and 11.9.
[2.1.0]
Bug Fixes
Created new APIs for the RTC driver.
RTC_EnableTimer
RTC_EnableWakeUpTimerInterruptFromDPD
RTC_EnableAlarmTimerInterruptFromDPD
RTC_EnableWakeupTimer
RTC_GetEnabledWakeupTimer
RTC_SetSecondsTimerMatch
RTC_GetSecondsTimerMatch
RTC_SetSecondsTimerCount
RTC_GetSecondsTimerCount
deprecated legacy APIs for the RTC driver.
RTC_StartTimer
RTC_StopTimer
RTC_EnableInterrupts
RTC_DisableInterrupts
RTC_GetEnabledInterrupts
[2.0.0]
Initial version.
SCTIMER
[2.5.1]
Bug Fixes
Fixed bug in SCTIMER_SetupCaptureAction: When kSCTIMER_Counter_H is selected, events 12-15 and capture registers 12-15 CAPn_H field can’t be used.
[2.5.0]
Improvements
Add SCTIMER_GetCaptureValue API to get capture value in capture registers.
[2.4.9]
Improvements
Supported platforms which don’t have system level SCTIMER reset.
[2.4.8]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t writes MATCH_H bit and RELOADn_H.
[2.4.7]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t configure 100% duty cycle PWM.
[2.4.6]
Bug Fixes
Fixed the issue where the H register was not written as a word along with the L register.
Fixed the issue that the SCTIMER_SetCOUNTValue() is not configured with high 16 bits in unify mode.
[2.4.5]
Bug Fixes
Fix SCT_EV_STATE_STATEMSKn macro build error.
[2.4.4]
Bug Fixes
Fix MISRA C-2012 issue 10.8.
[2.4.3]
Bug Fixes
Fixed the wrong way of writing CAPCTRL and REGMODE registers in SCTIMER_SetupCaptureAction.
[2.4.2]
Bug Fixes
Fixed SCTIMER_SetupPwm 100% duty cycle issue.
[2.4.1]
Bug Fixes
Fixed the issue that MATCHn_H bit and RELOADn_H bit could not be written.
[2.4.0]
[2.3.0]
Bug Fixes
Fixed the potential overflow issue of pulseperiod variable in SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle API.
Fixed the issue of SCTIMER_CreateAndScheduleEvent API does not correctly work with 32 bit unified counter.
Fixed the issue of position of clear counter operation in SCTIMER_Init API.
Improvements
Update SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle to support generate 0% and 100% PWM signal.
Add SCTIMER_SetupEventActiveDirection API to configure event activity direction.
Update SCTIMER_StartTimer/SCTIMER_StopTimer API to support start/stop low counter and high counter at the same time.
Add SCTIMER_SetCounterState/SCTIMER_GetCounterState API to write/read counter current state value.
Update APIs to make it meaningful.
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
[2.2.0]
Improvements
Updated for 16-bit register access.
[2.1.3]
Bug Fixes
Fixed the issue of uninitialized variables in SCTIMER_SetupPwm.
Fixed the issue that the Low 16-bit and high 16-bit work independently in SCTIMER driver.
Improvements
Added an enumerable macro of unify counter for user.
kSCTIMER_Counter_U
Created new APIs for the RTC driver.
SCTIMER_SetupStateLdMethodAction
SCTIMER_SetupNextStateActionwithLdMethod
SCTIMER_SetCOUNTValue
SCTIMER_GetCOUNTValue
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
Deprecated legacy APIs for the RTC driver.
SCTIMER_SetupNextStateAction
[2.1.2]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7, 11.9, 14.2 and 15.5.
[2.1.1]
Improvements
Updated the register and macro names to align with the header of devices.
[2.1.0]
Bug Fixes
Fixed issue where SCT application level Interrupt handler function is occupied by SCT driver.
Fixed issue where wrong value for INSYNC field inside SCTIMER_Init function.
Fixed issue to change Default value for INSYNC field inside SCTIMER_GetDefaultConfig.
[2.0.1]
New Features
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
SDIF
[2.1.0]
Improvements
Removed reduntant member endianMode in sdif_config_t.
Added error status check in function SDIF_WaitCommandDone.
Fixed the read fifo data incomplete issue in interrupt non-dma mode.
[2.0.15]
Bug Fixes
Cleared the interrupt status before enable the interrupt to avoid interrupt generate unexpectedly.
Fixed the SDIF_ReadDataPortBlocking blocking at wrong condition issue.
Improvements
Enabled the functionality of timeout parameter in SDIF_SendCommand.
Added the error recovery while sending sync clock command timeout.
[2.0.14]
Improvements
Used different status code for command and data interrupt callback.
Bug Fixes
Fixed the DMA descriptor attribute field unreset when configuing the current transfer DMA descriptor issue which may cause the transfer terminate unexpected.
[2.0.13]
Improvements
Disabled redundant interrupt per different transfer request.
Disabled interrupt and reset command/data pointer in handle when transfer completes.
Bug Fixes
Fixed the PA082 build warning.
Fixed violations of the MISRA C-2012 rules 14.4, 17.7, 10.4, 10.3, 10.8, 14.3, 10.1, 16.4, 15.7, 12.2, 11.3, 11.9.
[2.0.12]
Bug Fixes
Fixed the issue that SDIF_ConfigClockDelay didn’t reset the delay field before write.
Removed useless fifo reset code in transfer function.
Fixed the divider overflow issue in function SDIF_SetCardClock.
[2.0.11]
Improvements
Added API SDIF_GetEnabledInterruptStatus/SDIF_GetEnabledDMAInterruptStatus and used in SDIF_TransferHandleIRQ.
Removed useless members interruptFlags/dmaInterruptFlags in the sdif_handle_t.
Improved SDIF_SendCommand with return success directly when timeout is 0.
Added timeout error check when sending update clock command in SDIF_SetCardClock.
Removed START_CMD status polling for normal command sending in SDIF_TransferBloking/SDIF_TransferNonBlocking.
Disabled timeout parameter in function SDIF_SendCommand.
Bug Fixes
Added delay cycle for the default speed mode(400 K and 25 M) to fix the timing issue when different AHB clocks are configured.
[2.0.10]
Bug Fixes
Fixed the issue that API SDIF_EnableCardClock could not clear the clock enable bit.
[2.0.9]
Bug Fixes
Fixed MDK 66-D warning.
[2.0.8]
New Features
Added control macro to enable/disable the RESET and CLOCK code in current driver.
Disabled useless interrupt while DMA is used.
Updated SDIF driver for one instance support two cards.
[2.0.7]
Bug Fixes
Enlarged the timeout value to avoid a command conflict issue.
[2.0.6]
Bug Fixes
Removed assert(srcClock_Hz <= FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK).
Used hardware reset instead of software reset during initialization.
[2.0.5]
New Features
Added non-word aligned data address and DMA descriptor address transfer support. Once one of the above addresses is not aligned, switch to host transfer mode.
Bug Fixes
Fixed the issue that DMA suspended during initialization.
Removed useless memset function call.
[2.0.4]
Improvements
Added cardInserted/cardRemoved callback function.
Added host base address/user data parameter for all call back functions.
[2.0.3]
Improvements
Improved Clock Delay macro to allow the user to redefine and remove useless delay for clock below 25 MHz.
[2.0.2]
Bug Fixes
Fixed the issue that the status flag could not be cleared entirely after transfer complete.
[2.0.1]
New Features
Improved interrupt transfer callback.
Bug Fixes
Added assert to limit the SDIF source clock below 52 MHz.
[2.0.0]
Initial version.
SHA
[2.3.2]
Add -O2 optimization for GCC to sha_process_message_data_master(), because without it the function hangs under some conditions.
[2.3.1]
Modified sha_process_message_data_master() to ensure that MEMCTRL will be written within 64 cycles of writing last word to INDATA as is mentioned in errata, even with different optimization levels.
[2.3.0]
Modified SHA_Update to use blocking version of AHB Master mode when its available on chip. Added SHA_UpdateNonBlocking() function which uses nonblocking AHB Master mode.
Fixed incorrect calculation of SHA when calling SHA_Update multiple times when is CPU used to load data.
Added Reset into SHA_ClkInit and SHA_ClkDeinit function.
[2.2.2]
Modified SHA_Finish function. While using pseudo DMA with maximum optimization, compiler optimize out condition. Which caused block in this function and did not check flag, which has been set in interrupt.
[2.2.1]
MISRA C-2012 issue fix.
[2.2.0]
Support MEMADDR pseudo DMA for loading input data in SHA_Update function (LPCXpresso54018 and LPCXpresso54628).
[2.1.1]
MISRA C-2012 issue fixed: rule 10.3, 10.4, 11.9, 14.4, 16.4 and 17.7.
[2.1.0]
Updated “sha_ldm_stm_16_words” “sha_one_block” API to match QN9090. QN9090 has no ALIAS register.
Added “SHA_ClkInit” “SHA_ClkInit”
[2.0.0]
Initial version.
SPI
[2.3.2]
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.1]
Improvements
Changed SPI_DUMMYDATA to 0x00.
[2.3.0]
Update version.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.2.1]
Bug Fixes
Fixed MISRA 2012 10.4 issue.
Added code to clear FIFOs before transfer using DMA.
[2.2.0]
Bug Fixes
Fixed bug that slave gets stuck during interrupt transfer.
[2.1.1]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.1, 5.7 issues.
[2.1.0]
Bug Fixes
Fixed Coverity issue of incrementing null pointer in SPI_TransferHandleIRQInternal.
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
New Features
Modified the definition of SPI_SSELPOL_MASK to support the socs that have only 3 SSEL pins.
[2.0.4]
Bug Fixes
Fixed the bug of using read only mode in DMA transfer. In DMA transfer mode, if transfer->txData is NULL, code attempts to read data from the address of 0x0 for configuring the last frame.
Fixed wrong assignment of handle->state. During transfer handle->state should be kSPI_Busy rather than kStatus_SPI_Busy.
Improvements
Rounded up the calculated divider value in SPI_MasterSetBaud.
[2.0.3]
Improvements
Added “SPI_FIFO_DEPTH(base)” with more definition.
[2.0.2]
Improvements
Unified the component full name to FLEXCOMM SPI(DMA/FREERTOS) driver.
[2.0.1]
Changed the data buffer from uint32_t to uint8_t which matches the real applications for SPI DMA driver.
Added dummy data setup API to allow users to configure the dummy data to be transferred.
Added new APIs for half-duplex transfer function. Users can not only send and receive data by one API in polling/interrupt/DMA way, but choose either to transmit first or to receive first. Besides, the PCS pin can be configured as assert status in transmission (between transmit and receive) by setting the isPcsAssertInTransfer to true.
[2.0.0]
Initial version.
SPI_DMA
[2.2.1]
Bug Fixes
Fixed MISRA 2012 11.6 issue..
[2.2.0]
Improvements
Supported dataSize larger than 1024 data transmit.
SPI Flash Interface
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.2]
Bug Fixes
Fixed the command function set issue. After the command being set, there will be no wait for the CMD flag, as it may have been cleared by CS deassert.
[2.0.1]
New Features
Added an API to read/write 1/2 Bytes data from/to SPIFI. This interface is useful for flash command, which only needs 1/2 Bytes data. The previous driver needed users to make sure of the minimum length being 4, which might cause issues in some flash commands.
[2.0.0]
Initial version.
USART
[2.8.5]
Bug Fixes
Fixed race condition during call of USART_EnableTxDMA and USART_EnableRxDMA.
[2.8.4]
Bug Fixes
Fixed exclusive access in USART_TransferReceiveNonBlocking and USART_TransferSendNonBlocking.
[2.8.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 11.8.
[2.8.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 14.2.
[2.8.1]
Bug Fixes
Fixed the Baud Rate Generator(BRG) configuration in 32kHz mode.
[2.8.0]
New Features
Added the rx timeout interrupts and status flags of bus status.
Added new rx timeout configuration item in usart_config_t.
Added API USART_SetRxTimeoutConfig for rx timeout configuration.
Improvements
When the calculated baudrate cannot meet user’s configuration, lower OSR value is allewed to use.
[2.7.0]
New Features
Added the missing interrupts and status flags of bus status.
Added the check of tx error, noise error framing error and parity error in interrupt handler.
[2.6.0]
Improvements
Used separate data for TX and RX in usart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling USART_TransferReceiveNonBlocking, the received data count returned by USART_TransferGetReceiveCount is wrong.
New Features
Added missing API USART_TransferGetSendCountDMA get send count using DMA.
[2.5.0]
New Features
Added APIs USART_GetRxFifoCount/USART_GetTxFifoCount to get rx/tx FIFO data count.
Added APIs USART_SetRxFifoWatermark/USART_SetTxFifoWatermark to set rx/tx FIFO water mark.
Bug Fixes
Fixed DMA transfer blocking issue by enabling tx idle interrupt after DMA transmission finishes.
[2.4.0]
New Features
Modified usart_config_t, USART_Init and USART_GetDefaultConfig APIs so that the hardware flow control can be enabled during module initialization.
Bug Fixes
Fixed MISRA 10.4 violation.
[2.3.1]
Bug Fixes
Fixed bug that operation on INTENSET, INTENCLR, FIFOINTENSET and FIFOINTENCLR should use bitwise operation not ‘or’ operation.
Fixed bug that if rx interrupt occurrs before TX interrupt is enabled and after txDataSize is configured, the data will be sent early by mistake, thus TX interrupt will be enabled after data is sent out.
Improvements
Added check for baud rate’s accuracy that returns kStatus_USART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
[2.3.0]
New Features
Added APIs to configure 9-bit data mode, set slave address and send address.
Modified USART_TransferReceiveNonBlocking and USART_TransferHandleIRQ to use 9-bit mode in multi-slave system.
[2.2.0]
New Features
Added the feature of supporting USART working at 32 kHz clocking mode.
Improvements
Modified USART_TransferHandleIRQ so that txState will be set to idle only when all data has been sent out to bus.
Modified USART_TransferGetSendCount so that this API returns the real byte count that USART has sent out rather than the software buffer status.
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.1 issues.
Fixed bug that operation on INTENSET, INTENCLR, FIFOINTENSET and FIFOINTENCLR should use bitwise operation not ‘or’ operation.
Fixed bug that if rx interrupt occurrs before TX interrupt is enabled and after txDataSize is configured, the data will be sent early by mistake, thus TX interrupt will be enabled after data is sent out.
[2.1.1]
Improvements
Added check for transmitter idle in USART_TransferHandleIRQ and USART_TransferSendDMACallback to ensure all the data would be sent out to bus.
Modified USART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.
Bug Fixes
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
[2.1.0]
New Features
Added features to allow users to configure the USART to synchronous transfer(master and slave) mode.
Bug Fixes
Modified USART_SetBaudRate to get more acurate configuration.
[2.0.3]
New Features
Added new APIs to allow users to enable the CTS which determines whether CTS is used for flow control.
[2.0.2]
Bug Fixes
Fixed the bug where transfer abort APIs could not disable the interrupts. The FIFOINTENSET register should not be used to disable the interrupts, so use the FIFOINTENCLR register instead.
[2.0.1]
Improvements
Unified the component full name to FLEXCOMM USART (DMA/FREERTOS) driver.
[2.0.0]
Initial version.
USART_DMA
[2.6.0]
Refer USART driver change log 2.0.1 to 2.6.0
UTICK
[2.0.5]
Improvements
Improved for SOC RW610.
[2.0.4]
Bug Fixes
Fixed compile fail issue of no-supporting PD configuration in utick driver.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 8.4, 14.4, 17.7
[2.0.2]
Added new feature definition macro to enable/disable power control in drivers for some devices have no power control function.
[2.0.1]
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
WWDT
[2.1.9]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 10.4.
[2.1.8]
Improvements
Updated the “WWDT_Init” API to add wait operation. Which can avoid the TV value read by CPU still be 0xFF (reset value) after WWDT_Init function returns.
[2.1.7]
Bug Fixes
Fixed the issue that the watchdog reset event affected the system from PMC.
Fixed the issue of setting watchdog WDPROTECT field without considering the backwards compatibility.
Fixed the issue of clearing bit fields by mistake in the function of WWDT_ClearStatusFlags.
[2.1.5]
Bug Fixes
deprecated a unusable API in WWWDT driver.
WWDT_Disable
[2.1.4]
Bug Fixes
Fixed violation of the MISRA C-2012 rules Rule 10.1, 10.3, 10.4 and 11.9.
Fixed the issue of the inseparable process interrupted by other interrupt source.
WWDT_Init
[2.1.3]
Bug Fixes
Fixed legacy issue when initializing the MOD register.
[2.1.2]
Improvements
Updated the “WWDT_ClearStatusFlags” API and “WWDT_GetStatusFlags” API to match QN9090. WDTOF is not set in case of WD reset. Get info from PMC instead.
[2.1.1]
New Features
Added new feature definition macro for devices which have no LCOK control bit in MOD register.
Implemented delay/retry in WWDT driver.
[2.1.0]
Improvements
Added new parameter in configuration when initializing WWDT module. This parameter, which must be set, allows the user to deliver the WWDT clock frequency.
[2.0.0]
Initial version.