MCUXpresso SDK Changelog

LPC_ACOMP

[2.1.0]

• Bug Fixes

  • Fixed one wrong enum value for the hysteresis.

  • Fixed the violations of MISRA C-2012 rules:

    • Rule 10.1, 17.7.

[2.0.2]

• Bug Fixes

  • Fixed the out-of-bounds error of Coverity caused by missing an assert sentence to avoid the return value of ACOMP_GetInstance() exceeding the array bounds.

[2.0.1]

• New Features

  • Added a control macro to enable/disable the CLOCK code in current driver.

[2.0.0]

• Initial version.

---

LPC_ADC

[2.6.0]

• New Features

  • Added new feature macro to distinguish whether the GPADC_CTRL0_GPADC_TSAMP control bit is on the device.

  • Added new variable extendSampleTimeNumber to indicate the ADC extend sample time.

• Bugfix

  • Fixed the bug that incorrectly sets the PASS_ENABLE bit based on the sample time setting.

[2.5.3]

• Improvements

  • Release peripheral from reset if necessary in init function.

[2.5.2]

• Improvements

  • Integrated different sequence’s sample time numbers into one variable.

• Bug Fixes

  • Fixed violation of MISRA C-2012 rule 20.9 .

[2.5.1]

• Bug Fixes

  • Fixed ADC conversion sequence priority misconfiguration issue in the ADC_SetConvSeqAHighPriority() and ADC_SetConvSeqBHighPriority() APIs.

• Improvements

  • Supported configuration ADC conversion sequence sampling time.

[2.5.0]

• Improvements

  • Add missing parameter tag of ADC_DoOffsetCalibration().

• Bug Fixes

  • Removed a duplicated API with typo in name: ADC_EnableShresholdCompareInterrupt().

[2.4.1]

• Bug Fixes

  • Enabled self-calibration after clock divider be changed to make sure the frequency update be taken.

[2.4.0]

• New Features

  • Added new API ADC_DoOffsetCalibration() which supports a specific operation frequency.

• Other Changes

  • Marked the ADC_DoSelfCalibration(ADC_Type *base) as deprecated.

• Bug Fixes

  • Fixed the violations of MISRA C-2012 rules:

    • Rule 10.1 10.3 10.4 10.7 10.8 17.7.

[2.3.2]

• Improvements

  • Added delay after enabling using the ADC GPADC_CTRL0 LDO_POWER_EN bit for JN5189/QN9090.

• New Features

  • Added support for platforms which have only one ADC sequence control/result register.

[2.3.1]

• Bug Fixes

  • Avoided writing ADC STARTUP register in ADC_Init().

  • Fixed Coverity zero divider error in ADC_DoSelfCalibration().

[2.3.0]

• Improvements

  • Updated “ADC_Init()””ADC_GetChannelConversionResult()” API and “adc_resolution_t” structure to match QN9090.

  • Added “ADC_EnableTemperatureSensor” API.

[2.2.1]

• Improvements

  • Added a brief delay in uSec after ADC calibration start.

[2.2.0]

• Improvements

  • Updated “ADC_DoSelfCalibration” API and “adc_config_t” structure to match LPC845.

[2.1.0]

• Improvements

  • Renamed “ADC_EnableShresholdCompareInterrupt” to “ADC_EnableThresholdCompareInterrupt”.

[2.0.0]

• Initial version.

---

CLOCK

[2.3.4]

• Improvements

  • Added CLOCK_SetFLASHAccessCyclesForFreq.

[2.3.3]

• Improvements

  • Added lost comments for some enumerations.

---

COMMON

[2.5.0]

• New Features

  • Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.

[2.4.3]

• Improvements

  • Enable irqs that mount under irqsteer interrupt extender.

[2.4.2]

• Improvements

  • Add the macros to convert peripheral address to secure address or non-secure address.

[2.4.1]

• Improvements

  • Improve for the macro redefinition error when integrated with zephyr.

[2.4.0]

• New Features

  • Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.

  • Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.

[2.3.3]

• New Features

  • Added NETC into status group.

[2.3.2]

• Improvements

  • Make driver aarch64 compatible

[2.3.1]

• Bug Fixes

  • Fixed MAKE_VERSION overflow on 16-bit platforms.

[2.3.0]

• Improvements

  • Split the driver to common part and CPU architecture related part.

[2.2.10]

• Bug Fixes

  • Fixed the ATOMIC macros build error in cpp files.

[2.2.9]

• Bug Fixes

  • Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.

  • Fixed SDK_Malloc issue that not allocate memory with required size.

[2.2.8]

• Improvements

  • Included stddef.h header file for MDK tool chain.

• New Features:

  • Added atomic modification macros.

[2.2.7]

• Other Change

  • Added MECC status group definition.

[2.2.6]

• Other Change

  • Added more status group definition.

• Bug Fixes

  • Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h

[2.2.5]

• Bug Fixes

  • Fixed MISRA C-2012 rule-15.5.

[2.2.4]

• Bug Fixes

  • Fixed MISRA C-2012 rule-10.4.

[2.2.3]

• New Features

  • Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.

  • Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.

[2.2.2]

• New Features

  • Added include RTE_Components.h for CMSIS pack RTE.

[2.2.1]

• Bug Fixes

  • Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.

[2.2.0]

• New Features

  • Moved SDK_DelayAtLeastUs function from clock driver to common driver.

[2.1.4]

• New Features

  • Added OTFAD into status group.

[2.1.3]

• Bug Fixes

  • MISRA C-2012 issue fixed.

    • Fixed the rule: rule-10.3.

[2.1.2]

• Improvements

  • Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.

[2.1.1]

• Bug Fixes

  • Deleted and optimized repeated macro.

[2.1.0]

• New Features

  • Added IRQ operation for XCC toolchain.

  • Added group IDs for newly supported drivers.

[2.0.2]

• Bug Fixes

  • MISRA C-2012 issue fixed.

    • Fixed the rule: rule-10.4.

[2.0.1]

• Improvements

  • Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.

  • Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.

  • Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.

[2.0.0]

• Initial version.

---

CRC

[2.1.1]

• Fix MISRA issue.

[2.1.0]

• Add CRC_WriteSeed function.

[2.0.2]

• Fix MISRA issue.

[2.0.1]

• Fixed KPSDK-13362. MDK compiler issue when writing to WR_DATA with -O3 optimize for time.

[2.0.0]

• Initial version.

---

LPC_DMA

[2.5.3]

• Improvements

  • Add assert in DMA_SetChannelXferConfig to prevent XFERCOUNT value overflow.

[2.5.2]

• Bug Fixes

  • Use separate “SET” and “CLR” registers to modify shared registers for all channels, in case of thread-safe issue.

[2.5.1]

• Bug Fixes

  • Fixed violation of the MISRA C-2012 rule 11.6.

[2.5.0]

• Improvements

  • Added a new api DMA_SetChannelXferConfig to set DMA xfer config.

[2.4.4]

• Bug Fixes

  • Fixed the issue that DMA_IRQHandle might generate redundant callbacks.

  • Fixed the issue that DMA driver cannot support channel bigger then 32.

  • Fixed violation of the MISRA C-2012 rule 13.5.

[2.4.3]

• Improvements

  • Added features FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn/FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE/FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE to support the descriptor align size not constant in the two instances.

[2.4.2]

• Bug Fixes

  • Fixed violation of the MISRA C-2012 rule 8.4.

[2.4.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 5.7, 8.3.

[2.4.0]

• Improvements

  • Added new APIs DMA_LoadChannelDescriptor/DMA_ChannelIsBusy to support polling transfer case.

• Bug Fixes

  • Added address alignment check for descriptor source and destination address.

  • Added DMA_ALLOCATE_DATA_TRANSFER_BUFFER for application buffer allocation.

  • Fixed the sign-compare warning.

  • Fixed violations of the MISRA C-2012 rules 18.1, 10.4, 11.6, 10.7, 14.4, 16.3, 20.7, 10.8, 16.1, 17.7, 10.3, 3.1, 18.1.

[2.3.0]

• Bug Fixes

  • Removed DMA_HandleIRQ prototype definition from header file.

  • Added DMA_IRQHandle prototype definition in header file.

[2.2.5]

• Improvements

  • Added new API DMA_SetupChannelDescriptor to support configuring wrap descriptor.

  • Added wrap support in function DMA_SubmitChannelTransfer.

[2.2.4]

• Bug Fixes

  • Fixed the issue that macro DMA_CHANNEL_CFER used wrong parameter to calculate DSTINC.

[2.2.3]

• Bug Fixes

  • Improved DMA driver Deinit function for correct logic order.

• Improvements

  • Added API DMA_SubmitChannelTransferParameter to support creating head descriptor directly.

  • Added API DMA_SubmitChannelDescriptor to support ping pong transfer.

  • Added macro DMA_ALLOCATE_HEAD_DESCRIPTOR/DMA_ALLOCATE_LINK_DESCRIPTOR to simplify DMA descriptor allocation.

[2.2.2]

• Bug Fixes

  • Do not use software trigger when hardware trigger is enabled.

[2.2.1]

• Bug Fixes

  • Fixed Coverity issue.

[2.2.0]

• Improvements

  • Changed API DMA_SetupDMADescriptor to non-static.

  • Marked APIs below as deprecated.

    • DMA_PrepareTransfer.

    • DMA_Submit transfer.

  • Added new APIs as below:

    • DMA_SetChannelConfig.

    • DMA_PrepareChannelTransfer.

    • DMA_InstallDescriptorMemory.

    • DMA_SubmitChannelTransfer.

    • DMA_SetChannelConfigValid.

    • DMA_DoChannelSoftwareTrigger.

    • DMA_LoadChannelTransferConfig.

[2.0.1]

• Improvements

  • Added volatile for DMA descriptor member xfercfg to avoid optimization.

[2.0.0]

• Initial version.

---

FTM

[2.7.0]

• Improvements

  • Support period dithering and edge dithering feature with new APIs:

    • FTM_SetPeriodDithering()

    • FTM_SetEdgeDithering()

  • Support get channel n output and input state feature with new APIs:

    • FTM_GetChannelOutputState()

    • FTM_GetChannelInputState()

  • Support configure deadtime for specific combined channel pair with new API:

    • FTM_SetPairDeadTime()

  • Support filter clock prescale, fault output state.

  • Support new APIs to configure PWM and Modified Combine PWM:

    • FTM_ConfigSinglePWM()

    • FTM_ConfigCombinePWM()

  • Support new API to configure channel software output control:

    • FTM_SetSoftwareOutputCtrl()

    • FTM_GetSoftwareOutputValue()

    • FTM_GetSoftwareOutputEnable()

  • Support new API to update FTM counter initial value, modulo value and chanle value:

    • FTM_SetInitialModuloValue()

    • FTM_SetChannelValue()

[2.6.1]

• Improvements

  • Release peripheral from reset if necessary in init function.

[2.6.0]

• Improvements

  • Added support to half and full cycle reload feature with new APIs:

    • FTM_SetLdok()

    • FTM_SetHalfCycPeriod()

    • FTM_LoadFreq()

• Bug Fixes

  • Set the HWRSTCNT and SWRSTCNT bits to optional at initialization.

[2.5.0]

• Improvements

  • Added FTM_CalculateCounterClkDiv to help calculates the counter clock prescaler.

  • Modify FTM_UpdatePwmDutycycle API to make it return pwm duty cycles status.

• Bug Fixes

  • Fixed TPM_SetupPwm can’t configure 100% center align combined PWM issues.

[2.4.1]

• Bug Fixes

  • Added function macro to determine if FTM instance has only basic features, to prevent access to protected register bits.

[2.4.0]

• Improvements

  • Added CNTIN register initialization in FTM_SetTimerPeriod API.

  • Added a new API to read the captured value of a FTM channel configured in capture mode:

    • FTM_GetInputCaptureValue()

[2.3.0]

• Improvements

  • Added support of EdgeAligned/CenterAligned/Asymmetrical combine PWM mode in FTM_SetupPWM() and FTM_SetupPwmMode() APIs.

  • Remove kFTM_ComplementaryPwm from support PWM mode, and add new parameter “enableComplementary” in structure ftm_chnl_pwm_signal_param_t.

  • Rename FTM_SetupFault() API to FTM_SetupFaultInput() to avoid ambiguity.

[2.2.3]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 14.4 and 17.7.

[2.2.2]

• Bug Fixes

  • Fixed the issue that when FTM instance has only TPM features cannot be initialized by FTM_Init() function. By added function macro to assert FTM is TPM only instance.

[2.2.1]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 10.1, 10.3, 10.4, 10.6, 10.7 and 11.9.

[2.2.0]

• Bug Fixes

  • Fixed the issue of comparison between signed and unsigned integer expressions.

• Improvements

  • Added support of complementary mode in FTM_SetupPWM() and FTM_SetupPwmMode() APIs.

  • Added new parameter “enableDeadtime” in structure ftm_chnl_pwm_signal_param_t.

[2.1.1]

• Bug Fixes

  • Fixed COVERITY integer handing issue where the right operand of a left bit shift statement should not be a negative value. This appears in FTM_SetReloadPoints().

[2.1.0]

• Improvements

  • Added a new API FTM_SetupPwmMode() to allow the user to set the channel match value in units of timer ticks. New configure structure called ftm_chnl_pwm_config_param_t was added to configure the channel’s PWM parameters. This API is similar with FTM_SetupPwm() API, but the new API will not set the timer period(MOD value), it will be useful for users to set the PWM parameters without changing the timer period.

• Bug Fixes

  • Added feature macro to enable/disable the external trigger source configuration.

[2.0.4]

• Improvements

  • Added a new API to enable DMA transfer:

    • FTM_EnableDmaTransfer()

[2.0.3]

• Bug Fixes

  • Updated the FTM driver to enable fault input after configuring polarity.

[2.0.2]

• Improvements

  • Added support to Quad Decoder feature with new APIs:

    • FTM_GetQuadDecoderFlags()

    • FTM_SetQuadDecoderModuloValue()

    • FTM_GetQuadDecoderCounterValue()

    • FTM_ClearQuadDecoderCounterValue()

[2.0.1]

• Bug Fixes

  • Updated the FTM driver to fix write to ELSA and ELSB bits.

  • FTM combine mode: set the COMBINE bit before writing to CnV register.

[2.0.0]

• Initial version.

---

GPIO

[2.1.7]

• Improvements

  • Enhanced GPIO_PinInit to enable clock internally.

[2.1.6]

• Bug Fixes

  • Clear bit before set it within GPIO_SetPinInterruptConfig() API.

[2.1.5]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 3.1, 10.6, 10.7, 17.7.

[2.1.4]

• Improvements

  • Added API GPIO_PortGetInterruptStatus to retrieve interrupt status for whole port.

  • Corrected typos in header file.

[2.1.3]

• Improvements

  • Updated “GPIO_PinInit” API. If it has DIRCLR and DIRSET registers, use them at set 1 or clean 0.

[2.1.2]

• Improvements

  • Removed deprecated APIs.

[2.1.1]

• Improvements

  • API interface changes:

    • Refined naming of APIs while keeping all original APIs, marking them as deprecated. Original APIs will be removed in next release. The mainin change is updating APIs with prefix of _PinXXX() and _PorortXXX

[2.1.0]

• New Features

  • Added GPIO initialize API.

[2.0.0]

• Initial version.

---

I2C

[2.1.0]

• Bug Fixes

  • Fixed MISRA 8.6 violations.

[2.0.4]

• Bug Fixes

  • Fixed wrong assignment for datasize in I2C_InitTransferStateMachineDMA.

  • Fixed wrong working flow in I2C_RunTransferStateMachineDMA to ensure master can work in no start flag and no stop flag mode.

  • Fixed wrong working flow in I2C_RunTransferStateMachine and added kReceiveDataBeginState in _i2c_transfer_states to ensure master can work in no start flag and no stop flag mode.

  • Fixed wrong handle state in I2C_MasterTransferDMAHandleIRQ. After all the data has been transfered or nak is returned, handle state should be changed to idle.

  • Eliminated IAR Pa082 warning in I2C_SlaveTransferHandleIRQ by assigning volatile variable to local variable and using local variable instead.

  • Fixed MISRA issues.

    • Fixed rules 4.7, 10.1, 10.3, 10.4, 11.1, 11.8, 14.4, 17.7.

• Improvements

  • Rounded up the calculated divider value in I2C_MasterSetBaudRate.

  • Updated the I2C_WAIT_TIMEOUT macro to unified name I2C_RETRY_TIMES.

[2.0.3]

• Bug Fixes

  • Fixed Coverity issue of unchecked return value in I2C_RTOS_Transfer.

[2.0.2]

• New Features

  • Added macro gate “FSL_SDK_ENABLE_I2C_DRIVER_TRANSACTIONAL_APIS” to enable/disable the transactional APIs which will help reduce the code size when no nonblocking transfer is used. Default configuration is enabled.

  • Added a control macro to enable/disable the RESET and CLOCK code in current driver.

[2.0.1]

• Improvements

  • Added I2C_WATI_TIMEOUT macro to allow the user to specify the timeout times for waiting flags in functional API and blocking transfer API.

[2.0.0]

• Initial version.

---

I3C

[2.13.1]

• Bug Fixes

  • Disabled Rx auto-termination in repeated start interrupt event while transfer API doesn’t enable it.

  • Waited the completion event after loading all Tx data in Tx FIFO.

• Improvements

  • Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.

[2.13.0]

• New features

  • Added the hot-join support for I3C bus initialization API.

• Bug Fixes

  • Set read termination with START at the same time in case unknown issue.

  • Set MCTRL[TYPE] as 0 for DDR force exit.

• Improvements

  • Added the API to reset device count assigned by ENTDAA.

  • Provided the method to set global macro I3C_MAX_DEVCNT to determine how many device addresses ENTDAA can allocate at one time.

  • Initialized target management static array based on instance number for the case that multiple instances are used at the same time.

[2.12.0]

• Improvements

  • Added the slow clock parameter for Controller initialization function to calculate accurate timeout.

• Bug Fixes

  • Fixed the issue that BAMATCH field can’t be 0. BAMATCH should be 1 for 1MHz slow clock.

[2.11.1]

• Bug Fixes

  • Fixed the issue that interrupt API transmits extra byte when subaddress and data size are null.

  • Fixed the slow clock calculation issue.

[2.11.0]

• New features

  • Added the START/ReSTART SCL delay setting for the Soc which supports this feature.

• Bug Fixes

  • Fixed the issue that ENTDAA process waits Rx pending flag which causes problem when Rx watermark isn’t 0. Just check the Rx FIFO count.

[2.10.8]

• Improvements

  • Support more instances.

[2.10.7]

• Improvements

  • Fixed the potential compile warning.

[2.10.6]

• New features

  • Added the I3C private read/write with 0x7E address as start.

[2.10.5]

• New features

  • Added I3C HDR-DDR transfer support.

[2.10.4]

• Improvements

  • Added one more option for master to not set RDTERM when doing I3C Common Command Code transfer.

[2.10.3]

• Improvements

  • Masked the slave IBI/MR/HJ request functions with feature macro.

[2.10.2]

• Bug Fixes

  • Added workaround for errata ERR051617: I3C working with I2C mode creates the unintended Repeated START before actual STOP on some platforms.

[2.10.1]

• Bug Fixes

  • Fixed the issue that DAA function doesn’t wait until all Rx data is read out from FIFO after master control done flag is set.

  • Fixed the issue that DAA function could return directly although the disabled interrupts are not enabled back.

[2.10.0]

• New features

  • Added I3C extended IBI data support.

[2.9.0]

• Improvements

  • Added adaptive termination for master blocking transfer. Set termination with start signal when receiving bytes less than 256.

[2.8.2]

• Improvements

  • Fixed the build warning due to armgcc strict check.

[2.8.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 17.7.

[2.8.0]

• Improvements

  • Added API I3C_MasterProcessDAASpecifiedBaudrate for temporary baud rate adjustment when I3C master assigns dynamic address.

[2.7.1]

• Bug Fixes

  • Fixed the issue that I3C slave handle STOP event before finishing data transmission.

[2.7.0]

• Fixed the CCM problem in file fsl_i3c.c.

• Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in I3C_GetDefaultConfig and I3C_Init.

[2.6.0]

• Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in fsl_i3c.h.

• Changed some static functions in fsl_i3c.c as non-static and define the functions in fsl_i3c.h to make I3C DMA driver reuse:

  • I3C_GetIBIType

  • I3C_GetIBIAddress

  • I3C_SlaveCheckAndClearError

• Changed the handle pointer parameter in IRQ related funtions to void * type to make it reuse in I3C DMA driver.

• Added new API I3C_SlaveRequestIBIWithSingleData for slave to request single data byte, this API could be used regardless slave is working in non-blocking interrupt or non-blocking dma.

• Added new API I3C_MasterGetDeviceListAfterDAA for master application to get the device information list built up in DAA process.

[2.5.4]

• Improved I3C driver to avoid setting state twice in the SendCommandState of I3C_RunTransferStateMachine.

• Fixed MISRA violation of rule 20.9.

• Fixed the issue that I3C_MasterEmitRequest did not use Type I3C SDR.

[2.5.3]

• Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH and FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND.

[2.5.2]

• Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM.

• Fixed the issue that call to I3C_MasterTransferBlocking API did not generate STOP signal when NAK status was returned.

[2.5.1]

• Improved the receive terminate size setting for interrupt transfer read, now it’s set at beginning of transfer if the receive size is less than 256 bytes.

[2.5.0]

• Added new API I3C_MasterRepeatedStartWithRxSize to send repeated start signal with receive terminate size specified.

• Fixed the status used in I3C_RunTransferStateMachine, changed to use pending interrupts as status to be handled in the state machine.

• Fixed MISRA 2012 violation of rule 10.3, 10.7.

[2.4.0]

• Bug Fixes

  • Fixed kI3C_SlaveMatchedFlag interrupt is not properly handled in I3C_SlaveTransferHandleIRQ when it comes together with interrupt kI3C_SlaveBusStartFlag.

  • Fixed the inaccurate I2C baudrate calculation in I3C_MasterSetBaudRate.

  • Added new API I3C_MasterGetIBIRules to get registered IBI rules.

  • Added new variable isReadTerm in struct _i3c_master_handle for transfer state routine to check if MCTRL.RDTERM is configured for read transfer.

  • Changed to emit Auto IBI in transfer state routine for slave start flag assertion.

  • Fixed the slave maxWriteLength and maxReadLength does not be configured into SMAXLIMITS register issue.

  • Fixed incorrect state for IBI in I3C master interrupt transfer IRQ handle routine.

  • Added isHotJoin in i3c_slave_config_t to request hot-join event during slave init.

[2.3.2]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 8.4, 17.7.

  • Fixed incorrect HotJoin event index in I3C_GetIBIType.

[2.3.1]

• Bug Fixes

  • Fixed the issue that call of I3C_MasterTransferBlocking/I3C_MasterTransferNonBlocking fails for the case which receive length 1 byte of data.

  • Fixed the issue that STOP signal is not sent when NAK status is detected during execution of I3C_MasterTransferBlocking function.

[2.3.0]

• Improvements

  • Added I3C common driver APIs to initialize I3C with both master and slave configuration.

  • Updated I3C master transfer callback to function set structure to include callback invoke for IBI event and slave2master event.

  • Updated I3C master non-blocking transfer model and always enable the interrupts to be able to re-act to the slave start event and handle slave IBI.

[2.2.0]

• Bug Fixes

  • Fixed the issue that I3C transfer size limit to 255 bytes.

[2.1.2]

• Bug Fixes

  • Reset default hkeep value to kI3C_MasterHighKeeperNone in I3C_MasterGetDefaultConfig

[2.1.1]

• Bug Fixes

  • Fixed incorrect FIFO reset operation in I3C Master Transfer APIs.

  • Fixed i3c slave IRQ handler issue, slave transmit could be underrun because tx FIFO is not filled in time right after start flag detected.

[2.1.0]

• Added definitions and APIs for I3C slave functionality, updated previous I3C APIs to support I3C functionality.

[2.0.0]

• Initial version.

---

I3C_DMA

[2.1.8]

• Bug Fixes

  • Updated the logic to handle Rx termination and complete event to adapt different situation.

• Improvements

  • Added the MCTRLDONE flag check after STOP request to ensure the completion of whole transfer operation.

[2.1.7]

• Bug Fixes

  • Fixed the issue to use subaddress to read/write data with RT500/600 DMA.

[2.1.6]

• Improvements

  • Added the FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG to select the correct register to write data based on specific Soc.

[2.1.5]

• New features

  • Supported I3C HDR-DDR transfer with DMA.

• Improvements

  • Added workaround for RT500/600 I3C DMA transfer.

  • Removed I3C IRQ handler calling in the Tx EDMA callback. Previously driver doesn’t use the END byte which can trigger the complete interrupt for controller sending and receiving, now let I3C event handler deal with I3C events.

  • Used linked DMA to transfer all I3C subaddress and data without handling of intermediate states, simplifying code logic.

  • Prepare the Tx DMA before I3C START to ensure there’s no time delay between START and transmitting data.

[2.1.4]

• Improvements

  • Used linked DMA transfer to reduce the latency between DMA transfers previous data and the END byte.

[2.1.3]

• Bug Fixes

  • Fixed the MISRA issue rule 10.4, 11.3.

[2.1.2]

• Bug Fixes

  • Fixed the issue that I3C slave send the last byte data without using the END type register.

[2.1.1]

• Bug Fixes

  • Fixed MISRA issue rule 9.1.

[2.1.0]

• Improvements

  • Deleted legacy IBI data request code.

[2.0.1]

• Bug Fixes

  • Fixed issue that bus STOP occurs when Tx FIFO still takes data.

• Improvements

  • Fixed the build warning due to armgcc strict check.

[2.0.0]

• Initial version.

---

IAP

[2.0.7]

• Bug Fixes

  • Fixed IAP_ReinvokeISP bug that can’t support UART ISP auto baud detection.

[2.0.6]

• Bug Fixes

  • Fixed IAP_ReinvokeISP wrong parameter setting.

[2.0.5]

• New Feature

  • Added support config flash memory access time.

[2.0.4]

• Bug Fixes

  • Fixed the violations of MISRA 2012 rules 9.1

[2.0.3]

• New Features

  • Added support for LPC 845’s FAIM operation.

  • Added support for LPC 80x’s fixed reference clock for flash controller.

  • Added support for LPC 5411x’s Read UID command useless situation.

• Improvements

  • Improved the document and code structure.

• Bug Fixes

  • Fixed the violations of MISRA 2012 rules:

    • Rule 10.1 10.3 10.4 17.7

[2.0.2]

• New Features

  • Added an API to read generated signature.

• Bug Fixes

  • Fixed the incorrect board support of IAP_ExtendedFlashSignatureRead().

[2.0.1]

• New Features

  • Added an API to read factory settings for some calibration registers.

• Improvements

  • Updated the size of result array in part APIs.

[2.0.0]

• Initial version.

---

INPUTMUX

[2.0.8]

• Improvements

  • Updated a feature macro usage for function INPUTMUX_EnableSignal.

[2.0.7]

• Improvements

  • Release peripheral from reset if necessary in init function.

[2.0.6]

• Bug Fixes

  • Fixed the documentation wrong in API INPUTMUX_AttachSignal.

[2.0.5]

• Bug Fixes

  • Fixed build error because some devices has no sct.

[2.0.4]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rule 10.4, 12.2 in INPUTMUX_EnableSignal() function.

[2.0.3]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.4, 10.7, 12.2.

[2.0.2]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.4, 12.2.

[2.0.1]

• Support channel mux setting in INPUTMUX_EnableSignal().

[2.0.0]

• Initial version.

---

IOCON

[2.0.2]

• Bug Fixes

  • Fixed MISRA-C 2012 violations.

[2.0.1]

• Bug Fixes

  • Fixed out-of-range issue of the IOCON mode function when enabling DAC.

[2.0.0]

• Initial version.

---

MRT

[2.0.4]

• Improvements

  • Don’t reset MRT when there is not system level MRT reset functions.

[2.0.3]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 10.1 and 10.4.

  • Fixed the wrong count value assertion in MRT_StartTimer API.

[2.0.2]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 10.4.

[2.0.1]

• Added control macro to enable/disable the RESET and CLOCK code in current driver.

[2.0.0]

• Initial version.

---

PINT

[2.1.13]

• Improvements

  • Added instance array for PINT to adapt more devices.

  • Used release reset instead of reset PINT which may clear other related registers out of PINT.

[2.1.12]

• Bug Fixes

  • Fixed coverity issue.

[2.1.11]

• Bug Fixes

  • Fixed MISRA C-2012 rule 10.7 violation.

[2.1.10]

• New Features

  • Added the driver support for MCXN10 platform with combined interrupt handler.

[2.1.9]

• Bug Fixes

  • Fixed MISRA-2012 rule 8.4.

[2.1.8]

• Bug Fixes

  • Fixed MISRA-2012 rule 10.1 rule 10.4 rule 10.8 rule 18.1 rule 20.9.

[2.1.7]

• Improvements

  • Added fully support for the SECPINT, making it can be used just like PINT.

[2.1.6]

• Bug Fixes

  • Fixed the bug of not enabling common pint clock when enabling security pint clock.

[2.1.5]

• Bug Fixes

  • Fixed issue for MISRA-2012 check.

    • Fixed rule 10.1 rule 10.3 rule 10.4 rule 10.8 rule 14.4.

  • Changed interrupt init order to make pin interrupt configuration more reasonable.

[2.1.4]

• Improvements

  • Added feature to control distinguish PINT/SECPINT relevant interrupt/clock configurations for PINT_Init and PINT_Deinit API.

  • Swapped the order of clearing PIN interrupt status flag and clearing pending NVIC interrupt in PINT_EnableCallback and PINT_EnableCallbackByIndex function.

  • Bug Fixes

    • Fixed build issue caused by incorrect macro definitions.

[2.1.3]

• Bug fix:

  • Updated PINT_PinInterruptClrStatus to clear PINT interrupt status when the bit is asserted and check whether was triggered by edge-sensitive mode.

  • Write 1 to IST corresponding bit will clear interrupt status only in edge-sensitive mode and will switch the active level for this pin in level-sensitive mode.

  • Fixed MISRA c-2012 rule 10.1, rule 10.6, rule 10.7.

  • Added FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS to distinguish IRQ relevant array definitions for SECPINT/PINT on lpc55s69 board.

  • Fixed PINT driver c++ build error and remove index offset operation.

[2.1.2]

• Improvement:

  • Improved way of initialization for SECPINT/PINT in PINT_Init API.

[2.1.1]

• Improvement:

  • Enabled secure pint interrupt and add secure interrupt handle.

[2.1.0]

• Added PINT_EnableCallbackByIndex/PINT_DisableCallbackByIndex APIs to enable/disable callback by index.

[2.0.2]

• Added control macro to enable/disable the RESET and CLOCK code in current driver.

[2.0.1]

• Bug fix:

  • Updated PINT driver to clear interrupt only in Edge sensitive.

[2.0.0]

• Initial version.

---

POWER

[2.1.0]

• initial version.

---

RESET

[2.4.0]

• Improvements

  • Add RESET_ReleasePeripheralReset API.

[2.0.0]

• initial version.

---

SPI

[2.0.7]

• Bug Fixes

  • Fixed the txData from void * to const void * in transmit API.

[2.0.6]

• Improvements

  • Changed SPI_DUMMYDATA to 0x00.

[2.0.5]

• Bug Fixes

  • Fixed bug that the transfer configuration does not take effect after the first transfer.

[2.0.4]

• Bug Fixes

  • Fixed the issue that when transfer finish callback is invoked TX data is not sent to bus yet.

[2.0.3]

• Improvements

  • Added timeout mechanism when waiting certain states in transfer driver.

  • Fixed MISRA 10.4 issue.

[2.0.2]

• Bug Fixes

  • Fixed Coverity issue of incrementing null pointer in SPI_MasterTransferNonBlocking.

  • Fixed MISRA issues.

    • Fixed rules 10.1, 10.3, 10.4, 10.6, 14.4.

• New Features

  • Added enumeration for dataWidth.

[2.0.1]

• Bug Fixes

  • Added wait mechanism in SPI_MasterTransferBlocking() API, which checks if master SPI becomes IDLE when the EOT bit is set before returning. This confirms that all data will be sent out by SPI master.

  • Fixed the bug that the EOT bit couldn’t be set when only one frame was sent in polling mode and interrupt transfer mode.

• New Features

  • Added macro gate “FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS” to enable/disable the transactional APIs, which helps reduce the code size when no nonblocking transfer is used. Enabled default configuration.

  • Added a control macro to enable/disable the RESET and CLOCK code in current driver.

[2.0.0]

• Initial version.

---

SWM

[2.1.2]

• Improvements

  • Reduce RAM footprint.

[2.1.1]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 10.1 and 10.3.

[2.1.0]

• New Features

  • Supported Flextimer function pin assign.

[2.0.2]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 14.3.

[2.0.1]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 10.1, 10.3, and 10.4.

[2.0.0]

• Initial version.

• The API SWM_SetFixedMovablePinSelect() is targeted at the device that has PINASSIGNFIXED0 register, such as LPC804.

---

SYSCON

[2.0.1]

• Bug Fixes

  • Fixed issue for MISRA-2012 check.

    • Fixed rule 10.4.

[2.0.0]

• Initial version.

---

USART

[2.5.1]

• Improvements

  • Fixed doxygen warning in USART_SetRxIdleTimeout.

[2.5.0]

• New Features

  • Supported new feature of rx idle timeout.

[2.4.0]

• Improvements

  • Used separate data for TX and RX in usart_transfer_t.

• Bug Fixes

  • Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling USART_TransferReceiveNonBlocking, the received data count returned by USART_TransferGetReceiveCount is wrong.

[2.3.0]

• New Features

  • Modified usart_config_t, USART_Init and USART_GetDefaultConfig APIs so that the hardware flow control can be enabled during module initialization.

[2.2.0]

• Improvements

  • Added timeout mechanism when waiting for certain states in transfer driver.

  • Fixed MISRA 10.4 issues.

[2.1.1]

• Bug Fixes

  • Fixed the bug that in USART_SetBaudRate best_diff rather than diff should be used to compare with calculated baudrate.

  • Eliminated IAR pa082 warnings from USART_TransferGetRxRingBufferLength and USART_TransferHandleIRQ.

  • Fixed MISRA issues.

• Improvements

  • Rounded up the calculated sbr value in USART_SetBaudRate to achieve more acurate baudrate setting.

  • Modified USART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.

[2.1.0]

• New Features

  • Added new APIs to allow users to configure the USART continuous SCLK feature in synchronous mode transfer.

[2.0.1]

• Bug Fixes

  • Fixed the repeated reading issue of the STAT register while dealing with the IRQ routine.

• New Features

  • Added macro gate “FSL_SDK_ENABLE_USART_DRIVER_TRANSACTIONAL_APIS” to enable/disable the transactional APIs, which helps reduce the code size when no nonblocking transfer is used. Enabled default configuration.

  • Added a control macro to enable/disable the RESET and CLOCK code in current driver.

  • Added macro switch gate “FSL_SDK_USART_DRIVER_ENABLE_BAUDRATE_AUTO_GENERATE” to enable/disable the baud rate to generate automatically. Disabling this feature will help reduce the code size to a certain degree. Default configuration enables auto generating of baud rate.

  • Added the check of baud rate while initializing the USART. If the baud rate calculated is not precise, the software assertion will be triggered.

  • Added a new API to allow users to enable the CTS, which determines whether CTS is used for flow control.

[2.0.0]

• Initial version.

---

WKT

[2.0.2]

• Bug Fixes

  • Fixed violation of MISRA C-2012 rule 10.3.

[2.0.1]

• New Features

  • Added control macro to enable/disable the RESET and CLOCK code in current driver.

[2.0.0]

• Initial version.

---

WWDT

[2.1.9]

• Bug Fixes

  • Fixed violation of the MISRA C-2012 rule 10.4.

[2.1.8]

• Improvements

  • Updated the “WWDT_Init” API to add wait operation. Which can avoid the TV value read by CPU still be 0xFF (reset value) after WWDT_Init function returns.

[2.1.7]

• Bug Fixes

  • Fixed the issue that the watchdog reset event affected the system from PMC.

  • Fixed the issue of setting watchdog WDPROTECT field without considering the backwards compatibility.

  • Fixed the issue of clearing bit fields by mistake in the function of WWDT_ClearStatusFlags.

[2.1.5]

• Bug Fixes

  • deprecated a unusable API in WWWDT driver.

    • WWDT_Disable

[2.1.4]

• Bug Fixes

  • Fixed violation of the MISRA C-2012 rules Rule 10.1, 10.3, 10.4 and 11.9.

  • Fixed the issue of the inseparable process interrupted by other interrupt source.

    • WWDT_Init

[2.1.3]

• Bug Fixes

  • Fixed legacy issue when initializing the MOD register.

[2.1.2]

• Improvements

  • Updated the “WWDT_ClearStatusFlags” API and “WWDT_GetStatusFlags” API to match QN9090. WDTOF is not set in case of WD reset. Get info from PMC instead.

[2.1.1]

• New Features

  • Added new feature definition macro for devices which have no LCOK control bit in MOD register.

  • Implemented delay/retry in WWDT driver.

[2.1.0]

• Improvements

  • Added new parameter in configuration when initializing WWDT module. This parameter, which must be set, allows the user to deliver the WWDT clock frequency.

[2.0.0]

• Initial version.

---