MCUXpresso SDK Changelog
CACHE64
[2.0.9]
Improvements
Removed assert(false) in CACHE64_GetInstanceByAddr.
[2.0.8]
Improvements
Updated function CACHE64_GetInstanceByAddr() to support some devices that provide alias of cacheable memory section.
[2.0.7]
Improvements
Check input parameter “size_byte” must be larger than 0.
[2.0.6]
Bug Fixes
Fixed overflow for CACHE64_GetInstanceByAddr()/CACHE64_CleanCacheByRange()/CACHE64_InvalidateCacheByRange() APIs.
[2.0.5]
Improvement
Made use of FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF feature
[2.0.4]
Improvement
Disable cache policy feature on SoC without CACHE64_POLSEL IP.
Bug Fixes
Fixed doxygen issue.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4 and 14.4.
Fixed doxygen issue.
[2.0.1]
Improvements
Moved CLCR register configuration out of the while loop, it’s unnecessary to repeat this operation.
[2.0.0]
Initial version.
CACHE LPCAC
[2.1.1]
Bug Fixes
Fixed an issue of L1CACHE_InvalidateCodeCache() function, to clean cache the LPCAC_CTRL[CLR_LPCAC] should be set not clear.
[2.1.0]
Improvements
Supported more features, such as write buffer contron, write buffer limit and so on.
[2.0.0]
Initial version.
CDOG
[2.1.3]
Re-design multiple instance IRQs and Clocks
Add fix for RESTART command errata
[2.1.2]
Support multiple IRQs
Fix default CONTROL values
[2.1.1]
Remove bit CONTROL[CONTROL_CTRL].
[2.1.0]
Rename CWT to CDOG.
[2.0.2]
Fix MISRA-2012 issues.
[2.0.1]
Fix doxygen issues.
[2.0.0]
Initial version.
CLOCK
[1.0.1]
Improvements
Added Clock ip name array for SINC.
[1.0.0]
initial version.
MCX_CMC
[2.2.3]
Improvements
Clear SCB SCR[SLEEPDEEP] bitfield after wakeup.
[2.2.2]
Improvements
Fixed the violation of MISRA C-2012 rules.
[2.2.1]
Improvements
Updated _cmc_system_reset_interrupt_enable, _cmc_system_reset_interrupt_flag and _cmc_system_reset_sources to support new added bit field.
Bug Fixes
Fixed issue in CMC_PowerOffSRAMAllMode() and CMC_PowerOffSRAMLowPowerOnly() which overwrite reserved bit fields.
[2.2.0]
Improvements
Added feature macro “FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE” to support some devices where FLASHCR[WAKE] is reserved.
[2.1.0]
Improvements
Added macros to support some devices(such as MCXA family) that only support one power domain.
[2.0.0]
Initial version.
COMMON
[2.5.0]
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]
New Features
Added NETC into status group.
[2.3.2]
Improvements
Make driver aarch64 compatible
[2.3.1]
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]
Other Change
Added MECC status group definition.
[2.2.6]
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]
New Features
Added OTFAD into status group.
[2.1.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]
Initial version.
CRC
[2.0.4]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]
Bug fix:
Fix MISRA issues.
[2.0.2]
Bug fix:
Fix MISRA issues.
[2.0.1]
Bug fix:
DATA and DATALL macro definition moved from header file to source file.
[2.0.0]
Initial version.
CTIMER
[2.3.3]
Bug Fixes
Fix CERT INT30-C INT31-C issue.
Make API CTIMER_SetupPwm and CTIMER_UpdatePwmDutycycle return fail if pulse width register overflow.
[2.3.2]
Bug Fixes
Clear unexpected DMA request generated by RESET_PeripheralReset in API CTIMER_Init to avoid trigger DMA by mistake.
[2.3.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.7 and 12.2.
[2.3.0]
Improvements
Added the CTIMER_SetPrescale(), CTIMER_GetCaptureValue(), CTIMER_EnableResetMatchChannel(), CTIMER_EnableStopMatchChannel(), CTIMER_EnableRisingEdgeCapture(), CTIMER_EnableFallingEdgeCapture(), CTIMER_SetShadowValue(),APIs Interface to reduce code complexity.
[2.2.2]
Bug Fixes
Fixed SetupPwm() API only can use match 3 as period channel issue.
[2.2.1]
Bug Fixes
Fixed use specified channel to setting the PWM period in SetupPwmPeriod() API.
Fixed Coverity Out-of-bounds issue.
[2.2.0]
Improvements
Updated three API Interface to support Users to flexibly configure the PWM period and PWM output.
Bug Fixes
MISRA C-2012 issue fixed: rule 8.4.
[2.1.0]
Improvements
Added the CTIMER_GetOutputMatchStatus() API Interface.
Added feature macro for FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 and FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7 and 11.9.
[2.0.2]
New Features
Added new API “CTIMER_GetTimerCountValue” to get the current timer count value.
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
Added a new feature macro to update the API of CTimer driver for lpc8n04.
[2.0.1]
Improvements
API Interface Change
Changed API interface by adding CTIMER_SetupPwmPeriod API and CTIMER_UpdatePwmPulsePeriod API, which both can set up the right PWM with high resolution.
[2.0.0]
Initial version.
DAC
[2.1.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.1.0]
New Features
Added support for period trigger mode.
Added support for sync trigger between dac instances.
Added support for configuring DAC sync cycles.
Added support for internal reference current selection.
Enabled buffer mode manually for K4 series board.
[2.0.2]
Bug Fixes
Fixed MISRA C-2012 rule 10.3 and rule 17.7.
[2.0.1]
New Features
Added a control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
EDMA
[2.10.5]
Bug Fixes
Fixed memory convert would convert NULL as zero address issue.
[2.10.4]
Improvements
Add new MP register macros to ensure compatibility with different devices.
Add macro DMA_CHANNEL_ARRAY_STEPn to adapt to complex addressing of edma tcd registers.
[2.10.3]
Bug Fixes
Clear interrupt status flags in EDMA_CreateHandle to avoid triggering interrupt by mistake.
[2.10.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.10.1]
Bug Fixes
Fixed EDMA_GetRemainingMajorLoopCount may return wrong value issue.
Fixed violations of the MISRA C-2012 rules 13.5, 10.4.
[2.10.0]
Improvements
Modify the structures edma_core_mp_t, edma_core_channel_t, edma_core_tcd_t to adapt to edma5.
Add TCD register macro to facilitate confirmation of tcd type.
Modfiy the mask macro to a fixed value.
Add EDMA_TCD_TYPE macro to determine edma tcd type.
Add extension API to the following API to determine edma tcd type.
EDMA_ConfigChannelSoftwareTCD -> EDMA_ConfigChannelSoftwareTCDExt
EDMA_TcdReset -> EDMA_TcdResetExt
EDMA_TcdSetTransferConfig -> EDMA_TcdSetTransferConfigExt
EDMA_TcdSetMinorOffsetConfig -> EDMA_TcdSetMinorOffsetConfigExt
EDMA_TcdSetChannelLink -> EDMA_TcdSetChannelLinkExt
EDMA_TcdSetBandWidth -> EDMA_TcdSetBandWidthExt
EDMA_TcdSetModulo -> EDMA_TcdSetModuloExt
EDMA_TcdEnableAutoStopRequest -> EDMA_TcdEnableAutoStopRequestExt
EDMA_TcdEnableInterrupts -> EDMA_TcdEnableInterruptsExt
EDMA_TcdDisableInterrupts -> EDMA_TcdDisableInterruptsExt
EDMA_TcdSetMajorOffsetConfig -> EDMA_TcdSetMajorOffsetConfigExt
[2.9.2]
Improvements
Remove tcd alignment check in API that is low level and does not necessarily use scather/gather mode.
[2.9.1]
Bug Fixes
Deinit channel request source before set channel mux.
[2.9.0]
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed the variable type definition error issue.
Fixed doxygen warning.
Fixed violations of MISRA C-2012 rule 18.1.
[2.8.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3
[2.8.0]
Improvements
Added feature FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC to separate DMA without SEC bitfield.
[2.7.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, 10.4, 11.6, 11.8, 14.3,.
[2.7.0]
Improvements
Use more accurate DMA instance based feature macros.
New Features
Add new APIs EDMA_PrepareTransferTCD and EDMA_SubmitTransferTCD, which support EDMA transfer using TCD.
[2.6.0]
Improvements
Modify the type of parameter channelRequestSource from dma_request_source_t to int32_t in the EDMA_SetChannelMux.
[2.5.3]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, 10.4, 11.6, 20.7, 12.2, 20.9, 5.3, 10.8, 8.4, 9.3.
[2.5.2]
Improvements
Applied ERRATA 51327.
[2.5.1]
Bug Fixes
Fixed the EDMA_ResetChannel function cannot reset channel DONE/ERROR status.
[2.5.0]
Improvements
Added feature FSL_FEATURE_EDMA_HAS_NO_SBR_ATTR_BIT to separate DMA without ATTR bitfield.
Added api EDMA_GetChannelSystemBusInformation to gets the channel identification and attribute information on the system bus interface.
Bug Fixes
Fixed the ESG bit not set in scatter gather mode issue.
Fixed the DREQ bit configuration missed in single transfer issue.
Cleared the interrupt status before invoke callback to avoid miss interrupt issue.
Removed disableRequestAfterMajorLoopComplete from edma_transfer_config_t structure as driver will handle it.
Fixed the channel mux configuration not compatible issue.
Fixed the out of bound access in function EDMA_DriverIRQHandler.
[2.4.4]
Bug Fixes
Fixed comments by replacing STCD with TCD
Fixed the TCD overwrite issue when submit transfer request in the callback if there is a active TCD in hardware.
[2.4.3]
Improvements
Added FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET to convert the address between system mapped address and dma quick access address.
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt for the non scatter gather case.
[2.4.2]
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt by correct the initial value of the header.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.4.1]
Bug Fixes
Added clear CITER and BITER registers in EDMA_AbortTransfer to make sure the TCD registers in a correct state for next calling of EDMA_SubmitTransfer.
Removed the clear DONE status for ESG not enabled case to aovid DONE bit cleared unexpectedly.
[2.4.0]
Improvements
Added api EDMA_EnableContinuousChannelLinkMode to support continuous link mode.
Added apis EDMA_SetMajorOffsetConfig/EDMA_TcdSetMajorOffsetConfig to support major loop address offset feature.
Added api EDMA_EnableChannelMinorLoopMapping for minor loop offset feature.
Removed the reduntant IRQ Handler in edma driver.
[2.3.2]
Improvements
Fixed HIS ccm issue in function EDMA_PrepareTransferConfig.
Fixed violations of MISRA C-2012 rule 11.6, 10.7, 10.3, 18.1.
Bug Fixes
Added ACTIVE & BITER & CITER bitfields to determine the channel status to fixed the issue of the transfer request cannot submit by function EDMA_SubmitTransfer when channel is idle.
[2.3.1]
Improvements
Added source/destination address alignment check.
Added driver IRQ handler support for multi DMA instance in one SOC.
[2.3.0]
Improvements
Added new api EDMA_PrepareTransferConfig to allow different configurations of width and offset.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4, 10.1.
Fixed the Coverity issue regarding out-of-bounds write.
[2.2.0]
Improvements
Added peripheral-to-peripheral support in EDMA driver.
[2.1.9]
Bug Fixes
Fixed MISRA issue: Rule 10.7 and 10.8 in function EDMA_DisableChannelInterrupts and EDMA_SubmitTransfer.
Fixed MISRA issue: Rule 10.7 in function EDMA_EnableAsyncRequest.
[2.1.8]
Bug Fixes
Fixed incorrect channel preemption base address used in EDMA_SetChannelPreemptionConfig API which causes incorrect configuration of the channel preemption register.
[2.1.7]
Bug Fixes
Fixed incorrect transfer size setting.
Added 8 bytes transfer configuration and feature for RT series;
Added feature to support 16 bytes transfer for Kinetis.
Fixed the issue that EDMA_HandleIRQ would go to incorrect branch when TCD was not used and callback function not registered.
[2.1.6]
Bug Fixes
Fixed KW3X MISRA Issue.
Rule 14.4, 10.8, 10.4, 10.7, 10.1, 10.3, 13.5, and 13.2.
Improvements
Cleared the IRQ handler unavailable for specific platform with macro FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET.
[2.1.5]
Improvements
Improved EDMA IRQ handler to support half interrupt feature.
[2.1.4]
Bug Fixes
Cleared enabled request, status during EDMA_Init for the case that EDMA is halted before reinitialization.
[2.1.3]
Bug Fixes
Added clear DONE bit in IRQ handler to avoid overwrite TCD issue.
Optimized above solution for the case that transfer request occurs in callback.
[2.1.2]
Improvements
Added interface to get next TCD address.
Added interface to get the unused TCD number.
[2.1.1]
Improvements
Added documentation for eDMA data flow when scatter/gather is implemented for the EDMA_HandleIRQ API.
Updated and corrected some related comments in the EDMA_HandleIRQ API and edma_handle_t struct.
[2.1.0]
Improvements
Changed the EDMA_GetRemainingBytes API into EDMA_GetRemainingMajorLoopCount due to eDMA IP limitation (see API comments/note for further details).
[2.0.5]
Improvements
Added pubweak DriverIRQHandler for K32H844P (16 channels shared).
[2.0.4]
Improvements
Added support for SoCs with multiple eDMA instances.
Added pubweak DriverIRQHandler for KL28T DMA1 and MCIMX7U5_M4.
[2.0.3]
Bug Fixes
Fixed the incorrect pubweak IRQHandler name issue, which caused re-definition build errors when client set his/her own IRQHandler, by changing the 32-channel IRQHandler name to DriverIRQHandler.
[2.0.2]
Bug Fixes
Fixed incorrect minorLoopBytes type definition in _edma_transfer_config struct, and defined minorLoopBytes as uint32_t instead of uint16_t.
[2.0.1]
Bug Fixes
Fixed the eDMA callback issue (which did not check valid status) in EDMA_HandleIRQ API.
[2.0.0]
Initial version.
EDMA_SOC
[1.0.0]
Initial version.
EIM
[2.0.1]
Improvements
Update driver to support fewer channel.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3.
[2.0.0]
Initial version.
MCX_ENET
[2.1.4]
Bug Fixes
Fixed ENET_GetMacAddr address byte order not matching ENET_SetMacAddr.
[2.1.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.6.
[2.1.2]
New features
Added hardware checksum acceleration support.
[2.1.1]
Bug Fixes
Fixed the issue that free wrong buffer address when one frame stores in multiple buffers and memory pool is not enough to allocate these buffers to receive one complete frame.
Fixed the issue that ENET_DropFrame checks the buffer descriptor flag after it has been re-initialized.
Fixed the ENET_GetRxFrame FCS calculation issue.
Fixed the issue that there’s no valid error type in the return structure when Rx error bit is set.
[2.1.0]
New Features
Added the VLAN control setting APIs in the driver.
[2.0.1]
Bug Fixes
Fixed the issue that enable/disable interrupt APIs miss part of configuration.
[2.0.0]
Initial version.
ERM
[2.0.1]
Improvements
Update driver to support fewer channel.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3.
[2.0.0]
Initial version.
EVTG
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.7,15.7,10.1,10.4,10.8,10.3,16.1,16.3 .
[2.0.0]
Initial version.
EWM
[2.0.3]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.1, 10.3.
[2.0.2]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.3, 10.4.
[2.0.1]
Bug Fixes
Fixed the hard fault in EWM_Deinit.
[2.0.0]
Initial version.
FLEXCAN
[2.13.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
Improvements
Support payload endianness selection feature.
[2.12.0]
Improvements
Support automatic Remote Response feature.
Add API FLEXCAN_SetRemoteResponseMbConfig() to configure automatic Remote Response mailbox.
[2.11.8]
Improvements
Synchronize flexcan driver update on s32z platform.
[2.11.7]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compatibility with edma5.
[2.11.6]
Bug Fixes
Fixed ERRATA_9595 FLEXCAN_EnterFreezeMode() may result to bus fault on some platform.
[2.11.5]
Bug Fixes
Fixed flexcan_memset() crash under high optimization compilation.
[2.11.4]
Improvements
Update CANFD max bitrate to 10Mbps on MCXNx3x and MCXNx4x.
Release peripheral from reset if necessary in init function.
[2.11.3]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compile error with DMA3.
[2.11.2]
Bug Fixes
Fixed bug that timestamp in flexcan_handle_t not updated when RX overflow happens.
[2.11.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
[2.11.0]
Bug Fixes
Fixed wrong base address argument in FLEXCAN2 IRQ Handler.
Improvements
Add API to determine if the instance supports CAN FD mode at run time.
[2.10.1]
Bug Fixes
Fixed HIS CCM issue.
Fixed RTOS issue by adding protection to read-modify-write operations on interrupt enable/disable API.
[2.10.0]
Improvements
Update driver to make it able to support devices which has more than 64 8bytes MBs.
Update CAN FD transfer APIs to make them set/get edl bit according to frame content, which can make them compatible with classic CAN.
[2.9.2]
Bug Fixes
Fixed the issue that FLEXCAN_CheckUnhandleInterruptEvents() can’t detecting the exist enhanced RX FIFO interrupt status.
Fixed the issue that FLEXCAN_ReadPNWakeUpMB() does not return fail even no existing valid wake-up frame.
Fixed the issue that FLEXCAN_ReadEnhancedRxFifo() may clear bits other than the data available bit.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8.
Improvements
Return kStatus_FLEXCAN_RxFifoDisabled instead of kStatus_Fail when read FIFO fail during IRQ handler.
Remove unreachable code from timing calculates APIs.
Update Enhanced Rx FIFO handler to make it deal with underflow/overflow status first.
[2.9.1]
Bug Fixes
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoBlocking() API clearing Fifo data available flag more than once.
Fixed the issue that entering FLEXCAN_SubHandlerForEhancedRxFifo() even if Enhanced Rx fifo interrupts are not enabled.
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoEDMA() update handle even if previous Rx FIFO receive not finished.
Fixed the issue that FLEXCAN_SetEnhancedRxFifoConfig() not configure the ERFCR[NFE] bits to the correct value.
Fixed the issue that FLEXCAN_ReceiveFifoEDMACallback() can’t differentiate between Rx fifo and enhanced rx fifo.
Fixed the issue that FLEXCAN_TransferHandleIRQ() can’t report Legacy Rx FIFO warning status.
[2.9.0]
Improvements
Add public set bit rate API to make driver easier to use.
Update Legacy Rx FIFO transfer APIs to make it support received multiple frames during one API call.
Optimized FLEXCAN_SubHandlerForDataTransfered() API in interrupt handling to reduce the probability of packet loss.
[2.8.7]
Improvements
Initialized the EDMA configuration structure in the FLEXCAN EDMA driver.
[2.8.6]
Bug Fixes
Fix Coverity overrun issues in fsl_flexcan_edma driver.
[2.8.5]
Improvements
Make driver aarch64 compatible.
[2.8.4]
Bug Fixes
Fixed FlexCan_Errata_6032 to disable all interrupts.
[2.8.3]
Bug Fixes
Fixed an issue with the FLEXCAN_EnableInterrupts and FLEXCAN_DisableInterrupts interrupt enable bits in the CTRL1 register.
[2.8.2]
Bug Fixes
Fixed errors in timing calculations and simplify the calculation process.
Fixed issue of CBT and FDCBT register may write failure.
[2.8.1]
Bug Fixes
Fixed the issue of CAN FD three sampling points.
Added macro to support the devices that no MCR[SUPV] bit.
Remove unnecessary clear WMB operations.
[2.8.0]
Improvements
Update config configuration.
Added enableSupervisorMode member to support enable/disable Supervisor mode.
Simplified the algorithm in CAN FD improved timing APIs.
[2.7.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.7.
[2.7.0]
Improvements
Update config configuration.
Added enablePretendedeNetworking member to support enable/disable Pretended Networking feature.
Added enableTransceiverDelayMeasure member to support enable/disable Transceiver Delay MeasurementPretended feature.
Added bitRate/bitRateFD member to work as baudRate/baudRateFD member union.
Rename all “baud” in code or comments to “bit” to align with the CAN spec.
Added Pretended Networking mode related APIs.
FLEXCAN_SetPNConfig
FLEXCAN_GetPNMatchCount
FLEXCAN_ReadPNWakeUpMB
Added support for Enhanced Rx FIFO.
Removed independent memory error interrupt/status APIs and put all interrupt/status control operation into FLEXCAN_EnableInterrupts/FLEXCAN_DisableInterrupts and FLEXCAN_GetStatusFlags/FLEXCAN_ClearStatusFlags APIs.
Update improved timing APIs to make it calculate improved timing according to CiA doc recommended.
FLEXCAN_CalculateImprovedTimingValues.
FLEXCAN_FDCalculateImprovedTimingValues.
Update FLEXCAN_SetBitRate/FLEXCAN_SetFDBitRate to added the use of enhanced timing registers.
[2.6.2]
Improvements
Add CANFD frame data length enumeration.
[2.6.1]
Bug Fixes
Fixed the issue of not fully initializing memory in FLEXCAN_Reset() API.
[2.6.0]
Improvements
Enable CANFD ISO mode in FLEXCAN_FDInit API.
Enable the transceiver delay compensation feature when enable FD operation and set bitrate switch.
Implementation memory error control in FLEXCAN_Init API.
Improve FLEXCAN_FDCalculateImprovedTimingValues API to get same value for FPRESDIV and PRESDIV.
Added memory error configuration for user.
enableMemoryErrorControl
enableNonCorrectableErrorEnterFreeze
Added memory error related APIs.
FLEXCAN_GetMemoryErrorReportStatus
FLEXCAN_GetMemoryErrorStatusFlags
FLEXCAN_ClearMemoryErrorStatusFlags
FLEXCAN_EnableMemoryErrorInterrupts
FLEXCAN_DisableMemoryErrorInterrupts
Bug Fixes
Fixed the issue of sent duff CAN frame after call FLEXCAN_FDInit() API.
[2.5.2]
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
The bit field in CTRL1 register couldn’t calculate higher ideal SP, we set it as the lowest one(75%)
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
Fixed MISRA-C 2012 Rule 17.7 and 14.4.
Improvements
Pass EsrStatus to callback function when kStatus_FLEXCAN_ErrorStatus is comming.
[2.5.1]
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
[2.5.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-11.8, rule-12.2, rule-13.4, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-16.4, rule-17.3, rule-5.8, rule-8.3, rule-8.5.
Fixed the issue that API FLEXCAN_SetFDRxMbConfig lacks inactive message buff.
Fixed the issue of Pa082 warning.
Fixed the issue of dead lock in the function of interruption handler.
Fixed the issue of Legacy Rx Fifo EDMA transfer data fail in evkmimxrt1060 and evkmimxrt1064.
Fixed the issue of setting CANFD Bit Rate Switch.
Fixed the issue of operating unknown pointer risk.
when used the pointer “handle->mbFrameBuf[mbIdx]” to update the timestamp in a short-live TX frame, the frame pointer became as unknown, the action of operating it would result in program stack destroyed.
Added assert to check current CAN clock source affected by other clock gates in current device.
In some chips, CAN clock sources could be selected by CCM. But for some clock sources affected by other clock gates, if user insisted on using that clock source, they had to open these gates at the same time. However, they should take into consideration the power consumption issue at system level. In RT10xx chips, CAN clock source 2 was affected by the clock gate of lpuart1. ERRATA ID: (ERR050235 in CCM).
Improvements
Implementation for new FLEXCAN with ECC feature able to exit Freeze mode.
Optimized the function of interruption handler.
Added two APIs for FLEXCAN EDMA driver.
FLEXCAN_PrepareTransfConfiguration
FLEXCAN_StartTransferDatafromRxFIFO
Added new API for FLEXCAN driver.
FLEXCAN_GetTimeStamp
For TX non-blocking API, we wrote the frame into mailbox only, so no need to register TX frame address to the pointer, and the timestamp could be updated into the new global variable handle->timestamp[mbIdx], the FLEXCAN driver provided a new API for user to get it by handle and index number after TX DONE Success.
FLEXCAN_EnterFreezeMode
FLEXCAN_ExitFreezeMode
Added new configuration for user.
disableSelfReception
enableListenOnlyMode
Renamed the two clock source enum macros based on CLKSRC bit field value directly.
The CLKSRC bit value had no property about Oscillator or Peripheral type in lots of devices, it acted as two different clock input source only, but the legacy enum macros name contained such property, that misled user to select incorrect CAN clock source.
Created two new enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrc0
kFLEXCAN_ClkSrc1
Deprecated two legacy enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrcOsc
kFLEXCAN_ClkSrcPeri
Changed the process flow for Remote request frame response..
Created a new enum macro for the FLEXCAN driver.
kStatus_FLEXCAN_RxRemote
Changed the process flow for kFLEXCAN_StateRxRemote state in the interrupt handler.
Should the TX frame not register to the pointer of frame handle, interrupt handler would not be able to read the remote response frame from the mail box to ram, so user should read the frame by manual from mail box after a complete remote frame transfer.
[2.4.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-12.1, rule-17.7, rule-16.4, rule-11.9, rule-8.4, rule-14.4, rule-10.8, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-8.3, rule-12.2 and rule-16.1.
Fixed the issue that CANFD transfer data fail when bus baudrate is 30Khz.
Fixed the issue that ERR009595 does not folllow the ERRATA document.
Fixed code error for ERR006032 work around solution.
Fixed the Coverity issue of BAD_SHIFT in FLEXCAN.
Fixed the Repo build warning issue for variable without initial.
Improvements
Fixed the run fail issue of FlexCAN RemoteRequest UT Case.
Implementation all TX and RX transfering Timestamp used in FlexCAN demos.
Fixed the issue of UT Test Fail for CANFD payload size changed from 64BperMB to 8PerMB.
Implementation for improved timing API by baud rate.
[2.3.2]
Improvements
Implementation for ERR005959.
Implementation for ERR005829.
Implementation for ERR006032.
[2.3.1]
Bug Fixes
Added correct handle when kStatus_FLEXCAN_TxSwitchToRx is comming.
[2.3.0]
Improvements
Added self-wakeup support for STOP mode in the interrupt handling.
[2.2.3]
Bug Fixes
Fixed the issue of CANFD data phase’s bit rate not set as expected.
[2.2.2]
Improvements
Added a time stamp feature and enable it in the interrupt_transfer example.
[2.2.1]
Improvements
Separated CANFD initialization API.
In the interrupt handling, fix the issue that the user cannot use the normal CAN API when with an FD.
[2.2.0]
Improvements
Added FSL_FEATURE_FLEXCAN_HAS_SUPPORT_ENGINE_CLK_SEL_REMOVE feature to support SoCs without CAN Engine Clock selection in FlexCAN module.
Added FlexCAN Serial Clock Operation to support i.MX SoCs.
[2.1.0]
Bug Fixes
Corrected the spelling error in the function name FLEXCAN_XXX().
Moved Freeze Enable/Disable setting from FLEXCAN_Enter/ExitFreezeMode() to FLEXCAN_Init().
Corrected wrong helper macro values.
Improvements
Hid FLEXCAN_Reset() from user.
Used NDEBUG macro to wrap FLEXCAN_IsMbOccupied() function instead of DEBUG macro.
[2.0.0]
Initial version.
FLEXIO
[2.3.0]
Improvements
Supported platforms which don’t have DOZE mode control.
Added more pin control functions.
[2.2.3]
Improvements
Adapter the FLEXIO driver to platforms which don’t have system level interrupt controller, such as NVIC.
[2.2.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]
Improvements
Added doxygen index parameter comment in FLEXIO_SetClockMode.
[2.2.0]
New Features
Added new APIs to support FlexIO pin register.
[2.1.0]
Improvements
Added API FLEXIO_SetClockMode to set flexio channel counter and source clock.
[2.0.4]
Bug Fixes
Fixed MISRA 8.4 issues.
[2.0.3]
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.2]
Improvements
Split FLEXIO component which combines all flexio/flexio_uart/flexio_i2c/flexio_i2s drivers into several components: FlexIO component, flexio_uart component, flexio_i2c_master component, and flexio_i2s component.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.0.1]
Bug Fixes
Fixed the dozen mode configuration error in FLEXIO_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
FLEXIO_I2C
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Split some functions, fixed CCM problem in file fsl_flexio_i2c_master.c.
[2.4.0]
Improvements
Added delay of 1 clock cycle in FLEXIO_I2C_MasterTransferRunStateMachine to ensure that bus would be idle before next transfer if master is nacked.
Fixed issue that the restart setup time is less than the time in I2C spec by adding delay of 1 clock cycle before restart signal.
[2.3.0]
Improvements
Used 3 timers instead of 2 to support transfer which is more than 14 bytes in single transfer.
Improved FLEXIO_I2C_MasterTransferGetCount so that the API can check whether the transfer is still in progress.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Added an API for checking bus pin status.
Bug Fixes
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
Added codes in FLEXIO_I2C_MasterTransferCreateHandle to clear pending NVIC IRQ, disable internal IRQs before enabling NVIC IRQ.
Modified code so that during master’s nonblocking transfer the start and slave address are sent after interrupts being enabled, in order to avoid potential issue of sending the start and slave address twice.
[2.1.7]
Bug Fixes
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking did not wait for STOP bit sent.
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed the issue that I2C master did not check whether bus was busy before transfer.
[2.1.6]
Bug Fixes
Fixed the issue that I2C Master transfer APIs(blocking/non-blocking) did not support the situation of master transfer with subaddress and transfer data size being zero, which means no data followed the subaddress.
[2.1.5]
Improvements
Unified component full name to FLEXIO I2C Driver.
[2.1.4]
Bug Fixes
The following modifications support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.3]
Improvements
Changed the prototype of FLEXIO_I2C_MasterInit to return kStatus_Success if initialized successfully or to return kStatus_InvalidArgument if “(srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1” exceeds 0xFFU.
[2.1.2]
Bug Fixes
Fixed the FLEXIO I2C issue where the master could not receive data from I2C slave in high baudrate.
Fixed the FLEXIO I2C issue where the master could not receive NAK when master sent non-existent addr.
Fixed the FLEXIO I2C issue where the master could not get transfer count successfully.
Fixed the FLEXIO I2C issue where the master could not receive data successfully when sending data first.
Fixed the Dozen mode configuration error in FLEXIO_I2C_MasterInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking API called FLEXIO_I2C_MasterTransferCreateHandle, which lead to the s_flexioHandle/s_flexioIsr/s_flexioType variable being written. Then, if calling FLEXIO_I2C_MasterTransferBlocking API multiple times, the s_flexioHandle/s_flexioIsr/s_flexioType variable would not be written any more due to it being out of range. This lead to the following situation: NonBlocking transfer APIs could not work due to the fail of register IRQ.
[2.1.1]
Bug Fixes
Implemented the FLEXIO_I2C_MasterTransferBlocking API which is defined in header file but has no implementation in the C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S
[2.2.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed violations of the MISRA C-2012 rules 10.4, 14.4, 11.8, 11.9, 10.1, 17.7, 11.6, 10.3, 10.7.
[2.1.6]
Bug Fixes
Added reset flexio before flexio i2s init to make sure flexio status is normal.
[2.1.5]
Bug Fixes
Fixed the issue that I2S driver used hard code for bitwidth setting.
[2.1.4]
Improvements
Unified component’s full name to FLEXIO I2S (DMA/EDMA) driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
New Features
Added configure items for all pin polarity and data valid polarity.
Added default configure for pin polarity and data valid polarity.
[2.1.1]
Bug Fixes
Fixed FlexIO I2S RX data read error and eDMA address error.
Fixed FlexIO I2S slave timer compare setting error.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S_EDMA
[2.1.8]
Improvements
Applied EDMA ERRATA 51327.
FLEXIO_MCU_LCD
[2.2.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.1.0]
New Features
Supported transmit only data without command.
[2.0.8]
Bug Fixes
Fixed bug that FLEXIO_MCULCD_Init return kStatus_Success even with invalid parameter.
Fixed glitch on WR, that when initially configure the timer pin as output, or change the pin back to disabled, the pin may be driven low causing glitch on bus. Configure the pin as bidirection output first then perform a subsequent write to change to output or dsiabled to avoid the issue.
[2.0.6]
Bug Fixes
Fixed MISRA 10.4 issues when FLEXIO_MCULCD_DATA_BUS_WIDTH defined as signed value.
[2.0.5]
Improvements
Changed FLEXIO_MCULCD_WriteDataArrayBlocking’s data parameter to const type.
[2.0.4]
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.2]
Improvements
Unified component full name to FLEXIO_MCU_LCD (EDMA) driver.
[2.0.1]
Bug Fixes
The following modification to support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.0.0]
Initial version.
FLEXIO_MCU_LCD_EDMA
[2.0.5]
New Features
Supported transmit only data without command.
[2.0.4]
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.2]
Improvements
Unified component full name to FLEXIO_MCU_LCD (EDMA) driver.
[2.0.1]
Bug Fixes
The following modification to support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.0.0]
Initial version.
FLEXIO_MCU_LCD_SMARTDMA
[2.0.4]
New Features
Supported the platforms which use FlexIO SHIFTER DMA to trigger SmartDMA, such as MCXN235, MCXN236.
[2.0.3]
New Features
Supported transmit only data without command.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.1]
Other Changes
Update driver implementation due to SMARTDMA driver update.
[2.0.0]
Initial version.
FLEXIO_SPI
[2.4.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.3.5]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.4]
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.3]
Bugfixes
Fixed cs-continuous mode.
[2.3.2]
Improvements
Changed FLEXIO_SPI_DUMMYDATA to 0x00.
[2.3.1]
Bugfixes
Fixed IRQ SHIFTBUF overrun issue when one FLEXIO instance used as multiple SPIs.
[2.3.0]
New Features
Supported FLEXIO_SPI slave transfer with continuous master CS signal and CPHA=0.
Supported FLEXIO_SPI master transfer with continuous CS signal.
Support 32 bit transfer width.
Bug Fixes
Fixed wrong timer compare configuration for dma/edma transfer.
Fixed wrong byte order of rx data if transfer width is 16 bit, since the we use shifter buffer bit swapped/byte swapped register to read in received data, so the high byte should be read from the high bits of the register when MSB.
[2.2.1]
Bug Fixes
Fixed bug in FLEXIO_SPI_MasterTransferAbortEDMA that when aborting EDMA transfer EDMA_AbortTransfer should be used rather than EDMA_StopTransfer.
[2.2.0]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
Added codes in FLEXIO_SPI_MasterTransferCreateHandle and FLEXIO_SPI_SlaveTransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.1.3]
Improvements
Unified component full name to FLEXIO SPI(DMA/EDMA) Driver.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.2]
Bug Fixes
The following modification support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.1]
Bug Fixes
Fixed bug where FLEXIO SPI transfer data is in 16 bit per frame mode with eDMA.
Fixed bug when FLEXIO SPI works in eDMA and interrupt mode with 16-bit per frame and Lsbfirst.
Fixed the Dozen mode configuration error in FLEXIO_SPI_MasterInit/FLEXIO_SPI_SlaveInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Improvements
Added #ifndef/#endif to allow users to change the default TX value at compile time.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
Bug Fixes
Fixed the error register address return for 16-bit data write in FLEXIO_SPI_GetTxDataRegisterAddress.
Provided independent IRQHandler/transfer APIs for Master and slave to fix the baudrate limit issue.
FLEXIO_UART
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Added API FLEXIO_UART_FlushShifters to flush UART fifo.
[2.4.0]
Improvements
Use separate data for TX and RX in flexio_uart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling FLEXIO_UART_TransferReceiveNonBlocking, the received data count returned by FLEXIO_UART_TransferGetReceiveCount is wrong.
[2.3.0]
Improvements
Added check for baud rate’s accuracy that returns kStatus_FLEXIO_UART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
Bug Fixes
Added codes in FLEXIO_UART_TransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.2.0]
Improvements
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.1.6]
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.5]
Improvements
Triggered user callback after all the data in ringbuffer were received in FLEXIO_UART_TransferReceiveNonBlocking.
[2.1.4]
Improvements
Unified component full name to FLEXIO UART(DMA/EDMA) Driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
Bug Fixes
Fixed the transfer count calculation issue in FLEXIO_UART_TransferGetReceiveCount, FLEXIO_UART_TransferGetSendCount, FLEXIO_UART_TransferGetReceiveCountDMA, FLEXIO_UART_TransferGetSendCountDMA, FLEXIO_UART_TransferGetReceiveCountEDMA and FLEXIO_UART_TransferGetSendCountEDMA.
Fixed the Dozen mode configuration error in FLEXIO_UART_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Added code to report errors if the user sets a too-low-baudrate which FLEXIO cannot reach.
Disabled FLEXIO_UART receive interrupt instead of all NVICs when reading data from ring buffer. If ring buffer is used, receive nonblocking will disable all NVIC interrupts to protect the ring buffer. This had negative effects on other IPs using interrupt.
[2.1.1]
Bug Fixes
Changed the API name FLEXIO_UART_StopRingBuffer to FLEXIO_UART_TransferStopRingBuffer to align with the definition in C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added txSize/rxSize in handle structure to record the transfer size.
Bug Fixes
Added an error handle to handle the situation that data count is zero or data buffer is NULL.
FLEXIO_UART_EDMA
[2.3.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.3.0]
Refer FLEXIO_UART driver change log to 2.3.0
FLEXSPI
[2.6.3]
Bug Fixes
Fixed an issue which cause IPCR1[IPAREN] cleared by mistake.
[2.6.2]
Bug Fixes
Wait Bus IDLE before operation of FLEXSPI_SoftwareReset(), FLEXSPI_TransferBlocking() and FLEXSPI_TransferNonBlocking().
[2.6.1]
Bug Fixes
Updated code of reset peripheral.
Updated FLEXSPI_UpdateLUT() to check if input lut address is not in Flexspi AMBA region.
Updated FLEXSPI_Init() to check if input AHB buffer size exceeded maximum AHB size.
[2.6.0]
New Features
Added new API to set AHB memory-mapped flash base address.
Added support of DLLxCR[REFPHASEGAP] bit field, it is recommended to set it as 0x2 if DLL calibration is enabled.
[2.5.1]
Bugfixes
Fixed handling of W1C bits in the INTR register
Removed FIFO resets from FLEXSPI_CheckAndClearError
FLEXSPI_TransferBlocking is observing IPCMDDONE and then fetches the final status of the transfer
Fixed issue that FLEXSPI2_DriverIRQHandler not defined.
[2.5.0]
Improvements
Supported word un-aligned access for write/read blocking/non-blocking API functions.
Fixed dead loop issue in DLL update function when using FRO clock source.
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.4.0]
Improvements
Isolated IP command parallel mode and AHB command parallel mode using feature MACRO.
Supported new column address shift feature for external memory.
[2.3.5]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.2.
[2.3.4]
Bug Fixes
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_CONBINATION.
[2.3.3]
Bug Fixes
Removed feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS for DLL delay setting. Changed to use feature FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN to set slave delay target as 0 for DLL enable and clock frequency higher than 100MHz.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 8.4, 8.5, 10.1, 10.3, 10.4, 11.6 and 14.4.
[2.3.1]
Bug Fixes
Wait for bus to be idle before using it as access to external flash with new setting in FLEXSPI_SetFlashConfig() API.
Fixed the potential buffer overread and Tx FIFO overwrite issue in FLEXSPI_WriteBlocking.
[2.3.0]
New Features
Added new API FLEXSPI_UpdateDllValue for users to update DLL value after updating flexspi root clock.
Corrected grammatical issues for comments.
Added support for new feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS in DLL configuration.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3 and 10.4.
Updated _flexspi_command from named enumerator into anonymous enumerator.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8, 11.9, 14.4, 15.7, 16.4, 17.7, 7.3.
Fixed IAR build warning Pe167.
Fixed the potential buffer overwrite and Rx FIFO overread issue in FLEXSPI_ReadBlocking.
[2.2.0]
Bug Fixes
Fixed flag name typos: kFLEXSPI_IpTxFifoWatermarkEmpltyFlag to kFLEXSPI_IpTxFifoWatermarkEmptyFlag; kFLEXSPI_IpCommandExcutionDoneFlag to kFLEXSPI_IpCommandExecutionDoneFlag.
Fixed comments typos such as sequencen->sequence, levle->level.
Fixed FLSHCR2[ARDSEQID] field clean issue.
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN and FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN.
Updated flexspi_flags_t structure to support new feature FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN.
[2.1.1]
Improvements
Defaulted enable prefetch for AHB RX buffer configuration in FLEXSPI_GetDefaultConfig, which is align with the reset value in AHBRXBUFxCR0.
Added software workaround for ERR011377 in FLEXSPI_SetFlashConfig; added some delay after DLL lock status set to ensure correct data read/write.
[2.1.0]
New Features
Added new API FLEXSPI_UpdateRxSampleClock for users to update read sample clock source after initialization.
Added reset peripheral operation in FLEXSPI_Init if required.
[2.0.5]
Bug Fixes
Fixed FLEXSPI_UpdateLUT cannot do partial update issue.
[2.0.4]
Bug Fixes
Reset flash size to zero for all ports in FLEXSPI_Init; fixed the possible out-of-range flash access with no error reported.
[2.0.3]
Bug Fixes
Fixed AHB receive buffer size configuration issue. The FLEXSPI_AHBRXBUFCR0_BUFSZ field should configure 64 bits size, and currently the AHB receive buffer size is in bytes which means 8-bit, so the correct configuration should be config->ahbConfig.buffer[i].bufferSize / 8.
[2.0.2]
New Features
Supported DQS write mask enable/disable feature during set FLEXSPI configuration.
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
Bug Fixes
Fixed invalid operation of FLEXSPI_Init to enable AHB bus Read Access to IP RX FIFO.
Fixed incorrect operation of FLEXSPI_Init to configure IP TX FIFO watermark.
[2.0.1]
Bug Fixes
Fixed the flag clear issue and AHB read Command index configuration issue in FLEXSPI_SetFlashConfig.
Updated FLEXSPI_UpdateLUT function to update LUT table from any index instead of previous command index.
Added bus idle wait in FLEXSPI_SetFlashConfig and FLEXSPI_UpdateLUT to ensure bus is idle before any change to FlexSPI controller.
Updated interrupt API FLEXSPI_TransferNonBlocking and interrupt handle flow FLEXSPI_TransferHandleIRQ.
Updated eDMA API FLEXSPI_TransferEDMA.
[2.0.0]
Initial version.
FLEXSPI EDMA Driver
[2.3.3]
Bug Fixes
Fixed FLEXSPI_TransferEDMA bug that, the DMA channel not configured correctly when using kFLEXSPI_Read.
[2.3.2]
Bug Fixes
Fixed the bug that internal variable s_edmaPrivateHandle overflows when using FlexSPI2.
[2.0.2]
New Features
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
[2.0.0]
Initial version.
FREQME
[2.1.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.1]
Fixed MISRA issues.
[2.1.0]
Updated register name.
[2.0.0]
Initial version.
GDET
[2.1.0]
Update for multiple instances
Fix bug in isolation off API
Add enable and disable APIs
[2.0.1]
Fix MISRA in GDET_ReconfigureVoltageMode().
[2.0.0]
Initial version.
GPIO
[2.8.1]
Bug Fixes
Fixed CERT INT31-C issues.
[2.8.0]
Improvements
Add API GPIO_PortInit/GPIO_PortDeinit to set GPIO clock enable and releasing GPIO reset.
[2.8.0]
Improvements
Add API GPIO_PortInit/GPIO_PortDeinit to set GPIO clock enable and releasing GPIO reset.
Remove support for API GPIO_GetPinsDMARequestFlags with GPIO_ISFR_COUNT <= 1.
[2.7.3]
Improvements
Release peripheral from reset if necessary in init function.
[2.7.2]
New Features
Support devices without PORT module.
[2.7.1]
Bug Fixes
Fixed MISRA C-2012 rule 10.4 issues in GPIO_GpioGetInterruptChannelFlags() function and GPIO_GpioClearInterruptChannelFlags() function.
[2.7.0]
New Features
Added API to support Interrupt select (IRQS) bitfield.
[2.6.0]
New Features
Added API to get GPIO version information.
Added API to control a pin for general purpose input.
Added some APIs to control pin in secure and previliege status.
[2.5.3]
Bug Fixes
Correct the feature macro typo: FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTORL.
[2.5.2]
Improvements
Improved GPIO_PortSet/GPIO_PortClear/GPIO_PortToggle functions to support devices without Set/Clear/Toggle registers.
[2.5.1]
Bug Fixes
Fixed wrong macro definition.
Fixed MISRA C-2012 rule issues in the FGPIO_CheckAttributeBytes() function.
Defined the new macro to separate the scene when the width of registers is different.
Removed some redundant macros.
New Features
Added some APIs to get/clear the interrupt status flag when the port doesn’t control pins’ interrupt.
[2.4.1]
Improvements
Improved GPIO_CheckAttributeBytes() function to support 8 bits width GACR register.
[2.4.0]
Improvements
API interface added:
New APIs were added to configure the GPIO interrupt clear settings.
[2.3.2]
Bug Fixes
Fixed the issue for MISRA-2012 check.
Fixed rule 3.1, 10.1, 8.6, 10.6, and 10.3.
[2.3.1]
Improvements
Removed deprecated APIs.
[2.3.0]
New Features
Updated the driver code to adapt the case of interrupt configurations in GPIO module. New APIs were added to configure the GPIO interrupt settings if the module has this feature on it.
[2.2.1]
Improvements
API interface changes:
Refined naming of APIs while keeping all original APIs by marking them as deprecated. The original APIs will be removed in next release. The main change is updating APIs with prefix of _PinXXX() and _PortXXX.
[2.1.1]
Improvements
API interface changes:
Added an API for the check attribute bytes.
[2.1.0]
Improvements
API interface changes:
Added “pins” or “pin” to some APIs’ names.
Renamed “_PinConfigure” to “GPIO_PinInit”.
I3C
[2.13.1]
Bug Fixes
Disabled Rx auto-termination in repeated start interrupt event while transfer API doesn’t enable it.
Waited the completion event after loading all Tx data in Tx FIFO.
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
New features
Added the hot-join support for I3C bus initialization API.
Bug Fixes
Set read termination with START at the same time in case unknown issue.
Set MCTRL[TYPE] as 0 for DDR force exit.
Improvements
Added the API to reset device count assigned by ENTDAA.
Provided the method to set global macro I3C_MAX_DEVCNT to determine how many device addresses ENTDAA can allocate at one time.
Initialized target management static array based on instance number for the case that multiple instances are used at the same time.
[2.12.0]
Improvements
Added the slow clock parameter for Controller initialization function to calculate accurate timeout.
Bug Fixes
Fixed the issue that BAMATCH field can’t be 0. BAMATCH should be 1 for 1MHz slow clock.
[2.11.1]
Bug Fixes
Fixed the issue that interrupt API transmits extra byte when subaddress and data size are null.
Fixed the slow clock calculation issue.
[2.11.0]
New features
Added the START/ReSTART SCL delay setting for the Soc which supports this feature.
Bug Fixes
Fixed the issue that ENTDAA process waits Rx pending flag which causes problem when Rx watermark isn’t 0. Just check the Rx FIFO count.
[2.10.8]
Improvements
Support more instances.
[2.10.7]
Improvements
Fixed the potential compile warning.
[2.10.6]
New features
Added the I3C private read/write with 0x7E address as start.
[2.10.5]
New features
Added I3C HDR-DDR transfer support.
[2.10.4]
Improvements
Added one more option for master to not set RDTERM when doing I3C Common Command Code transfer.
[2.10.3]
Improvements
Masked the slave IBI/MR/HJ request functions with feature macro.
[2.10.2]
Bug Fixes
Added workaround for errata ERR051617: I3C working with I2C mode creates the unintended Repeated START before actual STOP on some platforms.
[2.10.1]
Bug Fixes
Fixed the issue that DAA function doesn’t wait until all Rx data is read out from FIFO after master control done flag is set.
Fixed the issue that DAA function could return directly although the disabled interrupts are not enabled back.
[2.10.0]
New features
Added I3C extended IBI data support.
[2.9.0]
Improvements
Added adaptive termination for master blocking transfer. Set termination with start signal when receiving bytes less than 256.
[2.8.2]
Improvements
Fixed the build warning due to armgcc strict check.
[2.8.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.8.0]
Improvements
Added API I3C_MasterProcessDAASpecifiedBaudrate for temporary baud rate adjustment when I3C master assigns dynamic address.
[2.7.1]
Bug Fixes
Fixed the issue that I3C slave handle STOP event before finishing data transmission.
[2.7.0]
Fixed the CCM problem in file fsl_i3c.c.
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in I3C_GetDefaultConfig and I3C_Init.
[2.6.0]
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in fsl_i3c.h.
Changed some static functions in fsl_i3c.c as non-static and define the functions in fsl_i3c.h to make I3C DMA driver reuse:
I3C_GetIBIType
I3C_GetIBIAddress
I3C_SlaveCheckAndClearError
Changed the handle pointer parameter in IRQ related funtions to void * type to make it reuse in I3C DMA driver.
Added new API I3C_SlaveRequestIBIWithSingleData for slave to request single data byte, this API could be used regardless slave is working in non-blocking interrupt or non-blocking dma.
Added new API I3C_MasterGetDeviceListAfterDAA for master application to get the device information list built up in DAA process.
[2.5.4]
Improved I3C driver to avoid setting state twice in the SendCommandState of I3C_RunTransferStateMachine.
Fixed MISRA violation of rule 20.9.
Fixed the issue that I3C_MasterEmitRequest did not use Type I3C SDR.
[2.5.3]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH and FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND.
[2.5.2]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM.
Fixed the issue that call to I3C_MasterTransferBlocking API did not generate STOP signal when NAK status was returned.
[2.5.1]
Improved the receive terminate size setting for interrupt transfer read, now it’s set at beginning of transfer if the receive size is less than 256 bytes.
[2.5.0]
Added new API I3C_MasterRepeatedStartWithRxSize to send repeated start signal with receive terminate size specified.
Fixed the status used in I3C_RunTransferStateMachine, changed to use pending interrupts as status to be handled in the state machine.
Fixed MISRA 2012 violation of rule 10.3, 10.7.
[2.4.0]
Bug Fixes
Fixed kI3C_SlaveMatchedFlag interrupt is not properly handled in I3C_SlaveTransferHandleIRQ when it comes together with interrupt kI3C_SlaveBusStartFlag.
Fixed the inaccurate I2C baudrate calculation in I3C_MasterSetBaudRate.
Added new API I3C_MasterGetIBIRules to get registered IBI rules.
Added new variable isReadTerm in struct _i3c_master_handle for transfer state routine to check if MCTRL.RDTERM is configured for read transfer.
Changed to emit Auto IBI in transfer state routine for slave start flag assertion.
Fixed the slave maxWriteLength and maxReadLength does not be configured into SMAXLIMITS register issue.
Fixed incorrect state for IBI in I3C master interrupt transfer IRQ handle routine.
Added isHotJoin in i3c_slave_config_t to request hot-join event during slave init.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 17.7.
Fixed incorrect HotJoin event index in I3C_GetIBIType.
[2.3.1]
Bug Fixes
Fixed the issue that call of I3C_MasterTransferBlocking/I3C_MasterTransferNonBlocking fails for the case which receive length 1 byte of data.
Fixed the issue that STOP signal is not sent when NAK status is detected during execution of I3C_MasterTransferBlocking function.
[2.3.0]
Improvements
Added I3C common driver APIs to initialize I3C with both master and slave configuration.
Updated I3C master transfer callback to function set structure to include callback invoke for IBI event and slave2master event.
Updated I3C master non-blocking transfer model and always enable the interrupts to be able to re-act to the slave start event and handle slave IBI.
[2.2.0]
Bug Fixes
Fixed the issue that I3C transfer size limit to 255 bytes.
[2.1.2]
Bug Fixes
Reset default hkeep value to kI3C_MasterHighKeeperNone in I3C_MasterGetDefaultConfig
[2.1.1]
Bug Fixes
Fixed incorrect FIFO reset operation in I3C Master Transfer APIs.
Fixed i3c slave IRQ handler issue, slave transmit could be underrun because tx FIFO is not filled in time right after start flag detected.
[2.1.0]
Added definitions and APIs for I3C slave functionality, updated previous I3C APIs to support I3C functionality.
[2.0.0]
Initial version.
I3C_EDMA
[2.2.9]
Bug Fixes
Fixed MISRA issue rule 11.3.
Added the master control done flag waiting code after STOP in case the bus is not idle when transfer function finishes.
[2.2.8]
Improvements
Removed I3C IRQ handler calling in the EDMA callback. Previously driver doesn’t use the END byte which can trigger the STOP interrupt for controller sending and receiving, now let I3C event handler deal with all I3C events.
Bug Fixes
Fixed the bug that the END type Tx register is not used when command length or data length is one byte.
[2.2.7]
Bug Fixes
Fixed MISRA issue rule 11.6.
[2.2.6]
New features
Added the I3C private read/write with 0x7E address as start.
[2.2.5]
Improvements
Added the workaround for RT1180 I3C EDMA issue ERR052086.
[2.2.4]
Bug Fixes
Fixed the issue that I3C master sends the last byte data without using the END type register.
[2.2.3]
Bug Fixes
Fixed issue that slave polulates the last byte when Tx FIFO may be full.
[2.2.2]
Bug Fixes
Fixed I3C MISRA issue rule 10.4, 11.3.
[2.2.1]
Bug Fixes
Fixed the issue that I3C slave send the last byte data without using the END type register.
Improvements
There’s no need to reserve two bytes FIFO for DMA transfer which is for IP issue workaround.
[2.2.0]
Improvements
Deleted legacy IBI data request code.
[2.1.0]
Bug Fixes
Fixed MISRA issue rule 8.4, 8.6, 11.8.
[2.0.1]
Bug Fixes
Fixed MISRA issue rule 9.1.
[2.0.0]
Initial version.
INPUTMUX
[2.0.8]
Improvements
Updated a feature macro usage for function INPUTMUX_EnableSignal.
[2.0.7]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.6]
Bug Fixes
Fixed the documentation wrong in API INPUTMUX_AttachSignal.
[2.0.5]
Bug Fixes
Fixed build error because some devices has no sct.
[2.0.4]
Bug Fixes
Fixed violations of the MISRA C-2012 rule 10.4, 12.2 in INPUTMUX_EnableSignal() function.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 10.7, 12.2.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 12.2.
[2.0.1]
Support channel mux setting in INPUTMUX_EnableSignal().
[2.0.0]
Initial version.
INTM
[2.1.0]
Replace macro FSL_FEATURE_INTM_MONITOR_COUNT to INTM_MON_COUNT.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4.
[2.0.0]
Initial version.
IPED
[2.2.0]
Renamed CSS to ELS.
[2.1.1]
Fix build error due to renamed symbols.
[2.1.0]
Add IPED_Config() (including FFR CMPA write) and IPED_Reconfig() features.
[2.0.0]
Initial version.
IRTC
[2.3.2]
Bug Fixes
Fixed API IRTC_GetDatetime read YEARMON, DAYS, HOURMIN, SECONDS registers issue.
[2.3.1]
Bug Fixes
Fixed MISRA C-2012 issue 10.4.
[2.3.0]
New Feature
Supported platforms with multiple IRTC instances.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 issue 10.1, 10.3, 10.4, 10.7, 12.2.
[2.2.3]
Bug Fixes
Updated undefined macro names by available ones.
[2.2.2]
Bug Fixes
Fixed MISRA C-2012 issue 10.3.
[2.2.1]
Bug Fixes
Fixed MISRA issues.
[2.2.0]
New Feature
Add new APIs for CLK_SEL and CLKO to select RTC clock and enable/disable output to peripherals.
Supported platforms without tamper feature.
[2.1.3]
Bug Fixes
Fixed MISRA C-2012 issue 10.1 and 10.4.
[2.1.2]
Bug Fixes
Fixed kIRTC_TamperFlag flag can’t be cleared issue.
[2.1.1]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4.
[2.1.0]
Bug Fixes
Fixed incorrect leap year check in IRTC_CheckDatetimeFormat.
New Feature
Added new APIs for new feature FSL_FEATURE_RTC_HAS_SUBSYSTEM.
Added new APIs for TAMPER, TAMPER QUEUE status get and clear.
Added new API to enable/disable 32 kHz RTC OSC clock during RTC register write.
Updated IRTC_SetTamperParams to support new feature FSL_FEATURE_RTC_HAS_FILTER23_CFG
Updated irtc_config_t to exclude member wakeupSelect for new feature FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE.
[2.0.2]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.6, rule-10.8, rule-11.9, rule-12.2, rule-15.5, rule-16.4, rule-17.7.
[2.0.1]
Bug Fixes
Fixed the issue of hard code in IRTC_Init.
[2.0.0]
Initial version.
ITRC
[2.4.0]
Rework the input signal definition for better flexibility
[2.3.0]
Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM
[2.2.0]
Update driver to new version and input events
[2.1.0]
Make SYSCON glitch platform dependent.
[2.0.0]
Initial version.
LPADC
[2.9.1]
Bug Fixes
Fixed incorrect channel B FIFO selection logic.
[2.9.0]
Bug Fixes
Add code to handle the case where GCC[GAIN_CAL] is a signed number.
Split LPADC_FinishAutoCalibration function into two functions.
Improved LPADC driver.
[2.8.4]
Bug Fixes
Remove function ‘LPADC_SetOffsetValue’ assert statement, this statement may cause runtime errors in existing code.
[2.8.3]
Bug Fixes
Fixed SDK lpadc driver examples compile issue, move condition ‘commandId < ADC_CV_COUNT’ to a more appropriate location.
[2.8.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rule 18.1, 10.3, 10.1 and 10.4.
[2.8.1]
Bug Fixes
Fixed LPADC sample mode enum name mistake.
[2.8.0]
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed function LPADC_GetConvResult() issue.
Fixed function LPADC_SetConvCommandConfig() bugs.
[2.7.2]
Improvements
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.1]
Improvements
Corrected descriptions of several functions.
Improved function LPADC_GetOffsetValue and LPADC_SetOffsetValue.
Revert changes of feature macros for lpadc.
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.8.
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.0]
Improvements
Added supports of CFG2 register.
Removed some useless macros.
[2.6.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rules.
Fixed LPADC driver code compile error issue.
[2.6.1]
Improvements
Updated the use of macros in the driver code.
[2.6.0]
Improvements
Added the API LPADC_SetOffset12BitValue() to configure 12bit ADC conversion offset trim value manually.
Added the API LPADC_SetOffset16BitValue() to configure 16bit ADC conversion offset trim value manually.
Added API to set offset calibration mode.
Added configuration of alternate channel.
Updated auto calibration API and added calibration value conversion API.
New feature
Added API LPADC_EnableHardwareTriggerCommandSelection() to enable trigger commands controlled by ADC_ETC.
Updated LPADC_DoAutoCalibration() to allow doing something else before the ADC inititialization to be totally complete. Enhance initialization duration time of the ADC.
Added two new APIs to get/set calibration value.
[2.5.2]
Improvements
Added while loop, LPADC_GetConvResult() will return only when the FIFO will not be empty.
[2.5.1]
Bug Fixes
Fixed some typos in Lpadc driver comments.
[2.5.0]
Improvements
Added missing items to enable trigger interrupts.
[2.4.0]
New features
Added APIs to get/clear trigger status flags.
[2.3.0]
Improvements
Removed LPADC_MeasureTemperature() function for the LPADC supports different temperature sensor calculation equations.
[2.2.1]
Improvements
Optimized LPADC_MeasureTemperature() function to support the specific series with flash solidified calibration value.
Clean doxygen warnings.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, rule 10.8 and rule 17.7.
[2.2.0]
New Feature
Added API LPADC_MeasureTemperature() to get correct temperature from the internal sensor.
Improvements
Separated lpadc_conversion_resolution_mode_t with related feature macro.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.3, 10.4, 10.6, 10.7 and 17.7.
[2.1.1]
Improvements
Updated the gain calibration formula.
Used feature to segregate the new item kLPADC_TriggerPriorityPreemptSubsequently.
[2.1.0]
New Features
Added the API LPADC_SetOffsetValue() to support configure offset trim value manually.
Added the API LPADC_DoOffsetCalibration() to do offset calibration independently.
Improvements
Improved the usage of macros and removed invalid macros.
[2.0.2]
Improvements
Added support for platforms with 2 FIFOs and different calibration measures.
[2.0.1]
Bug Fixes
Ensured the API LPADC_SetConvCommandConfig configure related registers correctly.
[2.0.0]
Initial version.
LPCMP
[2.3.1]
Improvements
Update LPCMP driver to be compatible with platforms that do not support LPCMP nano power mode selection.
[2.3.0]
New Feature
Added some new features for platforms which support
Plus input source selection.
Minus input source selection.
CMP to DAC link.
Improvements
Removed some new features for platforms which doesn’t support
Functional clock source selection.
DAC high power mode selection.
Round Robin clock source selection.
Round Robin trigger source selection.
Round Robin channel sample numbers setting.
Round Robin channel sample time threshold setting.
Round Robin internal trigger configuration.
[2.2.0]
Improvements
Change FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN to FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN.
[2.1.3]
New Feature
Added new macro to handle the case where some instances do not have the CCR0 CMP_STOP_EN bit field.
[2.1.2]
New Feature
Add macros to be compatible with some platforms that do not have the CCR0 CMP_STOP_EN bitfield.
[2.1.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.0]
New Features:
Supported round robin mode and window mode feature.
[2.0.3]
Bug Fixes:
Fixed the violation of MISRA-2012 rule 17.7.
[2.0.2]
Bug Fixes:
The current API LPCMP_ClearStatusFlags has to check w1c bits.
[2.0.1]
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
LPFLEXCOMM
[2.2.1]
Bug Fix
Fixed the bug that function LPFLEXCOMM_GetBaseAddr() type was uint32_t,but return NULL((void*)0).
[2.2.0]
New Features
Added new API to get LPFLEXCOMM base address.
[2.1.2]
Bug Fix
Fixed the bug that when the same instance is initialized multiple times, all previous states will be cleared and only the last state will be retained.
[2.1.1]
New Features
Supported new platform that has more lpflexcomm instance.
[2.1.0]
Improvements
Function LP_FLEXCOMM_SetPeriph changed from public to private,function LP_FLEXCOMM_Init no longer judges the periph.
[2.0.0]
Initial version.
LPI2C
[2.2.5]
Improvements
Added assert with target feature check in LPI2C_SlaveInit().
Added feature check to LPI2C_CommonIRQHandler().
[2.2.4]
Bug Fixes
Fixed LPI2C_MasterTransferBlocking() - the return value was sometime affected by call of LPI2C_MasterStop().
[2.2.3]
Bug Fixes
Fixed an issue that LP_FLEXCOMM_Deinit() is called incorrectly.
[2.2.2]
Improvements
Fixed doxygen warning in LPI2C_SlaveTransferHandleIRQ.
[2.2.1]
Bug Fixes
Added bus stop incase of bus stall in LPI2C_MasterTransferBlocking.
[2.2.0]
Improvements
Support the normal LPI2C in LPFLEXCOMM driver.
[2.1.1]
Improvements
Optimize slave ISR.When replying to ack/nack,first judge whether the user performs the reply in the APP.
[2.1.0]
New Features
Added new function LPI2C_SlaveEnableAckStall to enable or disable ACKSTALL.
[2.0.1]
Improvements
Supported to initialize the flexcomm layer outside the peripheral driver initialization function.
[2.0.0]
Initial version.
LPI2C_EDMA
[2.0.1]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.0.0]
Initial version.
LPSPI
[2.2.7]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.2.6]
Bug Fixes
Fixed an issue that LP_FLEXCOMM_Deinit() is called incorrectly.
[2.2.5]
Bug Fixes
Fixed the txData from void * to const void * in transmit API.
[2.2.4]
Improvements
Fixed doxygen warning in LPSPI_SlaveTransferHandleIRQ.
[2.2.3]
Bug Fixes
Disabled lpspi before LPSPI_MasterSetBaudRate incase of LPSPI opened.
[2.2.2]
Bug Fixes
Fixed 3-wire txmask of handle vaule reentrant issue.
[2.2.1]
Bug Fixes
Workaround for errata ERR051588 by clearing FIFO after transmit underrun occurs.
[2.2.0]
Feature
Added the new feature of multi-IO SPI .
[2.1.1]
Fixed LPSPI_MasterGetDefaultConfig incorrect default inter-transfer delay calculation.
[2.0.0]
Initial version.
LPSPI_EDMA
[2.1.3]
Improvements
Increased transmit FIFO watermark to ensure whole transmit FIFO will be used during data transfer.
[2.1.2]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.1.1]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.1.0]
Improvements
Separated LPSPI_MasterTransferEDMA functions to LPSPI_MasterTransferPrepareEDMA and LPSPI_MasterTransferEDMALite to optimize the process of transfer.
[2.0.0]
Initial version.
LPTMR
[2.2.0]
Improvements
Updated lptmr_prescaler_clock_select_t, only define the valid options.
[2.1.1]
Improvements
Updated the characters from “PTMR” to “LPTMR” in “FSL_FEATURE_PTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT” feature definition.
[2.1.0]
Improvements
Implement for some special devices’ not supporting for all clock sources.
Bug Fixes
Fixed issue when accessing CMR register.
[2.0.2]
Bug Fixes
Fixed MISRA-2012 issues.
Rule 10.1.
[2.0.1]
Improvements
Updated the LPTMR driver to support 32-bit CNR and CMR registers in some devices.
[2.0.0]
Initial version.
LPUART
[2.3.2]
Bug Fix
Fixed the bug that LPUART_TransferEnable16Bit controled by wrong feature macro.
[2.3.1]
Bug Fix
Fixed MISRA C-2012 violations.
[2.3.0]
Improvements
Added support of DATA register for 9bit or 10bit data transmit in write and read API. Such as: LPUART_WriteBlocking16bit, LPUART_ReadBlocking16bit, LPUART_TransferEnable16Bit LPUART_WriteNonBlocking16bit, LPUART_ReadNonBlocking16bit.
[2.2.4]
Bug Fix
Fixed the bug that baud rate calculation overflow when srcClock_Hz is 528MHz.
[2.2.3]
Improvements
Added atomic in LPUART_EnableInterrupts and LPUART_DisableInterrupts.
[2.2.2]
Improvements
Added comment on txExtendedTimeoutValue of lpuart_timeout_config_t.
[2.2.1]
Bug Fix
Fixed the bug that the OSR calculation error when lupart init and lpuart set baud rate.
[2.2.0]
Improvements
Rename some enumeration variables to be consistent with lpuart driver.
[2.1.1]
Improvements
Supported to initialize the flexcomm layer outside the peripheral driver initialization function.
[2.1.0]
New Features
Supported new platform that does not have the feature of MODEM Control,MODEM Status,Receiver Extended Idle,Transmitter Extended Idle, Half Duplex Control,Timeout Control,Timeout Status and Timeout N.
[2.0.0]
Initial version.
MAILBOX
[2.3.2]
Improvements
Added support for the MCXN946 and MCXN546 series
[2.3.1]
Improvements
Added support for the LPC55S66 series.
[2.3.0]
Improvements
Added support for the MCXNx4x series with new value for kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1.
[2.2.0]
Improvements
Fixed missing conditional defines for the LPC5411x series.
[2.1.0]
Improvements
Added support for the LPC55S69 series. cpu_id parameter can be newly assigned to kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1.
[2.0.0]
Initial version.
MRT
[2.0.4]
Improvements
Don’t reset MRT when there is not system level MRT reset functions.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1 and 10.4.
Fixed the wrong count value assertion in MRT_StartTimer API.
[2.0.2]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.0.1]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
NPX
[2.0.0]
Initial version.
OSTIMER
[2.2.3]
Improvements
Disable and clear pending interrupts before disabling the OSTIMER clock to avoid interrupts being executed when the clock is already disabled.
[2.2.2]
Improvements
Support devices with different OSTIMER instance name.
[2.2.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.0]
Improvements
Move the PMC operation out of the OSTIMER driver to board specific files.
Added low level APIs to control OSTIMER MATCH and interrupt.
[2.1.2]
Bug Fixes
Fixed MISRA-2012 rule 10.8.
[2.1.1]
Bug Fixes
removes the suffix ‘n’ for some register names and bit fields’ names
Improvements
Added HW CODE GRAY feature supported by CODE GRAY in SYSCTRL register group.
[2.1.0]
Bug Fixes
Added a workaround to fix the issue that no interrupt was reported when user set smaller period.
Fixed violation of MISRA C-2012 rule 10.3 and 11.9.
Improvements
Added return value for the two APIs to set match value.
OSTIMER_SetMatchRawValue
OSTIMER_SetMatchValue
[2.0.3]
Bug Fixes
Fixed violation of MISRA C-2012 rule 10.3, 14.4, 17.7.
[2.0.2]
Improvements
Added support for OSTIMER0
[2.0.1]
Improvements
Removed the software reset function out of the initialization API.
Enabled interrupt directly instead of enabling deep sleep interrupt. Users need to enable the deep sleep interrupt in application code if needed.
[2.0.0]
Initial version.
OTP
[2.0.1]
Bug Fixes
Fixed MISRA-C 2012 violations.
[2.0.0]
Initial version.
PDM
[2.9.1]
Bug Fixes
Fixed the issue that the driver still enters the interrupt after disabling clock.
[2.9.0]
Improvements
Added feature FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS to config CTRL_2[DEC_BYPASS] field.
Modify code to make the OSR value is not limited to 16.
[2.8.1]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_DOZEN to handle nonexistent CTRL_1[DOZEN] field.
[2.8.0]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_HWVAD to remove the support of hadware voice activity detector.
Added feature FSL_FEATURE_PDM_HAS_NO_FILTER_BUFFER to remove the support of FIR_RDY bitfield in STAT register.
[2.7.4]
Bug Fixes
Fixed driver can not determine the specific float number of clock divider.
Fixed PDM_ValidateSrcClockRate calculates PDM channel in wrong method issue.
[2.7.3]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_VADEF to remove the support of VADEF bitfield in VAD0_STAT register.
[2.7.2]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV to decide whether the minimum clock frequency division is required.
[2.7.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.3, 10.1, 10.4, 14.4
[2.7.0]
Improvements
Added api PDM_EnableHwvadInterruptCallback to support handle hwvad IRQ in PDM driver.
Corrected the sample rate configuration for non high quality mode.
Added api PDM_SetChannelGain to support adjust the channel gain.
[2.6.0]
Improvements
Added new features FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ/FSL_FEATURE_PDM_HAS_DC_OUT_CTRL/FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED.
[2.5.0]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 16.5, 10.4, 10.3, 10.1, 11.9, 17.7, 10.6, 14.4, 11.8, 11.6.
[2.4.1]
Bug Fixes
Fixed MDK 66-D warning in pdm driver.
[2.4.0]
Improvements
Added api PDM_TransferSetChannelConfig/PDM_ReadFifo to support read different width data.
Added feature FSL_FEATURE_PDM_HAS_RANGE_CTRL and api PDM_ClearRangeStatus/PDM_GetRangeStatus for range register.
Bug Fixes
Fixed violation of MISRA C-2012 Rule 14.4, 10.3, 10.4.
[2.3.0]
Improvements
Enabled envelope/energy voice detect mode by adding apis PDM_SetHwvadInEnvelopeBasedMode/PDM_SetHwvadInEnergyBasedMode.
Added feature FSL_FEATURE_PDM_CHANNEL_NUM for different SOC.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.6, 10.7, 11.3, 11.8, 14.4, 17.7, 18.4.
Added medium quality mode support in function PDM_SetSampleRateConfig.
[2.2.0]
Improvements
Added api PDM_SetSampleRateConfig to improve user experience and marked api PDM_SetSampleRate as deprecated.
[2.1.1]
Improvements
Used new SDMA API SDMA_SetDoneConfig instead of SDMA_EnableSwDone for PDM SDMA driver.
[2.1.0]
Improvements
Added software buffer queue for transactional API.
[2.0.1]
Improvements
Improved HWVAD feature.
[2.0.0]
Initial version.
PDM_EDMA
[2.6.3]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.6.2]
Improvements
Add macro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL to let the user decide whether to enable it when calling PDM_TransferReceiveEDMA.
[2.6.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.3, 10.4.
[2.6.0]
Improvements
Updated api PDM_TransferReceiveEDMA to support channel block interleave transfer.
Added new api PDM_TransferSetMultiChannelInterleaveType to support channel interleave type configurations.
[2.5.0]
Refer PDM driver change log 2.1.0 to 2.5.0
PINT
[2.1.13]
Improvements
Added instance array for PINT to adapt more devices.
Used release reset instead of reset PINT which may clear other related registers out of PINT.
[2.1.12]
Bug Fixes
Fixed coverity issue.
[2.1.11]
Bug Fixes
Fixed MISRA C-2012 rule 10.7 violation.
[2.1.10]
New Features
Added the driver support for MCXN10 platform with combined interrupt handler.
[2.1.9]
Bug Fixes
Fixed MISRA-2012 rule 8.4.
[2.1.8]
Bug Fixes
Fixed MISRA-2012 rule 10.1 rule 10.4 rule 10.8 rule 18.1 rule 20.9.
[2.1.7]
Improvements
Added fully support for the SECPINT, making it can be used just like PINT.
[2.1.6]
Bug Fixes
Fixed the bug of not enabling common pint clock when enabling security pint clock.
[2.1.5]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule 10.1 rule 10.3 rule 10.4 rule 10.8 rule 14.4.
Changed interrupt init order to make pin interrupt configuration more reasonable.
[2.1.4]
Improvements
Added feature to control distinguish PINT/SECPINT relevant interrupt/clock configurations for PINT_Init and PINT_Deinit API.
Swapped the order of clearing PIN interrupt status flag and clearing pending NVIC interrupt in PINT_EnableCallback and PINT_EnableCallbackByIndex function.
Bug Fixes
Fixed build issue caused by incorrect macro definitions.
[2.1.3]
Bug fix:
Updated PINT_PinInterruptClrStatus to clear PINT interrupt status when the bit is asserted and check whether was triggered by edge-sensitive mode.
Write 1 to IST corresponding bit will clear interrupt status only in edge-sensitive mode and will switch the active level for this pin in level-sensitive mode.
Fixed MISRA c-2012 rule 10.1, rule 10.6, rule 10.7.
Added FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS to distinguish IRQ relevant array definitions for SECPINT/PINT on lpc55s69 board.
Fixed PINT driver c++ build error and remove index offset operation.
[2.1.2]
Improvement:
Improved way of initialization for SECPINT/PINT in PINT_Init API.
[2.1.1]
Improvement:
Enabled secure pint interrupt and add secure interrupt handle.
[2.1.0]
Added PINT_EnableCallbackByIndex/PINT_DisableCallbackByIndex APIs to enable/disable callback by index.
[2.0.2]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.1]
Bug fix:
Updated PINT driver to clear interrupt only in Edge sensitive.
[2.0.0]
Initial version.
PLU
[2.2.1]
Bug Fixes
Fixed MISRA C-2012 rule 10.3 and rule 17.7.
[2.2.0]
Bug Fixes
Fixed wrong parameter of the PLU_EnableWakeIntRequest function.
[2.1.0]
New Features
Added 4 new APIs to support Niobe4’s wake-up/interrupt control feature, including PLU_GetDefaultWakeIntConfig() PLU_EnableWakeIntRequest(), PLU_LatchInterrupt() and PLU_ClearLatchedInterrupt().
Other Changes
Changed the register name LUT_INP to LUT_INP_MUX due to register map update.
[2.0.1]
New Features
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
PORT
[2.5.1]
Bug Fixes
Fix CERT INT31-C issues.
[2.5.0]
Bug Fixes
Correct the kPORT_MuxAsGpio for some platforms.
[2.4.1]
Bug Fixes
Fixed the violations of MISRA C-2012 rules: 10.1, 10.8 and 14.4.
[2.4.0]
New Features
Updated port_pin_config_t to support input buffer and input invert.
[2.3.0]
New Features
Added new APIs for Electrical Fast Transient(EFT) detect.
Added new API to configure port voltage range.
[2.2.0]
New Features
Added new api PORT_EnablePinDoubleDriveStrength.
[2.1.1]
Bug Fixes
Fixed the violations of MISRA C-2012 rules: 10.1, 10.4，11.3，11.8, 14.4.
[2.1.0]
New Features
Updated the driver code to adapt the case of the interrupt configurations in GPIO module. Will move the pin configuration APIs to GPIO module.
[2.0.2]
Other Changes
Added feature guard macros in the driver.
[2.0.1]
Other Changes
Added “const” in function parameter.
Updated some enumeration variables’ names.
POWERQUAD
[2.2.0]
New Features
Added new API PQ_Arctan2Fixed.
[2.1.1]
Bug Fixes
Remove PQ_WaitDone from PQ_ArctanFixed and PQ_ArctanhFixed because it is unnecessary.
[2.1.0]
Improvements
Fixed typo issue for biquad related function name.
Changed operator from “%” into “&” to reduce heavy cycle for biquad functions.
[2.0.5]
Improvements
Added a note in driver for FIR that powerquad has a hardware limitation, when using it for FIR increment calculation, the address of pSrc needs to be a continuous address.
[2.0.4]
Improvements
Supported the platforms which don’t have PowerQuad clock and reset control.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.1, 10.3, 10.4, 10.6, and so on.
[2.0.2]
Bug Fixes
Fixed array size issue in fsl_powerquad_data.h file.
Fixed vector function pipeline issue.
[2.0.1]
Bug Fixes
Fixed build error in C++ mode.
[2.0.0]
Initial version.
PUFv3
[2.0.3]
Update for various PUF CTRL wrapper.
[2.0.2]
Fix MISRA issue in driver.
[2.0.1]
Fix PUF initialization issue and update driver to reflect SoC header changes.
[2.0.0]
Initial version.
PWM
[2.9.0]
Improvements
Support PWMX channel output for edge aligned PWM.
Forbid submodule 0 counter initialize with master sync and master reload mode.
[2.8.4]
Improvements
Support workaround for ERR051989. This function helps realize no phase delay between submodule 0 and other submodule.
[2.8.3]
Bug Fixes
Fixed MISRA C-2012 Rule 15.7
[2.8.2]
Bug Fixes
Fixed warning conversion from ‘int’ to ‘uint16_t’ on API PWM_Init.
Fixed warning unused variable ‘reg’ on API PWM_SetPwmForceOutputToZero.
[2.8.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.8.0]
Improvements
Added API PWM_UpdatePwmPeriodAndDutycycle to update the PWM signal’s period and dutycycle for a PWM submodule.
Added API PWM_SetPeriodRegister and PWM_SetDutycycleRegister to merge duplicate code in API PWM_SetupPwm, PWM_UpdatePwmDutycycleHighAccuracy and PWM_UpdatePwmPeriodAndDutycycle
[2.7.1]
Improvements
Supported UPDATE_MASK bit in MASK register.
[2.7.0]
Improvements
Supported platforms which don’t have Capture feature with channel A and B.
Supported platforms which don’t have Submodule 3.
Added assert function in API PWM_SetPhaseDelay to prevent wrong argument.
[2.6.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3.
[2.6.0]
Improvements
Added API PWM_SetPhaseDelay to set the phase delay from the master sync signal of submodule 0.
Added API PWM_SetFilterSampleCountthe to set number of consecutive samples that must agree prior to the input filter.
Added API PWM_SetFilterSamplePeriod to set set the sampling period of the fault pin input filter.
[2.5.1]
Bug Fixes
Fixed MISRA C-2012 rules: 10.1, 10.3, 10.4 , 10.6 and 10.8.
Fixed the issue that PWM_UpdatePwmDutycycle() can’t update duty cycle status value correct.
[2.5.0]
Improvements
Added API PWM_SetOouputToIdle to set pwm channel output to idle.
Added API PWM_GetPwmChannelState to get the pwm channel output duty cycle value.
Added API PWM_SetPwmForceOutputToZero to set the pwm channel output to zero logic.
Added API PWM_SetChannelOutput to set the pwm channel output state.
Added API PWM_SetClockMode to set the value of the clock prescaler.
Added API PWM_SetupPwmPhaseShift to set PWM which a special phase shift and 50% duty cycle.
Added API PWM_SetVALxValue/PWM_GetVALxValue to set/get PWM VALs registers values directly.
[2.4.0]
Improvements
Supported the PWM which can’t work in wait mode.
[2.3.0]
Improvements
Add PWM output enable&disbale API for SDK.
Bug Fixes
Fixed changing channel B configuration when parameter is kPWM_PWMX and PWMX configuration is not supported yet.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3, 10.4.
Bug Fixes
Fixed the issue that PWM drivers computed VAL1 improperly.
Improvements
Updated calculation accuracy of reloadValue in dutyCycleToReloadValue function.
[2.2.0]
Improvements
Added new enumeration and two APIs to support enabling and disabling one or more PWM output triggers.
Added a new function to make the most of 16-bit resolution PWM.
Added one API to support updating fault status of PWM output.
Added one API to support PWM DMA write request.
Added three APIs to support PWM DMA capture read request.
Added one API to support get default fault config of PWM.
Added one API to support setting PWM fault disable mapping.
[2.1.0]
Improvements
Moved the configuration of fault input filter into a new API to avoid be initialized multiple times.
Bug Fixes
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.2, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-14.4, rule-16.4.
[2.0.1]
Bug Fixes
Fixed the issue that PWM submodule may be initialized twice in function PWM_SetupPwm().
[2.0.0]
Initial version.
QDC
[2.0.0]
Initial version. Rename from driver ENC.
RESET
[2.4.0]
Improvements
Add RESET_ReleasePeripheralReset API.
[1.0.0]
Initial version.
SAI
[2.4.4]
Bug Fixes
Fixed enumeration sai_fifo_combine_t - add RX configuration.
[2.4.3]
Bug Fixes
Fixed enumeration sai_fifo_combine_t value configuration issue.
[2.4.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.4.1]
Bug Fixes
Fixed bitWidth incorrectly assigned issue.
[2.4.0]
Improvements
Removed deprecated APIs.
[2.3.8]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.3.7]
Improvements
Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.
Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function
[2.3.6]
Bug Fixes
Fixed violations of MISRA C-2012 rule 5.6.
[2.3.5]
Improvements
Make driver to be aarch64 compatible.
[2.3.4]
Bug Fixes
Corrected the fifo combine feature macro used in driver.
[2.3.3]
Bug Fixes
Added bit clock polarity configuration when sai act as slave.
Fixed out of bound access coverity issue.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.3.2]
Bug Fixes
Corrected the frame sync configuration when sai act as slave.
[2.3.1]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
Fixed violations of MISRA C-2012 rule 17.7.
[2.3.0]
Bug Fixes
Fixed the build error caused by the SOC has no fifo feature.
[2.2.3]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
[2.2.2]
Bug Fixes
Fixed the issue of MISRA 2004 rule 9.3.
Fixed sign-compare warning.
Fixed the PA082 build warning.
Fixed sign-compare warning.
Fixed violations of MISRA C-2012 rule 10.3,17.7,10.4,8.4,10.7,10.8,14.4,17.7,11.6,10.1,10.6,8.4,14.3,16.4,18.4.
Allow to reset Rx or Tx FIFO pointers only when Rx or Tx is disabled.
Improvements
Added 24bit raw audio data width support in sai sdma driver.
Disabled the interrupt/DMA request in the SAI_Init to avoid generates unexpected sai FIFO requests.
[2.2.1]
Improvements
Added mclk post divider support in function SAI_SetMasterClockDivider.
Removed useless configuration code in SAI_RxSetSerialDataConfig.
Bug Fixes
Fixed the SAI SDMA driver build issue caused by the wrong structure member name used in the function SAI_TransferRxSetConfigSDMA/SAI_TransferTxSetConfigSDMA.
Fixed BAD BIT SHIFT OPERATION issue caused by the FSL_FEATURE_SAI_CHANNEL_COUNTn.
Applied ERR05144: not set FCONT = 1 when TMR > 0, otherwise the TX may not work.
[2.2.0]
Improvements
Added new APIs for parameters collection and simplified user interfaces:
SAI_Init
SAI_SetMasterClockConfig
SAI_TxSetBitClockRate
SAI_TxSetSerialDataConfig
SAI_TxSetFrameSyncConfig
SAI_TxSetFifoConfig
SAI_TxSetBitclockConfig
SAI_TxSetConfig
SAI_TxSetTransferConfig
SAI_RxSetBitClockRate
SAI_RxSetSerialDataConfig
SAI_RxSetFrameSyncConfig
SAI_RxSetFifoConfig
SAI_RxSetBitclockConfig
SAI_RXSetConfig
SAI_RxSetTransferConfig
SAI_GetClassicI2SConfig
SAI_GetLeftJustifiedConfig
SAI_GetRightJustifiedConfig
SAI_GetTDMConfig
[2.1.9]
Improvements
Improved SAI driver comment for clock polarity.
Added enumeration for SAI for sample inputs on different edges.
Changed FSL_FEATURE_SAI_CHANNEL_COUNT to FSL_FEATURE_SAI_CHANNEL_COUNTn(base) for the difference between the different SAI instances.
Added new APIs:
SAI_TxSetBitClockDirection
SAI_RxSetBitClockDirection
SAI_RxSetFrameSyncDirection
SAI_TxSetFrameSyncDirection
[2.1.8]
Improvements
Added feature macro test for the sync mode2 and mode 3.
Added feature macro test for masterClockHz in sai_transfer_format_t.
[2.1.7]
Improvements
Added feature macro test for the mclkSource member in sai_config_t.
Changed “FSL_FEATURE_SAI5_SAI6_SHARE_IRQ” to “FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ”.
Added #ifndef #endif check for SAI_XFER_QUEUE_SIZE to allow redefinition.
Bug Fixes
Fixed build error caused by feature macro test for mclkSource.
[2.1.6]
Improvements
Added feature macro test for mclkSourceClockHz check.
Added bit clock source name for general devices.
Bug Fixes
Fixed incorrect channel numbers setting while calling RX/TX set format together.
[2.1.5]
Bug Fixes
Corrected SAI3 driver IRQ handler name.
Added I2S4/5/6 IRQ handler.
Added base in handler structure to support different instances sharing one IRQ number.
New Features
Updated SAI driver for MCR bit MICS.
Added 192 KHZ/384 KHZ in the sample rate enumeration.
Added multi FIFO interrupt/SDMA transfer support for TX/RX.
Added an API to read/write multi FIFO data in a blocking method.
Added bclk bypass support when bclk is same with mclk.
[2.1.4]
New Features
Added an API to enable/disable auto FIFO error recovery in platforms that support this feature.
Added an API to set data packing feature in platforms which support this feature.
[2.1.3]
New Features
Added feature to make I2S frame sync length configurable according to bitWidth.
[2.1.2]
Bug Fixes
Added 24-bit support for SAI eDMA transfer. All data shall be 32 bits for send/receive, as eDMA cannot directly handle 3-Byte transfer.
[2.1.1]
Improvements
Reduced code size while not using transactional API.
[2.1.0]
Improvements
API name changes:
SAI_GetSendRemainingBytes -> SAI_GetSentCount.
SAI_GetReceiveRemainingBytes -> SAI_GetReceivedCount.
All names of transactional APIs were added with “Transfer” prefix.
All transactional APIs use base and handle as input parameter.
Unified the parameter names.
Bug Fixes
Fixed WLC bug while reading TCSR/RCSR registers.
Fixed MOE enable flow issue. Moved MOE enable after MICS settings in SAI_TxInit/SAI_RxInit.
[2.0.0]
Initial version.
SAI_EDMA
[2.7.1]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.7.0]
Improvements
Updated api SAI_TransferReceiveEDMA to support voice channel block interleave transfer.
Updated api SAI_TransferSendEDMA to support voice channel block interleave transfer.
Added new api SAI_TransferSetInterleaveType to support channel interleave type configurations.
[2.6.0]
Improvements
Removed deprecated APIs.
[2.5.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 20.7.
[2.5.0]
Improvements
Added new api SAI_TransferSendLoopEDMA/SAI_TransferReceiveLoopEDMA to support loop transfer.
Added multi sai channel transfer support.
[2.4.0]
Improvements
Added new api SAI_TransferGetValidTransferSlotsEDMA which can be used to get valid transfer slot count in the sai edma transfer queue.
Deprecated the api SAI_TransferRxSetFormatEDMA and SAI_TransferTxSetFormatEDMA.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3,10.4.
[2.3.2]
Refer SAI driver change log 2.1.0 to 2.3.2
SCTIMER
[2.5.1]
Bug Fixes
Fixed bug in SCTIMER_SetupCaptureAction: When kSCTIMER_Counter_H is selected, events 12-15 and capture registers 12-15 CAPn_H field can’t be used.
[2.5.0]
Improvements
Add SCTIMER_GetCaptureValue API to get capture value in capture registers.
[2.4.9]
Improvements
Supported platforms which don’t have system level SCTIMER reset.
[2.4.8]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t writes MATCH_H bit and RELOADn_H.
[2.4.7]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t configure 100% duty cycle PWM.
[2.4.6]
Bug Fixes
Fixed the issue where the H register was not written as a word along with the L register.
Fixed the issue that the SCTIMER_SetCOUNTValue() is not configured with high 16 bits in unify mode.
[2.4.5]
Bug Fixes
Fix SCT_EV_STATE_STATEMSKn macro build error.
[2.4.4]
Bug Fixes
Fix MISRA C-2012 issue 10.8.
[2.4.3]
Bug Fixes
Fixed the wrong way of writing CAPCTRL and REGMODE registers in SCTIMER_SetupCaptureAction.
[2.4.2]
Bug Fixes
Fixed SCTIMER_SetupPwm 100% duty cycle issue.
[2.4.1]
Bug Fixes
Fixed the issue that MATCHn_H bit and RELOADn_H bit could not be written.
[2.4.0]
[2.3.0]
Bug Fixes
Fixed the potential overflow issue of pulseperiod variable in SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle API.
Fixed the issue of SCTIMER_CreateAndScheduleEvent API does not correctly work with 32 bit unified counter.
Fixed the issue of position of clear counter operation in SCTIMER_Init API.
Improvements
Update SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle to support generate 0% and 100% PWM signal.
Add SCTIMER_SetupEventActiveDirection API to configure event activity direction.
Update SCTIMER_StartTimer/SCTIMER_StopTimer API to support start/stop low counter and high counter at the same time.
Add SCTIMER_SetCounterState/SCTIMER_GetCounterState API to write/read counter current state value.
Update APIs to make it meaningful.
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
[2.2.0]
Improvements
Updated for 16-bit register access.
[2.1.3]
Bug Fixes
Fixed the issue of uninitialized variables in SCTIMER_SetupPwm.
Fixed the issue that the Low 16-bit and high 16-bit work independently in SCTIMER driver.
Improvements
Added an enumerable macro of unify counter for user.
kSCTIMER_Counter_U
Created new APIs for the RTC driver.
SCTIMER_SetupStateLdMethodAction
SCTIMER_SetupNextStateActionwithLdMethod
SCTIMER_SetCOUNTValue
SCTIMER_GetCOUNTValue
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
Deprecated legacy APIs for the RTC driver.
SCTIMER_SetupNextStateAction
[2.1.2]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7, 11.9, 14.2 and 15.5.
[2.1.1]
Improvements
Updated the register and macro names to align with the header of devices.
[2.1.0]
Bug Fixes
Fixed issue where SCT application level Interrupt handler function is occupied by SCT driver.
Fixed issue where wrong value for INSYNC field inside SCTIMER_Init function.
Fixed issue to change Default value for INSYNC field inside SCTIMER_GetDefaultConfig.
[2.0.1]
New Features
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
SEMA42
[2.0.4]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]
Improvements
Changed to implement SEMA42_Lock base on SEMA42_TryLock.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 18.1.
[2.0.0]
Initial version.
SMARTCARD
[2.3.0]
New features:
Added support for USIM
[2.2.2]
Bug fix:
Fixed MISRA C-2012 rule 10.4.
[2.2.1]
Bug fix:
Fixed IAR warnings Pa082 in smartcard_emvsim
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.6, 10.7, 10.8, 14.4, 16.1, 16.3, 16.4, 17.7
[2.2.0]
New features:
Updated to use RX/TX FIFO
[2.1.2]
Provided time delay function which works in microseconds.
Bug fix:
Changed event to semaphore in RTOS driver (KPSDK-11634).
Added check if de-initialized variables are not null iSMARTCARD_RTOS_Deinit() (KPSDK-8788).
Changed deactivation sequence iSMARTCARD_PHY_TDA8035_Deactivate() to properly stop the clockPOSCR-35).
Fixed timing issue with VSEL0/1 signals in smartcard TDA803driver (KPSDK-10160)
[2.1.1]
New features:
Added default phy interface selection into smartcard RTOS drivers (KPSDK-9063).
Replaced smartcard_phy_ncn8025 driver by smartcard_phy_tda8035.
Bug fix:
Fixed protocol timers activation sequences in smartcard_emvsim and smartcard_phy_tda8035 drivers during emvl1 pre-certification tests (KPSDK-9170, KPSDK-9556).
[2.1.0]
Initial version.
SMARTDMA
[2.11.0]
Improvements
Make the RT500 QSPI firmware can work with other display firmware in the same project.
[2.10.0]
New Features
Added new camera APIs for MCXN SoCs to support more resolutions.
[2.9.1]
New Features
Supported MCXN235, MCXN236.
[2.9.0]
New Features
Supported MCXN camera functions.
Supported user to select individual firmware for MIPI or FLEXIO alone, or both.
Added new API of enabling DMA from FlexIO to a Buffer.
Added new APIs of setting MIPI-DSI to enter and exit ultra low power state.
[2.8.0]
New Features
Supported converting the pixel data from RGB565 to RGB888.
Supported function to turn off certain pixel in a checker board pattern.
[2.7.0]
New Features
Supported data transfer in 2-dimensional way.
Supported data transfer in XRGB8888 format and rotate 180 degree.
Supported to fill data in whenever there is room in MIPI controller’s FIFO rather than using the tx FIFO in double buffered way.
[2.6.3]
Bug Fixes
Fixed EZH_MIPIDSI_RGB565_DMA, EZH_MIPIDSI_RGB888_DMA, EZH_MIPIDSI_ARGB8888toRGB888_DMA issues that don’t support some length.
[2.6.2]
Bug Fixes
Fixed MISRA C-2012 issues: 8.4, 11.6, 17.7.
[2.6.1]
Improvements
Optimized MIPI DSI APIs performance.
[2.6.0]
Improvements
Optimized MIPI DSI APIs performance.
New Features
Added new APIs to send MIPI DSI frame with 180 degree rotation.
[2.5.0]
Improvements
Supported swap or don’t swap the pixel byte before written to MIPI DSI FIFO.
Updated MIPI DSI firmware, make sure data has been sent out before calling callback function.
[2.4.0]
Improvements
Added new APIs for MIPI DSI kSMARTDMA_MIPI_XRGB2RGB_DMA.
[2.3.0]
Improvements
Added new APIs for FlexIO one SHIFTBUF, kSMARTDMA_FlexIO_DMA_ONELANE.
Bug Fixes
Fixed kSMARTDMA_MIPI_RGB565_DMA color bias issue.
[2.2.0]
Improvements
Added new APIs for MIPI DSI, kSMARTDMA_MIPI_RGB565_DMA and kSMARTDMA_MIPI_RGB888_DMA.
Supported install firmware and callback function dynamically.
[2.1.0]
Improvements
Removed test APIs, including kSMARTDMA_LightOn, kSMARTDMA_LightOff, kSMARTDMA_Notify, and kSMARTDMA_Test.
Added new APIs, including kSMARTDMA_FlexIO_DMA_Reverse, kSMARTDMA_FlexIO_DMA_ARGB2RGB, kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, and kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse.
[2.0.0]
Initial version.
MCX_SPC
[2.7.0]
New Features
Added new function to unretain RAM array.
[2.6.0]
Bug Fixes
The enumeration kSPC_DeepPowerDownWithSysClockOff should be 0x8U.
New Features
Added functions to get the last low-power mode that the power domain requested.
[2.5.0]
Improvements
Updated SPC_SetLowPowerModeCoreLDORegulatorConfig() with adding check that LP_CFG[CORELDO_VDD_LVL] only be updated when CORELDO is in normal driver strength in active mode.
Updated SPC_SetLowPowerModeRegulatorsConfig() with adding check the if DCDC voltage level set as retention mode, CORELDO low voltage detection must be disabled.
Updated spc_analog_module_control with adding Opamp3 support.
New Features
Added functions to mask/unmask voltage detections in active mode.
[2.4.2]
Improvements
Fixed the violation of MISRA C-2012 rules.
[2.4.1]
Improvements
Fixed the violation of MISRA C-2012 rules.
[2.4.0]
Improvements
Refined APIs to set regulators, the input parameters will be check firstly before setting register.
Improved APIs’ document.
Removed software check for DCDC’s settings since there is not hardware restrictions for DCDC.
Added new APIs to check if glitch detector is enabled in active/low power mode.
Added new APIs for DCDC burst feature, make it more flexible to use.
Added new API to enable/disable DCDC bleed resistor.
Set functions of VD_SYS_CFG[LVSEL] configuration as deprecated, since this bit filed is reserved for all devices.
Updated details of spc_core_ldo_voltage_level_t to align with description of latest RM, added comments to reminder users that the retention voltage is reserved in some devices.
[2.3.0]
New Features
Updated glitch detect API to support devices which do not have aGDET
[2.2.1]
Bug Fixes
Fixed an issue of SPC_SetActiveModeRegulatorsConfig() which will cause LVD in case of setting DCDC and CORE LDO into higher voltage level.
[2.2.0]
New Features
Added some macros to support some devices(such as MCXA family) do not equipped DCDC, SYS_LDO and so on.
Added new function SPC_EnableSRAMLdOLowPowerModeIREF(), SPC_TrimSRAMLdoRefVoltage(), SPC_EnableSRAMLdo() to support some devices(such as MCXA family) that support control of SRAM_LDO.
Fixed violation of MISRA C-2012 rule 17.7.
Fixed an issue in SPC_SetLowPowerModeRegulatorsConfig() function that set ACTIVE_CFG register by mistake.
[2.1.0]
Improvements
Added new functions to set regulators’ voltage level and drive strength individually.
Updated SPC_SetActiveModeRegulatorsConfig() and SPC_SetLowPowerModeRegulatorsConfig() based on new added functions.
[2.0.1]
Bug Fixes
Fixed a bug that external burst not working properly.
Fixed a bug that is SPC has VDD_DS the voltage is not configured correctly.
[2.0.0]
Initial version.
SYSPM
[2.3.0]
New Features
Supported instruction counter.
[2.2.0]
New Features
Supported platforms which only have one monitor.
Supported platforms whose instrction counter can’t be cleared.
Supported platforms whose counter can’t be disabled.
[2.1.0]
New Features
Added new APIs SYSPM_Init and SYSPM_Deinit.
[2.0.0]
Initial version.
TDET
[2.2.0]
Added support for chips without active tamper pins.
[2.1.1]
Added clearing SR_TAF and SR_DTF into TDET_Init().
Fix typo in kTDET_ClockType64Hz comment.
[2.1.0]
Added setting of disabling prescaler on tamper event into TDET_SetConfig() and TDET_GetDefaultConfig functions.
[2.0.0]
Initial version.
TRDC
[2.2.1]
Bug Fixes:
Fix MISRA violations.
[2.2.0]
New Features:
Supported SoCs that do not have all TRDC modules.
[2.1.0]
Bug Fixes:
Fix MISRA violations.
Fixed wrong operation of domain mask in TRDC_MbcNseClearAll and TRDC_MrcDomainNseClear.
[2.0.0]
Initial version.
TRDC_SOC
[1.0.0]
Initial version.
TSI_V6
[2.0.0]
Initial version.
USDHC
[2.8.4]
Improvements
Add feature macro FSL_FEATURE_USDHC_HAS_NO_VS18.
[2.8.3]
Improvements
Improved api USDHC_EnableAutoTuningForCmdAndData to adapt to new bit field name for USDHC_VEND_SPEC2 register.
[2.8.2]
Improvements
Added feature macro FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT.
[2.8.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9.
[2.8.0]
Improvements
Fixed the mmc boot transfer failed issue which is caused by the Dma complete interrupt not enabled.
Marked api USDHC_AdjustDelayForManualTuning as deprecated and added new api USDHC_SetTuingDelay/USDHC_GetTuningDelayStatus.
Improved the manual tuning flow accroding to specification.
Added memory address conversion to support buffers which could only be accessed using alias address by non-core masters.
Fixed violations of MISRA C-2012 rule 10.4.
[2.7.0]
Improvements
Added api USDHC_TransferScatterGatherADMANonBlocking to support scatter gather transfer.
Added feature FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER for re-tuning time counter field in HOST_CTRL_CAP register.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 10.1, 10.3, 10.4, 8.4.
[2.6.0]
Improvements
Added api USDHC_SetStandardTuningCounter to support adjust tuning counter of Standard tuning.
[2.5.1]
Improvements
Used different status code for command and data interrupt callback.
Added cache line invalidate for receive buffer in driver IRQ handler to fix CM7 speculative access issue.
[2.5.0]
Improvements
Added new api USDHC_SetStrobeDllOverride for HS400 strobe dll override mode delay taps configurations.
Corrected the STROBE DLL configurations sequence.
[2.4.0]
Improvements
Added feature macro for read/write burst length.
Disabled redundant interrupt per different transfer request.
Disabled interrupt and reset command/data pointer in handle when transfer completes.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3.
Fixed PA082 build warning.
Fixed logically dead code Coverity issue.
[2.3.0]
Improvements
Added USDHC_SetDataConfig API to support manual tuning.
Removed the limitaion that source clock must be bigger than the target in function USDHC_SetSdClock by using source clock frequency as target directly.
Added peripheral reset in USDHC_Init function.
Added tuning reset support in function USDHC_Reset function.
[2.2.8]
Bug Fixes
Fixed out-of bounds write in function USDHC_ReceiveCommandResponse.
[2.2.7]
Improvements
Added API USDHC_GetEnabledInterruptStatusFlags and used in USDHC_TransferHandleIRQ.
Removed useless member interruptFlags in usdhc_handle_t.
[2.2.6]
Improvements
Added address align check for ADMA descriptor table address.
Changed USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY to (65536-4096) to make sure the data address is 4KB align for a transfer which need more than one ADMA1 descriptor.
[2.2.5]
Bug Fixes
Fixed MDK 66-D warning.
[2.2.4]
Bug Fixes
Fixed issue that real clock frequency wss mismatched with target clock frequency, which was caused by an incorrect prescaler calculation.
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.2.3]
Bug Fixes
Fixed issue where AMDA did not disable with DMAEN clear.
Improvements
Improved set clock function to check the output frequency range.
Dynamic set SDCLKFS during DDR enable or disable.
[2.2.2]
Improvements
Improved read transfer cache maintain operation, combined clean, and invalidated them into one function.
[2.2.1]
Bug Fixes
Disabled the invalidate cache operation for tuning.
[2.2.0]
Improvements
Improved USDHC to support MMC boot feature.
[2.1.3]
Bug Fixes
Fixed MISRA issue.
[2.1.2]
Bug Fixes
Fixed Coverity issue.
Added base address and userData parameter for all callback functions.
[2.1.1]
Improvements
Added cache maintain operation.
Added timeout status check for the DATA transfer which ignore error.
Added feature macro for SDR50/SDR104 mode.
Removed useless IRQ handler from different platforms.
[2.1.0]
Improvements
Integrated tuning into transfer function.
Added strobe DLL feature.
Added enableAutoCommand23 in data structure.
Removed enable card clock function because the controller would handle the clock on/off.
[2.0.0]
Initial version.
UTICK
[2.0.5]
Improvements
Improved for SOC RW610.
[2.0.4]
Bug Fixes
Fixed compile fail issue of no-supporting PD configuration in utick driver.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 8.4, 14.4, 17.7
[2.0.2]
Added new feature definition macro to enable/disable power control in drivers for some devices have no power control function.
[2.0.1]
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
MCX_VBAT
[2.3.1]
Bug Fixes
Fixed violations of MISRA C-2012 low impact rules.
[2.3.0]
Improvements
OSCCTLA[FINE_AMP_GAIN] is reserved, added new macro to support this change.
Defined VBAT_LDORAMC_RET in case of this macro is not defined in header file.
Bug Fixes
Fixed violaltions of MISRA C-2012 rule 10.8.
[2.2.0]
Improvements
Added macros to support some devices(such as MCXA family) that do not support OSC control, LDO control, bandgap timer, and tamper.
[2.1.0]
New features
Added functions to support tamper and clock monitor.
[2.0.0]
Initial version.
VREF
[2.4.0]
Improvements
Support TEST_UNLOCK and TRIM0 registers read and write.
[2.3.0]
Improvements
Add feature macros for compatibility with some platforms that don’t have CSR[LPBG_BUF_EN] and UTRIM[TRIM2V1].
[2.2.2]
Bug Fixes
Fixed typo in vref_buffer_mode_t enumerator.
[2.2.1]
Improvements
Updated VREF driver code to reduce code redundancy.
[2.2.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
[2.1.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
Bug Fixes
Fix issue which progeam stuck in VREF_Init
[2.0.0]
Initial version.
WUU
[2.4.0]
New Features
Added WUU_ClearExternalWakeupPinsConfig() to clear settings of PDC and PE register.
[2.3.0]
New Features
Added WUU_ClearInternalWakeUpModulesConfig() to clear settings of DM and ME register.
[2.2.1]
Bug Fixes
Fixed WUU_SetPinFilterConfig() unable to set edge detection of pin filter config.
Fixed wrong macro used in WUU_GetPinFilterFlag() function.
[2.2.0]
New Features
Added the WUU_GetExternalWakeupPinFlag() and WUU_ClearExternalWakeupPinFlag() function .
[2.1.0]
New Features
Added the WUU_GetModuleInterruptFlag() function to support the devices that equipped MF register.
[2.0.0]
Initial version.
WWDT
[2.1.9]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 10.4.
[2.1.8]
Improvements
Updated the “WWDT_Init” API to add wait operation. Which can avoid the TV value read by CPU still be 0xFF (reset value) after WWDT_Init function returns.
[2.1.7]
Bug Fixes
Fixed the issue that the watchdog reset event affected the system from PMC.
Fixed the issue of setting watchdog WDPROTECT field without considering the backwards compatibility.
Fixed the issue of clearing bit fields by mistake in the function of WWDT_ClearStatusFlags.
[2.1.5]
Bug Fixes
deprecated a unusable API in WWWDT driver.
WWDT_Disable
[2.1.4]
Bug Fixes
Fixed violation of the MISRA C-2012 rules Rule 10.1, 10.3, 10.4 and 11.9.
Fixed the issue of the inseparable process interrupted by other interrupt source.
WWDT_Init
[2.1.3]
Bug Fixes
Fixed legacy issue when initializing the MOD register.
[2.1.2]
Improvements
Updated the “WWDT_ClearStatusFlags” API and “WWDT_GetStatusFlags” API to match QN9090. WDTOF is not set in case of WD reset. Get info from PMC instead.
[2.1.1]
New Features
Added new feature definition macro for devices which have no LCOK control bit in MOD register.
Implemented delay/retry in WWDT driver.
[2.1.0]
Improvements
Added new parameter in configuration when initializing WWDT module. This parameter, which must be set, allows the user to deliver the WWDT clock frequency.
[2.0.0]
Initial version.