power_mode_switch#
Overview#
This demo is used to show all the power modes in core 0 (the primary core in dual_core SoC). With this demo, user can navigate all the power modes that are existing in core 0. In typical use case, the primary core is running the main control logic, while the secondary core is used to run the protocol or other complex mid-ware independently. Then the secondary core prepares the resource (data, message, etc) into the somewhere, so that the primary core would fetch when necessary. In some other cases, primary core would send the some kinds of message to the secondary core, and ask the secondary core to enter indicated power mode. This demo download the image to both core, also provides the reference code to enter any power mode.
Supported Boards#
FRDM-K32L3A6
Hardware requirements
FRDM-K32L3A6 board
Personal Computer
Prepare the demo
Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
Open a serial terminal with the following settings:
115200 baud rate
8 data bits
No parity
One stop bit
No flow control
Set the SoC booting up from core 0 (CM4 core), since the program would be downloaded and run in core 0.
Build the core 1’s image first and build the core 0’s image with core 1’s image linked inside.
Download the program to the target board.
Press the reset button on your board to begin running the demo.
Don’t debug dual core at the same time, because cm0plus is in VLLS0 and could not be connected.
Running the demo
In this demo, cm4 core is used as the primary core, which would boot from reset. The cm0plus core would be awaken up when cm4 core executes it. Then the cm0plus core would enter the VLLS0 mode. When the demo runs successfully, the log would be seen on the OpenSDA terminal like as below and LED will blink:
Power Mode Switch demo - dual core, core 0.
Boot up another core, core 1 ...
Core 1 is booted up now.
Shake hands done.
**************************************************************************
###### Power mode: RUN
- A: kAPP_PowerModeRun
- B: kAPP_PowerModeWait
- C: kAPP_PowerModeStop
- D: kAPP_PowerModeVlpr
- E: kAPP_PowerModeVlpw
- F: kAPP_PowerModeVlps
- G: kAPP_PowerModeLls
- H: kAPP_PowerModeVlls2
- I: kAPP_PowerModeVlls0
- J: kAPP_PowerModeHsrun
Input A to J:
MIMXRT700-EVK
Hardware requirements
Micro USB cable
MIMXRT700-EVK board
Personal Computer
Board settings
JP7(2-3) connected for 3.3V supply for VDDIO_2. JP55(1-2) disconnected to ommit the impact of MCU-LINK during DPD and FDPD mode.
The board supports multiple power supply options. The code should be aligned with power supply on the board.
VDDN supplied by internal DCDC, VDD1 and VDD2 by PMC LDOs. Jumper setting - JP1(Open), JP2(1-2), JP3(Open), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_PMC
VDDN supplied by PMIC, VDD1 and VDD2 by PMC. Jumper setting - JP1(Open), JP2(2-3), JP3(Open), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_MIXED
Default power supply. Use PMIC to supply all. Jumper setting - JP1(1-2), JP2(2-3), JP3(1-2), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_PMIC
NOTE,
Please disconnect the debugger when measuring the power consumption.
When measuring power consumption for Full Deep Power Down mode, please power the board using 5V adapter and disconnect MCU-LINK and JP55 to ommit the impact of MCU-LINK circute.
Prepare the Demo
Connect a micro USB cable between the PC host and the MCU-LINK on the board
Open a serial terminal with the following settings:
115200 baud rate
8 data bits
No parity
One stop bit
No flow control
Build cm33_core1 project first, then the cm33_core0 project.
Download the core0 program to the target board.
Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
The log below shows the output of the demo in the terminal window: For cm33_core0:
#################### Power Mode Switch - CPU0 ####################
Build Time: xxx x 2024--16:45:55
Core Clock: 190000000Hz
Select an option
1. Sleep mode
2. Deep Sleep mode
3. Deep Sleep Retention mode
4. Deep power down mode
5. Full deep power down mode
6. Active test mode
For cm33_core1:
#################### Power Mode Switch - CPU1 ####################
Build Time: xxx x 2024--16:44:27
Core Clock: 96000000Hz
Select an option
1. Sleep mode
2. Deep Sleep mode
3. Deep Sleep Retention mode
4. Deep power down mode
5. Full deep power down mode
6. Active test mode
Notes,
When each of the CPU runs “6. Active test mode”, the other core is expected to be in Deep sleep or Deep Sleep Retention mode and should not change the power mode before the active test mode finished.
FRDM-IMXRT700
Hardware requirements
Type-C USB cable
FRDM-IMXRT700 board
Personal Computer
Board settings
JP7(2-3) connected for 3.3V supply for VDDIO_2. JP55(1-2) disconnected to ommit the impact of MCU-LINK during DPD and FDPD mode.
The board supports multiple power supply options. The code should be aligned with power supply on the board.
VDDN supplied by internal DCDC, VDD1 and VDD2 by PMC LDOs. Jumper setting - JP1(Open), JP2(1-2), JP3(Open), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_PMC
VDDN supplied by PMIC, VDD1 and VDD2 by PMC. Jumper setting - JP1(Open), JP2(2-3), JP3(Open), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_MIXED
Default power supply. Use PMIC to supply all. Jumper setting - JP1(1-2), JP2(2-3), JP3(1-2), JP4(1-2) Code setting(power_demo_config.h) - #define DEMO_POWER_SUPPLY_OPTION DEMO_POWER_SUPPLY_PMIC
NOTE,
Please disconnect the debugger when measuring the power consumption.
When measuring power consumption for Full Deep Power Down mode, please power the board using 5V adapter and disconnect MCU-LINK and JP55 to ommit the impact of MCU-LINK circute.
Prepare the Demo
Connect a USB cable between the PC host and the MCU-LINK on the board
Open a serial terminal with the following settings:
115200 baud rate
8 data bits
No parity
One stop bit
No flow control
Build cm33_core1 project first, then the cm33_core0 project.
Download the core0 program to the target board.
Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
The log below shows the output of the demo in the terminal window: For cm33_core0:
#################### Power Mode Switch - CPU0 ####################
Build Time: xxx x 2024--16:45:55
Core Clock: 190000000Hz
Select an option
1. Sleep mode
2. Deep Sleep mode
3. Deep Sleep Retention mode
4. Deep power down mode
5. Full deep power down mode
6. Active test mode
For cm33_core1:
#################### Power Mode Switch - CPU1 ####################
Build Time: xxx x 2024--16:44:27
Core Clock: 96000000Hz
Select an option
1. Sleep mode
2. Deep Sleep mode
3. Deep Sleep Retention mode
4. Deep power down mode
5. Full deep power down mode
6. Active test mode
Notes,
When each of the CPU runs “6. Active test mode”, the other core is expected to be in Deep sleep or Deep Sleep Retention mode and should not change the power mode before the active test mode finished.