ISSDK  1.7
IoT Sensing Software Development Kit
fxls8471q.h
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1 /*
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4  * Copyright 2016-2017 NXP
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34 
35 /**
36  * @file fxls8471q.h
37  * @brief The fxls8471q.h file contains the register definitions for fxls8471q sensor driver.
38  */
39 
40 #ifndef FXLS8471Q_H_
41 #define FXLS8471Q_H_
42 
43 /**
44  ** FXLS8471Q I2C Address
45  */
46 #define FXLS8471Q_I2C_ADDRESS_SA0_0_SA1_0 0x1E /*fxls8471q Address - SA0 = 0 and SA1 = 0*/
47 #define FXLS8471Q_I2C_ADDRESS_SA0_1_SA1_0 0x1D /*fxls8471q Address - SA0 = 1 and SA1 = 0*/
48 #define FXLS8471Q_I2C_ADDRESS_SA0_0_SA1_1 0x1C /*fxls8471q Address - SA0 = 0 and SA1 = 1*/
49 #define FXLS8471Q_I2C_ADDRESS_SA0_1_SA1_1 0x1F /*fxls8471q Address - SA0 = 1 and SA1 = 1*/
50 
51 /**
52  **
53  ** fxls8471q Sensor Internal Registers
54  */
55 enum {
56  FXLS8471Q_STATUS = 0x00, /* FMODE = 0, real time status */
57  FXLS8471Q_F_STATUS = 0x00, /* FMODE > 0, FIFO status */
58  FXLS8471Q_OUT_X_MSB = 0x01, /* data registers */
59  FXLS8471Q_OUT_X_LSB = 0x02, /* data registers */
60  FXLS8471Q_OUT_Y_MSB = 0x03, /* data registers */
61  FXLS8471Q_OUT_Y_LSB = 0x04, /* data registers */
62  FXLS8471Q_OUT_Z_MSB = 0x05, /* data registers */
63  FXLS8471Q_OUT_Z_LSB = 0x06, /* data registers */
64  FXLS8471Q_F_SETUP = 0x09, /* FIFO setup */
65  FXLS8471Q_TRIG_CFG = 0x0A, /* Map of FIFO data capture events */
66  FXLS8471Q_SYSMOD = 0x0B, /* SYSMOD System Mode register */
67  FXLS8471Q_INT_SOURCE = 0x0C, /* INT_SOURCE System Interrupt Status register */
68  FXLS8471Q_WHO_AM_I = 0x0D, /* WHO_AM_I Device ID register */
69  FXLS8471Q_XYZ_DATA_CFG = 0x0E, /* XYZ_DATA_CFG register */
70  FXLS8471Q_HP_FILTER_CUTOFF = 0x0F, /* FXLS8471Q only */
71  FXLS8471Q_PL_STATUS = 0x10, /* PL_STATUS Portrait/Landscape Status register */
72  FXLS8471Q_PL_CFG = 0x11, /* Portrait/Landscape Configuration register */
73  FXLS8471Q_PL_COUNT = 0x12, /* Portrait/Landscape Debounce register */
74  FXLS8471Q_PL_BF_ZCOMP = 0x13, /* PL_BF_ZCOMP Back/Front and Z Compensation register */
75  FXLS8471Q_PL_THS_REG = 0x14, /* P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register */
76  FXLS8471Q_A_FFMT_CFG = 0x15, /* A_FFMT_CFG Freefall/Motion Configuration register */
77  FXLS8471Q_A_FFMT_SRC = 0x16, /* A_FFMT_SRC Freefall/Motion Source register */
78  FXLS8471Q_A_FFMT_THS = 0x17, /* A_FFMT_THS Freefall and Motion Threshold register */
79  FXLS8471Q_A_FFMT_COUNT = 0x18, /* A_FFMT_COUNT Debounce register */
80  FXLS8471Q_TRANSIENT_CFG = 0x1D, /* Transient_CFG register */
81  FXLS8471Q_TRANSIENT_SRC = 0x1E, /* TRANSIENT_SRC register */
82  FXLS8471Q_TRANSIENT_THS = 0x1F, /* TRANSIENT_THS register */
83  FXLS8471Q_TRANSIENT_COUNT = 0x20, /* TRANSIENT_COUNT register */
84  FXLS8471Q_PULSE_CFG = 0x21, /* PULSE_CFG Pulse Configuration register */
85  FXLS8471Q_PULSE_SRC = 0x22, /* PULSE_SRC Pulse Source register */
86  FXLS8471Q_PULSE_THSX = 0x23, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
87  FXLS8471Q_PULSE_THSY = 0x24, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
88  FXLS8471Q_PULSE_THSZ = 0x25, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
89  FXLS8471Q_PULSE_TMLT = 0x26, /* PULSE_TMLT Pulse Time Window 1 register */
90  FXLS8471Q_PULSE_LTCY = 0x27, /* PULSE_LTCY Pulse Latency Timer register */
91  FXLS8471Q_PULSE_WIND = 0x28, /* PULSE_WIND register (Read/Write) */
92  FXLS8471Q_ASLP_COUNT = 0x29, /* ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write) */
93  FXLS8471Q_CTRL_REG1 = 0x2A, /* CTRL_REG1 System Control 1 register */
94  FXLS8471Q_CTRL_REG2 = 0x2B, /* CTRL_REG2 System Control 1 register */
95  FXLS8471Q_CTRL_REG3 = 0x2C, /* CTRL_REG3 Interrupt Control register */
96  FXLS8471Q_CTRL_REG4 = 0x2D, /* CTRL_REG4 Interrupt Enable register (Read/Write) */
97  FXLS8471Q_CTRL_REG5 = 0x2E, /* CTRL_REG5 Interrupt Configuration register (Read/Write) */
98  FXLS8471Q_OFF_X = 0x2F, /* OFF_X Offset Correction X register */
99  FXLS8471Q_OFF_Y = 0x30, /* OFF_Y Offset Correction Y register */
100  FXLS8471Q_OFF_Z = 0x31, /* OFF_Z Offset Correction Z register */
101  FXLS8471Q_A_VECM_CFG = 0x5F, /* A_VECM_CFG Acceleration vectormagnitude configuration register */
102  FXLS8471Q_A_VECM_THS_MSB = 0x60, /* A_VECM_THS_MSB Acceleration vectormagnitude threshold MSB */
103  FXLS8471Q_A_VECM_THS_LSB = 0x61, /* A_VECM_THS_LSB Acceleration vectormagnitude threshold LSB */
104  FXLS8471Q_A_VECM_CNT = 0x62, /* A_VECM_CNT Acceleration vectormagnitude debounce count */
105  FXLS8471Q_A_VECM_INITX_MSB = 0x63, /* A_VECM_INITX_MSB Acceleration vectormagnitude X-axis reference value MSB */
106  FXLS8471Q_A_VECM_INITX_LSB = 0x64, /* A_VECM_INITX_LSB Acceleration vectormagnitude X-axis reference value LSB */
107  FXLS8471Q_A_VECM_INITY_MSB = 0x65, /* A_VECM_INITY_MSB Acceleration vectormagnitude Y-axis reference value MSB */
108  FXLS8471Q_A_VECM_INITY_LSB = 0x66, /* A_VECM_INITY_LSB Acceleration vectormagnitude y-axis reference value LSB */
109  FXLS8471Q_A_VECM_INITZ_MSB = 0x67, /* A_VECM_INITZ_MSB Acceleration vectormagnitude Y-axis reference value MSB */
110  FXLS8471Q_A_VECM_INITZ_LSB = 0x68, /* A_VECM_INITZ_LSB Acceleration vectormagnitude Z-axis reference value LSB */
111  FXLS8471Q_A_FFMT_THS_X_MSB = 0x73, /* A_FFMT_THS_X_MSB X-axis FMT threshold MSB */
112  FXLS8471Q_A_FFMT_THS_X_LSB = 0x74, /* A_FFMT_THS_X_LSB X-axis FMT threshold LSB */
113  FXLS8471Q_A_FFMT_THS_Y_MSB = 0x75, /* A_FFMT_THS_Y_MSB Y-axis FMT threshold MSB */
114  FXLS8471Q_A_FFMT_THS_Y_LSB = 0x76, /* A_FFMT_THS_Y_LSB Y-axis FMT threshold LSB */
115  FXLS8471Q_A_FFMT_THS_Z_MSB = 0x77, /* A_FFMT_THS_Z_MSB Z-axis FMT threshold MSB */
116  FXLS8471Q_A_FFMT_THS_Z_LSB = 0x78, /* A_FFMT_THS_Z_LSB Z-axis FMT threshold LSB */
117 };
118 
119 
120 /*--------------------------------
121 ** Register: STATUS
122 ** Enum: FXLS8471Q_STATUS
123 ** --
124 ** Offset : 0x00 - Real time status.
125 ** ------------------------------*/
126 typedef union {
127  struct {
128  uint8_t xdr : 1; /* - X-axis new Data Available. */
129 
130  uint8_t ydr : 1; /* - Y-axis new Data Available. */
131 
132  uint8_t zdr : 1; /* - Z-axis new Data Available. */
133 
134  uint8_t zyxdr : 1; /* - X, Y, Z-axis new Data Ready. */
135 
136  uint8_t xow : 1; /* - X-axis Data Overwrite. */
137 
138  uint8_t yow : 1; /* - Y-axis Data Overwrite. */
139 
140  uint8_t zow : 1; /* - Z-axis Data Overwrite */
141 
142  uint8_t zyxow : 1; /* - X, Y, Z-axis Data Overwrite. */
143 
144  } b;
145  uint8_t w;
146 } FXLS8471Q_STATUS_t;
147 
148 
149 /*
150 ** STATUS - Bit field mask definitions
151 */
152 #define FXLS8471Q_STATUS_XDR_MASK ((uint8_t) 0x01)
153 #define FXLS8471Q_STATUS_XDR_SHIFT ((uint8_t) 0)
154 
155 #define FXLS8471Q_STATUS_YDR_MASK ((uint8_t) 0x02)
156 #define FXLS8471Q_STATUS_YDR_SHIFT ((uint8_t) 1)
157 
158 #define FXLS8471Q_STATUS_ZDR_MASK ((uint8_t) 0x04)
159 #define FXLS8471Q_STATUS_ZDR_SHIFT ((uint8_t) 2)
160 
161 #define FXLS8471Q_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
162 #define FXLS8471Q_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
163 
164 #define FXLS8471Q_STATUS_XOW_MASK ((uint8_t) 0x10)
165 #define FXLS8471Q_STATUS_XOW_SHIFT ((uint8_t) 4)
166 
167 #define FXLS8471Q_STATUS_YOW_MASK ((uint8_t) 0x20)
168 #define FXLS8471Q_STATUS_YOW_SHIFT ((uint8_t) 5)
169 
170 #define FXLS8471Q_STATUS_ZOW_MASK ((uint8_t) 0x40)
171 #define FXLS8471Q_STATUS_ZOW_SHIFT ((uint8_t) 6)
172 
173 #define FXLS8471Q_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
174 #define FXLS8471Q_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
175 
176 
177 /*
178 ** STATUS - Bit field value definitions
179 */
180 #define FXLS8471Q_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */
181 #define FXLS8471Q_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */
182 #define FXLS8471Q_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */
183 #define FXLS8471Q_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */
184 #define FXLS8471Q_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */
185  /* data before it was read. */
186 #define FXLS8471Q_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */
187  /* data before it was read. */
188 #define FXLS8471Q_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */
189  /* data before it was read. */
190 #define FXLS8471Q_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, */
191  /* Y, or Z data before it was read. */
192 /*------------------------------*/
193 
194 
195 
196 /*--------------------------------
197 ** Register: F_STATUS
198 ** Enum: FXLS8471Q_F_STATUS
199 ** --
200 ** Offset : 0x00 - FIFO STATUS Register.
201 ** ------------------------------*/
202 typedef union {
203  struct {
204  uint8_t f_cnt : 6; /* - FIFO sample counter. 00_0001 to 10_0000 indicates 1 to 32 samples stored */
205  /* in FIFO. */
206 
207  uint8_t f_wmrk_flag : 1; /* - FIFO watermark flag. */
208 
209  uint8_t f_ovf : 1; /* - FIFO overflow flag. */
210 
211  } b;
212  uint8_t w;
213 } FXLS8471Q_F_STATUS_t;
214 
215 
216 /*
217 ** F_STATUS - Bit field mask definitions
218 */
219 #define FXLS8471Q_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
220 #define FXLS8471Q_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
221 
222 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
223 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
224 
225 #define FXLS8471Q_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
226 #define FXLS8471Q_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
227 
228 
229 /*
230 ** F_STATUS - Bit field value definitions
231 */
232 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */
233 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count */
234  /* is greater than watermark value. */
235 #define FXLS8471Q_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */
236 #define FXLS8471Q_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */
237 /*------------------------------*/
238 
239 
240 
241 /*--------------------------------
242 ** Register: OUT_X_MSB
243 ** Enum: FXLS8471Q_OUT_X_MSB
244 ** --
245 ** Offset : 0x01 - Bits 4-11 of 12-bit X Axis current sample data.
246 ** ------------------------------*/
247 typedef uint8_t FXLS8471Q_OUT_X_MSB_t;
248 
249 
250 /*--------------------------------
251 ** Register: OUT_X_LSB
252 ** Enum: FXLS8471Q_OUT_X_LSB
253 ** --
254 ** Offset : 0x02 - Bits 0-3 of 12-bit X Axis current sample data.
255 ** ------------------------------*/
256 typedef uint8_t FXLS8471Q_OUT_X_LSB_t;
257 
258 
259 
260 /*--------------------------------
261 ** Register: OUT_Y_MSB
262 ** Enum: FXLS8471Q_OUT_Y_MSB
263 ** --
264 ** Offset : 0x03 - Bits 4-11 of 12-bit Y Axis current sample data.
265 ** ------------------------------*/
266 typedef uint8_t FXLS8471Q_OUT_Y_MSB_t;
267 
268 
269 /*--------------------------------
270 ** Register: OUT_Y_LSB
271 ** Enum: FXLS8471Q_OUT_Y_LSB
272 ** --
273 ** Offset : 0x04 - Bits 0-3 of 12-bit Y Axis current sample data.
274 ** ------------------------------*/
275 typedef uint8_t FXLS8471Q_OUT_Y_LSB_t;
276 
277 
278 
279 /*--------------------------------
280 ** Register: OUT_Z_MSB
281 ** Enum: FXLS8471Q_OUT_Z_MSB
282 ** --
283 ** Offset : 0x05 - Bits 4-11 of 12-bit Z Axis current sample data.
284 ** ------------------------------*/
285 typedef uint8_t FXLS8471Q_OUT_Z_MSB_t;
286 
287 
288 /*--------------------------------
289 ** Register: OUT_Z_LSB
290 ** Enum: FXLS8471Q_OUT_Z_LSB
291 ** --
292 ** Offset : 0x06 - Bits 0-3 of 12-bit Z Axis current sample data.
293 ** ------------------------------*/
294 typedef uint8_t FXLS8471Q_OUT_Z_LSB_t;
295 
296 
297 
298 /*--------------------------------
299 ** Register: F_SETUP
300 ** Enum: FXLS8471Q_F_SETUP
301 ** --
302 ** Offset : 0x09 - FIFO Setup Register.
303 ** ------------------------------*/
304 typedef union {
305  struct {
306  uint8_t f_wmrk : 6; /* - FIFO Event Sample Count Watermark. These bits set the number of FIFO */
307  /* samples required to trigger a watermark interrupt. */
308 
309  uint8_t f_mode : 2; /* - FIFO buffer overflow mode. */
310 
311  } b;
312  uint8_t w;
313 } FXLS8471Q_F_SETUP_t;
314 
315 
316 /*
317 ** F_SETUP - Bit field mask definitions
318 */
319 #define FXLS8471Q_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
320 #define FXLS8471Q_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
321 
322 #define FXLS8471Q_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
323 #define FXLS8471Q_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
324 
325 
326 /*
327 ** F_SETUP - Bit field value definitions
328 */
329 #define FXLS8471Q_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */
330 #define FXLS8471Q_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when */
331  /* overflowed (circular buffer). */
332 #define FXLS8471Q_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
333 #define FXLS8471Q_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the */
334  /* number of samples in the watermark. The FIFO will */
335  /* be in a circular mode until the trigger event */
336  /* occurs. */
337 /*------------------------------*/
338 
339 
340 
341 /*--------------------------------
342 ** Register: TRIG_CFG
343 ** Enum: FXLS8471Q_TRIG_CFG
344 ** --
345 ** Offset : 0x0A - Trigger Configuration Register.
346 ** ------------------------------*/
347 typedef union {
348  struct {
349  uint8_t _reserved_ : 1;
350  uint8_t trig_a_vecm : 1;
351  uint8_t trig_ff_mt : 1; /* - Freefall/Motion trigger bit. */
352 
353  uint8_t trig_pulse : 1; /* - Pulse interrupt trigger bit. */
354 
355  uint8_t trig_lndprt : 1; /* - Landscape/Portrait Orientation interrupt trigger bit. */
356 
357  uint8_t trig_trans : 1; /* - Transient interrupt trigger bit. */
358 
359  } b;
360  uint8_t w;
361 } FXLS8471Q_TRIG_CFG_t;
362 
363 
364 /*
365 ** TRIG_CFG - Bit field mask definitions
366 */
367 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_MASK ((uint8_t) 0x02)
368 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_SHIFT ((uint8_t) 1)
369 
370 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04)
371 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2)
372 
373 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
374 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
375 
376 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
377 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
378 
379 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
380 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
381 
382 
383 /*
384 ** TRIG_CFG - Bit field value definitions
385 */
386 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_EN ((uint8_t) 0x02) /* Enable the vector-magnitude FIFO trigger */
387 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_DIS ((uint8_t) 0x00) /* Disable the vector-magnitude FIFO trigger */
388 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */
389 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */
390 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */
391 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */
392 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger */
393  /* bit is cleared. */
394 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger */
395  /* bit is set. */
396 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */
397 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */
398 /*------------------------------*/
399 
400 
401 
402 /*--------------------------------
403 ** Register: SYSMOD
404 ** Enum: FXLS8471Q_SYSMOD
405 ** --
406 ** Offset : 0x0B - System Mode Register indicates the current device operating mode.
407 ** ------------------------------*/
408 typedef union {
409  struct {
410  uint8_t sysmod : 2; /* - System mode data bits. */
411 
412  uint8_t fgt : 5; /* - Number of ODR time units since FGERR was asserted. Reset when FGERR */
413  /* Cleared. */
414 
415  uint8_t fgerr : 1; /* - FIFO Gate Error. */
416 
417  } b;
418  uint8_t w;
419 } FXLS8471Q_SYSMOD_t;
420 
421 
422 /*
423 ** SYSMOD - Bit field mask definitions
424 */
425 #define FXLS8471Q_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
426 #define FXLS8471Q_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
427 
428 #define FXLS8471Q_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
429 #define FXLS8471Q_SYSMOD_FGT_SHIFT ((uint8_t) 2)
430 
431 #define FXLS8471Q_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
432 #define FXLS8471Q_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
433 
434 
435 /*
436 ** SYSMOD - Bit field value definitions
437 */
438 #define FXLS8471Q_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
439 #define FXLS8471Q_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */
440 #define FXLS8471Q_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */
441 #define FXLS8471Q_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */
442 #define FXLS8471Q_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */
443 /*------------------------------*/
444 
445 
446 
447 /*--------------------------------
448 ** Register: INT_SOURCE
449 ** Enum: FXLS8471Q_INT_SOURCE
450 ** --
451 ** Offset : 0x0C - System Interrupt Status Register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
452 ** ------------------------------*/
453 typedef union {
454  struct {
455  uint8_t src_drdy : 1; /* Data Ready Interrupt bit status. */
456 
457  uint8_t src_a_vecm : 1; /* Accelerometer vector-magnitude interrupt status bit */
458 
459  uint8_t src_ff_mt : 1; /* Freefall/Motion interrupt status bit. */
460 
461  uint8_t src_pulse : 1; /* Pulse interrupt status bit. */
462 
463  uint8_t src_lndprt : 1; /* Landscape/Portrait Orientation interrupt status bit. */
464 
465  uint8_t src_trans : 1; /* Transient interrupt status bit. */
466 
467  uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
468 
469  uint8_t src_aslp : 1; /* Auto-SLEEP/WAKE interrupt status bit. */
470 
471  } b;
472  uint8_t w;
473 } FXLS8471Q_INT_SOURCE_t;
474 
475 
476 /*
477 ** INT_SOURCE - Bit field mask definitions
478 */
479 #define FXLS8471Q_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
480 #define FXLS8471Q_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
481 
482 #define FXLS8471Q_INT_SOURCE_SRC_A_VECM_MASK ((uint8_t) 0x02)
483 #define FXLS8471Q_INT_SOURCE_SRC_A_VECM_SHIFT ((uint8_t) 1)
484 
485 #define FXLS8471Q_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04)
486 #define FXLS8471Q_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2)
487 
488 #define FXLS8471Q_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
489 #define FXLS8471Q_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
490 
491 #define FXLS8471Q_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
492 #define FXLS8471Q_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
493 
494 #define FXLS8471Q_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
495 #define FXLS8471Q_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
496 
497 #define FXLS8471Q_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
498 #define FXLS8471Q_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
499 
500 #define FXLS8471Q_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
501 #define FXLS8471Q_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
502 
503 
504 /*------------------------------*/
505 
506 
507 
508 /*--------------------------------
509 ** Register: WHO_AM_I
510 ** Enum: FXLS8471Q_WHO_AM_I
511 ** --
512 ** Offset : 0x0D - Fixed Device ID Number.
513 ** ------------------------------*/
514 typedef union {
515  struct {
516  uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */
517  /* programmed. */
518 
519  } b;
520  uint8_t w;
521 } FXLS8471Q_WHO_AM_I_t;
522 
523 
524 /*
525 ** WHO_AM_I - Bit field mask definitions
526 */
527 #define FXLS8471Q_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF)
528 #define FXLS8471Q_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0)
529 
530 
531 /*------------------------------*/
532 
533 
534 /*
535 ** WHO_AM_I - Bit field value definitions
536 */
537 
538 #define FXLS8471Q_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x6a) /* Device identifier for FXLS8471 */
539 
540 
541 /*--------------------------------
542 ** Register: XYZ_DATA_CFG
543 ** Enum: FXLS8471Q_XYZ_DATA_CFG
544 ** --
545 ** Offset : 0x0E - XYZ Data Configuration Register. sets the dynamic range and sets the high-pass filter for the output data.
546 ** ------------------------------*/
547 typedef union {
548  struct {
549  uint8_t fs : 2; /* Output buffer data format full scale. */
550 
551  uint8_t _reserved_ : 2;
552  uint8_t hpf_out : 1; /* Enable High-Pass output data. */
553 
554  } b;
555  uint8_t w;
556 } FXLS8471Q_XYZ_DATA_CFG_t;
557 
558 
559 /*
560 ** XYZ_DATA_CFG - Bit field mask definitions
561 */
562 #define FXLS8471Q_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
563 #define FXLS8471Q_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
564 
565 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
566 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
567 
568 
569 /*
570 ** XYZ_DATA_CFG - Bit field value definitions
571 */
572 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */
573 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */
574 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */
575 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */
576 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */
577 /*------------------------------*/
578 
579 
580 
581 /*--------------------------------
582 ** Register: HP_FILTER_CUTOFF
583 ** Enum: FXLS8471Q_HP_FILTER_CUTOFF
584 ** --
585 ** Offset : 0x0F - HP_FILTER_CUTOFF High-Pass Filter Register. This register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data.
586 ** ------------------------------*/
587 typedef union {
588  struct {
589  uint8_t sel : 2; /* HPF Cutoff frequency selection. */
590 
591  uint8_t _reserved_ : 2;
592  uint8_t pulse_lpf_en : 1; /* Enable Low-Pass Filter for Pulse Processing Function. */
593 
594  uint8_t pulse_hpf_byp : 1; /* Bypass High-Pass Filter for Pulse Processing Function. */
595 
596  } b;
597  uint8_t w;
598 } FXLS8471Q_HP_FILTER_CUTOFF_t;
599 
600 
601 /*
602 ** HP_FILTER_CUTOFF - Bit field mask definitions
603 */
604 #define FXLS8471Q_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
605 #define FXLS8471Q_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
606 
607 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
608 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
609 
610 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
611 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
612 
613 
614 /*
615 ** HP_FILTER_CUTOFF - Bit field value definitions
616 */
617 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */
618 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */
619 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */
620 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */
621 /*------------------------------*/
622 
623 
624 
625 /*--------------------------------
626 ** Register: PL_STATUS
627 ** Enum: FXLS8471Q_PL_STATUS
628 ** --
629 ** Offset : 0x10 - Portrait/Landscape Status Register.
630 ** ------------------------------*/
631 typedef union {
632  struct {
633  uint8_t bafro : 1; /* Back or Front orientation. */
634 
635  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
636 
637  uint8_t _reserved_ : 3;
638  uint8_t lo : 1; /* Z-Tilt Angle Lockout. */
639 
640  uint8_t newlp : 1; /* Landscape/Portrait status change flag. */
641 
642  } b;
643  uint8_t w;
644 } FXLS8471Q_PL_STATUS_t;
645 
646 
647 /*
648 ** PL_STATUS - Bit field mask definitions
649 */
650 #define FXLS8471Q_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
651 #define FXLS8471Q_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
652 
653 #define FXLS8471Q_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
654 #define FXLS8471Q_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
655 
656 #define FXLS8471Q_PL_STATUS_LO_MASK ((uint8_t) 0x40)
657 #define FXLS8471Q_PL_STATUS_LO_SHIFT ((uint8_t) 6)
658 
659 #define FXLS8471Q_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
660 #define FXLS8471Q_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
661 
662 
663 /*
664 ** PL_STATUS - Bit field value definitions
665 */
666 #define FXLS8471Q_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */
667  /* orientation. */
668 #define FXLS8471Q_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing */
669  /* orientation. */
670 #define FXLS8471Q_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */
671  /* normal orientation. */
672 #define FXLS8471Q_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in */
673  /* the inverted orientation. */
674 #define FXLS8471Q_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode */
675  /* to the right. */
676 #define FXLS8471Q_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */
677  /* the left. */
678 #define FXLS8471Q_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */
679 #define FXLS8471Q_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */
680  /* Lockout has been detected. */
681 #define FXLS8471Q_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */
682 #define FXLS8471Q_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */
683  /* changed. */
684 /*------------------------------*/
685 
686 
687 
688 /*--------------------------------
689 ** Register: PL_CFG
690 ** Enum: FXLS8471Q_PL_CFG
691 ** --
692 ** Offset : 0x11 - Portrait/Landscape Configuration Register.
693 ** ------------------------------*/
694 typedef union {
695  struct {
696  uint8_t reserved : 6; /* - Bits 5-0 are reserved, will always read 0. */
697 
698  uint8_t pl_en : 1; /* - Portrait/Landscape Detection Enable. */
699 
700  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
701 
702  } b;
703  uint8_t w;
704 } FXLS8471Q_PL_CFG_t;
705 
706 
707 /*
708 ** PL_CFG - Bit field mask definitions
709 */
710 #define FXLS8471Q_PL_CFG_RESERVED_MASK ((uint8_t) 0x3F)
711 #define FXLS8471Q_PL_CFG_RESERVED_SHIFT ((uint8_t) 0)
712 
713 #define FXLS8471Q_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
714 #define FXLS8471Q_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
715 
716 #define FXLS8471Q_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
717 #define FXLS8471Q_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
718 
719 
720 /*
721 ** PL_CFG - Bit field value definitions
722 */
723 #define FXLS8471Q_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */
724 #define FXLS8471Q_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */
725 #define FXLS8471Q_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest */
726  /* is no longer valid. */
727 #define FXLS8471Q_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
728  /* longer valid. */
729 /*------------------------------*/
730 
731 
732 
733 /*--------------------------------
734 ** Register: PL_COUNT
735 ** Enum: FXLS8471Q_PL_COUNT
736 ** --
737 ** Offset : 0x12 - Portrait/Landscape Debounce Counter.
738 ** ------------------------------*/
739 typedef union {
740  struct {
741  uint8_t dbcne; /* - Debounce Count value. */
742 
743  } b;
744  uint8_t w;
745 } FXLS8471Q_PL_COUNT_t;
746 
747 
748 /*
749 ** PL_COUNT - Bit field mask definitions
750 */
751 #define FXLS8471Q_PL_COUNT_DBCNE_MASK ((uint8_t) 0xFF)
752 #define FXLS8471Q_PL_COUNT_DBCNE_SHIFT ((uint8_t) 0)
753 
754 
755 /*------------------------------*/
756 
757 
758 
759 /*--------------------------------
760 ** Register: PL_BF_ZCOMP
761 ** Enum: FXLS8471Q_PL_BF_ZCOMP
762 ** --
763 ** Offset : 0x13 - Back/Front and Z Compensation Register.
764 ** ------------------------------*/
765 typedef union {
766  struct {
767  uint8_t zlock : 3; /* - Z-Lock Angle Fixed Threshold. */
768 
769  uint8_t _reserved_ : 3;
770  uint8_t bkfr : 2; /* - Back Front Trip Angle Fixed Threshold. */
771 
772  } b;
773  uint8_t w;
774 } FXLS8471Q_PL_BF_ZCOMP_t;
775 
776 
777 /*
778 ** PL_BF_ZCOMP - Bit field mask definitions
779 */
780 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
781 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
782 
783 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
784 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
785 
786 
787 /*
788 ** PL_BF_ZCOMP - Bit field value definitions
789 */
790 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN13_6_MAX14_5 ((uint8_t) 0x00)
791 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN17_1_MAX18_2 ((uint8_t) 0x01)
792 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN20_7_MAX22_0 ((uint8_t) 0x02)
793 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN24_4_MAX25_9 ((uint8_t) 0x03)
794 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN28_1_MAX30_0 ((uint8_t) 0x04)
795 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN32_0_MAX34_2 ((uint8_t) 0x05)
796 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN36_1_MAX38_7 ((uint8_t) 0x06)
797 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN40_4_MAX43_4 ((uint8_t) 0x07)
798 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_80_280 ((uint8_t) 0x00)
799 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_75_285 ((uint8_t) 0x40)
800 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_70_290 ((uint8_t) 0x80)
801 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_65_295 ((uint8_t) 0xc0)
802 /*------------------------------*/
803 
804 
805 
806 /*--------------------------------
807 ** Register: PL_THS_REG
808 ** Enum: FXLS8471Q_PL_THS_REG
809 ** --
810 ** Offset : 0x14 - Portrait/Landscape Threshold and Hysteresis Register.
811 ** ------------------------------*/
812 typedef union {
813  struct {
814  uint8_t hys : 3; /* - Hysteresis, This is a fixed angle added to the threshold angle for a */
815  /* smoother transition from Portrait to Landscape and Landscape to Portrait. */
816 
817  uint8_t pl_ths : 5; /* - Portrait/Landscape Fixed Threshold angle. */
818 
819  } b;
820  uint8_t w;
821 } FXLS8471Q_PL_THS_REG_t;
822 
823 
824 /*
825 ** PL_THS_REG - Bit field mask definitions
826 */
827 #define FXLS8471Q_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
828 #define FXLS8471Q_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
829 
830 #define FXLS8471Q_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
831 #define FXLS8471Q_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
832 
833 
834 /*
835 ** PL_THS_REG - Bit field value definitions
836 */
837 #define FXLS8471Q_PL_THS_REG_HYS_45_45 ((uint8_t) 0x00)
838 #define FXLS8471Q_PL_THS_REG_HYS_49_41 ((uint8_t) 0x01)
839 #define FXLS8471Q_PL_THS_REG_HYS_52_38 ((uint8_t) 0x02)
840 #define FXLS8471Q_PL_THS_REG_HYS_56_34 ((uint8_t) 0x03)
841 #define FXLS8471Q_PL_THS_REG_HYS_59_31 ((uint8_t) 0x04)
842 #define FXLS8471Q_PL_THS_REG_HYS_62_28 ((uint8_t) 0x05)
843 #define FXLS8471Q_PL_THS_REG_HYS_66_24 ((uint8_t) 0x06)
844 #define FXLS8471Q_PL_THS_REG_HYS_69_21 ((uint8_t) 0x07)
845 #define FXLS8471Q_PL_THS_REG_PL_THS_15 ((uint8_t) 0x38)
846 #define FXLS8471Q_PL_THS_REG_PL_THS_20 ((uint8_t) 0x48)
847 #define FXLS8471Q_PL_THS_REG_PL_THS_30 ((uint8_t) 0x60)
848 #define FXLS8471Q_PL_THS_REG_PL_THS_35 ((uint8_t) 0x68)
849 #define FXLS8471Q_PL_THS_REG_PL_THS_40 ((uint8_t) 0x78)
850 #define FXLS8471Q_PL_THS_REG_PL_THS_45 ((uint8_t) 0x80)
851 #define FXLS8471Q_PL_THS_REG_PL_THS_55 ((uint8_t) 0x98)
852 #define FXLS8471Q_PL_THS_REG_PL_THS_60 ((uint8_t) 0xa0)
853 #define FXLS8471Q_PL_THS_REG_PL_THS_70 ((uint8_t) 0xb8)
854 #define FXLS8471Q_PL_THS_REG_PL_THS_75 ((uint8_t) 0xc8)
855 /*------------------------------*/
856 
857 
858 
859 
860 /*--------------------------------
861 ** Register: A_FFMT_CFG
862 ** Enum: FXLS8471Q_A_FFMT_CFG
863 ** --
864 ** Offset : 0x15 - Freefall/Motion Configuration Register.
865 ** ------------------------------*/
866 typedef union {
867  struct {
868  uint8_t reserved : 3; /* - Bits 2-0 are reserved, will always read 0. */
869 
870  uint8_t xefe : 1; /* - Event flag enable on X event. */
871 
872  uint8_t yefe : 1; /* - Event flag enable on Y event. */
873 
874  uint8_t zefe : 1; /* - Event flag enable on Z event. */
875 
876  uint8_t oae : 1; /* - Motion detect / Freefall detect flag selection. */
877 
878  uint8_t ele : 1; /* - Event Latch Enable. */
879 
880  } b;
881  uint8_t w;
882 } FXLS8471Q_A_FFMT_CFG_t;
883 
884 
885 /*
886 ** A_FFMT_CFG - Bit field mask definitions
887 */
888 #define FXLS8471Q_A_FFMT_CFG_RESERVED_MASK ((uint8_t) 0x07)
889 #define FXLS8471Q_A_FFMT_CFG_RESERVED_SHIFT ((uint8_t) 0)
890 
891 #define FXLS8471Q_A_FFMT_CFG_XEFE_MASK ((uint8_t) 0x08)
892 #define FXLS8471Q_A_FFMT_CFG_XEFE_SHIFT ((uint8_t) 3)
893 
894 #define FXLS8471Q_A_FFMT_CFG_YEFE_MASK ((uint8_t) 0x10)
895 #define FXLS8471Q_A_FFMT_CFG_YEFE_SHIFT ((uint8_t) 4)
896 
897 #define FXLS8471Q_A_FFMT_CFG_ZEFE_MASK ((uint8_t) 0x20)
898 #define FXLS8471Q_A_FFMT_CFG_ZEFE_SHIFT ((uint8_t) 5)
899 
900 #define FXLS8471Q_A_FFMT_CFG_OAE_MASK ((uint8_t) 0x40)
901 #define FXLS8471Q_A_FFMT_CFG_OAE_SHIFT ((uint8_t) 6)
902 
903 #define FXLS8471Q_A_FFMT_CFG_ELE_MASK ((uint8_t) 0x80)
904 #define FXLS8471Q_A_FFMT_CFG_ELE_SHIFT ((uint8_t) 7)
905 
906 
907 /*
908 ** A_FFMT_CFG - Bit field value definitions
909 */
910 #define FXLS8471Q_A_FFMT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
911 #define FXLS8471Q_A_FFMT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */
912  /* beyond preset threshold. */
913 #define FXLS8471Q_A_FFMT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
914 #define FXLS8471Q_A_FFMT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */
915  /* beyond preset threshold. */
916 #define FXLS8471Q_A_FFMT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
917 #define FXLS8471Q_A_FFMT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */
918  /* beyond preset threshold. */
919 #define FXLS8471Q_A_FFMT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */
920 #define FXLS8471Q_A_FFMT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */
921 #define FXLS8471Q_A_FFMT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
922 #define FXLS8471Q_A_FFMT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */
923 /*------------------------------*/
924 
925 
926 
927 /*--------------------------------
928 ** Register: A_FFMT_SRC
929 ** Enum: FXLS8471Q_A_FFMT_SRC
930 ** --
931 ** Offset : 0x16 - Freefall/Motion Source Register.
932 ** ------------------------------*/
933 typedef union {
934  struct {
935  uint8_t xhp : 1; /* - Event flag enable on X event. */
936 
937  uint8_t xhe : 1; /* - Event flag enable on Y event. */
938 
939  uint8_t yhp : 1; /* - Event flag enable on Z event. */
940 
941  uint8_t yhe : 1; /* - Motion detect / Freefall detect flag selection. */
942 
943  uint8_t zhp : 1; /* - Event Latch Enable. */
944 
945  uint8_t zhe : 1; /* - Event Latch Enable. */
946 
947  uint8_t _reserved_ : 1;
948  uint8_t ea : 1; /* - Event Latch Enable. */
949 
950  } b;
951  uint8_t w;
952 } FXLS8471Q_A_FFMT_SRC_t;
953 
954 
955 /*
956 ** A_FFMT_SRC - Bit field mask definitions
957 */
958 #define FXLS8471Q_A_FFMT_SRC_XHP_MASK ((uint8_t) 0x01)
959 #define FXLS8471Q_A_FFMT_SRC_XHP_SHIFT ((uint8_t) 0)
960 
961 #define FXLS8471Q_A_FFMT_SRC_XHE_MASK ((uint8_t) 0x02)
962 #define FXLS8471Q_A_FFMT_SRC_XHE_SHIFT ((uint8_t) 1)
963 
964 #define FXLS8471Q_A_FFMT_SRC_YHP_MASK ((uint8_t) 0x04)
965 #define FXLS8471Q_A_FFMT_SRC_YHP_SHIFT ((uint8_t) 2)
966 
967 #define FXLS8471Q_A_FFMT_SRC_YHE_MASK ((uint8_t) 0x08)
968 #define FXLS8471Q_A_FFMT_SRC_YHE_SHIFT ((uint8_t) 3)
969 
970 #define FXLS8471Q_A_FFMT_SRC_ZHP_MASK ((uint8_t) 0x10)
971 #define FXLS8471Q_A_FFMT_SRC_ZHP_SHIFT ((uint8_t) 4)
972 
973 #define FXLS8471Q_A_FFMT_SRC_ZHE_MASK ((uint8_t) 0x20)
974 #define FXLS8471Q_A_FFMT_SRC_ZHE_SHIFT ((uint8_t) 5)
975 
976 #define FXLS8471Q_A_FFMT_SRC_EA_MASK ((uint8_t) 0x80)
977 #define FXLS8471Q_A_FFMT_SRC_EA_SHIFT ((uint8_t) 7)
978 
979 
980 /*
981 ** A_FFMT_SRC - Bit field value definitions
982 */
983 #define FXLS8471Q_A_FFMT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
984 #define FXLS8471Q_A_FFMT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
985 #define FXLS8471Q_A_FFMT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */
986 #define FXLS8471Q_A_FFMT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */
987 #define FXLS8471Q_A_FFMT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
988 #define FXLS8471Q_A_FFMT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
989 #define FXLS8471Q_A_FFMT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */
990 #define FXLS8471Q_A_FFMT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */
991 #define FXLS8471Q_A_FFMT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
992 #define FXLS8471Q_A_FFMT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
993 #define FXLS8471Q_A_FFMT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */
994 #define FXLS8471Q_A_FFMT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */
995 #define FXLS8471Q_A_FFMT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
996 #define FXLS8471Q_A_FFMT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */
997 /*------------------------------*/
998 
999 
1000 
1001 /*--------------------------------
1002 ** Register: A_FFMT_THS
1003 ** Enum: FXLS8471Q_A_FFMT_THS
1004 ** --
1005 ** Offset : 0x17 - Freefall and Motion Threshold Register.
1006 ** ------------------------------*/
1007 typedef union {
1008  struct {
1009  uint8_t ths : 7; /* - Freefall /Motion Threshold. */
1010 
1011  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
1012 
1013  } b;
1014  uint8_t w;
1015 } FXLS8471Q_A_FFMT_THS_t;
1016 
1017 
1018 /*
1019 ** A_FFMT_THS - Bit field mask definitions
1020 */
1021 #define FXLS8471Q_A_FFMT_THS_THS_MASK ((uint8_t) 0x7F)
1022 #define FXLS8471Q_A_FFMT_THS_THS_SHIFT ((uint8_t) 0)
1023 
1024 #define FXLS8471Q_A_FFMT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1025 #define FXLS8471Q_A_FFMT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1026 
1027 
1028 /*
1029 ** A_FFMT_THS - Bit field value definitions
1030 */
1031 #define FXLS8471Q_A_FFMT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1032 #define FXLS8471Q_A_FFMT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1033 /*------------------------------*/
1034 
1035 
1036 
1037 /*--------------------------------
1038 ** Register: A_FFMT_COUNT
1039 ** Enum: FXLS8471Q_A_FFMT_COUNT
1040 ** --
1041 ** Offset : 0x18 - Debounce Register.
1042 ** ------------------------------*/
1043 typedef union {
1044  struct {
1045  uint8_t d; /* - Count value. */
1046 
1047  } b;
1048  uint8_t w;
1049 } FXLS8471Q_A_FFMT_COUNT_t;
1050 
1051 
1052 /*
1053 ** A_FFMT_COUNT - Bit field mask definitions
1054 */
1055 #define FXLS8471Q_A_FFMT_COUNT_D_MASK ((uint8_t) 0xFF)
1056 #define FXLS8471Q_A_FFMT_COUNT_D_SHIFT ((uint8_t) 0)
1057 
1058 
1059 /*------------------------------*/
1060 
1061 
1062 
1063 /*--------------------------------
1064 ** Register: TRANSIENT_CFG
1065 ** Enum: FXLS8471Q_TRANSIENT_CFG
1066 ** --
1067 ** Offset : 0x1D - Transient_CFG Register.
1068 ** ------------------------------*/
1069 typedef union {
1070  struct {
1071  uint8_t hpf_byp : 1; /* - Bypass High-Pass filter. */
1072 
1073  uint8_t xtefe : 1; /* - Event flag enable on X transient acceleration greater than transient */
1074  /* threshold event. */
1075 
1076  uint8_t ytefe : 1; /* - Event flag enable on Y transient acceleration greater than transient */
1077  /* threshold event. */
1078 
1079  uint8_t ztefe : 1; /* - Event flag enable on Z transient acceleration greater than transient */
1080  /* threshold event. */
1081 
1082  uint8_t ele : 1; /* - Transient event flags are latched into the TRANSIENT_SRC register. */
1083 
1084  uint8_t reserved : 3; /* - Bits 7-5 are reserved, will always read 0. */
1085 
1086  } b;
1087  uint8_t w;
1088 } FXLS8471Q_TRANSIENT_CFG_t;
1089 
1090 
1091 /*
1092 ** TRANSIENT_CFG - Bit field mask definitions
1093 */
1094 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1095 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1096 
1097 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1098 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1099 
1100 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1101 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1102 
1103 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1104 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1105 
1106 #define FXLS8471Q_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10)
1107 #define FXLS8471Q_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4)
1108 
1109 #define FXLS8471Q_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0)
1110 #define FXLS8471Q_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5)
1111 
1112 
1113 /*
1114 ** TRANSIENT_CFG - Bit field value definitions
1115 */
1116 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection */
1117  /* block is through HPF. */
1118 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection */
1119  /* block is NOT through HPF. */
1120 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1121 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration */
1122  /* delta value greater than transient threshold. */
1123 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1124 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration */
1125  /* delta value greater than transient threshold. */
1126 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1127 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration */
1128  /* delta value greater than transient threshold. */
1129 #define FXLS8471Q_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1130 #define FXLS8471Q_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */
1131 /*------------------------------*/
1132 
1133 
1134 
1135 /*--------------------------------
1136 ** Register: TRANSIENT_SRC
1137 ** Enum: FXLS8471Q_TRANSIENT_SRC
1138 ** --
1139 ** Offset : 0x1E - Transient_SRC Register.
1140 ** ------------------------------*/
1141 typedef union {
1142  struct {
1143  uint8_t x_trans_pol : 1; /* - Polarity of X Transient Event that triggered interrupt. */
1144 
1145  uint8_t xtrans : 1; /* - X transient event. */
1146 
1147  uint8_t y_trans_pol : 1; /* - Polarity of Y Transient Event that triggered interrupt. */
1148 
1149  uint8_t ytrans : 1; /* - Y transient event. */
1150 
1151  uint8_t z_trans_pol : 1; /* - Polarity of Z Transient Event that triggered interrupt. */
1152 
1153  uint8_t ztrans : 1; /* - Z transient event. */
1154 
1155  uint8_t ea : 1; /* - Event Active Flag. */
1156 
1157  } b;
1158  uint8_t w;
1159 } FXLS8471Q_TRANSIENT_SRC_t;
1160 
1161 
1162 /*
1163 ** TRANSIENT_SRC - Bit field mask definitions
1164 */
1165 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01)
1166 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0)
1167 
1168 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02)
1169 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_SHIFT ((uint8_t) 1)
1170 
1171 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04)
1172 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2)
1173 
1174 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08)
1175 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_SHIFT ((uint8_t) 3)
1176 
1177 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10)
1178 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4)
1179 
1180 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20)
1181 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_SHIFT ((uint8_t) 5)
1182 
1183 #define FXLS8471Q_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40)
1184 #define FXLS8471Q_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6)
1185 
1186 
1187 /*
1188 ** TRANSIENT_SRC - Bit field value definitions
1189 */
1190 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
1191 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
1192 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1193 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the */
1194  /* value of TRANSIENT_THS event has occurred. */
1195 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
1196 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
1197 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1198 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the */
1199  /* value of TRANSIENT_THS event has occurred. */
1200 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
1201 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
1202 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1203 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the */
1204  /* value of TRANSIENT_THS event has occurred. */
1205 #define FXLS8471Q_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
1206 #define FXLS8471Q_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */
1207 /*------------------------------*/
1208 
1209 
1210 
1211 /*--------------------------------
1212 ** Register: TRANSIENT_THS
1213 ** Enum: FXLS8471Q_TRANSIENT_THS
1214 ** --
1215 ** Offset : 0x1F - TRANSIENT_THS Register.
1216 ** ------------------------------*/
1217 typedef union {
1218  struct {
1219  uint8_t ths : 7; /* - Transient Threshold. */
1220 
1221  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
1222 
1223  } b;
1224  uint8_t w;
1225 } FXLS8471Q_TRANSIENT_THS_t;
1226 
1227 
1228 /*
1229 ** TRANSIENT_THS - Bit field mask definitions
1230 */
1231 #define FXLS8471Q_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F)
1232 #define FXLS8471Q_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0)
1233 
1234 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1235 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1236 
1237 
1238 /*
1239 ** TRANSIENT_THS - Bit field value definitions
1240 */
1241 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1242 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1243 /*------------------------------*/
1244 
1245 
1246 
1247 /*--------------------------------
1248 ** Register: TRANSIENT_COUNT
1249 ** Enum: FXLS8471Q_TRANSIENT_COUNT
1250 ** --
1251 ** Offset : 0x20 - TRANSIENT_COUNT Register.
1252 ** ------------------------------*/
1253 typedef union {
1254  struct {
1255  uint8_t d; /* - Count value. */
1256 
1257  } b;
1258  uint8_t w;
1259 } FXLS8471Q_TRANSIENT_COUNT_t;
1260 
1261 
1262 /*
1263 ** TRANSIENT_COUNT - Bit field mask definitions
1264 */
1265 #define FXLS8471Q_TRANSIENT_COUNT_D_MASK ((uint8_t) 0xFF)
1266 #define FXLS8471Q_TRANSIENT_COUNT_D_SHIFT ((uint8_t) 0)
1267 
1268 
1269 /*------------------------------*/
1270 
1271 
1272 
1273 /*--------------------------------
1274 ** Register: PULSE_CFG
1275 ** Enum: FXLS8471Q_PULSE_CFG
1276 ** --
1277 ** Offset : 0x21 - Pulse Configuration Register.
1278 ** ------------------------------*/
1279 typedef union {
1280  struct {
1281  uint8_t xspefe : 1; /* - Event flag enable on single pulse event on X-axis. */
1282 
1283  uint8_t xdpefe : 1; /* - Event flag enable on double pulse event on X-axis. */
1284 
1285  uint8_t yspefe : 1; /* - Event flag enable on single pulse event on Y-axis. */
1286 
1287  uint8_t ydpefe : 1; /* - Event flag enable on double pulse event on Y-axis. */
1288 
1289  uint8_t zspefe : 1; /* - Event flag enable on single pulse event on Z-axis. */
1290 
1291  uint8_t zdpefe : 1; /* - Event flag enable on double pulse event on Z-axis. */
1292 
1293  uint8_t ele : 1; /* - Pulse event flags are latched into the PULSE_SRC register. */
1294 
1295  uint8_t dpa : 1; /* - Double Pulse Abort. */
1296 
1297  } b;
1298  uint8_t w;
1299 } FXLS8471Q_PULSE_CFG_t;
1300 
1301 
1302 /*
1303 ** PULSE_CFG - Bit field mask definitions
1304 */
1305 #define FXLS8471Q_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01)
1306 #define FXLS8471Q_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0)
1307 
1308 #define FXLS8471Q_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02)
1309 #define FXLS8471Q_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1)
1310 
1311 #define FXLS8471Q_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04)
1312 #define FXLS8471Q_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2)
1313 
1314 #define FXLS8471Q_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08)
1315 #define FXLS8471Q_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3)
1316 
1317 #define FXLS8471Q_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10)
1318 #define FXLS8471Q_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4)
1319 
1320 #define FXLS8471Q_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20)
1321 #define FXLS8471Q_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5)
1322 
1323 #define FXLS8471Q_PULSE_CFG_ELE_MASK ((uint8_t) 0x40)
1324 #define FXLS8471Q_PULSE_CFG_ELE_SHIFT ((uint8_t) 6)
1325 
1326 #define FXLS8471Q_PULSE_CFG_DPA_MASK ((uint8_t) 0x80)
1327 #define FXLS8471Q_PULSE_CFG_DPA_SHIFT ((uint8_t) 7)
1328 
1329 
1330 /*
1331 ** PULSE_CFG - Bit field value definitions
1332 */
1333 #define FXLS8471Q_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1334 #define FXLS8471Q_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */
1335 #define FXLS8471Q_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1336 #define FXLS8471Q_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */
1337 #define FXLS8471Q_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1338 #define FXLS8471Q_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */
1339 #define FXLS8471Q_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1340 #define FXLS8471Q_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */
1341 #define FXLS8471Q_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1342 #define FXLS8471Q_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */
1343 #define FXLS8471Q_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1344 #define FXLS8471Q_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */
1345 #define FXLS8471Q_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1346 #define FXLS8471Q_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */
1347 #define FXLS8471Q_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the */
1348  /* start of a pulse is detected. */
1349 #define FXLS8471Q_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */
1350  /* pulse is detected. */
1351 /*------------------------------*/
1352 
1353 
1354 
1355 /*--------------------------------
1356 ** Register: PULSE_SRC
1357 ** Enum: FXLS8471Q_PULSE_SRC
1358 ** --
1359 ** Offset : 0x22 - Pulse Source Register.
1360 ** ------------------------------*/
1361 typedef union {
1362  struct {
1363  uint8_t polx : 1; /* - Pulse polarity of X-axis Event. */
1364 
1365  uint8_t poly : 1; /* - Pulse polarity of Y-axis Event. */
1366 
1367  uint8_t polz : 1; /* - Pulse polarity of Z-axis Event. */
1368 
1369  uint8_t dpe : 1; /* - Double pulse on first event. */
1370 
1371  uint8_t axx : 1; /* - X-axis event. */
1372 
1373  uint8_t axy : 1; /* - Y-axis event. */
1374 
1375  uint8_t axz : 1; /* - Z-axis event. */
1376 
1377  uint8_t ea : 1; /* - Event Active Flag. */
1378 
1379  } b;
1380  uint8_t w;
1381 } FXLS8471Q_PULSE_SRC_t;
1382 
1383 
1384 /*
1385 ** PULSE_SRC - Bit field mask definitions
1386 */
1387 #define FXLS8471Q_PULSE_SRC_POLX_MASK ((uint8_t) 0x01)
1388 #define FXLS8471Q_PULSE_SRC_POLX_SHIFT ((uint8_t) 0)
1389 
1390 #define FXLS8471Q_PULSE_SRC_POLY_MASK ((uint8_t) 0x02)
1391 #define FXLS8471Q_PULSE_SRC_POLY_SHIFT ((uint8_t) 1)
1392 
1393 #define FXLS8471Q_PULSE_SRC_POLZ_MASK ((uint8_t) 0x04)
1394 #define FXLS8471Q_PULSE_SRC_POLZ_SHIFT ((uint8_t) 2)
1395 
1396 #define FXLS8471Q_PULSE_SRC_DPE_MASK ((uint8_t) 0x08)
1397 #define FXLS8471Q_PULSE_SRC_DPE_SHIFT ((uint8_t) 3)
1398 
1399 #define FXLS8471Q_PULSE_SRC_AXX_MASK ((uint8_t) 0x10)
1400 #define FXLS8471Q_PULSE_SRC_AXX_SHIFT ((uint8_t) 4)
1401 
1402 #define FXLS8471Q_PULSE_SRC_AXY_MASK ((uint8_t) 0x20)
1403 #define FXLS8471Q_PULSE_SRC_AXY_SHIFT ((uint8_t) 5)
1404 
1405 #define FXLS8471Q_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40)
1406 #define FXLS8471Q_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6)
1407 
1408 #define FXLS8471Q_PULSE_SRC_EA_MASK ((uint8_t) 0x80)
1409 #define FXLS8471Q_PULSE_SRC_EA_SHIFT ((uint8_t) 7)
1410 
1411 
1412 /*
1413 ** PULSE_SRC - Bit field value definitions
1414 */
1415 #define FXLS8471Q_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1416  /* Positive. */
1417 #define FXLS8471Q_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was */
1418  /* negative. */
1419 #define FXLS8471Q_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1420  /* Positive. */
1421 #define FXLS8471Q_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was */
1422  /* negative. */
1423 #define FXLS8471Q_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1424  /* Positive. */
1425 #define FXLS8471Q_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was */
1426  /* negative. */
1427 #define FXLS8471Q_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */
1428 #define FXLS8471Q_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */
1429 #define FXLS8471Q_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1430 #define FXLS8471Q_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */
1431 #define FXLS8471Q_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1432 #define FXLS8471Q_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */
1433 #define FXLS8471Q_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1434 #define FXLS8471Q_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */
1435 #define FXLS8471Q_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */
1436 #define FXLS8471Q_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */
1437 /*------------------------------*/
1438 
1439 
1440 
1441 /*--------------------------------
1442 ** Register: PULSE_THSX
1443 ** Enum: FXLS8471Q_PULSE_THSX
1444 ** --
1445 ** Offset : 0x23 - Pulse Threshold for X.
1446 ** ------------------------------*/
1447 typedef union {
1448  struct {
1449  uint8_t thsx : 7; /* - Pulse Threshold on X-axis. */
1450 
1451  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1452 
1453  } b;
1454  uint8_t w;
1455 } FXLS8471Q_PULSE_THSX_t;
1456 
1457 
1458 /*
1459 ** PULSE_THSX - Bit field mask definitions
1460 */
1461 #define FXLS8471Q_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F)
1462 #define FXLS8471Q_PULSE_THSX_THSX_SHIFT ((uint8_t) 0)
1463 
1464 #define FXLS8471Q_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80)
1465 #define FXLS8471Q_PULSE_THSX_RESERVED_SHIFT ((uint8_t) 7)
1466 
1467 
1468 /*------------------------------*/
1469 
1470 
1471 
1472 /*--------------------------------
1473 ** Register: PULSE_THSY
1474 ** Enum: FXLS8471Q_PULSE_THSY
1475 ** --
1476 ** Offset : 0x24 - Pulse Threshold for Y.
1477 ** ------------------------------*/
1478 typedef union {
1479  struct {
1480  uint8_t thsy : 7; /* - Pulse Threshold on Y-axis. */
1481 
1482  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1483 
1484  } b;
1485  uint8_t w;
1486 } FXLS8471Q_PULSE_THSY_t;
1487 
1488 
1489 /*
1490 ** PULSE_THSY - Bit field mask definitions
1491 */
1492 #define FXLS8471Q_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F)
1493 #define FXLS8471Q_PULSE_THSY_THSY_SHIFT ((uint8_t) 0)
1494 
1495 #define FXLS8471Q_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80)
1496 #define FXLS8471Q_PULSE_THSY_RESERVED_SHIFT ((uint8_t) 7)
1497 
1498 
1499 /*------------------------------*/
1500 
1501 
1502 
1503 /*--------------------------------
1504 ** Register: PULSE_THSZ
1505 ** Enum: FXLS8471Q_PULSE_THSZ
1506 ** --
1507 ** Offset : 0x25 - Pulse Threshold for Z.
1508 ** ------------------------------*/
1509 typedef union {
1510  struct {
1511  uint8_t thsz : 7; /* - Pulse Threshold on Z-axis. */
1512 
1513  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1514 
1515  } b;
1516  uint8_t w;
1517 } FXLS8471Q_PULSE_THSZ_t;
1518 
1519 
1520 /*
1521 ** PULSE_THSZ - Bit field mask definitions
1522 */
1523 #define FXLS8471Q_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F)
1524 #define FXLS8471Q_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0)
1525 
1526 #define FXLS8471Q_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80)
1527 #define FXLS8471Q_PULSE_THSZ_RESERVED_SHIFT ((uint8_t) 7)
1528 
1529 
1530 /*------------------------------*/
1531 
1532 
1533 
1534 /*--------------------------------
1535 ** Register: PULSE_TMLT
1536 ** Enum: FXLS8471Q_PULSE_TMLT
1537 ** --
1538 ** Offset : 0x26 - Pulse Time Window 1 Register.
1539 ** ------------------------------*/
1540 typedef union {
1541  struct {
1542  uint8_t tmlt; /* - Pulse Time Limit. */
1543 
1544  } b;
1545  uint8_t w;
1546 } FXLS8471Q_PULSE_TMLT_t;
1547 
1548 
1549 /*
1550 ** PULSE_TMLT - Bit field mask definitions
1551 */
1552 #define FXLS8471Q_PULSE_TMLT_TMLT_MASK ((uint8_t) 0xFF)
1553 #define FXLS8471Q_PULSE_TMLT_TMLT_SHIFT ((uint8_t) 0)
1554 
1555 
1556 /*------------------------------*/
1557 
1558 
1559 
1560 /*--------------------------------
1561 ** Register: PULSE_LTCY
1562 ** Enum: FXLS8471Q_PULSE_LTCY
1563 ** --
1564 ** Offset : 0x27 - Pulse Latency Timer Register.
1565 ** ------------------------------*/
1566 typedef union {
1567  struct {
1568  uint8_t ltcy; /* - Latency Time Limit. */
1569 
1570  } b;
1571  uint8_t w;
1572 } FXLS8471Q_PULSE_LTCY_t;
1573 
1574 
1575 /*
1576 ** PULSE_LTCY - Bit field mask definitions
1577 */
1578 #define FXLS8471Q_PULSE_LTCY_LTCY_MASK ((uint8_t) 0xFF)
1579 #define FXLS8471Q_PULSE_LTCY_LTCY_SHIFT ((uint8_t) 0)
1580 
1581 
1582 /*------------------------------*/
1583 
1584 
1585 
1586 /*--------------------------------
1587 ** Register: PULSE_WIND
1588 ** Enum: FXLS8471Q_PULSE_WIND
1589 ** --
1590 ** Offset : 0x28 - Second Pulse Time Window Register.
1591 ** ------------------------------*/
1592 typedef union {
1593  struct {
1594  uint8_t wind; /* - Second Pulse Time Window. */
1595 
1596  } b;
1597  uint8_t w;
1598 } FXLS8471Q_PULSE_WIND_t;
1599 
1600 
1601 /*
1602 ** PULSE_WIND - Bit field mask definitions
1603 */
1604 #define FXLS8471Q_PULSE_WIND_WIND_MASK ((uint8_t) 0xFF)
1605 #define FXLS8471Q_PULSE_WIND_WIND_SHIFT ((uint8_t) 0)
1606 
1607 
1608 /*------------------------------*/
1609 
1610 
1611 
1612 /*--------------------------------
1613 ** Register: ASLP_COUNT
1614 ** Enum: FXLS8471Q_ASLP_COUNT
1615 ** --
1616 ** Offset : 0x29 - Auto-WAKE/SLEEP count Register.
1617 ** ------------------------------*/
1618 typedef union {
1619  struct {
1620  uint8_t d; /* - Duration value. */
1621 
1622  } b;
1623  uint8_t w;
1624 } FXLS8471Q_ASLP_COUNT_t;
1625 
1626 
1627 /*
1628 ** ASLP_COUNT - Bit field mask definitions
1629 */
1630 #define FXLS8471Q_ASLP_COUNT_D_MASK ((uint8_t) 0xFF)
1631 #define FXLS8471Q_ASLP_COUNT_D_SHIFT ((uint8_t) 0)
1632 
1633 
1634 /*------------------------------*/
1635 
1636 
1637 
1638 /*--------------------------------
1639 ** Register: CTRL_REG1
1640 ** Enum: FXLS8471Q_CTRL_REG1
1641 ** --
1642 ** Offset : 0x2A - System Control 1 Register.
1643 ** ------------------------------*/
1644 typedef union {
1645  struct {
1646  uint8_t mode : 1; /* - Full Scale selection. */
1647 
1648  uint8_t f_read : 1; /* - Fast Read mode. */
1649 
1650  uint8_t lnoise : 1; /* - Reduced noise reduced Maximum range mode. */
1651 
1652  uint8_t dr : 3; /* - Data rate selection. */
1653 
1654  uint8_t aslp_rate : 2; /* - Configures the Auto-WAKE sample frequency when the device is in SLEEP */
1655  /* Mode. */
1656 
1657  } b;
1658  uint8_t w;
1659 } FXLS8471Q_CTRL_REG1_t;
1660 
1661 
1662 /*
1663 ** CTRL_REG1 - Bit field mask definitions
1664 */
1665 #define FXLS8471Q_CTRL_REG1_MODE_MASK ((uint8_t) 0x01)
1666 #define FXLS8471Q_CTRL_REG1_MODE_SHIFT ((uint8_t) 0)
1667 
1668 #define FXLS8471Q_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1669 #define FXLS8471Q_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1670 
1671 #define FXLS8471Q_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1672 #define FXLS8471Q_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1673 
1674 #define FXLS8471Q_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1675 #define FXLS8471Q_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1676 
1677 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1678 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1679 
1680 
1681 /*
1682 ** CTRL_REG1 - Bit field value definitions
1683 */
1684 #define FXLS8471Q_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */
1685 #define FXLS8471Q_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */
1686 #define FXLS8471Q_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1687 #define FXLS8471Q_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */
1688 #define FXLS8471Q_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1689 #define FXLS8471Q_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */
1690 #define FXLS8471Q_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */
1691 #define FXLS8471Q_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */
1692 #define FXLS8471Q_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */
1693 #define FXLS8471Q_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */
1694 #define FXLS8471Q_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */
1695 #define FXLS8471Q_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */
1696 #define FXLS8471Q_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */
1697 #define FXLS8471Q_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */
1698 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */
1699 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */
1700 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */
1701 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */
1702 /*------------------------------*/
1703 
1704 
1705 
1706 /*--------------------------------
1707 ** Register: CTRL_REG2
1708 ** Enum: FXLS8471Q_CTRL_REG2
1709 ** --
1710 ** Offset : 0x2B - System Control 2 Register.
1711 ** ------------------------------*/
1712 typedef union {
1713  struct {
1714  uint8_t mods : 2; /* - ACTIVE mode power scheme selection. */
1715 
1716  uint8_t slpe : 1; /* - Auto-SLEEP enable. */
1717 
1718  uint8_t smods : 2; /* - SLEEP mode power scheme selection. */
1719 
1720  uint8_t _reserved_ : 1;
1721  uint8_t rst : 1; /* - Software Reset. */
1722 
1723  uint8_t st : 1; /* - Self-Test Enable. */
1724 
1725  } b;
1726  uint8_t w;
1727 } FXLS8471Q_CTRL_REG2_t;
1728 
1729 
1730 /*
1731 ** CTRL_REG2 - Bit field mask definitions
1732 */
1733 #define FXLS8471Q_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1734 #define FXLS8471Q_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1735 
1736 #define FXLS8471Q_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1737 #define FXLS8471Q_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1738 
1739 #define FXLS8471Q_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1740 #define FXLS8471Q_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1741 
1742 #define FXLS8471Q_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1743 #define FXLS8471Q_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1744 
1745 #define FXLS8471Q_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1746 #define FXLS8471Q_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1747 
1748 
1749 /*
1750 ** CTRL_REG2 - Bit field value definitions
1751 */
1752 #define FXLS8471Q_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1753 #define FXLS8471Q_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */
1754 #define FXLS8471Q_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */
1755 #define FXLS8471Q_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */
1756 #define FXLS8471Q_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */
1757 #define FXLS8471Q_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */
1758 #define FXLS8471Q_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1759 #define FXLS8471Q_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */
1760 #define FXLS8471Q_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */
1761 #define FXLS8471Q_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */
1762 #define FXLS8471Q_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */
1763 #define FXLS8471Q_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */
1764 #define FXLS8471Q_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */
1765 #define FXLS8471Q_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */
1766 /*------------------------------*/
1767 
1768 
1769 
1770 /*--------------------------------
1771 ** Register: CTRL_REG3
1772 ** Enum: FXLS8471Q_CTRL_REG3
1773 ** --
1774 ** Offset : 0x2C - Interrupt Control Register.
1775 ** ------------------------------*/
1776 typedef union {
1777  struct {
1778  uint8_t pp_od : 1; /* - Push-Pull/Open Drain selection on interrupt pad. */
1779 
1780  uint8_t ipol : 1; /* - Interrupt polarity ACTIVE high, or ACTIVE low. */
1781 
1782  uint8_t wake_en_a_vecm : 1; /* vector magnitude wake mode en/dis */
1783 
1784  uint8_t wake_ff_mt : 1; /* - Freefall/Motion wake up interrupt. */
1785 
1786  uint8_t wake_pulse : 1; /* - Pulse wake up interrupt. */
1787 
1788  uint8_t wake_lndprt : 1; /* - Orientation wake up interrupt. */
1789 
1790  uint8_t wake_trans : 1; /* - Transient wake up interrupt. */
1791 
1792  uint8_t fifo_gate : 1; /* - FIFO Gate wake up interrupt. */
1793 
1794  } b;
1795  uint8_t w;
1796 } FXLS8471Q_CTRL_REG3_t;
1797 
1798 
1799 /*
1800 ** CTRL_REG3 - Bit field mask definitions
1801 */
1802 #define FXLS8471Q_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1803 #define FXLS8471Q_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1804 
1805 #define FXLS8471Q_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1806 #define FXLS8471Q_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1807 
1808 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_MASK ((uint8_t) 0x04)
1809 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_SHIFT ((uint8_t) 2)
1810 
1811 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08)
1812 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3)
1813 
1814 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1815 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1816 
1817 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1818 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1819 
1820 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1821 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1822 
1823 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1824 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1825 
1826 
1827 /*
1828 ** CTRL_REG3 - Bit field value definitions
1829 */
1830 #define FXLS8471Q_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */
1831 #define FXLS8471Q_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */
1832 #define FXLS8471Q_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */
1833 #define FXLS8471Q_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */
1834 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_EN ((uint8_t) 0x04) /* Acceleration vector-magnitude function is enabled */
1835  /* in Sleep mode and can generate an interrupt to */
1836  /* wake the system */
1837 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude function is */
1838  /* disabled in Sleep mode */
1839 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP */
1840  /* mode. */
1841 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */
1842 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */
1843 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */
1844 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */
1845 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */
1846 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */
1847 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */
1848 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */
1849  /* system mode transitioning from WAKE to SLEEP mode */
1850  /* or from SLEEP to WAKE mode. */
1851 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when */
1852  /* transitioning from WAKE to SLEEP mode or from */
1853  /* SLEEP to WAKE mode until the FIFO is flushed. */
1854 /*------------------------------*/
1855 
1856 
1857 
1858 /*--------------------------------
1859 ** Register: CTRL_REG4
1860 ** Enum: FXLS8471Q_CTRL_REG4
1861 ** --
1862 ** Offset : 0x2D - Interrupt Enable register (Read/Write).
1863 ** ------------------------------*/
1864 typedef union {
1865  struct {
1866  uint8_t int_en_drdy : 1; /* - Interrupt Enable. */
1867 
1868  uint8_t int_en_a_vecm : 1; /* Vector magnitude interrupt */
1869 
1870  uint8_t int_en_ff_mt : 1; /* - Interrupt Enable. */
1871 
1872  uint8_t int_en_pulse : 1; /* - Interrupt Enable. */
1873 
1874  uint8_t int_en_lndprt : 1; /* - Interrupt Enable. */
1875 
1876  uint8_t int_en_trans : 1; /* - Interrupt Enable. */
1877 
1878  uint8_t int_en_fifo : 1; /* - Interrupt Enable. */
1879 
1880  uint8_t int_en_aslp : 1; /* - Interrupt Enable. */
1881 
1882  } b;
1883  uint8_t w;
1884 } FXLS8471Q_CTRL_REG4_t;
1885 
1886 
1887 /*
1888 ** CTRL_REG4 - Bit field mask definitions
1889 */
1890 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1891 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1892 
1893 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_MASK ((uint8_t) 0x02)
1894 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_SHIFT ((uint8_t) 1)
1895 
1896 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04)
1897 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2)
1898 
1899 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1900 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1901 
1902 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1903 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1904 
1905 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1906 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1907 
1908 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1909 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1910 
1911 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1912 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1913 
1914 
1915 /*
1916 ** CTRL_REG4 - Bit field value definitions
1917 */
1918 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1919 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */
1920 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_DISABLED ((uint8_t) 0x00) /* Vector magnitude interrupt disabled. */
1921 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_ENABLED ((uint8_t) 0x02) /* Vector magnitude interrupt enabled. */
1922 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */
1923 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */
1924 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */
1925 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */
1926 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */
1927  /* disabled. */
1928 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt */
1929  /* enabled. */
1930 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */
1931 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */
1932 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1933 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */
1934 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */
1935 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */
1936 /*------------------------------*/
1937 
1938 
1939 
1940 /*--------------------------------
1941 ** Register: CTRL_REG5
1942 ** Enum: FXLS8471Q_CTRL_REG5
1943 ** --
1944 ** Offset : 0x2E - Interrupt Configuration Register.
1945 ** ------------------------------*/
1946 typedef union {
1947  struct {
1948  uint8_t int_cfg_drdy : 1; /* - INT1/INT2 Configuration. */
1949 
1950  uint8_t int_cfg_a_vecm : 1; /* Acceleration vector-magnitude interrupt routing */
1951 
1952  uint8_t int_cfg_ff_mt : 1; /* - INT1/INT2 Configuration. */
1953 
1954  uint8_t int_cfg_pulse : 1; /* - INT1/INT2 Configuration. */
1955 
1956  uint8_t int_cfg_lndprt : 1; /* - INT1/INT2 Configuration. */
1957 
1958  uint8_t int_cfg_trans : 1; /* - INT1/INT2 Configuration. */
1959 
1960  uint8_t int_cfg_fifo : 1; /* - INT1/INT2 Configuration. */
1961 
1962  uint8_t int_cfg_aslp : 1; /* - INT1/INT2 Configuration. */
1963 
1964  } b;
1965  uint8_t w;
1966 } FXLS8471Q_CTRL_REG5_t;
1967 
1968 
1969 /*
1970 ** CTRL_REG5 - Bit field mask definitions
1971 */
1972 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1973 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1974 
1975 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_MASK ((uint8_t) 0x02)
1976 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_SHIFT ((uint8_t) 1)
1977 
1978 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04)
1979 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2)
1980 
1981 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1982 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1983 
1984 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1985 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1986 
1987 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1988 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1989 
1990 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1991 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1992 
1993 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1994 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1995 
1996 
1997 /*
1998 ** CTRL_REG5 - Bit field value definitions
1999 */
2000 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2001 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */
2002 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2003 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 pin. */
2004 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2005 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */
2006 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2007 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */
2008 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2009 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */
2010 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2011 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */
2012 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2013 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */
2014 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
2015 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */
2016 /*------------------------------*/
2017 
2018 
2019 
2020 /*--------------------------------
2021 ** Register: OFF_X
2022 ** Enum: FXLS8471Q_OFF_X
2023 ** --
2024 ** Offset : 0x2F - Offset Correction X Register.
2025 ** ------------------------------*/
2026 typedef union {
2027  struct {
2028  uint8_t d; /* - X-axis offset value. */
2029 
2030  } b;
2031  uint8_t w;
2032 } FXLS8471Q_OFF_X_t;
2033 
2034 
2035 /*
2036 ** OFF_X - Bit field mask definitions
2037 */
2038 #define FXLS8471Q_OFF_X_D_MASK ((uint8_t) 0xFF)
2039 #define FXLS8471Q_OFF_X_D_SHIFT ((uint8_t) 0)
2040 
2041 
2042 /*------------------------------*/
2043 
2044 
2045 
2046 /*--------------------------------
2047 ** Register: OFF_Y
2048 ** Enum: FXLS8471Q_OFF_Y
2049 ** --
2050 ** Offset : 0x30 - Offset Correction Y Register.
2051 ** ------------------------------*/
2052 typedef union {
2053  struct {
2054  uint8_t d; /* - Y-axis offset value. */
2055 
2056  } b;
2057  uint8_t w;
2058 } FXLS8471Q_OFF_Y_t;
2059 
2060 
2061 /*
2062 ** OFF_Y - Bit field mask definitions
2063 */
2064 #define FXLS8471Q_OFF_Y_D_MASK ((uint8_t) 0xFF)
2065 #define FXLS8471Q_OFF_Y_D_SHIFT ((uint8_t) 0)
2066 
2067 
2068 /*------------------------------*/
2069 
2070 
2071 
2072 /*--------------------------------
2073 ** Register: OFF_Z
2074 ** Enum: FXLS8471Q_OFF_Z
2075 ** --
2076 ** Offset : 0x31 - Offset Correction Z Register.
2077 ** ------------------------------*/
2078 typedef union {
2079  struct {
2080  uint8_t d; /* - Z-axis offset value. */
2081 
2082  } b;
2083  uint8_t w;
2084 } FXLS8471Q_OFF_Z_t;
2085 
2086 
2087 /*
2088 ** OFF_Z - Bit field mask definitions
2089 */
2090 #define FXLS8471Q_OFF_Z_D_MASK ((uint8_t) 0xFF)
2091 #define FXLS8471Q_OFF_Z_D_SHIFT ((uint8_t) 0)
2092 
2093 
2094 /*------------------------------*/
2095 
2096 
2097 
2098 /*--------------------------------
2099 ** Register: A_VECM_CFG
2100 ** Enum: FXLS8471Q_A_VECM_CFG
2101 ** --
2102 ** Offset : 0x5F - Acceleration vectormagnitude configuration register
2103 ** ------------------------------*/
2104 typedef union {
2105  struct {
2106  uint8_t _reserved_ : 3;
2107  uint8_t a_vecm_ele : 1; /* - Control bit a_vecm_ele defines the event latch enable mode. */
2108 
2109  uint8_t a_vecm_initm : 1; /* - Control bit a_vecm_initm defines how the initial reference values */
2110  /* (x_ref, y_ref, and z_ref) are chosen */
2111 
2112  uint8_t a_vecm_updm : 1; /* - How the reference values are updated once the vector-magnitude function */
2113  /* has been triggered. */
2114 
2115  uint8_t a_vecm_en : 1; /* - The accelerometer vector-magnitude function enable/disable */
2116 
2117  } b;
2118  uint8_t w;
2119 } FXLS8471Q_A_VECM_CFG_t;
2120 
2121 
2122 /*
2123 ** A_VECM_CFG - Bit field mask definitions
2124 */
2125 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_MASK ((uint8_t) 0x08)
2126 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_SHIFT ((uint8_t) 3)
2127 
2128 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_MASK ((uint8_t) 0x10)
2129 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_SHIFT ((uint8_t) 4)
2130 
2131 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_MASK ((uint8_t) 0x20)
2132 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_SHIFT ((uint8_t) 5)
2133 
2134 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x40)
2135 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 6)
2136 
2137 
2138 /*
2139 ** A_VECM_CFG - Bit field value definitions
2140 */
2141 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_EN ((uint8_t) 0x08) /* The interrupt flag is latched in and held until */
2142  /* the host application reads the INT_SOURCE */
2143  /* register(0x0C) */
2144 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_DIS ((uint8_t) 0x00) /* Event latching is disabled */
2145 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_EN ((uint8_t) 0x10) /* The function uses the data from */
2146  /* A_VECM_INIT_X/Y/Z registers as the initial */
2147  /* reference values */
2148 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_DIS ((uint8_t) 0x00) /* The function uses the current x/y/z */
2149  /* accelerometer output data at the time when the */
2150  /* vector magnitude function is enabled */
2151 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_EN ((uint8_t) 0x20) /* The function does not update the reference */
2152  /* values when the interrupt is triggered. */
2153 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_DIS ((uint8_t) 0x00) /* The function updates the reference value with */
2154  /* the current x, y, and z accelerometer output */
2155  /* data values. */
2156 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_EN ((uint8_t) 0x40) /* The accelerometer vector-magnitude function is */
2157  /* enabled. */
2158 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_DIS ((uint8_t) 0x00) /* The accelerometer vector-magnitude function is */
2159  /* disabled. */
2160 /*------------------------------*/
2161 
2162 
2163 
2164 /*--------------------------------
2165 ** Register: A_VECM_THS_MSB
2166 ** Enum: FXLS8471Q_A_VECM_THS_MSB
2167 ** --
2168 ** Offset : 0x60 - Acceleration vectormagnitude threshold MSB
2169 ** ------------------------------*/
2170 typedef union {
2171  struct {
2172  uint8_t a_vecm_ths : 5; /* Five MSBs of the 13-bit unsigned A_VECM_THS value */
2173 
2174  uint8_t _reserved_ : 2;
2175  uint8_t a_vecm_dbcntm : 1; /* How the debounce timer is reset when the condition for triggering the */
2176  /* interrupt is no longer true */
2177 
2178  } b;
2179  uint8_t w;
2180 } FXLS8471Q_A_VECM_THS_MSB_t;
2181 
2182 
2183 /*
2184 ** A_VECM_THS_MSB - Bit field mask definitions
2185 */
2186 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_THS_MASK ((uint8_t) 0x1F)
2187 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_THS_SHIFT ((uint8_t) 0)
2188 
2189 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_DBCNTM_MASK ((uint8_t) 0x80)
2190 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_DBCNTM_SHIFT ((uint8_t) 7)
2191 
2192 
2193 /*------------------------------*/
2194 
2195 
2196 
2197 /*--------------------------------
2198 ** Register: A_VECM_THS_LSB
2199 ** Enum: FXLS8471Q_A_VECM_THS_LSB
2200 ** --
2201 ** Offset : 0x61 - Acceleration vectormagnitude threshold LSB
2202 ** ------------------------------*/
2203 typedef uint8_t FXLS8471Q_A_VECM_THS_LSB_t;
2204 
2205 
2206 
2207 /*--------------------------------
2208 ** Register: A_VECM_CNT
2209 ** Enum: FXLS8471Q_A_VECM_CNT
2210 ** --
2211 ** Offset : 0x62 - Acceleration vectormagnitude debounce count
2212 ** ------------------------------*/
2213 typedef union {
2214  struct {
2215  uint8_t a_vecm_cnt; /* Vector-magnitude function debounce count value. */
2216 
2217  } b;
2218  uint8_t w;
2219 } FXLS8471Q_A_VECM_CNT_t;
2220 
2221 
2222 /*
2223 ** A_VECM_CNT - Bit field mask definitions
2224 */
2225 #define FXLS8471Q_A_VECM_CNT_A_VECM_CNT_MASK ((uint8_t) 0xFF)
2226 #define FXLS8471Q_A_VECM_CNT_A_VECM_CNT_SHIFT ((uint8_t) 0)
2227 
2228 
2229 /*------------------------------*/
2230 
2231 
2232 
2233 /*--------------------------------
2234 ** Register: A_VECM_INITX_MSB
2235 ** Enum: FXLS8471Q_A_VECM_INITX_MSB
2236 ** --
2237 ** Offset 0x63 - Acceleration vectormagnitude X-axis reference value MSB
2238 ** ------------------------------*/
2239 typedef union {
2240  struct {
2241  uint8_t a_vecm_initx : 6; /* Most significant 6 bits of the signed 14-bit initial X-axis value */
2242 
2243  } b;
2244  uint8_t w;
2245 } FXLS8471Q_A_VECM_INITX_MSB_t;
2246 
2247 
2248 /*
2249 ** A_VECM_INITX_MSB - Bit field mask definitions
2250 */
2251 #define FXLS8471Q_A_VECM_INITX_MSB_A_VECM_INITX_MASK ((uint8_t) 0x3F)
2252 #define FXLS8471Q_A_VECM_INITX_MSB_A_VECM_INITX_SHIFT ((uint8_t) 0)
2253 
2254 
2255 /*------------------------------*/
2256 
2257 
2258 
2259 /*--------------------------------
2260 ** Register: A_VECM_INITX_LSB
2261 ** Enum: FXLS8471Q_A_VECM_INITX_LSB
2262 ** --
2263 ** Offset 0x64 - Acceleration vectormagnitude X-axis reference value LSB
2264 ** ------------------------------*/
2265 typedef uint8_t FXLS8471Q_A_VECM_INITX_LSB_t;
2266 
2267 
2268 
2269 /*--------------------------------
2270 ** Register: A_VECM_INITY_MSB
2271 ** Enum: FXLS8471Q_A_VECM_INITY_MSB
2272 ** --
2273 ** Offset 0x65 - Acceleration vectormagnitude Y-axis reference value MSB
2274 ** ------------------------------*/
2275 typedef union {
2276  struct {
2277  uint8_t a_vecm_inity : 6; /* Most significant 6 bits of the signed 14-bit initial Y-axis value */
2278 
2279  } b;
2280  uint8_t w;
2281 } FXLS8471Q_A_VECM_INITY_MSB_t;
2282 
2283 
2284 /*
2285 ** A_VECM_INITY_MSB - Bit field mask definitions
2286 */
2287 #define FXLS8471Q_A_VECM_INITY_MSB_A_VECM_INITY_MASK ((uint8_t) 0x3F)
2288 #define FXLS8471Q_A_VECM_INITY_MSB_A_VECM_INITY_SHIFT ((uint8_t) 0)
2289 
2290 
2291 /*------------------------------*/
2292 
2293 
2294 
2295 /*--------------------------------
2296 ** Register: A_VECM_INITY_LSB
2297 ** Enum: FXLS8471Q_A_VECM_INITY_LSB
2298 ** --
2299 ** Offset 0x66 - Acceleration vectormagnitude y-axis reference value LSB
2300 ** ------------------------------*/
2301 typedef uint8_t FXLS8471Q_A_VECM_INITY_LSB_t;
2302 
2303 
2304 
2305 /*--------------------------------
2306 ** Register: A_VECM_INITZ_MSB
2307 ** Enum: FXLS8471Q_A_VECM_INITZ_MSB
2308 ** --
2309 ** Offset 0x67 - Acceleration vectormagnitude Y-axis reference value MSB
2310 ** ------------------------------*/
2311 typedef union {
2312  struct {
2313  uint8_t a_vecm_initz : 6; /* Most significant 6 bits of the signed 14-bit initial Z-axis value */
2314 
2315  } b;
2316  uint8_t w;
2317 } FXLS8471Q_A_VECM_INITZ_MSB_t;
2318 
2319 
2320 /*
2321 ** A_VECM_INITZ_MSB - Bit field mask definitions
2322 */
2323 #define FXLS8471Q_A_VECM_INITZ_MSB_A_VECM_INITZ_MASK ((uint8_t) 0x3F)
2324 #define FXLS8471Q_A_VECM_INITZ_MSB_A_VECM_INITZ_SHIFT ((uint8_t) 0)
2325 
2326 
2327 /*------------------------------*/
2328 
2329 
2330 
2331 /*--------------------------------
2332 ** Register: A_VECM_INITZ_LSB
2333 ** Enum: FXLS8471Q_A_VECM_INITZ_LSB
2334 ** --
2335 ** Offset 0x68 - Acceleration vectormagnitude Z-axis reference value LSB
2336 ** ------------------------------*/
2337 typedef uint8_t FXLS8471Q_A_VECM_INITZ_LSB_t;
2338 
2339 
2340 
2341 /*--------------------------------
2342 ** Register: A_FFMT_THS_X_MSB
2343 ** Enum: FXLS8471Q_A_FFMT_THS_X_MSB
2344 ** --
2345 ** Offset 0x73 - X-axis FMT threshold MSB
2346 ** ------------------------------*/
2347 typedef union {
2348  struct {
2349  uint8_t a_ffmt_ths_x : 7; /* 7-bit MSB of X-axis acceleration threshold */
2350 
2351  uint8_t a_ffmt_ths_xyz_en : 1;
2352  } b;
2353  uint8_t w;
2354 } FXLS8471Q_A_FFMT_THS_X_MSB_t;
2355 
2356 
2357 /*
2358 ** A_FFMT_THS_X_MSB - Bit field mask definitions
2359 */
2360 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_X_MASK ((uint8_t) 7F)
2361 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2362 
2363 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_MASK ((uint8_t) 0x80)
2364 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_SHIFT ((uint8_t) 7)
2365 
2366 
2367 /*
2368 ** A_FFMT_THS_X_MSB - Bit field value definitions
2369 */
2370 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_EN ((uint8_t) 0x80) /* the ASIC ignores the common 7-bit */
2371  /* G_FFMT_THS value located in register x17 */
2372  /* when executing the FFMT function, and the */
2373  /* following independent threshold values are */
2374  /* used for each axis */
2375 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_DIS ((uint8_t) 0x00) /* the ASIC uses the ffmt_ths[6:0] value */
2376  /* located in register x17[6:0] as a common */
2377  /* threshold for the X, Y, and Z-axis */
2378  /* acceleration detection. The common */
2379  /* unsigned 7-bit acceleration threshold has */
2380  /* a fixed resolution of 63 mg/LSB, with a */
2381  /* range of 0-127 counts */
2382 /*------------------------------*/
2383 
2384 
2385 
2386 /*--------------------------------
2387 ** Register: A_FFMT_THS_X_LSB
2388 ** Enum: FXLS8471Q_A_FFMT_THS_X_LSB
2389 ** --
2390 ** Offset 0x74 - X-axis FMT threshold LSB
2391 ** ------------------------------*/
2392 typedef union {
2393  struct {
2394  uint8_t a_ffmt_ths_x : 6;
2395  } b;
2396  uint8_t w;
2397 } FXLS8471Q_A_FFMT_THS_X_LSB_t;
2398 
2399 
2400 /*
2401 ** A_FFMT_THS_X_LSB - Bit field mask definitions
2402 */
2403 #define FXLS8471Q_A_FFMT_THS_X_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x3F)
2404 #define FXLS8471Q_A_FFMT_THS_X_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2405 
2406 
2407 /*------------------------------*/
2408 
2409 
2410 
2411 /*--------------------------------
2412 ** Register: A_FFMT_THS_Y_MSB
2413 ** Enum: FXLS8471Q_A_FFMT_THS_Y_MSB
2414 ** --
2415 ** Offset 0x75 - Y-axis FMT threshold MSB
2416 ** ------------------------------*/
2417 typedef union {
2418  struct {
2419  uint8_t a_ffmt_ths_y : 7;
2420  uint8_t a_ffmt_trans_ths_en : 1;
2421  } b;
2422  uint8_t w;
2423 } FXLS8471Q_A_FFMT_THS_Y_MSB_t;
2424 
2425 
2426 /*
2427 ** A_FFMT_THS_Y_MSB - Bit field mask definitions
2428 */
2429 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x7F)
2430 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
2431 
2432 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_TRANS_THS_EN_MASK ((uint8_t) 0x80)
2433 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_TRANS_THS_EN_SHIFT ((uint8_t) 7)
2434 
2435 
2436 /*------------------------------*/
2437 
2438 
2439 
2440 /*--------------------------------
2441 ** Register: A_FFMT_THS_Y_LSB
2442 ** Enum: FXLS8471Q_A_FFMT_THS_Y_LSB
2443 ** --
2444 ** Offset 0x76 - Y-axis FMT threshold LSB
2445 ** ------------------------------*/
2446 typedef union {
2447  struct {
2448  uint8_t a_ffmt_ths_y : 6;
2449  } b;
2450  uint8_t w;
2451 } FXLS8471Q_A_FFMT_THS_Y_LSB_t;
2452 
2453 
2454 /*
2455 ** A_FFMT_THS_Y_LSB - Bit field mask definitions
2456 */
2457 #define FXLS8471Q_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x3F)
2458 #define FXLS8471Q_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
2459 
2460 
2461 /*------------------------------*/
2462 
2463 
2464 
2465 /*--------------------------------
2466 ** Register: A_FFMT_THS_Z_MSB
2467 ** Enum: FXLS8471Q_A_FFMT_THS_Z_MSB
2468 ** --
2469 ** Offset 0x77 - Z-axis FMT threshold MSB
2470 ** ------------------------------*/
2471 typedef union {
2472  struct {
2473  uint8_t a_ffmt_ths_z : 7;
2474  } b;
2475  uint8_t w;
2476 } FXLS8471Q_A_FFMT_THS_Z_MSB_t;
2477 
2478 
2479 /*
2480 ** A_FFMT_THS_Z_MSB - Bit field mask definitions
2481 */
2482 #define FXLS8471Q_A_FFMT_THS_Z_MSB_A_FFMT_THS_Z_MASK ((uint8_t) 0x7F)
2483 #define FXLS8471Q_A_FFMT_THS_Z_MSB_A_FFMT_THS_Z_SHIFT ((uint8_t) 0)
2484 
2485 
2486 /*------------------------------*/
2487 
2488 
2489 
2490 /*--------------------------------
2491 ** Register: A_FFMT_THS_Z_LSB
2492 ** Enum: FXLS8471Q_A_FFMT_THS_Z_LSB
2493 ** --
2494 ** Offset 0x78 - Z-axis FMT threshold LSB
2495 ** ------------------------------*/
2496 typedef union {
2497  struct {
2498  uint8_t a_ffmt_ths_x : 6;
2499  } b;
2500  uint8_t w;
2501 } FXLS8471Q_A_FFMT_THS_Z_LSB_t;
2502 
2503 
2504 /*
2505 ** A_FFMT_THS_Z_LSB - Bit field mask definitions
2506 */
2507 #define FXLS8471Q_A_FFMT_THS_Z_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x3F)
2508 #define FXLS8471Q_A_FFMT_THS_Z_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2509 
2510 
2511 /*------------------------------*/
2512 
2513 
2514 #endif /* _FXLS8471Q_H_ */
FXLS8471Q_A_VECM_CFG_t::w
uint8_t w
Definition: fxls8471q.h:2118
FXLS8471Q_TRIG_CFG_t
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FXLS8471Q_PULSE_CFG_t::w
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FXLS8471Q_A_FFMT_THS_Y_MSB_t
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uint8_t hpf_byp
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FXLS8471Q_PULSE_THSY_t::thsy
uint8_t thsy
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FXLS8471Q_STATUS_t::xdr
uint8_t xdr
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FXLS8471Q_A_VECM_CFG_t::_reserved_
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FXLS8471Q_A_FFMT_THS_Y_LSB_t::w
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Definition: fxls8471q.h:2450
FXLS8471Q_STATUS_t::zdr
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Definition: fxls8471q.h:132
FXLS8471Q_CTRL_REG1_t::w
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Definition: fxls8471q.h:1658
FXLS8471Q_HP_FILTER_CUTOFF_t::_reserved_
uint8_t _reserved_
Definition: fxls8471q.h:591
FXLS8471Q_A_FFMT_THS_t::ths
uint8_t ths
Definition: fxls8471q.h:1009
FXLS8471Q_A_FFMT_THS_X_MSB_t
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FXLS8471Q_INT_SOURCE_t
Definition: fxls8471q.h:453
FXLS8471Q_A_FFMT_SRC_t::_reserved_
uint8_t _reserved_
Definition: fxls8471q.h:947
FXLS8471Q_A_FFMT_THS_Z_LSB_t::w
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Definition: fxls8471q.h:2500
FXLS8471Q_PL_THS_REG_t
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FXLS8471Q_OFF_Y_t::d
uint8_t d
Definition: fxls8471q.h:2054
FXLS8471Q_INT_SOURCE_t::src_pulse
uint8_t src_pulse
Definition: fxls8471q.h:461
FXLS8471Q_PULSE_WIND_t
Definition: fxls8471q.h:1592
FXLS8471Q_CTRL_REG3_t::wake_pulse
uint8_t wake_pulse
Definition: fxls8471q.h:1786
FXLS8471Q_A_FFMT_THS_Z_LSB_t::a_ffmt_ths_x
uint8_t a_ffmt_ths_x
Definition: fxls8471q.h:2498
FXLS8471Q_A_FFMT_CFG_t::ele
uint8_t ele
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FXLS8471Q_PULSE_LTCY_t
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FXLS8471Q_A_VECM_CFG_t::a_vecm_ele
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FXLS8471Q_A_VECM_INITZ_MSB_t
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FXLS8471Q_CTRL_REG4_t
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FXLS8471Q_TRANSIENT_SRC_t
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FXLS8471Q_A_FFMT_THS_Y_MSB_t::a_ffmt_ths_y
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FXLS8471Q_OUT_Y_MSB_t
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FXLS8471Q_F_SETUP_t
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FXLS8471Q_SYSMOD_t::w
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FXLS8471Q_A_VECM_CFG_t::a_vecm_en
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FXLS8471Q_A_FFMT_THS_Y_LSB_t
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FXLS8471Q_A_FFMT_CFG_t
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FXLS8471Q_CTRL_REG4_t::int_en_ff_mt
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FXLS8471Q_OUT_Z_MSB_t
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FXLS8471Q_F_SETUP_t::f_wmrk
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FXLS8471Q_PULSE_CFG_t
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FXLS8471Q_A_VECM_THS_MSB_t
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FXLS8471Q_F_STATUS_t::f_cnt
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FXLS8471Q_HP_FILTER_CUTOFF_t
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FXLS8471Q_A_FFMT_THS_t
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Definition: fxls8471q.h:1367
FXLS8471Q_TRANSIENT_CFG_t::ytefe
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Definition: fxls8471q.h:1076
FXLS8471Q_TRANSIENT_CFG_t::xtefe
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Definition: fxls8471q.h:1073
FXLS8471Q_ASLP_COUNT_t
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FXLS8471Q_PL_CFG_t
Definition: fxls8471q.h:694
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FXLS8471Q_TRANSIENT_COUNT_t::w
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FXLS8471Q_A_VECM_INITX_MSB_t::w
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FXLS8471Q_CTRL_REG3_t::ipol
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FXLS8471Q_INT_SOURCE_t::src_fifo
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FXLS8471Q_A_FFMT_THS_X_LSB_t
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FXLS8471Q_A_VECM_CFG_t
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Definition: fxls8471q.h:640
FXLS8471Q_PULSE_THSZ_t::reserved
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FXLS8471Q_A_FFMT_THS_Z_MSB_t
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FXLS8471Q_TRANSIENT_CFG_t
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FXLS8471Q_A_VECM_THS_LSB_t
uint8_t FXLS8471Q_A_VECM_THS_LSB_t
Definition: fxls8471q.h:2203
FXLS8471Q_A_VECM_CNT_t
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FXLS8471Q_A_VECM_INITY_MSB_t::w
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FXLS8471Q_OUT_X_MSB_t
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FXLS8471Q_PULSE_TMLT_t::w
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FXLS8471Q_HP_FILTER_CUTOFF_t::pulse_hpf_byp
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FXLS8471Q_A_VECM_INITZ_MSB_t::a_vecm_initz
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Definition: fxls8471q.h:2031
FXLS8471Q_PULSE_SRC_t::w
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FXLS8471Q_STATUS_t::yow
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Definition: fxls8471q.h:1872
FXLS8471Q_A_VECM_INITZ_LSB_t
uint8_t FXLS8471Q_A_VECM_INITZ_LSB_t
Definition: fxls8471q.h:2337
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Definition: fxls8471q.h:1087
FXLS8471Q_A_FFMT_CFG_t::reserved
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FXLS8471Q_A_FFMT_THS_X_MSB_t::w
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FXLS8471Q_A_VECM_INITX_LSB_t
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