ISSDK  1.7
IoT Sensing Software Development Kit
fxls8962.h
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1 /*
2  * The Clear BSD License
3  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
4  * Copyright 2016-2017 NXP
5  * All rights reserved.
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34 /**
35  * @file fxls8962.h
36  * @brief This file contains the FXLS8962 Accelerometer register definitions, access macros, and
37  * device access functions.
38  */
39 #ifndef FXLS8962_H_
40 #define FXLS8962_H_
41 #include <stddef.h>
42 #include <stdint.h>
43 #include <stdbool.h>
44 /**
45  * @brief The FXLS8962 types
46  */
47 
48 /**
49  **
50  ** @brief The FXLS8962 Sensor Internal Register Map.
51  */
52 enum
53 {
54  FXLS8962_INT_STATUS = 0x00,
55  FXLS8962_TEMP_OUT = 0x01,
56  FXLS8962_VECM_LSB = 0x02,
57  FXLS8962_VECM_MSB = 0x03,
58  FXLS8962_OUT_X_LSB = 0x04,
59  FXLS8962_OUT_X_MSB = 0x05,
60  FXLS8962_OUT_Y_LSB = 0x06,
61  FXLS8962_OUT_Y_MSB = 0x07,
62  FXLS8962_OUT_Z_LSB = 0x08,
63  FXLS8962_OUT_Z_MSB = 0x09,
64  FXLS8962_BUF_STATUS = 0x0B,
65  FXLS8962_BUF_X_LSB = 0x0C,
66  FXLS8962_BUF_X_MSB = 0x0D,
67  FXLS8962_BUF_Y_LSB = 0x0E,
68  FXLS8962_BUF_Y_MSB = 0x0F,
69  FXLS8962_BUF_Z_LSB = 0x10,
70  FXLS8962_BUF_Z_MSB = 0x11,
71  FXLS8962_PROD_REV = 0x12,
72  FXLS8962_WHO_AM_I = 0x13,
73  FXLS8962_SYS_MODE = 0x14,
74  FXLS8962_SENS_CONFIG1 = 0x15,
75  FXLS8962_SENS_CONFIG2 = 0x16,
76  FXLS8962_SENS_CONFIG3 = 0x17,
77  FXLS8962_SENS_CONFIG4 = 0x18,
78  FXLS8962_SENS_CONFIG5 = 0x19,
79  FXLS8962_WAKE_IDLE_LSB = 0x1A,
80  FXLS8962_WAKE_IDLE_MSB = 0x1B,
81  FXLS8962_SLEEP_IDLE_LSB = 0x1C,
82  FXLS8962_SLEEP_IDLE_MSB = 0x1D,
83  FXLS8962_ASLP_COUNT_LSB = 0x1E,
84  FXLS8962_ASLP_COUNT_MSB = 0x1F,
85  FXLS8962_INT_EN = 0x20,
86  FXLS8962_INT_PIN_SEL = 0x21,
87  FXLS8962_OFF_X = 0x22,
88  FXLS8962_OFF_Y = 0x23,
89  FXLS8962_OFF_Z = 0x24,
90  FXLS8962_BUF_CONFIG1 = 0x26,
91  FXLS8962_BUF_CONFIG2 = 0x27,
92  FXLS8962_ORIENT_STATUS = 0x28,
93  FXLS8962_ORIENT_CONFIG = 0x29,
94  FXLS8962_ORIENT_DBCOUNT = 0x2A,
95  FXLS8962_ORIENT_BF_ZCOMP = 0x2B,
96  FXLS8962_ORIENT_THS_REG = 0x2C,
97  FXLS8962_SDCD_INT_SRC1 = 0x2D,
98  FXLS8962_SDCD_INT_SRC2 = 0x2E,
99  FXLS8962_SDCD_CONFIG1 = 0x2F,
100  FXLS8962_SDCD_CONFIG2 = 0x30,
101  FXLS8962_SDCD_OT_DBCNT = 0x31,
102  FXLS8962_SDCD_WT_DBCNT = 0x32,
103  FXLS8962_SDCD_LTHS_LSB = 0x33,
104  FXLS8962_SDCD_LTHS_MSB = 0x34,
105  FXLS8962_SDCD_UTHS_LSB = 0x35,
106  FXLS8962_SDCD_UTHS_MSB = 0x36,
107  FXLS8962_SELF_TEST_CONFIG1 = 0x37,
108  FXLS8962_SELF_TEST_CONFIG2 = 0x38,
109 };
110 
111 #define FXLS8962_DEVICE_ADDRESS_SA0_0 (0x18) /*!< Device Address Value. */
112 #define FXLS8962_DEVICE_ADDRESS_SA0_1 (0x19) /*!< Device Address Value. */
113 #define FXLS8962_WHOAMI_VALUE (0x62) /*!< Who AM I Value. */
114 #define FXLS8962_TBOOT_MAX 20 /*!< Maximum safe value for TBOOT1/2 in ms (1ms, 17.7ms)=~20ms. */
115 
116 /*--------------------------------
117 ** Register: INT_STATUS
118 ** Enum: FXLS8962_INT_STATUS
119 ** --
120 ** Offset : 0x00 Interrupt and system status event flags.
121 ** ------------------------------*/
122 typedef union
123 {
124  struct
125  {
126  uint8_t src_boot : 1; /* System boot complete event flag. */
127 
128  uint8_t src_aslp : 1; /* Auto-Wake/Sleep event status flag. */
129 
130  uint8_t src_orient : 1; /* Orientation change event flag. */
131 
132  uint8_t src_sdcd_wt : 1; /* SDCD within thresholds condition event flag. */
133 
134  uint8_t src_sdcd_ot : 1; /* SDCD outside of threshold condition event flag. */
135 
136  uint8_t src_buf : 1;/* Output data buffer status event flag. */
137 
138  uint8_t src_ovf : 1; /* Output data overflow event flag. */
139 
140  uint8_t src_drdy : 1; /* Output data ready event flag. */
141 
142  } b;
143  uint8_t w;
144 } FXLS8962_INT_STATUS_t;
145 
146 /*
147 ** INT_STATUS - Bit field mask definitions
148 */
149 #define FXLS8962_INT_STATUS_SRC_BOOT_MASK ((uint8_t)0x01)
150 #define FXLS8962_INT_STATUS_SRC_BOOT_SHIFT ((uint8_t)0)
151 
152 #define FXLS8962_INT_STATUS_SRC_ASLP_MASK ((uint8_t)0x02)
153 #define FXLS8962_INT_STATUS_SRC_ASLP_SHIFT ((uint8_t)1)
154 
155 #define FXLS8962_INT_STATUS_SRC_ORIENT_MASK ((uint8_t)0x04)
156 #define FXLS8962_INT_STATUS_SRC_ORIENT_SHIFT ((uint8_t)2)
157 
158 #define FXLS8962_INT_STATUS_SRC_SDCD_WT_MASK ((uint8_t)0x08)
159 #define FXLS8962_INT_STATUS_SRC_SDCD_WT_SHIFT ((uint8_t)3)
160 
161 #define FXLS8962_INT_STATUS_SRC_SDCD_OT_MASK ((uint8_t)0x10)
162 #define FXLS8962_INT_STATUS_SRC_SDCD_OT_SHIFT ((uint8_t)4)
163 
164 #define FXLS8962_INT_STATUS_SRC_BUF_MASK ((uint8_t)0x20)
165 #define FXLS8962_INT_STATUS_SRC_BUF_SHIFT ((uint8_t)5)
166 
167 #define FXLS8962_INT_STATUS_SRC_OVF_MASK ((uint8_t)0x40)
168 #define FXLS8962_INT_STATUS_SRC_OVF_SHIFT ((uint8_t)6)
169 
170 #define FXLS8962_INT_STATUS_SRC_DRDY_MASK ((uint8_t)0x80)
171 #define FXLS8962_INT_STATUS_SRC_DRDY_SHIFT ((uint8_t)7)
172 
173 /*------------------------------*/
174 
175 /*--------------------------------
176 ** Register: TEMP_OUT
177 ** Enum: FXLS8962_TEMP_OUT
178 ** --
179 ** Offset : 0x01 Temperature output data.
180 ** ------------------------------*/
181 typedef uint8_t FXLS8962_TEMP_OUT_t;
182 
183 /*--------------------------------
184 ** Register: VECM_LSB
185 ** Enum: FXLS8962_VECM_LSB
186 ** --
187 ** Offset : 0x02 12-bit unsigned vector magnitude LSB.
188 ** ------------------------------*/
189 typedef uint8_t FXLS8962_VECM_LSB_t;
190 
191 /*--------------------------------
192 ** Register: VECM_MSB
193 ** Enum: FXLS8962_VECM_MSB
194 ** --
195 ** Offset : 0x03 12-bit unsigned vector magnitude MSB.
196 ** ------------------------------*/
197 typedef uint8_t FXLS8962_VECM_MSB_t;
198 
199 /*--------------------------------
200 ** Register: OUT_X_LSB
201 ** Enum: FXLS8962_OUT_X_LSB
202 ** --
203 ** Offset : 0x04 LSB of current 12-bit X-axis accelerometer output data.
204 ** ------------------------------*/
205 typedef uint8_t FXLS8962_OUT_X_LSB_t;
206 
207 /*--------------------------------
208 ** Register: OUT_X_MSB
209 ** Enum: FXLS8962_OUT_X_MSB
210 ** --
211 ** Offset : 0x05 MSB of current 12-bit X-axis accelerometer output data.
212 ** ------------------------------*/
213 typedef uint8_t FXLS8962_OUT_X_MSB_t;
214 
215 /*--------------------------------
216 ** Register: OUT_Y_LSB
217 ** Enum: FXLS8962_OUT_Y_LSB
218 ** --
219 ** Offset : 0x06 LSB of current 12-bit Y-axis accelerometer output data.
220 ** ------------------------------*/
221 typedef uint8_t FXLS8962_OUT_Y_LSB_t;
222 
223 /*--------------------------------
224 ** Register: OUT_Y_MSB
225 ** Enum: FXLS8962_OUT_Y_MSB
226 ** --
227 ** Offset : 0x07 MSB of current 12-bit Y-axis accelerometer output data.
228 ** ------------------------------*/
229 typedef uint8_t FXLS8962_OUT_Y_MSB_t;
230 
231 /*--------------------------------
232 ** Register: OUT_Z_LSB
233 ** Enum: FXLS8962_OUT_Z_LSB
234 ** --
235 ** Offset : 0x08 LSB of current 12-bit Z-axis accelerometer output data.
236 ** ------------------------------*/
237 typedef uint8_t FXLS8962_OUT_Z_LSB_t;
238 
239 /*--------------------------------
240 ** Register: OUT_Z_MSB
241 ** Enum: FXLS8962_OUT_Z_MSB
242 ** --
243 ** Offset : 0x09 MSB of current 12-bit Z-axis accelerometer output data.
244 ** ------------------------------*/
245 typedef uint8_t FXLS8962_OUT_Z_MSB_t;
246 
247 /*--------------------------------
248 ** Register: BUF_STATUS
249 ** Enum: FXLS8962_BUF_STATUS
250 ** --
251 ** Offset : 0x0B Buf status.
252 ** ------------------------------*/
253 typedef union {
254  struct {
255  uint8_t buf_cnt : 6; /* Count of the acceleration data samples */
256 
257  uint8_t buf_ovf : 1; /* Buffer Overflow Event Flag */
258 
259  uint8_t buf_wmrk : 1; /* Buffer Watermark Event Flag */
260 
261  } b;
262  uint8_t w;
263 } FXLS8962_BUF_STATUS_t;
264 
265 
266 /*
267 ** BUF_STATUS - Bit field mask definitions
268 */
269 #define FXLS8962_BUF_STATUS_BUF_CNT_MASK ((uint8_t) 0x3F)
270 #define FXLS8962_BUF_STATUS_BUF_CNT_SHIFT ((uint8_t) 0)
271 
272 #define FXLS8962_BUF_STATUS_BUF_OVF_MASK ((uint8_t) 0x40)
273 #define FXLS8962_BUF_STATUS_BUF_OVF_SHIFT ((uint8_t) 6)
274 
275 #define FXLS8962_BUF_STATUS_BUF_WMRK_MASK ((uint8_t) 0x80)
276 #define FXLS8962_BUF_STATUS_BUF_WMRK_SHIFT ((uint8_t) 7)
277 
278 
279 
280 /*--------------------------------
281 ** Register: BUF_X_LSB
282 ** Enum: FXLS8962_BUF_X_LSB
283 ** --
284 ** Offset : 0x0C LSB Head Tail output buffer buffer X axis.
285 ** ------------------------------*/
286 typedef uint8_t FXLS8962_BUF_X_LSB_t;
287 
288 
289 /*--------------------------------
290 ** Register: BUF_X_MSB
291 ** Enum: FXLS8962_BUF_X_MSB
292 ** --
293 ** Offset : 0x0D MSB Head Tail output buffer buffer Z axis.
294 ** ------------------------------*/
295 typedef uint8_t FXLS8962_BUF_X_MSB_t;
296 
297 
298 /*--------------------------------
299 ** Register: BUF_Y_LSB
300 ** Enum: FXLS8962_BUF_Y_LSB
301 ** --
302 ** Offset : 0x0E LSB Head Tail output buffer buffer Y axis.
303 ** ------------------------------*/
304 typedef uint8_t FXLS8962_BUF_Y_LSB_t;
305 
306 
307 /*--------------------------------
308 ** Register: BUF_Y_MSB
309 ** Enum: FXLS8962_BUF_Y_MSB
310 ** --
311 ** Offset : 0x0F MSB Head Tail output buffer buffer Y axis.
312 ** ------------------------------*/
313 typedef uint8_t FXLS8962_BUF_Y_MSB_t;
314 
315 
316 /*--------------------------------
317 ** Register: BUF_Z_LSB
318 ** Enum: FXLS8962_BUF_Z_LSB
319 ** --
320 ** Offset : 0x10 LSB Head Tail output buffer buffer Z axis.
321 ** ------------------------------*/
322 typedef uint8_t FXLS8962_BUF_Z_LSB_t;
323 
324 
325 /*--------------------------------
326 ** Register: BUF_Z_MSB
327 ** Enum: FXLS8962_BUF_Z_MSB
328 ** --
329 ** Offset : 0x11 MSB Head Tail output buffer buffer Z axis.
330 ** ------------------------------*/
331 typedef uint8_t FXLS8962_BUF_Z_MSB_t;
332 
333 /*--------------------------------
334 ** Register: PROD_REV
335 ** Enum: FXLS8962_PROD_REV
336 ** --
337 ** Offset : 0x12 Product revision number in BCD format.
338 ** ------------------------------*/
339 typedef union
340 {
341  struct
342  {
343  uint8_t prod_rev_min : 4; /* Product revision info, minor product revision value with range 0 to 9 in */
344  /* BCD format. */
345 
346  uint8_t prod_rev_maj : 4; /* Product revision info, major product revision value with range 1 to 9 in */
347  /* BCD format. */
348 
349  } b;
350  uint8_t w;
351 } FXLS8962_PROD_REV_t;
352 
353 /*
354 ** PROD_REV - Bit field mask definitions
355 */
356 #define FXLS8962_PROD_REV_PROD_REV_MIN_MASK ((uint8_t)0x0F)
357 #define FXLS8962_PROD_REV_PROD_REV_MIN_SHIFT ((uint8_t)0)
358 
359 #define FXLS8962_PROD_REV_PROD_REV_MAJ_MASK ((uint8_t)0xF0)
360 #define FXLS8962_PROD_REV_PROD_REV_MAJ_SHIFT ((uint8_t)4)
361 
362 /*--------------------------------
363 ** Register: WHO_AM_I
364 ** Enum: FXLS8962_WHO_AM_I
365 ** --
366 ** Offset : 0x13 8-bit NXP unique sensor Product ID.
367 ** ------------------------------*/
368 typedef uint8_t FXLS8962_WHO_AM_I_t;
369 
370 /*--------------------------------
371 ** Register: SYS_MODE
372 ** Enum: FXLS8962_SYS_MODE
373 ** --
374 ** Offset : 0x14 Current System Operating Mode.
375 ** ------------------------------*/
376 typedef union
377 {
378  struct
379  {
380  uint8_t sys_mode : 2; /* Current System operating mode. */
381 
382  uint8_t buf_gate_cnt : 5; /* number of OOR periods that have elapsed since the BUF _GATE_ERR flag was asserted. */
383 
384  uint8_t buf_gate_error : 1; /* Buffer gate error flag. */
385 
386  } b;
387  uint8_t w;
388 } FXLS8962_SYS_MODE_t;
389 
390 /*
391 ** SYS_MODE - Bit field mask definitions
392 */
393 #define FXLS8962_SYS_MODE_BUF_GATE_ERROR_MASK ((uint8_t)0x03)
394 #define FXLS8962_SYS_MODE_BUF_GATE_ERROR_SHIFT ((uint8_t)0)
395 
396 #define FXLS8962_SYS_MODE_BUF_GATE_CNT_MASK ((uint8_t)0x7C)
397 #define FXLS8962_SYS_MODE_BUF_GATE_CNT_SHIFT ((uint8_t)2)
398 
399 #define FXLS8962_SYS_MODE_SYS_MODE_MASK ((uint8_t)0x80)
400 #define FXLS8962_SYS_MODE_SYS_MODE_SHIFT ((uint8_t)7)
401 
402 /*
403 ** SYS_MODE - Bit field value definitions
404 */
405 #define FXLS8962_SYS_MODE_BUF_GARE_ERROR_NO ((uint8_t)0x00) /* Not Detected. */
406 #define FXLS8962_SYS_MODE_BUF_GARE_ERROR_YES ((uint8_t)0x80)/* Detected. */
407 #define FXLS8962_SYS_MODE_SYS_MODE_STANDBY ((uint8_t)0x00) /* Standby Mode. */
408 #define FXLS8962_SYS_MODE_SYS_MODE_WAKE ((uint8_t)0x01) /* Wake Mode. */
409 #define FXLS8962_SYS_MODE_SYS_MODE_SLEEP ((uint8_t)0x02) /* Sleep Mode. */
410 #define FXLS8962_SYS_MODE_SYS_MODE_EXT_TRIG ((uint8_t)0x03) /* External Trigger Mode. */
411  /*------------------------------*/
412 
413 /*--------------------------------
414 ** Register: SENS_CONFIG1
415 ** Enum: FXLS8962_SENS_CONFIG1
416 ** --
417 ** Offset : 0x15 Configuration register 1.
418 ** ------------------------------*/
419 typedef union
420 {
421  struct
422  {
423  uint8_t active : 1; /* Standby/Active mode selection */
424 
425  uint8_t fsr : 2; /* Full-scale measurement range (FSR) selection. */
426 
427  uint8_t spi_m : 1; /* SPI interface mode selection; selects between 3- and 4-wire operating */
428  /* modes for the SPI interface. */
429 
430  uint8_t st_pol : 1; /* Self-Test Displacement Polarity */
431 
432  uint8_t st_axis_sel : 2; /* Self-Test Axis Selection */
433 
434  uint8_t rst : 1; /* The RST bit may be used to initiate a software reset. */
435 
436  } b;
437  uint8_t w;
438 } FXLS8962_SENS_CONFIG1_t;
439 
440 /*
441 ** SENS_CONFIG1 - Bit field mask definitions
442 */
443 #define FXLS8962_SENS_CONFIG1_ACTIVE_MASK ((uint8_t)0x01)
444 #define FXLS8962_SENS_CONFIG1_ACTIVE_SHIFT ((uint8_t)0)
445 
446 #define FXLS8962_SENS_CONFIG1_FSR_MASK ((uint8_t)0x06)
447 #define FXLS8962_SENS_CONFIG1_FSR_SHIFT ((uint8_t)1)
448 
449 #define FXLS8962_SENS_CONFIG1_SPI_M_MASK ((uint8_t)0x08)
450 #define FXLS8962_SENS_CONFIG1_SPI_M_SHIFT ((uint8_t)3)
451 
452 #define FXLS8962_SENS_CONFIG1_ST_POL_MASK ((uint8_t)0x10)
453 #define FXLS8962_SENS_CONFIG1_ST_POL_SHIFT ((uint8_t)4)
454 
455 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_MASK ((uint8_t)0x60)
456 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_SHIFT ((uint8_t)5)
457 
458 #define FXLS8962_SENS_CONFIG1_RST_MASK ((uint8_t)0x80)
459 #define FXLS8962_SENS_CONFIG1_RST_SHIFT ((uint8_t)7)
460 
461 /*
462 ** SENS_CONFIG1 - Bit field value definitions
463 */
464 #define FXLS8962_SENS_CONFIG1_RST_RST ((uint8_t)0x80) /* Trigger Reset */
465 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_DISABLED \
466  ((uint8_t)0x00) /* Self-Test function is disabled */
467 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_EN_X ((uint8_t)0x20) /* Self-Test function is enabled for X-axis */
468 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_EN_Y ((uint8_t)0x40) /* Self-Test function is enabled for Y-axis */
469 #define FXLS8962_SENS_CONFIG1_ST_AXIS_SEL_EN_Z ((uint8_t)0x60) /* Self-Test function is enabled for Z-axis */
470 #define FXLS8962_SENS_CONFIG1_ST_POL_POSITIVE ((uint8_t)0x00) /* Proof mass displacement for the selected axis */
471  /* is in the positive direction. */
472 #define FXLS8962_SENS_CONFIG1_ST_POL_NEGATIVE ((uint8_t)0x10) /* Proof mass displacement for the selected axis */
473  /* is in the negative direction. */
474 #define FXLS8962_SENS_CONFIG1_SPI_M_FOUR ((uint8_t)0x00) /* 4-wire interface mode is selected. */
475 #define FXLS8962_SENS_CONFIG1_SPI_M_THREE ((uint8_t)0x08) /* 3-wire interface mode is selected. */
476 #define FXLS8962_SENS_CONFIG1_FSR_2G ((uint8_t)0x00) /* ±2g; 0.98 mg/LSB (1024 LSB/g) nominal */
477  /* sensitivity. */
478 #define FXLS8962_SENS_CONFIG1_FSR_4G ((uint8_t)0x02) /* ±4g; 1.95 mg/LSB (512 LSB/g) nominal */
479  /* sensitivity. */
480 #define FXLS8962_SENS_CONFIG1_FSR_8G ((uint8_t)0x04) /* ±8g; 3.91 mg/LSB (256 LSB/g) nominal */
481  /* sensitivity. */
482 #define FXLS8962_SENS_CONFIG1_FSR_16G ((uint8_t)0x06) /* ±16g; 7.81 mg/LSB (128 LSB/g) nominal */
483  /* sensitivity. */
484 #define FXLS8962_SENS_CONFIG1_ACTIVE_STANDBY ((uint8_t)0x00) /* Standby mode. */
485 #define FXLS8962_SENS_CONFIG1_ACTIVE_ACTIVE ((uint8_t)0x01) /* Active mode. */
486  /*------------------------------*/
487 
488 /*--------------------------------
489 ** Register: SENS_CONFIG2
490 ** Enum: FXLS8962_SENS_CONFIG2
491 ** --
492 ** Offset : 0x16 Configuration register 2.
493 ** ------------------------------*/
494 typedef union
495 {
496  struct
497  {
498  uint8_t f_read : 1; /* Fast-read mode selection. */
499 
500  uint8_t anic_temp : 1; /* Temperature output data auto-increment control. */
501 
502  uint8_t _reserved_ : 1;
503  uint8_t le_be : 1; /* Little/Big-endian output mode selection. */
504 
505  uint8_t sleep_pm : 2; /* SLEEP power mode selection. */
506 
507  uint8_t wake_pm : 2; /* WAKE power mode selection. */
508 
509  } b;
510  uint8_t w;
511 } FXLS8962_SENS_CONFIG2_t;
512 
513 /*
514 ** SENS_CONFIG2 - Bit field mask definitions
515 */
516 #define FXLS8962_SENS_CONFIG2_F_READ_MASK ((uint8_t)0x01)
517 #define FXLS8962_SENS_CONFIG2_F_READ_SHIFT ((uint8_t)0)
518 
519 #define FXLS8962_SENS_CONFIG2_ANIC_TEMP_MASK ((uint8_t)0x02)
520 #define FXLS8962_SENS_CONFIG2_ANIC_TEMP_SHIFT ((uint8_t)1)
521 
522 #define FXLS8962_SENS_CONFIG2_LE_BE_MASK ((uint8_t)0x08)
523 #define FXLS8962_SENS_CONFIG2_LE_BE_SHIFT ((uint8_t)3)
524 
525 #define FXLS8962_SENS_CONFIG2_SLEEP_PM_MASK ((uint8_t)0x30)
526 #define FXLS8962_SENS_CONFIG2_SLEEP_PM_SHIFT ((uint8_t)4)
527 
528 #define FXLS8962_SENS_CONFIG2_WAKE_PM_MASK ((uint8_t)0xC0)
529 #define FXLS8962_SENS_CONFIG2_WAKE_PM_SHIFT ((uint8_t)6)
530 
531 /*
532 ** SENS_CONFIG2 - Bit field value definitions
533 */
534 #define FXLS8962_SENS_CONFIG2_WAKE_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
535 #define FXLS8962_SENS_CONFIG2_WAKE_PM_HIGH_PERF ((uint8_t)0x40) /* High Performance Mode is selected. */
536 #define FXLS8962_SENS_CONFIG2_WAKE_PM_FLEX_PERF ((uint8_t)0x80) /* Flexible Performance Mode is selected. */
537 #define FXLS8962_SENS_CONFIG2_SLEEP_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
538 #define FXLS8962_SENS_CONFIG2_SLEEP_PM_HIGH_PERF ((uint8_t)0x10) /* High Performance Mode is selected. */
539 #define FXLS8962_SENS_CONFIG2_SLEEP_PM_FLEX_PERF ((uint8_t)0x20) /* Flexible Performance Mode is selected. */
540 #define FXLS8962_SENS_CONFIG2_LE_BE_LE ((uint8_t)0x00) /* Little-endian output mode is selected. */
541 #define FXLS8962_SENS_CONFIG2_LE_BE_BE ((uint8_t)0x08) /* Big-endian output mode is selected. */
542 #define FXLS8962_SENS_CONFIG2_ANIC_TEMP_DIS ((uint8_t)0x00) /* TEMP_OUT register content is not included in */
543  /* auto-increment address range. */
544 #define FXLS8962_SENS_CONFIG2_ANIC_TEMP_EN ((uint8_t)0x02) /* TEMP_OUT register content is included in */
545  /* auto-increment address range. */
546 #define FXLS8962_SENS_CONFIG2_F_READ_NORMAL ((uint8_t)0x00) /* Normal read mode. */
547 #define FXLS8962_SENS_CONFIG2_F_READ_FAST ((uint8_t)0x01) /* Fast read mode. */
548  /*------------------------------*/
549 
550 /*--------------------------------
551 ** Register: SENS_CONFIG3
552 ** Enum: FXLS8962_SENS_CONFIG3
553 ** --
554 ** Offset : 0x17 Configuration register 3.
555 ** ------------------------------*/
556 typedef union
557 {
558  struct
559  {
560  uint8_t sleep_odr : 4; /* Sleep ODR */
561 
562  uint8_t wake_odr : 4; /* Wake ODR */
563 
564  } b;
565  uint8_t w;
566 } FXLS8962_SENS_CONFIG3_t;
567 
568 /*
569 ** SENS_CONFIG3 - Bit field mask definitions
570 */
571 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_MASK ((uint8_t)0x0F)
572 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_SHIFT ((uint8_t)0)
573 
574 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_MASK ((uint8_t)0xF0)
575 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_SHIFT ((uint8_t)4)
576 
577 /*
578 ** SENS_CONFIG3 - Bit field value definitions
579 */
580 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_3200HZ ((uint8_t)0x00)
581 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_1600HZ ((uint8_t)0x10)
582 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_800HZ ((uint8_t)0x20)
583 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_400HZ ((uint8_t)0x30)
584 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_200HZ ((uint8_t)0x40)
585 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_100HZ ((uint8_t)0x50)
586 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_50HZ ((uint8_t)0x60)
587 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_25HZ ((uint8_t)0x70)
588 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_12_5HZ ((uint8_t)0x80)
589 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_6_25HZ ((uint8_t)0x90) /* 6.25 HZ */
590 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_3_125HZ ((uint8_t)0xa0) /* 3.125 HZ */
591 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_1_563HZ ((uint8_t)0xb0) /* 1.563 HZ */
592 #define FXLS8962_SENS_CONFIG3_WAKE_ODR_0_781HZ ((uint8_t)0xc0) /* 0.781 HZ */
593 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_3200HZ ((uint8_t)0x00)
594 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_1600HZ ((uint8_t)0x01)
595 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_800HZ ((uint8_t)0x02)
596 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_400HZ ((uint8_t)0x03)
597 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_200HZ ((uint8_t)0x04)
598 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_100HZ ((uint8_t)0x05)
599 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_50HZ ((uint8_t)0x06)
600 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_25HZ ((uint8_t)0x07)
601 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_12_5HZ ((uint8_t)0x08)
602 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_6_25HZ ((uint8_t)0x09) /* 6.25 HZ */
603 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_3_125HZ ((uint8_t)0x0a) /* 3.125 HZ */
604 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_1_563HZ ((uint8_t)0x0b) /* 1.563 HZ */
605 #define FXLS8962_SENS_CONFIG3_SLEEP_ODR_0_781HZ ((uint8_t)0x0c) /* 0.781 HZ */
606  /*------------------------------*/
607 
608 /*--------------------------------
609 ** Register: SENS_CONFIG4
610 ** Enum: FXLS8962_SENS_CONFIG4
611 ** --
612 ** Offset : 0x18 Configuration register 4.
613 ** ------------------------------*/
614 typedef union
615 {
616  struct
617  {
618  uint8_t int_pol : 1; /* Interrupt logic polarity on INT1 and INT2 pins. */
619 
620  uint8_t int_pp_od : 1; /* INT1 and INT2 pins output driver selection. */
621 
622  uint8_t int2_func : 1; /* INT2 output / EXT_TRIG input pin selection. */
623 
624  uint8_t drdy_pul : 1; /* Pulse generation option for DRDY event. */
625 
626  uint8_t wk_orient : 1; /* Orientation change event Auto-WAKE/SLEEP transition source enable. */
627 
628  uint8_t wk_sdcd_ot : 1; /* SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable. */
629 
630  uint8_t wk_sdcd_wt : 1; /* SDCD within thresholds event Auto-WAKE/SLEEP transition source enable. */
631 
632  uint8_t ext_trig_m : 1; /* External trigger function acquisition mode. */
633 
634  } b;
635  uint8_t w;
636 } FXLS8962_SENS_CONFIG4_t;
637 
638 /*
639 ** SENS_CONFIG4 - Bit field mask definitions
640 */
641 #define FXLS8962_SENS_CONFIG4_INT_POL_MASK ((uint8_t)0x01)
642 #define FXLS8962_SENS_CONFIG4_INT_POL_SHIFT ((uint8_t)0)
643 
644 #define FXLS8962_SENS_CONFIG4_INT_PP_OD_MASK ((uint8_t)0x02)
645 #define FXLS8962_SENS_CONFIG4_INT_PP_OD_SHIFT ((uint8_t)1)
646 
647 #define FXLS8962_SENS_CONFIG4_INT2_FUNC_MASK ((uint8_t)0x04)
648 #define FXLS8962_SENS_CONFIG4_INT2_FUNC_SHIFT ((uint8_t)2)
649 
650 #define FXLS8962_SENS_CONFIG4_DRDY_PUL_MASK ((uint8_t)0x08)
651 #define FXLS8962_SENS_CONFIG4_DRDY_PUL_SHIFT ((uint8_t)3)
652 
653 #define FXLS8962_SENS_CONFIG4_WK_ORIENT_MASK ((uint8_t)0x10)
654 #define FXLS8962_SENS_CONFIG4_WK_ORIENT_SHIFT ((uint8_t)4)
655 
656 #define FXLS8962_SENS_CONFIG4_WK_SDCD_OT_MASK ((uint8_t)0x20)
657 #define FXLS8962_SENS_CONFIG4_WK_SDCD_OT_SHIFT ((uint8_t)5)
658 
659 #define FXLS8962_SENS_CONFIG4_WK_SDCD_WT_MASK ((uint8_t)0x40)
660 #define FXLS8962_SENS_CONFIG4_WK_SDCD_WT_SHIFT ((uint8_t)6)
661 
662 #define FXLS8962_SENS_CONFIG4_EXT_TRIG_M_MASK ((uint8_t)0x80)
663 #define FXLS8962_SENS_CONFIG4_EXT_TRIG_M_SHIFT ((uint8_t)7)
664 
665 /*
666 ** SENS_CONFIG4 - Bit field value definitions
667 */
668 #define FXLS8962_SENS_CONFIG4_EXT_TRIG_M_SINGLE ((uint8_t)0x00) /* Each positive going trigger edge causes a */
669  /* single ADC acquisition to be made. */
670 #define FXLS8962_SENS_CONFIG4_EXT_TRIG_M_MULTIPLE ((uint8_t)0x80) /* Each positive going trigger edge causes the */
671 /* number of acquisitions. */
672 #define FXLS8962_SENS_CONFIG4_WK_SDCD_WT_DIS ((uint8_t)0x00) /* SDCD within thresholds event is not used to */
673  /* prevent entry into/trigger. */
674 #define FXLS8962_SENS_CONFIG4_WK_SDCD_WT_EN ((uint8_t)0x40) /* SDCD within thresholds event is used to prevent */
675  /* entry into/trigger an exit from SLEEP mode. */
676 #define FXLS8962_SENS_CONFIG4_WK_SDCD_OT_DIS ((uint8_t)0x00) /* SDCD outside thresholds event is not used to */
677  /* prevent entry into/trigger. */
678 #define FXLS8962_SENS_CONFIG4_WK_SDCD_OT_EN ((uint8_t)0x20) /* SDCD outside thresholds event is used to */
679  /* prevent entry into/trigger an exit from SLEEP */
680  /* mode. */
681 #define FXLS8962_SENS_CONFIG4_WK_ORIENT_DIS ((uint8_t)0x00) /* Orientation change condition is not used as an */
682  /* event to prevent entry into /trigger an exit */
683  /* from SLEEP mode. */
684 #define FXLS8962_SENS_CONFIG4_WK_ORIENT_EN ((uint8_t)0x10) /* Orientation change condition is used as an */
685  /* event to prevent entry into/trigger an exit */
686  /* from SLEEP mode. */
687 #define FXLS8962_SENS_CONFIG4_DRDY_PUL_DIS ((uint8_t)0x00) /* A SRC_DRDY event is output on the INTx pin as */
688  /* an active high or active low signal. */
689 #define FXLS8962_SENS_CONFIG4_DRDY_PUL_EN ((uint8_t)0x08) /* A 32 μs (nominal) duration pulse is output on */
690  /* the configured INTx pin once per ODR cycle. */
691 #define FXLS8962_SENS_CONFIG4_INT2_FUNC_INT2 ((uint8_t)0x00) /* INT2/EXT_TRIG pin is configured for the INT2 */
692  /* output function. */
693 #define FXLS8962_SENS_CONFIG4_INT2_FUNC_EXT_TRIG \
694  ((uint8_t)0x04) /* INT2/EXT_TRIG pin is configured as the EXT_TRIG \ \ \
695  */
696 /* input function. */
697 #define FXLS8962_SENS_CONFIG4_INT_PP_OD_PUSH_PULL ((uint8_t)0x00) /* INTx output pin driver is push-pull type. */
698 #define FXLS8962_SENS_CONFIG4_INT_PP_OD_OPEN_DRAIN \
699  ((uint8_t)0x02) /* INTx output pin driver is */
700  /* open-drain/open-source type. */
701 #define FXLS8962_SENS_CONFIG4_INT_POL_ACT_LOW ((uint8_t)0x00) /* Active low:Interrupt events are signaled with a */
702  /* logical 0 level. */
703 #define FXLS8962_SENS_CONFIG4_INT_POL_ACT_HIGH ((uint8_t)0x01) /* Active high: interrupt events are signaled with */
704  /* a logical 1 level. */
705  /*------------------------------*/
706 
707 /*--------------------------------
708 ** Register: SENS_CONFIG5
709 ** Enum: FXLS8962_SENS_CONFIG5
710 ** --
711 ** Offset : 0x19 Configuration register 5.
712 ** ------------------------------*/
713 typedef union
714 {
715  struct
716  {
717  uint8_t hibernate_en : 1; /* Hibernate mode enable. */
718 
719  uint8_t z_dis : 1; /* Z-axis auto-increment disable. */
720 
721  uint8_t y_dis : 1; /* Y-axis auto-increment disable. */
722 
723  uint8_t x_dis : 1; /* X-axis auto-increment disable. */
724 
725  uint8_t vecm_en : 1; /* Vector Magnitude calculation enable. */
726 
727  } b;
728  uint8_t w;
729 } FXLS8962_SENS_CONFIG5_t;
730 
731 /*
732 ** SENS_CONFIG5 - Bit field mask definitions
733 */
734 #define FXLS8962_SENS_CONFIG5_HIBERNATE_EN_MASK ((uint8_t)0x01)
735 #define FXLS8962_SENS_CONFIG5_HIBERNATE_EN_SHIFT ((uint8_t)0)
736 
737 #define FXLS8962_SENS_CONFIG5_Z_DIS_MASK ((uint8_t)0x02)
738 #define FXLS8962_SENS_CONFIG5_Z_DIS_SHIFT ((uint8_t)1)
739 
740 #define FXLS8962_SENS_CONFIG5_Y_DIS_MASK ((uint8_t)0x04)
741 #define FXLS8962_SENS_CONFIG5_Y_DIS_SHIFT ((uint8_t)2)
742 
743 #define FXLS8962_SENS_CONFIG5_X_DIS_MASK ((uint8_t)0x08)
744 #define FXLS8962_SENS_CONFIG5_X_DIS_SHIFT ((uint8_t)3)
745 
746 #define FXLS8962_SENS_CONFIG5_VECM_EN_MASK ((uint8_t)0x10)
747 #define FXLS8962_SENS_CONFIG5_VECM_EN_SHIFT ((uint8_t)4)
748 
749 /*
750 ** SENS_CONFIG5 - Bit field value definitions
751 */
752 #define FXLS8962_SENS_CONFIG5_VECM_EN_DIS ((uint8_t)0x00) /* 12-bit vector magnitude result is not */
753  /* calculated on every ODR cycle. */
754 #define FXLS8962_SENS_CONFIG5_VECM_EN_EN ((uint8_t)0x10) /* 12-bit vector magnitude result is calculated on */
755  /* every ODR cycle. */
756 #define FXLS8962_SENS_CONFIG5_X_DIS_EN ((uint8_t)0x00) /* X-axis measurement is included in the */
757  /* auto-increment address range. */
758 #define FXLS8962_SENS_CONFIG5_X_DIS_DIS ((uint8_t)0x08) /* X-axis measurement is excluded from the */
759  /* auto-increment address range. */
760 #define FXLS8962_SENS_CONFIG5_Y_DIS_EN ((uint8_t)0x00) /* Y-axis measurement is included in the */
761  /* auto-increment address range. */
762 #define FXLS8962_SENS_CONFIG5_Y_DIS_DIS ((uint8_t)0x04) /* Y-axis measurement is excluded from the */
763  /* auto-increment address range. */
764 #define FXLS8962_SENS_CONFIG5_Z_DIS_EN ((uint8_t)0x00) /* Z-axis measurement is included in the */
765  /* auto-increment address range. */
766 #define FXLS8962_SENS_CONFIG5_Z_DIS_DIS ((uint8_t)0x02) /* Z-axis measurement is excluded from the */
767  /* auto-increment address range. */
768 #define FXLS8962_SENS_CONFIG5_HIBERNATE_EN_DIS ((uint8_t)0x00) /* Hibernate mode not enabled. */
769 #define FXLS8962_SENS_CONFIG5_HIBERNATE_EN_EN ((uint8_t)0x01) /* Commands device to enter Hibernate mode. */
770  /*------------------------------*/
771 
772 /*--------------------------------
773 ** Register: WAKE_IDLE_LSB
774 ** Enum: FXLS8962_WAKE_IDLE_LSB
775 ** --
776 ** Offset : 0x1A LSB of 12-bit user programmable wake mode idle.
777 ** ------------------------------*/
778 typedef uint8_t FXLS8962_WAKE_IDLE_LSB_t;
779 
780 /*--------------------------------
781 ** Register: WAKE_IDLE_MSB
782 ** Enum: FXLS8962_WAKE_IDLE_MSB
783 ** --
784 ** Offset : 0x1B MSB of 12-bit user programmable wake mode idle.
785 ** ------------------------------*/
786 typedef uint8_t FXLS8962_WAKE_IDLE_MSB_t;
787 
788 /*--------------------------------
789 ** Register: SLEEP_IDLE_LSB
790 ** Enum: FXLS8962_SLEEP_IDLE_LSB
791 ** --
792 ** Offset : 0x1C LSB of 12-bit user programmable sleep mode idle.
793 ** ------------------------------*/
794 typedef uint8_t FXLS8962_SLEEP_IDLE_LSB_t;
795 
796 /*--------------------------------
797 ** Register: SLEEP_IDLE_MSB
798 ** Enum: FXLS8962_SLEEP_IDLE_MSB
799 ** --
800 ** Offset : 0x1D MSB of 12-bit user programmable sleep mode idle.
801 ** ------------------------------*/
802 typedef uint8_t FXLS8962_SLEEP_IDLE_MSB_t;
803 
804 /*--------------------------------
805 ** Register: ASLP_COUNT_LSB
806 ** Enum: FXLS8962_ASLP_COUNT_LSB
807 ** --
808 ** Offset : 0x1E LSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
809 ** ------------------------------*/
810 typedef uint8_t FXLS8962_ASLP_COUNT_LSB_t;
811 
812 /*--------------------------------
813 ** Register: ASLP_COUNT_MSB
814 ** Enum: FXLS8962_ASLP_COUNT_MSB
815 ** --
816 ** Offset : 0x1F MSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
817 ** ------------------------------*/
818 typedef uint8_t FXLS8962_ASLP_COUNT_MSB_t;
819 
820 /*--------------------------------
821 ** Register: INT_EN
822 ** Enum: FXLS8962_INT_EN
823 ** --
824 ** Offset : 0x20 Interrupt output enable register.
825 ** ------------------------------*/
826 typedef union
827 {
828  struct
829  {
830  uint8_t wake_out_en : 1; /* WAKE power state output enable. */
831 
832  uint8_t boot_dis : 1; /* Boot interrupt output disable. */
833 
834  uint8_t aslp_en : 1; /* Auto-WAKE/SLEEP interrupt output enable. */
835 
836  uint8_t orient_en : 1; /* Orientation interrupt output enable. */
837 
838  uint8_t sdcd_wt_en : 1; /* SDCD within thresholds interrupt output enable. */
839 
840  uint8_t sdcd_ot_en : 1; /* SDCD outside of thresholds interrupt output enable. */
841 
842  uint8_t buf_en : 1; /* Output data buffer interrupt output enable */
843  uint8_t drdy_en : 1; /* Data Ready interrupt output enable. */
844 
845  } b;
846  uint8_t w;
847 } FXLS8962_INT_EN_t;
848 
849 /*
850 ** INT_EN - Bit field mask definitions
851 */
852 #define FXLS8962_INT_EN_WAKE_OUT_EN_MASK ((uint8_t)0x01)
853 #define FXLS8962_INT_EN_WAKE_OUT_EN_SHIFT ((uint8_t)0)
854 
855 #define FXLS8962_INT_EN_BOOT_DIS_MASK ((uint8_t)0x02)
856 #define FXLS8962_INT_EN_BOOT_DIS_SHIFT ((uint8_t)1)
857 
858 #define FXLS8962_INT_EN_ASLP_EN_MASK ((uint8_t)0x04)
859 #define FXLS8962_INT_EN_ASLP_EN_SHIFT ((uint8_t)2)
860 
861 #define FXLS8962_INT_EN_ORIENT_EN_MASK ((uint8_t)0x08)
862 #define FXLS8962_INT_EN_ORIENT_EN_SHIFT ((uint8_t)3)
863 
864 #define FXLS8962_INT_EN_SDCD_WT_EN_MASK ((uint8_t)0x10)
865 #define FXLS8962_INT_EN_SDCD_WT_EN_SHIFT ((uint8_t)4)
866 
867 #define FXLS8962_INT_EN_SDCD_OT_EN_MASK ((uint8_t)0x20)
868 #define FXLS8962_INT_EN_SDCD_OT_EN_SHIFT ((uint8_t)5)
869 
870 #define FXLS8962_INT_EN_BUF_EN_MASK ((uint8_t)0x40)
871 #define FXLS8962_INT_EN_BUF_EN_SHIFT ((uint8_t)6)
872 
873 #define FXLS8962_INT_EN_DRDY_EN_MASK ((uint8_t)0x80)
874 #define FXLS8962_INT_EN_DRDY_EN_SHIFT ((uint8_t)7)
875 
876 /*
877 ** INT_EN - Bit field value definitions
878 */
879 #define FXLS8962_INT_EN_DRDY_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
880 #define FXLS8962_INT_EN_DRDY_EN_EN ((uint8_t)0x80) /* Interrupt enabled. */
881 #define FXLS8962_INT_EN_BUF_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
882 #define FXLS8962_INT_EN_BUF_EN_EN ((uint8_t)0x40) /* Interrupt enabled. */
883 #define FXLS8962_INT_EN_SDCD_OT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
884 #define FXLS8962_INT_EN_SDCD_OT_EN_EN ((uint8_t)0x20) /* Interrupt is routed to either the INT1 or INT2. */
885 #define FXLS8962_INT_EN_SDCD_WT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
886 #define FXLS8962_INT_EN_SDCD_WT_EN_EN ((uint8_t)0x10) /* Interrupt is routed to either the INT1 or INT2. */
887 #define FXLS8962_INT_EN_ORIENT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
888 #define FXLS8962_INT_EN_ORIENT_EN_EN ((uint8_t)0x08) /* Interrupt is enabled and signaled on either the INT1 */
889  /* or INT2. */
890 #define FXLS8962_INT_EN_ASLP_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
891 #define FXLS8962_INT_EN_ASLP_EN_EN ((uint8_t)0x04) /* Interrupt is enabled and signaled on either the INT1 */
892  /* or INT2. */
893 #define FXLS8962_INT_EN_BOOT_DIS_EN ((uint8_t)0x00) /* Boot interrupt is enabled and routed to either the */
894  /* INT1 or INT2. */
895 #define FXLS8962_INT_EN_BOOT_DIS_DIS ((uint8_t)0x02) /* Interrupt is disabled and not routed to the INTx */
896  /* output pins. */
897 #define FXLS8962_INT_EN_WAKE_OUT_EN_DIS ((uint8_t)0x00) /* The device does not signal the WAKE operating mode on */
898  /* the INTx output pin. */
899 #define FXLS8962_INT_EN_WAKE_OUT_EN_EN ((uint8_t)0x01) /* The device signals that it is currently in WAKE mode */
900  /* via the INT1 or INT2 pin. */
901  /*------------------------------*/
902 
903 /*--------------------------------
904 ** Register: INT_PIN_SEL
905 ** Enum: FXLS8962_INT_PIN_SEL
906 ** --
907 ** Offset : 0x21 Interrupt output pin routing register, INT1 or INT2.
908 ** ------------------------------*/
909 typedef union
910 {
911  struct
912  {
913  uint8_t wk_out_int2 : 1; /* WAKE power state interrupt routing. */
914 
915  uint8_t boot_int2 : 1; /* BOOT event interrupt routing. */
916 
917  uint8_t aslp_int2 : 1; /* Auto-WAKE/SLEEP event interrupt routing. */
918 
919  uint8_t orient_int2 : 1; /* ORIENT event interrupt routing. */
920 
921  uint8_t sdcd_wt_int2 : 1; /* SDCD within thresholds event interrupt routing. */
922 
923  uint8_t sdcd_ot_int2 : 1; /* SDCD outside of thresholds event interrupt routing. */
924 
925  uint8_t buf_int2 : 1; /* Output buffer interrupt routing. */
926 
927  uint8_t drdy_int2 : 1; /* Data Ready interrupt routing. */
928 
929  } b;
930  uint8_t w;
931 } FXLS8962_INT_PIN_SEL_t;
932 
933 /*
934 ** INT_PIN_SEL - Bit field mask definitions
935 */
936 #define FXLS8962_INT_PIN_SEL_WK_OUT_INT2_MASK ((uint8_t)0x01)
937 #define FXLS8962_INT_PIN_SEL_WK_OUT_INT2_SHIFT ((uint8_t)0)
938 
939 #define FXLS8962_INT_PIN_SEL_BOOT_INT2_MASK ((uint8_t)0x02)
940 #define FXLS8962_INT_PIN_SEL_BOOT_INT2_SHIFT ((uint8_t)1)
941 
942 #define FXLS8962_INT_PIN_SEL_ASLP_INT2_MASK ((uint8_t)0x04)
943 #define FXLS8962_INT_PIN_SEL_ASLP_INT2_SHIFT ((uint8_t)2)
944 
945 #define FXLS8962_INT_PIN_SEL_ORIENT_INT2_MASK ((uint8_t)0x08)
946 #define FXLS8962_INT_PIN_SEL_ORIENT_INT2_SHIFT ((uint8_t)3)
947 
948 #define FXLS8962_INT_PIN_SEL_SDCD_WT_INT2_MASK ((uint8_t)0x10)
949 #define FXLS8962_INT_PIN_SEL_SDCD_WT_INT2_SHIFT ((uint8_t)4)
950 
951 #define FXLS8962_INT_PIN_SEL_SDCD_OT_INT2_MASK ((uint8_t)0x20)
952 #define FXLS8962_INT_PIN_SEL_SDCD_OT_INT2_SHIFT ((uint8_t)5)
953 
954 #define FXLS8962_INT_PIN_SEL_BUF_INT2_MASK ((uint8_t)0x40)
955 #define FXLS8962_INT_PIN_SEL_BUF_INT2_SHIFT ((uint8_t)6)
956 
957 #define FXLS8962_INT_PIN_SEL_DRDY_INT2_MASK ((uint8_t)0x80)
958 #define FXLS8962_INT_PIN_SEL_DRDY_INT2_SHIFT ((uint8_t)7)
959 
960 /*
961 ** INT_PIN_SEL - Bit field value definitions
962 */
963 #define FXLS8962_INT_PIN_SEL_DRDY_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
964  /* enabled. */
965 #define FXLS8962_INT_PIN_SEL_DRDY_INT2_EN ((uint8_t)0x80) /* Interrupt signal is routed to INT2 pin if it is */
966  /* enabled. */
967 #define FXLS8962_INT_PIN_SEL_BUF_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
968  /* enabled. */
969 #define FXLS8962_INT_PIN_SEL_BUF_INT2_EN ((uint8_t)0x40) /* Interrupt signal is routed to INT2 pin if it is */
970  /* enabled. */
971 #define FXLS8962_INT_PIN_SEL_SDCD_OT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
972  /* enabled. */
973 #define FXLS8962_INT_PIN_SEL_SDCD_OT_INT2_EN ((uint8_t)0x20) /* Interrupt signal is routed to INT2 pin if it is */
974  /* enabled. */
975 #define FXLS8962_INT_PIN_SEL_SDCD_WT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
976  /* enabled. */
977 #define FXLS8962_INT_PIN_SEL_SDCD_WT_INT2_EN ((uint8_t)0x10) /* Interrupt signal is routed to INT2 pin if it is */
978  /* enabled. */
979 #define FXLS8962_INT_PIN_SEL_ORIENT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
980  /* enabled. */
981 #define FXLS8962_INT_PIN_SEL_ORIENT_INT2_EN ((uint8_t)0x08) /* Interrupt signal is routed to INT2 pin if it is */
982  /* enabled. */
983 #define FXLS8962_INT_PIN_SEL_ASLP_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
984  /* enabled. */
985 #define FXLS8962_INT_PIN_SEL_ASLP_INT2_EN ((uint8_t)0x04) /* Interrupt signal is routed to INT2 pin if it is */
986  /* enabled. */
987 #define FXLS8962_INT_PIN_SEL_BOOT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
988  /* enabled. */
989 #define FXLS8962_INT_PIN_SEL_BOOT_INT2_EN ((uint8_t)0x02) /* Interrupt signal is routed to INT2 pin if it is */
990  /* enabled. */
991 #define FXLS8962_INT_PIN_SEL_WK_OUT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
992  /* enabled. */
993 #define FXLS8962_INT_PIN_SEL_WK_OUT_INT2_EN ((uint8_t)0x01) /* Interrupt signal is routed to INT2 pin if it is */
994  /* enabled. */
995  /*------------------------------*/
996 
997 /*--------------------------------
998 ** Register: OFF_X
999 ** Enum: FXLS8962_OFF_X
1000 ** --
1001 ** Offset : 0x22 X-Acceleration zero-g offset.
1002 ** ------------------------------*/
1003 typedef uint8_t FXLS8962_OFF_X_t;
1004 
1005 /*--------------------------------
1006 ** Register: OFF_Y
1007 ** Enum: FXLS8962_OFF_Y
1008 ** --
1009 ** Offset : 0x23 Y-Acceleration zero-g offset.
1010 ** ------------------------------*/
1011 typedef uint8_t FXLS8962_OFF_Y_t;
1012 
1013 /*--------------------------------
1014 ** Register: OFF_Z
1015 ** Enum: FXLS8962_OFF_Z
1016 ** --
1017 ** Offset : 0x24 Z-Acceleration zero-g offset.
1018 ** ------------------------------*/
1019 typedef uint8_t FXLS8962_OFF_Z_t;
1020 
1021 
1022 
1023 /*--------------------------------
1024 ** Register: BUF_CONFIG1
1025 ** Enum: FXLS8962_BUF_CONFIG1
1026 ** --
1027 ** Offset : 0x26 Buf configuration1.
1028 ** ------------------------------*/
1029 typedef union {
1030  struct {
1031  uint8_t trg_orient : 1; /* Orientation change event trigger enable */
1032 
1033  uint8_t _reserved_ : 1;
1034  uint8_t trg_sdcd_ot : 1; /* SDCD outside-of-thresholds event buffer trigger enable */
1035 
1036  uint8_t trg_sdcd_wt : 1; /* SDCD within-thresholds event trigger enable */
1037 
1038  uint8_t buf_gate : 1; /* Output data buffer gate enable */
1039 
1040  uint8_t buf_mode : 2; /* Buffer data collection mode */
1041 
1042  uint8_t buf_type : 1; /* Buffer data read out order */
1043 
1044  } b;
1045  uint8_t w;
1046 } FXLS8962_BUF_CONFIG1_t;
1047 
1048 
1049 /*
1050 ** BUF_CONFIG1 - Bit field mask definitions
1051 */
1052 #define FXLS8962_BUF_CONFIG1_TRG_ORIENT_MASK ((uint8_t) 0x01)
1053 #define FXLS8962_BUF_CONFIG1_TRG_ORIENT_SHIFT ((uint8_t) 0)
1054 
1055 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_OT_MASK ((uint8_t) 0x04)
1056 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_OT_SHIFT ((uint8_t) 2)
1057 
1058 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_WT_MASK ((uint8_t) 0x08)
1059 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_WT_SHIFT ((uint8_t) 3)
1060 
1061 #define FXLS8962_BUF_CONFIG1_BUF_GATE_MASK ((uint8_t) 0x10)
1062 #define FXLS8962_BUF_CONFIG1_BUF_GATE_SHIFT ((uint8_t) 4)
1063 
1064 #define FXLS8962_BUF_CONFIG1_BUF_MODE_MASK ((uint8_t) 0x60)
1065 #define FXLS8962_BUF_CONFIG1_BUF_MODE_SHIFT ((uint8_t) 5)
1066 
1067 #define FXLS8962_BUF_CONFIG1_BUF_TYPE_MASK ((uint8_t) 0x80)
1068 #define FXLS8962_BUF_CONFIG1_BUF_TYPE_SHIFT ((uint8_t) 7)
1069 
1070 
1071 /*
1072 ** BUF_CONFIG1 - Bit field value definitions
1073 */
1074 #define FXLS8962_BUF_CONFIG1_BUF_TYPE_FIFO ((uint8_t) 0x00) /* In FIFO mode */
1075 #define FXLS8962_BUF_CONFIG1_BUF_TYPE_FILO ((uint8_t) 0x80) /* First In Last Out (FILO) */
1076 #define FXLS8962_BUF_CONFIG1_BUF_MODE_DIS ((uint8_t) 0x00) /* Buffer is disabled */
1077 #define FXLS8962_BUF_CONFIG1_BUF_MODE_STREAM_MODE ((uint8_t) 0x20) /* Stream Mode */
1078 #define FXLS8962_BUF_CONFIG1_BUF_MODE_STOP_MODE ((uint8_t) 0x40) /* Stop mode */
1079 #define FXLS8962_BUF_CONFIG1_BUF_MODE_TRIGGER_MODE ((uint8_t) 0x60) /* Trigger Mode */
1080 #define FXLS8962_BUF_CONFIG1_BUF_GATE_BY_PASSED ((uint8_t) 0x00) /* Buffer gate is bypassed. */
1081 #define FXLS8962_BUF_CONFIG1_BUF_GATE_ENABLED ((uint8_t) 0x10) /* The Buffer gate input is enabled. */
1082 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_WT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1083 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_WT_EN ((uint8_t) 0x08) /* Trigger source is enabled. */
1084 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_OT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1085 #define FXLS8962_BUF_CONFIG1_TRG_SDCD_OT_EN ((uint8_t) 0x04) /* Trigger source is enabled. */
1086 #define FXLS8962_BUF_CONFIG1_TRG_ORIENT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1087 #define FXLS8962_BUF_CONFIG1_TRG_ORIENT_EN ((uint8_t) 0x01) /* Trigger source is enabled. */
1088 /*------------------------------*/
1089 
1090 
1091 
1092 /*--------------------------------
1093 ** Register: BUF_CONFIG2
1094 ** Enum: FXLS8962_BUF_CONFIG2
1095 ** --
1096 ** Offset : 0x27 buf configuration2.
1097 ** ------------------------------*/
1098 typedef union {
1099  struct {
1100  uint8_t buf_wmrk : 6; /* Buffer sample count watermark */
1101 
1102  uint8_t wake_src_buf : 1; /* Buffer WAKE-to-SLEEP transition source enable */
1103 
1104  uint8_t buf_flush : 1; /* Buffer flush enable */
1105 
1106  } b;
1107  uint8_t w;
1108 } FXLS8962_BUF_CONFIG2_t;
1109 
1110 
1111 /*
1112 ** BUF_CONFIG2 - Bit field mask definitions
1113 */
1114 #define FXLS8962_BUF_CONFIG2_BUF_WMRK_MASK ((uint8_t) 0x3F)
1115 #define FXLS8962_BUF_CONFIG2_BUF_WMRK_SHIFT ((uint8_t) 0)
1116 
1117 #define FXLS8962_BUF_CONFIG2_WAKE_SRC_BUF_MASK ((uint8_t) 0x40)
1118 #define FXLS8962_BUF_CONFIG2_WAKE_SRC_BUF_SHIFT ((uint8_t) 6)
1119 
1120 #define FXLS8962_BUF_CONFIG2_BUF_FLUSH_MASK ((uint8_t) 0x80)
1121 #define FXLS8962_BUF_CONFIG2_BUF_FLUSH_SHIFT ((uint8_t) 7)
1122 
1123 
1124 /*
1125 ** BUF_CONFIG2 - Bit field value definitions
1126 */
1127 #define FXLS8962_BUF_CONFIG2_BUF_FLUSH_COMPLETED ((uint8_t) 0x00) /* Buffer flush operation not pending/completed. */
1128 #define FXLS8962_BUF_CONFIG2_BUF_FLUSH_EN ((uint8_t) 0x80) /* Buffer flush enable. */
1129 #define FXLS8962_BUF_CONFIG2_WAKE_SRC_BUF_IGNORED ((uint8_t) 0x00) /* BUF_WMRK and BUF_OVF and event flags are ignored */
1130  /* by the auto-WAKE/SLEEP function. */
1131 #define FXLS8962_BUF_CONFIG2_WAKE_SRC_BUF_EN ((uint8_t) 0x40) /* BUF_WMRK and BUF_OVF event flags are used by the */
1132  /* auto-WAKE/SLEEP function */
1133 
1134 
1135 /*--------------------------------
1136 ** Register: ORIENT_STATUS
1137 ** Enum: FXLS8962_ORIENT_STATUS
1138 ** --
1139 ** Offset : 0x28 Orientation event status.
1140 ** ------------------------------*/
1141 typedef union
1142 {
1143  struct
1144  {
1145  uint8_t bafro : 1; /* Back or front orientation. */
1146 
1147  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
1148 
1149  uint8_t _reserved_ : 3;
1150  uint8_t lo : 1; /* Z-tilt angle lockout. */
1151 
1152  uint8_t new_orient : 1; /* Orientation status change flag. */
1153 
1154  } b;
1155  uint8_t w;
1156 } FXLS8962_ORIENT_STATUS_t;
1157 
1158 /*
1159 ** ORIENT_STATUS - Bit field mask definitions
1160 */
1161 #define FXLS8962_ORIENT_STATUS_BAFRO_MASK ((uint8_t)0x01)
1162 #define FXLS8962_ORIENT_STATUS_BAFRO_SHIFT ((uint8_t)0)
1163 
1164 #define FXLS8962_ORIENT_STATUS_LAPO_MASK ((uint8_t)0x06)
1165 #define FXLS8962_ORIENT_STATUS_LAPO_SHIFT ((uint8_t)1)
1166 
1167 #define FXLS8962_ORIENT_STATUS_LO_MASK ((uint8_t)0x40)
1168 #define FXLS8962_ORIENT_STATUS_LO_SHIFT ((uint8_t)6)
1169 
1170 #define FXLS8962_ORIENT_STATUS_NEW_ORIENT_MASK ((uint8_t)0x80)
1171 #define FXLS8962_ORIENT_STATUS_NEW_ORIENT_SHIFT ((uint8_t)7)
1172 
1173 /*
1174 ** ORIENT_STATUS - Bit field value definitions
1175 */
1176 #define FXLS8962_ORIENT_STATUS_NEW_ORIENT_NO_CHANGE \
1177  ((uint8_t)0x00) /* No change in orientation detected. */
1178 #define FXLS8962_ORIENT_STATUS_NEW_ORIENT_CHANGED ((uint8_t)0x80) /* BAFRO and/or LAPO and/or Z-tilt lockout value */
1179 /* has changed. */
1180 #define FXLS8962_ORIENT_STATUS_LO_NOT_DETECTED ((uint8_t)0x00) /* Lockout condition has not been detected. */
1181 #define FXLS8962_ORIENT_STATUS_LO_DETECTED ((uint8_t)0x40) /* Z-tilt lockout trip angle has been exceeded. */
1182  /* Lockout condition has been detected. */
1183 #define FXLS8962_ORIENT_STATUS_LAPO_UP ((uint8_t)0x00) /* Portrait up. */
1184 #define FXLS8962_ORIENT_STATUS_LAPO_DOWN ((uint8_t)0x02) /* Portrait down. */
1185 #define FXLS8962_ORIENT_STATUS_LAPO_RIGHT ((uint8_t)0x04) /* Landscape right. */
1186 #define FXLS8962_ORIENT_STATUS_LAPO_LEFT ((uint8_t)0x06) /* Landscape left. */
1187 #define FXLS8962_ORIENT_STATUS_BAFRO_FRONT ((uint8_t)0x00) /* The device is in the front-facing orientation. */
1188 #define FXLS8962_ORIENT_STATUS_BAFRO_BACK ((uint8_t)0x01) /* The device is in the back-facing orientation. */
1189  /*------------------------------*/
1190 
1191 /*--------------------------------
1192 ** Register: ORIENT_CONFIG
1193 ** Enum: FXLS8962_ORIENT_CONFIG
1194 ** --
1195 ** Offset : 0x29 Orientation detection function configuration.
1196 ** ------------------------------*/
1197 typedef union
1198 {
1199  struct
1200  {
1201  uint8_t _reserved_ : 6;
1202  uint8_t orient_enable : 1; /* Orientation detection function enable. */
1203 
1204  uint8_t orient_dbcntm : 1; /* Orientation debounce counter mode selection. */
1205 
1206  } b;
1207  uint8_t w;
1208 } FXLS8962_ORIENT_CONFIG_t;
1209 
1210 /*
1211 ** ORIENT_CONFIG - Bit field mask definitions
1212 */
1213 #define FXLS8962_ORIENT_CONFIG_ORIENT_ENABLE_MASK ((uint8_t)0x40)
1214 #define FXLS8962_ORIENT_CONFIG_ORIENT_ENABLE_SHIFT ((uint8_t)6)
1215 
1216 #define FXLS8962_ORIENT_CONFIG_ORIENT_DBCNTM_MASK ((uint8_t)0x80)
1217 #define FXLS8962_ORIENT_CONFIG_ORIENT_DBCNTM_SHIFT ((uint8_t)7)
1218 
1219 /*
1220 ** ORIENT_CONFIG - Bit field value definitions
1221 */
1222 #define FXLS8962_ORIENT_CONFIG_ORIENT_DBCNTM_DEC ((uint8_t)0x00) /* Orientation debounce counter is decremented */
1223  /* whenever the current orientation is different */
1224  /* thanthe previous one. */
1225 #define FXLS8962_ORIENT_CONFIG_ORIENT_DBCNTM_CLR ((uint8_t)0x80) /* Orientation debounce counter is cleared */
1226  /* whenever the current orientation is different */
1227  /* than the previous one. */
1228 #define FXLS8962_ORIENT_CONFIG_ORIENT_ENABLE_DIS ((uint8_t)0x00) /* Orientation detection function is disabled. */
1229 #define FXLS8962_ORIENT_CONFIG_ORIENT_ENABLE_EN ((uint8_t)0x40) /* Orientation detection function is enabled. */
1230  /*------------------------------*/
1231 
1232 /*--------------------------------
1233 ** Register: ORIENT_DBCOUNT
1234 ** Enum: FXLS8962_ORIENT_DBCOUNT
1235 ** --
1236 ** Offset : 0x2A Orientation detection debounce counter.
1237 ** ------------------------------*/
1238 typedef uint8_t FXLS8962_ORIENT_DBCOUNT_t;
1239 
1240 /*--------------------------------
1241 ** Register: ORIENT_BF_ZCOMP
1242 ** Enum: FXLS8962_ORIENT_BF_ZCOMP
1243 ** --
1244 ** Offset : 0x2B Orientation back/front and Z-tilt angle compensation register.
1245 ** ------------------------------*/
1246 typedef union
1247 {
1248  struct
1249  {
1250  uint8_t orient_zlock : 3; /* Z-lock out angle threshold. */
1251 
1252  uint8_t _reserved_ : 3;
1253  uint8_t orient_bkfr : 2; /* Back-Up / Front-Up trip angle threshold. */
1254 
1255  } b;
1256  uint8_t w;
1257 } FXLS8962_ORIENT_BF_ZCOMP_t;
1258 
1259 /*
1260 ** ORIENT_BF_ZCOMP - Bit field mask definitions
1261 */
1262 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_MASK ((uint8_t)0x07)
1263 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_SHIFT ((uint8_t)0)
1264 
1265 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_MASK ((uint8_t)0xC0)
1266 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_SHIFT ((uint8_t)6)
1267 
1268 /*
1269 ** ORIENT_BF_ZCOMP - Bit field value definitions
1270 */
1271 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_80_280_FB_100_260 \
1272  ((uint8_t)0x00) /* Back to front Z < 80° or Z > 280° */
1273  /* and Front to back Z > 100° and Z */
1274  /* < 260° */
1275 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_75_285_FB_105_255 \
1276  ((uint8_t)0x40) /* Back to front Z < 75° or Z > 285° */
1277  /* and Front to back Z > 105° and Z */
1278  /* < 255° */
1279 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_70_290_FB_110_250 \
1280  ((uint8_t)0x80) /* Back to front Z < 70° or Z > 290° */
1281  /* and Front to back Z > 110° and Z */
1282  /* < 250° */
1283 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_65_295_FB_115_245 \
1284  ((uint8_t)0xc0) /* Back to front Z < 65° or Z > 295° */
1285  /* and Front to back Z > 115° and Z */
1286  /* < 250° */
1287 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_13_6 ((uint8_t)0x00) /* Resultant angle 13.6 */
1288 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_17_1 ((uint8_t)0x01) /* Resultant angle 17.1 */
1289 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_20_7 ((uint8_t)0x02) /* Resultant angle 20.7 */
1290 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_24_4 ((uint8_t)0x03) /* Resultant angle 24.4 */
1291 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_28_1 ((uint8_t)0x04) /* Resultant angle 28.1 */
1292 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_32_0 ((uint8_t)0x05) /* Resultant angle 32.0 */
1293 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_36_1 ((uint8_t)0x06) /* Resultant angle 36.1 */
1294 #define FXLS8962_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_40_4 ((uint8_t)0x07) /* Resultant angle 40.4 */
1295  /*------------------------------*/
1296 
1297 /*--------------------------------
1298 ** Register: ORIENT_THS_REG
1299 ** Enum: FXLS8962_ORIENT_THS_REG
1300 ** --
1301 ** Offset : 0x2C Orientation detection state change threshold angle (Portrait/Landscape) and hysteresis settings.
1302 ** ------------------------------*/
1303 typedef union
1304 {
1305  struct
1306  {
1307  uint8_t hys : 3; /* ORIENT_HYS[2:0] */
1308 
1309  uint8_t orient_ths : 5; /* ORIENT_THS[4:0] value */
1310 
1311  } b;
1312  uint8_t w;
1313 } FXLS8962_ORIENT_THS_REG_t;
1314 
1315 /*
1316 ** ORIENT_THS_REG - Bit field mask definitions
1317 */
1318 #define FXLS8962_ORIENT_THS_REG_HYS_MASK ((uint8_t)0x07)
1319 #define FXLS8962_ORIENT_THS_REG_HYS_SHIFT ((uint8_t)0)
1320 
1321 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_MASK ((uint8_t)0xF8)
1322 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_SHIFT ((uint8_t)3)
1323 
1324 /*
1325 ** ORIENT_THS_REG - Bit field value definitions
1326 */
1327 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_0_0 ((uint8_t)0x00) /* 0.0° */
1328 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_1_8 ((uint8_t)0x08) /* 1.8° */
1329 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_3_8 ((uint8_t)0x10) /* 3.8° */
1330 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_5_9 ((uint8_t)0x18) /* 5.9° */
1331 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_8_1 ((uint8_t)0x20) /* 8.1° */
1332 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_10_5 ((uint8_t)0x28) /* 10.5° */
1333 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_13_0 ((uint8_t)0x30) /* 13.0° */
1334 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_15_6 ((uint8_t)0x38) /* 15.6° */
1335 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_18_4 ((uint8_t)0x40) /* 18.4° */
1336 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_21_4 ((uint8_t)0x48) /* 21.4° */
1337 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_24_4 ((uint8_t)0x50) /* 24.4° */
1338 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_27_6 ((uint8_t)0x58) /* 27.6° */
1339 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_31_0 ((uint8_t)0x60) /* 31.0° */
1340 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_34_4 ((uint8_t)0x68) /* 34.4° */
1341 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_37_9 ((uint8_t)0x70) /* 37.9° */
1342 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_41_4 ((uint8_t)0x78) /* 41.4° */
1343 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_45_0 ((uint8_t)0x80) /* 45.0° */
1344 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_48_6 ((uint8_t)0x88) /* 48.6° */
1345 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_52_1 ((uint8_t)0x90) /* 52.1° */
1346 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_55_6 ((uint8_t)0x98) /* 55.6° */
1347 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_59_0 ((uint8_t)0xa0) /* 59.0° */
1348 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_62_4 ((uint8_t)0xa8) /* 62.4° */
1349 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_65_6 ((uint8_t)0xb0) /* 65.6° */
1350 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_68_6 ((uint8_t)0xb8) /* 68.6° */
1351 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_71_6 ((uint8_t)0xc0) /* 71.6° */
1352 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_74_4 ((uint8_t)0xc8) /* 74.4° */
1353 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_77_0 ((uint8_t)0xd0) /* 77.0° */
1354 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_79_5 ((uint8_t)0xd8) /* 79.5° */
1355 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_81_9 ((uint8_t)0xe0) /* 81.9° */
1356 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_84_1 ((uint8_t)0xe8) /* 84.1° */
1357 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_86_2 ((uint8_t)0xf0) /* 86.2° */
1358 #define FXLS8962_ORIENT_THS_REG_ORIENT_THS_88_2 ((uint8_t)0xf8) /* 88.2° */
1359 #define FXLS8962_ORIENT_THS_REG_HYS_45_45 ((uint8_t)0x00) /* L-to-P 45° P-to-L 45° */
1360 #define FXLS8962_ORIENT_THS_REG_HYS_49_41 ((uint8_t)0x01) /* L-to-P 49° P-to-L 41° */
1361 #define FXLS8962_ORIENT_THS_REG_HYS_52_38 ((uint8_t)0x02) /* L-to-P 52° P-to-L 38° */
1362 #define FXLS8962_ORIENT_THS_REG_HYS_56_34 ((uint8_t)0x03) /* L-to-P 56° P-to-L 34° */
1363 #define FXLS8962_ORIENT_THS_REG_HYS_59_31 ((uint8_t)0x04) /* L-to-P 59° P-to-L 31° */
1364 #define FXLS8962_ORIENT_THS_REG_HYS_62_28 ((uint8_t)0x05) /* L-to-P 62° P-to-L 28° */
1365 #define FXLS8962_ORIENT_THS_REG_HYS_66_24 ((uint8_t)0x06) /* L-to-P 66° P-to-L 24° */
1366 #define FXLS8962_ORIENT_THS_REG_HYS_69_21 ((uint8_t)0x07) /* L-to-P 69° P-to-L 21° */
1367  /*------------------------------*/
1368 
1369 /*--------------------------------
1370 ** Register: SDCD_INT_SRC1
1371 ** Enum: FXLS8962_SDCD_INT_SRC1
1372 ** --
1373 ** Offset : 0x2D Sensor data change detection function 1.
1374 ** ------------------------------*/
1375 typedef union
1376 {
1377  struct
1378  {
1379  uint8_t z_ot_pol : 1; /* Z-axis outside of thresholds polarity flag. */
1380 
1381  uint8_t z_ot_ef : 1; /* Z-axis data or delta outside of upper and lower thresholds event flag. */
1382 
1383  uint8_t y_ot_pol : 1; /* Y-axis outside of thresholds polarity flag. */
1384 
1385  uint8_t y_ot_ef : 1; /* Y-axis data or delta outside of upper and lower thresholds event flag. */
1386 
1387  uint8_t x_ot_pol : 1; /* X-axis outside of thresholds polarity flag. */
1388 
1389  uint8_t x_ot_ef : 1; /* X-axis data or delta outside of upper and lower thresholds event flag. */
1390 
1391  uint8_t _reserved_ : 1;
1392  uint8_t ot_ea : 1; /* SDCD outside of thresholds event active flag. */
1393 
1394  } b;
1395  uint8_t w;
1396 } FXLS8962_SDCD_INT_SRC1_t;
1397 
1398 /*
1399 ** SDCD_INT_SRC1 - Bit field mask definitions
1400 */
1401 #define FXLS8962_SDCD_INT_SRC1_Z_OT_POL_MASK ((uint8_t)0x01)
1402 #define FXLS8962_SDCD_INT_SRC1_Z_OT_POL_SHIFT ((uint8_t)0)
1403 
1404 #define FXLS8962_SDCD_INT_SRC1_Z_OT_EF_MASK ((uint8_t)0x02)
1405 #define FXLS8962_SDCD_INT_SRC1_Z_OT_EF_SHIFT ((uint8_t)1)
1406 
1407 #define FXLS8962_SDCD_INT_SRC1_Y_OT_POL_MASK ((uint8_t)0x04)
1408 #define FXLS8962_SDCD_INT_SRC1_Y_OT_POL_SHIFT ((uint8_t)2)
1409 
1410 #define FXLS8962_SDCD_INT_SRC1_Y_OT_EF_MASK ((uint8_t)0x08)
1411 #define FXLS8962_SDCD_INT_SRC1_Y_OT_EF_SHIFT ((uint8_t)3)
1412 
1413 #define FXLS8962_SDCD_INT_SRC1_X_OT_POL_MASK ((uint8_t)0x10)
1414 #define FXLS8962_SDCD_INT_SRC1_X_OT_POL_SHIFT ((uint8_t)4)
1415 
1416 #define FXLS8962_SDCD_INT_SRC1_X_OT_EF_MASK ((uint8_t)0x20)
1417 #define FXLS8962_SDCD_INT_SRC1_X_OT_EF_SHIFT ((uint8_t)5)
1418 
1419 #define FXLS8962_SDCD_INT_SRC1_OT_EA_MASK ((uint8_t)0x80)
1420 #define FXLS8962_SDCD_INT_SRC1_OT_EA_SHIFT ((uint8_t)7)
1421 
1422 /*
1423 ** SDCD_INT_SRC1 - Bit field value definitions
1424 */
1425 #define FXLS8962_SDCD_INT_SRC1_OT_EA_INSIDE ((uint8_t)0x00) /* Event flag has not been asserted. */
1426 #define FXLS8962_SDCD_INT_SRC1_OT_EA_OUTSIDE ((uint8_t)0x80) /* Event flag has been asserted. */
1427 #define FXLS8962_SDCD_INT_SRC1_X_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1428 #define FXLS8962_SDCD_INT_SRC1_X_OT_EF_EVENT_YES ((uint8_t)0x20) /* Event has occured. */
1429 #define FXLS8962_SDCD_INT_SRC1_X_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1430 #define FXLS8962_SDCD_INT_SRC1_X_OT_POL_GT_THS ((uint8_t)0x10) /* Greater than upper threshold. */
1431 #define FXLS8962_SDCD_INT_SRC1_Y_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1432 #define FXLS8962_SDCD_INT_SRC1_Y_OT_EF_EVENT_YES ((uint8_t)0x08) /* Event has occured. */
1433 #define FXLS8962_SDCD_INT_SRC1_Y_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1434 #define FXLS8962_SDCD_INT_SRC1_Y_OT_POL_GT_THS ((uint8_t)0x04) /* Greater than upper threshold. */
1435 #define FXLS8962_SDCD_INT_SRC1_Z_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1436 #define FXLS8962_SDCD_INT_SRC1_Z_OT_EF_EVENT_YES ((uint8_t)0x02) /* Event has occured. */
1437 #define FXLS8962_SDCD_INT_SRC1_Z_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1438 #define FXLS8962_SDCD_INT_SRC1_Z_OT_POL_GT_THS ((uint8_t)0x01) /* Greater than upper threshold. */
1439  /*------------------------------*/
1440 
1441 /*--------------------------------
1442 ** Register: SDCD_INT_SRC2
1443 ** Enum: FXLS8962_SDCD_INT_SRC2
1444 ** --
1445 ** Offset : 0x2E Sensor data change detection function 2.
1446 ** ------------------------------*/
1447 typedef union
1448 {
1449  struct
1450  {
1451  uint8_t _reserved_ : 1;
1452  uint8_t z_wt_ef : 1; /* Z-axis data or delta inside of upper and lower thresholds event flag. */
1453 
1454  uint8_t _reserved_1 : 1;
1455  uint8_t y_wt_ef : 1; /* Y-axis data or delta inside of upper and lower thresholds event flag. */
1456 
1457  uint8_t _reserved_2 : 1;
1458  uint8_t x_wt_ef : 1; /* X-axis data or delta inside of upper and lower thresholds event flag. */
1459 
1460  uint8_t _reserved_3 : 1;
1461  uint8_t wt_ea : 1; /* SDCD within-thresholds event active flag. */
1462 
1463  } b;
1464  uint8_t w;
1465 } FXLS8962_SDCD_INT_SRC2_t;
1466 
1467 /*
1468 ** SDCD_INT_SRC2 - Bit field mask definitions
1469 */
1470 #define FXLS8962_SDCD_INT_SRC2_Z_WT_EF_MASK ((uint8_t)0x02)
1471 #define FXLS8962_SDCD_INT_SRC2_Z_WT_EF_SHIFT ((uint8_t)1)
1472 
1473 #define FXLS8962_SDCD_INT_SRC2_Y_WT_EF_MASK ((uint8_t)0x08)
1474 #define FXLS8962_SDCD_INT_SRC2_Y_WT_EF_SHIFT ((uint8_t)3)
1475 
1476 #define FXLS8962_SDCD_INT_SRC2_X_WT_EF_MASK ((uint8_t)0x20)
1477 #define FXLS8962_SDCD_INT_SRC2_X_WT_EF_SHIFT ((uint8_t)5)
1478 
1479 #define FXLS8962_SDCD_INT_SRC2_WT_EA_MASK ((uint8_t)0x80)
1480 #define FXLS8962_SDCD_INT_SRC2_WT_EA_SHIFT ((uint8_t)7)
1481 
1482 /*
1483 ** SDCD_INT_SRC2 - Bit field value definitions
1484 */
1485 #define FXLS8962_SDCD_INT_SRC2_WT_EA_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1486 #define FXLS8962_SDCD_INT_SRC2_WT_EA_EVENT_YES ((uint8_t)0x80) /* Event has occured. */
1487 #define FXLS8962_SDCD_INT_SRC2_X_WT_EF_IN_RANGE ((uint8_t)0x00) /* X-axis data or delta is >= SDCD_UTHS or =< */
1488  /* SDCD_LTHS values. */
1489 #define FXLS8962_SDCD_INT_SRC2_X_WT_EF_OUT_RANGE ((uint8_t)0x20) /* X-axis data or delta is < SDCD_UTHS and > */
1490  /* SDCD_LTHS value. */
1491 #define FXLS8962_SDCD_INT_SRC2_Y_WT_EF_IN_RANGE ((uint8_t)0x00) /* Y-axis data or delta is >= SDCD_UTHS or =< */
1492  /* SDCD_LTHS values. */
1493 #define FXLS8962_SDCD_INT_SRC2_Y_WT_EF_OUT_RANGE ((uint8_t)0x08) /* Y-axis data or delta is < SDCD_UTHS and > */
1494  /* SDCD_LTHS value. */
1495 #define FXLS8962_SDCD_INT_SRC2_Z_WT_EF_IN_RANGE ((uint8_t)0x00) /* Z-axis data or delta is >= SDCD_UTHS or =< */
1496  /* SDCD_LTHS values. */
1497 #define FXLS8962_SDCD_INT_SRC2_Z_WT_EF_OUT_RANGE ((uint8_t)0x02) /* Z-axis data or delta is < SDCD_UTHS and > */
1498  /* SDCD_LTHS value. */
1499  /*------------------------------*/
1500 
1501 /*--------------------------------
1502 ** Register: SDCD_CONFIG1
1503 ** Enum: FXLS8962_SDCD_CONFIG1
1504 ** --
1505 ** Offset : 0x2F Sensor data change detection function 1 register.
1506 ** ------------------------------*/
1507 typedef union
1508 {
1509  struct
1510  {
1511  uint8_t z_wt_en : 1; /* SDCD function Z-axis within thresholds condition enable. */
1512 
1513  uint8_t y_wt_en : 1; /* SDCD function Y-axis within thresholds condition enable. */
1514 
1515  uint8_t x_wt_en : 1; /* SDCD function X-axis within thresholds condition enable. */
1516 
1517  uint8_t z_ot_en : 1; /* SDCD function Z-axis outside of thresholds condition enable. */
1518 
1519  uint8_t y_ot_en : 1; /* SDCD function Y-axis outside of thresholds condition enable. */
1520 
1521  uint8_t x_ot_en : 1; /* SDCD function X-axis outside of thresholds condition enable. */
1522 
1523  uint8_t wt_ele : 1; /* SDCD within thresholds event latch enable. */
1524 
1525  uint8_t ot_ele : 1; /* SDCD outside of thresholds event latch enable. */
1526 
1527  } b;
1528  uint8_t w;
1529 } FXLS8962_SDCD_CONFIG1_t;
1530 
1531 /*
1532 ** SDCD_CONFIG1 - Bit field mask definitions
1533 */
1534 #define FXLS8962_SDCD_CONFIG1_Z_WT_EN_MASK ((uint8_t)0x01)
1535 #define FXLS8962_SDCD_CONFIG1_Z_WT_EN_SHIFT ((uint8_t)0)
1536 
1537 #define FXLS8962_SDCD_CONFIG1_Y_WT_EN_MASK ((uint8_t)0x02)
1538 #define FXLS8962_SDCD_CONFIG1_Y_WT_EN_SHIFT ((uint8_t)1)
1539 
1540 #define FXLS8962_SDCD_CONFIG1_X_WT_EN_MASK ((uint8_t)0x04)
1541 #define FXLS8962_SDCD_CONFIG1_X_WT_EN_SHIFT ((uint8_t)2)
1542 
1543 #define FXLS8962_SDCD_CONFIG1_Z_OT_EN_MASK ((uint8_t)0x08)
1544 #define FXLS8962_SDCD_CONFIG1_Z_OT_EN_SHIFT ((uint8_t)3)
1545 
1546 #define FXLS8962_SDCD_CONFIG1_Y_OT_EN_MASK ((uint8_t)0x10)
1547 #define FXLS8962_SDCD_CONFIG1_Y_OT_EN_SHIFT ((uint8_t)4)
1548 
1549 #define FXLS8962_SDCD_CONFIG1_X_OT_EN_MASK ((uint8_t)0x20)
1550 #define FXLS8962_SDCD_CONFIG1_X_OT_EN_SHIFT ((uint8_t)5)
1551 
1552 #define FXLS8962_SDCD_CONFIG1_WT_ELE_MASK ((uint8_t)0x40)
1553 #define FXLS8962_SDCD_CONFIG1_WT_ELE_SHIFT ((uint8_t)6)
1554 
1555 #define FXLS8962_SDCD_CONFIG1_OT_ELE_MASK ((uint8_t)0x80)
1556 #define FXLS8962_SDCD_CONFIG1_OT_ELE_SHIFT ((uint8_t)7)
1557 
1558 /*
1559 ** SDCD_CONFIG1 - Bit field value definitions
1560 */
1561 #define FXLS8962_SDCD_CONFIG1_OT_ELE_DIS ((uint8_t)0x00) /* Outside of thresholds event flag latching is */
1562  /* disabled. */
1563 #define FXLS8962_SDCD_CONFIG1_OT_ELE_EN ((uint8_t)0x80) /* Outside of thresholds event flag latching is */
1564  /* enabled. */
1565 #define FXLS8962_SDCD_CONFIG1_WT_ELE_DIS ((uint8_t)0x00) /* Within thresholds event flag latching is */
1566  /* disabled. */
1567 #define FXLS8962_SDCD_CONFIG1_WT_ELE_EN ((uint8_t)0x40) /* Within thresholds event flag latching is */
1568  /* enabled. */
1569 #define FXLS8962_SDCD_CONFIG1_X_OT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1570  /* of thresholds condition evaluation. */
1571 #define FXLS8962_SDCD_CONFIG1_X_OT_EN_EN ((uint8_t)0x20) /* X-axis data or delta is used in the outside of */
1572  /* thresholds condition evaluation. */
1573 #define FXLS8962_SDCD_CONFIG1_Y_OT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1574  /* of thresholds condition evaluation. */
1575 #define FXLS8962_SDCD_CONFIG1_Y_OT_EN_EN ((uint8_t)0x10) /* Y-axis data or delta is used in the outside of */
1576  /* thresholds condition evaluation. */
1577 #define FXLS8962_SDCD_CONFIG1_Z_OT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1578  /* of thresholds condition evaluation. */
1579 #define FXLS8962_SDCD_CONFIG1_Z_OT_EN_EN ((uint8_t)0x08) /* Z-axis data or delta is used in the outside of */
1580  /* thresholds condition evaluation. */
1581 #define FXLS8962_SDCD_CONFIG1_X_WT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1582  /* of thresholds condition evaluation. */
1583 #define FXLS8962_SDCD_CONFIG1_X_WT_EN_EN ((uint8_t)0x04) /* X-axis data or delta is used in the outside of */
1584  /* thresholds condition evaluation. */
1585 #define FXLS8962_SDCD_CONFIG1_Y_WT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1586  /* of thresholds condition evaluation. */
1587 #define FXLS8962_SDCD_CONFIG1_Y_WT_EN_EN ((uint8_t)0x02) /* Y-axis data or delta is used in the outside of */
1588  /* thresholds condition evaluation. */
1589 #define FXLS8962_SDCD_CONFIG1_Z_WT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1590  /* of thresholds condition evaluation. */
1591 #define FXLS8962_SDCD_CONFIG1_Z_WT_EN_EN ((uint8_t)0x01) /* Z-axis data or delta is used in the outside of */
1592  /* thresholds condition evaluation. */
1593  /*------------------------------*/
1594 
1595 /*--------------------------------
1596 ** Register: SDCD_CONFIG2
1597 ** Enum: FXLS8962_SDCD_CONFIG2
1598 ** --
1599 ** Offset : 0x30 Sensor data change detection function 2 register.
1600 ** ------------------------------*/
1601 typedef union
1602 {
1603  struct
1604  {
1605  uint8_t ref_upd : 1; /* SDCD synchronous X/Y/Z reference values update bit. */
1606 
1607  uint8_t mode : 1; /* SDCD input data mode. */
1608 
1609  uint8_t wt_log_sel : 1; /* SDCD within thresholds event logic selection. */
1610 
1611  uint8_t wt_dbctm : 1; /* SDCD within thresholds event debounce counter behavior. */
1612 
1613  uint8_t ot_dbctm : 1; /* SDCD outside of threshold event debounce counter behavior. */
1614 
1615  uint8_t ref_updm : 2; /* SDCD internal reference values update mode. */
1616 
1617  uint8_t sdcd_en : 1; /* SDCD function. */
1618 
1619  } b;
1620  uint8_t w;
1621 } FXLS8962_SDCD_CONFIG2_t;
1622 
1623 /*
1624 ** SDCD_CONFIG2 - Bit field mask definitions
1625 */
1626 #define FXLS8962_SDCD_CONFIG2_REF_UPD_MASK ((uint8_t)0x01)
1627 #define FXLS8962_SDCD_CONFIG2_REF_UPD_SHIFT ((uint8_t)0)
1628 
1629 #define FXLS8962_SDCD_CONFIG2_MODE_MASK ((uint8_t)0x02)
1630 #define FXLS8962_SDCD_CONFIG2_MODE_SHIFT ((uint8_t)1)
1631 
1632 #define FXLS8962_SDCD_CONFIG2_WT_LOG_SEL_MASK ((uint8_t)0x04)
1633 #define FXLS8962_SDCD_CONFIG2_WT_LOG_SEL_SHIFT ((uint8_t)2)
1634 
1635 #define FXLS8962_SDCD_CONFIG2_WT_DBCTM_MASK ((uint8_t)0x08)
1636 #define FXLS8962_SDCD_CONFIG2_WT_DBCTM_SHIFT ((uint8_t)3)
1637 
1638 #define FXLS8962_SDCD_CONFIG2_OT_DBCTM_MASK ((uint8_t)0x10)
1639 #define FXLS8962_SDCD_CONFIG2_OT_DBCTM_SHIFT ((uint8_t)4)
1640 
1641 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_MASK ((uint8_t)0x60)
1642 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_SHIFT ((uint8_t)5)
1643 
1644 #define FXLS8962_SDCD_CONFIG2_SDCD_EN_MASK ((uint8_t)0x80)
1645 #define FXLS8962_SDCD_CONFIG2_SDCD_EN_SHIFT ((uint8_t)7)
1646 
1647 /*
1648 ** SDCD_CONFIG2 - Bit field value definitions
1649 */
1650 #define FXLS8962_SDCD_CONFIG2_SDCD_EN_DIS ((uint8_t)0x00) /* SDCD function is disabled. */
1651 #define FXLS8962_SDCD_CONFIG2_SDCD_EN_EN ((uint8_t)0x80) /* SDCD function is Enabled. */
1652 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_12_BIT ((uint8_t)0x00) /* The function stores the first 12-bit X/Y/Z */
1653  /* decimated and trimmed input data. */
1654 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_FIRST ((uint8_t)0x20) /* The function stores the first decimated and */
1655  /* trimmed X/Y/Z acceleration input data. */
1656 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_SDCD_REF ((uint8_t)0x40) /* The function updates the SDCD_REF_X/Y/Z values */
1657  /* with the current decimated and trimmed X/Y/Z */
1658  /* acceleration input data after the function */
1659  /* evaluation. */
1660 #define FXLS8962_SDCD_CONFIG2_REF_UPDM_FIXED_VAL ((uint8_t)0x60) /* The function uses a fixed value of 0 for each */
1661 /* of the SDCD_REF_X/Y/Z registers. */
1662 #define FXLS8962_SDCD_CONFIG2_OT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1663 /* current outside of thresholds result for the */
1664 /* enabled axes is false. */
1665 #define FXLS8962_SDCD_CONFIG2_OT_DBCTM_CLEARED ((uint8_t)0x10) /* Debounce counter is cleared whenever the */
1666  /* current outside of thresholds result for the */
1667  /* enabled axes is false. */
1668 #define FXLS8962_SDCD_CONFIG2_WT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1669 /* current outside of thresholds result for the */
1670 /* enabled axes is false. */
1671 #define FXLS8962_SDCD_CONFIG2_WT_DBCTM_CLEARED ((uint8_t)0x08) /* Debounce counter is cleared whenever the */
1672  /* current outside of thresholds result for the */
1673  /* enabled axes is false. */
1674 #define FXLS8962_SDCD_CONFIG2_WT_LOG_SEL_AND ((uint8_t)0x00) /* Function uses the logical AND of the enabled */
1675  /* axes. */
1676 #define FXLS8962_SDCD_CONFIG2_WT_LOG_SEL_OR ((uint8_t)0x04) /* Function uses the logical OR of the enabled */
1677  /* axes. */
1678 #define FXLS8962_SDCD_CONFIG2_MODE_XYZ ((uint8_t)0x00) /* Function uses X, Y, Z acceleration data for the */
1679  /* window comparison. */
1680 #define FXLS8962_SDCD_CONFIG2_MODE_VECM ((uint8_t)0x02) /* Function uses Vector magnitude data for the */
1681  /* window comparison on the X-axis channel only. */
1682 #define FXLS8962_SDCD_CONFIG2_REF_UPD_NO_PENDING \
1683  ((uint8_t)0x00) /* No reference update pending or reference update \ \ \
1684  */
1685 /* has completed. */
1686 #define FXLS8962_SDCD_CONFIG2_REF_UPD_SYNC_UPDATE ((uint8_t)0x01) /* Triggers a synchronous update of the internal */
1687  /* X/Y/Z reference registers. */
1688  /*------------------------------*/
1689 
1690 /*--------------------------------
1691 ** Register: SDCD_OT_DBCNT
1692 ** Enum: FXLS8962_SDCD_OT_DBCNT
1693 ** --
1694 ** Offset : 0x31 Sensor Data Change Detection outside of thresholds condition debounce count value.
1695 ** ------------------------------*/
1696 typedef uint8_t FXLS8962_SDCD_OT_DBCNT_t;
1697 
1698 /*--------------------------------
1699 ** Register: SDCD_WT_DBCNT
1700 ** Enum: FXLS8962_SDCD_WT_DBCNT
1701 ** --
1702 ** Offset : 0x32 Sensor Data Change Detection within thresholds condition debounce count value.
1703 ** ------------------------------*/
1704 typedef uint8_t FXLS8962_SDCD_WT_DBCNT_t;
1705 
1706 /*--------------------------------
1707 ** Register: SDCD_LTHS_LSB
1708 ** Enum: FXLS8962_SDCD_LTHS_LSB
1709 ** --
1710 ** Offset : 0x33 Sensor Data Change Detection lower threshold value LSB.
1711 ** ------------------------------*/
1712 typedef uint8_t FXLS8962_SDCD_LTHS_LSB_t;
1713 
1714 /*--------------------------------
1715 ** Register: SDCD_LTHS_MSB
1716 ** Enum: FXLS8962_SDCD_LTHS_MSB
1717 ** --
1718 ** Offset : 0x34 Sensor Data change Detection lower threshold value MSB.
1719 ** ------------------------------*/
1720 typedef uint8_t FXLS8962_SDCD_LTHS_MSB_t;
1721 
1722 /*--------------------------------
1723 ** Register: SDCD_UTHS_LSB
1724 ** Enum: FXLS8962_SDCD_UTHS_LSB
1725 ** --
1726 ** Offset : 0x35 Sensor Data change detection upper threshold value LSB.
1727 ** ------------------------------*/
1728 typedef uint8_t FXLS8962_SDCD_UTHS_LSB_t;
1729 
1730 /*--------------------------------
1731 ** Register: SDCD_UTHS_MSB
1732 ** Enum: FXLS8962_SDCD_UTHS_MSB
1733 ** --
1734 ** Offset : 0x36 Sensor Data change detection upper threshold value MSB.
1735 ** ------------------------------*/
1736 typedef uint8_t FXLS8962_SDCD_UTHS_MSB_t;
1737 
1738 
1739 /*--------------------------------
1740 ** Register: SELF_TEST_CONFIG1
1741 ** Enum: FXLS8962_SELF_TEST_CONFIG1
1742 ** --
1743 ** Offset : 0x37 Self Test Configuration function 1 register.
1744 ** ------------------------------*/
1745 typedef union
1746 {
1747  struct
1748  {
1749  uint8_t st_idle : 5; /* Self-Test Idle phase duration. */
1750 
1751  } b;
1752  uint8_t w;
1753 } FXLS8962_SELF_TEST_CONFIG1_t;
1754 
1755 /*
1756 ** SELF_TEST_CONFIG1 - Bit field mask definitions
1757 */
1758 #define FXLS8962_SELF_TEST_CONFIG1_ST_IDLE_MASK ((uint8_t)0x1f)
1759 #define FXLS8962_SELF_TEST_CONFIG1_ST_IDLE_SHIFT ((uint8_t)0)
1760 
1761 
1762 /*--------------------------------
1763 ** Register: SELF_TEST_CONFIG2
1764 ** Enum: FXLS8962_SELF_TEST_CONFIG2
1765 ** --
1766 ** Offset : 0x38 Self Test Configuration function 2 register.
1767 ** ------------------------------*/
1768 typedef union
1769 {
1770  struct
1771  {
1772  uint8_t st_dec : 4; /* Self-Test measurement phase decimation factor. */
1773 
1774  } b;
1775  uint8_t w;
1776 } FXLS8962_SELF_TEST_CONFIG2_t;
1777 
1778 /*
1779 ** SELF_TEST_CONFIG2 - Bit field mask definitions
1780 */
1781 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_MASK ((uint8_t)0x0f)
1782 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_SHIFT ((uint8_t)0)
1783 
1784 /*
1785 ** SELF_TEST_CONFIG2 - Bit field value definitions
1786 */
1787 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_1 ((uint8_t)0x00)
1788 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_2 ((uint8_t)0x01)
1789 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_4 ((uint8_t)0x02)
1790 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_8 ((uint8_t)0x03)
1791 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_16 ((uint8_t)0x04)
1792 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_32 ((uint8_t)0x05)
1793 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_64 ((uint8_t)0x06)
1794 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_128 ((uint8_t)0x07)
1795 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_256 ((uint8_t)0x08)
1796 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_512 ((uint8_t)0x09)
1797 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_1024 ((uint8_t)0x0a)
1798 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_2048 ((uint8_t)0x0b)
1799 #define FXLS8962_SELF_TEST_CONFIG2_ST_DEC_4096 ((uint8_t)0x0c)
1800 
1801 
1802 #endif /* FXLS8962_H_ */
FXLS8962_INT_STATUS_t::src_boot
uint8_t src_boot
Definition: fxls8962.h:126
FXLS8962_WAKE_IDLE_MSB_t
uint8_t FXLS8962_WAKE_IDLE_MSB_t
Definition: fxls8962.h:786
FXLS8962_ORIENT_CONFIG_t::orient_enable
uint8_t orient_enable
Definition: fxls8962.h:1202
FXLS8962_ORIENT_STATUS_t
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FXLS8962_BUF_CONFIG1_t::trg_sdcd_wt
uint8_t trg_sdcd_wt
Definition: fxls8962.h:1036
FXLS8962_ORIENT_STATUS_t::bafro
uint8_t bafro
Definition: fxls8962.h:1145
FXLS8962_SDCD_INT_SRC1_t::z_ot_ef
uint8_t z_ot_ef
Definition: fxls8962.h:1381
FXLS8962_SDCD_INT_SRC2_t::_reserved_3
uint8_t _reserved_3
Definition: fxls8962.h:1460
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uint8_t wake_src_buf
Definition: fxls8962.h:1102
FXLS8962_SENS_CONFIG2_t
Definition: fxls8962.h:494
FXLS8962_SDCD_UTHS_MSB_t
uint8_t FXLS8962_SDCD_UTHS_MSB_t
Definition: fxls8962.h:1736
FXLS8962_INT_STATUS_t::src_orient
uint8_t src_orient
Definition: fxls8962.h:130
FXLS8962_SENS_CONFIG5_t::z_dis
uint8_t z_dis
Definition: fxls8962.h:719
FXLS8962_SDCD_CONFIG1_t::y_ot_en
uint8_t y_ot_en
Definition: fxls8962.h:1519
FXLS8962_INT_EN_t::buf_en
uint8_t buf_en
Definition: fxls8962.h:842
FXLS8962_OUT_Y_LSB_t
uint8_t FXLS8962_OUT_Y_LSB_t
Definition: fxls8962.h:221
FXLS8962_SDCD_INT_SRC1_t::x_ot_ef
uint8_t x_ot_ef
Definition: fxls8962.h:1389
FXLS8962_ORIENT_THS_REG_t::orient_ths
uint8_t orient_ths
Definition: fxls8962.h:1309
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uint8_t wk_sdcd_ot
Definition: fxls8962.h:628
FXLS8962_INT_STATUS_t::src_buf
uint8_t src_buf
Definition: fxls8962.h:136
FXLS8962_VECM_LSB_t
uint8_t FXLS8962_VECM_LSB_t
Definition: fxls8962.h:189
FXLS8962_SENS_CONFIG4_t::wk_sdcd_wt
uint8_t wk_sdcd_wt
Definition: fxls8962.h:630
FXLS8962_SDCD_CONFIG2_t::ot_dbctm
uint8_t ot_dbctm
Definition: fxls8962.h:1613
FXLS8962_OFF_Z_t
uint8_t FXLS8962_OFF_Z_t
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FXLS8962_INT_EN_t
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FXLS8962_SENS_CONFIG1_t::rst
uint8_t rst
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FXLS8962_BUF_STATUS_t::w
uint8_t w
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FXLS8962_SDCD_OT_DBCNT_t
uint8_t FXLS8962_SDCD_OT_DBCNT_t
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FXLS8962_INT_PIN_SEL_t::drdy_int2
uint8_t drdy_int2
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FXLS8962_SYS_MODE_t::buf_gate_error
uint8_t buf_gate_error
Definition: fxls8962.h:384
FXLS8962_INT_PIN_SEL_t::boot_int2
uint8_t boot_int2
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FXLS8962_SELF_TEST_CONFIG2_t
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FXLS8962_INT_EN_t::boot_dis
uint8_t boot_dis
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FXLS8962_SENS_CONFIG5_t::vecm_en
uint8_t vecm_en
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FXLS8962_INT_STATUS_t
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FXLS8962_BUF_Y_MSB_t
uint8_t FXLS8962_BUF_Y_MSB_t
Definition: fxls8962.h:313
FXLS8962_SENS_CONFIG5_t::w
uint8_t w
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FXLS8962_BUF_Z_MSB_t
uint8_t FXLS8962_BUF_Z_MSB_t
Definition: fxls8962.h:331
FXLS8962_ORIENT_STATUS_t::lo
uint8_t lo
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FXLS8962_SENS_CONFIG1_t
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FXLS8962_INT_EN_t::sdcd_wt_en
uint8_t sdcd_wt_en
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FXLS8962_SDCD_UTHS_LSB_t
uint8_t FXLS8962_SDCD_UTHS_LSB_t
Definition: fxls8962.h:1728
FXLS8962_SENS_CONFIG4_t::int_pol
uint8_t int_pol
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FXLS8962_BUF_X_MSB_t
uint8_t FXLS8962_BUF_X_MSB_t
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FXLS8962_SDCD_INT_SRC1_t
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FXLS8962_SELF_TEST_CONFIG2_t::st_dec
uint8_t st_dec
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FXLS8962_SELF_TEST_CONFIG1_t
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FXLS8962_SENS_CONFIG2_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:502
FXLS8962_ORIENT_BF_ZCOMP_t::_reserved_
uint8_t _reserved_
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FXLS8962_INT_STATUS_t::src_drdy
uint8_t src_drdy
Definition: fxls8962.h:140
FXLS8962_SDCD_CONFIG1_t
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FXLS8962_ORIENT_THS_REG_t::hys
uint8_t hys
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FXLS8962_SYS_MODE_t::buf_gate_cnt
uint8_t buf_gate_cnt
Definition: fxls8962.h:382
FXLS8962_SDCD_INT_SRC2_t::w
uint8_t w
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FXLS8962_SENS_CONFIG4_t::wk_orient
uint8_t wk_orient
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FXLS8962_SDCD_WT_DBCNT_t
uint8_t FXLS8962_SDCD_WT_DBCNT_t
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FXLS8962_SYS_MODE_t::sys_mode
uint8_t sys_mode
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FXLS8962_VECM_MSB_t
uint8_t FXLS8962_VECM_MSB_t
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FXLS8962_SDCD_INT_SRC1_t::w
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FXLS8962_INT_PIN_SEL_t
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FXLS8962_SENS_CONFIG5_t::y_dis
uint8_t y_dis
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FXLS8962_ORIENT_THS_REG_t
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FXLS8962_SENS_CONFIG2_t::le_be
uint8_t le_be
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FXLS8962_SDCD_INT_SRC1_t::y_ot_ef
uint8_t y_ot_ef
Definition: fxls8962.h:1385
FXLS8962_BUF_STATUS_t
Definition: fxls8962.h:253
FXLS8962_ORIENT_CONFIG_t::orient_dbcntm
uint8_t orient_dbcntm
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FXLS8962_ORIENT_BF_ZCOMP_t::orient_bkfr
uint8_t orient_bkfr
Definition: fxls8962.h:1253
FXLS8962_SYS_MODE_t
Definition: fxls8962.h:376
FXLS8962_SDCD_CONFIG1_t::wt_ele
uint8_t wt_ele
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FXLS8962_SDCD_CONFIG1_t::z_wt_en
uint8_t z_wt_en
Definition: fxls8962.h:1511
FXLS8962_PROD_REV_t::w
uint8_t w
Definition: fxls8962.h:350
FXLS8962_BUF_Z_LSB_t
uint8_t FXLS8962_BUF_Z_LSB_t
Definition: fxls8962.h:322
FXLS8962_SYS_MODE_t::w
uint8_t w
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FXLS8962_INT_EN_t::drdy_en
uint8_t drdy_en
Definition: fxls8962.h:843
FXLS8962_BUF_CONFIG1_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:1033
FXLS8962_SDCD_CONFIG2_t
Definition: fxls8962.h:1601
FXLS8962_INT_PIN_SEL_t::buf_int2
uint8_t buf_int2
Definition: fxls8962.h:925
FXLS8962_BUF_CONFIG1_t::buf_type
uint8_t buf_type
Definition: fxls8962.h:1042
FXLS8962_INT_PIN_SEL_t::wk_out_int2
uint8_t wk_out_int2
Definition: fxls8962.h:913
FXLS8962_BUF_CONFIG1_t::trg_sdcd_ot
uint8_t trg_sdcd_ot
Definition: fxls8962.h:1034
FXLS8962_INT_EN_t::sdcd_ot_en
uint8_t sdcd_ot_en
Definition: fxls8962.h:840
FXLS8962_INT_STATUS_t::src_sdcd_wt
uint8_t src_sdcd_wt
Definition: fxls8962.h:132
FXLS8962_SENS_CONFIG4_t::ext_trig_m
uint8_t ext_trig_m
Definition: fxls8962.h:632
FXLS8962_SDCD_CONFIG1_t::z_ot_en
uint8_t z_ot_en
Definition: fxls8962.h:1517
FXLS8962_BUF_CONFIG1_t
Definition: fxls8962.h:1029
FXLS8962_BUF_CONFIG1_t::buf_gate
uint8_t buf_gate
Definition: fxls8962.h:1038
FXLS8962_TEMP_OUT_t
uint8_t FXLS8962_TEMP_OUT_t
Definition: fxls8962.h:181
FXLS8962_INT_PIN_SEL_t::w
uint8_t w
Definition: fxls8962.h:930
FXLS8962_SDCD_CONFIG1_t::x_ot_en
uint8_t x_ot_en
Definition: fxls8962.h:1521
FXLS8962_SDCD_INT_SRC2_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:1451
FXLS8962_SENS_CONFIG3_t::w
uint8_t w
Definition: fxls8962.h:565
FXLS8962_SDCD_INT_SRC2_t
Definition: fxls8962.h:1447
FXLS8962_BUF_CONFIG2_t::buf_wmrk
uint8_t buf_wmrk
Definition: fxls8962.h:1100
FXLS8962_SENS_CONFIG3_t::wake_odr
uint8_t wake_odr
Definition: fxls8962.h:562
FXLS8962_BUF_STATUS_t::buf_ovf
uint8_t buf_ovf
Definition: fxls8962.h:257
FXLS8962_ORIENT_BF_ZCOMP_t
Definition: fxls8962.h:1246
FXLS8962_SENS_CONFIG5_t::hibernate_en
uint8_t hibernate_en
Definition: fxls8962.h:717
FXLS8962_SENS_CONFIG1_t::st_pol
uint8_t st_pol
Definition: fxls8962.h:430
FXLS8962_INT_STATUS_t::src_aslp
uint8_t src_aslp
Definition: fxls8962.h:128
FXLS8962_SDCD_INT_SRC1_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:1391
FXLS8962_SENS_CONFIG1_t::fsr
uint8_t fsr
Definition: fxls8962.h:425
FXLS8962_SDCD_CONFIG2_t::mode
uint8_t mode
Definition: fxls8962.h:1607
FXLS8962_ORIENT_STATUS_t::new_orient
uint8_t new_orient
Definition: fxls8962.h:1152
FXLS8962_BUF_CONFIG2_t
Definition: fxls8962.h:1098
FXLS8962_OUT_Y_MSB_t
uint8_t FXLS8962_OUT_Y_MSB_t
Definition: fxls8962.h:229
FXLS8962_SDCD_INT_SRC2_t::_reserved_2
uint8_t _reserved_2
Definition: fxls8962.h:1457
FXLS8962_ORIENT_STATUS_t::w
uint8_t w
Definition: fxls8962.h:1155
FXLS8962_SDCD_CONFIG1_t::w
uint8_t w
Definition: fxls8962.h:1528
FXLS8962_OFF_X_t
uint8_t FXLS8962_OFF_X_t
Definition: fxls8962.h:1003
FXLS8962_ORIENT_BF_ZCOMP_t::w
uint8_t w
Definition: fxls8962.h:1256
FXLS8962_SDCD_INT_SRC1_t::z_ot_pol
uint8_t z_ot_pol
Definition: fxls8962.h:1379
FXLS8962_INT_EN_t::wake_out_en
uint8_t wake_out_en
Definition: fxls8962.h:830
FXLS8962_WAKE_IDLE_LSB_t
uint8_t FXLS8962_WAKE_IDLE_LSB_t
Definition: fxls8962.h:778
FXLS8962_SDCD_INT_SRC2_t::y_wt_ef
uint8_t y_wt_ef
Definition: fxls8962.h:1455
FXLS8962_ORIENT_DBCOUNT_t
uint8_t FXLS8962_ORIENT_DBCOUNT_t
Definition: fxls8962.h:1238
FXLS8962_BUF_CONFIG1_t::w
uint8_t w
Definition: fxls8962.h:1045
FXLS8962_SENS_CONFIG4_t::w
uint8_t w
Definition: fxls8962.h:635
FXLS8962_SDCD_INT_SRC2_t::_reserved_1
uint8_t _reserved_1
Definition: fxls8962.h:1454
FXLS8962_BUF_STATUS_t::buf_cnt
uint8_t buf_cnt
Definition: fxls8962.h:255
FXLS8962_SELF_TEST_CONFIG2_t::w
uint8_t w
Definition: fxls8962.h:1775
FXLS8962_INT_PIN_SEL_t::aslp_int2
uint8_t aslp_int2
Definition: fxls8962.h:917
FXLS8962_WHO_AM_I_t
uint8_t FXLS8962_WHO_AM_I_t
Definition: fxls8962.h:368
FXLS8962_SENS_CONFIG5_t
Definition: fxls8962.h:713
FXLS8962_BUF_STATUS_t::buf_wmrk
uint8_t buf_wmrk
Definition: fxls8962.h:259
FXLS8962_INT_EN_t::aslp_en
uint8_t aslp_en
Definition: fxls8962.h:834
FXLS8962_SLEEP_IDLE_LSB_t
uint8_t FXLS8962_SLEEP_IDLE_LSB_t
Definition: fxls8962.h:794
FXLS8962_ORIENT_BF_ZCOMP_t::orient_zlock
uint8_t orient_zlock
Definition: fxls8962.h:1250
FXLS8962_ORIENT_CONFIG_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:1201
FXLS8962_ORIENT_STATUS_t::_reserved_
uint8_t _reserved_
Definition: fxls8962.h:1149
FXLS8962_SENS_CONFIG1_t::spi_m
uint8_t spi_m
Definition: fxls8962.h:427
FXLS8962_SENS_CONFIG2_t::w
uint8_t w
Definition: fxls8962.h:510
FXLS8962_SENS_CONFIG5_t::x_dis
uint8_t x_dis
Definition: fxls8962.h:723
FXLS8962_OUT_Z_MSB_t
uint8_t FXLS8962_OUT_Z_MSB_t
Definition: fxls8962.h:245
FXLS8962_INT_PIN_SEL_t::sdcd_wt_int2
uint8_t sdcd_wt_int2
Definition: fxls8962.h:921
FXLS8962_SDCD_CONFIG1_t::ot_ele
uint8_t ot_ele
Definition: fxls8962.h:1525
FXLS8962_PROD_REV_t::prod_rev_maj
uint8_t prod_rev_maj
Definition: fxls8962.h:346
FXLS8962_BUF_CONFIG2_t::w
uint8_t w
Definition: fxls8962.h:1107
FXLS8962_INT_PIN_SEL_t::orient_int2
uint8_t orient_int2
Definition: fxls8962.h:919
FXLS8962_SDCD_INT_SRC2_t::wt_ea
uint8_t wt_ea
Definition: fxls8962.h:1461
FXLS8962_SELF_TEST_CONFIG1_t::w
uint8_t w
Definition: fxls8962.h:1752
FXLS8962_BUF_CONFIG2_t::buf_flush
uint8_t buf_flush
Definition: fxls8962.h:1104
FXLS8962_BUF_CONFIG1_t::buf_mode
uint8_t buf_mode
Definition: fxls8962.h:1040
FXLS8962_ORIENT_CONFIG_t::w
uint8_t w
Definition: fxls8962.h:1207
FXLS8962_ORIENT_STATUS_t::lapo
uint8_t lapo
Definition: fxls8962.h:1147
FXLS8962_INT_STATUS_t::src_ovf
uint8_t src_ovf
Definition: fxls8962.h:138
FXLS8962_SDCD_INT_SRC1_t::y_ot_pol
uint8_t y_ot_pol
Definition: fxls8962.h:1383
FXLS8962_SLEEP_IDLE_MSB_t
uint8_t FXLS8962_SLEEP_IDLE_MSB_t
Definition: fxls8962.h:802
FXLS8962_PROD_REV_t::prod_rev_min
uint8_t prod_rev_min
Definition: fxls8962.h:343
FXLS8962_ASLP_COUNT_MSB_t
uint8_t FXLS8962_ASLP_COUNT_MSB_t
Definition: fxls8962.h:818
FXLS8962_ORIENT_THS_REG_t::w
uint8_t w
Definition: fxls8962.h:1312
FXLS8962_INT_STATUS_t::src_sdcd_ot
uint8_t src_sdcd_ot
Definition: fxls8962.h:134
FXLS8962_SDCD_CONFIG2_t::sdcd_en
uint8_t sdcd_en
Definition: fxls8962.h:1617
FXLS8962_SDCD_LTHS_MSB_t
uint8_t FXLS8962_SDCD_LTHS_MSB_t
Definition: fxls8962.h:1720
FXLS8962_SENS_CONFIG4_t::int_pp_od
uint8_t int_pp_od
Definition: fxls8962.h:620
FXLS8962_SDCD_CONFIG1_t::x_wt_en
uint8_t x_wt_en
Definition: fxls8962.h:1515
FXLS8962_INT_EN_t::w
uint8_t w
Definition: fxls8962.h:846
FXLS8962_SDCD_CONFIG1_t::y_wt_en
uint8_t y_wt_en
Definition: fxls8962.h:1513
FXLS8962_SDCD_LTHS_LSB_t
uint8_t FXLS8962_SDCD_LTHS_LSB_t
Definition: fxls8962.h:1712
FXLS8962_SDCD_CONFIG2_t::w
uint8_t w
Definition: fxls8962.h:1620
FXLS8962_SDCD_CONFIG2_t::ref_upd
uint8_t ref_upd
Definition: fxls8962.h:1605
FXLS8962_BUF_CONFIG1_t::trg_orient
uint8_t trg_orient
Definition: fxls8962.h:1031
FXLS8962_SDCD_INT_SRC1_t::ot_ea
uint8_t ot_ea
Definition: fxls8962.h:1392
FXLS8962_SENS_CONFIG1_t::active
uint8_t active
Definition: fxls8962.h:423
FXLS8962_SENS_CONFIG4_t::drdy_pul
uint8_t drdy_pul
Definition: fxls8962.h:624
FXLS8962_SDCD_CONFIG2_t::wt_log_sel
uint8_t wt_log_sel
Definition: fxls8962.h:1609
FXLS8962_SENS_CONFIG2_t::wake_pm
uint8_t wake_pm
Definition: fxls8962.h:507
FXLS8962_SDCD_INT_SRC1_t::x_ot_pol
uint8_t x_ot_pol
Definition: fxls8962.h:1387
FXLS8962_BUF_Y_LSB_t
uint8_t FXLS8962_BUF_Y_LSB_t
Definition: fxls8962.h:304
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