ISSDK  1.7
IoT Sensing Software Development Kit
fxos8700.h
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1 /*
2  * The Clear BSD License
3  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
4  * Copyright 2016-2017 NXP
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34 
35 /**
36  * @file fxos8700.h
37  * @brief The fxos8700.h file contains the register definitions for FXOS8700 sensor driver.
38  */
39 
40 #ifndef FXOS8700_H_
41 #define FXOS8700_H_
42 /**
43  * @brief FXOS8700 internal register addresses explained in the FXOS8700 data sheet.
44  */
45 enum {
46  FXOS8700_STATUS = 0x00, /*!< Alias for ::FXOS8700_DR_STATUS or ::FXOS8700_F_STATUS. */
47  FXOS8700_OUT_X_MSB = 0x01, /*!< 14-bit X-axis measurement data bits 13:6. */
48  FXOS8700_OUT_X_LSB = 0x02, /*!< 14-bit X-axis measurement data bits 5:0. */
49  FXOS8700_OUT_Y_MSB = 0x03, /*!< 14-bit Y-axis measurement data bits 13:6. */
50  FXOS8700_OUT_Y_LSB = 0x04, /*!< 14-bit Y-axis measurement data bits 5:0. */
51  FXOS8700_OUT_Z_MSB = 0x05, /*!< 14-bit Z-axis measurement data bits 13:6. */
52  FXOS8700_OUT_Z_LSB = 0x06, /*!< 14-bit Z-axis measurement data bits 5:0. */
53  FXOS8700_F_SETUP = 0x09, /*!< FIFO setup. */
54  FXOS8700_TRIG_CFG = 0x0A, /*!< FIFO event trigger configuration register. */
55  FXOS8700_SYSMOD = 0x0B, /*!< Current system mode. */
56  FXOS8700_INT_SOURCE = 0x0C, /*!< Interrupt status. */
57  FXOS8700_WHO_AM_I = 0x0D, /*!< Device ID. */
58  FXOS8700_XYZ_DATA_CFG = 0x0E, /*!< Acceleration dynamic range and filter enable settings. */
59  FXOS8700_HP_FILTER_CUTOFF = 0x0F, /*!< Pulse detection highpass and lowpass filter enabling bits. */
60  FXOS8700_PL_STATUS = 0x10, /*!< Landscape/portrait orientation status. */
61  FXOS8700_PL_CFG = 0x11, /*!< Landscape/portrait configuration. */
62  FXOS8700_PL_COUNT = 0x12, /*!< Landscape/portrait debounce counter. */
63  FXOS8700_PL_BF_ZCOMP = 0x13, /*!< Back/front trip angle threshold. */
64  FXOS8700_PL_THS_REG = 0x14, /*!< Portrait to landscape trip threshold angle and hysteresis settings. */
65  FXOS8700_A_FFMT_CFG = 0x15, /*!< Freefall/motion function configuration. */
66  FXOS8700_A_FFMT_SRC = 0x16, /*!< Freefall/motion event source register. */
67  FXOS8700_A_FFMT_THS = 0x17, /*!< Freefall/motion threshold register. */
68  FXOS8700_A_FFMT_COUNT = 0x18, /*!< Freefall/motion debounce counter. */
69  FXOS8700_TRANSIENT_CFG = 0x1D, /*!< Transient function configuration. */
70  FXOS8700_TRANSIENT_SRC = 0x1E, /*!< Transient event status register. */
71  FXOS8700_TRANSIENT_THS = 0x1F, /*!< Transient event threshold. */
72  FXOS8700_TRANSIENT_COUNT = 0x20, /*!< Transient debounce counter. */
73  FXOS8700_PULSE_CFG = 0x21, /*!< Pulse function configuration. */
74  FXOS8700_PULSE_SRC = 0x22, /*!< Pulse function source register. */
75  FXOS8700_PULSE_THSX = 0x23, /*!< X-axis pulse threshold. */
76  FXOS8700_PULSE_THSY = 0x24, /*!< Y-axis pulse threshold. */
77  FXOS8700_PULSE_THSZ = 0x25, /*!< Z-axis pulse threshold. */
78  FXOS8700_PULSE_TMLT = 0x26, /*!< Time limit for pulse detection. */
79  FXOS8700_PULSE_LTCY = 0x27, /*!< Latency time for second pulse detection. */
80  FXOS8700_PULSE_WIND = 0x28, /*!< Window time for second pulse detection. */
81  FXOS8700_ASLP_COUNT = 0x29, /*!< The counter setting for auto-sleep period. */
82  FXOS8700_CTRL_REG1 = 0x2A, /*!< System ODR, accelerometer OSR (Output sample rate), operating mode. */
83  FXOS8700_CTRL_REG2 = 0x2B, /*!< Self-test, reset, accelerometer OSR, and sleep mode settings. */
84  FXOS8700_CTRL_REG3 = 0x2C, /*!< Sleep mode interrupt wake enable, interrupt polarity, push-pull/open drain configuration. */
85  FXOS8700_CTRL_REG4 = 0x2D, /*!< Interrupt enable register. */
86  FXOS8700_CTRL_REG5 = 0x2E, /*!< Interrupt pin (INT1/INT2) map. */
87  FXOS8700_OFF_X = 0x2F, /*!< X-axis accelerometer offset adjust. */
88  FXOS8700_OFF_Y = 0x30, /*!< Y-axis accelerometer offset adjust. */
89  FXOS8700_OFF_Z = 0x31, /*!< Z-axis accelerometer offset adjust. */
90  FXOS8700_M_DR_STATUS = 0x32, /*!< The magnetometer data ready status. */
91  FXOS8700_M_OUT_X_MSB = 0x33, /*!< MSB of the 16-bit magnetometer data for X-axis. */
92  FXOS8700_M_OUT_X_LSB = 0x34, /*!< LSB of the 16-bit magnetometer data for X-axis. */
93  FXOS8700_M_OUT_Y_MSB = 0x35, /*!< MSB of the 16-bit magnetometer data for Y-axis. */
94  FXOS8700_M_OUT_Y_LSB = 0x36, /*!< LSB of the 16-bit magnetometer data for Y-axis. */
95  FXOS8700_M_OUT_Z_MSB = 0x37, /*!< MSB of the 16-bit magnetometer data for Z-axis. */
96  FXOS8700_M_OUT_Z_LSB = 0x38, /*!< LSB of the 16-bit magnetometer data for Z-axis. */
97  FXOS8700_CMP_X_MSB = 0x39, /*!< Bits [13:8] of integrated X-axis acceleration data. */
98  FXOS8700_CMP_X_LSB = 0x3A, /*!< Bits [7:0] of integrated X-axis acceleration data. */
99  FXOS8700_CMP_Y_MSB = 0x3B, /*!< Bits [13:8] of integrated Y-axis acceleration data. */
100  FXOS8700_CMP_Y_LSB = 0x3C, /*!< Bits [7:0] of integrated Y-axis acceleration data. */
101  FXOS8700_CMP_Z_MSB = 0x3D, /*!< Bits [13:8] of integrated Z-axis acceleration data. */
102  FXOS8700_CMP_Z_LSB = 0x3E, /*!< Bits [7:0] of integrated Z-axis acceleration data. */
103  FXOS8700_M_OFF_X_MSB = 0x3F, /*!< MSB of magnetometer X-axis offset. */
104  FXOS8700_M_OFF_X_LSB = 0x40, /*!< LSB of magnetometer X-axis offset. */
105  FXOS8700_M_OFF_Y_MSB = 0x41, /*!< MSB of magnetometer Y-axis offset. */
106  FXOS8700_M_OFF_Y_LSB = 0x42, /*!< LSB of magnetometer Y-axis offset. */
107  FXOS8700_M_OFF_Z_MSB = 0x43, /*!< MSB of magnetometer Z-axis offset. */
108  FXOS8700_M_OFF_Z_LSB = 0x44, /*!< LSB of magnetometer Z-axis offset. */
109  FXOS8700_MAX_X_MSB = 0x45, /*!< Magnetometer X-axis maximum value MSB. */
110  FXOS8700_MAX_X_LSB = 0x46, /*!< Magnetometer X-axis maximum value LSB. */
111  FXOS8700_MAX_Y_MSB = 0x47, /*!< Magnetometer Y-axis maximum value MSB. */
112  FXOS8700_MAX_Y_LSB = 0x48, /*!< Magnetometer Y-axis maximum value LSB. */
113  FXOS8700_MAX_Z_MSB = 0x49, /*!< Magnetometer Z-axis maximum value MSB. */
114  FXOS8700_MAX_Z_LSB = 0x4A, /*!< Magnetometer Z-axis maximum value LSB. */
115  FXOS8700_MIN_X_MSB = 0x4B, /*!< Magnetometer X-axis minimum value MSB. */
116  FXOS8700_MIN_X_LSB = 0x4C, /*!< Magnetometer X-axis minimum value LSB. */
117  FXOS8700_MIN_Y_MSB = 0x4D, /*!< Magnetometer Y-axis minimum value MSB. */
118  FXOS8700_MIN_Y_LSB = 0x4E, /*!< Magnetometer Y-axis minimum value LSB. */
119  FXOS8700_MIN_Z_MSB = 0x4F, /*!< Magnetometer Z-axis minimum value MSB. */
120  FXOS8700_MIN_Z_LSB = 0x50, /*!< Magnetometer Z-axis minimum value LSB. */
121  FXOS8700_TEMP = 0x51, /*!< Device temperature with a valid range of -128 to 127 degrees C. */
122  FXOS8700_M_THS_CFG = 0x52, /*!< Magnetic threshold detection function configuration. */
123  FXOS8700_M_THS_SRC = 0x53, /*!< Magnetic threshold event source register. */
124  FXOS8700_M_THS_X_MSB = 0x54, /*!< X-axis magnetic threshold MSB. */
125  FXOS8700_M_THS_X_LSB = 0x55, /*!< X-axis magnetic threshold LSB. */
126  FXOS8700_M_THS_Y_MSB = 0x56, /*!< Y-axis magnetic threshold MSB. */
127  FXOS8700_M_THS_Y_LSB = 0x57, /*!< Y-axis magnetic threshold LSB. */
128  FXOS8700_M_THS_Z_MSB = 0x58, /*!< Z-axis magnetic threshold MSB. */
129  FXOS8700_M_THS_Z_LSB = 0x59, /*!< Z-axis magnetic threshold LSB. */
130  FXOS8700_M_THS_COUNT = 0x5A, /*!< Magnetic threshold debounce counter. */
131  FXOS8700_M_CTRL_REG1 = 0x5B, /*!< Control for magnetometer sensor functions. */
132  FXOS8700_M_CTRL_REG2 = 0x5C, /*!< Control for magnetometer sensor functions. */
133  FXOS8700_M_CTRL_REG3 = 0x5D, /*!< Control for magnetometer sensor functions. */
134  FXOS8700_M_INT_SRC = 0x5E, /*!< Magnetometer interrupt source. */
135  FXOS8700_A_VECM_CFG = 0x5F, /*!< Acceleration vector magnitude configuration register. */
136  FXOS8700_A_VECM_THS_MSB = 0x60, /*!< Acceleration vector magnitude threshold MSB. */
137  FXOS8700_A_VECM_THS_LSB = 0x61, /*!< Acceleration vector magnitude threshold LSB. */
138  FXOS8700_A_VECM_CNT = 0x62, /*!< Acceleration vector magnitude debounce count. */
139  FXOS8700_A_VECM_INITX_MSB = 0x63, /*!< Acceleration vector magnitude X-axis reference value MSB. */
140  FXOS8700_A_VECM_INITX_LSB = 0x64, /*!< Acceleration vector magnitude X-axis reference value LSB. */
141  FXOS8700_A_VECM_INITY_MSB = 0x65, /*!< Acceleration vector magnitude Y-axis reference value MSB. */
142  FXOS8700_A_VECM_INITY_LSB = 0x66, /*!< Acceleration vector magnitude Y-axis reference value LSB. */
143  FXOS8700_A_VECM_INITZ_MSB = 0x67, /*!< Acceleration vector magnitude Z-axis reference value MSB. */
144  FXOS8700_A_VECM_INITZ_LSB = 0x68, /*!< Acceleration vector magnitude Z-axis reference value LSB. */
145  FXOS8700_M_VECM_CFG = 0x69, /*!< Magnetic vector magnitude configuration register. */
146  FXOS8700_M_VECM_THS_MSB = 0x6A, /*!< Magnetic vector magnitude threshold MSB. */
147  FXOS8700_M_VECM_THS_LSB = 0x6B, /*!< Magnetic vector magnitude threshold LSB. */
148  FXOS8700_M_VECM_CNT = 0x6C, /*!< Magnetic vector magnitude debounce count. */
149  FXOS8700_M_VECM_INITX_MSB = 0x6D, /*!< Magnetic vector magnitude X-axis reference value MSB. */
150  FXOS8700_M_VECM_INITX_LSB = 0x6E, /*!< Magnetic vector magnitude X-axis reference value LSB. */
151  FXOS8700_M_VECM_INITY_MSB = 0x6F, /*!< Magnetic vector magnitude Y-axis reference value MSB. */
152  FXOS8700_M_VECM_INITY_LSB = 0x70, /*!< Magnetic vector magnitude Y-axis reference value LSB. */
153  FXOS8700_M_VECM_INITZ_MSB = 0x71, /*!< Magnetic vector magnitude Z-axis reference value MSB. */
154  FXOS8700_M_VECM_INITZ_LSB = 0x72, /*!< Magnetic vector magnitude Z-axis reference value LSB. */
155  FXOS8700_A_FFMT_THS_X_MSB = 0x73, /*!< X-axis FFMT threshold MSB. */
156  FXOS8700_A_FFMT_THS_X_LSB = 0x74, /*!< X-axis FFMT threshold LSB. */
157  FXOS8700_A_FFMT_THS_Y_MSB = 0x75, /*!< Y-axis FFMT threshold MSB. */
158  FXOS8700_A_FFMT_THS_Y_LSB = 0x76, /*!< Y-axis FFMT threshold LSB. */
159  FXOS8700_A_FFMT_THS_Z_MSB = 0x77, /*!< Z-axis FFMT threshold MSB. */
160  FXOS8700_A_FFMT_THS_Z_LSB = 0x78, /*!< Z-axis FFMT threshold LSB. */
161 };
162 
163 #define FXOS8700_DEVICE_ADDR_SA_00 (0x1E)
164 
165 #define FXOS8700_DEVICE_ADDR_SA_01 (0x1D)
166 
167 #define FXOS8700_DEVICE_ADDR_SA_10 (0x1C)
168 
169 #define FXOS8700_DEVICE_ADDR_SA_11 (0x1F)
170 
171 
172 #define FXOS8700_WHO_AM_I_PROD_VALUE (0xC7)
173 
174 
175 /**
176  * The following are the macro definitions to address each bit and its value in the hardware registers.
177  */
178 
179 /*--------------------------------
180 ** Register: DR_STATUS
181 ** Enum: FXOS8700_DR_STATUS
182 ** --
183 ** Offset : 0x00 - Alias for ::FXOS8700_DR_STATUS or ::FXOS8700_F_STATUS.
184 ** ------------------------------*/
185 typedef union {
186  struct {
187  uint8_t xdr : 1;
188  uint8_t ydr : 1;
189  uint8_t zdr : 1;
190  uint8_t zyxdr : 1;
191  uint8_t xow : 1;
192  uint8_t yow : 1;
193  uint8_t zow : 1;
194  uint8_t zyxow : 1;
195  } b;
196  uint8_t w;
197 } FXOS8700_DR_STATUS_t;
198 
199 
200 /*
201 ** DR_STATUS - Bit field mask definitions
202 */
203 #define FXOS8700_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
204 #define FXOS8700_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
205 
206 #define FXOS8700_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
207 #define FXOS8700_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
208 
209 #define FXOS8700_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
210 #define FXOS8700_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
211 
212 #define FXOS8700_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
213 #define FXOS8700_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
214 
215 #define FXOS8700_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
216 #define FXOS8700_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
217 
218 #define FXOS8700_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
219 #define FXOS8700_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
220 
221 #define FXOS8700_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
222 #define FXOS8700_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
223 
224 #define FXOS8700_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
225 #define FXOS8700_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
226 
227 
228 /*
229 ** DR_STATUS - Bit field value definitions
230 */
231 #define FXOS8700_DR_STATUS_XDR_DRDY ((uint8_t) 0x01) /* xdr is set to 1 whenever a new X-axis data */
232  /* acquisition is completed. xdr is cleared anytime */
233  /* the OUT_X_MSB register is read. */
234 #define FXOS8700_DR_STATUS_YDR_DRDY ((uint8_t) 0x02) /* ydr is set to 1 whenever a new Y-axis data */
235  /* acquisition is completed. xdr is cleared anytime */
236  /* the OUT_Y_MSB register is read. */
237 #define FXOS8700_DR_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* zdr is set to 1 whenever a new Z-axis data */
238  /* acquisition is completed. xdr is cleared anytime */
239  /* the OUT_Z_MSB register is read. */
240 #define FXOS8700_DR_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* zyxdr signals that a new acquisition for any of */
241  /* the enabled channels is available. zyxdr is */
242  /* cleared when the high-bytes of the acceleration */
243  /* data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. */
244 #define FXOS8700_DR_STATUS_XOW_OWR ((uint8_t) 0x10)
245 #define FXOS8700_DR_STATUS_YOW_OWR ((uint8_t) 0x20)
246 #define FXOS8700_DR_STATUS_ZOW_OWR ((uint8_t) 0x40)
247 #define FXOS8700_DR_STATUS_ZYXOW_OWR ((uint8_t) 0x80)
248 /*------------------------------*/
249 
250 
251 
252 /*--------------------------------
253 ** Register: F_STATUS
254 ** Enum: FXOS8700_F_STATUS
255 ** --
256 ** Offset : 0x00 - Fifo Status register
257 ** ------------------------------*/
258 typedef union {
259  struct {
260  uint8_t f_cnt : 6; /* These bits indicate the number of acceleration samples currently stored in */
261  /* the FIFO buffer. Count 0b00_0000 indicates that the FIFO is empty */
262 
263  uint8_t f_wmrk_flag : 1;
264  uint8_t f_ovf : 1;
265  } b;
266  uint8_t w;
267 } FXOS8700_F_STATUS_t;
268 
269 
270 /*
271 ** F_STATUS - Bit field mask definitions
272 */
273 #define FXOS8700_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
274 #define FXOS8700_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
275 
276 #define FXOS8700_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
277 #define FXOS8700_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
278 
279 #define FXOS8700_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
280 #define FXOS8700_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
281 
282 
283 /*
284 ** F_STATUS - Bit field value definitions
285 */
286 #define FXOS8700_F_STATUS_F_WMRK_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected */
287 #define FXOS8700_F_STATUS_F_WMRK_FLAG_EVTDET ((uint8_t) 0x40)
288 #define FXOS8700_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected */
289 #define FXOS8700_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO overflow event detected */
290 /*------------------------------*/
291 
292 
293 
294 /*--------------------------------
295 ** Register: OUT_X_MSB
296 ** Enum: FXOS8700_OUT_X_MSB
297 ** --
298 ** Offset : 0x01 - MSB of Accelerometer X value
299 ** ------------------------------*/
300 typedef union {
301  struct {
302  uint8_t xd; /* - 14-bit X-axis measurement data bits 13:6. */
303 
304  } b;
305  uint8_t w;
306 } FXOS8700_OUT_X_MSB_t;
307 
308 
309 /*
310 ** OUT_X_MSB - Bit field mask definitions
311 */
312 #define FXOS8700_OUT_X_MSB_XD_MASK ((uint8_t) 0xFF)
313 #define FXOS8700_OUT_X_MSB_XD_SHIFT ((uint8_t) 0)
314 
315 
316 /*------------------------------*/
317 
318 
319 
320 /*--------------------------------
321 ** Register: OUT_X_LSB
322 ** Enum: FXOS8700_OUT_X_LSB
323 ** --
324 ** Offset : 0x02 - LSB of Accelerometer X value
325 ** ------------------------------*/
326 typedef union {
327  struct {
328  uint8_t _reserved_ : 2;
329  uint8_t xd : 6; /* - 14-bit X-axis measurement data bits 5:0. */
330 
331  } b;
332  uint8_t w;
333 } FXOS8700_OUT_X_LSB_t;
334 
335 
336 /*
337 ** OUT_X_LSB - Bit field mask definitions
338 */
339 #define FXOS8700_OUT_X_LSB_XD_MASK ((uint8_t) 0xFC)
340 #define FXOS8700_OUT_X_LSB_XD_SHIFT ((uint8_t) 2)
341 
342 
343 /*------------------------------*/
344 
345 
346 
347 /*--------------------------------
348 ** Register: OUT_Y_MSB
349 ** Enum: FXOS8700_OUT_Y_MSB
350 ** --
351 ** Offset : 0x03 - 14-bit Y-axis measurement data bits 13:6.
352 ** ------------------------------*/
353 typedef union {
354  struct {
355  uint8_t yd; /* - 14-bit Y-axis measurement data bits 13:6. */
356 
357  } b;
358  uint8_t w;
359 } FXOS8700_OUT_Y_MSB_t;
360 
361 
362 /*
363 ** OUT_Y_MSB - Bit field mask definitions
364 */
365 #define FXOS8700_OUT_Y_MSB_YD_MASK ((uint8_t) 0xFF)
366 #define FXOS8700_OUT_Y_MSB_YD_SHIFT ((uint8_t) 0)
367 
368 
369 /*------------------------------*/
370 
371 
372 
373 /*--------------------------------
374 ** Register: OUT_Y_LSB
375 ** Enum: FXOS8700_OUT_Y_LSB
376 ** --
377 ** Offset : 0x04 - 14-bit Y-axis measurement data bits 5:0.
378 ** ------------------------------*/
379 typedef union {
380  struct {
381  uint8_t _reserved_ : 2;
382  uint8_t yd : 6; /* - 14-bit Y-axis measurement data bits 5:0. */
383 
384  } b;
385  uint8_t w;
386 } FXOS8700_OUT_Y_LSB_t;
387 
388 
389 /*
390 ** OUT_Y_LSB - Bit field mask definitions
391 */
392 #define FXOS8700_OUT_Y_LSB_YD_MASK ((uint8_t) 0xFC)
393 #define FXOS8700_OUT_Y_LSB_YD_SHIFT ((uint8_t) 2)
394 
395 
396 /*------------------------------*/
397 
398 
399 
400 /*--------------------------------
401 ** Register: OUT_Z_MSB
402 ** Enum: FXOS8700_OUT_Z_MSB
403 ** --
404 ** Offset : 0x05 - 14-bit Z-axis measurement data bits 13:6.
405 ** ------------------------------*/
406 typedef union {
407  struct {
408  uint8_t zd; /* - 14-bit Z-axis measurement data bits 13:6. */
409 
410  } b;
411  uint8_t w;
412 } FXOS8700_OUT_Z_MSB_t;
413 
414 
415 /*
416 ** OUT_Z_MSB - Bit field mask definitions
417 */
418 #define FXOS8700_OUT_Z_MSB_ZD_MASK ((uint8_t) 0xFF)
419 #define FXOS8700_OUT_Z_MSB_ZD_SHIFT ((uint8_t) 0)
420 
421 
422 /*------------------------------*/
423 
424 
425 
426 /*--------------------------------
427 ** Register: OUT_Z_LSB
428 ** Enum: FXOS8700_OUT_Z_LSB
429 ** --
430 ** Offset : 0x06 - 14-bit Z-axis measurement data bits 5:0.
431 ** ------------------------------*/
432 typedef union {
433  struct {
434  uint8_t _reserved_ : 2;
435  uint8_t zd : 6; /* - 14-bit Z-axis measurement data bits 5:0. */
436 
437  } b;
438  uint8_t w;
439 } FXOS8700_OUT_Z_LSB_t;
440 
441 
442 /*
443 ** OUT_Z_LSB - Bit field mask definitions
444 */
445 #define FXOS8700_OUT_Z_LSB_ZD_MASK ((uint8_t) 0xFC)
446 #define FXOS8700_OUT_Z_LSB_ZD_SHIFT ((uint8_t) 2)
447 
448 
449 /*------------------------------*/
450 
451 
452 
453 /*--------------------------------
454 ** Register: F_SETUP
455 ** Enum: FXOS8700_F_SETUP
456 ** --
457 ** Offset : 0x09 - FIFO setup.
458 ** ------------------------------*/
459 typedef union {
460  struct {
461  uint8_t f_wmrk : 6; /* FIFO sample count watermark */
462 
463  uint8_t f_mode : 2; /* - FIFO Buffer operating mode */
464 
465  } b;
466  uint8_t w;
467 } FXOS8700_F_SETUP_t;
468 
469 
470 /*
471 ** F_SETUP - Bit field mask definitions
472 */
473 #define FXOS8700_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
474 #define FXOS8700_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
475 
476 #define FXOS8700_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
477 #define FXOS8700_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
478 
479 
480 /*
481 ** F_SETUP - Bit field value definitions
482 */
483 #define FXOS8700_F_SETUP_F_MODE_FIFO_DISABLE ((uint8_t) 0x00) /* FIFO is disabled */
484 #define FXOS8700_F_SETUP_F_MODE_FIFO_CIRC ((uint8_t) 0x40) /* FIFO contains the most recent samples when */
485  /* overflowed (circular buffer). Oldest sample is */
486  /* discarded to be replaced by new sample */
487 #define FXOS8700_F_SETUP_F_MODE_FIFO_STOP_OVF ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed */
488 #define FXOS8700_F_SETUP_F_MODE_FIFO_TRIGGER ((uint8_t) 0xc0) /* FIFO trigger mode */
489 /*------------------------------*/
490 
491 
492 
493 /*--------------------------------
494 ** Register: TRIG_CFG
495 ** Enum: FXOS8700_TRIG_CFG
496 ** --
497 ** Offset : 0x0A - FIFO event trigger configuration register.
498 ** ------------------------------*/
499 typedef union {
500  struct {
501  uint8_t _reserved_ : 1;
502  uint8_t trig_a_vecm : 1;
503  uint8_t trig_a_ffmt : 1;
504  uint8_t trig_pulse : 1;
505  uint8_t trig_lndprt : 1;
506  uint8_t trig_trans : 1;
507  } b;
508  uint8_t w;
509 } FXOS8700_TRIG_CFG_t;
510 
511 
512 /*
513 ** TRIG_CFG - Bit field mask definitions
514 */
515 #define FXOS8700_TRIG_CFG_TRIG_A_VECM_MASK ((uint8_t) 0x02)
516 #define FXOS8700_TRIG_CFG_TRIG_A_VECM_SHIFT ((uint8_t) 1)
517 
518 #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_MASK ((uint8_t) 0x04)
519 #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_SHIFT ((uint8_t) 2)
520 
521 #define FXOS8700_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
522 #define FXOS8700_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
523 
524 #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
525 #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
526 
527 #define FXOS8700_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
528 #define FXOS8700_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
529 
530 
531 /*
532 ** TRIG_CFG - Bit field value definitions
533 */
534 #define FXOS8700_TRIG_CFG_TRIG_A_VECM_EN ((uint8_t) 0x02) /* Acceleration vector-magnitude FIFO trigger enable */
535 #define FXOS8700_TRIG_CFG_TRIG_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude FIFO trigger disable */
536 #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_EN ((uint8_t) 0x04) /* Freefall/motion interrupt FIFO trigger enable */
537 #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion interrupt FIFO trigger disable */
538 #define FXOS8700_TRIG_CFG_TRIG_PULSE_EN ((uint8_t) 0x08) /* Pluse interrupt FIFO trigger enable */
539 #define FXOS8700_TRIG_CFG_TRIG_PULSE_DIS ((uint8_t) 0x00) /* Pluse FIFO trigger enable */
540 #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_EN ((uint8_t) 0x10) /* Landscape/portrait orientation interrupt FIFO */
541  /* trigger enable */
542 #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_DIS ((uint8_t) 0x00) /* Landscape/portrait orientation interrupt FIFO */
543  /* trigger disable */
544 #define FXOS8700_TRIG_CFG_TRIG_TRANS_EN ((uint8_t) 0x20) /* Transient interrupt FIFO trigger enable */
545 #define FXOS8700_TRIG_CFG_TRIG_TRANS_DIS ((uint8_t) 0x00) /* Transient interrupt FIFO trigger disable */
546 /*------------------------------*/
547 
548 
549 
550 /*--------------------------------
551 ** Register: SYSMOD
552 ** Enum: FXOS8700_SYSMOD
553 ** --
554 ** Offset : 0x0B - Current system mode.
555 ** ------------------------------*/
556 typedef union {
557  struct {
558  uint8_t sysmod : 2;
559  uint8_t fgt : 5;
560  uint8_t fgerr : 1;
561  } b;
562  uint8_t w;
563 } FXOS8700_SYSMOD_t;
564 
565 
566 /*
567 ** SYSMOD - Bit field mask definitions
568 */
569 #define FXOS8700_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
570 #define FXOS8700_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
571 
572 #define FXOS8700_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
573 #define FXOS8700_SYSMOD_FGT_SHIFT ((uint8_t) 2)
574 
575 #define FXOS8700_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
576 #define FXOS8700_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
577 
578 
579 /*
580 ** SYSMOD - Bit field value definitions
581 */
582 #define FXOS8700_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* Standby mode */
583 #define FXOS8700_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* Wake mode */
584 #define FXOS8700_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* Sleep mode */
585 /*------------------------------*/
586 
587 
588 
589 
590 /*--------------------------------
591 ** Register: INT_SOURCE
592 ** Enum: FXOS8700_INT_SOURCE
593 ** --
594 ** Offset : 0x0C - Interrupt status.
595 ** ------------------------------*/
596 typedef union {
597  struct {
598  uint8_t src_drdy : 1;
599  uint8_t src_a_vecm : 1;
600  uint8_t src_ffmt : 1;
601  uint8_t src_pulse : 1;
602  uint8_t src_lndprt : 1;
603  uint8_t src_trans : 1;
604  uint8_t src_fifo : 1;
605  uint8_t src_aslp : 1;
606  } b;
607  uint8_t w;
608 } FXOS8700_INT_SOURCE_t;
609 
610 
611 /*
612 ** INT_SOURCE - Bit field mask definitions
613 */
614 #define FXOS8700_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
615 #define FXOS8700_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
616 
617 #define FXOS8700_INT_SOURCE_SRC_A_VECM_MASK ((uint8_t) 0x02)
618 #define FXOS8700_INT_SOURCE_SRC_A_VECM_SHIFT ((uint8_t) 1)
619 
620 #define FXOS8700_INT_SOURCE_SRC_FFMT_MASK ((uint8_t) 0x04)
621 #define FXOS8700_INT_SOURCE_SRC_FFMT_SHIFT ((uint8_t) 2)
622 
623 #define FXOS8700_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
624 #define FXOS8700_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
625 
626 #define FXOS8700_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
627 #define FXOS8700_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
628 
629 #define FXOS8700_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
630 #define FXOS8700_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
631 
632 #define FXOS8700_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
633 #define FXOS8700_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
634 
635 #define FXOS8700_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
636 #define FXOS8700_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
637 
638 
639 /*------------------------------*/
640 
641 
642 
643 /*--------------------------------
644 ** Register: WHO_AM_I
645 ** Enum: FXOS8700_WHO_AM_I
646 ** --
647 ** Offset : 0x0D - Device ID.
648 ** ------------------------------*/
649 typedef uint8_t FXOS8700_WHO_AM_I_t;
650 
651 
652 
653 /*--------------------------------
654 ** Register: XYZ_DATA_CFG
655 ** Enum: FXOS8700_XYZ_DATA_CFG
656 ** --
657 ** Offset : 0x0E - Acceleration dynamic range and filter enable settings.
658 ** ------------------------------*/
659 typedef union {
660  struct {
661  uint8_t fs : 2;
662  uint8_t _reserved_ : 2;
663  uint8_t hpf_out : 1; /* - Enable high-pass filter on acceleration output data */
664 
665  } b;
666  uint8_t w;
667 } FXOS8700_XYZ_DATA_CFG_t;
668 
669 
670 /*
671 ** XYZ_DATA_CFG - Bit field mask definitions
672 */
673 #define FXOS8700_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
674 #define FXOS8700_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
675 
676 #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
677 #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
678 
679 
680 /*
681 ** XYZ_DATA_CFG - Bit field value definitions
682 */
683 #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_EN ((uint8_t) 0x10) /* Enable high-pass filter on acceleration output */
684  /* data */
685 #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_DISABLE ((uint8_t) 0x00) /* High-pass filter is disabled */
686 #define FXOS8700_XYZ_DATA_CFG_FS_2G_0P244 ((uint8_t) 0x00) /* 0.244 mg/LSB */
687 #define FXOS8700_XYZ_DATA_CFG_FS_4G_0P488 ((uint8_t) 0x01) /* 0.488 mg/LSB */
688 #define FXOS8700_XYZ_DATA_CFG_FS_8G_0P976 ((uint8_t) 0x02) /* 0.976 mg/LSB */
689 /*------------------------------*/
690 
691 
692 
693 /*--------------------------------
694 ** Register: HP_FILTER_CUTOFF
695 ** Enum: FXOS8700_HP_FILTER_CUTOFF
696 ** --
697 ** Offset : 0x0F - Pulse detection highpass and lowpass filter enabling bits.
698 ** ------------------------------*/
699 typedef union {
700  struct {
701  uint8_t sel : 2;
702  uint8_t _reserved_ : 2;
703  uint8_t pulse_lpf_en : 1;
704  uint8_t pulse_hpf_byp : 1;
705  } b;
706  uint8_t w;
707 } FXOS8700_HP_FILTER_CUTOFF_t;
708 
709 
710 /*
711 ** HP_FILTER_CUTOFF - Bit field mask definitions
712 */
713 #define FXOS8700_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
714 #define FXOS8700_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
715 
716 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
717 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
718 
719 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
720 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
721 
722 
723 /*
724 ** HP_FILTER_CUTOFF - Bit field value definitions
725 */
726 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_EN ((uint8_t) 0x00) /* HPF enabled for pulse processing */
727 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_BYPASS ((uint8_t) 0x20) /* HPF bypassed for pulse processing */
728 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_EN ((uint8_t) 0x10) /* LPF enabled for pulse processing */
729 #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLE ((uint8_t) 0x00) /* LPF bypassed for pulse processing */
730 #define FXOS8700_HP_FILTER_CUTOFF_SEL_EN ((uint8_t) 0x01) /* HPF cutoff frequency selection Enabled */
731 #define FXOS8700_HP_FILTER_CUTOFF_SEL_DISABLE ((uint8_t) 0x00) /* HPF cutoff frequency selection Disabled */
732 /*------------------------------*/
733 
734 
735 
736 /*--------------------------------
737 ** Register: PL_STATUS
738 ** Enum: FXOS8700_PL_STATUS
739 ** --
740 ** Offset : 0x10 - Landscape/portrait orientation status.
741 ** ------------------------------*/
742 typedef union {
743  struct {
744  uint8_t bafro : 1;
745  uint8_t lapo : 2;
746  uint8_t _reserved_ : 3;
747  uint8_t lo : 1;
748  uint8_t newlp : 1;
749  } b;
750  uint8_t w;
751 } FXOS8700_PL_STATUS_t;
752 
753 
754 /*
755 ** PL_STATUS - Bit field mask definitions
756 */
757 #define FXOS8700_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
758 #define FXOS8700_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
759 
760 #define FXOS8700_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
761 #define FXOS8700_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
762 
763 #define FXOS8700_PL_STATUS_LO_MASK ((uint8_t) 0x40)
764 #define FXOS8700_PL_STATUS_LO_SHIFT ((uint8_t) 6)
765 
766 #define FXOS8700_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
767 #define FXOS8700_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
768 
769 
770 /*------------------------------*/
771 
772 
773 
774 /*--------------------------------
775 ** Register: PL_CFG
776 ** Enum: FXOS8700_PL_CFG
777 ** --
778 ** Offset : 0x11 - Landscape/portrait configuration.
779 ** ------------------------------*/
780 typedef union {
781  struct {
782  uint8_t _reserved_ : 6;
783  uint8_t pl_en : 1;
784  uint8_t dbcntm : 1;
785  } b;
786  uint8_t w;
787 } FXOS8700_PL_CFG_t;
788 
789 
790 /*
791 ** PL_CFG - Bit field mask definitions
792 */
793 #define FXOS8700_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
794 #define FXOS8700_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
795 
796 #define FXOS8700_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
797 #define FXOS8700_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
798 
799 
800 /*
801 ** PL_CFG - Bit field value definitions
802 */
803 #define FXOS8700_PL_CFG_DBCNTM_DECREMENT_MODE ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */
804  /* no longer valid */
805 #define FXOS8700_PL_CFG_DBCNTM_CLEAR_MODE ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
806  /* longer valid */
807 #define FXOS8700_PL_CFG_PL_EN_DISABLE ((uint8_t) 0x00) /* Portrait/Landscape detection is disabled. */
808 #define FXOS8700_PL_CFG_PL_EN_ENABLE ((uint8_t) 0x40) /* Portrait/Landscape detection is enabled. */
809 /*------------------------------*/
810 
811 
812 
813 /*--------------------------------
814 ** Register: PL_COUNT
815 ** Enum: FXOS8700_PL_COUNT
816 ** --
817 ** Offset : 0x12 - Landscape/portrait debounce counter.
818 ** ------------------------------*/
819 typedef union {
820  struct {
821  uint8_t dbnce;
822  } b;
823  uint8_t w;
824 } FXOS8700_PL_COUNT_t;
825 
826 
827 /*
828 ** PL_COUNT - Bit field mask definitions
829 */
830 #define FXOS8700_PL_COUNT_DBNCE_MASK ((uint8_t) 0xFF)
831 #define FXOS8700_PL_COUNT_DBNCE_SHIFT ((uint8_t) 0)
832 
833 
834 /*------------------------------*/
835 
836 
837 
838 /*--------------------------------
839 ** Register: PL_BF_ZCOMP
840 ** Enum: FXOS8700_PL_BF_ZCOMP
841 ** --
842 ** Offset : 0x13 - Back/front trip angle threshold.
843 ** ------------------------------*/
844 typedef union {
845  struct {
846  uint8_t zlock : 3;
847  uint8_t _reserved_ : 3;
848  uint8_t bkfr : 2;
849  } b;
850  uint8_t w;
851 } FXOS8700_PL_BF_ZCOMP_t;
852 
853 
854 /*
855 ** PL_BF_ZCOMP - Bit field mask definitions
856 */
857 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
858 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
859 
860 #define FXOS8700_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
861 #define FXOS8700_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
862 
863 
864 /*
865 ** PL_BF_ZCOMP - Bit field value definitions
866 */
867 #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT80_GT280__FB_LT260_GT100 ((uint8_t) 0x00)
868 #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT75_GT285__FB_LT255_GT105 ((uint8_t) 0x40)
869 #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT70_GT290__FB_LT250_GT110 ((uint8_t) 0x80)
870 #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT65_GT295__FB_LT245_GT115 ((uint8_t) 0xc0)
871 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_13P6MIN_14P5MAX ((uint8_t) 0x00)
872 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_17P1MIN_18P2MAX ((uint8_t) 0x01)
873 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_20P7MIN_22P0MAX ((uint8_t) 0x02)
874 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_24P4MIN_25P9MAX ((uint8_t) 0x04)
875 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_28P1MIN_30P0MAX ((uint8_t) 0x04)
876 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_32P0MIN_34P2MAX ((uint8_t) 0x05)
877 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_36P1MIN_38P7MAX ((uint8_t) 0x06)
878 #define FXOS8700_PL_BF_ZCOMP_ZLOCK_40P4MIN_43P4MAX ((uint8_t) 0x07)
879 /*------------------------------*/
880 
881 
882 
883 /*--------------------------------
884 ** Register: PL_THS_REG
885 ** Enum: FXOS8700_PL_THS_REG
886 ** --
887 ** Offset : 0x14 - Portrait to landscape trip threshold angle and hysteresis settings.
888 ** ------------------------------*/
889 typedef union {
890  struct {
891  uint8_t hys : 3;
892  uint8_t pl_ths : 5;
893  } b;
894  uint8_t w;
895 } FXOS8700_PL_THS_REG_t;
896 
897 
898 /*
899 ** PL_THS_REG - Bit field mask definitions
900 */
901 #define FXOS8700_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
902 #define FXOS8700_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
903 
904 #define FXOS8700_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
905 #define FXOS8700_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
906 
907 
908 /*
909 ** PL_THS_REG - Bit field value definitions
910 */
911 #define FXOS8700_PL_THS_REG_PL_THS_15DEG ((uint8_t) 0x38)
912 #define FXOS8700_PL_THS_REG_PL_THS_20DEG ((uint8_t) 0x48)
913 #define FXOS8700_PL_THS_REG_PL_THS_30DEG ((uint8_t) 0x60)
914 #define FXOS8700_PL_THS_REG_PL_THS_35DEG ((uint8_t) 0x68)
915 #define FXOS8700_PL_THS_REG_PL_THS_40DEG ((uint8_t) 0x78)
916 #define FXOS8700_PL_THS_REG_PL_THS_45DEG ((uint8_t) 0x80)
917 #define FXOS8700_PL_THS_REG_PL_THS_55DEG ((uint8_t) 0x98)
918 #define FXOS8700_PL_THS_REG_PL_THS_60DEG ((uint8_t) 0xa0)
919 #define FXOS8700_PL_THS_REG_PL_THS_70DEG ((uint8_t) 0xb8)
920 #define FXOS8700_PL_THS_REG_PL_THS_75DEG ((uint8_t) 0xc8)
921 #define FXOS8700_PL_THS_REG_HYS_LP45_PL45 ((uint8_t) 0x00)
922 #define FXOS8700_PL_THS_REG_HYS_LP49_PL41 ((uint8_t) 0x01)
923 #define FXOS8700_PL_THS_REG_HYS_LP52_PL38 ((uint8_t) 0x02)
924 #define FXOS8700_PL_THS_REG_HYS_LP56_PL34 ((uint8_t) 0x03)
925 #define FXOS8700_PL_THS_REG_HYS_LP59_PL31 ((uint8_t) 0x04)
926 #define FXOS8700_PL_THS_REG_HYS_LP62_PL28 ((uint8_t) 0x05)
927 #define FXOS8700_PL_THS_REG_HYS_LP66_PL24 ((uint8_t) 0x06)
928 #define FXOS8700_PL_THS_REG_HYS_LP69_PL21 ((uint8_t) 0x07)
929 /*------------------------------*/
930 
931 
932 
933 /*--------------------------------
934 ** Register: A_FFMT_CFG
935 ** Enum: FXOS8700_A_FFMT_CFG
936 ** --
937 ** Offset : 0x15 - Freefall/motion function configuration.
938 ** ------------------------------*/
939 typedef union {
940  struct {
941  uint8_t _reserved_ : 3;
942  uint8_t xefe : 1;
943  uint8_t yefe : 1;
944  uint8_t zefe : 1;
945  uint8_t oae : 1;
946  uint8_t ele : 1;
947  } b;
948  uint8_t w;
949 } FXOS8700_A_FFMT_CFG_t;
950 
951 
952 /*
953 ** A_FFMT_CFG - Bit field mask definitions
954 */
955 #define FXOS8700_A_FFMT_CFG_XEFE_MASK ((uint8_t) 0x08)
956 #define FXOS8700_A_FFMT_CFG_XEFE_SHIFT ((uint8_t) 3)
957 
958 #define FXOS8700_A_FFMT_CFG_YEFE_MASK ((uint8_t) 0x10)
959 #define FXOS8700_A_FFMT_CFG_YEFE_SHIFT ((uint8_t) 4)
960 
961 #define FXOS8700_A_FFMT_CFG_ZEFE_MASK ((uint8_t) 0x20)
962 #define FXOS8700_A_FFMT_CFG_ZEFE_SHIFT ((uint8_t) 5)
963 
964 #define FXOS8700_A_FFMT_CFG_OAE_MASK ((uint8_t) 0x40)
965 #define FXOS8700_A_FFMT_CFG_OAE_SHIFT ((uint8_t) 6)
966 
967 #define FXOS8700_A_FFMT_CFG_ELE_MASK ((uint8_t) 0x80)
968 #define FXOS8700_A_FFMT_CFG_ELE_SHIFT ((uint8_t) 7)
969 
970 
971 /*
972 ** A_FFMT_CFG - Bit field value definitions
973 */
974 #define FXOS8700_A_FFMT_CFG_ELE_EN ((uint8_t) 0x80) /* Event flag latch enabled */
975 #define FXOS8700_A_FFMT_CFG_ELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
976 #define FXOS8700_A_FFMT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall flag */
977 #define FXOS8700_A_FFMT_CFG_OAE_MOTION ((uint8_t) 0x40) /* Motion flag */
978 #define FXOS8700_A_FFMT_CFG_ZEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
979 #define FXOS8700_A_FFMT_CFG_ZEFE_RAISE_EVENT ((uint8_t) 0x20) /* Raise event flag on measured Z-axis acceleration */
980  /* above/below threshold */
981 #define FXOS8700_A_FFMT_CFG_YEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
982 #define FXOS8700_A_FFMT_CFG_YEFE_RAISE_EVENT ((uint8_t) 0x10) /* Raise event flag on measured Y-axis acceleration */
983  /* above/below threshold */
984 #define FXOS8700_A_FFMT_CFG_XEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
985 #define FXOS8700_A_FFMT_CFG_XEFE_RAISE_EVENT ((uint8_t) 0x08) /* Raise event flag on measured X-axis acceleration */
986  /* above/below threshold */
987 /*------------------------------*/
988 
989 
990 
991 /*--------------------------------
992 ** Register: A_FFMT_SRC
993 ** Enum: FXOS8700_A_FFMT_SRC
994 ** --
995 ** Offset : 0x16 - Freefall/motion event source register.
996 ** ------------------------------*/
997 typedef union {
998  struct {
999  uint8_t xhp : 1;
1000  uint8_t xhe : 1;
1001  uint8_t yhp : 1;
1002  uint8_t yhe : 1;
1003  uint8_t zhp : 1;
1004  uint8_t zhe : 1;
1005  uint8_t _reserved_ : 1;
1006  uint8_t ea : 1;
1007  } b;
1008  uint8_t w;
1009 } FXOS8700_A_FFMT_SRC_t;
1010 
1011 
1012 /*
1013 ** A_FFMT_SRC - Bit field mask definitions
1014 */
1015 #define FXOS8700_A_FFMT_SRC_XHP_MASK ((uint8_t) 0x01)
1016 #define FXOS8700_A_FFMT_SRC_XHP_SHIFT ((uint8_t) 0)
1017 
1018 #define FXOS8700_A_FFMT_SRC_XHE_MASK ((uint8_t) 0x02)
1019 #define FXOS8700_A_FFMT_SRC_XHE_SHIFT ((uint8_t) 1)
1020 
1021 #define FXOS8700_A_FFMT_SRC_YHP_MASK ((uint8_t) 0x04)
1022 #define FXOS8700_A_FFMT_SRC_YHP_SHIFT ((uint8_t) 2)
1023 
1024 #define FXOS8700_A_FFMT_SRC_YHE_MASK ((uint8_t) 0x08)
1025 #define FXOS8700_A_FFMT_SRC_YHE_SHIFT ((uint8_t) 3)
1026 
1027 #define FXOS8700_A_FFMT_SRC_ZHP_MASK ((uint8_t) 0x10)
1028 #define FXOS8700_A_FFMT_SRC_ZHP_SHIFT ((uint8_t) 4)
1029 
1030 #define FXOS8700_A_FFMT_SRC_ZHE_MASK ((uint8_t) 0x20)
1031 #define FXOS8700_A_FFMT_SRC_ZHE_SHIFT ((uint8_t) 5)
1032 
1033 #define FXOS8700_A_FFMT_SRC_EA_MASK ((uint8_t) 0x80)
1034 #define FXOS8700_A_FFMT_SRC_EA_SHIFT ((uint8_t) 7)
1035 
1036 
1037 /*------------------------------*/
1038 
1039 
1040 
1041 /*--------------------------------
1042 ** Register: A_FFMT_THS
1043 ** Enum: FXOS8700_A_FFMT_THS
1044 ** --
1045 ** Offset : 0x17 - Freefall/motion threshold register.
1046 ** ------------------------------*/
1047 typedef union {
1048  struct {
1049  uint8_t ths : 7;
1050  uint8_t dbcntm : 1;
1051  } b;
1052  uint8_t w;
1053 } FXOS8700_A_FFMT_THS_t;
1054 
1055 
1056 /*
1057 ** A_FFMT_THS - Bit field mask definitions
1058 */
1059 #define FXOS8700_A_FFMT_THS_THS_MASK ((uint8_t) 0x7F)
1060 #define FXOS8700_A_FFMT_THS_THS_SHIFT ((uint8_t) 0)
1061 
1062 #define FXOS8700_A_FFMT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1063 #define FXOS8700_A_FFMT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1064 
1065 
1066 /*------------------------------*/
1067 
1068 
1069 
1070 /*--------------------------------
1071 ** Register: A_FFMT_COUNT
1072 ** Enum: FXOS8700_A_FFMT_COUNT
1073 ** --
1074 ** Offset : 0x18 - Freefall/motion debounce counter.
1075 ** ------------------------------*/
1076 typedef uint8_t FXOS8700_A_FFMT_COUNT_t;
1077 
1078 
1079 
1080 
1081 /*--------------------------------
1082 ** Register: TRANSIENT_CFG
1083 ** Enum: FXOS8700_TRANSIENT_CFG
1084 ** --
1085 ** Offset : 0x1D - Transient function configuration.
1086 ** ------------------------------*/
1087 typedef union {
1088  struct {
1089  uint8_t hpf_byp : 1;
1090  uint8_t xtefe : 1;
1091  uint8_t ytefe : 1;
1092  uint8_t ztefe : 1;
1093  uint8_t tele : 1;
1094  } b;
1095  uint8_t w;
1096 } FXOS8700_TRANSIENT_CFG_t;
1097 
1098 
1099 /*
1100 ** TRANSIENT_CFG - Bit field mask definitions
1101 */
1102 #define FXOS8700_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1103 #define FXOS8700_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1104 
1105 #define FXOS8700_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1106 #define FXOS8700_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1107 
1108 #define FXOS8700_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1109 #define FXOS8700_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1110 
1111 #define FXOS8700_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1112 #define FXOS8700_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1113 
1114 #define FXOS8700_TRANSIENT_CFG_TELE_MASK ((uint8_t) 0x10)
1115 #define FXOS8700_TRANSIENT_CFG_TELE_SHIFT ((uint8_t) 4)
1116 
1117 
1118 /*
1119 ** TRANSIENT_CFG - Bit field value definitions
1120 */
1121 #define FXOS8700_TRANSIENT_CFG_TELE_EN ((uint8_t) 0x10) /* Event flag latch enabled: the transient */
1122  /* interrupt event flag is latched and a read of */
1123  /* the TRANSIENT_SRC register is required to */
1124  /* clear the event flag */
1125 #define FXOS8700_TRANSIENT_CFG_TELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled: the transient */
1126  /* interrupt flag reflects the real-time status */
1127  /* of the function */
1128 #define FXOS8700_TRANSIENT_CFG_ZTEFE_EN ((uint8_t) 0x08) /* Z-axis event detection enabled. Raise event */
1129  /* flag on Z-axis acceleration value greater than */
1130  /* threshold */
1131 #define FXOS8700_TRANSIENT_CFG_ZTEFE_DIS ((uint8_t) 0x00) /* Z-axis event detection disabled */
1132 #define FXOS8700_TRANSIENT_CFG_YTEFE_EN ((uint8_t) 0x04) /* Y-axis event detection enabled. Raise event */
1133  /* flag on Y-axis acceleration value greater than */
1134  /* threshold */
1135 #define FXOS8700_TRANSIENT_CFG_YTEFE_DIS ((uint8_t) 0x00) /* Y-axis event detection disabled */
1136 #define FXOS8700_TRANSIENT_CFG_XTEFE_EN ((uint8_t) 0x02) /* X-axis event detection enabled. Raise event */
1137  /* flag on X-axis acceleration value greater than */
1138  /* threshold */
1139 #define FXOS8700_TRANSIENT_CFG_XTEFE_DIS ((uint8_t) 0x00) /* X-axis event detection disabled */
1140 #define FXOS8700_TRANSIENT_CFG_HPF_BYP_EN ((uint8_t) 0x01) /* High-pass filter is not applied to */
1141  /* accelerometer data input to the transient */
1142  /* function */
1143 #define FXOS8700_TRANSIENT_CFG_HPF_BYP_DIS ((uint8_t) 0x00) /* High-pass filter is applied to accelerometer */
1144  /* data input to the transient function */
1145 /*------------------------------*/
1146 
1147 
1148 
1149 /*--------------------------------
1150 ** Register: TRANSIENT_SRC
1151 ** Enum: FXOS8700_TRANSIENT_SRC
1152 ** --
1153 ** Offset : 0x1E - Transient event status register.
1154 ** ------------------------------*/
1155 typedef union {
1156  struct {
1157  uint8_t trans_xpol : 1;
1158  uint8_t tran_xef : 1;
1159  uint8_t tran_ypol : 1;
1160  uint8_t tran_yef : 1;
1161  uint8_t tran_zpol : 1;
1162  uint8_t tran_zef : 1;
1163  uint8_t tran_ea : 1;
1164  } b;
1165  uint8_t w;
1166 } FXOS8700_TRANSIENT_SRC_t;
1167 
1168 
1169 /*
1170 ** TRANSIENT_SRC - Bit field mask definitions
1171 */
1172 #define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_MASK ((uint8_t) 0x01)
1173 #define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_SHIFT ((uint8_t) 0)
1174 
1175 #define FXOS8700_TRANSIENT_SRC_TRAN_XEF_MASK ((uint8_t) 0x02)
1176 #define FXOS8700_TRANSIENT_SRC_TRAN_XEF_SHIFT ((uint8_t) 1)
1177 
1178 #define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_MASK ((uint8_t) 0x04)
1179 #define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_SHIFT ((uint8_t) 2)
1180 
1181 #define FXOS8700_TRANSIENT_SRC_TRAN_YEF_MASK ((uint8_t) 0x08)
1182 #define FXOS8700_TRANSIENT_SRC_TRAN_YEF_SHIFT ((uint8_t) 3)
1183 
1184 #define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_MASK ((uint8_t) 0x10)
1185 #define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_SHIFT ((uint8_t) 4)
1186 
1187 #define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_MASK ((uint8_t) 0x20)
1188 #define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_SHIFT ((uint8_t) 5)
1189 
1190 #define FXOS8700_TRANSIENT_SRC_TRAN_EA_MASK ((uint8_t) 0x40)
1191 #define FXOS8700_TRANSIENT_SRC_TRAN_EA_SHIFT ((uint8_t) 6)
1192 
1193 
1194 /*------------------------------*/
1195 
1196 
1197 
1198 /*--------------------------------
1199 ** Register: TRANSIENT_THS
1200 ** Enum: FXOS8700_TRANSIENT_THS
1201 ** --
1202 ** Offset : 0x1F - Transient event threshold.
1203 ** ------------------------------*/
1204 typedef union {
1205  struct {
1206  uint8_t tr_ths : 7;
1207  uint8_t tr_dbcntm : 1;
1208  } b;
1209  uint8_t w;
1210 } FXOS8700_TRANSIENT_THS_t;
1211 
1212 
1213 /*
1214 ** TRANSIENT_THS - Bit field mask definitions
1215 */
1216 #define FXOS8700_TRANSIENT_THS_TR_THS_MASK ((uint8_t) 0x7F)
1217 #define FXOS8700_TRANSIENT_THS_TR_THS_SHIFT ((uint8_t) 0)
1218 
1219 #define FXOS8700_TRANSIENT_THS_TR_DBCNTM_MASK ((uint8_t) 0x80)
1220 #define FXOS8700_TRANSIENT_THS_TR_DBCNTM_SHIFT ((uint8_t) 7)
1221 
1222 
1223 /*
1224 ** TRANSIENT_THS - Bit field value definitions
1225 */
1226 #define FXOS8700_TRANSIENT_THS_TR_THS_DECREMENTS ((uint8_t) 0x00) /* Decrements debounce counter when the transient */
1227  /* event condition is not true during the current */
1228  /* ODR period */
1229 #define FXOS8700_TRANSIENT_THS_TR_THS_CLEAR ((uint8_t) 0x01) /* Clears debounce counter when the transient */
1230  /* event condition is not true during the current */
1231  /* ODR period */
1232 /*------------------------------*/
1233 
1234 
1235 
1236 /*--------------------------------
1237 ** Register: TRANSIENT_COUNT
1238 ** Enum: FXOS8700_TRANSIENT_COUNT
1239 ** --
1240 ** Offset : 0x20 - Transient debounce counter.
1241 ** ------------------------------*/
1242 typedef uint8_t FXOS8700_TRANSIENT_COUNT_t;
1243 
1244 
1245 
1246 
1247 
1248 /*--------------------------------
1249 ** Register: PULSE_CFG
1250 ** Enum: FXOS8700_PULSE_CFG
1251 ** --
1252 ** Offset : 0x21 - Pulse function configuration.
1253 ** ------------------------------*/
1254 typedef union {
1255  struct {
1256  uint8_t pls_xspefe : 1;
1257  uint8_t pls_xdpefe : 1;
1258  uint8_t pls_yspefe : 1;
1259  uint8_t pls_ydpefe : 1;
1260  uint8_t pls_zspefe : 1;
1261  uint8_t pls_zdpefe : 1;
1262  uint8_t pls_ele : 1;
1263  uint8_t pls_dpa : 1;
1264  } b;
1265  uint8_t w;
1266 } FXOS8700_PULSE_CFG_t;
1267 
1268 
1269 /*
1270 ** PULSE_CFG - Bit field mask definitions
1271 */
1272 #define FXOS8700_PULSE_CFG_PLS_XSPEFE_MASK ((uint8_t) 0x01)
1273 #define FXOS8700_PULSE_CFG_PLS_XSPEFE_SHIFT ((uint8_t) 0)
1274 
1275 #define FXOS8700_PULSE_CFG_PLS_XDPEFE_MASK ((uint8_t) 0x02)
1276 #define FXOS8700_PULSE_CFG_PLS_XDPEFE_SHIFT ((uint8_t) 1)
1277 
1278 #define FXOS8700_PULSE_CFG_PLS_YSPEFE_MASK ((uint8_t) 0x04)
1279 #define FXOS8700_PULSE_CFG_PLS_YSPEFE_SHIFT ((uint8_t) 2)
1280 
1281 #define FXOS8700_PULSE_CFG_PLS_YDPEFE_MASK ((uint8_t) 0x08)
1282 #define FXOS8700_PULSE_CFG_PLS_YDPEFE_SHIFT ((uint8_t) 3)
1283 
1284 #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_MASK ((uint8_t) 0x10)
1285 #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_SHIFT ((uint8_t) 4)
1286 
1287 #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_MASK ((uint8_t) 0x20)
1288 #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_SHIFT ((uint8_t) 5)
1289 
1290 #define FXOS8700_PULSE_CFG_PLS_ELE_MASK ((uint8_t) 0x40)
1291 #define FXOS8700_PULSE_CFG_PLS_ELE_SHIFT ((uint8_t) 6)
1292 
1293 #define FXOS8700_PULSE_CFG_PLS_DPA_MASK ((uint8_t) 0x80)
1294 #define FXOS8700_PULSE_CFG_PLS_DPA_SHIFT ((uint8_t) 7)
1295 
1296 
1297 /*
1298 ** PULSE_CFG - Bit field value definitions
1299 */
1300 #define FXOS8700_PULSE_CFG_PLS_DPA_DIS ((uint8_t) 0x00) /* Setting the pls_dpa bit momentarily suspends the */
1301  /* double-tap detection if the start of a pulse is */
1302  /* detected during the time period specified by the */
1303  /* PULSE_LTCY register and the pulse ends before the */
1304  /* end of the time period specified by the PULSE_LTCY */
1305  /* register */
1306 #define FXOS8700_PULSE_CFG_PLS_DPA_EN ((uint8_t) 0x80) /* Double-pulse detection is not aborted if the start */
1307  /* of a pulse is detected during the time period */
1308  /* specified by the PULSE_LTCY register */
1309 #define FXOS8700_PULSE_CFG_PLS_ELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1310 #define FXOS8700_PULSE_CFG_PLS_ELE_EN ((uint8_t) 0x40) /* Event flag latch enabled */
1311 #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1312 #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_EN ((uint8_t) 0x20) /* Raise event flag on detection of double-pulse */
1313  /* event on Z-axis */
1314 #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1315 #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_EN ((uint8_t) 0x10) /* Raise event flag on detection of single-pulse */
1316  /* event on Z-axis */
1317 #define FXOS8700_PULSE_CFG_PLS_YDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1318 #define FXOS8700_PULSE_CFG_PLS_YDPEFE_EN ((uint8_t) 0x08) /* Raise event flag on detection of double-pulse */
1319  /* event on Y-axis */
1320 #define FXOS8700_PULSE_CFG_PLS_YSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1321 #define FXOS8700_PULSE_CFG_PLS_YSPEFE_EN ((uint8_t) 0x04) /* Raise event flag on detection of single-pulse */
1322  /* event on Y-axis */
1323 #define FXOS8700_PULSE_CFG_PLS_XDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1324 #define FXOS8700_PULSE_CFG_PLS_XDPEFE_EN ((uint8_t) 0x02) /* Raise event flag on detection of double-pulse */
1325  /* event on X-axis */
1326 #define FXOS8700_PULSE_CFG_PLS_XSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1327 #define FXOS8700_PULSE_CFG_PLS_XSPEFE_EN ((uint8_t) 0x01) /* Raise event flag on detection of single-pulse */
1328  /* event on X-axis */
1329 /*------------------------------*/
1330 
1331 
1332 
1333 /*--------------------------------
1334 ** Register: PULSE_SRC
1335 ** Enum: FXOS8700_PULSE_SRC
1336 ** --
1337 ** Offset : 0x22 - Pulse function source register.
1338 ** ------------------------------*/
1339 typedef union {
1340  struct {
1341  uint8_t pls_src_polx : 1;
1342  uint8_t pls_src_poly : 1;
1343  uint8_t pls_src_polz : 1;
1344  uint8_t pls_src_dpe : 1;
1345  uint8_t pls_src_axx : 1;
1346  uint8_t pls_src_axy : 1;
1347  uint8_t pls_src_axz : 1;
1348  uint8_t pls_src_ea : 1;
1349  } b;
1350  uint8_t w;
1351 } FXOS8700_PULSE_SRC_t;
1352 
1353 
1354 /*
1355 ** PULSE_SRC - Bit field mask definitions
1356 */
1357 #define FXOS8700_PULSE_SRC_PLS_SRC_POLX_MASK ((uint8_t) 0x01)
1358 #define FXOS8700_PULSE_SRC_PLS_SRC_POLX_SHIFT ((uint8_t) 0)
1359 
1360 #define FXOS8700_PULSE_SRC_PLS_SRC_POLY_MASK ((uint8_t) 0x02)
1361 #define FXOS8700_PULSE_SRC_PLS_SRC_POLY_SHIFT ((uint8_t) 1)
1362 
1363 #define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_MASK ((uint8_t) 0x04)
1364 #define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_SHIFT ((uint8_t) 2)
1365 
1366 #define FXOS8700_PULSE_SRC_PLS_SRC_DPE_MASK ((uint8_t) 0x08)
1367 #define FXOS8700_PULSE_SRC_PLS_SRC_DPE_SHIFT ((uint8_t) 3)
1368 
1369 #define FXOS8700_PULSE_SRC_PLS_SRC_AXX_MASK ((uint8_t) 0x10)
1370 #define FXOS8700_PULSE_SRC_PLS_SRC_AXX_SHIFT ((uint8_t) 4)
1371 
1372 #define FXOS8700_PULSE_SRC_PLS_SRC_AXY_MASK ((uint8_t) 0x20)
1373 #define FXOS8700_PULSE_SRC_PLS_SRC_AXY_SHIFT ((uint8_t) 5)
1374 
1375 #define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_MASK ((uint8_t) 0x40)
1376 #define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_SHIFT ((uint8_t) 6)
1377 
1378 #define FXOS8700_PULSE_SRC_PLS_SRC_EA_MASK ((uint8_t) 0x80)
1379 #define FXOS8700_PULSE_SRC_PLS_SRC_EA_SHIFT ((uint8_t) 7)
1380 
1381 
1382 /*------------------------------*/
1383 
1384 
1385 
1386 /*--------------------------------
1387 ** Register: PULSE_THSX
1388 ** Enum: FXOS8700_PULSE_THSX
1389 ** --
1390 ** Offset : 0x23 - X-axis pulse threshold.
1391 ** ------------------------------*/
1392 typedef union {
1393  struct {
1394  uint8_t pls_thsx : 7;
1395  } b;
1396  uint8_t w;
1397 } FXOS8700_PULSE_THSX_t;
1398 
1399 
1400 /*
1401 ** PULSE_THSX - Bit field mask definitions
1402 */
1403 #define FXOS8700_PULSE_THSX_PLS_THSX_MASK ((uint8_t) 0x7F)
1404 #define FXOS8700_PULSE_THSX_PLS_THSX_SHIFT ((uint8_t) 0)
1405 
1406 
1407 /*------------------------------*/
1408 
1409 
1410 
1411 /*--------------------------------
1412 ** Register: PULSE_THSY
1413 ** Enum: FXOS8700_PULSE_THSY
1414 ** --
1415 ** Offset : 0x24 - Y-axis pulse threshold.
1416 ** ------------------------------*/
1417 typedef union {
1418  struct {
1419  uint8_t pls_thsy : 7;
1420  } b;
1421  uint8_t w;
1422 } FXOS8700_PULSE_THSY_t;
1423 
1424 
1425 /*
1426 ** PULSE_THSY - Bit field mask definitions
1427 */
1428 #define FXOS8700_PULSE_THSY_PLS_THSY_MASK ((uint8_t) 0x7F)
1429 #define FXOS8700_PULSE_THSY_PLS_THSY_SHIFT ((uint8_t) 0)
1430 
1431 
1432 /*------------------------------*/
1433 
1434 
1435 
1436 /*--------------------------------
1437 ** Register: PULSE_THSZ
1438 ** Enum: FXOS8700_PULSE_THSZ
1439 ** --
1440 ** Offset : 0x25 - Z-axis pulse threshold.
1441 ** ------------------------------*/
1442 typedef union {
1443  struct {
1444  uint8_t pls_thsz : 7;
1445  } b;
1446  uint8_t w;
1447 } FXOS8700_PULSE_THSZ_t;
1448 
1449 
1450 /*
1451 ** PULSE_THSZ - Bit field mask definitions
1452 */
1453 #define FXOS8700_PULSE_THSZ_PLS_THSZ_MASK ((uint8_t) 0x7F)
1454 #define FXOS8700_PULSE_THSZ_PLS_THSZ_SHIFT ((uint8_t) 0)
1455 
1456 
1457 /*------------------------------*/
1458 
1459 
1460 
1461 /*--------------------------------
1462 ** Register: PULSE_TMLT
1463 ** Enum: FXOS8700_PULSE_TMLT
1464 ** --
1465 ** Offset : 0x26 - Time limit for pulse detection.
1466 ** ------------------------------*/
1467 typedef uint8_t FXOS8700_PULSE_TMLT_t;
1468 
1469 
1470 
1471 /*--------------------------------
1472 ** Register: PULSE_LTCY
1473 ** Enum: FXOS8700_PULSE_LTCY
1474 ** --
1475 ** Offset : 0x27 - Latency time for second pulse detection.
1476 ** ------------------------------*/
1477 typedef uint8_t FXOS8700_PULSE_LTCY_t;
1478 
1479 
1480 /*--------------------------------
1481 ** Register: PULSE_WIND
1482 ** Enum: FXOS8700_PULSE_WIND
1483 ** --
1484 ** Offset : 0x28 - Window time for second pulse detection.
1485 ** ------------------------------*/
1486 typedef uint8_t FXOS8700_PULSE_WIND_t;
1487 
1488 
1489 
1490 /*--------------------------------
1491 ** Register: ASLP_COUNT
1492 ** Enum: FXOS8700_ASLP_COUNT
1493 ** --
1494 ** Offset : 0x29 - The counter setting for auto-sleep period.
1495 ** ------------------------------*/
1496 typedef uint8_t FXOS8700_ASLP_COUNT_t;
1497 
1498 
1499 
1500 /*--------------------------------
1501 ** Register: CTRL_REG1
1502 ** Enum: FXOS8700_CTRL_REG1
1503 ** --
1504 ** Offset : 0x2A - System ODR, accelerometer OSR (Output sample rate), operating mode.
1505 ** ------------------------------*/
1506 typedef union {
1507  struct {
1508  uint8_t active : 1;
1509  uint8_t f_read : 1;
1510  uint8_t lnoise : 1;
1511  uint8_t dr : 3;
1512  uint8_t aslp_rate : 2;
1513  } b;
1514  uint8_t w;
1515 } FXOS8700_CTRL_REG1_t;
1516 
1517 
1518 /*
1519 ** CTRL_REG1 - Bit field mask definitions
1520 */
1521 #define FXOS8700_CTRL_REG1_ACTIVE_MASK ((uint8_t) 0x01)
1522 #define FXOS8700_CTRL_REG1_ACTIVE_SHIFT ((uint8_t) 0)
1523 
1524 #define FXOS8700_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1525 #define FXOS8700_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1526 
1527 #define FXOS8700_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1528 #define FXOS8700_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1529 
1530 #define FXOS8700_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1531 #define FXOS8700_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1532 
1533 #define FXOS8700_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1534 #define FXOS8700_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1535 
1536 
1537 /*
1538 ** CTRL_REG1 - Bit field value definitions
1539 */
1540 #define FXOS8700_CTRL_REG1_ASLP_RATE_50_HZ ((uint8_t) 0x00)
1541 #define FXOS8700_CTRL_REG1_ASLP_RATE_12P5_HZ ((uint8_t) 0x40)
1542 #define FXOS8700_CTRL_REG1_ASLP_RATE_6P25_HZ ((uint8_t) 0x80)
1543 #define FXOS8700_CTRL_REG1_ASLP_RATE_1P56_HZ ((uint8_t) 0xc0)
1544 #define FXOS8700_CTRL_REG1_DR_SINGLE_800_HZ ((uint8_t) 0x00)
1545 #define FXOS8700_CTRL_REG1_DR_SINGLE_400_HZ ((uint8_t) 0x08)
1546 #define FXOS8700_CTRL_REG1_DR_SINGLE_200_HZ ((uint8_t) 0x10)
1547 #define FXOS8700_CTRL_REG1_DR_SINGLE_100_HZ ((uint8_t) 0x18)
1548 #define FXOS8700_CTRL_REG1_DR_SINGLE_50_HZ ((uint8_t) 0x20)
1549 #define FXOS8700_CTRL_REG1_DR_SINGLE_12P5_HZ ((uint8_t) 0x28)
1550 #define FXOS8700_CTRL_REG1_DR_SINGLE_6P25_HZ ((uint8_t) 0x30)
1551 #define FXOS8700_CTRL_REG1_DR_SINGLE_1P5625_HZ ((uint8_t) 0x38)
1552 #define FXOS8700_CTRL_REG1_DR_HYBRID_400_HZ ((uint8_t) 0x00)
1553 #define FXOS8700_CTRL_REG1_DR_HYBRID_200_HZ ((uint8_t) 0x08)
1554 #define FXOS8700_CTRL_REG1_DR_HYBRID_100_HZ ((uint8_t) 0x10)
1555 #define FXOS8700_CTRL_REG1_DR_HYBRID_50_HZ ((uint8_t) 0x18)
1556 #define FXOS8700_CTRL_REG1_DR_HYBRID_25_HZ ((uint8_t) 0x20)
1557 #define FXOS8700_CTRL_REG1_DR_HYBRID_6P25_HZ ((uint8_t) 0x28)
1558 #define FXOS8700_CTRL_REG1_DR_HYBRID_3P125_HZ ((uint8_t) 0x30)
1559 #define FXOS8700_CTRL_REG1_DR_HYBRID_0P7813_HZ ((uint8_t) 0x38)
1560 #define FXOS8700_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode */
1561 #define FXOS8700_CTRL_REG1_LNOISE_REDUCED_NOISE ((uint8_t) 0x04) /* Reduced noise mode; Note that the FSR setting is */
1562  /* restricted to ±2 g or ±4 g mode. This feature */
1563  /* cannot be used in ±8 g mode */
1564 #define FXOS8700_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode */
1565 #define FXOS8700_CTRL_REG1_F_READ_FAST ((uint8_t) 0x02) /* Fast-read mode */
1566 #define FXOS8700_CTRL_REG1_ACTIVE_ACTIVE_MODE ((uint8_t) 0x01) /* Active mode */
1567 #define FXOS8700_CTRL_REG1_ACTIVE_STANDBY_MODE ((uint8_t) 0x00) /* Standby mode */
1568 /*------------------------------*/
1569 
1570 
1571 
1572 /*--------------------------------
1573 ** Register: CTRL_REG2
1574 ** Enum: FXOS8700_CTRL_REG2
1575 ** --
1576 ** Offset : 0x2B - Self-test, reset, accelerometer OSR, and sleep mode settings.
1577 ** ------------------------------*/
1578 typedef union {
1579  struct {
1580  uint8_t mods : 2;
1581  uint8_t slpe : 1;
1582  uint8_t smods : 2;
1583  uint8_t _reserved_ : 1;
1584  uint8_t rst : 1;
1585  uint8_t st : 1;
1586  } b;
1587  uint8_t w;
1588 } FXOS8700_CTRL_REG2_t;
1589 
1590 
1591 /*
1592 ** CTRL_REG2 - Bit field mask definitions
1593 */
1594 #define FXOS8700_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1595 #define FXOS8700_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1596 
1597 #define FXOS8700_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1598 #define FXOS8700_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1599 
1600 #define FXOS8700_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1601 #define FXOS8700_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1602 
1603 #define FXOS8700_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1604 #define FXOS8700_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1605 
1606 #define FXOS8700_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1607 #define FXOS8700_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1608 
1609 
1610 /*
1611 ** CTRL_REG2 - Bit field value definitions
1612 */
1613 #define FXOS8700_CTRL_REG2_ST_DIS ((uint8_t) 0x00) /* Self-test disabled */
1614 #define FXOS8700_CTRL_REG2_ST_EN ((uint8_t) 0x80) /* Self-test enabled */
1615 #define FXOS8700_CTRL_REG2_RST_EN ((uint8_t) 0x40) /* Device reset enabled */
1616 #define FXOS8700_CTRL_REG2_RST_DIS ((uint8_t) 0x00) /* Device reset disabled */
1617 #define FXOS8700_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00)
1618 #define FXOS8700_CTRL_REG2_SMODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x08)
1619 #define FXOS8700_CTRL_REG2_SMODS_HIGH_RES ((uint8_t) 0x10)
1620 #define FXOS8700_CTRL_REG2_SMODS_LOW_POWER ((uint8_t) 0x18)
1621 #define FXOS8700_CTRL_REG2_SLPE_EN ((uint8_t) 0x04)
1622 #define FXOS8700_CTRL_REG2_SLPE_DISABLE ((uint8_t) 0x00)
1623 #define FXOS8700_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00)
1624 #define FXOS8700_CTRL_REG2_MODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x01)
1625 #define FXOS8700_CTRL_REG2_MODS_HIGH_RES ((uint8_t) 0x02)
1626 #define FXOS8700_CTRL_REG2_MODS_LOW_POWER ((uint8_t) 0x03)
1627 /*------------------------------*/
1628 
1629 
1630 
1631 /*--------------------------------
1632 ** Register: CTRL_REG3
1633 ** Enum: FXOS8700_CTRL_REG3
1634 ** --
1635 ** Offset : 0x2C - Sleep mode interrupt wake enable, interrupt polarity, push-pull/open drain configuration.
1636 ** ------------------------------*/
1637 typedef union {
1638  struct {
1639  uint8_t pp_od : 1;
1640  uint8_t ipol : 1;
1641  uint8_t wake_a_vecm : 1;
1642  uint8_t wake_ffmt : 1;
1643  uint8_t wake_pulse : 1;
1644  uint8_t wake_lndprt : 1;
1645  uint8_t wake_trans : 1;
1646  uint8_t fifo_gate : 1;
1647  } b;
1648  uint8_t w;
1649 } FXOS8700_CTRL_REG3_t;
1650 
1651 
1652 /*
1653 ** CTRL_REG3 - Bit field mask definitions
1654 */
1655 #define FXOS8700_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1656 #define FXOS8700_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1657 
1658 #define FXOS8700_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1659 #define FXOS8700_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1660 
1661 #define FXOS8700_CTRL_REG3_WAKE_A_VECM_MASK ((uint8_t) 0x04)
1662 #define FXOS8700_CTRL_REG3_WAKE_A_VECM_SHIFT ((uint8_t) 2)
1663 
1664 #define FXOS8700_CTRL_REG3_WAKE_FFMT_MASK ((uint8_t) 0x08)
1665 #define FXOS8700_CTRL_REG3_WAKE_FFMT_SHIFT ((uint8_t) 3)
1666 
1667 #define FXOS8700_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1668 #define FXOS8700_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1669 
1670 #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1671 #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1672 
1673 #define FXOS8700_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1674 #define FXOS8700_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1675 
1676 #define FXOS8700_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1677 #define FXOS8700_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1678 
1679 
1680 /*
1681 ** CTRL_REG3 - Bit field value definitions
1682 */
1683 #define FXOS8700_CTRL_REG3_FIFO_GATE_BYPASSED ((uint8_t) 0x00) /* FIFO gate is bypassed */
1684 #define FXOS8700_CTRL_REG3_FIFO_GATE_BLOCKED ((uint8_t) 0x80) /* The FIFO input buffer is blocked from accepting */
1685  /* new samples when transitioning from wake-to-sleep */
1686  /* mode or from sleep-to-wake mode until the FIFO is */
1687  /* flushed */
1688 #define FXOS8700_CTRL_REG3_WAKE_TRANS_DIS ((uint8_t) 0x00) /* Transient function is disabled in sleep mode */
1689 #define FXOS8700_CTRL_REG3_WAKE_TRANS_EN ((uint8_t) 0x40) /* Transient function is enabled in sleep mode and */
1690  /* can generate an interrupt to wake the system */
1691 #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_DIS ((uint8_t) 0x00) /* Orientation function is disabled sleep mode */
1692 #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_EN ((uint8_t) 0x20) /* Orientation function is enabled in sleep mode and */
1693  /* can generate an interrupt to wake the system */
1694 #define FXOS8700_CTRL_REG3_WAKE_PULSE_DIS ((uint8_t) 0x00) /* Pulse function is disabled in sleep mode */
1695 #define FXOS8700_CTRL_REG3_WAKE_PULSE_EN ((uint8_t) 0x10) /* Pulse function is enabled in sleep mode and can */
1696  /* generate an interrupt to wake the system */
1697 #define FXOS8700_CTRL_REG3_WAKE_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion function is disabled in sleep mode */
1698 #define FXOS8700_CTRL_REG3_WAKE_FFMT_EN ((uint8_t) 0x08) /* Freefall/motion function is enabled in sleep mode */
1699  /* and can generate an interrupt to wake the system */
1700 #define FXOS8700_CTRL_REG3_WAKE_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude function is disabled */
1701  /* in sleep mode */
1702 #define FXOS8700_CTRL_REG3_WAKE_A_VECM_EN ((uint8_t) 0x04) /* Acceleration vector-magnitude function is enabled */
1703  /* in sleep mode and can generate an interrupt to */
1704  /* wake the system */
1705 #define FXOS8700_CTRL_REG3_IPOL_ACTIVE_LOW ((uint8_t) 0x00) /* Active Low */
1706 #define FXOS8700_CTRL_REG3_IPOL_ACTIVE_HIGH ((uint8_t) 0x02) /* Active High */
1707 #define FXOS8700_CTRL_REG3_PP_OD_PUSH_PULL ((uint8_t) 0x00) /* Push-pull */
1708 #define FXOS8700_CTRL_REG3_PP_OD_OPEN_DRAIN ((uint8_t) 0x01) /* Open Drain */
1709 /*------------------------------*/
1710 
1711 
1712 
1713 /*--------------------------------
1714 ** Register: CTRL_REG4
1715 ** Enum: FXOS8700_CTRL_REG4
1716 ** --
1717 ** Offset : 0x2D - Interrupt enable register.
1718 ** ------------------------------*/
1719 typedef union {
1720  struct {
1721  uint8_t int_en_drdy : 1;
1722  uint8_t int_en_a_vecm : 1;
1723  uint8_t int_en_ffmt : 1;
1724  uint8_t int_en_pulse : 1;
1725  uint8_t int_en_lndprt : 1;
1726  uint8_t int_en_trans : 1;
1727  uint8_t int_en_fifo : 1;
1728  uint8_t int_en_aslp : 1;
1729  } b;
1730  uint8_t w;
1731 } FXOS8700_CTRL_REG4_t;
1732 
1733 
1734 /*
1735 ** CTRL_REG4 - Bit field mask definitions
1736 */
1737 #define FXOS8700_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1738 #define FXOS8700_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1739 
1740 #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_MASK ((uint8_t) 0x02)
1741 #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_SHIFT ((uint8_t) 1)
1742 
1743 #define FXOS8700_CTRL_REG4_INT_EN_FFMT_MASK ((uint8_t) 0x04)
1744 #define FXOS8700_CTRL_REG4_INT_EN_FFMT_SHIFT ((uint8_t) 2)
1745 
1746 #define FXOS8700_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1747 #define FXOS8700_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1748 
1749 #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1750 #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1751 
1752 #define FXOS8700_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1753 #define FXOS8700_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1754 
1755 #define FXOS8700_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1756 #define FXOS8700_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1757 
1758 #define FXOS8700_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1759 #define FXOS8700_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1760 
1761 
1762 /*
1763 ** CTRL_REG4 - Bit field value definitions
1764 */
1765 #define FXOS8700_CTRL_REG4_INT_EN_ASLP_DIS ((uint8_t) 0x00) /* Auto-sleep/wake interrupt disabled */
1766 #define FXOS8700_CTRL_REG4_INT_EN_ASLP_EN ((uint8_t) 0x80) /* Auto-sleep/wake interrupt Enabled */
1767 #define FXOS8700_CTRL_REG4_INT_EN_FIFO_DIS ((uint8_t) 0x00) /* FIFO interrupt disabled */
1768 #define FXOS8700_CTRL_REG4_INT_EN_FIFO_EN ((uint8_t) 0x40) /* FIFO interrupt enabled */
1769 #define FXOS8700_CTRL_REG4_INT_EN_TRANS_DIS ((uint8_t) 0x00) /* Transient interrupt disabled */
1770 #define FXOS8700_CTRL_REG4_INT_EN_TRANS_EN ((uint8_t) 0x20) /* Transient interrupt enabled */
1771 #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_DIS ((uint8_t) 0x00) /* Orientation (landscape/portrait) interrupt */
1772  /* disabled */
1773 #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_EN ((uint8_t) 0x10) /* Orientation (landscape/portrait) interrupt enabled */
1774 #define FXOS8700_CTRL_REG4_INT_EN_PULSE_DIS ((uint8_t) 0x00) /* Pulse detection interrupt disabled */
1775 #define FXOS8700_CTRL_REG4_INT_EN_PULSE_EN ((uint8_t) 0x08) /* Pulse detection interrupt enabled */
1776 #define FXOS8700_CTRL_REG4_INT_EN_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion interrupt disabled */
1777 #define FXOS8700_CTRL_REG4_INT_EN_FFMT_EN ((uint8_t) 0x04) /* Freefall/motion interrupt enabled */
1778 #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude interrupt disabled */
1779 #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_EN ((uint8_t) 0x02) /* Acceleration vector-magnitude interrupt disabled */
1780 #define FXOS8700_CTRL_REG4_INT_EN_DRDY_DIS ((uint8_t) 0x00) /* Data-ready interrupt disabled */
1781 #define FXOS8700_CTRL_REG4_INT_EN_DRDY_EN ((uint8_t) 0x01) /* Data-ready interrupt Enabled */
1782 /*------------------------------*/
1783 
1784 
1785 
1786 /*--------------------------------
1787 ** Register: CTRL_REG5
1788 ** Enum: FXOS8700_CTRL_REG5
1789 ** --
1790 ** Offset : 0x2E - Interrupt pin (INT1/INT2) map.
1791 ** ------------------------------*/
1792 typedef union {
1793  struct {
1794  uint8_t int_cfg_drdy : 1;
1795  uint8_t int_cfg_a_vecm : 1;
1796  uint8_t int_cfg_ffmt : 1;
1797  uint8_t int_cfg_pulse : 1;
1798  uint8_t int_cfg_lndprt : 1;
1799  uint8_t int_cfg_trans : 1;
1800  uint8_t int_cfg_fifo : 1;
1801  uint8_t int_cfg_aslp : 1;
1802  } b;
1803  uint8_t w;
1804 } FXOS8700_CTRL_REG5_t;
1805 
1806 
1807 /*
1808 ** CTRL_REG5 - Bit field mask definitions
1809 */
1810 #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1811 #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1812 
1813 #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_MASK ((uint8_t) 0x02)
1814 #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_SHIFT ((uint8_t) 1)
1815 
1816 #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_MASK ((uint8_t) 0x04)
1817 #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_SHIFT ((uint8_t) 2)
1818 
1819 #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1820 #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1821 
1822 #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1823 #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1824 
1825 #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1826 #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1827 
1828 #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1829 #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1830 
1831 #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1832 #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1833 
1834 
1835 /*
1836 ** CTRL_REG5 - Bit field value definitions
1837 */
1838 #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1839 #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin */
1840 #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1841 #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin */
1842 #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1843 #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin */
1844 #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1845 #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin */
1846 #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1847 #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin */
1848 #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1849 #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin */
1850 #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1851 #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 pin */
1852 #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1853 #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin */
1854 /*------------------------------*/
1855 
1856 
1857 
1858 /*--------------------------------
1859 ** Register: OFF_X
1860 ** Enum: FXOS8700_OFF_X
1861 ** --
1862 ** Offset : 0x2F - X-axis accelerometer offset adjust.
1863 ** ------------------------------*/
1864 typedef uint8_t FXOS8700_OFF_X_t;
1865 
1866 
1867 /*--------------------------------
1868 ** Register: OFF_Y
1869 ** Enum: FXOS8700_OFF_Y
1870 ** --
1871 ** Offset : 0x30 - Y-axis accelerometer offset adjust.
1872 ** ------------------------------*/
1873 typedef uint8_t FXOS8700_OFF_Y_t;
1874 
1875 
1876 /*--------------------------------
1877 ** Register: OFF_Z
1878 ** Enum: FXOS8700_OFF_Z
1879 ** --
1880 ** Offset : 0x31 - Z-axis accelerometer offset adjust.
1881 ** ------------------------------*/
1882 typedef uint8_t FXOS8700_OFF_Z_t;
1883 
1884 
1885 
1886 /*--------------------------------
1887 ** Register: M_DR_STATUS
1888 ** Enum: FXOS8700_M_DR_STATUS
1889 ** --
1890 ** Offset : 0x32 - The magnetometer data ready status.
1891 ** ------------------------------*/
1892 typedef union {
1893  struct {
1894  uint8_t xdr : 1;
1895  uint8_t ydr : 1;
1896  uint8_t zdr : 1;
1897  uint8_t zyxdr : 1;
1898  uint8_t xow : 1;
1899  uint8_t yow : 1;
1900  uint8_t zow : 1;
1901  uint8_t zyxow : 1;
1902  } b;
1903  uint8_t w;
1904 } FXOS8700_M_DR_STATUS_t;
1905 
1906 
1907 /*
1908 ** M_DR_STATUS - Bit field mask definitions
1909 */
1910 #define FXOS8700_M_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
1911 #define FXOS8700_M_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
1912 
1913 #define FXOS8700_M_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
1914 #define FXOS8700_M_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
1915 
1916 #define FXOS8700_M_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
1917 #define FXOS8700_M_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
1918 
1919 #define FXOS8700_M_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
1920 #define FXOS8700_M_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
1921 
1922 #define FXOS8700_M_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
1923 #define FXOS8700_M_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
1924 
1925 #define FXOS8700_M_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
1926 #define FXOS8700_M_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
1927 
1928 #define FXOS8700_M_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
1929 #define FXOS8700_M_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
1930 
1931 #define FXOS8700_M_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
1932 #define FXOS8700_M_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
1933 
1934 
1935 /*------------------------------*/
1936 
1937 
1938 
1939 /*--------------------------------
1940 ** Register: M_OUT_X_MSB
1941 ** Enum: FXOS8700_M_OUT_X_MSB
1942 ** --
1943 ** Offset : 0x33 - MSB of the 16-bit magnetometer data for X-axis.
1944 ** ------------------------------*/
1945 typedef uint8_t FXOS8700_M_OUT_X_MSB_t;
1946 
1947 
1948 /*--------------------------------
1949 ** Register: M_OUT_X_LSB
1950 ** Enum: FXOS8700_M_OUT_X_LSB
1951 ** --
1952 ** Offset : 0x34 - LSB of the 16-bit magnetometer data for X-axis.
1953 ** ------------------------------*/
1954 typedef uint8_t FXOS8700_M_OUT_X_LSB_t;
1955 
1956 
1957 /*--------------------------------
1958 ** Register: M_OUT_Y_MSB
1959 ** Enum: FXOS8700_M_OUT_Y_MSB
1960 ** --
1961 ** Offset : 0x35 - MSB of the 16-bit magnetometer data for Y-axis.
1962 ** ------------------------------*/
1963 typedef uint8_t FXOS8700_M_OUT_Y_MSB_t;
1964 
1965 
1966 /*--------------------------------
1967 ** Register: M_OUT_Y_LSB
1968 ** Enum: FXOS8700_M_OUT_Y_LSB
1969 ** --
1970 ** Offset : 0x36 - LSB of the 16-bit magnetometer data for Y-axis.
1971 ** ------------------------------*/
1972 typedef uint8_t FXOS8700_M_OUT_Y_LSB_t;
1973 
1974 
1975 /*--------------------------------
1976 ** Register: M_OUT_Z_MSB
1977 ** Enum: FXOS8700_M_OUT_Z_MSB
1978 ** --
1979 ** Offset : 0x37 - MSB of the 16-bit magnetometer data for Z-axis.
1980 ** ------------------------------*/
1981 typedef uint8_t FXOS8700_M_OUT_Z_MSB_t;
1982 
1983 
1984 /*--------------------------------
1985 ** Register: M_OUT_Z_LSB
1986 ** Enum: FXOS8700_M_OUT_Z_LSB
1987 ** --
1988 ** Offset : 0x38 - LSB of the 16-bit magnetometer data for Z-axis.
1989 ** ------------------------------*/
1990 typedef uint8_t FXOS8700_M_OUT_Z_LSB_t;
1991 
1992 
1993 
1994 /*--------------------------------
1995 ** Register: CMP_X_MSB
1996 ** Enum: FXOS8700_CMP_X_MSB
1997 ** --
1998 ** Offset : 0x39 - Bits [13:8] of integrated X-axis acceleration data.
1999 ** ------------------------------*/
2000 typedef union {
2001  struct {
2002  uint8_t cmp_x : 6;
2003  } b;
2004  uint8_t w;
2005 } FXOS8700_CMP_X_MSB_t;
2006 
2007 
2008 /*
2009 ** CMP_X_MSB - Bit field mask definitions
2010 */
2011 #define FXOS8700_CMP_X_MSB_CMP_X_MASK ((uint8_t) 0x3F)
2012 #define FXOS8700_CMP_X_MSB_CMP_X_SHIFT ((uint8_t) 0)
2013 
2014 
2015 /*------------------------------*/
2016 
2017 
2018 
2019 /*--------------------------------
2020 ** Register: CMP_X_LSB
2021 ** Enum: FXOS8700_CMP_X_LSB
2022 ** --
2023 ** Offset : 0x3A - Bits [7:0] of integrated X-axis acceleration data.
2024 ** ------------------------------*/
2025 typedef uint8_t FXOS8700_CMP_X_LSB_t;
2026 
2027 
2028 /*--------------------------------
2029 ** Register: CMP_Y_MSB
2030 ** Enum: FXOS8700_CMP_Y_MSB
2031 ** --
2032 ** Offset : 0x3B - Bits [13:8] of integrated Y-axis acceleration data.
2033 ** ------------------------------*/
2034 typedef union {
2035  struct {
2036  uint8_t cmp_y : 6;
2037  } b;
2038  uint8_t w;
2039 } FXOS8700_CMP_Y_MSB_t;
2040 
2041 
2042 /*
2043 ** CMP_Y_MSB - Bit field mask definitions
2044 */
2045 #define FXOS8700_CMP_Y_MSB_CMP_Y_MASK ((uint8_t) 0x3F)
2046 #define FXOS8700_CMP_Y_MSB_CMP_Y_SHIFT ((uint8_t) 0)
2047 
2048 
2049 /*------------------------------*/
2050 
2051 
2052 
2053 /*--------------------------------
2054 ** Register: CMP_Y_LSB
2055 ** Enum: FXOS8700_CMP_Y_LSB
2056 ** --
2057 ** Offset : 0x3C - Bits [7:0] of integrated Y-axis acceleration data.
2058 ** ------------------------------*/
2059 typedef uint8_t FXOS8700_CMP_Y_LSB_t;
2060 
2061 
2062 /*--------------------------------
2063 ** Register: CMP_Z_MSB
2064 ** Enum: FXOS8700_CMP_Z_MSB
2065 ** --
2066 ** Offset : 0x3D - Bits [13:8] of integrated Z-axis acceleration data.
2067 ** ------------------------------*/
2068 typedef union {
2069  struct {
2070  uint8_t cmp_z : 6;
2071  } b;
2072  uint8_t w;
2073 } FXOS8700_CMP_Z_MSB_t;
2074 
2075 
2076 /*
2077 ** CMP_Z_MSB - Bit field mask definitions
2078 */
2079 #define FXOS8700_CMP_Z_MSB_CMP_Z_MASK ((uint8_t) 0x3F)
2080 #define FXOS8700_CMP_Z_MSB_CMP_Z_SHIFT ((uint8_t) 0)
2081 
2082 
2083 /*------------------------------*/
2084 
2085 
2086 
2087 /*--------------------------------
2088 ** Register: CMP_Z_LSB
2089 ** Enum: FXOS8700_CMP_Z_LSB
2090 ** --
2091 ** Offset : 0x3E - Bits [7:0] of integrated Z-axis acceleration data.
2092 ** ------------------------------*/
2093 typedef uint8_t FXOS8700_CMP_Z_LSB_t;
2094 
2095 
2096 /*--------------------------------
2097 ** Register: M_OFF_X_MSB
2098 ** Enum: FXOS8700_M_OFF_X_MSB
2099 ** --
2100 ** Offset : 0x3F - MSB of magnetometer X-axis offset.
2101 ** ------------------------------*/
2102 typedef uint8_t FXOS8700_M_OFF_X_MSB_t;
2103 
2104 
2105 /*--------------------------------
2106 ** Register: M_OFF_X_LSB
2107 ** Enum: FXOS8700_M_OFF_X_LSB
2108 ** --
2109 ** Offset : 0x40 - LSB of magnetometer X-axis offset.
2110 ** ------------------------------*/
2111 typedef union {
2112  struct {
2113  uint8_t _reserved_ : 1;
2114  uint8_t m_off_x : 7;
2115  } b;
2116  uint8_t w;
2117 } FXOS8700_M_OFF_X_LSB_t;
2118 
2119 
2120 /*
2121 ** M_OFF_X_LSB - Bit field mask definitions
2122 */
2123 #define FXOS8700_M_OFF_X_LSB_M_OFF_X_MASK ((uint8_t) 0xFE)
2124 #define FXOS8700_M_OFF_X_LSB_M_OFF_X_SHIFT ((uint8_t) 1)
2125 
2126 
2127 /*------------------------------*/
2128 
2129 
2130 
2131 /*--------------------------------
2132 ** Register: M_OFF_Y_MSB
2133 ** Enum: FXOS8700_M_OFF_Y_MSB
2134 ** --
2135 ** Offset : 0x41 - MSB of magnetometer Y-axis offset.
2136 ** ------------------------------*/
2137 typedef uint8_t FXOS8700_M_OFF_Y_MSB_t;
2138 
2139 
2140 /*--------------------------------
2141 ** Register: M_OFF_Y_LSB
2142 ** Enum: FXOS8700_M_OFF_Y_LSB
2143 ** --
2144 ** Offset : 0x42 - LSB of magnetometer Y-axis offset.
2145 ** ------------------------------*/
2146 typedef union {
2147  struct {
2148  uint8_t _reserved_ : 1;
2149  uint8_t m_off_y : 7;
2150  } b;
2151  uint8_t w;
2152 } FXOS8700_M_OFF_Y_LSB_t;
2153 
2154 
2155 /*
2156 ** M_OFF_Y_LSB - Bit field mask definitions
2157 */
2158 #define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_MASK ((uint8_t) 0xFE)
2159 #define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_SHIFT ((uint8_t) 1)
2160 
2161 
2162 /*------------------------------*/
2163 
2164 
2165 
2166 /*--------------------------------
2167 ** Register: M_OFF_Z_MSB
2168 ** Enum: FXOS8700_M_OFF_Z_MSB
2169 ** --
2170 ** Offset : 0x43 - MSB of magnetometer Z-axis offset.
2171 ** ------------------------------*/
2172 typedef uint8_t FXOS8700_M_OFF_Z_MSB_t;
2173 
2174 
2175 /*--------------------------------
2176 ** Register: M_OFF_Z_LSB
2177 ** Enum: FXOS8700_M_OFF_Z_LSB
2178 ** --
2179 ** Offset : 0x44 - LSB of magnetometer Z-axis offset.
2180 ** ------------------------------*/
2181 typedef union {
2182  struct {
2183  uint8_t _reserved_ : 1;
2184  uint8_t m_off_z : 7;
2185  } b;
2186  uint8_t w;
2187 } FXOS8700_M_OFF_Z_LSB_t;
2188 
2189 
2190 /*
2191 ** M_OFF_Z_LSB - Bit field mask definitions
2192 */
2193 #define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_MASK ((uint8_t) 0xFE)
2194 #define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_SHIFT ((uint8_t) 1)
2195 
2196 
2197 /*------------------------------*/
2198 
2199 
2200 
2201 /*--------------------------------
2202 ** Register: MAX_X_MSB
2203 ** Enum: FXOS8700_MAX_X_MSB
2204 ** --
2205 ** Offset : 0x45 - Magnetometer X-axis maximum value MSB.
2206 ** ------------------------------*/
2207 typedef uint8_t FXOS8700_MAX_X_MSB_t;
2208 
2209 
2210 /*--------------------------------
2211 ** Register: MAX_X_LSB
2212 ** Enum: FXOS8700_MAX_X_LSB
2213 ** --
2214 ** Offset : 0x46 - Magnetometer X-axis maximum value LSB.
2215 ** ------------------------------*/
2216 typedef uint8_t FXOS8700_MAX_X_LSB_t;
2217 
2218 
2219 /*--------------------------------
2220 ** Register: MAX_Y_MSB
2221 ** Enum: FXOS8700_MAX_Y_MSB
2222 ** --
2223 ** Offset : 0x47 - Magnetometer Y-axis maximum value MSB.
2224 ** ------------------------------*/
2225 typedef uint8_t FXOS8700_MAX_Y_MSB_t;
2226 
2227 
2228 /*--------------------------------
2229 ** Register: MAX_Y_LSB
2230 ** Enum: FXOS8700_MAX_Y_LSB
2231 ** --
2232 ** Offset : 0x48 - Magnetometer Y-axis maximum value LSB.
2233 ** ------------------------------*/
2234 typedef uint8_t FXOS8700_MAX_Y_LSB_t;
2235 
2236 
2237 /*--------------------------------
2238 ** Register: MAX_Z_MSB
2239 ** Enum: FXOS8700_MAX_Z_MSB
2240 ** --
2241 ** Offset : 0x49 - Magnetometer Z-axis maximum value MSB.
2242 ** ------------------------------*/
2243 typedef uint8_t FXOS8700_MAX_Z_MSB_t;
2244 
2245 
2246 /*--------------------------------
2247 ** Register: MAX_Z_LSB
2248 ** Enum: FXOS8700_MAX_Z_LSB
2249 ** --
2250 ** Offset : 0x4A - Magnetometer Z-axis maximum value LSB.
2251 ** ------------------------------*/
2252 typedef uint8_t FXOS8700_MAX_Z_LSB_t;
2253 
2254 
2255 /*--------------------------------
2256 ** Register: MIN_X_MSB
2257 ** Enum: FXOS8700_MIN_X_MSB
2258 ** --
2259 ** Offset : 0x4B - Magnetometer X-axis minimum value MSB.
2260 ** ------------------------------*/
2261 typedef uint8_t FXOS8700_MIN_X_MSB_t;
2262 
2263 
2264 /*--------------------------------
2265 ** Register: MIN_X_LSB
2266 ** Enum: FXOS8700_MIN_X_LSB
2267 ** --
2268 ** Offset : 0x4C - Magnetometer X-axis minimum value LSB.
2269 ** ------------------------------*/
2270 typedef uint8_t FXOS8700_MIN_X_LSB_t;
2271 
2272 
2273 /*--------------------------------
2274 ** Register: MIN_Y_MSB
2275 ** Enum: FXOS8700_MIN_Y_MSB
2276 ** --
2277 ** Offset : 0x4D - Magnetometer Y-axis minimum value MSB.
2278 ** ------------------------------*/
2279 typedef uint8_t FXOS8700_MIN_Y_MSB_t;
2280 
2281 
2282 /*--------------------------------
2283 ** Register: MIN_Y_LSB
2284 ** Enum: FXOS8700_MIN_Y_LSB
2285 ** --
2286 ** Offset : 0x4E - Magnetometer Y-axis minimum value LSB.
2287 ** ------------------------------*/
2288 typedef uint8_t FXOS8700_MIN_Y_LSB_t;
2289 
2290 
2291 /*--------------------------------
2292 ** Register: MIN_Z_MSB
2293 ** Enum: FXOS8700_MIN_Z_MSB
2294 ** --
2295 ** Offset : 0x4F - Magnetometer Z-axis minimum value MSB.
2296 ** ------------------------------*/
2297 typedef uint8_t FXOS8700_MIN_Z_MSB_t;
2298 
2299 
2300 /*--------------------------------
2301 ** Register: MIN_Z_LSB
2302 ** Enum: FXOS8700_MIN_Z_LSB
2303 ** --
2304 ** Offset : 0x50 - Magnetometer Z-axis minimum value LSB.
2305 ** ------------------------------*/
2306 typedef uint8_t FXOS8700_MIN_Z_LSB_t;
2307 
2308 
2309 
2310 /*--------------------------------
2311 ** Register: TEMP
2312 ** Enum: FXOS8700_TEMP
2313 ** --
2314 ** Offset : 0x51 - Device temperature with a valid range of -128 to 127 degrees C.
2315 ** ------------------------------*/
2316 typedef union {
2317  struct {
2318  uint8_t die_temperature;
2319  } b;
2320  uint8_t w;
2321 } FXOS8700_TEMP_t;
2322 
2323 
2324 /*
2325 ** TEMP - Bit field mask definitions
2326 */
2327 #define FXOS8700_TEMP_DIE_TEMPERATURE_MASK ((uint8_t) 0xFF)
2328 #define FXOS8700_TEMP_DIE_TEMPERATURE_SHIFT ((uint8_t) 0)
2329 
2330 
2331 /*------------------------------*/
2332 
2333 
2334 
2335 /*--------------------------------
2336 ** Register: M_THS_CFG
2337 ** Enum: FXOS8700_M_THS_CFG
2338 ** --
2339 ** Offset : 0x52 - Magnetic threshold detection function configuration.
2340 ** ------------------------------*/
2341 typedef union {
2342  struct {
2343  uint8_t m_ths_int_cfg : 1;
2344  uint8_t m_ths_int_en : 1;
2345  uint8_t m_ths_wake_en : 1;
2346  uint8_t m_ths_xefe : 1;
2347  uint8_t m_ths_yefe : 1;
2348  uint8_t m_ths_zefe : 1;
2349  uint8_t m_ths_oae : 1;
2350  uint8_t m_ths_ele : 1;
2351  } b;
2352  uint8_t w;
2353 } FXOS8700_M_THS_CFG_t;
2354 
2355 
2356 /*
2357 ** M_THS_CFG - Bit field mask definitions
2358 */
2359 #define FXOS8700_M_THS_CFG_M_THS_INT_CFG_MASK ((uint8_t) 0x01)
2360 #define FXOS8700_M_THS_CFG_M_THS_INT_CFG_SHIFT ((uint8_t) 0)
2361 
2362 #define FXOS8700_M_THS_CFG_M_THS_INT_EN_MASK ((uint8_t) 0x02)
2363 #define FXOS8700_M_THS_CFG_M_THS_INT_EN_SHIFT ((uint8_t) 1)
2364 
2365 #define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_MASK ((uint8_t) 0x04)
2366 #define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_SHIFT ((uint8_t) 2)
2367 
2368 #define FXOS8700_M_THS_CFG_M_THS_XEFE_MASK ((uint8_t) 0x08)
2369 #define FXOS8700_M_THS_CFG_M_THS_XEFE_SHIFT ((uint8_t) 3)
2370 
2371 #define FXOS8700_M_THS_CFG_M_THS_YEFE_MASK ((uint8_t) 0x10)
2372 #define FXOS8700_M_THS_CFG_M_THS_YEFE_SHIFT ((uint8_t) 4)
2373 
2374 #define FXOS8700_M_THS_CFG_M_THS_ZEFE_MASK ((uint8_t) 0x20)
2375 #define FXOS8700_M_THS_CFG_M_THS_ZEFE_SHIFT ((uint8_t) 5)
2376 
2377 #define FXOS8700_M_THS_CFG_M_THS_OAE_MASK ((uint8_t) 0x40)
2378 #define FXOS8700_M_THS_CFG_M_THS_OAE_SHIFT ((uint8_t) 6)
2379 
2380 #define FXOS8700_M_THS_CFG_M_THS_ELE_MASK ((uint8_t) 0x80)
2381 #define FXOS8700_M_THS_CFG_M_THS_ELE_SHIFT ((uint8_t) 7)
2382 
2383 
2384 /*------------------------------*/
2385 
2386 
2387 
2388 /*--------------------------------
2389 ** Register: M_THS_SRC
2390 ** Enum: FXOS8700_M_THS_SRC
2391 ** --
2392 ** Offset : 0x53 - Magnetic threshold event source register.
2393 ** ------------------------------*/
2394 typedef union {
2395  struct {
2396  uint8_t m_ths_xhp : 1;
2397  uint8_t m_ths_xhe : 1;
2398  uint8_t m_ths_yhp : 1;
2399  uint8_t m_ths_yhe : 1;
2400  uint8_t m_ths_zhp : 1;
2401  uint8_t m_ths_zhe : 1;
2402  uint8_t _reserved_ : 1;
2403  uint8_t m_ths_ea : 1;
2404  } b;
2405  uint8_t w;
2406 } FXOS8700_M_THS_SRC_t;
2407 
2408 
2409 /*
2410 ** M_THS_SRC - Bit field mask definitions
2411 */
2412 #define FXOS8700_M_THS_SRC_M_THS_XHP_MASK ((uint8_t) 0x01)
2413 #define FXOS8700_M_THS_SRC_M_THS_XHP_SHIFT ((uint8_t) 0)
2414 
2415 #define FXOS8700_M_THS_SRC_M_THS_XHE_MASK ((uint8_t) 0x02)
2416 #define FXOS8700_M_THS_SRC_M_THS_XHE_SHIFT ((uint8_t) 1)
2417 
2418 #define FXOS8700_M_THS_SRC_M_THS_YHP_MASK ((uint8_t) 0x04)
2419 #define FXOS8700_M_THS_SRC_M_THS_YHP_SHIFT ((uint8_t) 2)
2420 
2421 #define FXOS8700_M_THS_SRC_M_THS_YHE_MASK ((uint8_t) 0x08)
2422 #define FXOS8700_M_THS_SRC_M_THS_YHE_SHIFT ((uint8_t) 3)
2423 
2424 #define FXOS8700_M_THS_SRC_M_THS_ZHP_MASK ((uint8_t) 0x10)
2425 #define FXOS8700_M_THS_SRC_M_THS_ZHP_SHIFT ((uint8_t) 4)
2426 
2427 #define FXOS8700_M_THS_SRC_M_THS_ZHE_MASK ((uint8_t) 0x20)
2428 #define FXOS8700_M_THS_SRC_M_THS_ZHE_SHIFT ((uint8_t) 5)
2429 
2430 #define FXOS8700_M_THS_SRC_M_THS_EA_MASK ((uint8_t) 0x80)
2431 #define FXOS8700_M_THS_SRC_M_THS_EA_SHIFT ((uint8_t) 7)
2432 
2433 
2434 /*------------------------------*/
2435 
2436 
2437 
2438 /*--------------------------------
2439 ** Register: M_THS_X_MSB
2440 ** Enum: FXOS8700_M_THS_X_MSB
2441 ** --
2442 ** Offset : 0x54 - X-axis magnetic threshold MSB.
2443 ** ------------------------------*/
2444 typedef union {
2445  struct {
2446  uint8_t m_ths_x : 7;
2447  } b;
2448  uint8_t w;
2449 } FXOS8700_M_THS_X_MSB_t;
2450 
2451 
2452 /*
2453 ** M_THS_X_MSB - Bit field mask definitions
2454 */
2455 #define FXOS8700_M_THS_X_MSB_M_THS_X_MASK ((uint8_t) 0x7F)
2456 #define FXOS8700_M_THS_X_MSB_M_THS_X_SHIFT ((uint8_t) 0)
2457 
2458 
2459 /*------------------------------*/
2460 
2461 
2462 
2463 /*--------------------------------
2464 ** Register: M_THS_X_LSB
2465 ** Enum: FXOS8700_M_THS_X_LSB
2466 ** --
2467 ** Offset : 0x55 - X-axis magnetic threshold LSB.
2468 ** ------------------------------*/
2469 typedef uint8_t FXOS8700_M_THS_X_LSB_t;
2470 
2471 
2472 /*--------------------------------
2473 ** Register: M_THS_Y_MSB
2474 ** Enum: FXOS8700_M_THS_Y_MSB
2475 ** --
2476 ** Offset : 0x56 - Y-axis magnetic threshold MSB.
2477 ** ------------------------------*/
2478 typedef union {
2479  struct {
2480  uint8_t m_ths_y : 7;
2481  } b;
2482  uint8_t w;
2483 } FXOS8700_M_THS_Y_MSB_t;
2484 
2485 
2486 /*
2487 ** M_THS_Y_MSB - Bit field mask definitions
2488 */
2489 #define FXOS8700_M_THS_Y_MSB_M_THS_Y_MASK ((uint8_t) 0x7F)
2490 #define FXOS8700_M_THS_Y_MSB_M_THS_Y_SHIFT ((uint8_t) 0)
2491 
2492 
2493 /*------------------------------*/
2494 
2495 
2496 
2497 /*--------------------------------
2498 ** Register: M_THS_Y_LSB
2499 ** Enum: FXOS8700_M_THS_Y_LSB
2500 ** --
2501 ** Offset : 0x57 - Y-axis magnetic threshold LSB.
2502 ** ------------------------------*/
2503 typedef uint8_t FXOS8700_M_THS_Y_LSB_t;
2504 
2505 
2506 /*--------------------------------
2507 ** Register: M_THS_Z_MSB
2508 ** Enum: FXOS8700_M_THS_Z_MSB
2509 ** --
2510 ** Offset : 0x58 - Z-axis magnetic threshold MSB.
2511 ** ------------------------------*/
2512 typedef union {
2513  struct {
2514  uint8_t m_ths_z : 7;
2515  } b;
2516  uint8_t w;
2517 } FXOS8700_M_THS_Z_MSB_t;
2518 
2519 
2520 /*
2521 ** M_THS_Z_MSB - Bit field mask definitions
2522 */
2523 #define FXOS8700_M_THS_Z_MSB_M_THS_Z_MASK ((uint8_t) 0x7F)
2524 #define FXOS8700_M_THS_Z_MSB_M_THS_Z_SHIFT ((uint8_t) 0)
2525 
2526 
2527 /*------------------------------*/
2528 
2529 
2530 
2531 /*--------------------------------
2532 ** Register: M_THS_Z_LSB
2533 ** Enum: FXOS8700_M_THS_Z_LSB
2534 ** --
2535 ** Offset : 0x59 - Z-axis magnetic threshold LSB.
2536 ** ------------------------------*/
2537 typedef uint8_t FXOS8700_M_THS_Z_LSB_t;
2538 
2539 
2540 /*--------------------------------
2541 ** Register: M_THS_COUNT
2542 ** Enum: FXOS8700_M_THS_COUNT
2543 ** --
2544 ** Offset : 0x5A - Magnetic threshold debounce counter.
2545 ** ------------------------------*/
2546 typedef uint8_t FXOS8700_M_THS_COUNT_t;
2547 
2548 
2549 
2550 /*--------------------------------
2551 ** Register: M_CTRL_REG1
2552 ** Enum: FXOS8700_M_CTRL_REG1
2553 ** --
2554 ** Offset : 0x5B - Control for magnetometer sensor functions.
2555 ** ------------------------------*/
2556 typedef union {
2557  struct {
2558  uint8_t m_hms : 2;
2559  uint8_t m_os : 3; /* M-cell oversample ratio */
2560 
2561  uint8_t m_ost : 1; /* One-shot triggered magnetic measurement mode: */
2562 
2563  uint8_t m_rst : 1;
2564  uint8_t m_acal : 1;
2565  } b;
2566  uint8_t w;
2567 } FXOS8700_M_CTRL_REG1_t;
2568 
2569 
2570 /*
2571 ** M_CTRL_REG1 - Bit field mask definitions
2572 */
2573 #define FXOS8700_M_CTRL_REG1_M_HMS_MASK ((uint8_t) 0x03)
2574 #define FXOS8700_M_CTRL_REG1_M_HMS_SHIFT ((uint8_t) 0)
2575 
2576 #define FXOS8700_M_CTRL_REG1_M_OS_MASK ((uint8_t) 0x1C)
2577 #define FXOS8700_M_CTRL_REG1_M_OS_SHIFT ((uint8_t) 2)
2578 
2579 #define FXOS8700_M_CTRL_REG1_M_OST_MASK ((uint8_t) 0x20)
2580 #define FXOS8700_M_CTRL_REG1_M_OST_SHIFT ((uint8_t) 5)
2581 
2582 #define FXOS8700_M_CTRL_REG1_M_RST_MASK ((uint8_t) 0x40)
2583 #define FXOS8700_M_CTRL_REG1_M_RST_SHIFT ((uint8_t) 6)
2584 
2585 #define FXOS8700_M_CTRL_REG1_M_ACAL_MASK ((uint8_t) 0x80)
2586 #define FXOS8700_M_CTRL_REG1_M_ACAL_SHIFT ((uint8_t) 7)
2587 
2588 
2589 /*
2590 ** M_CTRL_REG1 - Bit field value definitions
2591 */
2592 #define FXOS8700_M_CTRL_REG1_M_ACAL_EN ((uint8_t) 0x80) /* Auto-calibration feature enabled */
2593 #define FXOS8700_M_CTRL_REG1_M_ACAL_DISABLE ((uint8_t) 0x00) /* Auto-calibration feature disabled */
2594 #define FXOS8700_M_CTRL_REG1_M_RST_EN ((uint8_t) 0x40) /* One-shot magnetic sensor reset enabled, hw */
2595  /* cleared when complete */
2596 #define FXOS8700_M_CTRL_REG1_M_RST_DISABLE ((uint8_t) 0x00) /* No magnetic sensor reset active */
2597 #define FXOS8700_M_CTRL_REG1_M_OST_EN ((uint8_t) 0x20) /* If device is in Active mode no action is taken. */
2598  /* If device is in Standby mode, take one set of */
2599  /* magnetic measurements, clear this bit, and */
2600  /* return to Standby mode. */
2601 #define FXOS8700_M_CTRL_REG1_M_OST_DISABLE ((uint8_t) 0x00) /* No action taken, or one-shot measurement */
2602  /* complete */
2603 #define FXOS8700_M_CTRL_REG1_M_OS_OSR0 ((uint8_t) 0x00) /* 1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2, */
2604  /* 400=2, 800=2 */
2605 #define FXOS8700_M_CTRL_REG1_M_OS_OSR1 ((uint8_t) 0x04) /* 1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2, */
2606  /* 400=2, 800=2 */
2607 #define FXOS8700_M_CTRL_REG1_M_OS_OSR2 ((uint8_t) 0x08) /* 1.56=32, 6.25=8, 12.5=4, 50=2, 100=2, 200=2, */
2608  /* 400=2, 800=2 */
2609 #define FXOS8700_M_CTRL_REG1_M_OS_OSR3 ((uint8_t) 0x0c) /* 1.56=64, 6.25=16, 12.5=8, 50=2, 100=2, 200=2, */
2610  /* 400=2, 800=2 */
2611 #define FXOS8700_M_CTRL_REG1_M_OS_OSR4 ((uint8_t) 0x10) /* 1.56=128, 6.25=32, 12.5=16, 50=4, 100=2, 200=2, */
2612  /* 400=2, 800=2 */
2613 #define FXOS8700_M_CTRL_REG1_M_OS_OSR5 ((uint8_t) 0x14) /* 1.56=256, 6.25=64, 12.5=32, 50=8, 100=4, 200=2, */
2614  /* 400=2, 800=2 */
2615 #define FXOS8700_M_CTRL_REG1_M_OS_OSR6 ((uint8_t) 0x18) /* 1.56=512, 6.25=128, 12.5=64, 50=16, 100=8, */
2616  /* 200=4, 400=2, 800=2 */
2617 #define FXOS8700_M_CTRL_REG1_M_OS_OSR7 ((uint8_t) 0x1c) /* 1.56=1024, 6.25=256, 12.5=128, 50=32, 100=16, */
2618  /* 200=8, 400=4, 800=2 */
2619 #define FXOS8700_M_CTRL_REG1_M_HMS_ACCEL_ONLY ((uint8_t) 0x00) /* 0b00 = Only accelerometer sensor is active */
2620 #define FXOS8700_M_CTRL_REG1_M_HMS_MAG_ONLY ((uint8_t) 0x01) /* 0b01 = Only magnetometer sensor is active */
2621 #define FXOS8700_M_CTRL_REG1_M_HMS_HYBRID_MODE ((uint8_t) 0x03) /* 0b11 = Hybrid mode, both accelerometer and */
2622  /* magnetometer sensors are active */
2623 /*------------------------------*/
2624 
2625 
2626 
2627 /*--------------------------------
2628 ** Register: M_CTRL_REG2
2629 ** Enum: FXOS8700_M_CTRL_REG2
2630 ** --
2631 ** Offset : 0x5C - Control for magnetometer sensor functions.
2632 ** ------------------------------*/
2633 typedef union {
2634  struct {
2635  uint8_t m_rst_cnt : 2;
2636  uint8_t m_maxmin_rst : 1;
2637  uint8_t m_maxmin_dis_ths : 1;
2638  uint8_t m_maxmin_dis : 1;
2639  uint8_t m_autoinc : 1;
2640  } b;
2641  uint8_t w;
2642 } FXOS8700_M_CTRL_REG2_t;
2643 
2644 
2645 /*
2646 ** M_CTRL_REG2 - Bit field mask definitions
2647 */
2648 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_MASK ((uint8_t) 0x03)
2649 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_SHIFT ((uint8_t) 0)
2650 
2651 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_MASK ((uint8_t) 0x04)
2652 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SHIFT ((uint8_t) 2)
2653 
2654 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_MASK ((uint8_t) 0x08)
2655 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_SHIFT ((uint8_t) 3)
2656 
2657 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_MASK ((uint8_t) 0x10)
2658 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_SHIFT ((uint8_t) 4)
2659 
2660 #define FXOS8700_M_CTRL_REG2_M_AUTOINC_MASK ((uint8_t) 0x20)
2661 #define FXOS8700_M_CTRL_REG2_M_AUTOINC_SHIFT ((uint8_t) 5)
2662 
2663 
2664 /*
2665 ** M_CTRL_REG2 - Bit field value definitions
2666 */
2667 #define FXOS8700_M_CTRL_REG2_M_AUTOINC_HYBRID_MODE ((uint8_t) 0x20) /* With hyb_autoinc_mode = 1 and fast-read mode is */
2668  /* disabled (CTRL_REG1 [f_read] = 0), the register */
2669  /* address will automatically advance to register */
2670  /* x33 (M_OUT_X_MSB) after reading register x06 */
2671  /* (OUT_Z_LSB) in burst-read mode. */
2672  /* For hyb_autoinc_mode = 1 and fast read mode */
2673  /* enabled (CTRL_REG1[f_read = 1) the register */
2674  /* address will automatically advance to register */
2675  /* x33 (M_OUT_X_MSB) after reading register x05 */
2676  /* (OUT_Z_MSB) during a burstread mode. Please */
2677  /* refer to the register map auto-increment address */
2678  /* column for further information. */
2679 #define FXOS8700_M_CTRL_REG2_M_AUTOINC_ACCEL_ONLY_MODE ((uint8_t) 0x00) /* hyb_autoinc_mode = 0 */
2680 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_DIS ((uint8_t) 0x00) /* Magnetic min/max detection function is enabled */
2681 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_EN ((uint8_t) 0x10) /* Magnetic min/max detection function is disabled */
2682 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_DIS ((uint8_t) 0x00) /* No impact to magnetic min/max detection function */
2683  /* on a magnetic threshold event */
2684 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_EN ((uint8_t) 0x08) /* Magnetic min/max detection function is disabled */
2685  /* when magnetic threshold event is triggered */
2686 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_NO_SEQUENCE ((uint8_t) 0x00) /* No reset sequence is active */
2687 #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SET ((uint8_t) 0x04) /* Setting this bit resets the MIN_X/Y/Z and */
2688  /* MAX_X/Y/Z registers to 0x7FFF and 0x8000 */
2689 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY1 ((uint8_t) 0x00) /* Automatic magnetic reset at the beginning of */
2690  /* each ODR cycle (default). */
2691 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY16 ((uint8_t) 0x01) /* Automatic magnetic reset every 16 ODR cycles */
2692 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY512 ((uint8_t) 0x02) /* Automatic magnetic reset every 512 ODR cycles */
2693 #define FXOS8700_M_CTRL_REG2_M_RST_CNT_DISABLE ((uint8_t) 0x03) /* Automatic magnetic reset is disabled. Magnetic */
2694  /* reset only occurs automatically on a transition */
2695  /* from Standby to Active mode, or can be triggered */
2696  /* manually by setting M_CTRL_REG1[m_rst] = 1 */
2697 /*------------------------------*/
2698 
2699 
2700 
2701 
2702 /*--------------------------------
2703 ** Register: M_CTRL_REG3
2704 ** Enum: FXOS8700_M_CTRL_REG3
2705 ** --
2706 ** Offset : 0x5D - Control for magnetometer sensor functions.
2707 ** ------------------------------*/
2708 typedef union {
2709  struct {
2710  uint8_t m_st_xy : 2;
2711  uint8_t m_st_z : 1;
2712  uint8_t m_ths_xyz_update : 1;
2713  uint8_t m_aslp_os : 3;
2714  uint8_t m_raw : 1;
2715  } b;
2716  uint8_t w;
2717 } FXOS8700_M_CTRL_REG3_t;
2718 
2719 
2720 /*
2721 ** M_CTRL_REG3 - Bit field mask definitions
2722 */
2723 #define FXOS8700_M_CTRL_REG3_M_ST_XY_MASK ((uint8_t) 0x03)
2724 #define FXOS8700_M_CTRL_REG3_M_ST_XY_SHIFT ((uint8_t) 0)
2725 
2726 #define FXOS8700_M_CTRL_REG3_M_ST_Z_MASK ((uint8_t) 0x04)
2727 #define FXOS8700_M_CTRL_REG3_M_ST_Z_SHIFT ((uint8_t) 2)
2728 
2729 #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_MASK ((uint8_t) 0x08)
2730 #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_SHIFT ((uint8_t) 3)
2731 
2732 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_MASK ((uint8_t) 0x70)
2733 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_SHIFT ((uint8_t) 4)
2734 
2735 #define FXOS8700_M_CTRL_REG3_M_RAW_MASK ((uint8_t) 0x80)
2736 #define FXOS8700_M_CTRL_REG3_M_RAW_SHIFT ((uint8_t) 7)
2737 
2738 
2739 /*
2740 ** M_CTRL_REG3 - Bit field value definitions
2741 */
2742 #define FXOS8700_M_CTRL_REG3_M_RAW_EN ((uint8_t) 0x80) /* Values stored in the M_OFF_X/Y/Z registers are */
2743  /* applied to the magnetic sample data */
2744 #define FXOS8700_M_CTRL_REG3_M_RAW_DIS ((uint8_t) 0x00) /* Values stored in M_OFF_X/Y/Z are not applied to */
2745  /* the magnetic sample data */
2746 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_0 ((uint8_t) 0x00) /* OSR 0 look at table 203 */
2747 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_1 ((uint8_t) 0x10) /* OSR 1 look at table 203 */
2748 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_2 ((uint8_t) 0x20) /* OSR 2 look at table 203 */
2749 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_3 ((uint8_t) 0x30) /* OSR 3 look at table 203 */
2750 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_4 ((uint8_t) 0x40) /* OSR 4 look at table 203 */
2751 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_5 ((uint8_t) 0x50) /* OSR 5 look at table 203 */
2752 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_6 ((uint8_t) 0x60) /* OSR 6 look at table 203 */
2753 #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_7 ((uint8_t) 0x70) /* OSR look at table 203 */
2754 #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_EN ((uint8_t) 0x08) /* Only the reference value for the axis that */
2755  /* triggered the detection event is updated */
2756 #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_DIS ((uint8_t) 0x00) /* X, Y and Z reference values are all updated when */
2757  /* the function triggers on any of the X, Y, or Z */
2758  /* axes */
2759 /*------------------------------*/
2760 
2761 
2762 
2763 /*--------------------------------
2764 ** Register: M_INT_SRC
2765 ** Enum: FXOS8700_M_INT_SRC
2766 ** --
2767 ** Offset : 0x5E - Magnetometer interrupt source.
2768 ** ------------------------------*/
2769 typedef union {
2770  struct {
2771  uint8_t src_m_drdy : 1;
2772  uint8_t src_m_vecm : 1;
2773  uint8_t src_m_ths : 1;
2774  } b;
2775  uint8_t w;
2776 } FXOS8700_M_INT_SRC_t;
2777 
2778 
2779 /*
2780 ** M_INT_SRC - Bit field mask definitions
2781 */
2782 #define FXOS8700_M_INT_SRC_SRC_M_DRDY_MASK ((uint8_t) 0x01)
2783 #define FXOS8700_M_INT_SRC_SRC_M_DRDY_SHIFT ((uint8_t) 0)
2784 
2785 #define FXOS8700_M_INT_SRC_SRC_M_VECM_MASK ((uint8_t) 0x02)
2786 #define FXOS8700_M_INT_SRC_SRC_M_VECM_SHIFT ((uint8_t) 1)
2787 
2788 #define FXOS8700_M_INT_SRC_SRC_M_THS_MASK ((uint8_t) 0x04)
2789 #define FXOS8700_M_INT_SRC_SRC_M_THS_SHIFT ((uint8_t) 2)
2790 
2791 
2792 /*------------------------------*/
2793 
2794 
2795 
2796 /*--------------------------------
2797 ** Register: A_VECM_CFG
2798 ** Enum: FXOS8700_A_VECM_CFG
2799 ** --
2800 ** Offset : 0x5F - Acceleration vector magnitude configuration register.
2801 ** ------------------------------*/
2802 typedef union {
2803  struct {
2804  uint8_t _reserved_ : 4;
2805  uint8_t a_vecm_updm : 1;
2806  uint8_t a_vecm_initm : 1;
2807  uint8_t a_vecm_ele : 1;
2808  uint8_t a_vecm_en : 1;
2809  } b;
2810  uint8_t w;
2811 } FXOS8700_A_VECM_CFG_t;
2812 
2813 
2814 /*
2815 ** A_VECM_CFG - Bit field mask definitions
2816 */
2817 #define FXOS8700_A_VECM_CFG_A_VECM_UPDM_MASK ((uint8_t) 0x10)
2818 #define FXOS8700_A_VECM_CFG_A_VECM_UPDM_SHIFT ((uint8_t) 4)
2819 
2820 #define FXOS8700_A_VECM_CFG_A_VECM_INITM_MASK ((uint8_t) 0x20)
2821 #define FXOS8700_A_VECM_CFG_A_VECM_INITM_SHIFT ((uint8_t) 5)
2822 
2823 #define FXOS8700_A_VECM_CFG_A_VECM_ELE_MASK ((uint8_t) 0x40)
2824 #define FXOS8700_A_VECM_CFG_A_VECM_ELE_SHIFT ((uint8_t) 6)
2825 
2826 #define FXOS8700_A_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x80)
2827 #define FXOS8700_A_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 7)
2828 
2829 
2830 /*------------------------------*/
2831 
2832 
2833 
2834 /*--------------------------------
2835 ** Register: A_VECM_THS_MSB
2836 ** Enum: FXOS8700_A_VECM_THS_MSB
2837 ** --
2838 ** Offset : 0x60 - Acceleration vector magnitude threshold MSB.
2839 ** ------------------------------*/
2840 typedef union {
2841  struct {
2842  uint8_t a_vbecm_ths : 5;
2843  uint8_t _reserved_ : 2;
2844  uint8_t a_vbecm_dbcntm : 1;
2845  } b;
2846  uint8_t w;
2847 } FXOS8700_A_VECM_THS_MSB_t;
2848 
2849 
2850 /*
2851 ** A_VECM_THS_MSB - Bit field mask definitions
2852 */
2853 #define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_MASK ((uint8_t) 0x1F)
2854 #define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_SHIFT ((uint8_t) 0)
2855 
2856 #define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_MASK ((uint8_t) 0x80)
2857 #define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_SHIFT ((uint8_t) 7)
2858 
2859 
2860 /*------------------------------*/
2861 
2862 
2863 
2864 /*--------------------------------
2865 ** Register: A_VECM_THS_LSB
2866 ** Enum: FXOS8700_A_VECM_THS_LSB
2867 ** --
2868 ** Offset : 0x61 - Acceleration vector magnitude threshold LSB.
2869 ** ------------------------------*/
2870 typedef uint8_t FXOS8700_A_VECM_THS_LSB_t;
2871 
2872 
2873 /*--------------------------------
2874 ** Register: A_VECM_CNT
2875 ** Enum: FXOS8700_A_VECM_CNT
2876 ** --
2877 ** Offset : 0x62 - Acceleration vector magnitude debounce count.
2878 ** ------------------------------*/
2879 typedef uint8_t FXOS8700_A_VECM_CNT_t;
2880 
2881 
2882 
2883 /*--------------------------------
2884 ** Register: A_VECM_INITX_MSB
2885 ** Enum: FXOS8700_A_VECM_INITX_MSB
2886 ** --
2887 ** Offset : 0x63 - Acceleration vector magnitude X-axis reference value MSB.
2888 ** ------------------------------*/
2889 typedef union {
2890  struct {
2891  uint8_t a_vecm_initx : 6;
2892  } b;
2893  uint8_t w;
2894 } FXOS8700_A_VECM_INITX_MSB_t;
2895 
2896 
2897 /*
2898 ** A_VECM_INITX_MSB - Bit field mask definitions
2899 */
2900 #define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_MASK ((uint8_t) 0x3F)
2901 #define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_SHIFT ((uint8_t) 0)
2902 
2903 
2904 /*------------------------------*/
2905 
2906 
2907 
2908 /*--------------------------------
2909 ** Register: A_VECM_INITX_LSB
2910 ** Enum: FXOS8700_A_VECM_INITX_LSB
2911 ** --
2912 ** Offset : 0x64 - Acceleration vector magnitude X-axis reference value LSB.
2913 ** ------------------------------*/
2914 typedef uint8_t FXOS8700_A_VECM_INITX_LSB_t;
2915 
2916 
2917 /*--------------------------------
2918 ** Register: A_VECM_INITY_MSB
2919 ** Enum: FXOS8700_A_VECM_INITY_MSB
2920 ** --
2921 ** Offset : 0x65 - Acceleration vector magnitude Y-axis reference value MSB.
2922 ** ------------------------------*/
2923 typedef union {
2924  struct {
2925  uint8_t a_vecm_inity : 6;
2926  } b;
2927  uint8_t w;
2928 } FXOS8700_A_VECM_INITY_MSB_t;
2929 
2930 
2931 /*
2932 ** A_VECM_INITY_MSB - Bit field mask definitions
2933 */
2934 #define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_MASK ((uint8_t) 0x3F)
2935 #define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_SHIFT ((uint8_t) 0)
2936 
2937 
2938 /*------------------------------*/
2939 
2940 
2941 
2942 /*--------------------------------
2943 ** Register: A_VECM_INITY_LSB
2944 ** Enum: FXOS8700_A_VECM_INITY_LSB
2945 ** --
2946 ** Offset : 0x66 - Acceleration vector magnitude Y-axis reference value LSB.
2947 ** ------------------------------*/
2948 typedef uint8_t FXOS8700_A_VECM_INITY_LSB_t;
2949 
2950 
2951 /*--------------------------------
2952 ** Register: A_VECM_INITZ_MSB
2953 ** Enum: FXOS8700_A_VECM_INITZ_MSB
2954 ** --
2955 ** Offset : 0x67 - Acceleration vector magnitude Z-axis reference value MSB.
2956 ** ------------------------------*/
2957 typedef union {
2958  struct {
2959  uint8_t a_vecm_initz : 6;
2960  } b;
2961  uint8_t w;
2962 } FXOS8700_A_VECM_INITZ_MSB_t;
2963 
2964 
2965 /*
2966 ** A_VECM_INITZ_MSB - Bit field mask definitions
2967 */
2968 #define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_MASK ((uint8_t) 0x3F)
2969 #define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_SHIFT ((uint8_t) 0)
2970 
2971 
2972 /*------------------------------*/
2973 
2974 
2975 
2976 /*--------------------------------
2977 ** Register: A_VECM_INITZ_LSB
2978 ** Enum: FXOS8700_A_VECM_INITZ_LSB
2979 ** --
2980 ** Offset : 0x68 - Acceleration vector magnitude Z-axis reference value LSB.
2981 ** ------------------------------*/
2982 typedef uint8_t FXOS8700_A_VECM_INITZ_LSB_t;
2983 
2984 
2985 /*--------------------------------
2986 ** Register: M_VECM_CFG
2987 ** Enum: FXOS8700_M_VECM_CFG
2988 ** --
2989 ** Offset : 0x69 - Magnetic vector magnitude configuration register.
2990 ** ------------------------------*/
2991 typedef union {
2992  struct {
2993  uint8_t m_vecm_init_cfg : 1;
2994  uint8_t m_vecm_int_en : 1;
2995  uint8_t m_vecm_wake_en : 1;
2996  uint8_t a_vecm_en : 1;
2997  uint8_t m_vecm_updm : 1;
2998  uint8_t m_vecm_initm : 1;
2999  uint8_t m_vecm_ele : 1;
3000  uint8_t reserved : 1;
3001  } b;
3002  uint8_t w;
3003 } FXOS8700_M_VECM_CFG_t;
3004 
3005 
3006 /*
3007 ** M_VECM_CFG - Bit field mask definitions
3008 */
3009 #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_MASK ((uint8_t) 0x01)
3010 #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_SHIFT ((uint8_t) 0)
3011 
3012 #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_MASK ((uint8_t) 0x02)
3013 #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_SHIFT ((uint8_t) 1)
3014 
3015 #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_MASK ((uint8_t) 0x04)
3016 #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_SHIFT ((uint8_t) 2)
3017 
3018 #define FXOS8700_M_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x08)
3019 #define FXOS8700_M_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 3)
3020 
3021 #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_MASK ((uint8_t) 0x10)
3022 #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_SHIFT ((uint8_t) 4)
3023 
3024 #define FXOS8700_M_VECM_CFG_M_VECM_INITM_MASK ((uint8_t) 0x20)
3025 #define FXOS8700_M_VECM_CFG_M_VECM_INITM_SHIFT ((uint8_t) 5)
3026 
3027 #define FXOS8700_M_VECM_CFG_M_VECM_ELE_MASK ((uint8_t) 0x40)
3028 #define FXOS8700_M_VECM_CFG_M_VECM_ELE_SHIFT ((uint8_t) 6)
3029 
3030 #define FXOS8700_M_VECM_CFG_RESERVED_MASK ((uint8_t) 0x80)
3031 #define FXOS8700_M_VECM_CFG_RESERVED_SHIFT ((uint8_t) 7)
3032 
3033 
3034 /*
3035 ** M_VECM_CFG - Bit field value definitions
3036 */
3037 #define FXOS8700_M_VECM_CFG_M_VECM_ELE_DIS ((uint8_t) 0x00) /* Event latch disabled */
3038 #define FXOS8700_M_VECM_CFG_M_VECM_ELE_EN ((uint8_t) 0x40) /* Event latch enabled */
3039 #define FXOS8700_M_VECM_CFG_M_VECM_INITM_OUT ((uint8_t) 0x00) /* The ASIC uses the current magnetic output data as */
3040  /* the initial reference values at the time the */
3041  /* m_vecm_en bit is set */
3042 #define FXOS8700_M_VECM_CFG_M_VECM_INITM_STORED ((uint8_t) 0x20) /* The ASIC uses the data stored in the */
3043  /* M_VECM_X/Y/Z_INIT registers as the initial */
3044  /* reference values at the time the m_vecm_en bit is */
3045  /* set */
3046 #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_DIS ((uint8_t) 0x00) /* The function updates the reference values with */
3047  /* the current X, Y, and Z magnetic data when the */
3048  /* event is triggered */
3049 #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_EN ((uint8_t) 0x10) /* The function does not update the reference values */
3050  /* when the event is triggered */
3051 #define FXOS8700_M_VECM_CFG_A_VECM_EN_EN ((uint8_t) 0x00) /* Function is disabled */
3052 #define FXOS8700_M_VECM_CFG_A_VECM_EN_DIS ((uint8_t) 0x08) /* Function is enabled */
3053 #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_EN ((uint8_t) 0x00) /* The system excludes the src_m_vecm event flag */
3054  /* when evaluating the auto-sleep function */
3055 #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_DIS ((uint8_t) 0x04) /* The system includes the src_m_vecm event flag */
3056  /* when evaluating the auto-sleep function */
3057 #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_EN ((uint8_t) 0x00) /* Magnetic vector-magnitude interrupt is disabled */
3058 #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_DIS ((uint8_t) 0x02) /* Magnetic vector-magnitude interrupt is enabled */
3059 #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT2 ((uint8_t) 0x00) /* Magnetic vector-magnitude interrupt is output on */
3060  /* INT2 pin */
3061 #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT1 ((uint8_t) 0x01) /* Magnetic vector-magnitude interrupt is output on */
3062  /* INT1 pin. */
3063 #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_DIS ((uint8_t) 0x01) /* Function is enabled */
3064 /*------------------------------*/
3065 
3066 
3067 
3068 /*--------------------------------
3069 ** Register: M_VECM_THS_MSB
3070 ** Enum: FXOS8700_M_VECM_THS_MSB
3071 ** --
3072 ** Offset : 0x6A - Magnetic vector magnitude threshold MSB.
3073 ** ------------------------------*/
3074 typedef union {
3075  struct {
3076  uint8_t m_vecm_ths : 7;
3077  } b;
3078  uint8_t w;
3079 } FXOS8700_M_VECM_THS_MSB_t;
3080 
3081 
3082 /*
3083 ** M_VECM_THS_MSB - Bit field mask definitions
3084 */
3085 #define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_MASK ((uint8_t) 0x7F)
3086 #define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_SHIFT ((uint8_t) 0)
3087 
3088 
3089 /*------------------------------*/
3090 
3091 
3092 
3093 /*--------------------------------
3094 ** Register: M_VECM_THS_LSB
3095 ** Enum: FXOS8700_M_VECM_THS_LSB
3096 ** --
3097 ** Offset : 0x6B - Magnetic vector magnitude threshold LSB.
3098 ** ------------------------------*/
3099 typedef uint8_t FXOS8700_M_VECM_THS_LSB_t;
3100 
3101 
3102 /*--------------------------------
3103 ** Register: M_VECM_CNT
3104 ** Enum: FXOS8700_M_VECM_CNT
3105 ** --
3106 ** Offset : 0x6C - Magnetic vector magnitude debounce count.
3107 ** ------------------------------*/
3108 typedef uint8_t FXOS8700_M_VECM_CNT_t;
3109 
3110 
3111 /*--------------------------------
3112 ** Register: M_VECM_INITX_MSB
3113 ** Enum: FXOS8700_M_VECM_INITX_MSB
3114 ** --
3115 ** Offset : 0x6D - Magnetic vector magnitude X-axis reference value MSB.
3116 ** ------------------------------*/
3117 typedef uint8_t FXOS8700_M_VECM_INITX_MSB_t;
3118 
3119 
3120 /*--------------------------------
3121 ** Register: M_VECM_INITX_LSB
3122 ** Enum: FXOS8700_M_VECM_INITX_LSB
3123 ** --
3124 ** Offset : 0x6E - Magnetic vector magnitude X-axis reference value LSB.
3125 ** ------------------------------*/
3126 typedef uint8_t FXOS8700_M_VECM_INITX_LSB_t;
3127 
3128 
3129 /*--------------------------------
3130 ** Register: M_VECM_INITY_MSB
3131 ** Enum: FXOS8700_M_VECM_INITY_MSB
3132 ** --
3133 ** Offset : 0x6F - Magnetic vector magnitude Y-axis reference value MSB.
3134 ** ------------------------------*/
3135 typedef uint8_t FXOS8700_M_VECM_INITY_MSB_t;
3136 
3137 
3138 /*--------------------------------
3139 ** Register: M_VECM_INITY_LSB
3140 ** Enum: FXOS8700_M_VECM_INITY_LSB
3141 ** --
3142 ** Offset : 0x70 - Magnetic vector magnitude Y-axis reference value LSB.
3143 ** ------------------------------*/
3144 typedef uint8_t FXOS8700_M_VECM_INITY_LSB_t;
3145 
3146 
3147 /*--------------------------------
3148 ** Register: M_VECM_INITZ_MSB
3149 ** Enum: FXOS8700_M_VECM_INITZ_MSB
3150 ** --
3151 ** Offset : 0x71 - Magnetic vector magnitude Z-axis reference value MSB.
3152 ** ------------------------------*/
3153 typedef uint8_t FXOS8700_M_VECM_INITZ_MSB_t;
3154 
3155 
3156 /*--------------------------------
3157 ** Register: M_VECM_INITZ_LSB
3158 ** Enum: FXOS8700_M_VECM_INITZ_LSB
3159 ** --
3160 ** Offset : 0x72 - Magnetic vector magnitude Z-axis reference value LSB.
3161 ** ------------------------------*/
3162 typedef uint8_t FXOS8700_M_VECM_INITZ_LSB_t;
3163 
3164 
3165 /*--------------------------------
3166 ** Register: A_FFMT_THS_X_MSB
3167 ** Enum: FXOS8700_A_FFMT_THS_X_MSB
3168 ** --
3169 ** Offset : 0x73 - X-axis FFMT threshold MSB.
3170 ** ------------------------------*/
3171 typedef uint8_t FXOS8700_A_FFMT_THS_X_MSB_t;
3172 
3173 
3174 
3175 /*--------------------------------
3176 ** Register: A_FFMT_THS_X_LSB
3177 ** Enum: FXOS8700_A_FFMT_THS_X_LSB
3178 ** --
3179 ** Offset : 0x74 - X-axis FFMT threshold LSB.
3180 ** ------------------------------*/
3181 typedef union {
3182  struct {
3183  uint8_t a_ffmt_ths_x : 7;
3184  } b;
3185  uint8_t w;
3186 } FXOS8700_A_FFMT_THS_X_LSB_t;
3187 
3188 
3189 /*
3190 ** A_FFMT_THS_X_LSB - Bit field mask definitions
3191 */
3192 #define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x7F)
3193 #define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
3194 
3195 
3196 /*------------------------------*/
3197 
3198 
3199 
3200 /*--------------------------------
3201 ** Register: A_FFMT_THS_Y_MSB
3202 ** Enum: FXOS8700_A_FFMT_THS_Y_MSB
3203 ** --
3204 ** Offset : 0x75 - Y-axis FFMT threshold MSB.
3205 ** ------------------------------*/
3206 typedef uint8_t FXOS8700_A_FFMT_THS_Y_MSB_t;
3207 
3208 
3209 /*--------------------------------
3210 ** Register: A_FFMT_THS_Y_LSB
3211 ** Enum: FXOS8700_A_FFMT_THS_Y_LSB
3212 ** --
3213 ** Offset : 0x76 - Y-axis FFMT threshold LSB.
3214 ** ------------------------------*/
3215 typedef union {
3216  struct {
3217  uint8_t a_ffmt_ths_y : 7;
3218  } b;
3219  uint8_t w;
3220 } FXOS8700_A_FFMT_THS_Y_LSB_t;
3221 
3222 
3223 /*
3224 ** A_FFMT_THS_Y_LSB - Bit field mask definitions
3225 */
3226 #define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x7F)
3227 #define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
3228 
3229 
3230 /*------------------------------*/
3231 
3232 
3233 
3234 /*--------------------------------
3235 ** Register: A_FFMT_THS_Z_MSB
3236 ** Enum: FXOS8700_A_FFMT_THS_Z_MSB
3237 ** --
3238 ** Offset : 0x77 - Z-axis FFMT threshold MSB.
3239 ** ------------------------------*/
3240 typedef uint8_t FXOS8700_A_FFMT_THS_Z_MSB_t;
3241 
3242 
3243 /*--------------------------------
3244 ** Register: A_FFMT_THS_Z_LSB
3245 ** Enum: FXOS8700_A_FFMT_THS_Z_LSB
3246 ** --
3247 ** Offset : 0x78 - Z-axis FFMT threshold LSB.
3248 ** ------------------------------*/
3249 typedef union {
3250  struct {
3251  uint8_t a_ffmt_ths_z : 7;
3252  } b;
3253  uint8_t w;
3254 } FXOS8700_A_FFMT_THS_Z_LSB_t;
3255 
3256 
3257 /*
3258 ** A_FFMT_THS_Z_LSB - Bit field mask definitions
3259 */
3260 #define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_MASK ((uint8_t) 0x7F)
3261 #define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_SHIFT ((uint8_t) 0)
3262 
3263 
3264 /*------------------------------*/
3265 
3266 
3267 #endif /* FXOS8700_H_ */
3268 
3269 // STATUS : 0x00
FXOS8700_SYSMOD_t::w
uint8_t w
Definition: fxos8700.h:562
FXOS8700_INT_SOURCE_t::src_fifo
uint8_t src_fifo
Definition: fxos8700.h:604
FXOS8700_M_CTRL_REG2_t::m_autoinc
uint8_t m_autoinc
Definition: fxos8700.h:2639
FXOS8700_M_INT_SRC_t
Definition: fxos8700.h:2769
FXOS8700_CTRL_REG2_t::mods
uint8_t mods
Definition: fxos8700.h:1580
FXOS8700_F_SETUP_t
Definition: fxos8700.h:459
FXOS8700_CTRL_REG4_t::int_en_aslp
uint8_t int_en_aslp
Definition: fxos8700.h:1728
FXOS8700_OUT_Z_LSB_t::w
uint8_t w
Definition: fxos8700.h:438
FXOS8700_TRANSIENT_CFG_t::ztefe
uint8_t ztefe
Definition: fxos8700.h:1092
FXOS8700_TRIG_CFG_t::_reserved_
uint8_t _reserved_
Definition: fxos8700.h:501
FXOS8700_M_THS_SRC_t::m_ths_yhe
uint8_t m_ths_yhe
Definition: fxos8700.h:2399
FXOS8700_M_VECM_INITZ_MSB_t
uint8_t FXOS8700_M_VECM_INITZ_MSB_t
Definition: fxos8700.h:3153
FXOS8700_OUT_Y_LSB_t::_reserved_
uint8_t _reserved_
Definition: fxos8700.h:381
FXOS8700_MIN_Z_LSB_t
uint8_t FXOS8700_MIN_Z_LSB_t
Definition: fxos8700.h:2306
FXOS8700_PULSE_THSX_t::pls_thsx
uint8_t pls_thsx
Definition: fxos8700.h:1394
FXOS8700_M_THS_CFG_t::m_ths_yefe
uint8_t m_ths_yefe
Definition: fxos8700.h:2347
FXOS8700_MIN_X_MSB_t
uint8_t FXOS8700_MIN_X_MSB_t
Definition: fxos8700.h:2261
FXOS8700_OUT_X_LSB_t::xd
uint8_t xd
Definition: fxos8700.h:329
FXOS8700_INT_SOURCE_t::src_a_vecm
uint8_t src_a_vecm
Definition: fxos8700.h:599
FXOS8700_M_THS_CFG_t::m_ths_wake_en
uint8_t m_ths_wake_en
Definition: fxos8700.h:2345
FXOS8700_M_CTRL_REG3_t::m_st_xy
uint8_t m_st_xy
Definition: fxos8700.h:2710
FXOS8700_OUT_Y_MSB_t::yd
uint8_t yd
Definition: fxos8700.h:355
FXOS8700_OUT_X_LSB_t::w
uint8_t w
Definition: fxos8700.h:332
FXOS8700_M_DR_STATUS_t::zdr
uint8_t zdr
Definition: fxos8700.h:1896
FXOS8700_A_FFMT_SRC_t::_reserved_
uint8_t _reserved_
Definition: fxos8700.h:1005
FXOS8700_A_VECM_INITY_LSB_t
uint8_t FXOS8700_A_VECM_INITY_LSB_t
Definition: fxos8700.h:2948
FXOS8700_MIN_Y_MSB_t
uint8_t FXOS8700_MIN_Y_MSB_t
Definition: fxos8700.h:2279
FXOS8700_CTRL_REG5_t::int_cfg_trans
uint8_t int_cfg_trans
Definition: fxos8700.h:1799
FXOS8700_A_VECM_CFG_t::a_vecm_updm
uint8_t a_vecm_updm
Definition: fxos8700.h:2805
FXOS8700_TRANSIENT_SRC_t::w
uint8_t w
Definition: fxos8700.h:1165
FXOS8700_DR_STATUS_t::zow
uint8_t zow
Definition: fxos8700.h:193
FXOS8700_M_INT_SRC_t::src_m_vecm
uint8_t src_m_vecm
Definition: fxos8700.h:2772
FXOS8700_MIN_Y_LSB_t
uint8_t FXOS8700_MIN_Y_LSB_t
Definition: fxos8700.h:2288
FXOS8700_CTRL_REG2_t::rst
uint8_t rst
Definition: fxos8700.h:1584
FXOS8700_HP_FILTER_CUTOFF_t::pulse_hpf_byp
uint8_t pulse_hpf_byp
Definition: fxos8700.h:704
FXOS8700_M_THS_Y_LSB_t
uint8_t FXOS8700_M_THS_Y_LSB_t
Definition: fxos8700.h:2503
FXOS8700_CTRL_REG3_t::fifo_gate
uint8_t fifo_gate
Definition: fxos8700.h:1646
FXOS8700_PULSE_CFG_t::w
uint8_t w
Definition: fxos8700.h:1265
FXOS8700_CTRL_REG3_t::wake_a_vecm
uint8_t wake_a_vecm
Definition: fxos8700.h:1641
FXOS8700_M_DR_STATUS_t::zyxow
uint8_t zyxow
Definition: fxos8700.h:1901
FXOS8700_TRANSIENT_COUNT_t
uint8_t FXOS8700_TRANSIENT_COUNT_t
Definition: fxos8700.h:1242
FXOS8700_PL_COUNT_t
Definition: fxos8700.h:819
FXOS8700_M_CTRL_REG1_t::m_rst
uint8_t m_rst
Definition: fxos8700.h:2563
FXOS8700_M_DR_STATUS_t::ydr
uint8_t ydr
Definition: fxos8700.h:1895
FXOS8700_TRIG_CFG_t
Definition: fxos8700.h:499
FXOS8700_TRIG_CFG_t::trig_a_vecm
uint8_t trig_a_vecm
Definition: fxos8700.h:502
FXOS8700_CTRL_REG5_t::int_cfg_pulse
uint8_t int_cfg_pulse
Definition: fxos8700.h:1797
FXOS8700_CMP_X_MSB_t
Definition: fxos8700.h:2000
FXOS8700_M_DR_STATUS_t::zow
uint8_t zow
Definition: fxos8700.h:1900
FXOS8700_M_OUT_Y_MSB_t
uint8_t FXOS8700_M_OUT_Y_MSB_t
Definition: fxos8700.h:1963
FXOS8700_OUT_Z_LSB_t::_reserved_
uint8_t _reserved_
Definition: fxos8700.h:434
FXOS8700_CTRL_REG1_t::w
uint8_t w
Definition: fxos8700.h:1514
FXOS8700_M_VECM_CFG_t::a_vecm_en
uint8_t a_vecm_en
Definition: fxos8700.h:2996
FXOS8700_A_FFMT_THS_t::w
uint8_t w
Definition: fxos8700.h:1052
FXOS8700_CTRL_REG1_t::active
uint8_t active
Definition: fxos8700.h:1508
FXOS8700_M_CTRL_REG3_t::w
uint8_t w
Definition: fxos8700.h:2716
FXOS8700_M_THS_SRC_t::m_ths_yhp
uint8_t m_ths_yhp
Definition: fxos8700.h:2398
FXOS8700_PL_COUNT_t::dbnce
uint8_t dbnce
Definition: fxos8700.h:821
FXOS8700_M_THS_Z_MSB_t::w
uint8_t w
Definition: fxos8700.h:2516
FXOS8700_M_VECM_CFG_t::m_vecm_ele
uint8_t m_vecm_ele
Definition: fxos8700.h:2999
FXOS8700_M_CTRL_REG1_t::m_os
uint8_t m_os
Definition: fxos8700.h:2559
FXOS8700_CTRL_REG4_t::int_en_drdy
uint8_t int_en_drdy
Definition: fxos8700.h:1721
FXOS8700_TRANSIENT_THS_t::tr_dbcntm
uint8_t tr_dbcntm
Definition: fxos8700.h:1207
FXOS8700_A_VECM_INITZ_LSB_t
uint8_t FXOS8700_A_VECM_INITZ_LSB_t
Definition: fxos8700.h:2982
FXOS8700_M_THS_SRC_t::m_ths_ea
uint8_t m_ths_ea
Definition: fxos8700.h:2403
FXOS8700_PL_CFG_t::dbcntm
uint8_t dbcntm
Definition: fxos8700.h:784
FXOS8700_A_FFMT_THS_Y_LSB_t
Definition: fxos8700.h:3215
FXOS8700_A_FFMT_THS_X_MSB_t
uint8_t FXOS8700_A_FFMT_THS_X_MSB_t
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FXOS8700_A_VECM_INITX_MSB_t
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FXOS8700_A_VECM_INITY_MSB_t
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FXOS8700_A_FFMT_SRC_t
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FXOS8700_M_OUT_X_MSB_t
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FXOS8700_M_VECM_THS_MSB_t
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FXOS8700_M_THS_X_MSB_t::w
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FXOS8700_PULSE_THSY_t
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FXOS8700_PULSE_WIND_t
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FXOS8700_PULSE_THSX_t
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FXOS8700_CMP_Z_LSB_t
uint8_t FXOS8700_CMP_Z_LSB_t
Definition: fxos8700.h:2093
FXOS8700_CMP_X_LSB_t
uint8_t FXOS8700_CMP_X_LSB_t
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FXOS8700_MIN_X_LSB_t
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FXOS8700_PULSE_THSZ_t
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Definition: fxos8700.h:190
FXOS8700_M_OFF_Y_LSB_t
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uint8_t FXOS8700_A_VECM_CNT_t
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FXOS8700_M_THS_Z_MSB_t
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Definition: fxos8700.h:948
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FXOS8700_A_FFMT_THS_Z_MSB_t
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FXOS8700_A_VECM_THS_MSB_t::_reserved_
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Definition: fxos8700.h:2843
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FXOS8700_A_FFMT_CFG_t::_reserved_
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Definition: fxos8700.h:2402
FXOS8700_M_THS_X_MSB_t
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Definition: fxos8700.h:3251
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Definition: fxos8700.h:1343
FXOS8700_OUT_Z_MSB_t
Definition: fxos8700.h:406
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Definition: fxos8700.h:3000
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Definition: fxos8700.h:2343
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Definition: fxos8700.h:1089
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FXOS8700_M_CTRL_REG3_t
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FXOS8700_OUT_Z_LSB_t
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uint8_t FXOS8700_OFF_Z_t
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Definition: fxos8700.h:601
FXOS8700_M_THS_SRC_t
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FXOS8700_A_FFMT_THS_Z_LSB_t
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Definition: fxos8700.h:702
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Definition: fxos8700.h:1583
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Definition: fxos8700.h:748
FXOS8700_CTRL_REG2_t
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FXOS8700_M_OFF_Z_MSB_t
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FXOS8700_MAX_X_MSB_t
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Definition: fxos8700.h:2207
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Definition: fxos8700.h:3126
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FXOS8700_ASLP_COUNT_t
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