ISSDK  1.7
IoT Sensing Software Development Kit
mag3110.h
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1 /**
2  * @file mag3110.h
3  * @brief The mag3110.h contains the MAG3110 Magnetic sensor register definitions, access macros, and
4  * device access functions.
5  *
6  * @copyright Copyright (c) 2016, Freescale Semiconductor, Inc.
7  */
8 #ifndef MAG3110_H_
9 #define MAG3110_H_
10 
11 /**
12  **
13  ** MAG3110 Sensor Internal Registers
14  */
15 enum {
16  MAG3110_DR_STATUS = 0x00,
17  MAG3110_OUT_X_MSB = 0x01,
18  MAG3110_OUT_X_LSB = 0x02,
19  MAG3110_OUT_Y_MSB = 0x03,
20  MAG3110_OUT_Y_LSB = 0x04,
21  MAG3110_OUT_Z_MSB = 0x05,
22  MAG3110_OUT_Z_LSB = 0x06,
23  MAG3110_WHO_AM_I = 0x07,
24  MAG3110_SYSMOD = 0x08,
25  MAG3110_OFF_X_MSB = 0x09,
26  MAG3110_OFF_X_LSB = 0x0A,
27  MAG3110_OFF_Y_MSB = 0x0B,
28  MAG3110_OFF_Y_LSB = 0x0C,
29  MAG3110_OFF_Z_MSB = 0x0D,
30  MAG3110_OFF_Z_LSB = 0x0E,
31  MAG3110_DIE_TEMP = 0x0F,
32  MAG3110_CTRL_REG1 = 0x10,
33  MAG3110_CTRL_REG2 = 0x11,
34 };
35 
36 #define MAG3110_I2C_ADDRESS (0x0E) /* MAG3110 I2C Slave Address. */
37 #define MAG3110_WHOAMI_VALUE (0xC4) /* MAG3110 Who_Am_I Value. */
38 
39 
40 
41 /*--------------------------------
42 ** Register: DR_STATUS
43 ** Enum: MAG3110_DR_STATUS
44 ** --
45 ** Offset : 0x00 - Data-ready status information
46 ** ------------------------------*/
47 typedef union {
48  struct {
49  uint8_t xdr : 1; /* - X-Axis new Data Available. */
50 
51  uint8_t ydr : 1; /* - Y-Axis new data available. */
52 
53  uint8_t zdr : 1; /* - Z-Axis new data available. */
54 
55  uint8_t zyxdr : 1; /* - X or Y or Z-Axis new data available. */
56 
57  uint8_t xow : 1; /* - X-Axis data overwrite. */
58 
59  uint8_t yow : 1; /* - Y-Axis data overwrite. */
60 
61  uint8_t zow : 1; /* - Z-Axis data overwrite. */
62 
63  uint8_t zyxow : 1; /* - X, Y, Z-Axis data overwrite. */
64 
65  } b;
66  uint8_t w;
67 } MAG3110_DR_STATUS_t;
68 
69 
70 /*
71 ** DR_STATUS - Bit field mask definitions
72 */
73 #define MAG3110_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
74 #define MAG3110_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
75 
76 #define MAG3110_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
77 #define MAG3110_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
78 
79 #define MAG3110_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
80 #define MAG3110_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
81 
82 #define MAG3110_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
83 #define MAG3110_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
84 
85 #define MAG3110_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
86 #define MAG3110_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
87 
88 #define MAG3110_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
89 #define MAG3110_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
90 
91 #define MAG3110_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
92 #define MAG3110_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
93 
94 #define MAG3110_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
95 #define MAG3110_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
96 
97 
98 /*
99 ** DR_STATUS - Bit field value definitions
100 */
101 #define MAG3110_DR_STATUS_XDR_DRDY ((uint8_t) 0x01) /* - Set to 1 whenever new X-axis data acquisition is */
102  /* completed. XDR is cleared any time OUT_X_MSB */
103  /* register is read. */
104 #define MAG3110_DR_STATUS_YDR_DRDY ((uint8_t) 0x02) /* - Set to 1 whenever new Y-axis data acquisition is */
105  /* completed. YDR is cleared any time OUT_Y_MSB */
106  /* register is read. */
107 #define MAG3110_DR_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* - Set to 1 whenever new Z-axis data acquisition is */
108  /* completed. ZDR is cleared any time OUT_Z_MSB */
109  /* register is read. */
110 #define MAG3110_DR_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* - Signals that new acquisition for any of the */
111  /* enabled channels is available. ZYXDR is cleared */
112  /* when the high-bytes of the data (OUT_X_MSB, */
113  /* OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels */
114  /* are read. */
115 #define MAG3110_DR_STATUS_XOW_OWR ((uint8_t) 0x10) /* - Set to 1 whenever new X-axis acquisition is */
116  /* completed before the retrieval of the previous */
117  /* data. When this occurs the previous data is */
118  /* overwritten. XOW is cleared any time OUT_X_MSB */
119  /* register is read. */
120 #define MAG3110_DR_STATUS_YOW_OWR ((uint8_t) 0x20) /* - Set to 1 whenever new Y-axis acquisition is */
121  /* completed before the retrieval of the previous */
122  /* data. When this occurs the previous data is */
123  /* overwritten. YOW is cleared any time OUT_Y_MSB */
124  /* register is read. */
125 #define MAG3110_DR_STATUS_ZOW_OWR ((uint8_t) 0x40) /* - Set to 1 whenever new Z-axis acquisition is */
126  /* completed before the retrieval of the previous */
127  /* data. When this occurs the previous data is */
128  /* overwritten. ZOW is cleared any time OUT_Z_MSB */
129  /* register is read. */
130 #define MAG3110_DR_STATUS_ZYXOW_OWR ((uint8_t) 0x80) /* - Set to 1 whenever new data is acquired before */
131  /* completing the retrieval of the previous set. This */
132  /* event occurs when the content of at least one data */
133  /* register (i.e. OUT_X, OUT_Y, OUT_Z) has been */
134  /* overwritten. ZYXOW is cleared when the highbytes of */
135  /* the data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all */
136  /* active channels are read. */
137 /*------------------------------*/
138 
139 
140 
141 
142 /*--------------------------------
143 ** Register: OUT_X_MSB
144 ** Enum: MAG3110_OUT_X_MSB
145 ** --
146 ** Offset : 0x01 - Bits 8-15 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
147 ** ------------------------------*/
148 typedef uint8_t MAG3110_OUT_X_MSB_t;
149 
150 
151 /*--------------------------------
152 ** Register: OUT_X_LSB
153 ** Enum: MAG3110_OUT_X_LSB
154 ** --
155 ** Offset : 0x02 - Bits 0-7 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
156 ** ------------------------------*/
157 typedef uint8_t MAG3110_OUT_X_LSB_t;
158 
159 
160 /*--------------------------------
161 ** Register: OUT_Y_MSB
162 ** Enum: MAG3110_OUT_Y_MSB
163 ** --
164 ** Offset : 0x03 - Bits 8-15 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
165 ** ------------------------------*/
166 typedef uint8_t MAG3110_OUT_Y_MSB_t;
167 
168 
169 /*--------------------------------
170 ** Register: OUT_Y_LSB
171 ** Enum: MAG3110_OUT_Y_LSB
172 ** --
173 ** Offset : 0x04 - Bits 0-7 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
174 ** ------------------------------*/
175 typedef uint8_t MAG3110_OUT_Y_LSB_t;
176 
177 
178 /*--------------------------------
179 ** Register: OUT_Z_MSB
180 ** Enum: MAG3110_OUT_Z_MSB
181 ** --
182 ** Offset : 0x05 - Bits 8-15 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
183 ** ------------------------------*/
184 typedef uint8_t MAG3110_OUT_Z_MSB_t;
185 
186 
187 /*--------------------------------
188 ** Register: OUT_Z_LSB
189 ** Enum: MAG3110_OUT_Z_LSB
190 ** --
191 ** Offset : 0x06 - Bits 0-7 of 16-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers.
192 ** ------------------------------*/
193 
194 typedef uint8_t MAG3110_OUT_Z_LSB_t;
195 
196 
197 
198 /*--------------------------------
199 ** Register: WHO_AM_I
200 ** Enum: MAG3110_WHO_AM_I
201 ** --
202 ** Offset : 0x07 - Device identification register containing Fixed Device ID Number.
203 ** ------------------------------*/
204 typedef uint8_t MAG3110_WHO_AM_I_t;
205 
206 
207 
208 
209 /*--------------------------------
210 ** Register: SYSMOD
211 ** Enum: MAG3110_SYSMOD
212 ** --
213 ** Offset : 0x08 - The read-only system mode register indicating the current device operating mode.
214 ** ------------------------------*/
215 typedef union {
216  struct {
217  uint8_t sysmod : 2; /* - System mode data bits 0-1. (Bits 7-2 will always read 0.) */
218 
219  } b;
220  uint8_t w;
221 } MAG3110_SYSMOD_t;
222 
223 
224 /*
225 ** SYSMOD - Bit field mask definitions
226 */
227 #define MAG3110_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
228 #define MAG3110_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
229 
230 
231 /*
232 ** SYSMOD - Bit field value definitions
233 */
234 #define MAG3110_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* - STANDBY Mode. */
235 #define MAG3110_SYSMOD_SYSMOD_ACTIVE_RAW ((uint8_t) 0x01) /* - ACTIVE Mode, RAW Data. */
236 #define MAG3110_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x02) /* - ACTIVE Mode, non-RAW user-corrected Data. */
237 /*------------------------------*/
238 
239 
240 
241 
242 /*--------------------------------
243 ** Register: OFF_X_MSB
244 ** Enum: MAG3110_OFF_X_MSB
245 ** --
246 ** Offset : 0x09 - Bits 7-14 of X-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
247 ** ------------------------------*/
248 typedef uint8_t MAG3110_OFF_X_MSB_t;
249 
250 
251 
252 /*--------------------------------
253 ** Register: OFF_X_LSB
254 ** Enum: MAG3110_OFF_X_LSB
255 ** --
256 ** Offset : 0x0A - Bits 0-6 of X-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
257 ** ------------------------------*/
258 typedef union {
259  struct {
260  uint8_t _reserved_ : 1;
261  uint8_t off_x_lsb : 7; /* - OFF_X_LSB register bits 1-7. (Bit 0 will always be 0.) */
262 
263  } b;
264  uint8_t w;
265 } MAG3110_OFF_X_LSB_t;
266 
267 
268 /*
269 ** OFF_X_LSB - Bit field mask definitions
270 */
271 #define MAG3110_OFF_X_LSB_OFF_X_LSB_MASK ((uint8_t) 0xFE)
272 #define MAG3110_OFF_X_LSB_OFF_X_LSB_SHIFT ((uint8_t) 1)
273 
274 
275 /*------------------------------*/
276 
277 
278 
279 /*--------------------------------
280 ** Register: OFF_Y_MSB
281 ** Enum: MAG3110_OFF_Y_MSB
282 ** --
283 ** Offset : 0x0B - Bits 7-14 of Y-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
284 ** ------------------------------*/
285 typedef uint8_t MAG3110_OFF_Y_MSB_t;
286 
287 
288 
289 /*--------------------------------
290 ** Register: OFF_Y_LSB
291 ** Enum: MAG3110_OFF_Y_LSB
292 ** --
293 ** Offset : 0x0C - Bits 0-6 of Y-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
294 ** ------------------------------*/
295 typedef union {
296  struct {
297  uint8_t _reserved_ : 1;
298  uint8_t off_y_lsb : 7; /* - OFF_Y_LSB register bits 1-7. (Bit 0 will always be 0.) */
299 
300  } b;
301  uint8_t w;
302 } MAG3110_OFF_Y_LSB_t;
303 
304 
305 /*
306 ** OFF_Y_LSB - Bit field mask definitions
307 */
308 #define MAG3110_OFF_Y_LSB_OFF_Y_LSB_MASK ((uint8_t) 0xFE)
309 #define MAG3110_OFF_Y_LSB_OFF_Y_LSB_SHIFT ((uint8_t) 1)
310 
311 
312 /*------------------------------*/
313 
314 
315 
316 /*--------------------------------
317 ** Register: OFF_Z_MSB
318 ** Enum: MAG3110_OFF_Z_MSB
319 ** --
320 ** Offset : 0x0D - Bits 7-14 of Z-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
321 ** ------------------------------*/
322 typedef uint8_t MAG3110_OFF_Z_MSB_t;
323 
324 
325 
326 /*--------------------------------
327 ** Register: OFF_Z_LSB
328 ** Enum: MAG3110_OFF_Z_LSB
329 ** --
330 ** Offset : 0x0E - Bits 0-6 of Z-Axis user defined offsets in 2's complement format which are used when CTRL_REG2[RAW] = 0.
331 ** ------------------------------*/
332 typedef union {
333  struct {
334  uint8_t _reserved_ : 1;
335  uint8_t off_z_lsb : 7; /* - OFF_Z_LSB register bits 1-7. (Bit 0 will always be 0.) */
336 
337  } b;
338  uint8_t w;
339 } MAG3110_OFF_Z_LSB_t;
340 
341 
342 /*
343 ** OFF_Z_LSB - Bit field mask definitions
344 */
345 #define MAG3110_OFF_Z_LSB_OFF_Z_LSB_MASK ((uint8_t) 0xFE)
346 #define MAG3110_OFF_Z_LSB_OFF_Z_LSB_SHIFT ((uint8_t) 1)
347 
348 
349 /*------------------------------*/
350 
351 
352 
353 
354 /*--------------------------------
355 ** Register: DIE_TEMP
356 ** Enum: MAG3110_DIE_TEMP
357 ** --
358 ** Offset : 0x0F - The die temperature in °C expressed as an 8-bit 2's complement number.
359 ** ------------------------------*/
360 typedef uint8_t MAG3110_DIE_TEMP_t;
361 
362 
363 
364 
365 /*--------------------------------
366 ** Register: CTRL_REG1
367 ** Enum: MAG3110_CTRL_REG1
368 ** --
369 ** Offset : 0x10 - Control Register 1: Modes, Trigger, ODR, OSR.
370 ** ------------------------------*/
371 typedef union {
372  struct {
373  uint8_t ac : 1; /* - Operating Mode. */
374 
375  uint8_t tm : 1; /* - Trigger immediate measurement (if the ac bit is set to standby). */
376 
377  uint8_t fr : 1; /* - Fast Read selection Mode. 8-bit values are read from the MSB registers */
378  /* (Auto-increment skips over the LSB register in burst-read mode). */
379 
380  uint8_t os : 2; /* - These bits configures the over sampling ratio for the measurement. */
381 
382  uint8_t dr : 3; /* - These bits configures the Output Data Rate. */
383 
384  } b;
385  uint8_t w;
386 } MAG3110_CTRL_REG1_t;
387 
388 
389 /*
390 ** CTRL_REG1 - Bit field mask definitions
391 */
392 #define MAG3110_CTRL_REG1_AC_MASK ((uint8_t) 0x01)
393 #define MAG3110_CTRL_REG1_AC_SHIFT ((uint8_t) 0)
394 
395 #define MAG3110_CTRL_REG1_TM_MASK ((uint8_t) 0x02)
396 #define MAG3110_CTRL_REG1_TM_SHIFT ((uint8_t) 1)
397 
398 #define MAG3110_CTRL_REG1_FR_MASK ((uint8_t) 0x04)
399 #define MAG3110_CTRL_REG1_FR_SHIFT ((uint8_t) 2)
400 
401 #define MAG3110_CTRL_REG1_OS_MASK ((uint8_t) 0x18)
402 #define MAG3110_CTRL_REG1_OS_SHIFT ((uint8_t) 3)
403 
404 #define MAG3110_CTRL_REG1_DR_MASK ((uint8_t) 0xE0)
405 #define MAG3110_CTRL_REG1_DR_SHIFT ((uint8_t) 5)
406 
407 
408 /*
409 ** CTRL_REG1 - Bit field value definitions
410 */
411 #define MAG3110_CTRL_REG1_AC_STANDBY ((uint8_t) 0x00) /* - Standby Mode. */
412 #define MAG3110_CTRL_REG1_AC_ACTIVE ((uint8_t) 0x01) /* - Active Mode. */
413 #define MAG3110_CTRL_REG1_TM_NORMAL ((uint8_t) 0x00) /* - Normal operation based on AC condition. */
414 #define MAG3110_CTRL_REG1_TM_TRIGGER ((uint8_t) 0x02) /* - Trigger Measurement. */
415 #define MAG3110_CTRL_REG1_FR_FULL ((uint8_t) 0x00) /* - The full 16-bit values are read. */
416 #define MAG3110_CTRL_REG1_FR_FAST ((uint8_t) 0x04) /* - 8-bit values read from the MSB registers. */
417 #define MAG3110_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x00) /* - OSR = 16. */
418 #define MAG3110_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x08) /* - OSR = 32. */
419 #define MAG3110_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x10) /* - OSR = 64. */
420 #define MAG3110_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x18) /* - OSR = 128. */
421 #define MAG3110_CTRL_REG1_DR_ODR_0 ((uint8_t) 0x00) /* - ADC Rate = 1280Hz; Output Rate = ADC/OS. */
422 #define MAG3110_CTRL_REG1_DR_ODR_1 ((uint8_t) 0x20) /* - ADC Rate = 640Hz; Output Rate = ADC/OS. */
423 #define MAG3110_CTRL_REG1_DR_ODR_2 ((uint8_t) 0x40) /* - ADC Rate = 320Hz; Output Rate = ADC/OS. */
424 #define MAG3110_CTRL_REG1_DR_ODR_3 ((uint8_t) 0x60) /* - ADC Rate = 160Hz; Output Rate = ADC/OS. */
425 #define MAG3110_CTRL_REG1_DR_ODR_4 ((uint8_t) 0x80) /* - ADC Rate = 80Hz; Output Rate = ADC/OS. */
426 #define MAG3110_CTRL_REG1_DR_ODR_5 ((uint8_t) 0xa0) /* - ADC Rate = 80Hz; Output Rate = ADC/OS. */
427 #define MAG3110_CTRL_REG1_DR_ODR_6 ((uint8_t) 0xc0) /* - ADC Rate = 80Hz; Output Rate = ADC/OS. */
428 #define MAG3110_CTRL_REG1_DR_ODR_7 ((uint8_t) 0xe0) /* - ADC Rate = 80Hz; Output Rate = ADC/OS. */
429 /*------------------------------*/
430 
431 
432 
433 
434 /*--------------------------------
435 ** Register: CTRL_REG2
436 ** Enum: MAG3110_CTRL_REG2
437 ** --
438 ** Offset : 0x11 - Control Register 2: Correction, Reset.
439 ** ------------------------------*/
440 typedef union {
441  struct {
442  uint8_t _reserved_ : 4;
443  uint8_t mag_rst : 1; /* - Magnetic Sensor Reset (One-Shot) Bit. */
444 
445  uint8_t raw : 1; /* - Data output correction Bit. */
446 
447  uint8_t _reserved_1 : 1;
448  uint8_t auto_msrt_en : 1; /* - Automatic Magnetic Sensor Reset Bit. */
449 
450  } b;
451  uint8_t w;
452 } MAG3110_CTRL_REG2_t;
453 
454 
455 /*
456 ** CTRL_REG2 - Bit field mask definitions
457 */
458 #define MAG3110_CTRL_REG2_MAG_RST_MASK ((uint8_t) 0x10)
459 #define MAG3110_CTRL_REG2_MAG_RST_SHIFT ((uint8_t) 4)
460 
461 #define MAG3110_CTRL_REG2_RAW_MASK ((uint8_t) 0x20)
462 #define MAG3110_CTRL_REG2_RAW_SHIFT ((uint8_t) 5)
463 
464 #define MAG3110_CTRL_REG2_AUTO_MSRT_EN_MASK ((uint8_t) 0x80)
465 #define MAG3110_CTRL_REG2_AUTO_MSRT_EN_SHIFT ((uint8_t) 7)
466 
467 
468 /*
469 ** CTRL_REG2 - Bit field value definitions
470 */
471 #define MAG3110_CTRL_REG2_MAG_RST_EN ((uint8_t) 0x10) /* - Reset cycle initiate or Reset cycle busy/active. */
472 #define MAG3110_CTRL_REG2_RAW_NORMAL ((uint8_t) 0x00) /* - The data values are corrected by the user offset */
473  /* register values. */
474 #define MAG3110_CTRL_REG2_RAW_RAW ((uint8_t) 0x20) /* - The data values are not corrected by the user */
475  /* offset register values. */
476 #define MAG3110_CTRL_REG2_AUTO_MSRT_EN_DIS ((uint8_t) 0x00) /* - Automatic magnetic sensor resets disabled. */
477 #define MAG3110_CTRL_REG2_AUTO_MSRT_EN_EN ((uint8_t) 0x80) /* - Automatic magnetic sensor resets enabled. */
478 /*------------------------------*/
479 
480 
481 
482 #endif /* MAG3110_H_ */
MAG3110_CTRL_REG2_t
Definition: mag3110.h:440
MAG3110_CTRL_REG2_t::_reserved_
uint8_t _reserved_
Definition: mag3110.h:442
MAG3110_OFF_Y_MSB_t
uint8_t MAG3110_OFF_Y_MSB_t
Definition: mag3110.h:285
MAG3110_OFF_Y_LSB_t::w
uint8_t w
Definition: mag3110.h:301
MAG3110_OFF_Z_LSB_t
Definition: mag3110.h:332
MAG3110_OFF_X_LSB_t::w
uint8_t w
Definition: mag3110.h:264
MAG3110_DR_STATUS_t::zyxdr
uint8_t zyxdr
Definition: mag3110.h:55
MAG3110_OFF_X_LSB_t::_reserved_
uint8_t _reserved_
Definition: mag3110.h:260
MAG3110_DIE_TEMP_t
uint8_t MAG3110_DIE_TEMP_t
Definition: mag3110.h:360
MAG3110_OFF_Z_MSB_t
uint8_t MAG3110_OFF_Z_MSB_t
Definition: mag3110.h:322
MAG3110_OFF_Y_LSB_t
Definition: mag3110.h:295
MAG3110_DR_STATUS_t::zow
uint8_t zow
Definition: mag3110.h:61
MAG3110_OUT_Y_LSB_t
uint8_t MAG3110_OUT_Y_LSB_t
Definition: mag3110.h:175
MAG3110_OFF_Y_LSB_t::_reserved_
uint8_t _reserved_
Definition: mag3110.h:297
MAG3110_OFF_X_LSB_t::off_x_lsb
uint8_t off_x_lsb
Definition: mag3110.h:261
MAG3110_OFF_Z_LSB_t::w
uint8_t w
Definition: mag3110.h:338
MAG3110_DR_STATUS_t
Definition: mag3110.h:47
MAG3110_OUT_Y_MSB_t
uint8_t MAG3110_OUT_Y_MSB_t
Definition: mag3110.h:166
MAG3110_DR_STATUS_t::zdr
uint8_t zdr
Definition: mag3110.h:53
MAG3110_OFF_Z_LSB_t::_reserved_
uint8_t _reserved_
Definition: mag3110.h:334
MAG3110_SYSMOD_t::sysmod
uint8_t sysmod
Definition: mag3110.h:217
MAG3110_DR_STATUS_t::w
uint8_t w
Definition: mag3110.h:66
MAG3110_OUT_Z_MSB_t
uint8_t MAG3110_OUT_Z_MSB_t
Definition: mag3110.h:184
MAG3110_DR_STATUS_t::zyxow
uint8_t zyxow
Definition: mag3110.h:63
MAG3110_CTRL_REG2_t::raw
uint8_t raw
Definition: mag3110.h:445
MAG3110_OFF_Y_LSB_t::off_y_lsb
uint8_t off_y_lsb
Definition: mag3110.h:298
MAG3110_OFF_X_MSB_t
uint8_t MAG3110_OFF_X_MSB_t
Definition: mag3110.h:248
MAG3110_DR_STATUS_t::xdr
uint8_t xdr
Definition: mag3110.h:49
MAG3110_DR_STATUS_t::yow
uint8_t yow
Definition: mag3110.h:59
MAG3110_SYSMOD_t
Definition: mag3110.h:215
MAG3110_CTRL_REG1_t::w
uint8_t w
Definition: mag3110.h:385
MAG3110_OUT_X_LSB_t
uint8_t MAG3110_OUT_X_LSB_t
Definition: mag3110.h:157
MAG3110_WHO_AM_I_t
uint8_t MAG3110_WHO_AM_I_t
Definition: mag3110.h:204
MAG3110_CTRL_REG2_t::auto_msrt_en
uint8_t auto_msrt_en
Definition: mag3110.h:448
MAG3110_CTRL_REG2_t::_reserved_1
uint8_t _reserved_1
Definition: mag3110.h:447
MAG3110_DR_STATUS_t::ydr
uint8_t ydr
Definition: mag3110.h:51
MAG3110_CTRL_REG1_t::dr
uint8_t dr
Definition: mag3110.h:382
MAG3110_CTRL_REG1_t::ac
uint8_t ac
Definition: mag3110.h:373
MAG3110_CTRL_REG1_t::tm
uint8_t tm
Definition: mag3110.h:375
MAG3110_CTRL_REG1_t::fr
uint8_t fr
Definition: mag3110.h:377
MAG3110_CTRL_REG2_t::mag_rst
uint8_t mag_rst
Definition: mag3110.h:443
MAG3110_CTRL_REG2_t::w
uint8_t w
Definition: mag3110.h:451
MAG3110_OUT_Z_LSB_t
uint8_t MAG3110_OUT_Z_LSB_t
Definition: mag3110.h:194
MAG3110_DR_STATUS_t::xow
uint8_t xow
Definition: mag3110.h:57
MAG3110_CTRL_REG1_t::os
uint8_t os
Definition: mag3110.h:380
MAG3110_OFF_Z_LSB_t::off_z_lsb
uint8_t off_z_lsb
Definition: mag3110.h:335
MAG3110_OUT_X_MSB_t
uint8_t MAG3110_OUT_X_MSB_t
Definition: mag3110.h:148
MAG3110_SYSMOD_t::w
uint8_t w
Definition: mag3110.h:220
MAG3110_CTRL_REG1_t
Definition: mag3110.h:371
MAG3110_OFF_X_LSB_t
Definition: mag3110.h:258
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