The MCUXpresso SDK provides a peripheral clock driver for the SYSCON module of MCUXpresso SDK devices.
Function description
Clock driver provides these functions:
- Functions to initialize the Core clock to given frequency
- Functions to configure the clock selection muxes.
- Functions to setup peripheral clock dividers
- Functions to get the frequency of the selected clock
- Functions to set PLL frequency
SYSCON Clock frequency functions
SYSCON clock module provides clocks, such as MCLKCLK, ADCCLK, DMICCLK, MCGFLLCLK, FXCOMCLK, WDTOSC, RTCOSC, and USBCLK. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. The SYSCON clock driver provides functions to receive the frequency of these clocks, such as CLOCK_GetFreq().
SYSCON clock Selection Muxes
The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC, and PLL.
SYSCON clock dividers
The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, SYSTICK, AHB, and also for CLKOUT functions.
Typical use case
/* when CLK_XTAL_SEL is set to 1(means 32M xtal is used), XTAL_DIV is valid
|
enum | clock_ip_name_t |
| Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
|
|
enum | clock_name_t {
kCLOCK_CoreSysClk,
kCLOCK_BusClk,
kCLOCK_ApbClk,
kCLOCK_WdtClk,
kCLOCK_FroHf,
kCLOCK_Xin,
kCLOCK_32KClk
} |
| Clock name used to get clock frequency. More...
|
|
enum | clock_attach_id_t {
kXTAL32K_to_32K_CLK = MUX_A(CM_32KCLKSEL, 0),
kRCO32K_to_32K_CLK = MUX_A(CM_32KCLKSEL, 1),
kOSC32M_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 0),
kXTAL_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 1),
k32K_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 2),
k32K_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 0),
kAPB_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 1),
k8M_to_BLE_CLK = MUX_A(CM_BLECLKSEL, 0),
k16M_to_BLE_CLK = MUX_A(CM_BLECLKSEL, 1),
k16M_to_XTAL_CLK = MUX_A(CM_XTALCLKSEL, 0),
k32M_to_XTAL_CLK = MUX_A(CM_XTALCLKSEL, 1)
} |
|
enum | clock_usb_src_t { kCLOCK_UsbSrcFro
} |
| USB clock source definition. More...
|
|
enum | clock_clkout_src_t {
kCLOCK_Clkout_32K = SYSCON_CLK_CTRL_CLK_32K_OE_MASK,
kCLOCK_Clkout_XTAL = SYSCON_CLK_CTRL_CLK_XTAL_OE_MASK
} |
|
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could contol the clock out of the driver.
- Note
- All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
Value:{ \
kCLOCK_Flexcomm0, kCLOCK_Flexcomm1 \
}
Value:{ \
kCLOCK_Flexcomm1, kCLOCK_Flexcomm2 \
}
Value:{ \
kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
}
Value:{ \
kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer2, kCLOCK_Ctimer3 \
}
Value:{ \
kCLOCK_Qdec0, kCLOCK_Qdec1 \
}
#define MUX_A |
( |
|
m, |
|
|
|
choice |
|
) |
| (((m) << 0) | ((choice + 1) << 8)) |
[4 bits for choice] [8 bits mux ID]
Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.
Enumerator |
---|
kCLOCK_CoreSysClk |
Core/system clock (aka MAIN_CLK)
|
kCLOCK_BusClk |
Bus clock (AHB clock)
|
kCLOCK_ApbClk |
Apb clock.
|
kCLOCK_WdtClk |
Wdt clock.
|
kCLOCK_FroHf |
FRO.
|
kCLOCK_Xin |
16/32 MHz XIN
|
kCLOCK_32KClk |
32K clock
|
Enumerator |
---|
kXTAL32K_to_32K_CLK |
XTAL 32K clock.
|
kRCO32K_to_32K_CLK |
RCO 32KHz clock.
|
kOSC32M_to_SYS_CLK |
OSC 32MHz clock.
|
kXTAL_to_SYS_CLK |
XTAL 16MHz/32MHz clock.
|
k32K_to_SYS_CLK |
32KHz clock
|
k32K_to_WDT_CLK |
32KHz clock
|
kAPB_to_WDT_CLK |
APB clock.
|
k8M_to_BLE_CLK |
8M CLOCK
|
k16M_to_BLE_CLK |
16M CLOCK
|
k16M_to_XTAL_CLK |
16M XTAL
|
k32M_to_XTAL_CLK |
32M XTAL
|
Enumerator |
---|
kCLOCK_UsbSrcFro |
Fake USB src clock, temporary fix until USB clock control is done properly.
|
Enumerator |
---|
kCLOCK_Clkout_32K |
32KHz clock out
|
kCLOCK_Clkout_XTAL |
XTAL clock out.
|
- Parameters
-
connection,: | Clock to be configured. |
void CLOCK_SetClkDiv |
( |
clock_div_name_t |
div_name, |
|
|
uint32_t |
divided_by_value |
|
) |
| |
- Parameters
-
div_name,: | Clock divider name |
divided_by_value,: | Value to be divided |
- Returns
- Frequency of selected clock
static void CLOCK_DisableUsbfs0Clock |
( |
void |
| ) |
|
|
inlinestatic |
void CLOCK_EnableClkoutSource |
( |
uint32_t |
mask, |
|
|
bool |
enable |
|
) |
| |
- Parameters
-
mask | Mask value for the clock source, See "clock_clkout_src_t". |
enable | Enable/Disable the clock out source. |
void CLOCK_EnableClkoutPin |
( |
uint32_t |
mask, |
|
|
bool |
enable |
|
) |
| |
- Parameters
-
mask | Mask value for the clock source, See "clock_clkout_pin_t". |
enable | Enable/Disable the clock out pin. |
uint32_t CLOCK_GetFRGInputClock |
( |
void |
| ) |
|
- Returns
- Input Frequency for FRG
uint32_t CLOCK_SetFRGClock |
( |
clock_div_name_t |
div_name, |
|
|
uint32_t |
freq |
|
) |
| |
- Parameters
-
div_name,: | Clock divider name: kCLOCK_DivFrg0 and kCLOCK_DivFrg1 |
freq,: | Desired output frequency |
- Returns
- Error Code 0 - fail 1 - success