Reset Driver

Overview

Reset driver supports peripheral reset and system reset.

Macros
#define	RST_CTL0_PSCCTL0   0
	Reset control registers index.
#define	ADC_RSTS

Typedefs
typedef RSTCTL_RSTn_t	reset_ip_name_t
	IP reset handle.

Enumerations
enum	RSTCTL_RSTn_t {   kDSP_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 1U,   kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U,   kCASPER_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 9U,   kHASHCRYPT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 10U,   kPUF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 11U,   kRNG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 12U,   kFLEXSPI_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 16U,   kUSBHS_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 20U,   kUSBHS_DEVICE_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 21U,   kUSBHS_HOST_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 22U,   kUSBHS_SRAM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 23U,   kSCT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 24U,   kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U,   kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U,   kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U,   kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U,   kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U,   kUTICK0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 0U,   kWWDT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 1U,   kFC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U,   kFC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U,   kFC2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U,   kFC3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U,   kFC4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 12U,   kFC5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 13U,   kFC6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 14U,   kFC7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 15U,   kFC14_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 22U,   kFC15_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 23U,   kDMIC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U,   kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U,   kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U,   kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U,   kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U,   kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U,   kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U,   kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U,   kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U,   kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U,   kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U,   kDMAC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 23U,   kDMAC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 24U,   kMU_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 28U,   kSEMA_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 29U,   kFREQME_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 31U,   kCT32B0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 0U,   kCT32B1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 1U,   kCT32B2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 2U,   kCT32B3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 3U,   kCT32B4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 4U,   kMRT0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 8U,   kWWDT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 10U,   kI3C0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 16U,   kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 30U,   kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U }
	Enumeration for peripheral reset control bits. More...

Functions
void	RESET_SetPeripheralReset (reset_ip_name_t peripheral)
	Assert reset to peripheral. More...
void	RESET_ClearPeripheralReset (reset_ip_name_t peripheral)
	Clear reset to peripheral. More...
void	RESET_PeripheralReset (reset_ip_name_t peripheral)
	Reset peripheral module. More...

Driver version
#define	FSL_RESET_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))
	reset driver version 2.1.1. More...

Macro Definition Documentation

#define FSL_RESET_DRIVER_VERSION   (MAKE_VERSION(2, 1, 1))

#define ADC_RSTS

Value:

{                        \
        kADC0_RST_SHIFT_RSTn \
    } /* Reset bits for ADC peripheral */

Array initializers with peripheral reset bits

Enumeration Type Documentation

enum RSTCTL_RSTn_t

Defines the enumeration for peripheral reset control bits in RSTCLTx registers

Enumerator
kDSP_RST_SHIFT_RSTn	DSP reset control
kPOWERQUAD_RST_SHIFT_RSTn	POWERQUAD reset control
kCASPER_RST_SHIFT_RSTn	CASPER reset control
kHASHCRYPT_RST_SHIFT_RSTn	HASHCRYPT reset control
kPUF_RST_SHIFT_RSTn	Physical unclonable function reset control
kRNG_RST_SHIFT_RSTn	Random number generator (RNG) reset control
kFLEXSPI_RST_SHIFT_RSTn	FLEXSPI reset control
kUSBHS_PHY_RST_SHIFT_RSTn	High speed USB PHY reset control
kUSBHS_DEVICE_RST_SHIFT_RSTn	High speed USB Device reset control
kUSBHS_HOST_RST_SHIFT_RSTn	High speed USB Host reset control
kUSBHS_SRAM_RST_SHIFT_RSTn	High speed USB SRAM reset control
kSCT_RST_SHIFT_RSTn	Standard ctimers reset control
kSDIO0_RST_SHIFT_RSTn	SDIO0 reset control
kSDIO1_RST_SHIFT_RSTn	SDIO1 reset control
kACMP0_RST_SHIFT_RSTn	Grouped interrupt (PINT) reset control.
kADC0_RST_SHIFT_RSTn	ADC0 reset control
kSHSGPIO0_RST_SHIFT_RSTn	Security HSGPIO 0 reset control
kUTICK0_RST_SHIFT_RSTn	Micro-tick timer reset control
kWWDT0_RST_SHIFT_RSTn	Windowed Watchdog timer 0 reset control
kFC0_RST_SHIFT_RSTn	Flexcomm Interface 0 reset control
kFC1_RST_SHIFT_RSTn	Flexcomm Interface 1 reset control
kFC2_RST_SHIFT_RSTn	Flexcomm Interface 2 reset control
kFC3_RST_SHIFT_RSTn	Flexcomm Interface 3 reset control
kFC4_RST_SHIFT_RSTn	Flexcomm Interface 4 reset control
kFC5_RST_SHIFT_RSTn	Flexcomm Interface 5 reset control
kFC6_RST_SHIFT_RSTn	Flexcomm Interface 6 reset control
kFC7_RST_SHIFT_RSTn	Flexcomm Interface 7 reset control
kFC14_RST_SHIFT_RSTn	Flexcomm Interface 14 reset control
kFC15_RST_SHIFT_RSTn	Flexcomm Interface 15 reset control
kDMIC_RST_SHIFT_RSTn	Digital microphone interface reset control
kOSEVENT_TIMER_RST_SHIFT_RSTn	Osevent Timer reset control
kHSGPIO0_RST_SHIFT_RSTn	HSGPIO 0 reset control
kHSGPIO1_RST_SHIFT_RSTn	HSGPIO 1 reset control
kHSGPIO2_RST_SHIFT_RSTn	HSGPIO 2 reset control
kHSGPIO3_RST_SHIFT_RSTn	HSGPIO 3 reset control
kHSGPIO4_RST_SHIFT_RSTn	HSGPIO 4 reset control
kHSGPIO5_RST_SHIFT_RSTn	HSGPIO 5 reset control
kHSGPIO6_RST_SHIFT_RSTn	HSGPIO 6 reset control
kHSGPIO7_RST_SHIFT_RSTn	HSGPIO 7 reset control
kCRC_RST_SHIFT_RSTn	CRC reset control
kDMAC0_RST_SHIFT_RSTn	DMA Controller 0 reset control
kDMAC1_RST_SHIFT_RSTn	DMA Controller 1 reset control
kMU_RST_SHIFT_RSTn	Message Unit reset control
kSEMA_RST_SHIFT_RSTn	Semaphore reset control
kFREQME_RST_SHIFT_RSTn	Frequency Measure reset control
kCT32B0_RST_SHIFT_RSTn	CT32B0 reset control
kCT32B1_RST_SHIFT_RSTn	CT32B1 reset control
kCT32B2_RST_SHIFT_RSTn	CT32B3 reset control
kCT32B3_RST_SHIFT_RSTn	CT32B4 reset control
kCT32B4_RST_SHIFT_RSTn	CT32B4 reset control
kMRT0_RST_SHIFT_RSTn	Multi-rate timer (MRT) reset control
kWWDT1_RST_SHIFT_RSTn	Windowed Watchdog timer 1 reset control
kI3C0_RST_SHIFT_RSTn	I3C reset control
kPINT_RST_SHIFT_RSTn	GPIO Pin interrupt reset control
kINPUTMUX_RST_SHIFT_RSTn	Peripheral input muxes reset control

Function Documentation

void RESET_SetPeripheralReset

(

reset_ip_name_t

peripheral

)

Asserts reset signal to specified peripheral module.

Parameters

peripheral

Assert reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_ClearPeripheralReset

(

reset_ip_name_t

peripheral

)

Clears reset signal to specified peripheral module, allows it to operate.

Parameters

peripheral

Clear reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_PeripheralReset

(

reset_ip_name_t

peripheral

)

Reset peripheral module.

Parameters

peripheral

Peripheral to reset. The enum argument contains encoding of reset register and reset bit position in the reset register.