Power: Power driver

Overview

The MCUXpresso SDK provides a power driver for the MCUXpresso SDK devices.

Function description

Power driver and library provides these functions:

• Functions to enable and disable power to different peripherals
• Functions to obtain power down config structure with default parameters
• Functions to determine cause of reset
• Functions to get power Library API to return the library version.

Power enable and disable

Power driver provides two API's POWER_EnablePD() and POWER_DisablePD() to enable or disable the PDRUNCFG bits in SYSCON The PDRUNCFG has an inverted logic i.e. the peripheral is powered on when the bit is cleared and powered off when bit is set. So the API POWER_DisablePD() is used to power on a peripheral and POWER_EnablePD() is used to power off a peripheral. The API's take a parameter of type pd_bit_t which organizes the PDRUNCFG bits. The driver also provides two separate API's to power down and power up Flash, POWER_PowerDownFlash() and POWER_PowerUpFlash()

Files
file	fsl_power.h

Data Structures
struct	pm_bod_cfg_t
	BOD config. More...
struct	pm_power_config_t
	Power config. More...

Macros
#define	POWER_BOD_ENABLE   ( 1 << 0 )
	BODVBAT configuration flag.
#define	POWER_BOD_HIGH   ( 1 << 3 )
	ES2 BOD VBAT only.
#define	POWER_BOD_LVL_1_75V   9
	BOD trigger level setting. More...
#define	POWER_BOD_LVL_1_8V   10
	BOD trigger level 1.8V.
#define	POWER_BOD_LVL_1_9V   11
	BOD trigger level 1.9V.
#define	POWER_BOD_LVL_2_0V   12
	BOD trigger level 2.0V.
#define	POWER_BOD_LVL_2_1V   13
	BOD trigger level 2.1V.
#define	POWER_BOD_LVL_2_2V   14
	BOD trigger level 2.2V.
#define	POWER_BOD_LVL_2_3V   15
	BOD trigger level 2.3V.
#define	POWER_BOD_LVL_2_4V   16
	BOD trigger level 2.4V.
#define	POWER_BOD_LVL_2_5V   17
	BOD trigger level 2.5V.
#define	POWER_BOD_LVL_2_6V   18
	BOD trigger level 2.6V.
#define	POWER_BOD_LVL_2_7V   19
	BOD trigger level 2.7V.
#define	POWER_BOD_LVL_2_8V   20
	BOD trigger level 2.8V.
#define	POWER_BOD_LVL_2_9V   21
	BOD trigger level 2.9V.
#define	POWER_BOD_LVL_3_0V   22
	BOD trigger level 3.0V.
#define	POWER_BOD_LVL_3_1V   23
	BOD trigger level 3.1V.
#define	POWER_BOD_LVL_3_2V   24
	BOD trigger level 3.2V.
#define	POWER_BOD_LVL_3_3V   25
	BOD trigger level 3.3V.
#define	POWER_BOD_HYST_25MV   0
	BOD Hysteresis control setting. More...
#define	POWER_BOD_HYST_50MV   1
	BOD Hysteresis control 50mV.
#define	POWER_BOD_HYST_75MV   2
	BOD Hysteresis control 75mV.
#define	POWER_BOD_HYST_100MV   3
	BOD Hysteresis control 100mV, default at Reset.
#define	PM_CFG_SRAM_BANK_BIT_BASE   0
	SRAM banks definition list for retention in power down modes !
#define	PM_CFG_SRAM_BANK0_RET   (1<<0)
	On ES1, this bank shall be kept in retention for Warmstart from power down.
#define	PM_CFG_SRAM_BANK1_RET   (1<<1)
	Bank 1 shall be kept in retention.
#define	PM_CFG_SRAM_BANK2_RET   (1<<2)
	Bank 2 shall be kept in retention.
#define	PM_CFG_SRAM_BANK3_RET   (1<<3)
	Bank 3 shall be kept in retention.
#define	PM_CFG_SRAM_BANK4_RET   (1<<4)
	Bank 4 shall be kept in retention.
#define	PM_CFG_SRAM_BANK5_RET   (1<<5)
	Bank 5 shall be kept in retention.
#define	PM_CFG_SRAM_BANK6_RET   (1<<6)
	Bank 6 shall be kept in retention.
#define	PM_CFG_SRAM_BANK7_RET   (1<<7)
	On ES2, this bank shall be kept in retention for Warmstart.
#define	PM_CFG_SRAM_BANK8_RET   (1<<8)
	Bank 8 shall be kept in retention.
#define	PM_CFG_SRAM_BANK9_RET   (1<<9)
	Bank 9 shall be kept in retention.
#define	PM_CFG_SRAM_BANK10_RET   (1<<10)
	Bank 10 shall be kept in retention.
#define	PM_CFG_SRAM_BANK11_RET   (1<<11)
	Bank 11 shall be kept in retention.
#define	PM_CFG_SRAM_ALL_RETENTION   0xFFF
	All banks shall be kept in retention.
#define	PM_CFG_KEEP_AO_VOLTAGE   (1<<15)
	keep the same voltage on the Always-on power domain - typical used with FRO32K to avoid timebase drift
#define	POWER_WAKEUPSRC_SYSTEM   LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ
	BOD, Watchdog Timer, Flash controller, [DEEP SLEEP] BODVBAT [POWER_DOWN].
#define	POWER_WAKEUPSRC_DMA   LOWPOWER_WAKEUPSRCINT0_DMA_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_GINT   LOWPOWER_WAKEUPSRCINT0_GINT_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_IRBLASTER   LOWPOWER_WAKEUPSRCINT0_IRBLASTER_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PINT0   LOWPOWER_WAKEUPSRCINT0_PINT0_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PINT1   LOWPOWER_WAKEUPSRCINT0_PINT1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PINT2   LOWPOWER_WAKEUPSRCINT0_PINT2_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PINT3   LOWPOWER_WAKEUPSRCINT0_PINT3_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_SPIFI   LOWPOWER_WAKEUPSRCINT0_SPIFI_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_TIMER0   LOWPOWER_WAKEUPSRCINT0_TIMER0_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_TIMER1   LOWPOWER_WAKEUPSRCINT0_TIMER1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_USART0   LOWPOWER_WAKEUPSRCINT0_USART0_IRQ
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_USART1   LOWPOWER_WAKEUPSRCINT0_USART1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_I2C0   LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_I2C1   LOWPOWER_WAKEUPSRCINT0_I2C1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_SPI0   LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_SPI1   LOWPOWER_WAKEUPSRCINT0_SPI1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM0   LOWPOWER_WAKEUPSRCINT0_PWM0_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM1   LOWPOWER_WAKEUPSRCINT0_PWM1_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM2   LOWPOWER_WAKEUPSRCINT0_PWM2_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM3   LOWPOWER_WAKEUPSRCINT0_PWM3_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM4   LOWPOWER_WAKEUPSRCINT0_PWM4_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM5   LOWPOWER_WAKEUPSRCINT0_PWM5_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM6   LOWPOWER_WAKEUPSRCINT0_PWM6_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM7   LOWPOWER_WAKEUPSRCINT0_PWM7_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM8   LOWPOWER_WAKEUPSRCINT0_PWM8_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM9   LOWPOWER_WAKEUPSRCINT0_PWM9_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_PWM10   LOWPOWER_WAKEUPSRCINT0_PWM10_IR
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_I2C2   LOWPOWER_WAKEUPSRCINT0_I2C2_IRQ
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_RTC   LOWPOWER_WAKEUPSRCINT0_RTC_IRQ
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_NFCTAG   LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ
	[DEEP SLEEP, POWER DOWN (ES2 Only), DEEP DOWN (ES2 only)]
#define	POWER_WAKEUPSRC_MAILBOX   LOWPOWER_WAKEUPSRCINT0_MAILBOX_IRQ
	Mailbox, Wake-up from DEEP SLEEP and POWER DOWN low power mode [DEEP SLEEP, POWER DOWN].
#define	POWER_WAKEUPSRC_ADC_SEQA   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQA_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ADC_SEQB   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQB_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ADC_THCMP_OVR   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_THCMP_OVR_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_DMIC   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_DMIC_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_HWVAD   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_HWVAD_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_BLE_DP   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_BLE_DP0   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP0_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_BLE_DP1   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP1_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_BLE_DP2   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP2_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_BLE_LL_ALL   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_LL_ALL_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ZIGBEE_MAC   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MAC_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ZIGBEE_MODEM   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MODEM_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_RFP_TMU   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_TMU_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_RFP_AGC   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_AGC_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ISO7816   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ISO7816_IRQ << 32)
	[DEEP SLEEP]
#define	POWER_WAKEUPSRC_ANA_COMP   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ANA_COMP_IRQ << 32)
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_WAKE_UP_TIMER0   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER0_IRQ << 32)
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_WAKE_UP_TIMER1   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER1_IRQ << 32)
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_BLE_WAKE_TIMER   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_WAKE_TIMER_IRQ << 32)
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_BLE_OSC_EN   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_OSC_EN_IRQ << 32)
	[DEEP SLEEP, POWER DOWN]
#define	POWER_WAKEUPSRC_IO   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_IO_IRQ << 32)
	[POWER DOWN, DEEP DOWN]

Enumerations
enum	pd_bit_t {   kPDRUNCFG_PD_LDO_ADC_EN = 22,   kPDRUNCFG_PD_BOD_MEM_EN = 23,   kPDRUNCFG_PD_BOD_CORE_EN = 24,   kPDRUNCFG_PD_FRO32K_EN = 25,   kPDRUNCFG_PD_XTAL32K_EN = 26,   kPDRUNCFG_PD_BOD_ANA_COMP_EN = 27 }
	PDRUNCFG bits offset. More...
enum	pm_power_mode_t {   PM_POWER_DOWN,   PM_DEEP_DOWN }
	Power modes. More...
enum	reset_cause_t { ,   RESET_POR = (1 << 0),   RESET_EXT_PIN = (1 << 1),   RESET_BOR = (1 << 2),   RESET_SYS_REQ = (1 << 3),   RESET_WDT = (1 << 4),   RESET_WAKE_DEEP_PD = (1 << 5),   RESET_WAKE_PD = (1 << 6),   RESET_SW_REQ = (1 << 7) }
	Reset Cause definition. More...
enum	pm_ldo_volt_t {   PM_LDO_VOLT_1_1V_DEFAULT,   PM_LDO_VOLT_1_0V }
	LDO voltage setting. More...

Power Configuration
void	POWER_Init (void)
	Initialize the sdk power drivers. More...
void	POWER_SetTrimDefaultActiveVoltage (void)
	Optimize the LDO voltage for power saving Initialize the power domains. More...
void	POWER_BodSetUp (void)
	BODMEM and BODCORE setup. More...
void	POWER_BodActivate (void)
	enable SW reset for the BODCORE More...
static void	POWER_EnablePD (pd_bit_t en)
	API to enable PDRUNCFG bit in the Syscon. More...
static void	POWER_DisablePD (pd_bit_t en)
	API to disable PDRUNCFG bit in the Syscon. More...
static uint32_t	POWER_GetIoWakeStatus (void)
	Get IO and Ntag Field detect Wake-up sources from Power Down and Deep Power Down modes. More...
static void	POWER_EnterSleep (void)
	Power API to enter sleep mode (Doze mode) More...
bool	POWER_EnterPowerMode (pm_power_mode_t pm_power_mode, pm_power_config_t *pm_power_config)
	Power Library API to enter different power mode. More...
reset_cause_t	POWER_GetResetCause (void)
	determine cause of reset More...
void	POWER_ClearResetCause (void)
	Clear cause of reset.
uint32_t	POWER_GetLibVersion (void)
	Power Library API to return the library version. More...
void	POWER_BodVbatGetDefaultConfig (pm_bod_cfg_t *bod_cfg_p)
	Get default Vbat BOD config parameters, level @1.75V, Hysteresis @ 100mV. More...
bool	POWER_BodVbatConfig (pm_bod_cfg_t *bod_cfg_p)
	Configure the VBAT BOD. More...
void	POWER_ApplyLdoActiveVoltage (pm_ldo_volt_t ldoVolt)
	Configure the LDO voltage. More...
#define	POWER_ENTER_SLEEP()   __DSB(); __WFI(); __ISB();
	Power API to enter sleep mode (Doze mode) More...

---

Data Structure Documentation

struct pm_bod_cfg_t

Data Fields
uint8_t	bod_level
	BOD trigger level.
uint8_t	bod_hyst
	BOD Hysteresis control.
uint8_t	bod_cfg
	BOD config setting.

struct pm_power_config_t

Data Fields
pm_wake_source_t	pm_wakeup_src
	Wakeup source select.
uint32_t	pm_wakeup_io
	Wakeup IO.
uint32_t	pm_config
	Power mode config.

Macro Definition Documentation

#define POWER_BOD_LVL_1_75V   9

Default at Reset , 1.7V on ES1

#define POWER_BOD_HYST_25MV   0

BOD Hysteresis control 25mV

#define POWER_ENTER_SLEEP

(

)

__DSB(); __WFI(); __ISB();

Note

: The static inline function has not the expecetd effect in -O0. If order to force inline this macro is added

Returns

none

Enumeration Type Documentation

enum pd_bit_t

Enumerator
kPDRUNCFG_PD_LDO_ADC_EN	Offset is 22, LDO ADC enabled.
kPDRUNCFG_PD_BOD_MEM_EN	Offset is 23, BOD MEM enabled.
kPDRUNCFG_PD_BOD_CORE_EN	Offset is 24, BOD CORE enabled.
kPDRUNCFG_PD_FRO32K_EN	Offset is 25, FRO32K enabled.
kPDRUNCFG_PD_XTAL32K_EN	Offset is 26, XTAL32K enabled.
kPDRUNCFG_PD_BOD_ANA_COMP_EN	Offset is 27, Analog Comparator enabled.

enum pm_power_mode_t

Enumerator
PM_POWER_DOWN	Power down mode.
PM_DEEP_DOWN	Deep power down mode.

enum reset_cause_t

Enumerator
RESET_POR	The last chip reset was caused by a Power On Reset.
RESET_EXT_PIN	The last chip reset was caused by a Pad Reset.
RESET_BOR	The last chip reset was caused by a Brown Out Detector.
RESET_SYS_REQ	The last chip reset was caused by a System Reset requested by the ARM CPU.
RESET_WDT	The last chip reset was caused by the Watchdog Timer.
RESET_WAKE_DEEP_PD	The last chip reset was caused by a Wake-up I/O (GPIO or internal NTAG FD INT).
RESET_WAKE_PD	The last CPU reset was caused by a Wake-up from Power down (many sources possible: timer, IO, ...).
RESET_SW_REQ	The last chip reset was caused by a Software. ES2 Only

enum pm_ldo_volt_t

Enumerator
PM_LDO_VOLT_1_1V_DEFAULT	LDO voltage 1.1V.
PM_LDO_VOLT_1_0V	not safe at system start/wakeup and CPU clock switch to higher frequency

Function Documentation

void POWER_Init

(

void

)

Optimize the LDO voltage for power saving Initialize the power domains

Returns

none

void POWER_SetTrimDefaultActiveVoltage

(

void

)

Returns

none

void POWER_BodSetUp

(

void

)

Enable the BOD core and BOD mem Disable the analog comnparator clock

Returns

none

void POWER_BodActivate

(

void

)

Returns

none

static void POWER_EnablePD ( pd_bit_t  en )

inlinestatic

Note that enabling the bit powers down the peripheral

Parameters

en	peripheral for which to enable the PDRUNCFG bit

Returns

none

static void POWER_DisablePD ( pd_bit_t  en )

inlinestatic

Note that disabling the bit powers up the peripheral

Parameters

en	peripheral for which to disable the PDRUNCFG bit

Returns

none

static uint32_t POWER_GetIoWakeStatus ( void  )

inlinestatic

Allow to identify the wake-up source when waking up from Power-Down modes or Deep Power Down modes. Status is reset by POR, RSTN, WDT. bit in range from 0 to 21 are for DIO0 to DIO21 bit 22 is NTAG field detect wakeup source

Returns

IO and Field detect Wake-up source

static void POWER_EnterSleep ( void  )

inlinestatic

Note

: If the user desires to program a wakeup timer before going to sleep, it needs to use either the fsl_wtimer.h API or use the POWER_SetLowPower() API instead see POWER_ENTER_SLEEP

Returns

none

bool POWER_EnterPowerMode	(	pm_power_mode_t	pm_power_mode,
		pm_power_config_t *	pm_power_config
	)

If requested mode is PM_POWER_DOWN, the API will perform the clamping of the DIOs if the PIO register has the bit IO_CLAMPING set: SYSCON->RETENTIONCTRL.IOCLAMP will be set

Parameters

pm_power_mode

Power modes

See Also

pm_power_mode_t

Parameters

pm_power_config

Power config

See Also

pm_power_config_t

Returns

false if chip could not go to sleep. Configuration structure is incorrect

reset_cause_t POWER_GetResetCause

(

void

)

Returns

reset_cause

uint32_t POWER_GetLibVersion

(

void

)

Parameters

none

Returns

version number of the power library

void POWER_BodVbatGetDefaultConfig

(

pm_bod_cfg_t *

bod_cfg_p

)

Parameters

bod_cfg_p

BOD config

See Also

pm_bod_cfg_t

Returns

none

bool POWER_BodVbatConfig

(

pm_bod_cfg_t *

bod_cfg_p

)

Parameters

bod_cfg_p

BOD config

See Also

pm_bod_cfg_t

Returns

false if configuration parameters are incorrect

void POWER_ApplyLdoActiveVoltage

(

pm_ldo_volt_t

ldoVolt

)

Parameters

ldoVolt

LDO voltage setting

See Also

pm_ldo_volt_t

Returns

none