eDMA core Driver

Overview

Data Structures
struct	edma_core_mp_t
	edma core channel struture definition More...
struct	edma_core_channel_t
	edma core channel struture definition More...
struct	edma5_core_tcd_t
	edma5 core TCD struture definition More...
struct	edma4_core_tcd_t
	edma4 core TCD struture definition More...
struct	edma_core_tcd_t
	edma core TCD struture definition More...

Macros
#define	DMA_ERR_DBE_FLAG   DMA_MP_ES_DBE_MASK
	DMA error flag.
#define	DMA_CLEAR_DONE_STATUS(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK)
	get/clear DONE bit
#define	DMA_ENABLE_ERROR_INT(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK)
	enable/disable error interupt
#define	DMA_CLEAR_ERROR_STATUS(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK)
	get/clear error status
#define	DMA_CLEAR_INT_STATUS(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
	get/clear INT status
#define	DMA_ENABLE_MAJOR_INT(base, channel)   (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK)
	enable/dsiable MAJOR/HALF INT
#define	EDMA_TCD_ALIGN_SIZE   (32U)
	EDMA tcd align size.
#define	EDMA_BASE(base)
	EDMA base address convert macro.
#define	EDMA_TCD_TYPE(x)   FSL_FEATURE_EDMA_TCD_TYPEn(x)
	EDMA TCD type macro.
#define	EDMA_TCD_SADDR(tcd, flag)   (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)
	EDMA TCD address convert macro.

Typedefs
typedef edma_core_channel_t	EDMA_ChannelType
	EDMA typedef.

Enumerations
enum	edma_tcd_type_t {   kEDMA_EDMA4Flag = 0x0U,   kEDMA_EDMA5Flag = 0x1U }
	eDMA tcd flag type More...

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Data Structure Documentation

struct edma_core_mp_t

Data Fields
__IO uint32_t	MP_CSR
__IO uint32_t	MP_ES
__IO uint32_t	MP_INT_LOW
__I uint32_t	MP_INT_HIGH
__I uint32_t	MP_HRS_LOW
__I uint32_t	MP_HRS_HIGH
__IO uint32_t	MP_STOPCH
__I uint32_t	MP_SSR_LOW
__I uint32_t	MP_SSR_HIGH
__IO uint32_t	CH_GRPRI [64]
__IO uint32_t	CH_MUX [64]
__IO uint32_t	CH_PROT [64]

Field Documentation

__IO uint32_t edma_core_mp_t::MP_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t edma_core_mp_t::MP_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t edma_core_mp_t::MP_INT_LOW

Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t edma_core_mp_t::MP_INT_HIGH

Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t edma_core_mp_t::MP_HRS_LOW

Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t edma_core_mp_t::MP_HRS_HIGH

Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t edma_core_mp_t::MP_STOPCH

Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t edma_core_mp_t::MP_SSR_LOW

Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t edma_core_mp_t::MP_SSR_HIGH

Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t edma_core_mp_t::CH_GRPRI[64]

Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t edma_core_mp_t::CH_MUX[64]

Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t edma_core_mp_t::CH_PROT[64]

Channel Control and Status, array offset: 0x10400, array step: 0x10000

struct edma_core_channel_t

Data Fields
__IO uint32_t	CH_CSR
__IO uint32_t	CH_ES
__IO uint32_t	CH_INT
__IO uint32_t	CH_SBR
__IO uint32_t	CH_PRI
__IO uint32_t	CH_MATTR
__IO uint32_t	CH_MUX
__IO uint16_t	CH_MATTR

Field Documentation

__IO uint32_t edma_core_channel_t::CH_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t edma_core_channel_t::CH_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t edma_core_channel_t::CH_INT

Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t edma_core_channel_t::CH_SBR

Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t edma_core_channel_t::CH_PRI

Channel Priority, array offset: 0x10010, array step: 0x10000

__IO uint32_t edma_core_channel_t::CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

__IO uint32_t edma_core_channel_t::CH_MUX

Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t edma_core_channel_t::CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct edma5_core_tcd_t

Data Fields
__IO uint32_t	SADDR
	SADDR register, used to save source address.
__IO uint32_t	SADDR_HIGH
	SADDR HIGH register, used to save source address.
__IO uint16_t	SOFF
	SOFF register, save offset bytes every transfer.
__IO uint16_t	ATTR
	ATTR register, source/destination transfer size and modulo.
__IO uint32_t	NBYTES
	Nbytes register, minor loop length in bytes.
__IO uint32_t	SLAST
	SLAST register.
__IO uint32_t	SLAST_SDA_HIGH
	SLAST SDA HIGH register.
__IO uint32_t	DADDR
	DADDR register, used for destination address.
__IO uint32_t	DADDR_HIGH
	DADDR HIGH register, used for destination address.
__IO uint32_t	DLAST_SGA
	DLASTSGA register, next tcd address used in scatter-gather mode.
__IO uint32_t	DLAST_SGA_HIGH
	DLASTSGA HIGH register, next tcd address used in scatter-gather mode.
__IO uint16_t	DOFF
	DOFF register, used for destination offset.
__IO uint16_t	CITER
	CITER register, current minor loop numbers, for unfinished minor loop. More...
__IO uint16_t	CSR
	CSR register, for TCD control status.
__IO uint16_t	BITER
	BITER register, begin minor loop count. More...
uint8_t	RESERVED [16]
	Aligned 64 bytes.

Field Documentation

__IO uint16_t edma5_core_tcd_t::CITER

__IO uint16_t edma5_core_tcd_t::BITER

struct edma4_core_tcd_t

Data Fields
__IO uint32_t	SADDR
	SADDR register, used to save source address.
__IO uint16_t	SOFF
	SOFF register, save offset bytes every transfer.
__IO uint16_t	ATTR
	ATTR register, source/destination transfer size and modulo.
__IO uint32_t	NBYTES
	Nbytes register, minor loop length in bytes.
__IO uint32_t	SLAST
	SLAST register.
__IO uint32_t	DADDR
	DADDR register, used for destination address.
__IO uint16_t	DOFF
	DOFF register, used for destination offset.
__IO uint16_t	CITER
	CITER register, current minor loop numbers, for unfinished minor loop. More...
__IO uint32_t	DLAST_SGA
	DLASTSGA register, next tcd address used in scatter-gather mode.
__IO uint16_t	CSR
	CSR register, for TCD control status.
__IO uint16_t	BITER
	BITER register, begin minor loop count. More...

Field Documentation

__IO uint16_t edma4_core_tcd_t::CITER

__IO uint16_t edma4_core_tcd_t::BITER

struct edma_core_tcd_t

Enumeration Type Documentation

enum edma_tcd_type_t

Enumerator
kEDMA_EDMA4Flag	Data access for eDMA4 transfers.
kEDMA_EDMA5Flag	Instruction access for eDMA4 transfers.