CACHE: LMEM CACHE Memory Controller

Overview

The MCUXpresso SDK provides a peripheral driver for the CACHE Controller of MCUXpresso SDK devices.

The CACHE driver is created to help the user more easily operate the cache memory. The APIs for basic operations are including the following three levels: 1L. The L1 cache driver API. This level provides the level 1 caches controller drivers. The L1 caches in this arch is the previous the local memory controller (LMEM).

2L. The unified cache driver API. This level provides many APIs for unified cache driver APIs for combined L1 and L2 cache maintain operations. This is provided for SDK drivers (DMA, ENET, USDHC, etc) which should do the cache maintenance in their transactional APIs. Because in this arch, there is no L2 cache so the unified cache driver API directly calls only L1 driver APIs.

Function groups

L1 CACHE Operation

The L1 CACHE has both code cache and data cache. This function group provides two independent API groups for both code cache and data cache. There are Enable/Disable APIs for code cache and data cache control and cache maintenance operations as Invalidate/Clean/CleanInvalidate by all and by address range.

Macros
#define	L1CODEBUSCACHE_LINESIZE_BYTE   FSL_FEATURE_L1ICACHE_LINESIZE_BYTE
	code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. More...
#define	L1SYSTEMBUSCACHE_LINESIZE_BYTE   L1CODEBUSCACHE_LINESIZE_BYTE
	The system bus CACHE line size is 16B = 128b. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 6))
	cache driver version. More...

Unified Cache Control for all caches
static void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates instruction cache by range. More...
static void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates data cache by range. More...
static void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Clean data cache by range. More...
static void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates data cache by range. More...

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 6))

#define L1CODEBUSCACHE_LINESIZE_BYTE   FSL_FEATURE_L1ICACHE_LINESIZE_BYTE

The code bus CACHE line size is 16B = 128b.

#define L1SYSTEMBUSCACHE_LINESIZE_BYTE   L1CODEBUSCACHE_LINESIZE_BYTE

Function Documentation

static void ICACHE_InvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_InvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanInvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be Cleaned and Invalidated.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.