Overview

Reset driver supports peripheral reset and system reset.

Macros
#define	ADC_RSTS

Enumerations
enum	SYSCON_RSTn_t { kFMU_RST_SHIFT_RSTn = 0 \| 9U, kFLEXSPI_RST_SHIFT_RSTn = 0 \| 11U, kMUX_RST_SHIFT_RSTn = 0 \| 12U, kPORT0_RST_SHIFT_RSTn = 0 \| 13U, kPORT1_RST_SHIFT_RSTn = 0 \| 14U, kPORT2_RST_SHIFT_RSTn = 0 \| 15U, kPORT3_RST_SHIFT_RSTn = 0 \| 16U, kPORT4_RST_SHIFT_RSTn = 0 \| 17U, kGPIO0_RST_SHIFT_RSTn = 0 \| 19U, kGPIO1_RST_SHIFT_RSTn = 0 \| 20U, kGPIO2_RST_SHIFT_RSTn = 0 \| 21U, kGPIO3_RST_SHIFT_RSTn = 0 \| 22U, kGPIO4_RST_SHIFT_RSTn = 0 \| 23U, kPINT_RST_SHIFT_RSTn = 0 \| 25U, kDMA0_RST_SHIFT_RSTn = 0 \| 26U, kCRC_RST_SHIFT_RSTn = 0 \| 27U, kMAILBOX_RST_SHIFT_RSTn = 0 \| 31U, kMRT_RST_SHIFT_RSTn = 65536 \| 0U, kOSTIMER_RST_SHIFT_RSTn = 65536 \| 1U, kSCT_RST_SHIFT_RSTn = 65536 \| 2U, kADC0_RST_SHIFT_RSTn = 65536 \| 3U, kADC1_RST_SHIFT_RSTn = 65536 \| 4U, kDAC0_RST_SHIFT_RSTn = 65536 \| 5U, kEVSIM0_RST_SHIFT_RSTn = 65536 \| 8U, kEVSIM1_RST_SHIFT_RSTn = 65536 \| 9U, kUTICK_RST_SHIFT_RSTn = 65536 \| 10U, kFC0_RST_SHIFT_RSTn = 65536 \| 11U, kFC1_RST_SHIFT_RSTn = 65536 \| 12U, kFC2_RST_SHIFT_RSTn = 65536 \| 13U, kFC3_RST_SHIFT_RSTn = 65536 \| 14U, kFC4_RST_SHIFT_RSTn = 65536 \| 15U, kFC5_RST_SHIFT_RSTn = 65536 \| 16U, kFC6_RST_SHIFT_RSTn = 65536 \| 17U, kFC7_RST_SHIFT_RSTn = 65536 \| 18U, kFC8_RST_SHIFT_RSTn = 65536 \| 19U, kFC9_RST_SHIFT_RSTn = 65536 \| 20U, kMICFIL_RST_SHIFT_RSTn = 65536 \| 21U, kCTIMER2_RST_SHIFT_RSTn = 65536 \| 22U, kUSB0_RAM_RST_SHIFT_RSTn = 65536 \| 23U, kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 \| 24U, kUSB0_FS_RST_SHIFT_RSTn = 65536 \| 25U, kCTIMER0_RST_SHIFT_RSTn = 65536 \| 26U, kCTIMER1_RST_SHIFT_RSTn = 65536 \| 27U, kSMART_DMA_RST_SHIFT_RSTn = 65536 \| 31U, kDMA1_RST_SHIFT_RSTn = 131072 \| 1U, kENET_RST_SHIFT_RSTn = 131072 \| 2U, kUSDHC_RST_SHIFT_RSTn = 131072 \| 3U, kFLEXIO_RST_SHIFT_RSTn = 131072 \| 4U, kSAI0_RST_SHIFT_RSTn = 131072 \| 5U, kSAI1_RST_SHIFT_RSTn = 131072 \| 6U, kTRO_RST_SHIFT_RSTn = 131072 \| 7U, kFREQME_RST_SHIFT_RSTn = 131072 \| 8U, kTRNG_RST_SHIFT_RSTn = 131072 \| 13U, kFLEXCAN0_RST_SHIFT_RSTn = 131072 \| 14U, kFLEXCAN1_RST_SHIFT_RSTn = 131072 \| 15U, kUSB_HS_RST_SHIFT_RSTn = 131072 \| 16U, kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 \| 17U, kPOWERQUAD_RST_SHIFT_RSTn = 131072 \| 19U, kPLU_RST_SHIFT_RSTn = 131072 \| 20U, kCTIMER3_RST_SHIFT_RSTn = 131072 \| 21U, kCTIMER4_RST_SHIFT_RSTn = 131072 \| 22U, kPUF_RST_SHIFT_RSTn = 131072 \| 23U, kPKC_RST_SHIFT_RSTn = 131072 \| 24U, kSM3_RST_SHIFT_RSTn = 131072 \| 30U, kI3C0_RST_SHIFT_RSTn = 196608 \| 0U, kI3C1_RST_SHIFT_RSTn = 196608 \| 1U, kSINC_RST_SHIFT_RSTn = 196608 \| 2U, kCOOLFLUX_RST_SHIFT_RSTn = 196608 \| 3U, kQDC0_RST_SHIFT_RSTn = 196608 \| 4U, kQDC1_RST_SHIFT_RSTn = 196608 \| 5U, kPWM0_RST_SHIFT_RSTn = 196608 \| 6U, kPWM1_RST_SHIFT_RSTn = 196608 \| 7U, kAOI0_RST_SHIFT_RSTn = 196608 \| 8U, kDAC1_RST_SHIFT_RSTn = 196608 \| 11U, kDAC2_RST_SHIFT_RSTn = 196608 \| 12U, kOPAMP0_RST_SHIFT_RSTn = 196608 \| 13U, kOPAMP1_RST_SHIFT_RSTn = 196608 \| 14U, kOPAMP2_RST_SHIFT_RSTn = 196608 \| 15U, kCMP2_RST_SHIFT_RSTn = 196608 \| 18U, kVREF_RST_SHIFT_RSTn = 196608 \| 19U, kCOOLFLUX_APB_RST_SHIFT_RSTn = 196608 \| 20U, kNEUTRON_RST_SHIFT_RSTn = 196608 \| 21U, kTSI_RST_SHIFT_RSTn = 196608 \| 22U, kEWM_RST_SHIFT_RSTn = 196608 \| 23U, kEIM_RST_SHIFT_RSTn = 196608 \| 24U, kSEMA42_RST_SHIFT_RSTn = 196608 \| 27U }
	Enumeration for peripheral reset control bits. More...

Functions
void	RESET_SetPeripheralReset (reset_ip_name_t peripheral)
	Assert reset to peripheral. More...

void	RESET_ClearPeripheralReset (reset_ip_name_t peripheral)
	Clear reset to peripheral. More...

void	RESET_PeripheralReset (reset_ip_name_t peripheral)
	Reset peripheral module. More...

static void	RESET_ReleasePeripheralReset (reset_ip_name_t peripheral)
	Release peripheral module. More...

Driver version
#define	FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
	reset driver version 2.4.0

Macro Definition Documentation

#define ADC_RSTS

Value:

{                                              \
        kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
    } /* Reset bits for ADC peripheral */

Array initializers with peripheral reset bits

Enumeration Type Documentation

enum SYSCON_RSTn_t

Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers

Enumerator
kFMU_RST_SHIFT_RSTn	Flash management unit reset control
kFLEXSPI_RST_SHIFT_RSTn	FLEXSPI reset control
kMUX_RST_SHIFT_RSTn	Input mux reset control
kPORT0_RST_SHIFT_RSTn	PORT0 reset control
kPORT1_RST_SHIFT_RSTn	PORT1 reset control
kPORT2_RST_SHIFT_RSTn	PORT2 reset control
kPORT3_RST_SHIFT_RSTn	PORT3 reset control
kPORT4_RST_SHIFT_RSTn	PORT4 reset control
kGPIO0_RST_SHIFT_RSTn	GPIO0 reset control
kGPIO1_RST_SHIFT_RSTn	GPIO1 reset control
kGPIO2_RST_SHIFT_RSTn	GPIO2 reset control
kGPIO3_RST_SHIFT_RSTn	GPIO3 reset control
kGPIO4_RST_SHIFT_RSTn	GPIO4 reset control
kPINT_RST_SHIFT_RSTn	Pin interrupt (PINT) reset control
kDMA0_RST_SHIFT_RSTn	DMA0 reset control
kCRC_RST_SHIFT_RSTn	CRC reset control
kMAILBOX_RST_SHIFT_RSTn	Mailbox reset control
kMRT_RST_SHIFT_RSTn	Multi-rate timer (MRT) reset control
kOSTIMER_RST_SHIFT_RSTn	OSTimer reset control
kSCT_RST_SHIFT_RSTn	SCTimer/PWM(SCT) reset control
kADC0_RST_SHIFT_RSTn	ADC0 reset control
kADC1_RST_SHIFT_RSTn	ADC1 reset control
kDAC0_RST_SHIFT_RSTn	DAC0 reset control
kEVSIM0_RST_SHIFT_RSTn	EVSIM0 reset control
kEVSIM1_RST_SHIFT_RSTn	EVSIM1 reset control
kUTICK_RST_SHIFT_RSTn	Micro-tick timer reset control
kFC0_RST_SHIFT_RSTn	Flexcomm Interface 0 reset control
kFC1_RST_SHIFT_RSTn	Flexcomm Interface 1 reset control
kFC2_RST_SHIFT_RSTn	Flexcomm Interface 2 reset control
kFC3_RST_SHIFT_RSTn	Flexcomm Interface 3 reset control
kFC4_RST_SHIFT_RSTn	Flexcomm Interface 4 reset control
kFC5_RST_SHIFT_RSTn	Flexcomm Interface 5 reset control
kFC6_RST_SHIFT_RSTn	Flexcomm Interface 6 reset control
kFC7_RST_SHIFT_RSTn	Flexcomm Interface 7 reset control
kFC8_RST_SHIFT_RSTn	Flexcomm Interface 8 reset control
kFC9_RST_SHIFT_RSTn	MICFIL reset control
kMICFIL_RST_SHIFT_RSTn	Flexcomm Interface 7 reset control
kCTIMER2_RST_SHIFT_RSTn	CTimer 2 reset control
kUSB0_RAM_RST_SHIFT_RSTn	USB0 RAM reset control
kUSB0_FS_DCD_RST_SHIFT_RSTn	USB0-FS DCD reset control
kUSB0_FS_RST_SHIFT_RSTn	USB0-FS reset control
kCTIMER0_RST_SHIFT_RSTn	CTimer 0 reset control
kCTIMER1_RST_SHIFT_RSTn	CTimer 1 reset control
kSMART_DMA_RST_SHIFT_RSTn	SmartDMA reset control
kDMA1_RST_SHIFT_RSTn	DMA1 reset control
kENET_RST_SHIFT_RSTn	Ethernet reset control
kUSDHC_RST_SHIFT_RSTn	uSDHC reset control
kFLEXIO_RST_SHIFT_RSTn	FLEXIO reset control
kSAI0_RST_SHIFT_RSTn	SAI0 reset control
kSAI1_RST_SHIFT_RSTn	SAI1 reset control
kTRO_RST_SHIFT_RSTn	TRO reset control
kFREQME_RST_SHIFT_RSTn	FREQME reset control
kTRNG_RST_SHIFT_RSTn	TRNG reset control
kFLEXCAN0_RST_SHIFT_RSTn	Flexcan0 reset control
kFLEXCAN1_RST_SHIFT_RSTn	Flexcan1 reset control
kUSB_HS_RST_SHIFT_RSTn	USB HS reset control
kUSB_HS_PHY_RST_SHIFT_RSTn	USB HS PHY reset control
kPOWERQUAD_RST_SHIFT_RSTn	PowerQuad reset control
kPLU_RST_SHIFT_RSTn	PLU reset control
kCTIMER3_RST_SHIFT_RSTn	CTimer 3 reset control
kCTIMER4_RST_SHIFT_RSTn	CTimer 4 reset control
kPUF_RST_SHIFT_RSTn	PUF reset control
kPKC_RST_SHIFT_RSTn	PKC reset control
kSM3_RST_SHIFT_RSTn	SM3 reset control
kI3C0_RST_SHIFT_RSTn	I3C0 reset control
kI3C1_RST_SHIFT_RSTn	I3C1 reset control
kSINC_RST_SHIFT_RSTn	SINC reset control
kCOOLFLUX_RST_SHIFT_RSTn	CoolFlux reset control
kQDC0_RST_SHIFT_RSTn	QDC0 reset control
kQDC1_RST_SHIFT_RSTn	QDC1 reset control
kPWM0_RST_SHIFT_RSTn	PWM0 reset control
kPWM1_RST_SHIFT_RSTn	PWM1 reset control
kAOI0_RST_SHIFT_RSTn	AOI0 reset control
kDAC1_RST_SHIFT_RSTn	DAC1 reset control
kDAC2_RST_SHIFT_RSTn	DAC2 reset control
kOPAMP0_RST_SHIFT_RSTn	OPAMP0 reset control
kOPAMP1_RST_SHIFT_RSTn	OPAMP1 reset control
kOPAMP2_RST_SHIFT_RSTn	OPAMP2 reset control
kCMP2_RST_SHIFT_RSTn	CMP2 reset control
kVREF_RST_SHIFT_RSTn	VREF reset control
kCOOLFLUX_APB_RST_SHIFT_RSTn	CoolFlux APB reset control
kNEUTRON_RST_SHIFT_RSTn	Neutron mini reset control
kTSI_RST_SHIFT_RSTn	TSI reset control
kEWM_RST_SHIFT_RSTn	EWM reset control
kEIM_RST_SHIFT_RSTn	EIM reset control
kSEMA42_RST_SHIFT_RSTn	Semaphore reset control

Function Documentation

void RESET_SetPeripheralReset ( reset_ip_name_t peripheral )

Asserts reset signal to specified peripheral module.

Parameters

peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_ClearPeripheralReset ( reset_ip_name_t peripheral )

Clears reset signal to specified peripheral module, allows it to operate.

Parameters

peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_PeripheralReset ( reset_ip_name_t peripheral )

Reset peripheral module.

Parameters

peripheral Peripheral to reset. The enum argument contains encoding of reset register and reset bit position in the reset register.

static void RESET_ReleasePeripheralReset ( reset_ip_name_t peripheral )

inlinestatic

Release peripheral module.

Parameters

peripheral Peripheral to release. The enum argument contains encoding of reset register and reset bit position in the reset register.

Overview

Macros

Enumerations

Functions

Driver version

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation