Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	_pll_config
	PLL configuration structure. More...

struct	_pll_setup
	PLL setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...

struct	_usb_pll_setup
	PLL setup structure This structure can be used to pre-build a USB PLL setup configuration at run-time and quickly set the usb PLL to the configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
	User-defined the size of cache for CLOCK_PllGetConfig() function. More...

#define	CLOCK_FROHF_SETTING_API_ROM_ADDRESS (0x030091DFU)
	FROHF clock setting API address in ROM. More...

#define	set_fro_frequency(iFreq) (((void ()(uint32_t iFreq))(CLOCK_FROHF_SETTING_API_ROM_ADDRESS)))(iFreq)

#define	ADC_CLOCKS
	Clock ip name array for ROM. More...

#define	ROM_CLOCKS
	Clock ip name array for ROM. More...

#define	SRAM_CLOCKS
	Clock ip name array for SRAM. More...

#define	FLASH_CLOCKS
	Clock ip name array for FLASH. More...

#define	FMC_CLOCKS
	Clock ip name array for FMC. More...

#define	EEPROM_CLOCKS
	Clock ip name array for EEPROM. More...

#define	SPIFI_CLOCKS
	Clock ip name array for SPIFI. More...

#define	INPUTMUX_CLOCKS
	Clock ip name array for INPUTMUX. More...

#define	IOCON_CLOCKS
	Clock ip name array for IOCON. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	PINT_CLOCKS
	Clock ip name array for PINT. More...

#define	GINT_CLOCKS
	Clock ip name array for GINT. More...

#define	DMA_CLOCKS
	Clock ip name array for DMA. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	WWDT_CLOCKS
	Clock ip name array for WWDT. More...

#define	RTC_CLOCKS
	Clock ip name array for RTC. More...

#define	ADC0_CLOCKS
	Clock ip name array for ADC0. More...

#define	MRT_CLOCKS
	Clock ip name array for MRT. More...

#define	RIT_CLOCKS
	Clock ip name array for RIT. More...

#define	SCT_CLOCKS
	Clock ip name array for SCT0. More...

#define	MCAN_CLOCKS
	Clock ip name array for MCAN. More...

#define	UTICK_CLOCKS
	Clock ip name array for UTICK. More...

#define	FLEXCOMM_CLOCKS
	Clock ip name array for FLEXCOMM. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	BI2C_CLOCKS
	Clock ip name array for BI2C. More...

#define	LPSI_CLOCKS
	Clock ip name array for LSPI. More...

#define	FLEXI2S_CLOCKS
	Clock ip name array for FLEXI2S. More...

#define	DMIC_CLOCKS
	Clock ip name array for DMIC. More...

#define	CTIMER_CLOCKS
	Clock ip name array for CT32B. More...

#define	LCD_CLOCKS
	Clock ip name array for LCD. More...

#define	SDIO_CLOCKS
	Clock ip name array for SDIO. More...

#define	USBRAM_CLOCKS
	Clock ip name array for USBRAM. More...

#define	EMC_CLOCKS
	Clock ip name array for EMC. More...

#define	ETH_CLOCKS
	Clock ip name array for ETH. More...

#define	AES_CLOCKS
	Clock ip name array for AES. More...

#define	OTP_CLOCKS
	Clock ip name array for OTP. More...

#define	RNG_CLOCKS
	Clock ip name array for RNG. More...

#define	USBHMR0_CLOCKS
	Clock ip name array for USBHMR0. More...

#define	USBHSL0_CLOCKS
	Clock ip name array for USBHSL0. More...

#define	SHA0_CLOCKS
	Clock ip name array for SHA0. More...

#define	SMARTCARD_CLOCKS
	Clock ip name array for SMARTCARD. More...

#define	USBD_CLOCKS
	Clock ip name array for USBD. More...

#define	USBH_CLOCKS
	Clock ip name array for USBH. More...

#define	CLK_GATE_REG_OFFSET_SHIFT 8U
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

#define	CLK_ATTACH_ID(mux, sel, pos) ((((mux) << 0U) \| (((sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
	Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards. More...

#define	PLL_CONFIGFLAG_USEINRATE (1UL << 0U)
	PLL configuration structure flags for 'flags' field These flags control how the PLL configuration function sets up the PLL setup structure. More...

#define	PLL_CONFIGFLAG_FORCENOFRACT
	Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ hardware.

#define	PLL_SETUPFLAG_POWERUP (1UL << 0U)
	PLL setup structure flags for 'flags' field These flags control how the PLL setup function sets up the PLL. More...

#define	PLL_SETUPFLAG_WAITLOCK (1UL << 1U)
	Setup will wait for PLL lock, implies the PLL will be pwoered on.

#define	PLL_SETUPFLAG_ADGVOLT (1UL << 2U)
	Optimize system voltage for the new PLL rate.

Typedefs
typedef enum _clock_ip_name	clock_ip_name_t
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...

typedef enum _async_clock_src	async_clock_src_t
	Clock source selections for the asynchronous APB clock.

typedef enum _clock_attach_id	clock_attach_id_t
	The enumerator of clock attach Id.

typedef enum _clock_div_name	clock_div_name_t
	Clock dividers.

typedef enum _clock_flashtim	clock_flashtim_t
	FLASH Access time definitions.

typedef struct _pll_config	pll_config_t
	PLL configuration structure. More...

typedef struct _pll_setup	pll_setup_t
	PLL setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...

typedef enum _pll_error	pll_error_t
	PLL status definitions.

typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...

typedef enum _usb_pll_psel	usb_pll_psel
	USB PDEL Divider. More...

typedef struct _usb_pll_setup	usb_pll_setup_t
	PLL setup structure This structure can be used to pre-build a USB PLL setup configuration at run-time and quickly set the usb PLL to the configuration. More...

Enumerations
enum	_clock_ip_name { kCLOCK_IpInvalid = 0U, kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) }
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

enum	_clock_name { kCLOCK_CoreSysClk, kCLOCK_BusClk, kCLOCK_ClockOut, kCLOCK_FroHf, kCLOCK_UsbPll, kCLOCK_Mclk, kCLOCK_Fro12M, kCLOCK_ExtClk, kCLOCK_PllOut, kCLOCK_UsbClk, kCLOCK_WdtOsc, kCLOCK_Frg, kCLOCK_AsyncApbClk, kCLOCK_FlexI2S }
	Clock name used to get clock frequency. More...

enum	_async_clock_src { kCLOCK_AsyncMainClk = 0, kCLOCK_AsyncFro12Mhz, kCLOCK_AsyncAudioPllClk, kCLOCK_AsyncI2cClkFc6 }
	Clock source selections for the asynchronous APB clock. More...

enum	_clock_attach_id { kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 0, 0), kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) \| MUX_B(CM_MAINCLKSELB, 0, 0), kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) \| MUX_B(CM_MAINCLKSELB, 0, 0), kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) \| MUX_B(CM_MAINCLKSELB, 0, 0), kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 2, 0), kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) \| MUX_B(CM_MAINCLKSELB, 3, 0), kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), kNONE_to_NONE = (int)0x80000000U }
	The enumerator of clock attach Id. More...

enum	_clock_div_name { kCLOCK_DivSystickClk = 0, kCLOCK_DivArmTrClkDiv = 1, kCLOCK_DivCan0Clk = 2, kCLOCK_DivCan1Clk = 3, kCLOCK_DivSmartCard0Clk = 4, kCLOCK_DivSmartCard1Clk = 5, kCLOCK_DivAhbClk = 32, kCLOCK_DivClkOut = 33, kCLOCK_DivFrohfClk = 34, kCLOCK_DivSpifiClk = 36, kCLOCK_DivAdcAsyncClk = 37, kCLOCK_DivUsb0Clk = 38, kCLOCK_DivUsb1Clk = 39, kCLOCK_DivFrg = 40, kCLOCK_DivDmicClk = 42, kCLOCK_DivMClk = 43, kCLOCK_DivLcdClk = 44, kCLOCK_DivSctClk = 45, kCLOCK_DivEmcClk = 46, kCLOCK_DivSdioClk = 47 }
	Clock dividers. More...

enum	_clock_flashtim { kCLOCK_Flash1Cycle = 0U, kCLOCK_Flash2Cycle, kCLOCK_Flash3Cycle, kCLOCK_Flash4Cycle, kCLOCK_Flash5Cycle, kCLOCK_Flash6Cycle, kCLOCK_Flash7Cycle, kCLOCK_Flash8Cycle, kCLOCK_Flash9Cycle }
	FLASH Access time definitions. More...

enum	_pll_error { kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) }
	PLL status definitions. More...

enum	_clock_usb_src { kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, kCLOCK_UsbSrcNone }
	USB clock source definition. More...

enum	_usb_pll_psel
	USB PDEL Divider. More...

Functions
static void	CLOCK_SetFLASHAccessCycles (clock_flashtim_t clks)
	Set FLASH memory access time in clocks. More...

status_t	CLOCK_SetupFROClocking (uint32_t iFreq)
	Initialize the Core clock to given frequency (12, 48 or 96 MHz). Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is enabled. More...

void	CLOCK_AttachClk (clock_attach_id_t connection)
	Configure the clock selection muxes. More...

clock_attach_id_t	CLOCK_GetClockAttachId (clock_attach_id_t attachId)
	Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id. More...

void	CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
	Setup peripheral clock dividers. More...

void	CLOCK_SetFLASHAccessCyclesForFreq (uint32_t iFreq)
	Set the flash wait states for the input freuqency. More...

uint32_t	CLOCK_SetFRGClock (uint32_t freq)
	Set the frg output frequency. More...

uint32_t	CLOCK_GetFRGInputClock (void)
	Return Frequency of FRG input clock. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Return Frequency of selected clock. More...

uint32_t	CLOCK_GetFro12MFreq (void)
	Return Frequency of FRO 12MHz. More...

uint32_t	CLOCK_GetClockOutClkFreq (void)
	Return Frequency of ClockOut. More...

uint32_t	CLOCK_GetSpifiClkFreq (void)
	Return Frequency of Spifi Clock. More...

uint32_t	CLOCK_GetAdcClkFreq (void)
	Return Frequency of Adc Clock. More...

uint32_t	CLOCK_GetMCanClkFreq (uint32_t MCanSel)
	brief Return Frequency of MCAN Clock param MCanSel : 0U: MCAN0; 1U: MCAN1 return Frequency of MCAN Clock

uint32_t	CLOCK_GetUsb0ClkFreq (void)
	Return Frequency of Usb0 Clock. More...

uint32_t	CLOCK_GetUsb1ClkFreq (void)
	Return Frequency of Usb1 Clock. More...

uint32_t	CLOCK_GetMclkClkFreq (void)
	Return Frequency of MClk Clock. More...

uint32_t	CLOCK_GetSctClkFreq (void)
	Return Frequency of SCTimer Clock. More...

uint32_t	CLOCK_GetSdioClkFreq (void)
	Return Frequency of SDIO Clock. More...

uint32_t	CLOCK_GetLcdClkFreq (void)
	Return Frequency of LCD Clock. More...

uint32_t	CLOCK_GetLcdClkIn (void)
	Return Frequency of LCD CLKIN Clock. More...

uint32_t	CLOCK_GetExtClkFreq (void)
	Return Frequency of External Clock. More...

uint32_t	CLOCK_GetWdtOscFreq (void)
	Return Frequency of Watchdog Oscillator. More...

uint32_t	CLOCK_GetFroHfFreq (void)
	Return Frequency of High-Freq output of FRO. More...

uint32_t	CLOCK_GetFrgClkFreq (void)
	Return Frequency of frg. More...

uint32_t	CLOCK_GetDmicClkFreq (void)
	Return Frequency of dmic. More...

uint32_t	CLOCK_GetPllOutFreq (void)
	Return Frequency of PLL. More...

uint32_t	CLOCK_GetUsbPllOutFreq (void)
	Return Frequency of USB PLL. More...

uint32_t	CLOCK_GetAudioPllOutFreq (void)
	Return Frequency of AUDIO PLL. More...

uint32_t	CLOCK_GetOsc32KFreq (void)
	Return Frequency of 32kHz osc. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Return Frequency of Core System. More...

uint32_t	CLOCK_GetI2SMClkFreq (void)
	Return Frequency of I2S MCLK Clock. More...

uint32_t	CLOCK_GetFlexCommClkFreq (uint32_t id)
	Return Frequency of Flexcomm functional Clock. More...

__STATIC_INLINE async_clock_src_t	CLOCK_GetAsyncApbClkSrc (void)
	Return Asynchronous APB Clock source. More...

uint32_t	CLOCK_GetAsyncApbClkFreq (void)
	Return Frequency of Asynchronous APB Clock. More...

__STATIC_INLINE uint32_t	CLOCK_GetEmcClkFreq (void)
	Return EMC source. More...

uint32_t	CLOCK_GetAudioPLLInClockRate (void)
	Return Audio PLL input clock rate. More...

uint32_t	CLOCK_GetSystemPLLInClockRate (void)
	Return System PLL input clock rate. More...

uint32_t	CLOCK_GetSystemPLLOutClockRate (bool recompute)
	Return System PLL output clock rate. More...

uint32_t	CLOCK_GetAudioPLLOutClockRate (bool recompute)
	Return System AUDIO PLL output clock rate. More...

uint32_t	CLOCK_GetUsbPLLOutClockRate (bool recompute)
	Return System USB PLL output clock rate. More...

__STATIC_INLINE void	CLOCK_SetBypassPLL (bool bypass)
	Enables and disables PLL bypass mode. More...

__STATIC_INLINE bool	CLOCK_IsSystemPLLLocked (void)
	Check if PLL is locked or not. More...

__STATIC_INLINE bool	CLOCK_IsUsbPLLLocked (void)
	Check if USB PLL is locked or not. More...

__STATIC_INLINE bool	CLOCK_IsAudioPLLLocked (void)
	Check if AUDIO PLL is locked or not. More...

__STATIC_INLINE void	CLOCK_Enable_SysOsc (bool enable)
	Enables and disables SYS OSC. More...

void	CLOCK_SetStoredPLLClockRate (uint32_t rate)
	Store the current PLL rate. More...

void	CLOCK_SetStoredAudioPLLClockRate (uint32_t rate)
	Store the current AUDIO PLL rate. More...

uint32_t	CLOCK_GetSystemPLLOutFromSetup (pll_setup_t *pSetup)
	Return System PLL output clock rate from setup structure. More...

uint32_t	CLOCK_GetAudioPLLOutFromSetup (pll_setup_t *pSetup)
	Return System AUDIO PLL output clock rate from setup structure. More...

uint32_t	CLOCK_GetAudioPLLOutFromFractSetup (pll_setup_t *pSetup)
	Return System AUDIO PLL output clock rate from audio fractioanl setup structure. More...

uint32_t	CLOCK_GetUsbPLLOutFromSetup (const usb_pll_setup_t *pSetup)
	Return System USB PLL output clock rate from setup structure. More...

void	CLOCK_SetStoredUsbPLLClockRate (uint32_t rate)
	Set USB PLL output frequency. More...

pll_error_t	CLOCK_SetupPLLData (pll_config_t pControl, pll_setup_t pSetup)
	Set PLL output based on the passed PLL setup data. More...

pll_error_t	CLOCK_SetupAudioPLLData (pll_config_t pControl, pll_setup_t pSetup)
	Set AUDIO PLL output based on the passed AUDIO PLL setup data. More...

pll_error_t	CLOCK_SetupSystemPLLPrec (pll_setup_t *pSetup, uint32_t flagcfg)
	Set PLL output from PLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetupAudioPLLPrec (pll_setup_t *pSetup, uint32_t flagcfg)
	Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetupAudioPLLPrecFract (pll_setup_t *pSetup, uint32_t flagcfg)
	Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency) More...

pll_error_t	CLOCK_SetPLLFreq (const pll_setup_t *pSetup)
	Set PLL output from PLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetAudioPLLFreq (const pll_setup_t *pSetup)
	Set Audio PLL output from Audio PLL setup structure (precise frequency) More...

pll_error_t	CLOCK_SetUsbPLLFreq (const usb_pll_setup_t *pSetup)
	Set USB PLL output from USB PLL setup structure (precise frequency) More...

void	CLOCK_SetupSystemPLLMult (uint32_t multiply_by, uint32_t input_freq)
	Set PLL output based on the multiplier and input frequency. More...

static void	CLOCK_DisableUsbDevicefs0Clock (clock_ip_name_t clk)
	Disable USB clock. More...

bool	CLOCK_EnableUsbfs0DeviceClock (clock_usb_src_t src, uint32_t freq)
	Enable USB Device FS clock. More...

bool	CLOCK_EnableUsbfs0HostClock (clock_usb_src_t src, uint32_t freq)
	Enable USB HOST FS clock. More...

bool	CLOCK_EnableUsbhs0DeviceClock (clock_usb_src_t src, uint32_t freq)
	Enable USB Device HS clock. More...

bool	CLOCK_EnableUsbhs0HostClock (clock_usb_src_t src, uint32_t freq)
	Enable USB HOST HS clock. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 4))
	CLOCK driver version 2.5.4. More...

Data Structure Documentation

struct _pll_config

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

Data Fields
uint32_t	desiredRate
	Desired PLL rate in Hz.

uint32_t	inputRate
	PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set.

uint32_t	flags
	PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions.

struct _pll_setup

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

Data Fields
uint32_t	pllctrl
	PLL control register SYSPLLCTRL.

uint32_t	pllndec
	PLL NDEC register SYSPLLNDEC.

uint32_t	pllpdec
	PLL PDEC register SYSPLLPDEC.

uint32_t	pllmdec
	PLL MDEC registers SYSPLLPDEC.

uint32_t	pllRate
	Acutal PLL rate.

uint32_t	audpllfrac
	only aduio PLL has this function

uint32_t	flags
	PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions.

struct _usb_pll_setup

It can be populated with the USB PLL setup function. If powering up or waiting for USB PLL lock, the PLL input clock source should be configured prior to USB PLL setup.

Data Fields
uint8_t	msel
	USB PLL control register msel:1U-256U.

uint8_t	psel
	USB PLL control register psel:only support inter 1U 2U 4U 8U.

uint8_t	nsel
	USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U.

bool	direct
	USB PLL CCO output control.

bool	bypass
	USB PLL inout clock bypass control.

bool	fbsel
	USB PLL ineter mode and non-integer mode control.

uint32_t	inputRate
	USB PLL input rate.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 4))

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U

Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function would cache the recent calulation and accelerate the execution to get the right settings.

#define CLOCK_FROHF_SETTING_API_ROM_ADDRESS (0x030091DFU)

#define set_fro_frequency ( iFreq ) (*((void (*)(uint32_t iFreq))(CLOCK_FROHF_SETTING_API_ROM_ADDRESS)))(iFreq)

Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code. Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is enabled. Usage: set_fro_frequency(frequency), (frequency must be one of 12, 48 or 96 MHz)

#define ADC_CLOCKS

Value:

{               \
        kCLOCK_Adc0 \
    }

#define ROM_CLOCKS

Value:

{              \
        kCLOCK_Rom \
    }

#define SRAM_CLOCKS

Value:

{                                            \
        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
    }

#define FLASH_CLOCKS

Value:

{                \
        kCLOCK_Flash \
    }

#define FMC_CLOCKS

Value:

{              \
        kCLOCK_Fmc \
    }

#define EEPROM_CLOCKS

Value:

{                 \
        kCLOCK_Eeprom \
    }

#define SPIFI_CLOCKS

Value:

{                \
        kCLOCK_Spifi \
    }

#define INPUTMUX_CLOCKS

Value:

{                   \
        kCLOCK_InputMux \
    }

#define IOCON_CLOCKS

Value:

{                \
        kCLOCK_Iocon \
    }

#define GPIO_CLOCKS

Value:

{                                                                                      \
        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
    }

#define PINT_CLOCKS

Value:

{               \
        kCLOCK_Pint \
    }

#define GINT_CLOCKS

Value:

{                            \
        kCLOCK_Gint, kCLOCK_Gint \
    }

#define DMA_CLOCKS

Value:

{              \
        kCLOCK_Dma \
    }

#define CRC_CLOCKS

Value:

{              \
        kCLOCK_Crc \
    }

#define WWDT_CLOCKS

Value:

{               \
        kCLOCK_Wwdt \
    }

#define RTC_CLOCKS

Value:

{              \
        kCLOCK_Rtc \
    }

#define ADC0_CLOCKS

Value:

{               \
        kCLOCK_Adc0 \
    }

#define MRT_CLOCKS

Value:

{              \
        kCLOCK_Mrt \
    }

#define RIT_CLOCKS

Value:

{              \
        kCLOCK_Rit \
    }

#define SCT_CLOCKS

Value:

{               \
        kCLOCK_Sct0 \
    }

#define MCAN_CLOCKS

Value:

{                              \
        kCLOCK_Mcan0, kCLOCK_Mcan1 \
    }

#define UTICK_CLOCKS

Value:

{                \
        kCLOCK_Utick \
    }

#define FLEXCOMM_CLOCKS

Value:

{                                                                                                               \
        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
            kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9                                  \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
            kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9                                \
    }

#define BI2C_CLOCKS

Value:

{                                                                                                     \
        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
            kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9                                                      \
    }

#define LPSI_CLOCKS

Value:

{                                                                                                     \
        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
            kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9                                                      \
    }

#define FLEXI2S_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9                                \
    }

#define DMIC_CLOCKS

Value:

{               \
        kCLOCK_DMic \
    }

#define CTIMER_CLOCKS

Value:

{                                                                             \
        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
    }

#define LCD_CLOCKS

Value:

{              \
        kCLOCK_Lcd \
    }

#define SDIO_CLOCKS

Value:

{               \
        kCLOCK_Sdio \
    }

#define USBRAM_CLOCKS

Value:

{                  \
        kCLOCK_UsbRam1 \
    }

#define EMC_CLOCKS

Value:

{              \
        kCLOCK_Emc \
    }

#define ETH_CLOCKS

Value:

{              \
        kCLOCK_Eth \
    }

#define AES_CLOCKS

Value:

{              \
        kCLOCK_Aes \
    }

#define OTP_CLOCKS

Value:

{              \
        kCLOCK_Otp \
    }

#define RNG_CLOCKS

Value:

{              \
        kCLOCK_Rng \
    }

#define USBHMR0_CLOCKS

Value:

{                  \
        kCLOCK_Usbhmr0 \
    }

#define USBHSL0_CLOCKS

Value:

{                  \
        kCLOCK_Usbhsl0 \
    }

#define SHA0_CLOCKS

Value:

{               \
        kCLOCK_Sha0 \
    }

#define SMARTCARD_CLOCKS

Value:

{                                        \
        kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
    }

#define USBD_CLOCKS

Value:

{                                            \
        kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
    }

#define USBH_CLOCKS

Value:

{                \
        kCLOCK_Usbh1 \
    }

#define CLK_GATE_REG_OFFSET_SHIFT 8U

#define CLK_ATTACH_ID	(	mux,
		sel,
		pos
	)	((((mux) << 0U) \| (((sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

#define PLL_CONFIGFLAG_USEINRATE (1UL << 0U)

When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the configuration structure must be assigned with the expected PLL frequency. If the PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration function and the driver will determine the PLL rate from the currently selected PLL source. This flag might be used to configure the PLL input clock more accurately when using the WDT oscillator or a more dyanmic CLKIN source.

When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider are not used.
Flag to use InputRate in PLL configuration structure for setup

#define PLL_SETUPFLAG_POWERUP (1UL << 0U)

Setup will power on the PLL after setup

Typedef Documentation

typedef enum _clock_ip_name clock_ip_name_t

typedef enum _clock_name clock_name_t

typedef struct _pll_config pll_config_t

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

typedef struct _pll_setup pll_setup_t

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

typedef enum _clock_usb_src clock_usb_src_t

typedef enum _usb_pll_psel usb_pll_psel

typedef struct _usb_pll_setup usb_pll_setup_t

It can be populated with the USB PLL setup function. If powering up or waiting for USB PLL lock, the PLL input clock source should be configured prior to USB PLL setup.

Enumeration Type Documentation

enum _clock_ip_name

Enumerator
kCLOCK_IpInvalid	Invalid Ip Name.
kCLOCK_Rom	Clock gate name: Rom.
kCLOCK_Sram1	Clock gate name: Sram1.
kCLOCK_Sram2	Clock gate name: Sram2.
kCLOCK_Sram3	Clock gate name: Sram3.
kCLOCK_Flash	Clock gate name: Flash.
kCLOCK_Fmc	Clock gate name: Fmc.
kCLOCK_Eeprom	Clock gate name: Eeprom.
kCLOCK_Spifi	Clock gate name: Spifi.
kCLOCK_InputMux	Clock gate name: InputMux.
kCLOCK_Iocon	Clock gate name: Iocon.
kCLOCK_Gpio0	Clock gate name: Gpio0.
kCLOCK_Gpio1	Clock gate name: Gpio1.
kCLOCK_Gpio2	Clock gate name: Gpio2.
kCLOCK_Gpio3	Clock gate name: Gpio3.
kCLOCK_Pint	Clock gate name: Pint.
kCLOCK_Gint	Clock gate name: Gint.
kCLOCK_Dma	Clock gate name: Dma.
kCLOCK_Crc	Clock gate name: Crc.
kCLOCK_Wwdt	Clock gate name: Wwdt.
kCLOCK_Rtc	Clock gate name: Rtc.
kCLOCK_Adc0	Clock gate name: Adc0.
kCLOCK_Mrt	Clock gate name: Mrt.
kCLOCK_Rit	Clock gate name: Rit.
kCLOCK_Sct0	Clock gate name: Sct0.
kCLOCK_Mcan0	Clock gate name: Mcan0.
kCLOCK_Mcan1	Clock gate name: Mcan1.
kCLOCK_Utick	Clock gate name: Utick.
kCLOCK_FlexComm0	Clock gate name: FlexComm0.
kCLOCK_FlexComm1	Clock gate name: FlexComm1.
kCLOCK_FlexComm2	Clock gate name: FlexComm2.
kCLOCK_FlexComm3	Clock gate name: FlexComm3.
kCLOCK_FlexComm4	Clock gate name: FlexComm4.
kCLOCK_FlexComm5	Clock gate name: FlexComm5.
kCLOCK_FlexComm6	Clock gate name: FlexComm6.
kCLOCK_FlexComm7	Clock gate name: FlexComm7.
kCLOCK_MinUart0	Clock gate name: MinUart0.
kCLOCK_MinUart1	Clock gate name: MinUart1.
kCLOCK_MinUart2	Clock gate name: MinUart2.
kCLOCK_MinUart3	Clock gate name: MinUart3.
kCLOCK_MinUart4	Clock gate name: MinUart4.
kCLOCK_MinUart5	Clock gate name: MinUart5.
kCLOCK_MinUart6	Clock gate name: MinUart6.
kCLOCK_MinUart7	Clock gate name: MinUart7.
kCLOCK_LSpi0	Clock gate name: LSpi0.
kCLOCK_LSpi1	Clock gate name: LSpi1.
kCLOCK_LSpi2	Clock gate name: LSpi2.
kCLOCK_LSpi3	Clock gate name: LSpi3.
kCLOCK_LSpi4	Clock gate name: LSpi4.
kCLOCK_LSpi5	Clock gate name: LSpi5.
kCLOCK_LSpi6	Clock gate name: LSpi6.
kCLOCK_LSpi7	Clock gate name: LSpi7.
kCLOCK_BI2c0	Clock gate name: BI2c0.
kCLOCK_BI2c1	Clock gate name: BI2c1.
kCLOCK_BI2c2	Clock gate name: BI2c2.
kCLOCK_BI2c3	Clock gate name: BI2c3.
kCLOCK_BI2c4	Clock gate name: BI2c4.
kCLOCK_BI2c5	Clock gate name: BI2c5.
kCLOCK_BI2c6	Clock gate name: BI2c6.
kCLOCK_BI2c7	Clock gate name: BI2c7.
kCLOCK_FlexI2s0	Clock gate name: FlexI2s0.
kCLOCK_FlexI2s1	Clock gate name: FlexI2s1.
kCLOCK_FlexI2s2	Clock gate name: FlexI2s2.
kCLOCK_FlexI2s3	Clock gate name: FlexI2s3.
kCLOCK_FlexI2s4	Clock gate name: FlexI2s4.
kCLOCK_FlexI2s5	Clock gate name: FlexI2s5.
kCLOCK_FlexI2s6	Clock gate name: FlexI2s6.
kCLOCK_FlexI2s7	Clock gate name: FlexI2s7.
kCLOCK_DMic	Clock gate name: DMic.
kCLOCK_Ct32b2	Clock gate name: Ct32b2.
kCLOCK_Usbd0	Clock gate name: Usbd0.
kCLOCK_Ct32b0	Clock gate name: Ct32b0.
kCLOCK_Ct32b1	Clock gate name: Ct32b1.
kCLOCK_BodyBias0	Clock gate name: BodyBias0.
kCLOCK_EzhArchB0	Clock gate name: EzhArchB0.
kCLOCK_Lcd	Clock gate name: Lcd.
kCLOCK_Sdio	Clock gate name: Sdio.
kCLOCK_Usbh1	Clock gate name: Usbh1.
kCLOCK_Usbd1	Clock gate name: Usbd1.
kCLOCK_UsbRam1	Clock gate name: UsbRam1.
kCLOCK_Emc	Clock gate name: Emc.
kCLOCK_Eth	Clock gate name: Eth.
kCLOCK_Gpio4	Clock gate name: Gpio4.
kCLOCK_Gpio5	Clock gate name: Gpio5.
kCLOCK_Aes	Clock gate name: Aes.
kCLOCK_Otp	Clock gate name: Otp.
kCLOCK_Rng	Clock gate name: Rng.
kCLOCK_FlexComm8	Clock gate name: FlexComm8.
kCLOCK_FlexComm9	Clock gate name: FlexComm9.
kCLOCK_MinUart8	Clock gate name: MinUart8.
kCLOCK_MinUart9	Clock gate name: MinUart9.
kCLOCK_LSpi8	Clock gate name: LSpi8.
kCLOCK_LSpi9	Clock gate name: LSpi9.
kCLOCK_BI2c8	Clock gate name: BI2c8.
kCLOCK_BI2c9	Clock gate name: BI2c9.
kCLOCK_FlexI2s8	Clock gate name: FlexI2s8.
kCLOCK_FlexI2s9	Clock gate name: FlexI2s9.
kCLOCK_Usbhmr0	Clock gate name: Usbhmr0.
kCLOCK_Usbhsl0	Clock gate name: Usbhsl0.
kCLOCK_Sha0	Clock gate name: Sha0.
kCLOCK_SmartCard0	Clock gate name: SmartCard0.
kCLOCK_SmartCard1	Clock gate name: SmartCard1.
kCLOCK_Ct32b3	Clock gate name: Ct32b3.
kCLOCK_Ct32b4	Clock gate name: Ct32b4.

enum _clock_name

Enumerator
kCLOCK_CoreSysClk	Core/system clock (aka MAIN_CLK)
kCLOCK_BusClk	Bus clock (AHB clock)
kCLOCK_ClockOut	CLOCKOUT.
kCLOCK_FroHf	FRO48/96.
kCLOCK_UsbPll	USB1 PLL.
kCLOCK_Mclk	MCLK.
kCLOCK_Fro12M	FRO12M.
kCLOCK_ExtClk	External Clock.
kCLOCK_PllOut	PLL Output.
kCLOCK_UsbClk	USB input.
kCLOCK_WdtOsc	Watchdog Oscillator.
kCLOCK_Frg	Frg Clock.
kCLOCK_AsyncApbClk	Async APB clock.
kCLOCK_FlexI2S	FlexI2S clock.

enum _async_clock_src

Enumerator
kCLOCK_AsyncMainClk	Main System clock.
kCLOCK_AsyncFro12Mhz	12MHz FRO
kCLOCK_AsyncAudioPllClk	Async Audio PLL clock.
kCLOCK_AsyncI2cClkFc6	Async I2C clock.

enum _clock_attach_id

Enumerator
kFRO12M_to_MAIN_CLK	Attach FRO12M to MAIN_CLK.
kEXT_CLK_to_MAIN_CLK	Attach EXT_CLK to MAIN_CLK.
kWDT_OSC_to_MAIN_CLK	Attach WDT_OSC to MAIN_CLK.
kFRO_HF_to_MAIN_CLK	Attach FRO_HF to MAIN_CLK.
kSYS_PLL_to_MAIN_CLK	Attach SYS_PLL to MAIN_CLK.
kOSC32K_to_MAIN_CLK	Attach OSC32K to MAIN_CLK.
kMAIN_CLK_to_CLKOUT	Attach MAIN_CLK to CLKOUT.
kEXT_CLK_to_CLKOUT	Attach EXT_CLK to CLKOUT.
kWDT_OSC_to_CLKOUT	Attach WDT_OSC to CLKOUT.
kFRO_HF_to_CLKOUT	Attach FRO_HF to CLKOUT.
kSYS_PLL_to_CLKOUT	Attach SYS_PLL to CLKOUT.
kUSB_PLL_to_CLKOUT	Attach USB_PLL to CLKOUT.
kAUDIO_PLL_to_CLKOUT	Attach AUDIO_PLL to CLKOUT.
kOSC32K_OSC_to_CLKOUT	Attach OSC32K_OSC to CLKOUT.
kFRO12M_to_SYS_PLL	Attach FRO12M to SYS_PLL.
kEXT_CLK_to_SYS_PLL	Attach EXT_CLK to SYS_PLL.
kWDT_OSC_to_SYS_PLL	Attach WDT_OSC to SYS_PLL.
kOSC32K_to_SYS_PLL	Attach OSC32K to SYS_PLL.
kNONE_to_SYS_PLL	Attach NONE to SYS_PLL.
kFRO12M_to_AUDIO_PLL	Attach FRO12M to AUDIO_PLL.
kEXT_CLK_to_AUDIO_PLL	Attach EXT_CLK to AUDIO_PLL.
kNONE_to_AUDIO_PLL	Attach NONE to AUDIO_PLL.
kMAIN_CLK_to_SPIFI_CLK	Attach MAIN_CLK to SPIFI_CLK.
kSYS_PLL_to_SPIFI_CLK	Attach SYS_PLL to SPIFI_CLK.
kUSB_PLL_to_SPIFI_CLK	Attach USB_PLL to SPIFI_CLK.
kFRO_HF_to_SPIFI_CLK	Attach FRO_HF to SPIFI_CLK.
kAUDIO_PLL_to_SPIFI_CLK	Attach AUDIO_PLL to SPIFI_CLK.
kNONE_to_SPIFI_CLK	Attach NONE to SPIFI_CLK.
kFRO_HF_to_ADC_CLK	Attach FRO_HF to ADC_CLK.
kSYS_PLL_to_ADC_CLK	Attach SYS_PLL to ADC_CLK.
kUSB_PLL_to_ADC_CLK	Attach USB_PLL to ADC_CLK.
kAUDIO_PLL_to_ADC_CLK	Attach AUDIO_PLL to ADC_CLK.
kNONE_to_ADC_CLK	Attach NONE to ADC_CLK.
kFRO_HF_to_USB0_CLK	Attach FRO_HF to USB0_CLK.
kSYS_PLL_to_USB0_CLK	Attach SYS_PLL to USB0_CLK.
kUSB_PLL_to_USB0_CLK	Attach USB_PLL to USB0_CLK.
kNONE_to_USB0_CLK	Attach NONE to USB0_CLK.
kFRO_HF_to_USB1_CLK	Attach FRO_HF to USB1_CLK.
kSYS_PLL_to_USB1_CLK	Attach SYS_PLL to USB1_CLK.
kUSB_PLL_to_USB1_CLK	Attach USB_PLL to USB1_CLK.
kNONE_to_USB1_CLK	Attach NONE to USB1_CLK.
kFRO12M_to_FLEXCOMM0	Attach FRO12M to FLEXCOMM0.
kFRO_HF_to_FLEXCOMM0	Attach FRO_HF to FLEXCOMM0.
kAUDIO_PLL_to_FLEXCOMM0	Attach AUDIO_PLL to FLEXCOMM0.
kMCLK_to_FLEXCOMM0	Attach MCLK to FLEXCOMM0.
kFRG_to_FLEXCOMM0	Attach FRG to FLEXCOMM0.
kNONE_to_FLEXCOMM0	Attach NONE to FLEXCOMM0.
kFRO12M_to_FLEXCOMM1	Attach FRO12M to FLEXCOMM1.
kFRO_HF_to_FLEXCOMM1	Attach FRO_HF to FLEXCOMM1.
kAUDIO_PLL_to_FLEXCOMM1	Attach AUDIO_PLL to FLEXCOMM1.
kMCLK_to_FLEXCOMM1	Attach MCLK to FLEXCOMM1.
kFRG_to_FLEXCOMM1	Attach FRG to FLEXCOMM1.
kNONE_to_FLEXCOMM1	Attach NONE to FLEXCOMM1.
kFRO12M_to_FLEXCOMM2	Attach FRO12M to FLEXCOMM2.
kFRO_HF_to_FLEXCOMM2	Attach FRO_HF to FLEXCOMM2.
kAUDIO_PLL_to_FLEXCOMM2	Attach AUDIO_PLL to FLEXCOMM2.
kMCLK_to_FLEXCOMM2	Attach MCLK to FLEXCOMM2.
kFRG_to_FLEXCOMM2	Attach FRG to FLEXCOMM2.
kNONE_to_FLEXCOMM2	Attach NONE to FLEXCOMM2.
kFRO12M_to_FLEXCOMM3	Attach FRO12M to FLEXCOMM3.
kFRO_HF_to_FLEXCOMM3	Attach FRO_HF to FLEXCOMM3.
kAUDIO_PLL_to_FLEXCOMM3	Attach AUDIO_PLL to FLEXCOMM3.
kMCLK_to_FLEXCOMM3	Attach MCLK to FLEXCOMM3.
kFRG_to_FLEXCOMM3	Attach FRG to FLEXCOMM3.
kNONE_to_FLEXCOMM3	Attach NONE to FLEXCOMM3.
kFRO12M_to_FLEXCOMM4	Attach FRO12M to FLEXCOMM4.
kFRO_HF_to_FLEXCOMM4	Attach FRO_HF to FLEXCOMM4.
kAUDIO_PLL_to_FLEXCOMM4	Attach AUDIO_PLL to FLEXCOMM4.
kMCLK_to_FLEXCOMM4	Attach MCLK to FLEXCOMM4.
kFRG_to_FLEXCOMM4	Attach FRG to FLEXCOMM4.
kNONE_to_FLEXCOMM4	Attach NONE to FLEXCOMM4.
kFRO12M_to_FLEXCOMM5	Attach FRO12M to FLEXCOMM5.
kFRO_HF_to_FLEXCOMM5	Attach FRO_HF to FLEXCOMM5.
kAUDIO_PLL_to_FLEXCOMM5	Attach AUDIO_PLL to FLEXCOMM5.
kMCLK_to_FLEXCOMM5	Attach MCLK to FLEXCOMM5.
kFRG_to_FLEXCOMM5	Attach FRG to FLEXCOMM5.
kNONE_to_FLEXCOMM5	Attach NONE to FLEXCOMM5.
kFRO12M_to_FLEXCOMM6	Attach FRO12M to FLEXCOMM6.
kFRO_HF_to_FLEXCOMM6	Attach FRO_HF to FLEXCOMM6.
kAUDIO_PLL_to_FLEXCOMM6	Attach AUDIO_PLL to FLEXCOMM6.
kMCLK_to_FLEXCOMM6	Attach MCLK to FLEXCOMM6.
kFRG_to_FLEXCOMM6	Attach FRG to FLEXCOMM6.
kNONE_to_FLEXCOMM6	Attach NONE to FLEXCOMM6.
kFRO12M_to_FLEXCOMM7	Attach FRO12M to FLEXCOMM7.
kFRO_HF_to_FLEXCOMM7	Attach FRO_HF to FLEXCOMM7.
kAUDIO_PLL_to_FLEXCOMM7	Attach AUDIO_PLL to FLEXCOMM7.
kMCLK_to_FLEXCOMM7	Attach MCLK to FLEXCOMM7.
kFRG_to_FLEXCOMM7	Attach FRG to FLEXCOMM7.
kNONE_to_FLEXCOMM7	Attach NONE to FLEXCOMM7.
kFRO12M_to_FLEXCOMM8	Attach FRO12M to FLEXCOMM8.
kFRO_HF_to_FLEXCOMM8	Attach FRO_HF to FLEXCOMM8.
kAUDIO_PLL_to_FLEXCOMM8	Attach AUDIO_PLL to FLEXCOMM8.
kMCLK_to_FLEXCOMM8	Attach MCLK to FLEXCOMM8.
kFRG_to_FLEXCOMM8	Attach FRG to FLEXCOMM8.
kNONE_to_FLEXCOMM8	Attach NONE to FLEXCOMM8.
kFRO12M_to_FLEXCOMM9	Attach FRO12M to FLEXCOMM9.
kFRO_HF_to_FLEXCOMM9	Attach FRO_HF to FLEXCOMM9.
kAUDIO_PLL_to_FLEXCOMM9	Attach AUDIO_PLL to FLEXCOMM9.
kMCLK_to_FLEXCOMM9	Attach MCLK to FLEXCOMM9.
kFRG_to_FLEXCOMM9	Attach FRG to FLEXCOMM9.
kNONE_to_FLEXCOMM9	Attach NONE to FLEXCOMM9.
kFRO_HF_to_MCLK	Attach FRO_HF to MCLK.
kAUDIO_PLL_to_MCLK	Attach AUDIO_PLL to MCLK.
kNONE_to_MCLK	Attach NONE to MCLK.
kMAIN_CLK_to_FRG	Attach MAIN_CLK to FRG.
kSYS_PLL_to_FRG	Attach SYS_PLL to FRG.
kFRO12M_to_FRG	Attach FRO12M to FRG.
kFRO_HF_to_FRG	Attach FRO_HF to FRG.
kNONE_to_FRG	Attach NONE to FRG.
kFRO12M_to_DMIC	Attach FRO12M to DMIC.
kFRO_HF_DIV_to_DMIC	Attach FRO_HF_DIV to DMIC.
kAUDIO_PLL_to_DMIC	Attach AUDIO_PLL to DMIC.
kMCLK_to_DMIC	Attach MCLK to DMIC.
kNONE_to_DMIC	Attach NONE to DMIC.
kMAIN_CLK_to_SCT_CLK	Attach MAIN_CLK to SCT_CLK.
kSYS_PLL_to_SCT_CLK	Attach SYS_PLL to SCT_CLK.
kFRO_HF_to_SCT_CLK	Attach FRO_HF to SCT_CLK.
kAUDIO_PLL_to_SCT_CLK	Attach AUDIO_PLL to SCT_CLK.
kNONE_to_SCT_CLK	Attach NONE to SCT_CLK.
kMAIN_CLK_to_SDIO_CLK	Attach MAIN_CLK to SDIO_CLK.
kSYS_PLL_to_SDIO_CLK	Attach SYS_PLL to SDIO_CLK.
kUSB_PLL_to_SDIO_CLK	Attach USB_PLL to SDIO_CLK.
kFRO_HF_to_SDIO_CLK	Attach FRO_HF to SDIO_CLK.
kAUDIO_PLL_to_SDIO_CLK	Attach AUDIO_PLL to SDIO_CLK.
kNONE_to_SDIO_CLK	Attach NONE to SDIO_CLK.
kMAIN_CLK_to_LCD_CLK	Attach MAIN_CLK to LCD_CLK.
kLCDCLKIN_to_LCD_CLK	Attach LCDCLKIN to LCD_CLK.
kFRO_HF_to_LCD_CLK	Attach FRO_HF to LCD_CLK.
kNONE_to_LCD_CLK	Attach NONE to LCD_CLK.
kMAIN_CLK_to_ASYNC_APB	Attach MAIN_CLK to ASYNC_APB.
kFRO12M_to_ASYNC_APB	Attach FRO12M to ASYNC_APB.
kAUDIO_PLL_to_ASYNC_APB	Attach AUDIO_PLL to ASYNC_APB.
kI2C_CLK_FC6_to_ASYNC_APB	Attach I2C_CLK_FC6 to ASYNC_APB.
kNONE_to_NONE	Attach NONE to NONE.

enum _clock_div_name

Enumerator
kCLOCK_DivSystickClk	Systick Clock Divider.
kCLOCK_DivArmTrClkDiv	Arm Tr Clk Div Divider.
kCLOCK_DivCan0Clk	Can0 Clock Divider.
kCLOCK_DivCan1Clk	Can1 Clock Divider.
kCLOCK_DivSmartCard0Clk	Smart Card0 Clock Divider.
kCLOCK_DivSmartCard1Clk	Smart Card1 Clock Divider.
kCLOCK_DivAhbClk	Ahb Clock Divider.
kCLOCK_DivClkOut	Clk Out Divider.
kCLOCK_DivFrohfClk	Frohf Clock Divider.
kCLOCK_DivSpifiClk	Spifi Clock Divider.
kCLOCK_DivAdcAsyncClk	Adc Async Clock Divider.
kCLOCK_DivUsb0Clk	Usb0 Clock Divider.
kCLOCK_DivUsb1Clk	Usb1 Clock Divider.
kCLOCK_DivFrg	Frg Divider.
kCLOCK_DivDmicClk	Dmic Clock Divider.
kCLOCK_DivMClk	I2S MCLK Clock Divider.
kCLOCK_DivLcdClk	Lcd Clock Divider.
kCLOCK_DivSctClk	Sct Clock Divider.
kCLOCK_DivEmcClk	Emc Clock Divider.
kCLOCK_DivSdioClk	Sdio clock divider.

enum _clock_flashtim

Enumerator
kCLOCK_Flash1Cycle	Flash accesses use 1 CPU clocks.
kCLOCK_Flash2Cycle	Flash accesses use 2 CPU clocks.
kCLOCK_Flash3Cycle	Flash accesses use 3 CPU clocks.
kCLOCK_Flash4Cycle	Flash accesses use 4 CPU clocks.
kCLOCK_Flash5Cycle	Flash accesses use 5 CPU clocks.
kCLOCK_Flash6Cycle	Flash accesses use 6 CPU clocks.
kCLOCK_Flash7Cycle	Flash accesses use 7 CPU clocks.
kCLOCK_Flash8Cycle	Flash accesses use 8 CPU clocks.
kCLOCK_Flash9Cycle	Flash accesses use 9 CPU clocks.

enum _pll_error

Enumerator
kStatus_PLL_Success	PLL operation was successful.
kStatus_PLL_OutputTooLow	PLL output rate request was too low.
kStatus_PLL_OutputTooHigh	PLL output rate request was too high.
kStatus_PLL_InputTooLow	PLL input rate is too low.
kStatus_PLL_InputTooHigh	PLL input rate is too high.
kStatus_PLL_OutsideIntLimit	Requested output rate isn't possible.
kStatus_PLL_CCOTooLow	Requested CCO rate isn't possible.
kStatus_PLL_CCOTooHigh	Requested CCO rate isn't possible.

enum _clock_usb_src

Enumerator
kCLOCK_UsbSrcFro	Use FRO 96 or 48 MHz.
kCLOCK_UsbSrcSystemPll	Use System PLL output.
kCLOCK_UsbSrcMainClock	Use Main clock.
kCLOCK_UsbSrcUsbPll	Use USB PLL clock.
kCLOCK_UsbSrcNone	Use None, this may be selected in order to reduce power when no output is needed.

enum _usb_pll_psel

Function Documentation

static void CLOCK_SetFLASHAccessCycles ( clock_flashtim_t clks )

inlinestatic

Parameters

clks	: Clock cycles for FLASH access

Returns: Nothing

status_t CLOCK_SetupFROClocking ( uint32_t iFreq )

Parameters

iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)

Returns: returns success or fail status.

void CLOCK_AttachClk ( clock_attach_id_t connection )

Parameters

connection : Clock to be configured.

Returns: Nothing

clock_attach_id_t CLOCK_GetClockAttachId ( clock_attach_id_t attachId )

Parameters

attachId : Clock attach id to get.

Returns: Clock source value.

void CLOCK_SetClkDiv	(	clock_div_name_t	div_name,
		uint32_t	divided_by_value,
		bool	reset
	)

Parameters

div_name	: Clock divider name
divided_by_value,:	Value to be divided
reset	: Whether to reset the divider counter.

Returns: Nothing

void CLOCK_SetFLASHAccessCyclesForFreq ( uint32_t iFreq )

Parameters

iFreq : Input frequency

Returns: Nothing

uint32_t CLOCK_SetFRGClock ( uint32_t freq )

Parameters

freq	: output frequency

Returns: 0 : the frequency range is out of range. 1 : switch successfully.

uint32_t CLOCK_GetFRGInputClock ( void )

Returns: Frequency value

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

Returns: Frequency of selected clock

uint32_t CLOCK_GetFro12MFreq ( void )

Returns: Frequency of FRO 12MHz

uint32_t CLOCK_GetClockOutClkFreq ( void )

Returns: Frequency of ClockOut

uint32_t CLOCK_GetSpifiClkFreq ( void )

Returns: Frequency of Spifi.

uint32_t CLOCK_GetAdcClkFreq ( void )

Returns: Frequency of Adc Clock.

uint32_t CLOCK_GetUsb0ClkFreq ( void )

Returns: Frequency of Usb0 Clock.

uint32_t CLOCK_GetUsb1ClkFreq ( void )

Returns: Frequency of Usb1 Clock.

uint32_t CLOCK_GetMclkClkFreq ( void )

Returns: Frequency of MClk Clock.

uint32_t CLOCK_GetSctClkFreq ( void )

Returns: Frequency of SCTimer Clock.

uint32_t CLOCK_GetSdioClkFreq ( void )

Returns: Frequency of SDIO Clock.

uint32_t CLOCK_GetLcdClkFreq ( void )

Returns: Frequency of LCD Clock.

uint32_t CLOCK_GetLcdClkIn ( void )

Returns: Frequency of LCD CLKIN Clock.

uint32_t CLOCK_GetExtClkFreq ( void )

Returns: Frequency of External Clock. If no external clock is used returns 0.

uint32_t CLOCK_GetWdtOscFreq ( void )

Returns: Frequency of Watchdog Oscillator

uint32_t CLOCK_GetFroHfFreq ( void )

Returns: Frequency of High-Freq output of FRO

uint32_t CLOCK_GetFrgClkFreq ( void )

Returns: Frequency of FRG

uint32_t CLOCK_GetDmicClkFreq ( void )

Returns: Frequency of DMIC

uint32_t CLOCK_GetPllOutFreq ( void )

Returns: Frequency of PLL

uint32_t CLOCK_GetUsbPllOutFreq ( void )

Returns: Frequency of PLL

uint32_t CLOCK_GetAudioPllOutFreq ( void )

Returns: Frequency of PLL

uint32_t CLOCK_GetOsc32KFreq ( void )

Returns: Frequency of 32kHz osc

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Frequency of Core System

uint32_t CLOCK_GetI2SMClkFreq ( void )

Returns: Frequency of I2S MCLK Clock

uint32_t CLOCK_GetFlexCommClkFreq ( uint32_t id )

Returns: Frequency of Flexcomm functional Clock

__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc ( void )

Returns: Asynchronous APB CLock source

uint32_t CLOCK_GetAsyncApbClkFreq ( void )

Returns: Frequency of Asynchronous APB Clock Clock

__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq ( void )

Returns: EMC source

uint32_t CLOCK_GetAudioPLLInClockRate ( void )

Returns: Audio PLL input clock rate

uint32_t CLOCK_GetSystemPLLInClockRate ( void )

Returns: System PLL input clock rate

uint32_t CLOCK_GetSystemPLLOutClockRate ( bool recompute )

Parameters

recompute : Forces a PLL rate recomputation if true

Returns: System PLL output clock rate

Note: The PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

uint32_t CLOCK_GetAudioPLLOutClockRate ( bool recompute )

Parameters

recompute : Forces a AUDIO PLL rate recomputation if true

Returns: System AUDIO PLL output clock rate

Note: The AUDIO PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

uint32_t CLOCK_GetUsbPLLOutClockRate ( bool recompute )

Parameters

recompute : Forces a USB PLL rate recomputation if true

Returns: System USB PLL output clock rate

Note: The USB PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

__STATIC_INLINE void CLOCK_SetBypassPLL ( bool bypass )

bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass

Returns: System PLL output clock rate

__STATIC_INLINE bool CLOCK_IsSystemPLLLocked ( void )

Returns: true if the PLL is locked, false if not locked

__STATIC_INLINE bool CLOCK_IsUsbPLLLocked ( void )

Returns: true if the USB PLL is locked, false if not locked

__STATIC_INLINE bool CLOCK_IsAudioPLLLocked ( void )

Returns: true if the AUDIO PLL is locked, false if not locked

__STATIC_INLINE void CLOCK_Enable_SysOsc ( bool enable )

enable : true to enable SYS OSC, false to disable SYS OSC

void CLOCK_SetStoredPLLClockRate ( uint32_t rate )

Parameters

rate,: Current rate of the PLL

Returns: Nothing

void CLOCK_SetStoredAudioPLLClockRate ( uint32_t rate )

Parameters

rate,: Current rate of the PLL

Returns: Nothing

uint32_t CLOCK_GetSystemPLLOutFromSetup ( pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: System PLL output clock rate the setup structure will generate

uint32_t CLOCK_GetAudioPLLOutFromSetup ( pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: System PLL output clock rate the setup structure will generate

uint32_t CLOCK_GetAudioPLLOutFromFractSetup ( pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: System PLL output clock rate the setup structure will generate

uint32_t CLOCK_GetUsbPLLOutFromSetup ( const usb_pll_setup_t * pSetup )

Parameters

pSetup : Pointer to a PLL setup structure

Returns: System PLL output clock rate the setup structure will generate

void CLOCK_SetStoredUsbPLLClockRate ( uint32_t rate )

Parameters

rate	: frequency value

pll_error_t CLOCK_SetupPLLData	(	pll_config_t *	pControl,
		pll_setup_t *	pSetup
	)

Parameters

pControl	: Pointer to populated PLL control structure to generate setup with
pSetup	: Pointer to PLL setup structure to be filled

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: Actual frequency for setup may vary from the desired frequency based on the accuracy of input clocks, rounding, non-fractional PLL mode, etc.

pll_error_t CLOCK_SetupAudioPLLData	(	pll_config_t *	pControl,
		pll_setup_t *	pSetup
	)

Parameters

pControl	: Pointer to populated PLL control structure to generate setup with
pSetup	: Pointer to PLL setup structure to be filled

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: Actual frequency for setup may vary from the desired frequency based on the accuracy of input clocks, rounding, non-fractional PLL mode, etc.

pll_error_t CLOCK_SetupSystemPLLPrec	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetupAudioPLLPrec	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, and adjust system voltages to the new AUDIOPLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetupAudioPLLPrecFract	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns: PLL_ERROR_SUCCESS on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, and adjust system voltages to the new AUDIOPLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetPLLFreq ( const pll_setup_t * pSetup )

Parameters

pSetup : Pointer to populated PLL setup structure

Returns: kStatus_PLL_Success on success, or PLL setup error code

Note: This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetAudioPLLFreq ( const pll_setup_t * pSetup )

Parameters

pSetup : Pointer to populated PLL setup structure

Returns: kStatus_PLL_Success on success, or Audio PLL setup error code

Note: This function will power off the PLL, setup the Audio PLL with the new setup data, and then optionally powerup the PLL, wait for Audio PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the Audio PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetUsbPLLFreq ( const usb_pll_setup_t * pSetup )

Parameters

pSetup : Pointer to populated USB PLL setup structure

Returns: kStatus_PLL_Success on success, or USB PLL setup error code

Note: This function will power off the USB PLL, setup the PLL with the new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock, and adjust system voltages to the new USB PLL rate. The function will not alter any source clocks (ie, usb pll clock) that may use the USB PLL, so these should be setup prior to and after exiting the function.

void CLOCK_SetupSystemPLLMult	(	uint32_t	multiply_by,
		uint32_t	input_freq
	)

Parameters

multiply_by	: multiplier
input_freq	: Clock input frequency of the PLL

Returns: Nothing

Note: Unlike the Chip_Clock_SetupSystemPLLPrec() function, this function does not disable or enable PLL power, wait for PLL lock, or adjust system voltages. These must be done in the application. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

static void CLOCK_DisableUsbDevicefs0Clock ( clock_ip_name_t clk )

inlinestatic

Disable USB clock.

bool CLOCK_EnableUsbfs0DeviceClock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB Device Full Speed clock.

bool CLOCK_EnableUsbfs0HostClock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB HOST Full Speed clock.

bool CLOCK_EnableUsbhs0DeviceClock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB Device High Speed clock.

bool CLOCK_EnableUsbhs0HostClock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	: clock source
freq,:	clock frequency Enable USB HOST High Speed clock.

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