The MCUXpresso SDK provides a peripheral driver for the SHA module in MCUXpresso SDK devices.
The driver provides blocking synchronous APIs. The SHA operations are complete (and results are made availabe for further usage) when a function returns. When called, these functions do not return until an SHA operation is complete. These functions use main CPU for simple polling loops to determine operation complete or error status and data movements. The driver functions are not re-entrant. These functions provide typical interface to upper layer or application software.
SHA Driver Initialization and Configuration
Clock to the SHA module has to be enabled before using the driver API.
Comments about API usage in RTOS
SHA operations provided by this driver are not re-entrant. Therefore, the application software should ensure the SHA module operation is not requested from different tasks or interrupt service routines while an operation is in progress.
SHA Driver Example
Typical use case Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/sha
Current version: 2.3.2
Change log:
- Version 2.0.0
- Version 2.1.0
- Updated "sha_ldm_stm_16_words" "sha_one_block" API to match QN9090. QN9090 has no ALIAS register.
- Added "SHA_ClkInit" "SHA_ClkInit"
- Version 2.1.1
- MISRA C-2012 issue fixed: rule 10.3, 10.4, 11.9, 14.4, 16.4 and 17.7.
- Version 2.2.0
- Support MEMADDR pseudo DMA for loading input data in SHA_Update function (LPCXpresso54018 and LPCXpresso54628).
- Version 2.2.1
- Version 2.2.2 Modified SHA_Finish function. While using pseudo DMA with maximum optimization, compiler optimize out condition. Which caused block in this function and did not check state, which has been set in interrupt.
- Version 2.3.0 Modified SHA_Update to use blocking version of AHB Master mode when its available on chip. Added SHA_UpdateNonBlocking() function which uses nonblocking AHB Master mode. Fixed incorrect calculation of SHA when calling SHA_Update multiple times when is CPU used to load data. Added Reset into SHA_ClkInit and SHA_ClkDeinit function.
- Version 2.3.1 Modified sha_process_message_data_master() to ensure that MEMCTRL will be written within 64 cycles of writing last word to INDATA as is mentioned in errata, even with different optimization levels.
- Version 2.3.2 Add -O2 optimization for GCC to sha_process_message_data_master(), because without it the function hangs under some conditions.
typedef void(* sha_callback_t)(SHA_Type *base, sha_ctx_t *ctx, status_t status, void *userData) |
Enumerator |
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kSHA_Sha1 |
SHA_1.
|
kSHA_Sha256 |
SHA_256.
|