Overview

The MCUXpresso SDK provides a peripheral driver for the Synchronous DRAM Controller block of MCUXpresso SDK devices.

The SDRAM controller commands include the initialization MRS command, precharge command, enter/exit self-refresh command, and enable/disable auto-refresh command. Use the SDRAMC_SendCommand() to send these commands to SDRAM to initialize it. The SDRAMC_EnableWriteProtect() is provided to enable/disable the write protection. The SDRAMC_EnableOperateValid() is provided to enable/disable the operation valid.

Typical use case

This example shows how to use the SDRAM Controller driver to initialize the external 16 bit port-size 8-column SDRAM chip. Initialize the SDRAM controller and run the initialization sequence. The external SDRAM is initialized and the SDRAM read and write is available.

First, initialize the SDRAM Controller.

sdramc_config_t config;
uint32_t clockSrc;
// SDRAM refresh timing configuration.
clockSrc = CLOCK_GetFreq(kCLOCK_BusClk);
sdramc_refresh_config_t refConfig =
{
   kSDRAMC_RefreshThreeClocks,
   15625,    // SDRAM: 4096 rows/ 64ms.
   clockSrc,
};
// SDRAM controller configuration.
sdramc_blockctl_config_t ctlConfig =
{
    kSDRAMC_Block0,
    kSDRAMC_PortSize16Bit,
    kSDRAMC_Commandbit19,
    kSDRAMC_LatencyOne,
    SDRAM_START_ADDRESS,
    0x7c0000,
};
config.refreshConfig = &refConfig;
config.blockConfig = &ctlConfig;
config.numBlockConfig = 1;
// SDRAM controller initialization.
SDRAMC_Init(base, &config);

Then, run the initialization sequence.

// Issues a PALL command.
SDRAMC_SendCommand(base, whichBlock, kSDRAMC_PrechargeCommand);
// Accesses an SDRAM location.
*(uint8_t *)(SDRAM_START_ADDRESS) = SDRAM_COMMAND_ACCESSVALUE;
// Enables the refresh.
SDRAMC_SendCommand(base, whichBlock, kSDRAMC_AutoRefreshEnableCommand);
// Waits for 8 refresh cycles less than one microsecond.
delay;
// Issues the MSR command.
SDRAMC_SendCommand(base, whichBlock, kSDRAMC_ImrsCommand);
// Puts the correct value on the SDRAM address bus for the SDRAM mode register.
addr = ....;
// Set MRS register.
mrsAddr = (uint8_t *)(SDRAM_START_ADDRESS + addr);
*mrsAddr = SDRAM_COMMAND_ACCESSVALUE;

Data Structures
struct	sdramc_blockctl_config_t
	SDRAM controller block control configuration structure. More...

struct	sdramc_refresh_config_t
	SDRAM controller refresh timing configuration structure. More...

struct	sdramc_config_t
	SDRAM controller configuration structure. More...

Enumerations
enum	sdramc_refresh_time_t { kSDRAMC_RefreshThreeClocks = 0x0U, kSDRAMC_RefreshSixClocks, kSDRAMC_RefreshNineClocks }
	SDRAM controller auto-refresh timing. More...

enum	sdramc_latency_t { kSDRAMC_LatencyZero = 0x0U, kSDRAMC_LatencyOne, kSDRAMC_LatencyTwo, kSDRAMC_LatencyThree }
	Setting latency for SDRAM controller timing specifications. More...

enum	sdramc_command_bit_location_t { kSDRAMC_Commandbit17 = 0x0U, kSDRAMC_Commandbit18, kSDRAMC_Commandbit19, kSDRAMC_Commandbit20, kSDRAMC_Commandbit21, kSDRAMC_Commandbit22, kSDRAMC_Commandbit23, kSDRAMC_Commandbit24 }
	SDRAM controller command bit location. More...

enum	sdramc_command_t { kSDRAMC_ImrsCommand = 0x0U, kSDRAMC_PrechargeCommand, kSDRAMC_SelfrefreshEnterCommand, kSDRAMC_SelfrefreshExitCommand, kSDRAMC_AutoRefreshEnableCommand, kSDRAMC_AutoRefreshDisableCommand }
	SDRAM controller command. More...

enum	sdramc_port_size_t { kSDRAMC_PortSize32Bit = 0x0U, kSDRAMC_PortSize8Bit, kSDRAMC_PortSize16Bit }
	SDRAM port size. More...

enum	sdramc_block_selection_t { kSDRAMC_Block0 = 0x0U, kSDRAMC_Block1 }
	SDRAM controller block selection. More...

Driver version
#define	FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
	SDRAMC driver version 2.1.0. More...

SDRAM Controller Initialization and De-initialization
void	SDRAMC_Init (SDRAM_Type base, sdramc_config_t configure)
	Initializes the SDRAM controller. More...

void	SDRAMC_Deinit (SDRAM_Type *base)
	Deinitializes the SDRAM controller module and gates the clock. More...

SDRAM Controller Basic Operation
void	SDRAMC_SendCommand (SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
	Sends the SDRAM command. More...

static void	SDRAMC_EnableWriteProtect (SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
	Enables/disables the write protection. More...

static void	SDRAMC_EnableOperateValid (SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
	Enables/disables the valid operation. More...

Data Structure Documentation

struct sdramc_blockctl_config_t

Data Fields
sdramc_block_selection_t	block
	The block number. More...

sdramc_port_size_t	portSize
	The port size of the associated SDRAM block. More...

sdramc_command_bit_location_t	location
	The command bit location. More...

sdramc_latency_t	latency
	The latency for some timing specifications. More...

uint32_t	address
	The base address of the SDRAM block. More...

uint32_t	addressMask
	The base address mask of the SDRAM block. More...

Field Documentation

sdramc_block_selection_t sdramc_blockctl_config_t::block

sdramc_port_size_t sdramc_blockctl_config_t::portSize

sdramc_command_bit_location_t sdramc_blockctl_config_t::location

sdramc_latency_t sdramc_blockctl_config_t::latency

uint32_t sdramc_blockctl_config_t::address

uint32_t sdramc_blockctl_config_t::addressMask

struct sdramc_refresh_config_t

Data Fields
sdramc_refresh_time_t	refreshTime
	Trc:The number of bus clocks inserted between a REF and next ACTIVE command. More...

uint32_t	sdramRefreshRow
	The SDRAM refresh time each row: ns/row. More...

uint32_t	busClock_Hz
	The bus clock for SDRAMC. More...

Field Documentation

sdramc_refresh_time_t sdramc_refresh_config_t::refreshTime

uint32_t sdramc_refresh_config_t::sdramRefreshRow

uint32_t sdramc_refresh_config_t::busClock_Hz

struct sdramc_config_t

Defines a configure structure and uses the SDRAMC_Configure() function to make necessary initializations.

Data Fields
sdramc_refresh_config_t *	refreshConfig
	Refresh timing configure structure pointer. More...

sdramc_blockctl_config_t *	blockConfig
	Block configure structure pointer. More...

uint8_t	numBlockConfig
	SDRAM block numbers for configuration. More...

Field Documentation

sdramc_refresh_config_t* sdramc_config_t::refreshConfig

sdramc_blockctl_config_t* sdramc_config_t::blockConfig

If both SDRAM blocks are used, use the two continuous blockConfig.

uint8_t sdramc_config_t::numBlockConfig

Macro Definition Documentation

#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))

Enumeration Type Documentation

enum sdramc_refresh_time_t

Enumerator
kSDRAMC_RefreshThreeClocks	The refresh timing with three bus clocks.
kSDRAMC_RefreshSixClocks	The refresh timing with six bus clocks.
kSDRAMC_RefreshNineClocks	The refresh timing with nine bus clocks.

enum sdramc_latency_t

The latency setting affects the following SDRAM timing specifications:

trcd: SRAS assertion to SCAS assertion
tcasl: SCAS assertion to data out
tras: ACTV command to Precharge command
trp: Precharge command to ACTV command
trwl, trdl: Last data input to Precharge command
tep: Last data out to Precharge command
The details of the latency setting and timing specifications are shown in the following table list.
latency trcd: tcasl tras trp trwl,trdl tep
0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock
1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock
2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock
3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock

Enumerator
kSDRAMC_LatencyZero	Latency 0.
kSDRAMC_LatencyOne	Latency 1.
kSDRAMC_LatencyTwo	Latency 2.
kSDRAMC_LatencyThree	Latency 3.

enum sdramc_command_bit_location_t

Enumerator
kSDRAMC_Commandbit17	Command bit location is bit 17.
kSDRAMC_Commandbit18	Command bit location is bit 18.
kSDRAMC_Commandbit19	Command bit location is bit 19.
kSDRAMC_Commandbit20	Command bit location is bit 20.
kSDRAMC_Commandbit21	Command bit location is bit 21.
kSDRAMC_Commandbit22	Command bit location is bit 22.
kSDRAMC_Commandbit23	Command bit location is bit 23.
kSDRAMC_Commandbit24	Command bit location is bit 24.

enum sdramc_command_t

Enumerator
kSDRAMC_ImrsCommand	Initiate MRS command.
kSDRAMC_PrechargeCommand	Initiate precharge command.
kSDRAMC_SelfrefreshEnterCommand	Enter self-refresh command.
kSDRAMC_SelfrefreshExitCommand	Exit self-refresh command.
kSDRAMC_AutoRefreshEnableCommand	Enable Auto refresh command.
kSDRAMC_AutoRefreshDisableCommand	Disable Auto refresh command.

enum sdramc_port_size_t

Enumerator
kSDRAMC_PortSize32Bit	32-Bit port size.
kSDRAMC_PortSize8Bit	8-Bit port size.
kSDRAMC_PortSize16Bit	16-Bit port size.

enum sdramc_block_selection_t

Enumerator
kSDRAMC_Block0	Select SDRAM block 0.
kSDRAMC_Block1	Select SDRAM block 1.

Function Documentation

void SDRAMC_Init	(	SDRAM_Type *	base,
		sdramc_config_t *	configure
	)

This function ungates the SDRAM controller clock and initializes the SDRAM controller. This function must be called before calling any other SDRAM controller driver functions. Example

sdramc_refresh_config_t refreshConfig;
sdramc_blockctl_config_t blockConfig;
sdramc_config_t config;
refreshConfig.refreshTime  = kSDRAM_RefreshThreeClocks;
refreshConfig.sdramRefreshRow = 15625;
refreshConfig.busClock = 60000000;
blockConfig.block = kSDRAMC_Block0;
blockConfig.portSize = kSDRAMC_PortSize16Bit;
blockConfig.location = kSDRAMC_Commandbit19;
blockConfig.latency = kSDRAMC_RefreshThreeClocks;
blockConfig.address = SDRAM_START_ADDRESS;
blockConfig.addressMask = 0x7c0000;
config.refreshConfig = &refreshConfig,
config.blockConfig = &blockConfig,
config.totalBlocks = 1;
SDRAMC_Init(SDRAM, &config);

Parameters

base	SDRAM controller peripheral base address.
configure	The SDRAM configuration structure pointer.

void SDRAMC_Deinit ( SDRAM_Type * base )

This function gates the SDRAM controller clock. As a result, the SDRAM controller module doesn't work after calling this function.

Parameters

base	SDRAM controller peripheral base address.

void SDRAMC_SendCommand	(	SDRAM_Type *	base,
		sdramc_block_selection_t	block,
		sdramc_command_t	command
	)

This function sends commands to SDRAM. The commands are precharge command, initialization MRS command, auto-refresh enable/disable command, and self-refresh enter/exit commands. Note that the self-refresh enter/exit commands are all blocks setting and "block" is ignored. Ensure to set the correct "block" when send other commands.

Parameters

base	SDRAM controller peripheral base address.
block	The block selection.
command	The SDRAM command, see "sdramc_command_t". kSDRAMC_ImrsCommand - Initialize MRS command kSDRAMC_PrechargeCommand - Initialize precharge command kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command

static void SDRAMC_EnableWriteProtect	(	SDRAM_Type *	base,
		sdramc_block_selection_t	block,
		bool	enable
	)

inlinestatic

Parameters

base	SDRAM peripheral base address.
block	The block which is selected.
enable	True enable write protection, false disable write protection.

static void SDRAMC_EnableOperateValid	(	SDRAM_Type *	base,
		sdramc_block_selection_t	block,
		bool	enable
	)

inlinestatic

Parameters

base	SDRAM peripheral base address.
block	The block which is selected.
enable	True enable the valid operation; false disable the valid operation.

Overview

Typical use case

Data Structures

Enumerations

Driver version

SDRAM Controller Initialization and De-initialization

SDRAM Controller Basic Operation

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation