diff_p.h File Reference

The diff_p.h contains the DIFF_P Pressure sensor register definitions, access macros, and its bit mask. More...

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Data Structures
union	DIFF_P_INT_STATUS_0_t
union	DIFF_P_INT_STATUS_1_t
union	DIFF_P_INT_MASK0_t
union	DIFF_P_INT_MASK1_t
union	DIFF_P_STATUS_t
union	DIFF_P_CTRL_REG1_t
union	DIFF_P_CTRL_REG2_t
union	DIFF_P_CTRL_REG3_t
union	DIFF_P_INT_ROUTE0_t
union	DIFF_P_INT_ROUTE1_t

Macros
#define	DIFF_P_NPS3000VV_WHOAMI_VALUE   (0xD0) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */
#define	DIFF_P_NPS3001DV_WHOAMI_VALUE   (0xD1) /* DIFF_P Who_Am_I Value of Part Number NPS3001DV. */
#define	DIFF_P_NPS3002VV_WHOAMI_VALUE   (0xD2) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */
#define	DIFF_P_NPS3005DV_WHOAMI_VALUE   (0xD3) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */
#define	DIFF_P_INT_STATUS_0_PDU_MASK   ((uint8_t) 0x01)
#define	DIFF_P_INT_STATUS_0_PDU_SHIFT   ((uint8_t) 0)
#define	DIFF_P_INT_STATUS_0_PDO_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_STATUS_0_PDO_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_STATUS_0_VERRA_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_STATUS_0_VERRA_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_STATUS_0_TDR_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_STATUS_0_TDR_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_STATUS_0_PDR_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_STATUS_0_PDR_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_STATUS_0_TOW_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_STATUS_0_TOW_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_STATUS_0_POW_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_STATUS_0_POW_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_STATUS_0_PDU_UNDERFLOW   ((uint8_t) 0x01) /* Underflow occurred. */
#define	DIFF_P_INT_STATUS_0_PDU_NO_UNDERFLOW   ((uint8_t) 0x00) /* No Underflow occurred. */
#define	DIFF_P_INT_STATUS_0_PDO_OVERFLOW   ((uint8_t) 0x02) /* Overflow occurred. */
#define	DIFF_P_INT_STATUS_0_PDO_NO_OVERFLOW   ((uint8_t) 0x00) /* No overflow occurred. */
#define	DIFF_P_INT_STATUS_0_VERRA_BRWNOUT   ((uint8_t) 0x08) /* Analog voltage brownout occurred. */
#define	DIFF_P_INT_STATUS_0_VERRA_NO_BRWNOUT   ((uint8_t) 0x00) /* No brownout occurred. */
#define	DIFF_P_INT_STATUS_0_TDR_DRDY   ((uint8_t) 0x10) /* A new Temperature data is ready. */
#define	DIFF_P_INT_STATUS_0_PDR_DRDY   ((uint8_t) 0x20) /* A new set of Pressure data is ready. */
#define	DIFF_P_INT_STATUS_0_TOW_OWR   ((uint8_t) 0x40) /* Previous Temperature data was overwritten by new */
#define	DIFF_P_INT_STATUS_0_POW_OWR   ((uint8_t) 0x80) /* Previous Pressure data was overwritten by new */
#define	DIFF_P_INT_STATUS_1_P_WCHG_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_STATUS_1_P_WCHG_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_STATUS_1_P_TGT2_MASK   ((uint8_t) 0x04)
#define	DIFF_P_INT_STATUS_1_P_TGT2_SHIFT   ((uint8_t) 2)
#define	DIFF_P_INT_STATUS_1_P_TGT1_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_STATUS_1_P_TGT1_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_STATUS_1_P_TGT0_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_STATUS_1_P_TGT0_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_STATUS_1_T_TGT_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_STATUS_1_T_TGT_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_STATUS_1_TDU_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_STATUS_1_TDU_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_STATUS_1_TDO_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_STATUS_1_TDO_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_STATUS_1_P_WCHG_TH_CROSSED   ((uint8_t) 0x02) /* pressure has crossed the window threshold defined */
#define	DIFF_P_INT_STATUS_1_P_TGT2_REACHED   ((uint8_t) 0x04) /* Temperature target reached. */
#define	DIFF_P_INT_STATUS_1_P_TGT1_REACHED   ((uint8_t) 0x08) /* Temperature target reached. */
#define	DIFF_P_INT_STATUS_1_P_TGT0_REACHED   ((uint8_t) 0x10) /* Temperature target reached. */
#define	DIFF_P_INT_STATUS_1_T_TGT_REACHED   ((uint8_t) 0x20) /* Temperature target reached. */
#define	DIFF_P_INT_STATUS_1_TDU_UNDERFLOW   ((uint8_t) 0x40) /* Underflow occurred. */
#define	DIFF_P_INT_STATUS_1_TDU_NO_UNDERFLOW   ((uint8_t) 0x00) /* No Underflow occurred. */
#define	DIFF_P_INT_STATUS_1_TDO_OVERFLOW   ((uint8_t) 0x80) /* Overflow occurred. */
#define	DIFF_P_INT_STATUS_1_TDO_NO_OVERFLOW   ((uint8_t) 0x00) /* No overflow occurred. */
#define	DIFF_P_INT_MASK0_PDU_MASK   ((uint8_t) 0x01)
#define	DIFF_P_INT_MASK0_PDU_SHIFT   ((uint8_t) 0)
#define	DIFF_P_INT_MASK0_PDO_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_MASK0_PDO_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_MASK0_VERRA_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_MASK0_VERRA_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_MASK0_TDR_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_MASK0_TDR_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_MASK0_PDR_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_MASK0_PDR_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_MASK0_TOW_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_MASK0_TOW_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_MASK0_POW_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_MASK0_POW_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_MASK0_PDU_INT_EN   ((uint8_t) 0x01) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_PDO_INT_EN   ((uint8_t) 0x02) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_VERRA_INT_EN   ((uint8_t) 0x08) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_TDR_INT_EN   ((uint8_t) 0x10) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_PDR_INT_EN   ((uint8_t) 0x20) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_TOW_INT_EN   ((uint8_t) 0x40) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK0_POW_INT_EN   ((uint8_t) 0x80) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_P_WCHG_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_MASK1_P_WCHG_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_MASK1_P_TGT2_MASK   ((uint8_t) 0x04)
#define	DIFF_P_INT_MASK1_P_TGT2_SHIFT   ((uint8_t) 2)
#define	DIFF_P_INT_MASK1_P_TGT1_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_MASK1_P_TGT1_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_MASK1_P_TGT0_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_MASK1_P_TGT0_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_MASK1_T_TGT_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_MASK1_T_TGT_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_MASK1_TDU_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_MASK1_TDU_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_MASK1_TDO_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_MASK1_TDO_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_MASK1_P_WCHG_INT_EN   ((uint8_t) 0x02) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_P_TGT2_INT_EN   ((uint8_t) 0x04) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_P_TGT1_INT_EN   ((uint8_t) 0x08) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_P_TGT0_INT_EN   ((uint8_t) 0x10) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_T_TGT_INT_EN   ((uint8_t) 0x20) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_TDU_INT_EN   ((uint8_t) 0x40) /* Interrupt Enabled. */
#define	DIFF_P_INT_MASK1_TDO_INT_EN   ((uint8_t) 0x80) /* Interrupt Enabled. */
#define	DIFF_P_STATUS_RST_STATUS_MASK   ((uint8_t) 0x01)
#define	DIFF_P_STATUS_RST_STATUS_SHIFT   ((uint8_t) 0)
#define	DIFF_P_STATUS_OSR_ERR_MASK   ((uint8_t) 0x02)
#define	DIFF_P_STATUS_OSR_ERR_SHIFT   ((uint8_t) 1)
#define	DIFF_P_STATUS_STAT_CPLT_MASK   ((uint8_t) 0x04)
#define	DIFF_P_STATUS_STAT_CPLT_SHIFT   ((uint8_t) 2)
#define	DIFF_P_STATUS_STAT_EP_MASK   ((uint8_t) 0x08)
#define	DIFF_P_STATUS_STAT_EP_SHIFT   ((uint8_t) 3)
#define	DIFF_P_STATUS_I2C_RPG_STATUS_MASK   ((uint8_t) 0x10)
#define	DIFF_P_STATUS_I2C_RPG_STATUS_SHIFT   ((uint8_t) 4)
#define	DIFF_P_STATUS_I2C_RPG_MASK   ((uint8_t) 0x20)
#define	DIFF_P_STATUS_I2C_RPG_SHIFT   ((uint8_t) 5)
#define	DIFF_P_STATUS_I2C_RPG_CNT_MASK   ((uint8_t) 0x40)
#define	DIFF_P_STATUS_I2C_RPG_CNT_SHIFT   ((uint8_t) 6)
#define	DIFF_P_STATUS_ACTIVE_MODE_MASK   ((uint8_t) 0x80)
#define	DIFF_P_STATUS_ACTIVE_MODE_SHIFT   ((uint8_t) 7)
#define	DIFF_P_STATUS_RST_STATUS_RST   ((uint8_t) 0x01) /* Part has come out of POR, brownout or soft reset. */
#define	DIFF_P_STATUS_RST_STATUS_NO_RST   ((uint8_t) 0x00) /* No POR, brownout or soft reset has occurred. */
#define	DIFF_P_STATUS_OSR_ERR_ERR   ((uint8_t) 0x02) /* Illegal ODR/OSR combination. */
#define	DIFF_P_STATUS_OSR_ERR_NO_ERR   ((uint8_t) 0x00) /* No Error. */
#define	DIFF_P_STATUS_STAT_CPLT_SUCCESS   ((uint8_t) 0x04) /* Calibration routine was successful. */
#define	DIFF_P_STATUS_STAT_CPLT_NO_SUCCESS   ((uint8_t) 0x00) /* Calibration routine was not successful. */
#define	DIFF_P_STATUS_STAT_EP_DETECTED   ((uint8_t) 0x08) /* Existing pressure has been detected. */
#define	DIFF_P_STATUS_STAT_EP_NOTDETECTED   ((uint8_t) 0x00) /* No existing pressure detected. */
#define	DIFF_P_STATUS_I2C_RPG_STATUS_RPG_INIT   ((uint8_t) 0x10) /* Reprograming cycle initiated. */
#define	DIFF_P_STATUS_I2C_RPG_STATUS_RPG_CPLT   ((uint8_t) 0x00) /* Reprograming cycle completed. */
#define	DIFF_P_STATUS_I2C_RPG_RPG_SUCCESS   ((uint8_t) 0x20) /* I2C Reprograming successful. */
#define	DIFF_P_STATUS_I2C_RPG_NO_RPG   ((uint8_t) 0x00) /* No Reprograming has taken place. */
#define	DIFF_P_STATUS_I2C_RPG_CNT_CANT_RPG   ((uint8_t) 0x40) /* I2C address cannot be reprogrammed. */
#define	DIFF_P_STATUS_I2C_RPG_CNT_CAN_RPG   ((uint8_t) 0x00) /* I2C address can be reprogrammed. */
#define	DIFF_P_STATUS_ACTIVE_MODE_ACTIVE   ((uint8_t) 0x80) /* Sensor is in active mode. */
#define	DIFF_P_STATUS_ACTIVE_MODE_STANDBY   ((uint8_t) 0x00) /* Sensor is in standby mode. */
#define	DIFF_P_CTRL_REG1_SBYB_MASK   ((uint8_t) 0x01)
#define	DIFF_P_CTRL_REG1_SBYB_SHIFT   ((uint8_t) 0)
#define	DIFF_P_CTRL_REG1_OST_MASK   ((uint8_t) 0x02)
#define	DIFF_P_CTRL_REG1_OST_SHIFT   ((uint8_t) 1)
#define	DIFF_P_CTRL_REG1_RST_MASK   ((uint8_t) 0x04)
#define	DIFF_P_CTRL_REG1_RST_SHIFT   ((uint8_t) 2)
#define	DIFF_P_CTRL_REG1_OSR_MASK   ((uint8_t) 0xF8)
#define	DIFF_P_CTRL_REG1_OSR_SHIFT   ((uint8_t) 3)
#define	DIFF_P_CTRL_REG1_SBYB_ACTIVE   ((uint8_t) 0x01) /* Part is ACTIVE. */
#define	DIFF_P_CTRL_REG1_SBYB_STANDBY   ((uint8_t) 0x00) /* Part is in STANDBY mode. */
#define	DIFF_P_CTRL_REG1_OST_ONESHOT   ((uint8_t) 0x02) /* One Shot Mode. */
#define	DIFF_P_CTRL_REG1_OST_NORMAL   ((uint8_t) 0x00) /* Normal operating mode. */
#define	DIFF_P_CTRL_REG1_RST_RESET   ((uint8_t) 0x04) /* Device will be reset. */
#define	DIFF_P_CTRL_REG1_RST_NORMAL   ((uint8_t) 0x00) /* Normal operating mode. */
#define	DIFF_P_CTRL_REG1_OSR_OSR1   ((uint8_t) 0x00) /* Oversampling Rate#1. */
#define	DIFF_P_CTRL_REG1_OSR_OSR2   ((uint8_t) 0x08) /* Oversampling Rate#2. */
#define	DIFF_P_CTRL_REG1_OSR_OSR4   ((uint8_t) 0x10) /* Oversampling Rate#4. */
#define	DIFF_P_CTRL_REG1_OSR_OSR8   ((uint8_t) 0x18) /* Oversampling Rate#8. */
#define	DIFF_P_CTRL_REG1_OSR_OSR16   ((uint8_t) 0x20) /* Oversampling Rate#16. */
#define	DIFF_P_CTRL_REG1_OSR_OSR32   ((uint8_t) 0x28) /* Oversampling Rate#32. */
#define	DIFF_P_CTRL_REG1_OSR_OSR64   ((uint8_t) 0x30) /* Oversampling Rate#64. */
#define	DIFF_P_CTRL_REG1_OSR_OSR128   ((uint8_t) 0x38) /* Oversampling Rate#128. */
#define	DIFF_P_CTRL_REG1_OSR_OSR256   ((uint8_t) 0x40) /* Oversampling Rate#256. */
#define	DIFF_P_CTRL_REG1_OSR_OSR512   ((uint8_t) 0x48) /* Oversampling Rate#512. */
#define	DIFF_P_CTRL_REG1_OSR_OSR768   ((uint8_t) 0x50) /* Oversampling Rate#768. */
#define	DIFF_P_CTRL_REG1_OSR_OSR1024   ((uint8_t) 0x58) /* Oversampling Rate#1024. */
#define	DIFF_P_CTRL_REG1_OSR_OSR1280   ((uint8_t) 0x60) /* Oversampling Rate#1280. */
#define	DIFF_P_CTRL_REG1_OSR_OSR1536   ((uint8_t) 0x68) /* Oversampling Rate#1536. */
#define	DIFF_P_CTRL_REG1_OSR_OSR2048   ((uint8_t) 0x70) /* Oversampling Rate#2048. */
#define	DIFF_P_CTRL_REG1_OSR_OSR2560   ((uint8_t) 0x78) /* Oversampling Rate#2560. */
#define	DIFF_P_CTRL_REG1_OSR_OSR3072   ((uint8_t) 0x80) /* Oversampling Rate#3072. */
#define	DIFF_P_CTRL_REG1_OSR_OSR4096   ((uint8_t) 0x88) /* Oversampling Rate#4096. */
#define	DIFF_P_CTRL_REG1_OSR_OSR5120   ((uint8_t) 0x90) /* Oversampling Rate#5120. */
#define	DIFF_P_CTRL_REG1_OSR_OSR6144   ((uint8_t) 0x98) /* Oversampling Rate#6144. */
#define	DIFF_P_CTRL_REG1_OSR_OSR7168   ((uint8_t) 0xa0) /* Oversampling Rate#7168. */
#define	DIFF_P_CTRL_REG1_OSR_OSR8192   ((uint8_t) 0xa8) /* Oversampling Rate#8192. */
#define	DIFF_P_CTRL_REG2_ODR_MASK   ((uint8_t) 0x0F)
#define	DIFF_P_CTRL_REG2_ODR_SHIFT   ((uint8_t) 0)
#define	DIFF_P_CTRL_REG2_F_READ_MASK   ((uint8_t) 0x20)
#define	DIFF_P_CTRL_REG2_F_READ_SHIFT   ((uint8_t) 5)
#define	DIFF_P_CTRL_REG2_BRWNOUT_EN_MASK   ((uint8_t) 0x40)
#define	DIFF_P_CTRL_REG2_BRWNOUT_EN_SHIFT   ((uint8_t) 6)
#define	DIFF_P_CTRL_REG2_CTRL_AC_MASK   ((uint8_t) 0x80)
#define	DIFF_P_CTRL_REG2_CTRL_AC_SHIFT   ((uint8_t) 7)
#define	DIFF_P_CTRL_REG2_ODR_ODR3200   ((uint8_t) 0x00) /* Output Data Rate#3200. */
#define	DIFF_P_CTRL_REG2_ODR_ODR1600   ((uint8_t) 0x01) /* Output Data Rate#1600. */
#define	DIFF_P_CTRL_REG2_ODR_ODR800   ((uint8_t) 0x02) /* Output Data Rate#800. */
#define	DIFF_P_CTRL_REG2_ODR_ODR400   ((uint8_t) 0x03) /* Output Data Rate#400. */
#define	DIFF_P_CTRL_REG2_ODR_ODR200   ((uint8_t) 0x04) /* Output Data Rate#200. */
#define	DIFF_P_CTRL_REG2_ODR_ODR100   ((uint8_t) 0x05) /* Output Data Rate#100. */
#define	DIFF_P_CTRL_REG2_ODR_ODR50   ((uint8_t) 0x06) /* Output Data Rate#50. */
#define	DIFF_P_CTRL_REG2_ODR_ODR25   ((uint8_t) 0x07) /* Output Data Rate#25. */
#define	DIFF_P_CTRL_REG2_ODR_ODR12P5   ((uint8_t) 0x08) /* Output Data Rate#12.5. */
#define	DIFF_P_CTRL_REG2_ODR_ODR6P25   ((uint8_t) 0x09) /* Output Data Rate#6.25. */
#define	DIFF_P_CTRL_REG2_ODR_ODR3P125   ((uint8_t) 0x0a) /* Output Data Rate#3.125. */
#define	DIFF_P_CTRL_REG2_ODR_ODR1P563   ((uint8_t) 0x0b) /* Output Data Rate#1.563. */
#define	DIFF_P_CTRL_REG2_ODR_ODR0P781   ((uint8_t) 0x0c) /* Output Data Rate#0.781. */
#define	DIFF_P_CTRL_REG2_F_READ_NORMAL   ((uint8_t) 0x20) /* Loops between all register addresses. */
#define	DIFF_P_CTRL_REG2_F_READ_FASTREAD   ((uint8_t) 0x00) /* Loops between register address 0x00 and 0x04. */
#define	DIFF_P_CTRL_REG2_BRWNOUT_EN_ENABLED   ((uint8_t) 0x40) /* Internal brown out circuit is enabled. */
#define	DIFF_P_CTRL_REG2_BRWNOUT_EN_DISABLED   ((uint8_t) 0x00) /* Internal brown out circuit is disabled. */
#define	DIFF_P_CTRL_REG2_CTRL_AC_CALRUN   ((uint8_t) 0x80) /* Run Calibration Algorithm. */
#define	DIFF_P_CTRL_REG2_CTRL_AC_NOCALRUN   ((uint8_t) 0x00) /* Calibration Algorithm not run. */
#define	DIFF_P_CTRL_REG3_PP_OD2_MASK   ((uint8_t) 0x01)
#define	DIFF_P_CTRL_REG3_PP_OD2_SHIFT   ((uint8_t) 0)
#define	DIFF_P_CTRL_REG3_IPOL2_MASK   ((uint8_t) 0x02)
#define	DIFF_P_CTRL_REG3_IPOL2_SHIFT   ((uint8_t) 1)
#define	DIFF_P_CTRL_REG3_PP_OD1_MASK   ((uint8_t) 0x10)
#define	DIFF_P_CTRL_REG3_PP_OD1_SHIFT   ((uint8_t) 4)
#define	DIFF_P_CTRL_REG3_IPOL1_MASK   ((uint8_t) 0x20)
#define	DIFF_P_CTRL_REG3_IPOL1_SHIFT   ((uint8_t) 5)
#define	DIFF_P_CTRL_REG3_PP_OD2_OPENDRAIN   ((uint8_t) 0x01) /* Open drain. */
#define	DIFF_P_CTRL_REG3_PP_OD2_PUSHPULL   ((uint8_t) 0x00) /* Push-pull. */
#define	DIFF_P_CTRL_REG3_IPOL2_ACTIVE_HIGH   ((uint8_t) 0x02) /* Active High. */
#define	DIFF_P_CTRL_REG3_IPOL2_ACTIVE_LOW   ((uint8_t) 0x00) /* Active Low. */
#define	DIFF_P_CTRL_REG3_PP_OD1_OPENDRAIN   ((uint8_t) 0x10) /* Open drain. */
#define	DIFF_P_CTRL_REG3_PP_OD1_PUSHPULL   ((uint8_t) 0x00) /* Push-pull. */
#define	DIFF_P_CTRL_REG3_IPOL1_ACTIVE_HIGH   ((uint8_t) 0x20) /* Active High. */
#define	DIFF_P_CTRL_REG3_IPOL1_ACTIVE_LOW   ((uint8_t) 0x00) /* Active Low. */
#define	DIFF_P_INT_ROUTE0_PDU_MASK   ((uint8_t) 0x01)
#define	DIFF_P_INT_ROUTE0_PDU_SHIFT   ((uint8_t) 0)
#define	DIFF_P_INT_ROUTE0_PDO_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_ROUTE0_PDO_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_ROUTE0_VERRA_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_ROUTE0_VERRA_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_ROUTE0_TDR_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_ROUTE0_TDR_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_ROUTE0_PDR_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_ROUTE0_PDR_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_ROUTE0_TOW_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_ROUTE0_TOW_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_ROUTE0_POW_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_ROUTE0_POW_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_ROUTE0_PDU_INT2   ((uint8_t) 0x01) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_PDU_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_PDO_INT2   ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_PDO_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_VERRA_INT2   ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_VERRA_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_TDR_INT2   ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_TDR_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_PDR_INT2   ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_PDR_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_TOW_INT2   ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_TOW_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE0_POW_INT2   ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE0_POW_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_P_WCHG_MASK   ((uint8_t) 0x02)
#define	DIFF_P_INT_ROUTE1_P_WCHG_SHIFT   ((uint8_t) 1)
#define	DIFF_P_INT_ROUTE1_P_TGT2_MASK   ((uint8_t) 0x04)
#define	DIFF_P_INT_ROUTE1_P_TGT2_SHIFT   ((uint8_t) 2)
#define	DIFF_P_INT_ROUTE1_P_TGT1_MASK   ((uint8_t) 0x08)
#define	DIFF_P_INT_ROUTE1_P_TGT1_SHIFT   ((uint8_t) 3)
#define	DIFF_P_INT_ROUTE1_P_TGT0_MASK   ((uint8_t) 0x10)
#define	DIFF_P_INT_ROUTE1_P_TGT0_SHIFT   ((uint8_t) 4)
#define	DIFF_P_INT_ROUTE1_T_TGT_MASK   ((uint8_t) 0x20)
#define	DIFF_P_INT_ROUTE1_T_TGT_SHIFT   ((uint8_t) 5)
#define	DIFF_P_INT_ROUTE1_TDU_MASK   ((uint8_t) 0x40)
#define	DIFF_P_INT_ROUTE1_TDU_SHIFT   ((uint8_t) 6)
#define	DIFF_P_INT_ROUTE1_TDO_MASK   ((uint8_t) 0x80)
#define	DIFF_P_INT_ROUTE1_TDO_SHIFT   ((uint8_t) 7)
#define	DIFF_P_INT_ROUTE1_P_WCHG_INT2   ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_P_WCHG_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT2_INT2   ((uint8_t) 0x04) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT2_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT1_INT2   ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT1_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT0_INT2   ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_P_TGT0_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_T_TGT_INT2   ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_T_TGT_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_TDU_INT2   ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_TDU_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */
#define	DIFF_P_INT_ROUTE1_TDO_INT2   ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */
#define	DIFF_P_INT_ROUTE1_TDO_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Typedefs
typedef uint8_t	DIFF_P_OUT_P_LSB_t
typedef uint8_t	DIFF_P_OUT_P_MSB_t
typedef uint8_t	DIFF_P_OUT_T_t
typedef uint8_t	DIFF_P_P_MIN_LSB_t
typedef uint8_t	DIFF_P_P_MIN_MSB_t
typedef uint8_t	DIFF_P_T_MIN_t
typedef uint8_t	DIFF_P_P_MAX_LSB_t
typedef uint8_t	DIFF_P_P_MAX_MSB_t
typedef uint8_t	DIFF_P_T_MAX_t
typedef uint8_t	DIFF_P_WHO_AM_I_t
typedef uint8_t	DIFF_P_OFF_P_LSB_t
typedef uint8_t	DIFF_P_OFF_P_MSB_t
typedef uint8_t	DIFF_P_OFF_CAL_P_LSB_t
typedef uint8_t	DIFF_P_OFF_CAL_P_MSB_t
typedef uint8_t	DIFF_P_OFF_T_t
typedef uint8_t	DIFF_P_P_TGT0_LSB_t
typedef uint8_t	DIFF_P_P_TGT0_MSB_t
typedef uint8_t	DIFF_P_P_TGT1_LSB_t
typedef uint8_t	DIFF_P_P_TGT1_MSB_t
typedef uint8_t	DIFF_P_P_TGT2_LSB_t
typedef uint8_t	DIFF_P_P_TGT2_MSB_t
typedef uint8_t	DIFF_P_T_TGT_t
typedef uint8_t	DIFF_P_I2C_ADDRESS_t
typedef uint8_t	DIFF_P_PROD_REV_t
typedef uint8_t	DIFF_P_OFF_MOP_LSB_t
typedef uint8_t	DIFF_P_OFF_MOP_MSB_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE7_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE6_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE5_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE4_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE3_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE2_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE1_t
typedef uint8_t	DIFF_P_SERIALNUMBER_BYTE0_t

Enumerations
enum	{   DIFF_P_INT_STATUS_0 = 0x00, DIFF_P_INT_STATUS_1 = 0x01, DIFF_P_OUT_P_LSB = 0x02, DIFF_P_OUT_P_MSB = 0x03,   DIFF_P_OUT_T = 0x04, DIFF_P_P_MIN_LSB = 0x05, DIFF_P_P_MIN_MSB = 0x06, DIFF_P_T_MIN = 0x07,   DIFF_P_P_MAX_LSB = 0x08, DIFF_P_P_MAX_MSB = 0x09, DIFF_P_T_MAX = 0x0A, DIFF_P_INT_MASK0 = 0x0B,   DIFF_P_INT_MASK1 = 0x0C, DIFF_P_STATUS = 0x12, DIFF_P_WHO_AM_I = 0x13, DIFF_P_OFF_P_LSB = 0x14,   DIFF_P_OFF_P_MSB = 0x15, DIFF_P_OFF_CAL_P_LSB = 0x16, DIFF_P_OFF_CAL_P_MSB = 0x17, DIFF_P_OFF_T = 0x18,   DIFF_P_P_TGT0_LSB = 0x19, DIFF_P_P_TGT0_MSB = 0x1A, DIFF_P_P_TGT1_LSB = 0x1B, DIFF_P_P_TGT1_MSB = 0x1C,   DIFF_P_P_TGT2_LSB = 0x1D, DIFF_P_P_TGT2_MSB = 0x1E, DIFF_P_T_TGT = 0x1F, DIFF_P_CTRL_REG1 = 0x20,   DIFF_P_CTRL_REG2 = 0x21, DIFF_P_CTRL_REG3 = 0x22, DIFF_P_INT_ROUTE0 = 0x23, DIFF_P_INT_ROUTE1 = 0x24,   DIFF_P_I2C_ADDRESS = 0x61, DIFF_P_WHO_AM_I_ = 0x62, DIFF_P_PROD_REV = 0x63, DIFF_P_OFF_MOP_LSB = 0x64,   DIFF_P_OFF_MOP_MSB = 0x65, DIFF_P_SERIALNUMBER_BYTE7 = 0x66, DIFF_P_SERIALNUMBER_BYTE6 = 0x67, DIFF_P_SERIALNUMBER_BYTE5 = 0x68,   DIFF_P_SERIALNUMBER_BYTE4 = 0x69, DIFF_P_SERIALNUMBER_BYTE3 = 0x6A, DIFF_P_SERIALNUMBER_BYTE2 = 0x6B, DIFF_P_SERIALNUMBER_BYTE1 = 0x6C,   DIFF_P_SERIALNUMBER_BYTE0 = 0x6D }

Detailed Description

The diff_p.h contains the DIFF_P Pressure sensor register definitions, access macros, and its bit mask.

Definition in file diff_p.h.

Macro Definition Documentation

DIFF_P_CTRL_REG1_OSR_MASK

#define DIFF_P_CTRL_REG1_OSR_MASK   ((uint8_t) 0xF8)

Definition at line 709 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR1

#define DIFF_P_CTRL_REG1_OSR_OSR1   ((uint8_t) 0x00) /* Oversampling Rate#1. */

Definition at line 722 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR1024

#define DIFF_P_CTRL_REG1_OSR_OSR1024   ((uint8_t) 0x58) /* Oversampling Rate#1024. */

Definition at line 733 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR128

#define DIFF_P_CTRL_REG1_OSR_OSR128   ((uint8_t) 0x38) /* Oversampling Rate#128. */

Definition at line 729 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR1280

#define DIFF_P_CTRL_REG1_OSR_OSR1280   ((uint8_t) 0x60) /* Oversampling Rate#1280. */

Definition at line 734 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR1536

#define DIFF_P_CTRL_REG1_OSR_OSR1536   ((uint8_t) 0x68) /* Oversampling Rate#1536. */

Definition at line 735 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR16

#define DIFF_P_CTRL_REG1_OSR_OSR16   ((uint8_t) 0x20) /* Oversampling Rate#16. */

Definition at line 726 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR2

#define DIFF_P_CTRL_REG1_OSR_OSR2   ((uint8_t) 0x08) /* Oversampling Rate#2. */

Definition at line 723 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR2048

#define DIFF_P_CTRL_REG1_OSR_OSR2048   ((uint8_t) 0x70) /* Oversampling Rate#2048. */

Definition at line 736 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR256

#define DIFF_P_CTRL_REG1_OSR_OSR256   ((uint8_t) 0x40) /* Oversampling Rate#256. */

Definition at line 730 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR2560

#define DIFF_P_CTRL_REG1_OSR_OSR2560   ((uint8_t) 0x78) /* Oversampling Rate#2560. */

Definition at line 737 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR3072

#define DIFF_P_CTRL_REG1_OSR_OSR3072   ((uint8_t) 0x80) /* Oversampling Rate#3072. */

Definition at line 738 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR32

#define DIFF_P_CTRL_REG1_OSR_OSR32   ((uint8_t) 0x28) /* Oversampling Rate#32. */

Definition at line 727 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR4

#define DIFF_P_CTRL_REG1_OSR_OSR4   ((uint8_t) 0x10) /* Oversampling Rate#4. */

Definition at line 724 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR4096

#define DIFF_P_CTRL_REG1_OSR_OSR4096   ((uint8_t) 0x88) /* Oversampling Rate#4096. */

Definition at line 739 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR512

#define DIFF_P_CTRL_REG1_OSR_OSR512   ((uint8_t) 0x48) /* Oversampling Rate#512. */

Definition at line 731 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR5120

#define DIFF_P_CTRL_REG1_OSR_OSR5120   ((uint8_t) 0x90) /* Oversampling Rate#5120. */

Definition at line 740 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR6144

#define DIFF_P_CTRL_REG1_OSR_OSR6144   ((uint8_t) 0x98) /* Oversampling Rate#6144. */

Definition at line 741 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR64

#define DIFF_P_CTRL_REG1_OSR_OSR64   ((uint8_t) 0x30) /* Oversampling Rate#64. */

Definition at line 728 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR7168

#define DIFF_P_CTRL_REG1_OSR_OSR7168   ((uint8_t) 0xa0) /* Oversampling Rate#7168. */

Definition at line 742 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR768

#define DIFF_P_CTRL_REG1_OSR_OSR768   ((uint8_t) 0x50) /* Oversampling Rate#768. */

Definition at line 732 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR8

#define DIFF_P_CTRL_REG1_OSR_OSR8   ((uint8_t) 0x18) /* Oversampling Rate#8. */

Definition at line 725 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_OSR8192

#define DIFF_P_CTRL_REG1_OSR_OSR8192   ((uint8_t) 0xa8) /* Oversampling Rate#8192. */

Definition at line 743 of file diff_p.h.

DIFF_P_CTRL_REG1_OSR_SHIFT

#define DIFF_P_CTRL_REG1_OSR_SHIFT   ((uint8_t) 3)

Definition at line 710 of file diff_p.h.

DIFF_P_CTRL_REG1_OST_MASK

#define DIFF_P_CTRL_REG1_OST_MASK   ((uint8_t) 0x02)

Definition at line 703 of file diff_p.h.

DIFF_P_CTRL_REG1_OST_NORMAL

#define DIFF_P_CTRL_REG1_OST_NORMAL   ((uint8_t) 0x00) /* Normal operating mode. */

Definition at line 719 of file diff_p.h.

DIFF_P_CTRL_REG1_OST_ONESHOT

#define DIFF_P_CTRL_REG1_OST_ONESHOT   ((uint8_t) 0x02) /* One Shot Mode. */

Definition at line 718 of file diff_p.h.

DIFF_P_CTRL_REG1_OST_SHIFT

#define DIFF_P_CTRL_REG1_OST_SHIFT   ((uint8_t) 1)

Definition at line 704 of file diff_p.h.

DIFF_P_CTRL_REG1_RST_MASK

#define DIFF_P_CTRL_REG1_RST_MASK   ((uint8_t) 0x04)

Definition at line 706 of file diff_p.h.

Referenced by DIFF_P_I2C_DeInit(), and DIFF_P_SPI_DeInit().

DIFF_P_CTRL_REG1_RST_NORMAL

#define DIFF_P_CTRL_REG1_RST_NORMAL   ((uint8_t) 0x00) /* Normal operating mode. */

Definition at line 721 of file diff_p.h.

DIFF_P_CTRL_REG1_RST_RESET

#define DIFF_P_CTRL_REG1_RST_RESET   ((uint8_t) 0x04) /* Device will be reset. */

Definition at line 720 of file diff_p.h.

Referenced by DIFF_P_I2C_DeInit(), and DIFF_P_SPI_DeInit().

DIFF_P_CTRL_REG1_RST_SHIFT

#define DIFF_P_CTRL_REG1_RST_SHIFT   ((uint8_t) 2)

Definition at line 707 of file diff_p.h.

DIFF_P_CTRL_REG1_SBYB_ACTIVE

#define DIFF_P_CTRL_REG1_SBYB_ACTIVE   ((uint8_t) 0x01) /* Part is ACTIVE. */

Definition at line 716 of file diff_p.h.

Referenced by DIFF_P_I2C_Configure(), and DIFF_P_SPI_Configure().

DIFF_P_CTRL_REG1_SBYB_MASK

#define DIFF_P_CTRL_REG1_SBYB_MASK   ((uint8_t) 0x01)

Definition at line 700 of file diff_p.h.

Referenced by DIFF_P_I2C_Configure(), DIFF_P_I2C_Initialize(), DIFF_P_SPI_Configure(), and DIFF_P_SPI_Initialize().

DIFF_P_CTRL_REG1_SBYB_SHIFT

#define DIFF_P_CTRL_REG1_SBYB_SHIFT   ((uint8_t) 0)

Definition at line 701 of file diff_p.h.

DIFF_P_CTRL_REG1_SBYB_STANDBY

#define DIFF_P_CTRL_REG1_SBYB_STANDBY   ((uint8_t) 0x00) /* Part is in STANDBY mode. */

Definition at line 717 of file diff_p.h.

Referenced by DIFF_P_I2C_Configure(), DIFF_P_I2C_Initialize(), DIFF_P_SPI_Configure(), and DIFF_P_SPI_Initialize().

DIFF_P_CTRL_REG2_BRWNOUT_EN_DISABLED

#define DIFF_P_CTRL_REG2_BRWNOUT_EN_DISABLED   ((uint8_t) 0x00) /* Internal brown out circuit is disabled. */

Definition at line 806 of file diff_p.h.

DIFF_P_CTRL_REG2_BRWNOUT_EN_ENABLED

#define DIFF_P_CTRL_REG2_BRWNOUT_EN_ENABLED   ((uint8_t) 0x40) /* Internal brown out circuit is enabled. */

Definition at line 805 of file diff_p.h.

DIFF_P_CTRL_REG2_BRWNOUT_EN_MASK

#define DIFF_P_CTRL_REG2_BRWNOUT_EN_MASK   ((uint8_t) 0x40)

Definition at line 780 of file diff_p.h.

DIFF_P_CTRL_REG2_BRWNOUT_EN_SHIFT

#define DIFF_P_CTRL_REG2_BRWNOUT_EN_SHIFT   ((uint8_t) 6)

Definition at line 781 of file diff_p.h.

DIFF_P_CTRL_REG2_CTRL_AC_CALRUN

#define DIFF_P_CTRL_REG2_CTRL_AC_CALRUN   ((uint8_t) 0x80) /* Run Calibration Algorithm. */

Definition at line 807 of file diff_p.h.

Referenced by DIFF_P_I2C_Initialize(), and DIFF_P_SPI_Initialize().

DIFF_P_CTRL_REG2_CTRL_AC_MASK

#define DIFF_P_CTRL_REG2_CTRL_AC_MASK   ((uint8_t) 0x80)

Definition at line 783 of file diff_p.h.

Referenced by DIFF_P_I2C_Initialize(), and DIFF_P_SPI_Initialize().

DIFF_P_CTRL_REG2_CTRL_AC_NOCALRUN

#define DIFF_P_CTRL_REG2_CTRL_AC_NOCALRUN   ((uint8_t) 0x00) /* Calibration Algorithm not run. */

Definition at line 808 of file diff_p.h.

DIFF_P_CTRL_REG2_CTRL_AC_SHIFT

#define DIFF_P_CTRL_REG2_CTRL_AC_SHIFT   ((uint8_t) 7)

Definition at line 784 of file diff_p.h.

DIFF_P_CTRL_REG2_F_READ_FASTREAD

#define DIFF_P_CTRL_REG2_F_READ_FASTREAD   ((uint8_t) 0x00) /* Loops between register address 0x00 and 0x04. */

Definition at line 804 of file diff_p.h.

DIFF_P_CTRL_REG2_F_READ_MASK

#define DIFF_P_CTRL_REG2_F_READ_MASK   ((uint8_t) 0x20)

Definition at line 777 of file diff_p.h.

DIFF_P_CTRL_REG2_F_READ_NORMAL

#define DIFF_P_CTRL_REG2_F_READ_NORMAL   ((uint8_t) 0x20) /* Loops between all register addresses. */

Definition at line 803 of file diff_p.h.

DIFF_P_CTRL_REG2_F_READ_SHIFT

#define DIFF_P_CTRL_REG2_F_READ_SHIFT   ((uint8_t) 5)

Definition at line 778 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_MASK

#define DIFF_P_CTRL_REG2_ODR_MASK   ((uint8_t) 0x0F)

Definition at line 774 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR0P781

#define DIFF_P_CTRL_REG2_ODR_ODR0P781   ((uint8_t) 0x0c) /* Output Data Rate#0.781. */

Definition at line 802 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR100

#define DIFF_P_CTRL_REG2_ODR_ODR100   ((uint8_t) 0x05) /* Output Data Rate#100. */

Definition at line 795 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR12P5

#define DIFF_P_CTRL_REG2_ODR_ODR12P5   ((uint8_t) 0x08) /* Output Data Rate#12.5. */

Definition at line 798 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR1600

#define DIFF_P_CTRL_REG2_ODR_ODR1600   ((uint8_t) 0x01) /* Output Data Rate#1600. */

Definition at line 791 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR1P563

#define DIFF_P_CTRL_REG2_ODR_ODR1P563   ((uint8_t) 0x0b) /* Output Data Rate#1.563. */

Definition at line 801 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR200

#define DIFF_P_CTRL_REG2_ODR_ODR200   ((uint8_t) 0x04) /* Output Data Rate#200. */

Definition at line 794 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR25

#define DIFF_P_CTRL_REG2_ODR_ODR25   ((uint8_t) 0x07) /* Output Data Rate#25. */

Definition at line 797 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR3200

#define DIFF_P_CTRL_REG2_ODR_ODR3200   ((uint8_t) 0x00) /* Output Data Rate#3200. */

Definition at line 790 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR3P125

#define DIFF_P_CTRL_REG2_ODR_ODR3P125   ((uint8_t) 0x0a) /* Output Data Rate#3.125. */

Definition at line 800 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR400

#define DIFF_P_CTRL_REG2_ODR_ODR400   ((uint8_t) 0x03) /* Output Data Rate#400. */

Definition at line 793 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR50

#define DIFF_P_CTRL_REG2_ODR_ODR50   ((uint8_t) 0x06) /* Output Data Rate#50. */

Definition at line 796 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR6P25

#define DIFF_P_CTRL_REG2_ODR_ODR6P25   ((uint8_t) 0x09) /* Output Data Rate#6.25. */

Definition at line 799 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_ODR800

#define DIFF_P_CTRL_REG2_ODR_ODR800   ((uint8_t) 0x02) /* Output Data Rate#800. */

Definition at line 792 of file diff_p.h.

DIFF_P_CTRL_REG2_ODR_SHIFT

#define DIFF_P_CTRL_REG2_ODR_SHIFT   ((uint8_t) 0)

Definition at line 775 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL1_ACTIVE_HIGH

#define DIFF_P_CTRL_REG3_IPOL1_ACTIVE_HIGH   ((uint8_t) 0x20) /* Active High. */

Definition at line 862 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL1_ACTIVE_LOW

#define DIFF_P_CTRL_REG3_IPOL1_ACTIVE_LOW   ((uint8_t) 0x00) /* Active Low. */

Definition at line 863 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL1_MASK

#define DIFF_P_CTRL_REG3_IPOL1_MASK   ((uint8_t) 0x20)

Definition at line 849 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL1_SHIFT

#define DIFF_P_CTRL_REG3_IPOL1_SHIFT   ((uint8_t) 5)

Definition at line 850 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL2_ACTIVE_HIGH

#define DIFF_P_CTRL_REG3_IPOL2_ACTIVE_HIGH   ((uint8_t) 0x02) /* Active High. */

Definition at line 858 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL2_ACTIVE_LOW

#define DIFF_P_CTRL_REG3_IPOL2_ACTIVE_LOW   ((uint8_t) 0x00) /* Active Low. */

Definition at line 859 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL2_MASK

#define DIFF_P_CTRL_REG3_IPOL2_MASK   ((uint8_t) 0x02)

Definition at line 843 of file diff_p.h.

DIFF_P_CTRL_REG3_IPOL2_SHIFT

#define DIFF_P_CTRL_REG3_IPOL2_SHIFT   ((uint8_t) 1)

Definition at line 844 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD1_MASK

#define DIFF_P_CTRL_REG3_PP_OD1_MASK   ((uint8_t) 0x10)

Definition at line 846 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD1_OPENDRAIN

#define DIFF_P_CTRL_REG3_PP_OD1_OPENDRAIN   ((uint8_t) 0x10) /* Open drain. */

Definition at line 860 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD1_PUSHPULL

#define DIFF_P_CTRL_REG3_PP_OD1_PUSHPULL   ((uint8_t) 0x00) /* Push-pull. */

Definition at line 861 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD1_SHIFT

#define DIFF_P_CTRL_REG3_PP_OD1_SHIFT   ((uint8_t) 4)

Definition at line 847 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD2_MASK

#define DIFF_P_CTRL_REG3_PP_OD2_MASK   ((uint8_t) 0x01)

Definition at line 840 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD2_OPENDRAIN

#define DIFF_P_CTRL_REG3_PP_OD2_OPENDRAIN   ((uint8_t) 0x01) /* Open drain. */

Definition at line 856 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD2_PUSHPULL

#define DIFF_P_CTRL_REG3_PP_OD2_PUSHPULL   ((uint8_t) 0x00) /* Push-pull. */

Definition at line 857 of file diff_p.h.

DIFF_P_CTRL_REG3_PP_OD2_SHIFT

#define DIFF_P_CTRL_REG3_PP_OD2_SHIFT   ((uint8_t) 0)

Definition at line 841 of file diff_p.h.

DIFF_P_INT_MASK0_PDO_INT_EN

#define DIFF_P_INT_MASK0_PDO_INT_EN   ((uint8_t) 0x02) /* Interrupt Enabled. */

Definition at line 393 of file diff_p.h.

DIFF_P_INT_MASK0_PDO_MASK

#define DIFF_P_INT_MASK0_PDO_MASK   ((uint8_t) 0x02)

Definition at line 370 of file diff_p.h.

DIFF_P_INT_MASK0_PDO_SHIFT

#define DIFF_P_INT_MASK0_PDO_SHIFT   ((uint8_t) 1)

Definition at line 371 of file diff_p.h.

DIFF_P_INT_MASK0_PDR_INT_EN

#define DIFF_P_INT_MASK0_PDR_INT_EN   ((uint8_t) 0x20) /* Interrupt Enabled. */

Definition at line 396 of file diff_p.h.

DIFF_P_INT_MASK0_PDR_MASK

#define DIFF_P_INT_MASK0_PDR_MASK   ((uint8_t) 0x20)

Definition at line 379 of file diff_p.h.

DIFF_P_INT_MASK0_PDR_SHIFT

#define DIFF_P_INT_MASK0_PDR_SHIFT   ((uint8_t) 5)

Definition at line 380 of file diff_p.h.

DIFF_P_INT_MASK0_PDU_INT_EN

#define DIFF_P_INT_MASK0_PDU_INT_EN   ((uint8_t) 0x01) /* Interrupt Enabled. */

Definition at line 392 of file diff_p.h.

DIFF_P_INT_MASK0_PDU_MASK

#define DIFF_P_INT_MASK0_PDU_MASK   ((uint8_t) 0x01)

Definition at line 367 of file diff_p.h.

DIFF_P_INT_MASK0_PDU_SHIFT

#define DIFF_P_INT_MASK0_PDU_SHIFT   ((uint8_t) 0)

Definition at line 368 of file diff_p.h.

DIFF_P_INT_MASK0_POW_INT_EN

#define DIFF_P_INT_MASK0_POW_INT_EN   ((uint8_t) 0x80) /* Interrupt Enabled. */

Definition at line 398 of file diff_p.h.

DIFF_P_INT_MASK0_POW_MASK

#define DIFF_P_INT_MASK0_POW_MASK   ((uint8_t) 0x80)

Definition at line 385 of file diff_p.h.

DIFF_P_INT_MASK0_POW_SHIFT

#define DIFF_P_INT_MASK0_POW_SHIFT   ((uint8_t) 7)

Definition at line 386 of file diff_p.h.

DIFF_P_INT_MASK0_TDR_INT_EN

#define DIFF_P_INT_MASK0_TDR_INT_EN   ((uint8_t) 0x10) /* Interrupt Enabled. */

Definition at line 395 of file diff_p.h.

DIFF_P_INT_MASK0_TDR_MASK

#define DIFF_P_INT_MASK0_TDR_MASK   ((uint8_t) 0x10)

Definition at line 376 of file diff_p.h.

DIFF_P_INT_MASK0_TDR_SHIFT

#define DIFF_P_INT_MASK0_TDR_SHIFT   ((uint8_t) 4)

Definition at line 377 of file diff_p.h.

DIFF_P_INT_MASK0_TOW_INT_EN

#define DIFF_P_INT_MASK0_TOW_INT_EN   ((uint8_t) 0x40) /* Interrupt Enabled. */

Definition at line 397 of file diff_p.h.

DIFF_P_INT_MASK0_TOW_MASK

#define DIFF_P_INT_MASK0_TOW_MASK   ((uint8_t) 0x40)

Definition at line 382 of file diff_p.h.

DIFF_P_INT_MASK0_TOW_SHIFT

#define DIFF_P_INT_MASK0_TOW_SHIFT   ((uint8_t) 6)

Definition at line 383 of file diff_p.h.

DIFF_P_INT_MASK0_VERRA_INT_EN

#define DIFF_P_INT_MASK0_VERRA_INT_EN   ((uint8_t) 0x08) /* Interrupt Enabled. */

Definition at line 394 of file diff_p.h.

DIFF_P_INT_MASK0_VERRA_MASK

#define DIFF_P_INT_MASK0_VERRA_MASK   ((uint8_t) 0x08)

Definition at line 373 of file diff_p.h.

DIFF_P_INT_MASK0_VERRA_SHIFT

#define DIFF_P_INT_MASK0_VERRA_SHIFT   ((uint8_t) 3)

Definition at line 374 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT0_INT_EN

#define DIFF_P_INT_MASK1_P_TGT0_INT_EN   ((uint8_t) 0x10) /* Interrupt Enabled. */

Definition at line 462 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT0_MASK

#define DIFF_P_INT_MASK1_P_TGT0_MASK   ((uint8_t) 0x10)

Definition at line 443 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT0_SHIFT

#define DIFF_P_INT_MASK1_P_TGT0_SHIFT   ((uint8_t) 4)

Definition at line 444 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT1_INT_EN

#define DIFF_P_INT_MASK1_P_TGT1_INT_EN   ((uint8_t) 0x08) /* Interrupt Enabled. */

Definition at line 461 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT1_MASK

#define DIFF_P_INT_MASK1_P_TGT1_MASK   ((uint8_t) 0x08)

Definition at line 440 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT1_SHIFT

#define DIFF_P_INT_MASK1_P_TGT1_SHIFT   ((uint8_t) 3)

Definition at line 441 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT2_INT_EN

#define DIFF_P_INT_MASK1_P_TGT2_INT_EN   ((uint8_t) 0x04) /* Interrupt Enabled. */

Definition at line 460 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT2_MASK

#define DIFF_P_INT_MASK1_P_TGT2_MASK   ((uint8_t) 0x04)

Definition at line 437 of file diff_p.h.

DIFF_P_INT_MASK1_P_TGT2_SHIFT

#define DIFF_P_INT_MASK1_P_TGT2_SHIFT   ((uint8_t) 2)

Definition at line 438 of file diff_p.h.

DIFF_P_INT_MASK1_P_WCHG_INT_EN

#define DIFF_P_INT_MASK1_P_WCHG_INT_EN   ((uint8_t) 0x02) /* Interrupt Enabled. */

Definition at line 459 of file diff_p.h.

DIFF_P_INT_MASK1_P_WCHG_MASK

#define DIFF_P_INT_MASK1_P_WCHG_MASK   ((uint8_t) 0x02)

Definition at line 434 of file diff_p.h.

DIFF_P_INT_MASK1_P_WCHG_SHIFT

#define DIFF_P_INT_MASK1_P_WCHG_SHIFT   ((uint8_t) 1)

Definition at line 435 of file diff_p.h.

DIFF_P_INT_MASK1_T_TGT_INT_EN

#define DIFF_P_INT_MASK1_T_TGT_INT_EN   ((uint8_t) 0x20) /* Interrupt Enabled. */

Definition at line 463 of file diff_p.h.

DIFF_P_INT_MASK1_T_TGT_MASK

#define DIFF_P_INT_MASK1_T_TGT_MASK   ((uint8_t) 0x20)

Definition at line 446 of file diff_p.h.

DIFF_P_INT_MASK1_T_TGT_SHIFT

#define DIFF_P_INT_MASK1_T_TGT_SHIFT   ((uint8_t) 5)

Definition at line 447 of file diff_p.h.

DIFF_P_INT_MASK1_TDO_INT_EN

#define DIFF_P_INT_MASK1_TDO_INT_EN   ((uint8_t) 0x80) /* Interrupt Enabled. */

Definition at line 465 of file diff_p.h.

DIFF_P_INT_MASK1_TDO_MASK

#define DIFF_P_INT_MASK1_TDO_MASK   ((uint8_t) 0x80)

Definition at line 452 of file diff_p.h.

DIFF_P_INT_MASK1_TDO_SHIFT

#define DIFF_P_INT_MASK1_TDO_SHIFT   ((uint8_t) 7)

Definition at line 453 of file diff_p.h.

DIFF_P_INT_MASK1_TDU_INT_EN

#define DIFF_P_INT_MASK1_TDU_INT_EN   ((uint8_t) 0x40) /* Interrupt Enabled. */

Definition at line 464 of file diff_p.h.

DIFF_P_INT_MASK1_TDU_MASK

#define DIFF_P_INT_MASK1_TDU_MASK   ((uint8_t) 0x40)

Definition at line 449 of file diff_p.h.

DIFF_P_INT_MASK1_TDU_SHIFT

#define DIFF_P_INT_MASK1_TDU_SHIFT   ((uint8_t) 6)

Definition at line 450 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDO_INT1

#define DIFF_P_INT_ROUTE0_PDO_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 927 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDO_INT2

#define DIFF_P_INT_ROUTE0_PDO_INT2   ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */

Definition at line 926 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDO_MASK

#define DIFF_P_INT_ROUTE0_PDO_MASK   ((uint8_t) 0x02)

Definition at line 902 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDO_SHIFT

#define DIFF_P_INT_ROUTE0_PDO_SHIFT   ((uint8_t) 1)

Definition at line 903 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDR_INT1

#define DIFF_P_INT_ROUTE0_PDR_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 933 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDR_INT2

#define DIFF_P_INT_ROUTE0_PDR_INT2   ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */

Definition at line 932 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDR_MASK

#define DIFF_P_INT_ROUTE0_PDR_MASK   ((uint8_t) 0x20)

Definition at line 911 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDR_SHIFT

#define DIFF_P_INT_ROUTE0_PDR_SHIFT   ((uint8_t) 5)

Definition at line 912 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDU_INT1

#define DIFF_P_INT_ROUTE0_PDU_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 925 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDU_INT2

#define DIFF_P_INT_ROUTE0_PDU_INT2   ((uint8_t) 0x01) /* Interrupt routed to INT2 pin. */

Definition at line 924 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDU_MASK

#define DIFF_P_INT_ROUTE0_PDU_MASK   ((uint8_t) 0x01)

Definition at line 899 of file diff_p.h.

DIFF_P_INT_ROUTE0_PDU_SHIFT

#define DIFF_P_INT_ROUTE0_PDU_SHIFT   ((uint8_t) 0)

Definition at line 900 of file diff_p.h.

DIFF_P_INT_ROUTE0_POW_INT1

#define DIFF_P_INT_ROUTE0_POW_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 937 of file diff_p.h.

DIFF_P_INT_ROUTE0_POW_INT2

#define DIFF_P_INT_ROUTE0_POW_INT2   ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */

Definition at line 936 of file diff_p.h.

DIFF_P_INT_ROUTE0_POW_MASK

#define DIFF_P_INT_ROUTE0_POW_MASK   ((uint8_t) 0x80)

Definition at line 917 of file diff_p.h.

DIFF_P_INT_ROUTE0_POW_SHIFT

#define DIFF_P_INT_ROUTE0_POW_SHIFT   ((uint8_t) 7)

Definition at line 918 of file diff_p.h.

DIFF_P_INT_ROUTE0_TDR_INT1

#define DIFF_P_INT_ROUTE0_TDR_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 931 of file diff_p.h.

DIFF_P_INT_ROUTE0_TDR_INT2

#define DIFF_P_INT_ROUTE0_TDR_INT2   ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */

Definition at line 930 of file diff_p.h.

DIFF_P_INT_ROUTE0_TDR_MASK

#define DIFF_P_INT_ROUTE0_TDR_MASK   ((uint8_t) 0x10)

Definition at line 908 of file diff_p.h.

DIFF_P_INT_ROUTE0_TDR_SHIFT

#define DIFF_P_INT_ROUTE0_TDR_SHIFT   ((uint8_t) 4)

Definition at line 909 of file diff_p.h.

DIFF_P_INT_ROUTE0_TOW_INT1

#define DIFF_P_INT_ROUTE0_TOW_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 935 of file diff_p.h.

DIFF_P_INT_ROUTE0_TOW_INT2

#define DIFF_P_INT_ROUTE0_TOW_INT2   ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */

Definition at line 934 of file diff_p.h.

DIFF_P_INT_ROUTE0_TOW_MASK

#define DIFF_P_INT_ROUTE0_TOW_MASK   ((uint8_t) 0x40)

Definition at line 914 of file diff_p.h.

DIFF_P_INT_ROUTE0_TOW_SHIFT

#define DIFF_P_INT_ROUTE0_TOW_SHIFT   ((uint8_t) 6)

Definition at line 915 of file diff_p.h.

DIFF_P_INT_ROUTE0_VERRA_INT1

#define DIFF_P_INT_ROUTE0_VERRA_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 929 of file diff_p.h.

DIFF_P_INT_ROUTE0_VERRA_INT2

#define DIFF_P_INT_ROUTE0_VERRA_INT2   ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */

Definition at line 928 of file diff_p.h.

DIFF_P_INT_ROUTE0_VERRA_MASK

#define DIFF_P_INT_ROUTE0_VERRA_MASK   ((uint8_t) 0x08)

Definition at line 905 of file diff_p.h.

DIFF_P_INT_ROUTE0_VERRA_SHIFT

#define DIFF_P_INT_ROUTE0_VERRA_SHIFT   ((uint8_t) 3)

Definition at line 906 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT0_INT1

#define DIFF_P_INT_ROUTE1_P_TGT0_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1005 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT0_INT2

#define DIFF_P_INT_ROUTE1_P_TGT0_INT2   ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */

Definition at line 1004 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT0_MASK

#define DIFF_P_INT_ROUTE1_P_TGT0_MASK   ((uint8_t) 0x10)

Definition at line 982 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT0_SHIFT

#define DIFF_P_INT_ROUTE1_P_TGT0_SHIFT   ((uint8_t) 4)

Definition at line 983 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT1_INT1

#define DIFF_P_INT_ROUTE1_P_TGT1_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1003 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT1_INT2

#define DIFF_P_INT_ROUTE1_P_TGT1_INT2   ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */

Definition at line 1002 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT1_MASK

#define DIFF_P_INT_ROUTE1_P_TGT1_MASK   ((uint8_t) 0x08)

Definition at line 979 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT1_SHIFT

#define DIFF_P_INT_ROUTE1_P_TGT1_SHIFT   ((uint8_t) 3)

Definition at line 980 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT2_INT1

#define DIFF_P_INT_ROUTE1_P_TGT2_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1001 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT2_INT2

#define DIFF_P_INT_ROUTE1_P_TGT2_INT2   ((uint8_t) 0x04) /* Interrupt routed to INT2 pin. */

Definition at line 1000 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT2_MASK

#define DIFF_P_INT_ROUTE1_P_TGT2_MASK   ((uint8_t) 0x04)

Definition at line 976 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_TGT2_SHIFT

#define DIFF_P_INT_ROUTE1_P_TGT2_SHIFT   ((uint8_t) 2)

Definition at line 977 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_WCHG_INT1

#define DIFF_P_INT_ROUTE1_P_WCHG_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 999 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_WCHG_INT2

#define DIFF_P_INT_ROUTE1_P_WCHG_INT2   ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */

Definition at line 998 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_WCHG_MASK

#define DIFF_P_INT_ROUTE1_P_WCHG_MASK   ((uint8_t) 0x02)

Definition at line 973 of file diff_p.h.

DIFF_P_INT_ROUTE1_P_WCHG_SHIFT

#define DIFF_P_INT_ROUTE1_P_WCHG_SHIFT   ((uint8_t) 1)

Definition at line 974 of file diff_p.h.

DIFF_P_INT_ROUTE1_T_TGT_INT1

#define DIFF_P_INT_ROUTE1_T_TGT_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1007 of file diff_p.h.

DIFF_P_INT_ROUTE1_T_TGT_INT2

#define DIFF_P_INT_ROUTE1_T_TGT_INT2   ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */

Definition at line 1006 of file diff_p.h.

DIFF_P_INT_ROUTE1_T_TGT_MASK

#define DIFF_P_INT_ROUTE1_T_TGT_MASK   ((uint8_t) 0x20)

Definition at line 985 of file diff_p.h.

DIFF_P_INT_ROUTE1_T_TGT_SHIFT

#define DIFF_P_INT_ROUTE1_T_TGT_SHIFT   ((uint8_t) 5)

Definition at line 986 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDO_INT1

#define DIFF_P_INT_ROUTE1_TDO_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1011 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDO_INT2

#define DIFF_P_INT_ROUTE1_TDO_INT2   ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */

Definition at line 1010 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDO_MASK

#define DIFF_P_INT_ROUTE1_TDO_MASK   ((uint8_t) 0x80)

Definition at line 991 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDO_SHIFT

#define DIFF_P_INT_ROUTE1_TDO_SHIFT   ((uint8_t) 7)

Definition at line 992 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDU_INT1

#define DIFF_P_INT_ROUTE1_TDU_INT1   ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */

Definition at line 1009 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDU_INT2

#define DIFF_P_INT_ROUTE1_TDU_INT2   ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */

Definition at line 1008 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDU_MASK

#define DIFF_P_INT_ROUTE1_TDU_MASK   ((uint8_t) 0x40)

Definition at line 988 of file diff_p.h.

DIFF_P_INT_ROUTE1_TDU_SHIFT

#define DIFF_P_INT_ROUTE1_TDU_SHIFT   ((uint8_t) 6)

Definition at line 989 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDO_MASK

#define DIFF_P_INT_STATUS_0_PDO_MASK   ((uint8_t) 0x02)

Definition at line 142 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDO_NO_OVERFLOW

#define DIFF_P_INT_STATUS_0_PDO_NO_OVERFLOW   ((uint8_t) 0x00) /* No overflow occurred. */

Definition at line 167 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDO_OVERFLOW

#define DIFF_P_INT_STATUS_0_PDO_OVERFLOW   ((uint8_t) 0x02) /* Overflow occurred. */

Definition at line 166 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDO_SHIFT

#define DIFF_P_INT_STATUS_0_PDO_SHIFT   ((uint8_t) 1)

Definition at line 143 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDR_DRDY

#define DIFF_P_INT_STATUS_0_PDR_DRDY   ((uint8_t) 0x20) /* A new set of Pressure data is ready. */

Definition at line 171 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_0_PDR_MASK

#define DIFF_P_INT_STATUS_0_PDR_MASK   ((uint8_t) 0x20)

Definition at line 151 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_0_PDR_SHIFT

#define DIFF_P_INT_STATUS_0_PDR_SHIFT   ((uint8_t) 5)

Definition at line 152 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDU_MASK

#define DIFF_P_INT_STATUS_0_PDU_MASK   ((uint8_t) 0x01)

Definition at line 139 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDU_NO_UNDERFLOW

#define DIFF_P_INT_STATUS_0_PDU_NO_UNDERFLOW   ((uint8_t) 0x00) /* No Underflow occurred. */

Definition at line 165 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDU_SHIFT

#define DIFF_P_INT_STATUS_0_PDU_SHIFT   ((uint8_t) 0)

Definition at line 140 of file diff_p.h.

DIFF_P_INT_STATUS_0_PDU_UNDERFLOW

#define DIFF_P_INT_STATUS_0_PDU_UNDERFLOW   ((uint8_t) 0x01) /* Underflow occurred. */

Definition at line 164 of file diff_p.h.

DIFF_P_INT_STATUS_0_POW_MASK

#define DIFF_P_INT_STATUS_0_POW_MASK   ((uint8_t) 0x80)

Definition at line 157 of file diff_p.h.

DIFF_P_INT_STATUS_0_POW_OWR

#define DIFF_P_INT_STATUS_0_POW_OWR   ((uint8_t) 0x80) /* Previous Pressure data was overwritten by new */

Definition at line 174 of file diff_p.h.

DIFF_P_INT_STATUS_0_POW_SHIFT

#define DIFF_P_INT_STATUS_0_POW_SHIFT   ((uint8_t) 7)

Definition at line 158 of file diff_p.h.

DIFF_P_INT_STATUS_0_TDR_DRDY

#define DIFF_P_INT_STATUS_0_TDR_DRDY   ((uint8_t) 0x10) /* A new Temperature data is ready. */

Definition at line 170 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_0_TDR_MASK

#define DIFF_P_INT_STATUS_0_TDR_MASK   ((uint8_t) 0x10)

Definition at line 148 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_0_TDR_SHIFT

#define DIFF_P_INT_STATUS_0_TDR_SHIFT   ((uint8_t) 4)

Definition at line 149 of file diff_p.h.

DIFF_P_INT_STATUS_0_TOW_MASK

#define DIFF_P_INT_STATUS_0_TOW_MASK   ((uint8_t) 0x40)

Definition at line 154 of file diff_p.h.

DIFF_P_INT_STATUS_0_TOW_OWR

#define DIFF_P_INT_STATUS_0_TOW_OWR   ((uint8_t) 0x40) /* Previous Temperature data was overwritten by new */

Definition at line 172 of file diff_p.h.

DIFF_P_INT_STATUS_0_TOW_SHIFT

#define DIFF_P_INT_STATUS_0_TOW_SHIFT   ((uint8_t) 6)

Definition at line 155 of file diff_p.h.

DIFF_P_INT_STATUS_0_VERRA_BRWNOUT

#define DIFF_P_INT_STATUS_0_VERRA_BRWNOUT   ((uint8_t) 0x08) /* Analog voltage brownout occurred. */

Definition at line 168 of file diff_p.h.

DIFF_P_INT_STATUS_0_VERRA_MASK

#define DIFF_P_INT_STATUS_0_VERRA_MASK   ((uint8_t) 0x08)

Definition at line 145 of file diff_p.h.

DIFF_P_INT_STATUS_0_VERRA_NO_BRWNOUT

#define DIFF_P_INT_STATUS_0_VERRA_NO_BRWNOUT   ((uint8_t) 0x00) /* No brownout occurred. */

Definition at line 169 of file diff_p.h.

DIFF_P_INT_STATUS_0_VERRA_SHIFT

#define DIFF_P_INT_STATUS_0_VERRA_SHIFT   ((uint8_t) 3)

Definition at line 146 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT0_MASK

#define DIFF_P_INT_STATUS_1_P_TGT0_MASK   ((uint8_t) 0x10)

Definition at line 222 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_1_P_TGT0_REACHED

#define DIFF_P_INT_STATUS_1_P_TGT0_REACHED   ((uint8_t) 0x10) /* Temperature target reached. */

Definition at line 242 of file diff_p.h.

Referenced by main().

DIFF_P_INT_STATUS_1_P_TGT0_SHIFT

#define DIFF_P_INT_STATUS_1_P_TGT0_SHIFT   ((uint8_t) 4)

Definition at line 223 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT1_MASK

#define DIFF_P_INT_STATUS_1_P_TGT1_MASK   ((uint8_t) 0x08)

Definition at line 219 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT1_REACHED

#define DIFF_P_INT_STATUS_1_P_TGT1_REACHED   ((uint8_t) 0x08) /* Temperature target reached. */

Definition at line 241 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT1_SHIFT

#define DIFF_P_INT_STATUS_1_P_TGT1_SHIFT   ((uint8_t) 3)

Definition at line 220 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT2_MASK

#define DIFF_P_INT_STATUS_1_P_TGT2_MASK   ((uint8_t) 0x04)

Definition at line 216 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT2_REACHED

#define DIFF_P_INT_STATUS_1_P_TGT2_REACHED   ((uint8_t) 0x04) /* Temperature target reached. */

Definition at line 240 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_TGT2_SHIFT

#define DIFF_P_INT_STATUS_1_P_TGT2_SHIFT   ((uint8_t) 2)

Definition at line 217 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_WCHG_MASK

#define DIFF_P_INT_STATUS_1_P_WCHG_MASK   ((uint8_t) 0x02)

Definition at line 213 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_WCHG_SHIFT

#define DIFF_P_INT_STATUS_1_P_WCHG_SHIFT   ((uint8_t) 1)

Definition at line 214 of file diff_p.h.

DIFF_P_INT_STATUS_1_P_WCHG_TH_CROSSED

#define DIFF_P_INT_STATUS_1_P_WCHG_TH_CROSSED   ((uint8_t) 0x02) /* pressure has crossed the window threshold defined */

Definition at line 238 of file diff_p.h.

DIFF_P_INT_STATUS_1_T_TGT_MASK

#define DIFF_P_INT_STATUS_1_T_TGT_MASK   ((uint8_t) 0x20)

Definition at line 225 of file diff_p.h.

DIFF_P_INT_STATUS_1_T_TGT_REACHED

#define DIFF_P_INT_STATUS_1_T_TGT_REACHED   ((uint8_t) 0x20) /* Temperature target reached. */

Definition at line 243 of file diff_p.h.

DIFF_P_INT_STATUS_1_T_TGT_SHIFT

#define DIFF_P_INT_STATUS_1_T_TGT_SHIFT   ((uint8_t) 5)

Definition at line 226 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDO_MASK

#define DIFF_P_INT_STATUS_1_TDO_MASK   ((uint8_t) 0x80)

Definition at line 231 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDO_NO_OVERFLOW

#define DIFF_P_INT_STATUS_1_TDO_NO_OVERFLOW   ((uint8_t) 0x00) /* No overflow occurred. */

Definition at line 247 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDO_OVERFLOW

#define DIFF_P_INT_STATUS_1_TDO_OVERFLOW   ((uint8_t) 0x80) /* Overflow occurred. */

Definition at line 246 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDO_SHIFT

#define DIFF_P_INT_STATUS_1_TDO_SHIFT   ((uint8_t) 7)

Definition at line 232 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDU_MASK

#define DIFF_P_INT_STATUS_1_TDU_MASK   ((uint8_t) 0x40)

Definition at line 228 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDU_NO_UNDERFLOW

#define DIFF_P_INT_STATUS_1_TDU_NO_UNDERFLOW   ((uint8_t) 0x00) /* No Underflow occurred. */

Definition at line 245 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDU_SHIFT

#define DIFF_P_INT_STATUS_1_TDU_SHIFT   ((uint8_t) 6)

Definition at line 229 of file diff_p.h.

DIFF_P_INT_STATUS_1_TDU_UNDERFLOW

#define DIFF_P_INT_STATUS_1_TDU_UNDERFLOW   ((uint8_t) 0x40) /* Underflow occurred. */

Definition at line 244 of file diff_p.h.

DIFF_P_NPS3000VV_WHOAMI_VALUE

#define DIFF_P_NPS3000VV_WHOAMI_VALUE   (0xD0) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */

Definition at line 96 of file diff_p.h.

Referenced by main().

DIFF_P_NPS3001DV_WHOAMI_VALUE

#define DIFF_P_NPS3001DV_WHOAMI_VALUE   (0xD1) /* DIFF_P Who_Am_I Value of Part Number NPS3001DV. */

Definition at line 97 of file diff_p.h.

Referenced by main().

DIFF_P_NPS3002VV_WHOAMI_VALUE

#define DIFF_P_NPS3002VV_WHOAMI_VALUE   (0xD2) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */

Definition at line 98 of file diff_p.h.

Referenced by main().

DIFF_P_NPS3005DV_WHOAMI_VALUE

#define DIFF_P_NPS3005DV_WHOAMI_VALUE   (0xD3) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */

Definition at line 99 of file diff_p.h.

Referenced by main().

DIFF_P_STATUS_ACTIVE_MODE_ACTIVE

#define DIFF_P_STATUS_ACTIVE_MODE_ACTIVE   ((uint8_t) 0x80) /* Sensor is in active mode. */

Definition at line 548 of file diff_p.h.

DIFF_P_STATUS_ACTIVE_MODE_MASK

#define DIFF_P_STATUS_ACTIVE_MODE_MASK   ((uint8_t) 0x80)

Definition at line 527 of file diff_p.h.

DIFF_P_STATUS_ACTIVE_MODE_SHIFT

#define DIFF_P_STATUS_ACTIVE_MODE_SHIFT   ((uint8_t) 7)

Definition at line 528 of file diff_p.h.

DIFF_P_STATUS_ACTIVE_MODE_STANDBY

#define DIFF_P_STATUS_ACTIVE_MODE_STANDBY   ((uint8_t) 0x00) /* Sensor is in standby mode. */

Definition at line 549 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_CNT_CAN_RPG

#define DIFF_P_STATUS_I2C_RPG_CNT_CAN_RPG   ((uint8_t) 0x00) /* I2C address can be reprogrammed. */

Definition at line 547 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_CNT_CANT_RPG

#define DIFF_P_STATUS_I2C_RPG_CNT_CANT_RPG   ((uint8_t) 0x40) /* I2C address cannot be reprogrammed. */

Definition at line 546 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_CNT_MASK

#define DIFF_P_STATUS_I2C_RPG_CNT_MASK   ((uint8_t) 0x40)

Definition at line 524 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_CNT_SHIFT

#define DIFF_P_STATUS_I2C_RPG_CNT_SHIFT   ((uint8_t) 6)

Definition at line 525 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_MASK

#define DIFF_P_STATUS_I2C_RPG_MASK   ((uint8_t) 0x20)

Definition at line 521 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_NO_RPG

#define DIFF_P_STATUS_I2C_RPG_NO_RPG   ((uint8_t) 0x00) /* No Reprograming has taken place. */

Definition at line 545 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_RPG_SUCCESS

#define DIFF_P_STATUS_I2C_RPG_RPG_SUCCESS   ((uint8_t) 0x20) /* I2C Reprograming successful. */

Definition at line 544 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_SHIFT

#define DIFF_P_STATUS_I2C_RPG_SHIFT   ((uint8_t) 5)

Definition at line 522 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_STATUS_MASK

#define DIFF_P_STATUS_I2C_RPG_STATUS_MASK   ((uint8_t) 0x10)

Definition at line 518 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_STATUS_RPG_CPLT

#define DIFF_P_STATUS_I2C_RPG_STATUS_RPG_CPLT   ((uint8_t) 0x00) /* Reprograming cycle completed. */

Definition at line 543 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_STATUS_RPG_INIT

#define DIFF_P_STATUS_I2C_RPG_STATUS_RPG_INIT   ((uint8_t) 0x10) /* Reprograming cycle initiated. */

Definition at line 542 of file diff_p.h.

DIFF_P_STATUS_I2C_RPG_STATUS_SHIFT

#define DIFF_P_STATUS_I2C_RPG_STATUS_SHIFT   ((uint8_t) 4)

Definition at line 519 of file diff_p.h.

DIFF_P_STATUS_OSR_ERR_ERR

#define DIFF_P_STATUS_OSR_ERR_ERR   ((uint8_t) 0x02) /* Illegal ODR/OSR combination. */

Definition at line 536 of file diff_p.h.

DIFF_P_STATUS_OSR_ERR_MASK

#define DIFF_P_STATUS_OSR_ERR_MASK   ((uint8_t) 0x02)

Definition at line 509 of file diff_p.h.

DIFF_P_STATUS_OSR_ERR_NO_ERR

#define DIFF_P_STATUS_OSR_ERR_NO_ERR   ((uint8_t) 0x00) /* No Error. */

Definition at line 537 of file diff_p.h.

DIFF_P_STATUS_OSR_ERR_SHIFT

#define DIFF_P_STATUS_OSR_ERR_SHIFT   ((uint8_t) 1)

Definition at line 510 of file diff_p.h.

DIFF_P_STATUS_RST_STATUS_MASK

#define DIFF_P_STATUS_RST_STATUS_MASK   ((uint8_t) 0x01)

Definition at line 506 of file diff_p.h.

DIFF_P_STATUS_RST_STATUS_NO_RST

#define DIFF_P_STATUS_RST_STATUS_NO_RST   ((uint8_t) 0x00) /* No POR, brownout or soft reset has occurred. */

Definition at line 535 of file diff_p.h.

DIFF_P_STATUS_RST_STATUS_RST

#define DIFF_P_STATUS_RST_STATUS_RST   ((uint8_t) 0x01) /* Part has come out of POR, brownout or soft reset. */

Definition at line 534 of file diff_p.h.

DIFF_P_STATUS_RST_STATUS_SHIFT

#define DIFF_P_STATUS_RST_STATUS_SHIFT   ((uint8_t) 0)

Definition at line 507 of file diff_p.h.

DIFF_P_STATUS_STAT_CPLT_MASK

#define DIFF_P_STATUS_STAT_CPLT_MASK   ((uint8_t) 0x04)

Definition at line 512 of file diff_p.h.

DIFF_P_STATUS_STAT_CPLT_NO_SUCCESS

#define DIFF_P_STATUS_STAT_CPLT_NO_SUCCESS   ((uint8_t) 0x00) /* Calibration routine was not successful. */

Definition at line 539 of file diff_p.h.

DIFF_P_STATUS_STAT_CPLT_SHIFT

#define DIFF_P_STATUS_STAT_CPLT_SHIFT   ((uint8_t) 2)

Definition at line 513 of file diff_p.h.

DIFF_P_STATUS_STAT_CPLT_SUCCESS

#define DIFF_P_STATUS_STAT_CPLT_SUCCESS   ((uint8_t) 0x04) /* Calibration routine was successful. */

Definition at line 538 of file diff_p.h.

DIFF_P_STATUS_STAT_EP_DETECTED

#define DIFF_P_STATUS_STAT_EP_DETECTED   ((uint8_t) 0x08) /* Existing pressure has been detected. */

Definition at line 540 of file diff_p.h.

DIFF_P_STATUS_STAT_EP_MASK

#define DIFF_P_STATUS_STAT_EP_MASK   ((uint8_t) 0x08)

Definition at line 515 of file diff_p.h.

Referenced by DIFF_P_I2C_Initialize(), and DIFF_P_SPI_Initialize().

DIFF_P_STATUS_STAT_EP_NOTDETECTED

#define DIFF_P_STATUS_STAT_EP_NOTDETECTED   ((uint8_t) 0x00) /* No existing pressure detected. */

Definition at line 541 of file diff_p.h.

DIFF_P_STATUS_STAT_EP_SHIFT

#define DIFF_P_STATUS_STAT_EP_SHIFT   ((uint8_t) 3)

Definition at line 516 of file diff_p.h.

Typedef Documentation

DIFF_P_I2C_ADDRESS_t

typedef uint8_t DIFF_P_I2C_ADDRESS_t

Definition at line 1022 of file diff_p.h.

DIFF_P_OFF_CAL_P_LSB_t

typedef uint8_t DIFF_P_OFF_CAL_P_LSB_t

Definition at line 588 of file diff_p.h.

DIFF_P_OFF_CAL_P_MSB_t

typedef uint8_t DIFF_P_OFF_CAL_P_MSB_t

Definition at line 597 of file diff_p.h.

DIFF_P_OFF_MOP_LSB_t

typedef uint8_t DIFF_P_OFF_MOP_LSB_t

Definition at line 1041 of file diff_p.h.

DIFF_P_OFF_MOP_MSB_t

typedef uint8_t DIFF_P_OFF_MOP_MSB_t

Definition at line 1050 of file diff_p.h.

DIFF_P_OFF_P_LSB_t

typedef uint8_t DIFF_P_OFF_P_LSB_t

Definition at line 570 of file diff_p.h.

DIFF_P_OFF_P_MSB_t

typedef uint8_t DIFF_P_OFF_P_MSB_t

Definition at line 579 of file diff_p.h.

DIFF_P_OFF_T_t

typedef uint8_t DIFF_P_OFF_T_t

Definition at line 606 of file diff_p.h.

DIFF_P_OUT_P_LSB_t

typedef uint8_t DIFF_P_OUT_P_LSB_t

Definition at line 258 of file diff_p.h.

DIFF_P_OUT_P_MSB_t

typedef uint8_t DIFF_P_OUT_P_MSB_t

Definition at line 267 of file diff_p.h.

DIFF_P_OUT_T_t

typedef uint8_t DIFF_P_OUT_T_t

Definition at line 276 of file diff_p.h.

DIFF_P_P_MAX_LSB_t

typedef uint8_t DIFF_P_P_MAX_LSB_t

Definition at line 314 of file diff_p.h.

DIFF_P_P_MAX_MSB_t

typedef uint8_t DIFF_P_P_MAX_MSB_t

Definition at line 323 of file diff_p.h.

DIFF_P_P_MIN_LSB_t

typedef uint8_t DIFF_P_P_MIN_LSB_t

Definition at line 286 of file diff_p.h.

DIFF_P_P_MIN_MSB_t

typedef uint8_t DIFF_P_P_MIN_MSB_t

Definition at line 295 of file diff_p.h.

DIFF_P_P_TGT0_LSB_t

typedef uint8_t DIFF_P_P_TGT0_LSB_t

Definition at line 616 of file diff_p.h.

DIFF_P_P_TGT0_MSB_t

typedef uint8_t DIFF_P_P_TGT0_MSB_t

Definition at line 625 of file diff_p.h.

DIFF_P_P_TGT1_LSB_t

typedef uint8_t DIFF_P_P_TGT1_LSB_t

Definition at line 634 of file diff_p.h.

DIFF_P_P_TGT1_MSB_t

typedef uint8_t DIFF_P_P_TGT1_MSB_t

Definition at line 643 of file diff_p.h.

DIFF_P_P_TGT2_LSB_t

typedef uint8_t DIFF_P_P_TGT2_LSB_t

Definition at line 652 of file diff_p.h.

DIFF_P_P_TGT2_MSB_t

typedef uint8_t DIFF_P_P_TGT2_MSB_t

Definition at line 661 of file diff_p.h.

DIFF_P_PROD_REV_t

typedef uint8_t DIFF_P_PROD_REV_t

Definition at line 1031 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE0_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE0_t

Definition at line 1123 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE1_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE1_t

Definition at line 1114 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE2_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE2_t

Definition at line 1105 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE3_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE3_t

Definition at line 1096 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE4_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE4_t

Definition at line 1087 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE5_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE5_t

Definition at line 1078 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE6_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE6_t

Definition at line 1069 of file diff_p.h.

DIFF_P_SERIALNUMBER_BYTE7_t

typedef uint8_t DIFF_P_SERIALNUMBER_BYTE7_t

Definition at line 1060 of file diff_p.h.

DIFF_P_T_MAX_t

typedef uint8_t DIFF_P_T_MAX_t

Definition at line 332 of file diff_p.h.

DIFF_P_T_MIN_t

typedef uint8_t DIFF_P_T_MIN_t

Definition at line 304 of file diff_p.h.

DIFF_P_T_TGT_t

typedef uint8_t DIFF_P_T_TGT_t

Definition at line 670 of file diff_p.h.

DIFF_P_WHO_AM_I_t

typedef uint8_t DIFF_P_WHO_AM_I_t

Definition at line 560 of file diff_p.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

DIFF_P Sensor Internal Registers

Enumerator
DIFF_P_INT_STATUS_0
DIFF_P_INT_STATUS_1
DIFF_P_OUT_P_LSB
DIFF_P_OUT_P_MSB
DIFF_P_OUT_T
DIFF_P_P_MIN_LSB
DIFF_P_P_MIN_MSB
DIFF_P_T_MIN
DIFF_P_P_MAX_LSB
DIFF_P_P_MAX_MSB
DIFF_P_T_MAX
DIFF_P_INT_MASK0
DIFF_P_INT_MASK1
DIFF_P_STATUS
DIFF_P_WHO_AM_I
DIFF_P_OFF_P_LSB
DIFF_P_OFF_P_MSB
DIFF_P_OFF_CAL_P_LSB
DIFF_P_OFF_CAL_P_MSB
DIFF_P_OFF_T
DIFF_P_P_TGT0_LSB
DIFF_P_P_TGT0_MSB
DIFF_P_P_TGT1_LSB
DIFF_P_P_TGT1_MSB
DIFF_P_P_TGT2_LSB
DIFF_P_P_TGT2_MSB
DIFF_P_T_TGT
DIFF_P_CTRL_REG1
DIFF_P_CTRL_REG2
DIFF_P_CTRL_REG3
DIFF_P_INT_ROUTE0
DIFF_P_INT_ROUTE1
DIFF_P_I2C_ADDRESS
DIFF_P_WHO_AM_I_
DIFF_P_PROD_REV
DIFF_P_OFF_MOP_LSB
DIFF_P_OFF_MOP_MSB
DIFF_P_SERIALNUMBER_BYTE7
DIFF_P_SERIALNUMBER_BYTE6
DIFF_P_SERIALNUMBER_BYTE5
DIFF_P_SERIALNUMBER_BYTE4
DIFF_P_SERIALNUMBER_BYTE3
DIFF_P_SERIALNUMBER_BYTE2
DIFF_P_SERIALNUMBER_BYTE1
DIFF_P_SERIALNUMBER_BYTE0

Definition at line 45 of file diff_p.h.