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ISSDK
1.7
IoT Sensing Software Development Kit
|
The mma845x.h contains the MMA845x sensor register definitions and its bit mask. More...
Go to the source code of this file.
Macros | |
#define | MMA845x_I2C_ADDRESS_SA0_0 0x1C /*MMA845x Address - SA0=0*/ |
#define | MMA845x_I2C_ADDRESS_SA0_1 0x1D /*MMA845x Address - SA0=1*/ |
#define | MMA845x_STATUS_XDR_MASK ((uint8_t) 0x01) |
#define | MMA845x_STATUS_XDR_SHIFT ((uint8_t) 0) |
#define | MMA845x_STATUS_YDR_MASK ((uint8_t) 0x02) |
#define | MMA845x_STATUS_YDR_SHIFT ((uint8_t) 1) |
#define | MMA845x_STATUS_ZDR_MASK ((uint8_t) 0x04) |
#define | MMA845x_STATUS_ZDR_SHIFT ((uint8_t) 2) |
#define | MMA845x_STATUS_ZYXDR_MASK ((uint8_t) 0x08) |
#define | MMA845x_STATUS_ZYXDR_SHIFT ((uint8_t) 3) |
#define | MMA845x_STATUS_XOW_MASK ((uint8_t) 0x10) |
#define | MMA845x_STATUS_XOW_SHIFT ((uint8_t) 4) |
#define | MMA845x_STATUS_YOW_MASK ((uint8_t) 0x20) |
#define | MMA845x_STATUS_YOW_SHIFT ((uint8_t) 5) |
#define | MMA845x_STATUS_ZOW_MASK ((uint8_t) 0x40) |
#define | MMA845x_STATUS_ZOW_SHIFT ((uint8_t) 6) |
#define | MMA845x_STATUS_ZYXOW_MASK ((uint8_t) 0x80) |
#define | MMA845x_STATUS_ZYXOW_SHIFT ((uint8_t) 7) |
#define | MMA845x_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */ |
#define | MMA845x_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */ |
#define | MMA845x_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */ |
#define | MMA845x_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */ |
#define | MMA845x_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */ |
#define | MMA845x_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */ |
#define | MMA845x_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */ |
#define | MMA845x_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, Y, */ |
#define | MMA845x_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F) |
#define | MMA845x_F_STATUS_F_CNT_SHIFT ((uint8_t) 0) |
#define | MMA845x_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40) |
#define | MMA845x_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6) |
#define | MMA845x_F_STATUS_F_OVF_MASK ((uint8_t) 0x80) |
#define | MMA845x_F_STATUS_F_OVF_SHIFT ((uint8_t) 7) |
#define | MMA845x_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */ |
#define | MMA845x_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count is */ |
#define | MMA845x_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */ |
#define | MMA845x_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */ |
#define | MMA845x_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F) |
#define | MMA845x_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0) |
#define | MMA845x_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0) |
#define | MMA845x_F_SETUP_F_MODE_SHIFT ((uint8_t) 6) |
#define | MMA845x_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */ |
#define | MMA845x_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when overflowed */ |
#define | MMA845x_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */ |
#define | MMA845x_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the number */ |
#define | MMA845x_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04) |
#define | MMA845x_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2) |
#define | MMA845x_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08) |
#define | MMA845x_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3) |
#define | MMA845x_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10) |
#define | MMA845x_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4) |
#define | MMA845x_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20) |
#define | MMA845x_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5) |
#define | MMA845x_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */ |
#define | MMA845x_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */ |
#define | MMA845x_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */ |
#define | MMA845x_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */ |
#define | MMA845x_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger bit */ |
#define | MMA845x_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger bit */ |
#define | MMA845x_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */ |
#define | MMA845x_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */ |
#define | MMA845x_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03) |
#define | MMA845x_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0) |
#define | MMA845x_SYSMOD_FGT_MASK ((uint8_t) 0x7C) |
#define | MMA845x_SYSMOD_FGT_SHIFT ((uint8_t) 2) |
#define | MMA845x_SYSMOD_FGERR_MASK ((uint8_t) 0x80) |
#define | MMA845x_SYSMOD_FGERR_SHIFT ((uint8_t) 7) |
#define | MMA845x_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */ |
#define | MMA845x_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */ |
#define | MMA845x_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */ |
#define | MMA845x_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */ |
#define | MMA845x_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */ |
#define | MMA845x_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01) |
#define | MMA845x_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0) |
#define | MMA845x_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04) |
#define | MMA845x_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2) |
#define | MMA845x_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08) |
#define | MMA845x_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3) |
#define | MMA845x_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10) |
#define | MMA845x_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4) |
#define | MMA845x_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20) |
#define | MMA845x_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5) |
#define | MMA845x_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40) |
#define | MMA845x_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6) |
#define | MMA845x_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80) |
#define | MMA845x_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7) |
#define | MMA845x_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF) |
#define | MMA845x_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0) |
#define | MMA8451_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x1a) /* Device identifier for MMA8451 */ |
#define | MMA8452_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x2a) /* Device identifier for MMA8452 */ |
#define | MMA8453_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x3a) /* Device identifier for MMA8452 */ |
#define | MMA845x_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03) |
#define | MMA845x_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0) |
#define | MMA845x_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10) |
#define | MMA845x_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4) |
#define | MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */ |
#define | MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */ |
#define | MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */ |
#define | MMA845x_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */ |
#define | MMA845x_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */ |
#define | MMA845x_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03) |
#define | MMA845x_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0) |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10) |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4) |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20) |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5) |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */ |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */ |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */ |
#define | MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */ |
#define | MMA845x_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01) |
#define | MMA845x_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0) |
#define | MMA845x_PL_STATUS_LAPO_MASK ((uint8_t) 0x06) |
#define | MMA845x_PL_STATUS_LAPO_SHIFT ((uint8_t) 1) |
#define | MMA845x_PL_STATUS_LO_MASK ((uint8_t) 0x40) |
#define | MMA845x_PL_STATUS_LO_SHIFT ((uint8_t) 6) |
#define | MMA845x_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80) |
#define | MMA845x_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7) |
#define | MMA845x_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */ |
#define | MMA845x_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing orientation. */ |
#define | MMA845x_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */ |
#define | MMA845x_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in the */ |
#define | MMA845x_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode to */ |
#define | MMA845x_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */ |
#define | MMA845x_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */ |
#define | MMA845x_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */ |
#define | MMA845x_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */ |
#define | MMA845x_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */ |
#define | MMA845x_PL_CFG_RESERVED_MASK ((uint8_t) 0x3F) |
#define | MMA845x_PL_CFG_RESERVED_SHIFT ((uint8_t) 0) |
#define | MMA845x_PL_CFG_PL_EN_MASK ((uint8_t) 0x40) |
#define | MMA845x_PL_CFG_PL_EN_SHIFT ((uint8_t) 6) |
#define | MMA845x_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80) |
#define | MMA845x_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7) |
#define | MMA845x_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */ |
#define | MMA845x_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */ |
#define | MMA845x_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */ |
#define | MMA845x_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */ |
#define | MMA845x_PL_COUNT_DBCNE_MASK ((uint8_t) 0xFF) |
#define | MMA845x_PL_COUNT_DBCNE_SHIFT ((uint8_t) 0) |
#define | MMA845x_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07) |
#define | MMA845x_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0) |
#define | MMA845x_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0) |
#define | MMA845x_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6) |
#define | MMA845x_PL_BF_ZCOMP_ZLOCK_THR ((uint8_t) 0x64) /* Z-Lock angle compensation is set to 29°. */ |
#define | MMA845x_PL_BF_ZCOMP_BKFR_THR ((uint8_t) 0x40) /* Back to Front trip angle is set to ±75°. */ |
#define | MMA845x_PL_THS_REG_HYS_MASK ((uint8_t) 0x07) |
#define | MMA845x_PL_THS_REG_HYS_SHIFT ((uint8_t) 0) |
#define | MMA845x_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8) |
#define | MMA845x_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3) |
#define | MMA845x_PL_THS_REG_HYS_THR ((uint8_t) 0x64) /* Hysteresis angle is fixed at ±14°, which is 100. */ |
#define | MMA845x_PL_THS_REG_PL_THS_THR ((uint8_t) 0x80) /* Portrait/Landscape Fixed Threshold angle = 1_0000 */ |
#define | MMA845x_FF_MT_CFG_RESERVED_MASK ((uint8_t) 0x07) |
#define | MMA845x_FF_MT_CFG_RESERVED_SHIFT ((uint8_t) 0) |
#define | MMA845x_FF_MT_CFG_XEFE_MASK ((uint8_t) 0x08) |
#define | MMA845x_FF_MT_CFG_XEFE_SHIFT ((uint8_t) 3) |
#define | MMA845x_FF_MT_CFG_YEFE_MASK ((uint8_t) 0x10) |
#define | MMA845x_FF_MT_CFG_YEFE_SHIFT ((uint8_t) 4) |
#define | MMA845x_FF_MT_CFG_ZEFE_MASK ((uint8_t) 0x20) |
#define | MMA845x_FF_MT_CFG_ZEFE_SHIFT ((uint8_t) 5) |
#define | MMA845x_FF_MT_CFG_OAE_MASK ((uint8_t) 0x40) |
#define | MMA845x_FF_MT_CFG_OAE_SHIFT ((uint8_t) 6) |
#define | MMA845x_FF_MT_CFG_ELE_MASK ((uint8_t) 0x80) |
#define | MMA845x_FF_MT_CFG_ELE_SHIFT ((uint8_t) 7) |
#define | MMA845x_FF_MT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_FF_MT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */ |
#define | MMA845x_FF_MT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_FF_MT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */ |
#define | MMA845x_FF_MT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_FF_MT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */ |
#define | MMA845x_FF_MT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */ |
#define | MMA845x_FF_MT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */ |
#define | MMA845x_FF_MT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define | MMA845x_FF_MT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */ |
#define | MMA845x_FF_MT_SRC_XHP_MASK ((uint8_t) 0x01) |
#define | MMA845x_FF_MT_SRC_XHP_SHIFT ((uint8_t) 0) |
#define | MMA845x_FF_MT_SRC_XHE_MASK ((uint8_t) 0x02) |
#define | MMA845x_FF_MT_SRC_XHE_SHIFT ((uint8_t) 1) |
#define | MMA845x_FF_MT_SRC_YHP_MASK ((uint8_t) 0x04) |
#define | MMA845x_FF_MT_SRC_YHP_SHIFT ((uint8_t) 2) |
#define | MMA845x_FF_MT_SRC_YHE_MASK ((uint8_t) 0x08) |
#define | MMA845x_FF_MT_SRC_YHE_SHIFT ((uint8_t) 3) |
#define | MMA845x_FF_MT_SRC_ZHP_MASK ((uint8_t) 0x10) |
#define | MMA845x_FF_MT_SRC_ZHP_SHIFT ((uint8_t) 4) |
#define | MMA845x_FF_MT_SRC_ZHE_MASK ((uint8_t) 0x20) |
#define | MMA845x_FF_MT_SRC_ZHE_SHIFT ((uint8_t) 5) |
#define | MMA845x_FF_MT_SRC_EA_MASK ((uint8_t) 0x80) |
#define | MMA845x_FF_MT_SRC_EA_SHIFT ((uint8_t) 7) |
#define | MMA845x_FF_MT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */ |
#define | MMA845x_FF_MT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */ |
#define | MMA845x_FF_MT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */ |
#define | MMA845x_FF_MT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */ |
#define | MMA845x_FF_MT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */ |
#define | MMA845x_FF_MT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */ |
#define | MMA845x_FF_MT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */ |
#define | MMA845x_FF_MT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */ |
#define | MMA845x_FF_MT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */ |
#define | MMA845x_FF_MT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */ |
#define | MMA845x_FF_MT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */ |
#define | MMA845x_FF_MT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */ |
#define | MMA845x_FF_MT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */ |
#define | MMA845x_FF_MT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */ |
#define | MMA845x_FF_MT_THS_THS_MASK ((uint8_t) 0x7F) |
#define | MMA845x_FF_MT_THS_THS_SHIFT ((uint8_t) 0) |
#define | MMA845x_FF_MT_THS_DBCNTM_MASK ((uint8_t) 0x80) |
#define | MMA845x_FF_MT_THS_DBCNTM_SHIFT ((uint8_t) 7) |
#define | MMA845x_FF_MT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */ |
#define | MMA845x_FF_MT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */ |
#define | MMA845x_FF_MT_COUNT_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_FF_MT_COUNT_D_SHIFT ((uint8_t) 0) |
#define | MMA845x_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01) |
#define | MMA845x_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0) |
#define | MMA845x_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02) |
#define | MMA845x_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1) |
#define | MMA845x_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04) |
#define | MMA845x_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2) |
#define | MMA845x_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08) |
#define | MMA845x_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3) |
#define | MMA845x_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10) |
#define | MMA845x_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4) |
#define | MMA845x_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0) |
#define | MMA845x_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5) |
#define | MMA845x_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection block */ |
#define | MMA845x_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection block */ |
#define | MMA845x_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration delta */ |
#define | MMA845x_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration delta */ |
#define | MMA845x_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration delta */ |
#define | MMA845x_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define | MMA845x_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */ |
#define | MMA845x_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01) |
#define | MMA845x_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0) |
#define | MMA845x_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02) |
#define | MMA845x_TRANSIENT_SRC_XTRANS_SHIFT ((uint8_t) 1) |
#define | MMA845x_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04) |
#define | MMA845x_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2) |
#define | MMA845x_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08) |
#define | MMA845x_TRANSIENT_SRC_YTRANS_SHIFT ((uint8_t) 3) |
#define | MMA845x_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10) |
#define | MMA845x_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4) |
#define | MMA845x_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20) |
#define | MMA845x_TRANSIENT_SRC_ZTRANS_SHIFT ((uint8_t) 5) |
#define | MMA845x_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40) |
#define | MMA845x_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6) |
#define | MMA845x_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */ |
#define | MMA845x_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */ |
#define | MMA845x_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define | MMA845x_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the value */ |
#define | MMA845x_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */ |
#define | MMA845x_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */ |
#define | MMA845x_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define | MMA845x_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the value */ |
#define | MMA845x_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */ |
#define | MMA845x_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */ |
#define | MMA845x_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define | MMA845x_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the value */ |
#define | MMA845x_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */ |
#define | MMA845x_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */ |
#define | MMA845x_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F) |
#define | MMA845x_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0) |
#define | MMA845x_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80) |
#define | MMA845x_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7) |
#define | MMA845x_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */ |
#define | MMA845x_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */ |
#define | MMA845x_TRANSIENT_COUNT_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_TRANSIENT_COUNT_D_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01) |
#define | MMA845x_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02) |
#define | MMA845x_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1) |
#define | MMA845x_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04) |
#define | MMA845x_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2) |
#define | MMA845x_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08) |
#define | MMA845x_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3) |
#define | MMA845x_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10) |
#define | MMA845x_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4) |
#define | MMA845x_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20) |
#define | MMA845x_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5) |
#define | MMA845x_PULSE_CFG_ELE_MASK ((uint8_t) 0x40) |
#define | MMA845x_PULSE_CFG_ELE_SHIFT ((uint8_t) 6) |
#define | MMA845x_PULSE_CFG_DPA_MASK ((uint8_t) 0x80) |
#define | MMA845x_PULSE_CFG_DPA_SHIFT ((uint8_t) 7) |
#define | MMA845x_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define | MMA845x_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */ |
#define | MMA845x_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define | MMA845x_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */ |
#define | MMA845x_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the start */ |
#define | MMA845x_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */ |
#define | MMA845x_PULSE_SRC_POLX_MASK ((uint8_t) 0x01) |
#define | MMA845x_PULSE_SRC_POLX_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_SRC_POLY_MASK ((uint8_t) 0x02) |
#define | MMA845x_PULSE_SRC_POLY_SHIFT ((uint8_t) 1) |
#define | MMA845x_PULSE_SRC_POLZ_MASK ((uint8_t) 0x04) |
#define | MMA845x_PULSE_SRC_POLZ_SHIFT ((uint8_t) 2) |
#define | MMA845x_PULSE_SRC_DPE_MASK ((uint8_t) 0x08) |
#define | MMA845x_PULSE_SRC_DPE_SHIFT ((uint8_t) 3) |
#define | MMA845x_PULSE_SRC_AXX_MASK ((uint8_t) 0x10) |
#define | MMA845x_PULSE_SRC_AXX_SHIFT ((uint8_t) 4) |
#define | MMA845x_PULSE_SRC_AXY_MASK ((uint8_t) 0x20) |
#define | MMA845x_PULSE_SRC_AXY_SHIFT ((uint8_t) 5) |
#define | MMA845x_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40) |
#define | MMA845x_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6) |
#define | MMA845x_PULSE_SRC_EA_MASK ((uint8_t) 0x80) |
#define | MMA845x_PULSE_SRC_EA_SHIFT ((uint8_t) 7) |
#define | MMA845x_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define | MMA845x_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was negative. */ |
#define | MMA845x_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define | MMA845x_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was negative. */ |
#define | MMA845x_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define | MMA845x_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was negative. */ |
#define | MMA845x_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */ |
#define | MMA845x_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */ |
#define | MMA845x_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define | MMA845x_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */ |
#define | MMA845x_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define | MMA845x_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */ |
#define | MMA845x_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define | MMA845x_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */ |
#define | MMA845x_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */ |
#define | MMA845x_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */ |
#define | MMA845x_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F) |
#define | MMA845x_PULSE_THSX_THSX_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80) |
#define | MMA845x_PULSE_THSX_RESERVED_SHIFT ((uint8_t) 7) |
#define | MMA845x_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F) |
#define | MMA845x_PULSE_THSY_THSY_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80) |
#define | MMA845x_PULSE_THSY_RESERVED_SHIFT ((uint8_t) 7) |
#define | MMA845x_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F) |
#define | MMA845x_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80) |
#define | MMA845x_PULSE_THSZ_RESERVED_SHIFT ((uint8_t) 7) |
#define | MMA845x_PULSE_TMLT_TMLT_MASK ((uint8_t) 0xFF) |
#define | MMA845x_PULSE_TMLT_TMLT_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_LTCY_LTCY_MASK ((uint8_t) 0xFF) |
#define | MMA845x_PULSE_LTCY_LTCY_SHIFT ((uint8_t) 0) |
#define | MMA845x_PULSE_WIND_WIND_MASK ((uint8_t) 0xFF) |
#define | MMA845x_PULSE_WIND_WIND_SHIFT ((uint8_t) 0) |
#define | MMA845x_ASLP_COUNT_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_ASLP_COUNT_D_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG1_MODE_MASK ((uint8_t) 0x01) |
#define | MMA845x_CTRL_REG1_MODE_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02) |
#define | MMA845x_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1) |
#define | MMA845x_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04) |
#define | MMA845x_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2) |
#define | MMA845x_CTRL_REG1_DR_MASK ((uint8_t) 0x38) |
#define | MMA845x_CTRL_REG1_DR_SHIFT ((uint8_t) 3) |
#define | MMA845x_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0) |
#define | MMA845x_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6) |
#define | MMA845x_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */ |
#define | MMA845x_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */ |
#define | MMA845x_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */ |
#define | MMA845x_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */ |
#define | MMA845x_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */ |
#define | MMA845x_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */ |
#define | MMA845x_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */ |
#define | MMA845x_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */ |
#define | MMA845x_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */ |
#define | MMA845x_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */ |
#define | MMA845x_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */ |
#define | MMA845x_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */ |
#define | MMA845x_CTRL_REG2_MODS_MASK ((uint8_t) 0x03) |
#define | MMA845x_CTRL_REG2_MODS_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04) |
#define | MMA845x_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2) |
#define | MMA845x_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18) |
#define | MMA845x_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3) |
#define | MMA845x_CTRL_REG2_RST_MASK ((uint8_t) 0x40) |
#define | MMA845x_CTRL_REG2_RST_SHIFT ((uint8_t) 6) |
#define | MMA845x_CTRL_REG2_ST_MASK ((uint8_t) 0x80) |
#define | MMA845x_CTRL_REG2_ST_SHIFT ((uint8_t) 7) |
#define | MMA845x_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */ |
#define | MMA845x_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */ |
#define | MMA845x_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */ |
#define | MMA845x_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */ |
#define | MMA845x_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */ |
#define | MMA845x_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */ |
#define | MMA845x_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */ |
#define | MMA845x_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */ |
#define | MMA845x_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */ |
#define | MMA845x_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */ |
#define | MMA845x_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */ |
#define | MMA845x_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */ |
#define | MMA845x_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */ |
#define | MMA845x_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */ |
#define | MMA845x_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01) |
#define | MMA845x_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02) |
#define | MMA845x_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1) |
#define | MMA845x_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08) |
#define | MMA845x_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3) |
#define | MMA845x_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10) |
#define | MMA845x_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4) |
#define | MMA845x_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20) |
#define | MMA845x_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5) |
#define | MMA845x_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40) |
#define | MMA845x_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6) |
#define | MMA845x_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80) |
#define | MMA845x_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7) |
#define | MMA845x_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */ |
#define | MMA845x_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */ |
#define | MMA845x_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */ |
#define | MMA845x_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */ |
#define | MMA845x_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP mode. */ |
#define | MMA845x_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */ |
#define | MMA845x_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */ |
#define | MMA845x_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */ |
#define | MMA845x_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */ |
#define | MMA845x_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */ |
#define | MMA845x_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */ |
#define | MMA845x_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */ |
#define | MMA845x_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */ |
#define | MMA845x_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when transitioning */ |
#define | MMA845x_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01) |
#define | MMA845x_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04) |
#define | MMA845x_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2) |
#define | MMA845x_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08) |
#define | MMA845x_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3) |
#define | MMA845x_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10) |
#define | MMA845x_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4) |
#define | MMA845x_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20) |
#define | MMA845x_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5) |
#define | MMA845x_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40) |
#define | MMA845x_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6) |
#define | MMA845x_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80) |
#define | MMA845x_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7) |
#define | MMA845x_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */ |
#define | MMA845x_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */ |
#define | MMA845x_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01) |
#define | MMA845x_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0) |
#define | MMA845x_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04) |
#define | MMA845x_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2) |
#define | MMA845x_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08) |
#define | MMA845x_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3) |
#define | MMA845x_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10) |
#define | MMA845x_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4) |
#define | MMA845x_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20) |
#define | MMA845x_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5) |
#define | MMA845x_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40) |
#define | MMA845x_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6) |
#define | MMA845x_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80) |
#define | MMA845x_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7) |
#define | MMA845x_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define | MMA845x_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */ |
#define | MMA845x_OFF_X_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_OFF_X_D_SHIFT ((uint8_t) 0) |
#define | MMA845x_OFF_Y_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_OFF_Y_D_SHIFT ((uint8_t) 0) |
#define | MMA845x_OFF_Z_D_MASK ((uint8_t) 0xFF) |
#define | MMA845x_OFF_Z_D_SHIFT ((uint8_t) 0) |
Typedefs | |
typedef uint8_t | MMA845x_OUT_X_MSB_t |
typedef uint8_t | MMA845x_OUT_X_LSB_t |
typedef uint8_t | MMA845x_OUT_Y_MSB_t |
typedef uint8_t | MMA845x_OUT_Y_LSB_t |
typedef uint8_t | MMA845x_OUT_Z_MSB_t |
typedef uint8_t | MMA845x_OUT_Z_LSB_t |
The mma845x.h contains the MMA845x sensor register definitions and its bit mask.
Definition in file mma845x.h.
#define MMA8451_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x1a) /* Device identifier for MMA8451 */ |
#define MMA8452_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x2a) /* Device identifier for MMA8452 */ |
#define MMA8453_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x3a) /* Device identifier for MMA8452 */ |
#define MMA845x_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */ |
#define MMA845x_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */ |
#define MMA845x_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */ |
#define MMA845x_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */ |
#define MMA845x_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0) |
#define MMA845x_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */ |
#define MMA845x_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */ |
#define MMA845x_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */ |
#define MMA845x_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */ |
#define MMA845x_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */ |
#define MMA845x_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */ |
#define MMA845x_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */ |
Definition at line 1626 of file mma845x.h.
Referenced by MMA845x_I2C_Configure().
#define MMA845x_CTRL_REG1_MODE_MASK ((uint8_t) 0x01) |
Definition at line 1606 of file mma845x.h.
Referenced by MMA845x_I2C_Configure().
#define MMA845x_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */ |
Definition at line 1625 of file mma845x.h.
Referenced by MMA845x_I2C_Configure().
#define MMA845x_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */ |
#define MMA845x_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */ |
#define MMA845x_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */ |
#define MMA845x_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */ |
#define MMA845x_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */ |
#define MMA845x_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */ |
Definition at line 1704 of file mma845x.h.
Referenced by MMA845x_I2C_Deinit().
#define MMA845x_CTRL_REG2_RST_MASK ((uint8_t) 0x40) |
Definition at line 1683 of file mma845x.h.
Referenced by MMA845x_I2C_Deinit().
#define MMA845x_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */ |
#define MMA845x_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */ |
#define MMA845x_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */ |
#define MMA845x_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */ |
#define MMA845x_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */ |
#define MMA845x_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */ |
#define MMA845x_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */ |
#define MMA845x_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */ |
#define MMA845x_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */ |
#define MMA845x_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80) |
#define MMA845x_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when transitioning */ |
#define MMA845x_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */ |
#define MMA845x_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */ |
#define MMA845x_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */ |
#define MMA845x_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */ |
#define MMA845x_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP mode. */ |
#define MMA845x_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08) |
#define MMA845x_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */ |
#define MMA845x_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */ |
#define MMA845x_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20) |
#define MMA845x_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5) |
#define MMA845x_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */ |
#define MMA845x_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */ |
#define MMA845x_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10) |
#define MMA845x_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */ |
#define MMA845x_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */ |
#define MMA845x_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40) |
#define MMA845x_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */ |
#define MMA845x_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80) |
#define MMA845x_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7) |
#define MMA845x_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01) |
#define MMA845x_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0) |
#define MMA845x_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04) |
#define MMA845x_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2) |
#define MMA845x_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40) |
#define MMA845x_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6) |
#define MMA845x_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */ |
#define MMA845x_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10) |
#define MMA845x_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4) |
#define MMA845x_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08) |
#define MMA845x_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3) |
#define MMA845x_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */ |
#define MMA845x_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20) |
#define MMA845x_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5) |
#define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80) |
#define MMA845x_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7) |
#define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01) |
#define MMA845x_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0) |
#define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04) |
#define MMA845x_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2) |
#define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40) |
#define MMA845x_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6) |
#define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10) |
#define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4) |
#define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08) |
#define MMA845x_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3) |
#define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
#define MMA845x_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20) |
#define MMA845x_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5) |
#define MMA845x_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */ |
#define MMA845x_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when overflowed */ |
#define MMA845x_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */ |
#define MMA845x_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the number */ |
#define MMA845x_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */ |
#define MMA845x_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */ |
#define MMA845x_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count is */ |
#define MMA845x_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40) |
#define MMA845x_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */ |
#define MMA845x_FF_MT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define MMA845x_FF_MT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */ |
#define MMA845x_FF_MT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */ |
#define MMA845x_FF_MT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */ |
#define MMA845x_FF_MT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_FF_MT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */ |
#define MMA845x_FF_MT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_FF_MT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */ |
#define MMA845x_FF_MT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_FF_MT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */ |
#define MMA845x_FF_MT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */ |
#define MMA845x_FF_MT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */ |
#define MMA845x_FF_MT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */ |
#define MMA845x_FF_MT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */ |
#define MMA845x_FF_MT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */ |
#define MMA845x_FF_MT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */ |
#define MMA845x_FF_MT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */ |
#define MMA845x_FF_MT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */ |
#define MMA845x_FF_MT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */ |
#define MMA845x_FF_MT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */ |
#define MMA845x_FF_MT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */ |
#define MMA845x_FF_MT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */ |
#define MMA845x_FF_MT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */ |
#define MMA845x_FF_MT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */ |
#define MMA845x_FF_MT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */ |
#define MMA845x_FF_MT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */ |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */ |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */ |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20) |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5) |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */ |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */ |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10) |
#define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4) |
#define MMA845x_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03) |
#define MMA845x_I2C_ADDRESS_SA0_0 0x1C /*MMA845x Address - SA0=0*/ |
#define MMA845x_I2C_ADDRESS_SA0_1 0x1D /*MMA845x Address - SA0=1*/ |
#define MMA845x_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04) |
#define MMA845x_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10) |
#define MMA845x_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08) |
#define MMA845x_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20) |
#define MMA845x_PL_BF_ZCOMP_BKFR_THR ((uint8_t) 0x40) /* Back to Front trip angle is set to ±75°. */ |
#define MMA845x_PL_BF_ZCOMP_ZLOCK_THR ((uint8_t) 0x64) /* Z-Lock angle compensation is set to 29°. */ |
#define MMA845x_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */ |
#define MMA845x_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */ |
#define MMA845x_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */ |
#define MMA845x_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */ |
#define MMA845x_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing orientation. */ |
#define MMA845x_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */ |
#define MMA845x_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in the */ |
#define MMA845x_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */ |
#define MMA845x_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode to */ |
#define MMA845x_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */ |
#define MMA845x_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */ |
#define MMA845x_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */ |
#define MMA845x_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */ |
#define MMA845x_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */ |
#define MMA845x_PL_THS_REG_HYS_THR ((uint8_t) 0x64) /* Hysteresis angle is fixed at ±14°, which is 100. */ |
#define MMA845x_PL_THS_REG_PL_THS_THR ((uint8_t) 0x80) /* Portrait/Landscape Fixed Threshold angle = 1_0000 */ |
#define MMA845x_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the start */ |
#define MMA845x_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */ |
#define MMA845x_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define MMA845x_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */ |
#define MMA845x_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */ |
#define MMA845x_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */ |
#define MMA845x_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */ |
#define MMA845x_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */ |
#define MMA845x_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */ |
#define MMA845x_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */ |
#define MMA845x_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */ |
#define MMA845x_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define MMA845x_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */ |
#define MMA845x_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define MMA845x_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */ |
#define MMA845x_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */ |
#define MMA845x_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */ |
#define MMA845x_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */ |
#define MMA845x_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */ |
#define MMA845x_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */ |
#define MMA845x_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was negative. */ |
#define MMA845x_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define MMA845x_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was negative. */ |
#define MMA845x_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define MMA845x_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was negative. */ |
#define MMA845x_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */ |
#define MMA845x_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80) |
#define MMA845x_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80) |
#define MMA845x_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80) |
#define MMA845x_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */ |
#define MMA845x_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */ |
#define MMA845x_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */ |
#define MMA845x_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */ |
#define MMA845x_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */ |
#define MMA845x_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */ |
#define MMA845x_STATUS_ZYXDR_MASK ((uint8_t) 0x08) |
#define MMA845x_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */ |
#define MMA845x_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, Y, */ |
#define MMA845x_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */ |
#define MMA845x_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */ |
#define MMA845x_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */ |
#define MMA845x_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */ |
#define MMA845x_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */ |
#define MMA845x_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */ |
#define MMA845x_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */ |
#define MMA845x_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection block */ |
#define MMA845x_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01) |
#define MMA845x_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0) |
#define MMA845x_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection block */ |
#define MMA845x_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0) |
#define MMA845x_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5) |
#define MMA845x_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration delta */ |
#define MMA845x_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02) |
#define MMA845x_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration delta */ |
#define MMA845x_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04) |
#define MMA845x_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
#define MMA845x_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration delta */ |
#define MMA845x_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08) |
#define MMA845x_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */ |
#define MMA845x_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */ |
#define MMA845x_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01) |
#define MMA845x_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */ |
#define MMA845x_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */ |
#define MMA845x_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0) |
#define MMA845x_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the value */ |
#define MMA845x_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02) |
#define MMA845x_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04) |
#define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */ |
#define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */ |
#define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2) |
#define MMA845x_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the value */ |
#define MMA845x_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08) |
#define MMA845x_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10) |
#define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */ |
#define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */ |
#define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4) |
#define MMA845x_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the value */ |
#define MMA845x_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20) |
#define MMA845x_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */ |
#define MMA845x_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */ |
#define MMA845x_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */ |
#define MMA845x_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80) |
#define MMA845x_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */ |
#define MMA845x_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */ |
#define MMA845x_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger bit */ |
#define MMA845x_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10) |
#define MMA845x_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger bit */ |
#define MMA845x_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */ |
#define MMA845x_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */ |
#define MMA845x_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */ |
#define MMA845x_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */ |
#define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */ |
#define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */ |
#define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */ |
#define MMA845x_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */ |
#define MMA845x_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */ |
#define MMA845x_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10) |
typedef uint8_t MMA845x_OUT_X_LSB_t |
typedef uint8_t MMA845x_OUT_X_MSB_t |
typedef uint8_t MMA845x_OUT_Y_LSB_t |
typedef uint8_t MMA845x_OUT_Y_MSB_t |
typedef uint8_t MMA845x_OUT_Z_LSB_t |
typedef uint8_t MMA845x_OUT_Z_MSB_t |
anonymous enum |
MMA845x Sensor Internal Registers