ISSDK  1.7
IoT Sensing Software Development Kit
mma845x.h
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1 /*
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4  * Copyright 2016-2017 NXP
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34 
35 /**
36  * @file mma845x.h
37  * @brief The mma845x.h contains the MMA845x sensor register definitions and its bit mask.
38  */
39 
40 #ifndef MMA845x_H_
41 #define MMA845x_H_
42 
43 /**
44  ** MMA845x I2C Address
45  */
46 #define MMA845x_I2C_ADDRESS_SA0_0 0x1C /*MMA845x Address - SA0=0*/
47 #define MMA845x_I2C_ADDRESS_SA0_1 0x1D /*MMA845x Address - SA0=1*/
48 
49 /**
50  **
51  ** MMA845x Sensor Internal Registers
52  */
53 enum {
54  MMA845x_STATUS = 0x00, /*!< FMODE = 0, real time status */
55  MMA845x_F_STATUS = 0x00, /*!< FMODE > 0, FIFO status */
56  MMA845x_OUT_X_MSB = 0x01, /*!< data registers */
57  MMA845x_OUT_X_LSB = 0x02, /*!< data registers */
58  MMA845x_OUT_Y_MSB = 0x03, /*!< data registers */
59  MMA845x_OUT_Y_LSB = 0x04, /*!< data registers */
60  MMA845x_OUT_Z_MSB = 0x05, /*!< data registers */
61  MMA845x_OUT_Z_LSB = 0x06, /*!< data registers */
62  MMA845x_F_SETUP = 0x09, /*!< FIFO setup */
63  MMA845x_TRIG_CFG = 0x0A, /*!< Map of FIFO data capture events */
64  MMA845x_SYSMOD = 0x0B, /*!< SYSMOD System Mode register */
65  MMA845x_INT_SOURCE = 0x0C, /*!< INT_SOURCE System Interrupt Status register */
66  MMA845x_WHO_AM_I = 0x0D, /*!< WHO_AM_I Device ID register */
67  MMA845x_XYZ_DATA_CFG = 0x0E, /*!< XYZ_DATA_CFG register */
68  MMA845x_HP_FILTER_CUTOFF = 0x0F, /*!< MMA845x only */
69  MMA845x_PL_STATUS = 0x10, /*!< PL_STATUS Portrait/Landscape Status register */
70  MMA845x_PL_CFG = 0x11, /*!< Portrait/Landscape Configuration register */
71  MMA845x_PL_COUNT = 0x12, /*!< Portrait/Landscape Debounce register */
72  MMA845x_PL_BF_ZCOMP = 0x13, /*!< PL_BF_ZCOMP Back/Front and Z Compensation register */
73  MMA845x_PL_THS_REG = 0x14, /*!< P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register */
74  MMA845x_FF_MT_CFG = 0x15, /*!< FF_MT_CFG Freefall/Motion Configuration register */
75  MMA845x_FF_MT_SRC = 0x16, /*!< FF_MT_SRC Freefall/Motion Source register */
76  MMA845x_FF_MT_THS = 0x17, /*!< FF_MT_THS Freefall and Motion Threshold register */
77  MMA845x_FF_MT_COUNT = 0x18, /*!< FF_MT_COUNT Debounce register */
78  MMA845x_TRANSIENT_CFG = 0x1D, /*!< Transient_CFG register */
79  MMA845x_TRANSIENT_SRC = 0x1E, /*!< TRANSIENT_SRC register */
80  MMA845x_TRANSIENT_THS = 0x1F, /*!< TRANSIENT_THS register */
81  MMA845x_TRANSIENT_COUNT = 0x20, /*!< TRANSIENT_COUNT register */
82  MMA845x_PULSE_CFG = 0x21, /*!< PULSE_CFG Pulse Configuration register */
83  MMA845x_PULSE_SRC = 0x22, /*!< PULSE_SRC Pulse Source register */
84  MMA845x_PULSE_THSX = 0x23, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
85  MMA845x_PULSE_THSY = 0x24, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
86  MMA845x_PULSE_THSZ = 0x25, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
87  MMA845x_PULSE_TMLT = 0x26, /*!< PULSE_TMLT Pulse Time Window 1 register */
88  MMA845x_PULSE_LTCY = 0x27, /*!< PULSE_LTCY Pulse Latency Timer register */
89  MMA845x_PULSE_WIND = 0x28, /*!< PULSE_WIND register (Read/Write) */
90  MMA845x_ASLP_COUNT = 0x29, /*!< ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write) */
91  MMA845x_CTRL_REG1 = 0x2A, /*!< CTRL_REG1 System Control 1 register */
92  MMA845x_CTRL_REG2 = 0x2B, /*!< CTRL_REG2 System Control 1 register */
93  MMA845x_CTRL_REG3 = 0x2C, /*!< CTRL_REG3 Interrupt Control register */
94  MMA845x_CTRL_REG4 = 0x2D, /*!< CTRL_REG4 Interrupt Enable register (Read/Write) */
95  MMA845x_CTRL_REG5 = 0x2E, /*!< CTRL_REG5 Interrupt Configuration register (Read/Write) */
96  MMA845x_OFF_X = 0x2F, /*!< OFF_X Offset Correction X register */
97  MMA845x_OFF_Y = 0x30, /*!< OFF_Y Offset Correction Y register */
98  MMA845x_OFF_Z = 0x31, /*!< OFF_Z Offset Correction Z register */
99 };
100 
101 
102 /*--------------------------------
103 ** Register: STATUS
104 ** Enum: MMA845x_STATUS
105 ** --
106 ** Offset : 0x00 - Real time status.
107 ** ------------------------------*/
108 typedef union {
109  struct {
110  uint8_t xdr : 1; /* - X-axis new Data Available. */
111 
112  uint8_t ydr : 1; /* - Y-axis new Data Available. */
113 
114  uint8_t zdr : 1; /* - Z-axis new Data Available. */
115 
116  uint8_t zyxdr : 1; /* - X, Y, Z-axis new Data Ready. */
117 
118  uint8_t xow : 1; /* - X-axis Data Overwrite. */
119 
120  uint8_t yow : 1; /* - Y-axis Data Overwrite. */
121 
122  uint8_t zow : 1; /* - Z-axis Data Overwrite */
123 
124  uint8_t zyxow : 1; /* - X, Y, Z-axis Data Overwrite. */
125 
126  } b;
127  uint8_t w;
128 } MMA845x_STATUS_t;
129 
130 
131 /*
132 ** STATUS - Bit field mask definitions
133 */
134 #define MMA845x_STATUS_XDR_MASK ((uint8_t) 0x01)
135 #define MMA845x_STATUS_XDR_SHIFT ((uint8_t) 0)
136 
137 #define MMA845x_STATUS_YDR_MASK ((uint8_t) 0x02)
138 #define MMA845x_STATUS_YDR_SHIFT ((uint8_t) 1)
139 
140 #define MMA845x_STATUS_ZDR_MASK ((uint8_t) 0x04)
141 #define MMA845x_STATUS_ZDR_SHIFT ((uint8_t) 2)
142 
143 #define MMA845x_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
144 #define MMA845x_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
145 
146 #define MMA845x_STATUS_XOW_MASK ((uint8_t) 0x10)
147 #define MMA845x_STATUS_XOW_SHIFT ((uint8_t) 4)
148 
149 #define MMA845x_STATUS_YOW_MASK ((uint8_t) 0x20)
150 #define MMA845x_STATUS_YOW_SHIFT ((uint8_t) 5)
151 
152 #define MMA845x_STATUS_ZOW_MASK ((uint8_t) 0x40)
153 #define MMA845x_STATUS_ZOW_SHIFT ((uint8_t) 6)
154 
155 #define MMA845x_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
156 #define MMA845x_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
157 
158 
159 /*
160 ** STATUS - Bit field value definitions
161 */
162 #define MMA845x_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */
163 #define MMA845x_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */
164 #define MMA845x_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */
165 #define MMA845x_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */
166 #define MMA845x_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */
167  /* data before it was read. */
168 #define MMA845x_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */
169  /* data before it was read. */
170 #define MMA845x_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */
171  /* data before it was read. */
172 #define MMA845x_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, Y, */
173  /* or Z data before it was read. */
174 /*------------------------------*/
175 
176 
177 
178 /*--------------------------------
179 ** Register: F_STATUS
180 ** Enum: MMA845x_F_STATUS
181 ** --
182 ** Offset : 0x00 - FIFO STATUS Register.
183 ** ------------------------------*/
184 typedef union {
185  struct {
186  uint8_t f_cnt : 6; /* - FIFO sample counter. 00_0001 to 10_0000 indicates 1 to 32 samples stored */
187  /* in FIFO. */
188 
189  uint8_t f_wmrk_flag : 1; /* - FIFO watermark flag. */
190 
191  uint8_t f_ovf : 1; /* - FIFO overflow flag. */
192 
193  } b;
194  uint8_t w;
195 } MMA845x_F_STATUS_t;
196 
197 
198 /*
199 ** F_STATUS - Bit field mask definitions
200 */
201 #define MMA845x_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
202 #define MMA845x_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
203 
204 #define MMA845x_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
205 #define MMA845x_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
206 
207 #define MMA845x_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
208 #define MMA845x_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
209 
210 
211 /*
212 ** F_STATUS - Bit field value definitions
213 */
214 #define MMA845x_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */
215 #define MMA845x_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count is */
216  /* greater than watermark value. */
217 #define MMA845x_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */
218 #define MMA845x_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */
219 /*------------------------------*/
220 
221 
222 
223 /*--------------------------------
224 ** Register: OUT_X_MSB
225 ** Enum: MMA845x_OUT_X_MSB
226 ** --
227 ** Offset : 0x01 - Bits 4-11 of 12-bit X Axis current sample data.
228 ** ------------------------------*/
229 typedef uint8_t MMA845x_OUT_X_MSB_t;
230 
231 
232 /*--------------------------------
233 ** Register: OUT_X_LSB
234 ** Enum: MMA845x_OUT_X_LSB
235 ** --
236 ** Offset : 0x02 - Bits 0-3 of 12-bit X Axis current sample data.
237 ** ------------------------------*/
238 typedef uint8_t MMA845x_OUT_X_LSB_t;
239 
240 
241 
242 /*--------------------------------
243 ** Register: OUT_Y_MSB
244 ** Enum: MMA845x_OUT_Y_MSB
245 ** --
246 ** Offset : 0x03 - Bits 4-11 of 12-bit Y Axis current sample data.
247 ** ------------------------------*/
248 typedef uint8_t MMA845x_OUT_Y_MSB_t;
249 
250 
251 /*--------------------------------
252 ** Register: OUT_Y_LSB
253 ** Enum: MMA845x_OUT_Y_LSB
254 ** --
255 ** Offset : 0x04 - Bits 0-3 of 12-bit Y Axis current sample data.
256 ** ------------------------------*/
257 typedef uint8_t MMA845x_OUT_Y_LSB_t;
258 
259 
260 
261 /*--------------------------------
262 ** Register: OUT_Z_MSB
263 ** Enum: MMA845x_OUT_Z_MSB
264 ** --
265 ** Offset : 0x05 - Bits 4-11 of 12-bit Z Axis current sample data.
266 ** ------------------------------*/
267 typedef uint8_t MMA845x_OUT_Z_MSB_t;
268 
269 
270 /*--------------------------------
271 ** Register: OUT_Z_LSB
272 ** Enum: MMA845x_OUT_Z_LSB
273 ** --
274 ** Offset : 0x06 - Bits 0-3 of 12-bit Z Axis current sample data.
275 ** ------------------------------*/
276 typedef uint8_t MMA845x_OUT_Z_LSB_t;
277 
278 
279 
280 /*--------------------------------
281 ** Register: F_SETUP
282 ** Enum: MMA845x_F_SETUP
283 ** --
284 ** Offset : 0x09 - FIFO Setup Register.
285 ** ------------------------------*/
286 typedef union {
287  struct {
288  uint8_t f_wmrk : 6; /* - FIFO Event Sample Count Watermark. These bits set the number of FIFO */
289  /* samples required to trigger a watermark interrupt. */
290 
291  uint8_t f_mode : 2; /* - FIFO buffer overflow mode. */
292 
293  } b;
294  uint8_t w;
295 } MMA845x_F_SETUP_t;
296 
297 
298 /*
299 ** F_SETUP - Bit field mask definitions
300 */
301 #define MMA845x_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
302 #define MMA845x_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
303 
304 #define MMA845x_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
305 #define MMA845x_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
306 
307 
308 /*
309 ** F_SETUP - Bit field value definitions
310 */
311 #define MMA845x_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */
312 #define MMA845x_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when overflowed */
313  /* (circular buffer). */
314 #define MMA845x_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
315 #define MMA845x_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the number */
316  /* of samples in the watermark. The FIFO will be in a */
317  /* circular mode until the trigger event occurs. */
318 /*------------------------------*/
319 
320 
321 
322 /*--------------------------------
323 ** Register: TRIG_CFG
324 ** Enum: MMA845x_TRIG_CFG
325 ** --
326 ** Offset : 0x0A - Trigger Configuration Register.
327 ** ------------------------------*/
328 typedef union {
329  struct {
330  uint8_t _reserved_ : 2;
331  uint8_t trig_ff_mt : 1; /* - Freefall/Motion trigger bit. */
332 
333  uint8_t trig_pulse : 1; /* - Pulse interrupt trigger bit. */
334 
335  uint8_t trig_lndprt : 1; /* - Landscape/Portrait Orientation interrupt trigger bit. */
336 
337  uint8_t trig_trans : 1; /* - Transient interrupt trigger bit. */
338 
339  } b;
340  uint8_t w;
341 } MMA845x_TRIG_CFG_t;
342 
343 
344 /*
345 ** TRIG_CFG - Bit field mask definitions
346 */
347 #define MMA845x_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04)
348 #define MMA845x_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2)
349 
350 #define MMA845x_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
351 #define MMA845x_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
352 
353 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
354 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
355 
356 #define MMA845x_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
357 #define MMA845x_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
358 
359 
360 /*
361 ** TRIG_CFG - Bit field value definitions
362 */
363 #define MMA845x_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */
364 #define MMA845x_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */
365 #define MMA845x_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */
366 #define MMA845x_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */
367 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger bit */
368  /* is cleared. */
369 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger bit */
370  /* is set. */
371 #define MMA845x_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */
372 #define MMA845x_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */
373 /*------------------------------*/
374 
375 
376 
377 /*--------------------------------
378 ** Register: SYSMOD
379 ** Enum: MMA845x_SYSMOD
380 ** --
381 ** Offset : 0x0B - System Mode Register indicates the current device operating mode.
382 ** ------------------------------*/
383 typedef union {
384  struct {
385  uint8_t sysmod : 2; /* - System mode data bits. */
386 
387  uint8_t fgt : 5; /* - Number of ODR time units since FGERR was asserted. Reset when FGERR */
388  /* Cleared. */
389 
390  uint8_t fgerr : 1; /* - FIFO Gate Error. */
391 
392  } b;
393  uint8_t w;
394 } MMA845x_SYSMOD_t;
395 
396 
397 /*
398 ** SYSMOD - Bit field mask definitions
399 */
400 #define MMA845x_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
401 #define MMA845x_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
402 
403 #define MMA845x_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
404 #define MMA845x_SYSMOD_FGT_SHIFT ((uint8_t) 2)
405 
406 #define MMA845x_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
407 #define MMA845x_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
408 
409 
410 /*
411 ** SYSMOD - Bit field value definitions
412 */
413 #define MMA845x_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
414 #define MMA845x_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */
415 #define MMA845x_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */
416 #define MMA845x_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */
417 #define MMA845x_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */
418 /*------------------------------*/
419 
420 
421 
422 /*--------------------------------
423 ** Register: INT_SOURCE
424 ** Enum: MMA845x_INT_SOURCE
425 ** --
426 ** Offset : 0x0C - System Interrupt Status Register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
427 ** ------------------------------*/
428 typedef union {
429  struct {
430  uint8_t src_drdy : 1; /* Data Ready Interrupt bit status. */
431 
432  uint8_t _reserved_ : 1;
433  uint8_t src_ff_mt : 1; /* Freefall/Motion interrupt status bit. */
434 
435  uint8_t src_pulse : 1; /* Pulse interrupt status bit. */
436 
437  uint8_t src_lndprt : 1; /* Landscape/Portrait Orientation interrupt status bit. */
438 
439  uint8_t src_trans : 1; /* Transient interrupt status bit. */
440 
441  uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
442 
443  uint8_t src_aslp : 1; /* Auto-SLEEP/WAKE interrupt status bit. */
444 
445  } b;
446  uint8_t w;
447 } MMA845x_INT_SOURCE_t;
448 
449 
450 /*
451 ** INT_SOURCE - Bit field mask definitions
452 */
453 #define MMA845x_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
454 #define MMA845x_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
455 
456 #define MMA845x_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04)
457 #define MMA845x_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2)
458 
459 #define MMA845x_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
460 #define MMA845x_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
461 
462 #define MMA845x_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
463 #define MMA845x_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
464 
465 #define MMA845x_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
466 #define MMA845x_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
467 
468 #define MMA845x_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
469 #define MMA845x_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
470 
471 #define MMA845x_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
472 #define MMA845x_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
473 
474 
475 /*------------------------------*/
476 
477 
478 
479 /*--------------------------------
480 ** Register: WHO_AM_I
481 ** Enum: MMA845x_WHO_AM_I
482 ** --
483 ** Offset : 0x0D - Fixed Device ID Number.
484 ** ------------------------------*/
485 typedef union {
486  struct {
487  uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */
488  /* programmed. */
489 
490  } b;
491  uint8_t w;
492 } MMA845x_WHO_AM_I_t;
493 
494 
495 /*
496 ** WHO_AM_I - Bit field mask definitions
497 */
498 #define MMA845x_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF)
499 #define MMA845x_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0)
500 
501 
502 /*------------------------------*/
503 
504 
505 /*
506 ** WHO_AM_I - Bit field value definitions
507 */
508 #define MMA8451_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x1a) /* Device identifier for MMA8451 */
509 #define MMA8452_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x2a) /* Device identifier for MMA8452 */
510 #define MMA8453_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x3a) /* Device identifier for MMA8452 */
511 /*------------------------------*/
512 
513 
514 
515 /*--------------------------------
516 ** Register: XYZ_DATA_CFG
517 ** Enum: MMA845x_XYZ_DATA_CFG
518 ** --
519 ** Offset : 0x0E - XYZ Data Configuration Register. sets the dynamic range and sets the high-pass filter for the output data.
520 ** ------------------------------*/
521 typedef union {
522  struct {
523  uint8_t fs : 2; /* Output buffer data format full scale. */
524 
525  uint8_t _reserved_ : 2;
526  uint8_t hpf_out : 1; /* Enable High-Pass output data. */
527 
528  } b;
529  uint8_t w;
530 } MMA845x_XYZ_DATA_CFG_t;
531 
532 
533 /*
534 ** XYZ_DATA_CFG - Bit field mask definitions
535 */
536 #define MMA845x_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
537 #define MMA845x_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
538 
539 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
540 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
541 
542 
543 /*
544 ** XYZ_DATA_CFG - Bit field value definitions
545 */
546 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */
547 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */
548 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */
549 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */
550 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */
551 /*------------------------------*/
552 
553 
554 
555 /*--------------------------------
556 ** Register: HP_FILTER_CUTOFF
557 ** Enum: MMA845x_HP_FILTER_CUTOFF
558 ** --
559 ** Offset : 0x0F - HP_FILTER_CUTOFF High-Pass Filter Register. This register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data.
560 ** ------------------------------*/
561 typedef union {
562  struct {
563  uint8_t sel : 2; /* HPF Cutoff frequency selection. */
564 
565  uint8_t _reserved_ : 2;
566  uint8_t pulse_lpf_en : 1; /* Enable Low-Pass Filter for Pulse Processing Function. */
567 
568  uint8_t pulse_hpf_byp : 1; /* Bypass High-Pass Filter for Pulse Processing Function. */
569 
570  } b;
571  uint8_t w;
572 } MMA845x_HP_FILTER_CUTOFF_t;
573 
574 
575 /*
576 ** HP_FILTER_CUTOFF - Bit field mask definitions
577 */
578 #define MMA845x_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
579 #define MMA845x_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
580 
581 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
582 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
583 
584 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
585 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
586 
587 
588 /*
589 ** HP_FILTER_CUTOFF - Bit field value definitions
590 */
591 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */
592 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */
593 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */
594 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */
595 /*------------------------------*/
596 
597 
598 
599 /*--------------------------------
600 ** Register: PL_STATUS
601 ** Enum: MMA845x_PL_STATUS
602 ** --
603 ** Offset : 0x10 - Portrait/Landscape Status Register.
604 ** ------------------------------*/
605 typedef union {
606  struct {
607  uint8_t bafro : 1; /* Back or Front orientation. */
608 
609  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
610 
611  uint8_t _reserved_ : 3;
612  uint8_t lo : 1; /* Z-Tilt Angle Lockout. */
613 
614  uint8_t newlp : 1; /* Landscape/Portrait status change flag. */
615 
616  } b;
617  uint8_t w;
618 } MMA845x_PL_STATUS_t;
619 
620 
621 /*
622 ** PL_STATUS - Bit field mask definitions
623 */
624 #define MMA845x_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
625 #define MMA845x_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
626 
627 #define MMA845x_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
628 #define MMA845x_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
629 
630 #define MMA845x_PL_STATUS_LO_MASK ((uint8_t) 0x40)
631 #define MMA845x_PL_STATUS_LO_SHIFT ((uint8_t) 6)
632 
633 #define MMA845x_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
634 #define MMA845x_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
635 
636 
637 /*
638 ** PL_STATUS - Bit field value definitions
639 */
640 #define MMA845x_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */
641  /* orientation. */
642 #define MMA845x_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing orientation. */
643 #define MMA845x_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */
644  /* normal orientation. */
645 #define MMA845x_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in the */
646  /* inverted orientation. */
647 #define MMA845x_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode to */
648  /* the right. */
649 #define MMA845x_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */
650  /* the left. */
651 #define MMA845x_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */
652 #define MMA845x_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */
653  /* Lockout has been detected. */
654 #define MMA845x_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */
655 #define MMA845x_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */
656  /* changed. */
657 /*------------------------------*/
658 
659 
660 
661 /*--------------------------------
662 ** Register: PL_CFG
663 ** Enum: MMA845x_PL_CFG
664 ** --
665 ** Offset : 0x11 - Portrait/Landscape Configuration Register.
666 ** ------------------------------*/
667 typedef union {
668  struct {
669  uint8_t reserved : 6; /* - Bits 5-0 are reserved, will always read 0. */
670 
671  uint8_t pl_en : 1; /* - Portrait/Landscape Detection Enable. */
672 
673  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
674 
675  } b;
676  uint8_t w;
677 } MMA845x_PL_CFG_t;
678 
679 
680 /*
681 ** PL_CFG - Bit field mask definitions
682 */
683 #define MMA845x_PL_CFG_RESERVED_MASK ((uint8_t) 0x3F)
684 #define MMA845x_PL_CFG_RESERVED_SHIFT ((uint8_t) 0)
685 
686 #define MMA845x_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
687 #define MMA845x_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
688 
689 #define MMA845x_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
690 #define MMA845x_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
691 
692 
693 /*
694 ** PL_CFG - Bit field value definitions
695 */
696 #define MMA845x_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */
697 #define MMA845x_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */
698 #define MMA845x_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */
699  /* no longer valid. */
700 #define MMA845x_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
701  /* longer valid. */
702 /*------------------------------*/
703 
704 
705 
706 /*--------------------------------
707 ** Register: PL_COUNT
708 ** Enum: MMA845x_PL_COUNT
709 ** --
710 ** Offset : 0x12 - Portrait/Landscape Debounce Counter.
711 ** ------------------------------*/
712 typedef union {
713  struct {
714  uint8_t dbcne; /* - Debounce Count value. */
715 
716  } b;
717  uint8_t w;
718 } MMA845x_PL_COUNT_t;
719 
720 
721 /*
722 ** PL_COUNT - Bit field mask definitions
723 */
724 #define MMA845x_PL_COUNT_DBCNE_MASK ((uint8_t) 0xFF)
725 #define MMA845x_PL_COUNT_DBCNE_SHIFT ((uint8_t) 0)
726 
727 
728 /*------------------------------*/
729 
730 
731 
732 /*--------------------------------
733 ** Register: PL_BF_ZCOMP
734 ** Enum: MMA845x_PL_BF_ZCOMP
735 ** --
736 ** Offset : 0x13 - Back/Front and Z Compensation Register.
737 ** ------------------------------*/
738 typedef union {
739  struct {
740  uint8_t zlock : 3; /* - Z-Lock Angle Fixed Threshold. */
741 
742  uint8_t _reserved_ : 3;
743  uint8_t bkfr : 2; /* - Back Front Trip Angle Fixed Threshold. */
744 
745  } b;
746  uint8_t w;
747 } MMA845x_PL_BF_ZCOMP_t;
748 
749 
750 /*
751 ** PL_BF_ZCOMP - Bit field mask definitions
752 */
753 #define MMA845x_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
754 #define MMA845x_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
755 
756 #define MMA845x_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
757 #define MMA845x_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
758 
759 
760 /*
761 ** PL_BF_ZCOMP - Bit field value definitions
762 */
763 #define MMA845x_PL_BF_ZCOMP_ZLOCK_THR ((uint8_t) 0x64) /* Z-Lock angle compensation is set to 29°. */
764 #define MMA845x_PL_BF_ZCOMP_BKFR_THR ((uint8_t) 0x40) /* Back to Front trip angle is set to ±75°. */
765 /*------------------------------*/
766 
767 
768 
769 /*--------------------------------
770 ** Register: PL_THS_REG
771 ** Enum: MMA845x_PL_THS_REG
772 ** --
773 ** Offset : 0x14 - Portrait/Landscape Threshold and Hysteresis Register.
774 ** ------------------------------*/
775 typedef union {
776  struct {
777  uint8_t hys : 3; /* - Hysteresis, This is a fixed angle added to the threshold angle for a */
778  /* smoother transition from Portrait to Landscape and Landscape to Portrait. */
779 
780  uint8_t pl_ths : 5; /* - Portrait/Landscape Fixed Threshold angle. */
781 
782  } b;
783  uint8_t w;
784 } MMA845x_PL_THS_REG_t;
785 
786 
787 /*
788 ** PL_THS_REG - Bit field mask definitions
789 */
790 #define MMA845x_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
791 #define MMA845x_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
792 
793 #define MMA845x_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
794 #define MMA845x_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
795 
796 
797 /*
798 ** PL_THS_REG - Bit field value definitions
799 */
800 #define MMA845x_PL_THS_REG_HYS_THR ((uint8_t) 0x64) /* Hysteresis angle is fixed at ±14°, which is 100. */
801 #define MMA845x_PL_THS_REG_PL_THS_THR ((uint8_t) 0x80) /* Portrait/Landscape Fixed Threshold angle = 1_0000 */
802  /* (45°). */
803 /*------------------------------*/
804 
805 
806 
807 /*--------------------------------
808 ** Register: FF_MT_CFG
809 ** Enum: MMA845x_FF_MT_CFG
810 ** --
811 ** Offset : 0x15 - Freefall/Motion Configuration Register.
812 ** ------------------------------*/
813 typedef union {
814  struct {
815  uint8_t reserved : 3; /* - Bits 2-0 are reserved, will always read 0. */
816 
817  uint8_t xefe : 1; /* - Event flag enable on X event. */
818 
819  uint8_t yefe : 1; /* - Event flag enable on Y event. */
820 
821  uint8_t zefe : 1; /* - Event flag enable on Z event. */
822 
823  uint8_t oae : 1; /* - Motion detect / Freefall detect flag selection. */
824 
825  uint8_t ele : 1; /* - Event Latch Enable. */
826 
827  } b;
828  uint8_t w;
829 } MMA845x_FF_MT_CFG_t;
830 
831 
832 /*
833 ** FF_MT_CFG - Bit field mask definitions
834 */
835 #define MMA845x_FF_MT_CFG_RESERVED_MASK ((uint8_t) 0x07)
836 #define MMA845x_FF_MT_CFG_RESERVED_SHIFT ((uint8_t) 0)
837 
838 #define MMA845x_FF_MT_CFG_XEFE_MASK ((uint8_t) 0x08)
839 #define MMA845x_FF_MT_CFG_XEFE_SHIFT ((uint8_t) 3)
840 
841 #define MMA845x_FF_MT_CFG_YEFE_MASK ((uint8_t) 0x10)
842 #define MMA845x_FF_MT_CFG_YEFE_SHIFT ((uint8_t) 4)
843 
844 #define MMA845x_FF_MT_CFG_ZEFE_MASK ((uint8_t) 0x20)
845 #define MMA845x_FF_MT_CFG_ZEFE_SHIFT ((uint8_t) 5)
846 
847 #define MMA845x_FF_MT_CFG_OAE_MASK ((uint8_t) 0x40)
848 #define MMA845x_FF_MT_CFG_OAE_SHIFT ((uint8_t) 6)
849 
850 #define MMA845x_FF_MT_CFG_ELE_MASK ((uint8_t) 0x80)
851 #define MMA845x_FF_MT_CFG_ELE_SHIFT ((uint8_t) 7)
852 
853 
854 /*
855 ** FF_MT_CFG - Bit field value definitions
856 */
857 #define MMA845x_FF_MT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
858 #define MMA845x_FF_MT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */
859  /* beyond preset threshold. */
860 #define MMA845x_FF_MT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
861 #define MMA845x_FF_MT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */
862  /* beyond preset threshold. */
863 #define MMA845x_FF_MT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
864 #define MMA845x_FF_MT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */
865  /* beyond preset threshold. */
866 #define MMA845x_FF_MT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */
867 #define MMA845x_FF_MT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */
868 #define MMA845x_FF_MT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
869 #define MMA845x_FF_MT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */
870 /*------------------------------*/
871 
872 
873 
874 /*--------------------------------
875 ** Register: FF_MT_SRC
876 ** Enum: MMA845x_FF_MT_SRC
877 ** --
878 ** Offset : 0x16 - Freefall/Motion Source Register.
879 ** ------------------------------*/
880 typedef union {
881  struct {
882  uint8_t xhp : 1; /* - Event flag enable on X event. */
883 
884  uint8_t xhe : 1; /* - Event flag enable on Y event. */
885 
886  uint8_t yhp : 1; /* - Event flag enable on Z event. */
887 
888  uint8_t yhe : 1; /* - Motion detect / Freefall detect flag selection. */
889 
890  uint8_t zhp : 1; /* - Event Latch Enable. */
891 
892  uint8_t zhe : 1; /* - Event Latch Enable. */
893 
894  uint8_t _reserved_ : 1;
895  uint8_t ea : 1; /* - Event Latch Enable. */
896 
897  } b;
898  uint8_t w;
899 } MMA845x_FF_MT_SRC_t;
900 
901 
902 /*
903 ** FF_MT_SRC - Bit field mask definitions
904 */
905 #define MMA845x_FF_MT_SRC_XHP_MASK ((uint8_t) 0x01)
906 #define MMA845x_FF_MT_SRC_XHP_SHIFT ((uint8_t) 0)
907 
908 #define MMA845x_FF_MT_SRC_XHE_MASK ((uint8_t) 0x02)
909 #define MMA845x_FF_MT_SRC_XHE_SHIFT ((uint8_t) 1)
910 
911 #define MMA845x_FF_MT_SRC_YHP_MASK ((uint8_t) 0x04)
912 #define MMA845x_FF_MT_SRC_YHP_SHIFT ((uint8_t) 2)
913 
914 #define MMA845x_FF_MT_SRC_YHE_MASK ((uint8_t) 0x08)
915 #define MMA845x_FF_MT_SRC_YHE_SHIFT ((uint8_t) 3)
916 
917 #define MMA845x_FF_MT_SRC_ZHP_MASK ((uint8_t) 0x10)
918 #define MMA845x_FF_MT_SRC_ZHP_SHIFT ((uint8_t) 4)
919 
920 #define MMA845x_FF_MT_SRC_ZHE_MASK ((uint8_t) 0x20)
921 #define MMA845x_FF_MT_SRC_ZHE_SHIFT ((uint8_t) 5)
922 
923 #define MMA845x_FF_MT_SRC_EA_MASK ((uint8_t) 0x80)
924 #define MMA845x_FF_MT_SRC_EA_SHIFT ((uint8_t) 7)
925 
926 
927 /*
928 ** FF_MT_SRC - Bit field value definitions
929 */
930 #define MMA845x_FF_MT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
931 #define MMA845x_FF_MT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
932 #define MMA845x_FF_MT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */
933 #define MMA845x_FF_MT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */
934 #define MMA845x_FF_MT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
935 #define MMA845x_FF_MT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
936 #define MMA845x_FF_MT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */
937 #define MMA845x_FF_MT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */
938 #define MMA845x_FF_MT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
939 #define MMA845x_FF_MT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
940 #define MMA845x_FF_MT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */
941 #define MMA845x_FF_MT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */
942 #define MMA845x_FF_MT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
943 #define MMA845x_FF_MT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */
944 /*------------------------------*/
945 
946 
947 
948 /*--------------------------------
949 ** Register: FF_MT_THS
950 ** Enum: MMA845x_FF_MT_THS
951 ** --
952 ** Offset : 0x17 - Freefall and Motion Threshold Register.
953 ** ------------------------------*/
954 typedef union {
955  struct {
956  uint8_t ths : 7; /* - Freefall /Motion Threshold. */
957 
958  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
959 
960  } b;
961  uint8_t w;
962 } MMA845x_FF_MT_THS_t;
963 
964 
965 /*
966 ** FF_MT_THS - Bit field mask definitions
967 */
968 #define MMA845x_FF_MT_THS_THS_MASK ((uint8_t) 0x7F)
969 #define MMA845x_FF_MT_THS_THS_SHIFT ((uint8_t) 0)
970 
971 #define MMA845x_FF_MT_THS_DBCNTM_MASK ((uint8_t) 0x80)
972 #define MMA845x_FF_MT_THS_DBCNTM_SHIFT ((uint8_t) 7)
973 
974 
975 /*
976 ** FF_MT_THS - Bit field value definitions
977 */
978 #define MMA845x_FF_MT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
979 #define MMA845x_FF_MT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
980 /*------------------------------*/
981 
982 
983 
984 /*--------------------------------
985 ** Register: FF_MT_COUNT
986 ** Enum: MMA845x_FF_MT_COUNT
987 ** --
988 ** Offset : 0x18 - Debounce Register.
989 ** ------------------------------*/
990 typedef union {
991  struct {
992  uint8_t d; /* - Count value. */
993 
994  } b;
995  uint8_t w;
996 } MMA845x_FF_MT_COUNT_t;
997 
998 
999 /*
1000 ** FF_MT_COUNT - Bit field mask definitions
1001 */
1002 #define MMA845x_FF_MT_COUNT_D_MASK ((uint8_t) 0xFF)
1003 #define MMA845x_FF_MT_COUNT_D_SHIFT ((uint8_t) 0)
1004 
1005 
1006 /*------------------------------*/
1007 
1008 
1009 
1010 /*--------------------------------
1011 ** Register: TRANSIENT_CFG
1012 ** Enum: MMA845x_TRANSIENT_CFG
1013 ** --
1014 ** Offset : 0x1D - Transient_CFG Register.
1015 ** ------------------------------*/
1016 typedef union {
1017  struct {
1018  uint8_t hpf_byp : 1; /* - Bypass High-Pass filter. */
1019 
1020  uint8_t xtefe : 1; /* - Event flag enable on X transient acceleration greater than transient */
1021  /* threshold event. */
1022 
1023  uint8_t ytefe : 1; /* - Event flag enable on Y transient acceleration greater than transient */
1024  /* threshold event. */
1025 
1026  uint8_t ztefe : 1; /* - Event flag enable on Z transient acceleration greater than transient */
1027  /* threshold event. */
1028 
1029  uint8_t ele : 1; /* - Transient event flags are latched into the TRANSIENT_SRC register. */
1030 
1031  uint8_t reserved : 3; /* - Bits 7-5 are reserved, will always read 0. */
1032 
1033  } b;
1034  uint8_t w;
1035 } MMA845x_TRANSIENT_CFG_t;
1036 
1037 
1038 /*
1039 ** TRANSIENT_CFG - Bit field mask definitions
1040 */
1041 #define MMA845x_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1042 #define MMA845x_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1043 
1044 #define MMA845x_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1045 #define MMA845x_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1046 
1047 #define MMA845x_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1048 #define MMA845x_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1049 
1050 #define MMA845x_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1051 #define MMA845x_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1052 
1053 #define MMA845x_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10)
1054 #define MMA845x_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4)
1055 
1056 #define MMA845x_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0)
1057 #define MMA845x_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5)
1058 
1059 
1060 /*
1061 ** TRANSIENT_CFG - Bit field value definitions
1062 */
1063 #define MMA845x_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection block */
1064  /* is through HPF. */
1065 #define MMA845x_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection block */
1066  /* is NOT through HPF. */
1067 #define MMA845x_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1068 #define MMA845x_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration delta */
1069  /* value greater than transient threshold. */
1070 #define MMA845x_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1071 #define MMA845x_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration delta */
1072  /* value greater than transient threshold. */
1073 #define MMA845x_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1074 #define MMA845x_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration delta */
1075  /* value greater than transient threshold. */
1076 #define MMA845x_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1077 #define MMA845x_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */
1078 /*------------------------------*/
1079 
1080 
1081 
1082 /*--------------------------------
1083 ** Register: TRANSIENT_SRC
1084 ** Enum: MMA845x_TRANSIENT_SRC
1085 ** --
1086 ** Offset : 0x1E - Transient_SRC Register.
1087 ** ------------------------------*/
1088 typedef union {
1089  struct {
1090  uint8_t x_trans_pol : 1; /* - Polarity of X Transient Event that triggered interrupt. */
1091 
1092  uint8_t xtrans : 1; /* - X transient event. */
1093 
1094  uint8_t y_trans_pol : 1; /* - Polarity of Y Transient Event that triggered interrupt. */
1095 
1096  uint8_t ytrans : 1; /* - Y transient event. */
1097 
1098  uint8_t z_trans_pol : 1; /* - Polarity of Z Transient Event that triggered interrupt. */
1099 
1100  uint8_t ztrans : 1; /* - Z transient event. */
1101 
1102  uint8_t ea : 1; /* - Event Active Flag. */
1103 
1104  } b;
1105  uint8_t w;
1106 } MMA845x_TRANSIENT_SRC_t;
1107 
1108 
1109 /*
1110 ** TRANSIENT_SRC - Bit field mask definitions
1111 */
1112 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01)
1113 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0)
1114 
1115 #define MMA845x_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02)
1116 #define MMA845x_TRANSIENT_SRC_XTRANS_SHIFT ((uint8_t) 1)
1117 
1118 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04)
1119 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2)
1120 
1121 #define MMA845x_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08)
1122 #define MMA845x_TRANSIENT_SRC_YTRANS_SHIFT ((uint8_t) 3)
1123 
1124 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10)
1125 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4)
1126 
1127 #define MMA845x_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20)
1128 #define MMA845x_TRANSIENT_SRC_ZTRANS_SHIFT ((uint8_t) 5)
1129 
1130 #define MMA845x_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40)
1131 #define MMA845x_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6)
1132 
1133 
1134 /*
1135 ** TRANSIENT_SRC - Bit field value definitions
1136 */
1137 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
1138 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
1139 #define MMA845x_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1140 #define MMA845x_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the value */
1141  /* of TRANSIENT_THS event has occurred. */
1142 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
1143 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
1144 #define MMA845x_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1145 #define MMA845x_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the value */
1146  /* of TRANSIENT_THS event has occurred. */
1147 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
1148 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
1149 #define MMA845x_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1150 #define MMA845x_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the value */
1151  /* of TRANSIENT_THS event has occurred. */
1152 #define MMA845x_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
1153 #define MMA845x_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */
1154 /*------------------------------*/
1155 
1156 
1157 
1158 /*--------------------------------
1159 ** Register: TRANSIENT_THS
1160 ** Enum: MMA845x_TRANSIENT_THS
1161 ** --
1162 ** Offset : 0x1F - TRANSIENT_THS Register.
1163 ** ------------------------------*/
1164 typedef union {
1165  struct {
1166  uint8_t ths : 7; /* - Transient Threshold. */
1167 
1168  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
1169 
1170  } b;
1171  uint8_t w;
1172 } MMA845x_TRANSIENT_THS_t;
1173 
1174 
1175 /*
1176 ** TRANSIENT_THS - Bit field mask definitions
1177 */
1178 #define MMA845x_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F)
1179 #define MMA845x_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0)
1180 
1181 #define MMA845x_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1182 #define MMA845x_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1183 
1184 
1185 /*
1186 ** TRANSIENT_THS - Bit field value definitions
1187 */
1188 #define MMA845x_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1189 #define MMA845x_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1190 /*------------------------------*/
1191 
1192 
1193 
1194 /*--------------------------------
1195 ** Register: TRANSIENT_COUNT
1196 ** Enum: MMA845x_TRANSIENT_COUNT
1197 ** --
1198 ** Offset : 0x20 - TRANSIENT_COUNT Register.
1199 ** ------------------------------*/
1200 typedef union {
1201  struct {
1202  uint8_t d; /* - Count value. */
1203 
1204  } b;
1205  uint8_t w;
1206 } MMA845x_TRANSIENT_COUNT_t;
1207 
1208 
1209 /*
1210 ** TRANSIENT_COUNT - Bit field mask definitions
1211 */
1212 #define MMA845x_TRANSIENT_COUNT_D_MASK ((uint8_t) 0xFF)
1213 #define MMA845x_TRANSIENT_COUNT_D_SHIFT ((uint8_t) 0)
1214 
1215 
1216 /*------------------------------*/
1217 
1218 
1219 
1220 /*--------------------------------
1221 ** Register: PULSE_CFG
1222 ** Enum: MMA845x_PULSE_CFG
1223 ** --
1224 ** Offset : 0x21 - Pulse Configuration Register.
1225 ** ------------------------------*/
1226 typedef union {
1227  struct {
1228  uint8_t xspefe : 1; /* - Event flag enable on single pulse event on X-axis. */
1229 
1230  uint8_t xdpefe : 1; /* - Event flag enable on double pulse event on X-axis. */
1231 
1232  uint8_t yspefe : 1; /* - Event flag enable on single pulse event on Y-axis. */
1233 
1234  uint8_t ydpefe : 1; /* - Event flag enable on double pulse event on Y-axis. */
1235 
1236  uint8_t zspefe : 1; /* - Event flag enable on single pulse event on Z-axis. */
1237 
1238  uint8_t zdpefe : 1; /* - Event flag enable on double pulse event on Z-axis. */
1239 
1240  uint8_t ele : 1; /* - Pulse event flags are latched into the PULSE_SRC register. */
1241 
1242  uint8_t dpa : 1; /* - Double Pulse Abort. */
1243 
1244  } b;
1245  uint8_t w;
1246 } MMA845x_PULSE_CFG_t;
1247 
1248 
1249 /*
1250 ** PULSE_CFG - Bit field mask definitions
1251 */
1252 #define MMA845x_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01)
1253 #define MMA845x_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0)
1254 
1255 #define MMA845x_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02)
1256 #define MMA845x_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1)
1257 
1258 #define MMA845x_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04)
1259 #define MMA845x_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2)
1260 
1261 #define MMA845x_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08)
1262 #define MMA845x_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3)
1263 
1264 #define MMA845x_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10)
1265 #define MMA845x_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4)
1266 
1267 #define MMA845x_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20)
1268 #define MMA845x_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5)
1269 
1270 #define MMA845x_PULSE_CFG_ELE_MASK ((uint8_t) 0x40)
1271 #define MMA845x_PULSE_CFG_ELE_SHIFT ((uint8_t) 6)
1272 
1273 #define MMA845x_PULSE_CFG_DPA_MASK ((uint8_t) 0x80)
1274 #define MMA845x_PULSE_CFG_DPA_SHIFT ((uint8_t) 7)
1275 
1276 
1277 /*
1278 ** PULSE_CFG - Bit field value definitions
1279 */
1280 #define MMA845x_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1281 #define MMA845x_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */
1282 #define MMA845x_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1283 #define MMA845x_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */
1284 #define MMA845x_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1285 #define MMA845x_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */
1286 #define MMA845x_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1287 #define MMA845x_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */
1288 #define MMA845x_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1289 #define MMA845x_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */
1290 #define MMA845x_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1291 #define MMA845x_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */
1292 #define MMA845x_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1293 #define MMA845x_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */
1294 #define MMA845x_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the start */
1295  /* of a pulse is detected. */
1296 #define MMA845x_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */
1297  /* pulse is detected. */
1298 /*------------------------------*/
1299 
1300 
1301 
1302 /*--------------------------------
1303 ** Register: PULSE_SRC
1304 ** Enum: MMA845x_PULSE_SRC
1305 ** --
1306 ** Offset : 0x22 - Pulse Source Register.
1307 ** ------------------------------*/
1308 typedef union {
1309  struct {
1310  uint8_t polx : 1; /* - Pulse polarity of X-axis Event. */
1311 
1312  uint8_t poly : 1; /* - Pulse polarity of Y-axis Event. */
1313 
1314  uint8_t polz : 1; /* - Pulse polarity of Z-axis Event. */
1315 
1316  uint8_t dpe : 1; /* - Double pulse on first event. */
1317 
1318  uint8_t axx : 1; /* - X-axis event. */
1319 
1320  uint8_t axy : 1; /* - Y-axis event. */
1321 
1322  uint8_t axz : 1; /* - Z-axis event. */
1323 
1324  uint8_t ea : 1; /* - Event Active Flag. */
1325 
1326  } b;
1327  uint8_t w;
1328 } MMA845x_PULSE_SRC_t;
1329 
1330 
1331 /*
1332 ** PULSE_SRC - Bit field mask definitions
1333 */
1334 #define MMA845x_PULSE_SRC_POLX_MASK ((uint8_t) 0x01)
1335 #define MMA845x_PULSE_SRC_POLX_SHIFT ((uint8_t) 0)
1336 
1337 #define MMA845x_PULSE_SRC_POLY_MASK ((uint8_t) 0x02)
1338 #define MMA845x_PULSE_SRC_POLY_SHIFT ((uint8_t) 1)
1339 
1340 #define MMA845x_PULSE_SRC_POLZ_MASK ((uint8_t) 0x04)
1341 #define MMA845x_PULSE_SRC_POLZ_SHIFT ((uint8_t) 2)
1342 
1343 #define MMA845x_PULSE_SRC_DPE_MASK ((uint8_t) 0x08)
1344 #define MMA845x_PULSE_SRC_DPE_SHIFT ((uint8_t) 3)
1345 
1346 #define MMA845x_PULSE_SRC_AXX_MASK ((uint8_t) 0x10)
1347 #define MMA845x_PULSE_SRC_AXX_SHIFT ((uint8_t) 4)
1348 
1349 #define MMA845x_PULSE_SRC_AXY_MASK ((uint8_t) 0x20)
1350 #define MMA845x_PULSE_SRC_AXY_SHIFT ((uint8_t) 5)
1351 
1352 #define MMA845x_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40)
1353 #define MMA845x_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6)
1354 
1355 #define MMA845x_PULSE_SRC_EA_MASK ((uint8_t) 0x80)
1356 #define MMA845x_PULSE_SRC_EA_SHIFT ((uint8_t) 7)
1357 
1358 
1359 /*
1360 ** PULSE_SRC - Bit field value definitions
1361 */
1362 #define MMA845x_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1363 #define MMA845x_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was negative. */
1364 #define MMA845x_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1365 #define MMA845x_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was negative. */
1366 #define MMA845x_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1367 #define MMA845x_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was negative. */
1368 #define MMA845x_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */
1369 #define MMA845x_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */
1370 #define MMA845x_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1371 #define MMA845x_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */
1372 #define MMA845x_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1373 #define MMA845x_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */
1374 #define MMA845x_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1375 #define MMA845x_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */
1376 #define MMA845x_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */
1377 #define MMA845x_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */
1378 /*------------------------------*/
1379 
1380 
1381 
1382 /*--------------------------------
1383 ** Register: PULSE_THSX
1384 ** Enum: MMA845x_PULSE_THSX
1385 ** --
1386 ** Offset : 0x23 - Pulse Threshold for X.
1387 ** ------------------------------*/
1388 typedef union {
1389  struct {
1390  uint8_t thsx : 7; /* - Pulse Threshold on X-axis. */
1391 
1392  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1393 
1394  } b;
1395  uint8_t w;
1396 } MMA845x_PULSE_THSX_t;
1397 
1398 
1399 /*
1400 ** PULSE_THSX - Bit field mask definitions
1401 */
1402 #define MMA845x_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F)
1403 #define MMA845x_PULSE_THSX_THSX_SHIFT ((uint8_t) 0)
1404 
1405 #define MMA845x_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80)
1406 #define MMA845x_PULSE_THSX_RESERVED_SHIFT ((uint8_t) 7)
1407 
1408 
1409 /*------------------------------*/
1410 
1411 
1412 
1413 /*--------------------------------
1414 ** Register: PULSE_THSY
1415 ** Enum: MMA845x_PULSE_THSY
1416 ** --
1417 ** Offset : 0x24 - Pulse Threshold for Y.
1418 ** ------------------------------*/
1419 typedef union {
1420  struct {
1421  uint8_t thsy : 7; /* - Pulse Threshold on Y-axis. */
1422 
1423  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1424 
1425  } b;
1426  uint8_t w;
1427 } MMA845x_PULSE_THSY_t;
1428 
1429 
1430 /*
1431 ** PULSE_THSY - Bit field mask definitions
1432 */
1433 #define MMA845x_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F)
1434 #define MMA845x_PULSE_THSY_THSY_SHIFT ((uint8_t) 0)
1435 
1436 #define MMA845x_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80)
1437 #define MMA845x_PULSE_THSY_RESERVED_SHIFT ((uint8_t) 7)
1438 
1439 
1440 /*------------------------------*/
1441 
1442 
1443 
1444 /*--------------------------------
1445 ** Register: PULSE_THSZ
1446 ** Enum: MMA845x_PULSE_THSZ
1447 ** --
1448 ** Offset : 0x25 - Pulse Threshold for Z.
1449 ** ------------------------------*/
1450 typedef union {
1451  struct {
1452  uint8_t thsz : 7; /* - Pulse Threshold on Z-axis. */
1453 
1454  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1455 
1456  } b;
1457  uint8_t w;
1458 } MMA845x_PULSE_THSZ_t;
1459 
1460 
1461 /*
1462 ** PULSE_THSZ - Bit field mask definitions
1463 */
1464 #define MMA845x_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F)
1465 #define MMA845x_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0)
1466 
1467 #define MMA845x_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80)
1468 #define MMA845x_PULSE_THSZ_RESERVED_SHIFT ((uint8_t) 7)
1469 
1470 
1471 /*------------------------------*/
1472 
1473 
1474 
1475 /*--------------------------------
1476 ** Register: PULSE_TMLT
1477 ** Enum: MMA845x_PULSE_TMLT
1478 ** --
1479 ** Offset : 0x26 - Pulse Time Window 1 Register.
1480 ** ------------------------------*/
1481 typedef union {
1482  struct {
1483  uint8_t tmlt; /* - Pulse Time Limit. */
1484 
1485  } b;
1486  uint8_t w;
1487 } MMA845x_PULSE_TMLT_t;
1488 
1489 
1490 /*
1491 ** PULSE_TMLT - Bit field mask definitions
1492 */
1493 #define MMA845x_PULSE_TMLT_TMLT_MASK ((uint8_t) 0xFF)
1494 #define MMA845x_PULSE_TMLT_TMLT_SHIFT ((uint8_t) 0)
1495 
1496 
1497 /*------------------------------*/
1498 
1499 
1500 
1501 /*--------------------------------
1502 ** Register: PULSE_LTCY
1503 ** Enum: MMA845x_PULSE_LTCY
1504 ** --
1505 ** Offset : 0x27 - Pulse Latency Timer Register.
1506 ** ------------------------------*/
1507 typedef union {
1508  struct {
1509  uint8_t ltcy; /* - Latency Time Limit. */
1510 
1511  } b;
1512  uint8_t w;
1513 } MMA845x_PULSE_LTCY_t;
1514 
1515 
1516 /*
1517 ** PULSE_LTCY - Bit field mask definitions
1518 */
1519 #define MMA845x_PULSE_LTCY_LTCY_MASK ((uint8_t) 0xFF)
1520 #define MMA845x_PULSE_LTCY_LTCY_SHIFT ((uint8_t) 0)
1521 
1522 
1523 /*------------------------------*/
1524 
1525 
1526 
1527 /*--------------------------------
1528 ** Register: PULSE_WIND
1529 ** Enum: MMA845x_PULSE_WIND
1530 ** --
1531 ** Offset : 0x28 - Second Pulse Time Window Register.
1532 ** ------------------------------*/
1533 typedef union {
1534  struct {
1535  uint8_t wind; /* - Second Pulse Time Window. */
1536 
1537  } b;
1538  uint8_t w;
1539 } MMA845x_PULSE_WIND_t;
1540 
1541 
1542 /*
1543 ** PULSE_WIND - Bit field mask definitions
1544 */
1545 #define MMA845x_PULSE_WIND_WIND_MASK ((uint8_t) 0xFF)
1546 #define MMA845x_PULSE_WIND_WIND_SHIFT ((uint8_t) 0)
1547 
1548 
1549 /*------------------------------*/
1550 
1551 
1552 
1553 /*--------------------------------
1554 ** Register: ASLP_COUNT
1555 ** Enum: MMA845x_ASLP_COUNT
1556 ** --
1557 ** Offset : 0x29 - Auto-WAKE/SLEEP count Register.
1558 ** ------------------------------*/
1559 typedef union {
1560  struct {
1561  uint8_t d; /* - Duration value. */
1562 
1563  } b;
1564  uint8_t w;
1565 } MMA845x_ASLP_COUNT_t;
1566 
1567 
1568 /*
1569 ** ASLP_COUNT - Bit field mask definitions
1570 */
1571 #define MMA845x_ASLP_COUNT_D_MASK ((uint8_t) 0xFF)
1572 #define MMA845x_ASLP_COUNT_D_SHIFT ((uint8_t) 0)
1573 
1574 
1575 /*------------------------------*/
1576 
1577 
1578 
1579 /*--------------------------------
1580 ** Register: CTRL_REG1
1581 ** Enum: MMA845x_CTRL_REG1
1582 ** --
1583 ** Offset : 0x2A - System Control 1 Register.
1584 ** ------------------------------*/
1585 typedef union {
1586  struct {
1587  uint8_t mode : 1; /* - Full Scale selection. */
1588 
1589  uint8_t f_read : 1; /* - Fast Read mode. */
1590 
1591  uint8_t lnoise : 1; /* - Reduced noise reduced Maximum range mode. */
1592 
1593  uint8_t dr : 3; /* - Data rate selection. */
1594 
1595  uint8_t aslp_rate : 2; /* - Configures the Auto-WAKE sample frequency when the device is in SLEEP */
1596  /* Mode. */
1597 
1598  } b;
1599  uint8_t w;
1600 } MMA845x_CTRL_REG1_t;
1601 
1602 
1603 /*
1604 ** CTRL_REG1 - Bit field mask definitions
1605 */
1606 #define MMA845x_CTRL_REG1_MODE_MASK ((uint8_t) 0x01)
1607 #define MMA845x_CTRL_REG1_MODE_SHIFT ((uint8_t) 0)
1608 
1609 #define MMA845x_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1610 #define MMA845x_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1611 
1612 #define MMA845x_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1613 #define MMA845x_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1614 
1615 #define MMA845x_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1616 #define MMA845x_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1617 
1618 #define MMA845x_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1619 #define MMA845x_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1620 
1621 
1622 /*
1623 ** CTRL_REG1 - Bit field value definitions
1624 */
1625 #define MMA845x_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */
1626 #define MMA845x_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */
1627 #define MMA845x_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1628 #define MMA845x_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */
1629 #define MMA845x_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1630 #define MMA845x_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */
1631 #define MMA845x_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */
1632 #define MMA845x_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */
1633 #define MMA845x_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */
1634 #define MMA845x_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */
1635 #define MMA845x_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */
1636 #define MMA845x_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */
1637 #define MMA845x_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */
1638 #define MMA845x_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */
1639 #define MMA845x_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */
1640 #define MMA845x_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */
1641 #define MMA845x_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */
1642 #define MMA845x_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */
1643 /*------------------------------*/
1644 
1645 
1646 
1647 /*--------------------------------
1648 ** Register: CTRL_REG2
1649 ** Enum: MMA845x_CTRL_REG2
1650 ** --
1651 ** Offset : 0x2B - System Control 2 Register.
1652 ** ------------------------------*/
1653 typedef union {
1654  struct {
1655  uint8_t mods : 2; /* - ACTIVE mode power scheme selection. */
1656 
1657  uint8_t slpe : 1; /* - Auto-SLEEP enable. */
1658 
1659  uint8_t smods : 2; /* - SLEEP mode power scheme selection. */
1660 
1661  uint8_t _reserved_ : 1;
1662  uint8_t rst : 1; /* - Software Reset. */
1663 
1664  uint8_t st : 1; /* - Self-Test Enable. */
1665 
1666  } b;
1667  uint8_t w;
1668 } MMA845x_CTRL_REG2_t;
1669 
1670 
1671 /*
1672 ** CTRL_REG2 - Bit field mask definitions
1673 */
1674 #define MMA845x_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1675 #define MMA845x_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1676 
1677 #define MMA845x_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1678 #define MMA845x_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1679 
1680 #define MMA845x_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1681 #define MMA845x_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1682 
1683 #define MMA845x_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1684 #define MMA845x_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1685 
1686 #define MMA845x_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1687 #define MMA845x_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1688 
1689 
1690 /*
1691 ** CTRL_REG2 - Bit field value definitions
1692 */
1693 #define MMA845x_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1694 #define MMA845x_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */
1695 #define MMA845x_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */
1696 #define MMA845x_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */
1697 #define MMA845x_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */
1698 #define MMA845x_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */
1699 #define MMA845x_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1700 #define MMA845x_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */
1701 #define MMA845x_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */
1702 #define MMA845x_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */
1703 #define MMA845x_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */
1704 #define MMA845x_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */
1705 #define MMA845x_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */
1706 #define MMA845x_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */
1707 /*------------------------------*/
1708 
1709 
1710 
1711 /*--------------------------------
1712 ** Register: CTRL_REG3
1713 ** Enum: MMA845x_CTRL_REG3
1714 ** --
1715 ** Offset : 0x2C - Interrupt Control Register.
1716 ** ------------------------------*/
1717 typedef union {
1718  struct {
1719  uint8_t pp_od : 1; /* - Push-Pull/Open Drain selection on interrupt pad. */
1720 
1721  uint8_t ipol : 1; /* - Interrupt polarity ACTIVE high, or ACTIVE low. */
1722 
1723  uint8_t _reserved_ : 1;
1724  uint8_t wake_ff_mt : 1; /* - Freefall/Motion wake up interrupt. */
1725 
1726  uint8_t wake_pulse : 1; /* - Pulse wake up interrupt. */
1727 
1728  uint8_t wake_lndprt : 1; /* - Orientation wake up interrupt. */
1729 
1730  uint8_t wake_trans : 1; /* - Transient wake up interrupt. */
1731 
1732  uint8_t fifo_gate : 1; /* - FIFO Gate wake up interrupt. */
1733 
1734  } b;
1735  uint8_t w;
1736 } MMA845x_CTRL_REG3_t;
1737 
1738 
1739 /*
1740 ** CTRL_REG3 - Bit field mask definitions
1741 */
1742 #define MMA845x_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1743 #define MMA845x_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1744 
1745 #define MMA845x_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1746 #define MMA845x_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1747 
1748 #define MMA845x_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08)
1749 #define MMA845x_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3)
1750 
1751 #define MMA845x_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1752 #define MMA845x_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1753 
1754 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1755 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1756 
1757 #define MMA845x_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1758 #define MMA845x_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1759 
1760 #define MMA845x_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1761 #define MMA845x_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1762 
1763 
1764 /*
1765 ** CTRL_REG3 - Bit field value definitions
1766 */
1767 #define MMA845x_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */
1768 #define MMA845x_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */
1769 #define MMA845x_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */
1770 #define MMA845x_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */
1771 #define MMA845x_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP mode. */
1772 #define MMA845x_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */
1773 #define MMA845x_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */
1774 #define MMA845x_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */
1775 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */
1776 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */
1777 #define MMA845x_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */
1778 #define MMA845x_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */
1779 #define MMA845x_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */
1780  /* system mode transitioning from WAKE to SLEEP mode */
1781  /* or from SLEEP to WAKE mode. */
1782 #define MMA845x_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when transitioning */
1783  /* from WAKE to SLEEP mode or from SLEEP to WAKE mode */
1784  /* until the FIFO is flushed. */
1785 /*------------------------------*/
1786 
1787 
1788 
1789 /*--------------------------------
1790 ** Register: CTRL_REG4
1791 ** Enum: MMA845x_CTRL_REG4
1792 ** --
1793 ** Offset : 0x2D - Interrupt Enable register (Read/Write).
1794 ** ------------------------------*/
1795 typedef union {
1796  struct {
1797  uint8_t int_en_drdy : 1; /* - Interrupt Enable. */
1798 
1799  uint8_t _reserved_ : 1;
1800  uint8_t int_en_ff_mt : 1; /* - Interrupt Enable. */
1801 
1802  uint8_t int_en_pulse : 1; /* - Interrupt Enable. */
1803 
1804  uint8_t int_en_lndprt : 1; /* - Interrupt Enable. */
1805 
1806  uint8_t int_en_trans : 1; /* - Interrupt Enable. */
1807 
1808  uint8_t int_en_fifo : 1; /* - Interrupt Enable. */
1809 
1810  uint8_t int_en_aslp : 1; /* - Interrupt Enable. */
1811 
1812  } b;
1813  uint8_t w;
1814 } MMA845x_CTRL_REG4_t;
1815 
1816 
1817 /*
1818 ** CTRL_REG4 - Bit field mask definitions
1819 */
1820 #define MMA845x_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1821 #define MMA845x_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1822 
1823 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04)
1824 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2)
1825 
1826 #define MMA845x_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1827 #define MMA845x_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1828 
1829 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1830 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1831 
1832 #define MMA845x_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1833 #define MMA845x_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1834 
1835 #define MMA845x_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1836 #define MMA845x_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1837 
1838 #define MMA845x_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1839 #define MMA845x_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1840 
1841 
1842 /*
1843 ** CTRL_REG4 - Bit field value definitions
1844 */
1845 #define MMA845x_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1846 #define MMA845x_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */
1847 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */
1848 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */
1849 #define MMA845x_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */
1850 #define MMA845x_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */
1851 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */
1852  /* disabled. */
1853 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt enabled. */
1854 #define MMA845x_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */
1855 #define MMA845x_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */
1856 #define MMA845x_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1857 #define MMA845x_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */
1858 #define MMA845x_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */
1859 #define MMA845x_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */
1860 /*------------------------------*/
1861 
1862 
1863 
1864 /*--------------------------------
1865 ** Register: CTRL_REG5
1866 ** Enum: MMA845x_CTRL_REG5
1867 ** --
1868 ** Offset : 0x2E - Interrupt Configuration Register.
1869 ** ------------------------------*/
1870 typedef union {
1871  struct {
1872  uint8_t int_cfg_drdy : 1; /* - INT1/INT2 Configuration. */
1873 
1874  uint8_t _reserved_ : 1;
1875  uint8_t int_cfg_ff_mt : 1; /* - INT1/INT2 Configuration. */
1876 
1877  uint8_t int_cfg_pulse : 1; /* - INT1/INT2 Configuration. */
1878 
1879  uint8_t int_cfg_lndprt : 1; /* - INT1/INT2 Configuration. */
1880 
1881  uint8_t int_cfg_trans : 1; /* - INT1/INT2 Configuration. */
1882 
1883  uint8_t int_cfg_fifo : 1; /* - INT1/INT2 Configuration. */
1884 
1885  uint8_t int_cfg_aslp : 1; /* - INT1/INT2 Configuration. */
1886 
1887  } b;
1888  uint8_t w;
1889 } MMA845x_CTRL_REG5_t;
1890 
1891 
1892 /*
1893 ** CTRL_REG5 - Bit field mask definitions
1894 */
1895 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1896 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1897 
1898 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04)
1899 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2)
1900 
1901 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1902 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1903 
1904 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1905 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1906 
1907 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1908 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1909 
1910 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1911 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1912 
1913 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1914 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1915 
1916 
1917 /*
1918 ** CTRL_REG5 - Bit field value definitions
1919 */
1920 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1921 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */
1922 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1923 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */
1924 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1925 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */
1926 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1927 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */
1928 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1929 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */
1930 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1931 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */
1932 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1933 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */
1934 /*------------------------------*/
1935 
1936 
1937 
1938 /*--------------------------------
1939 ** Register: OFF_X
1940 ** Enum: MMA845x_OFF_X
1941 ** --
1942 ** Offset : 0x2F - Offset Correction X Register.
1943 ** ------------------------------*/
1944 typedef union {
1945  struct {
1946  uint8_t d; /* - X-axis offset value. */
1947 
1948  } b;
1949  uint8_t w;
1950 } MMA845x_OFF_X_t;
1951 
1952 
1953 /*
1954 ** OFF_X - Bit field mask definitions
1955 */
1956 #define MMA845x_OFF_X_D_MASK ((uint8_t) 0xFF)
1957 #define MMA845x_OFF_X_D_SHIFT ((uint8_t) 0)
1958 
1959 
1960 /*------------------------------*/
1961 
1962 
1963 
1964 /*--------------------------------
1965 ** Register: OFF_Y
1966 ** Enum: MMA845x_OFF_Y
1967 ** --
1968 ** Offset : 0x30 - Offset Correction Y Register.
1969 ** ------------------------------*/
1970 typedef union {
1971  struct {
1972  uint8_t d; /* - Y-axis offset value. */
1973 
1974  } b;
1975  uint8_t w;
1976 } MMA845x_OFF_Y_t;
1977 
1978 
1979 /*
1980 ** OFF_Y - Bit field mask definitions
1981 */
1982 #define MMA845x_OFF_Y_D_MASK ((uint8_t) 0xFF)
1983 #define MMA845x_OFF_Y_D_SHIFT ((uint8_t) 0)
1984 
1985 
1986 /*------------------------------*/
1987 
1988 
1989 
1990 /*--------------------------------
1991 ** Register: OFF_Z
1992 ** Enum: MMA845x_OFF_Z
1993 ** --
1994 ** Offset : 0x31 - Offset Correction Z Register.
1995 ** ------------------------------*/
1996 typedef union {
1997  struct {
1998  uint8_t d; /* - Z-axis offset value. */
1999 
2000  } b;
2001  uint8_t w;
2002 } MMA845x_OFF_Z_t;
2003 
2004 
2005 /*
2006 ** OFF_Z - Bit field mask definitions
2007 */
2008 #define MMA845x_OFF_Z_D_MASK ((uint8_t) 0xFF)
2009 #define MMA845x_OFF_Z_D_SHIFT ((uint8_t) 0)
2010 
2011 
2012 /*------------------------------*/
2013 
2014 
2015 #endif /* _MMA845x_H_ */
MMA845x_PULSE_SRC_t::axz
uint8_t axz
Definition: mma845x.h:1322
MMA845x_OUT_Y_MSB_t
uint8_t MMA845x_OUT_Y_MSB_t
Definition: mma845x.h:248
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MMA845x_STATUS_t
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MMA845x_OFF_X_t
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uint8_t MMA845x_OUT_X_LSB_t
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