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Memory attribution map after doing handshake

The memory attribution map settings after the handshake procedure is successful between Cortex-M33 and Cortex-A35.

Name	Memory block checker/ Memory region checker (MBC/MRC)	Resulting access level
FLEXSPI1 (alias)	Non Secure	Non Secure	0x5FFF_FFFF
0x5000_0000
FLEXSPI1	Non Secure	Non Secure	0x4FFF_FFFF
0x4000_0000
PBridge1 FlexCAN0 (alias)	Non Secure	Non Secure	0x380A_BFFF
0x380A_8000
PBridge1 SAI0 (alias)	Non Secure	Non Secure	0x3809_C0FF
0x3809_C000
PBridge1 LPUART1 (alias)	Non Secure	Non Secure	0x3809_B02F
0x3809_B000
PBridge1 LPI2C0 (alias)	Non Secure	Non Secure	0x3809_8173
0x3809_8000
PBridge1 FlexSPI1 (alias)	Non Secure	Non Secure	0x3809_22FF
0x3809_2000
PBridge0 LPSPI1 (alias)	Non Secure	Non Secure	0x3803_F7FF
0x3803_F000
PBridge0 FlexIO0 (alias)	Non Secure	Non Secure	0x3803_C91F
0x3803_C000
PBridge0 FlexSPI0 (alias)	Non Secure	Non Secure	0x3803_92FF
0x3803_9000
PBridge1 FlexCAN0	Non Secure	Non Secure	0x280A_BFFF
0x280A_8000
PBridge1 SAI0	Non Secure	Non Secure	0x2809_C0FF
0x2809_C000
PBridge1 LPUART1	Non Secure	Non Secure	0x2809_B02F
0x2809_B000
PBridge1 LPI2C0	Non Secure	Non Secure	0x2809_8173
0x2809_8000
PBridge1 FlexSPI1	Non Secure	Non Secure	0x2809_22FF
0x2809_2000
PBridge0 LPSPI1	Non Secure	Non Secure	0x2803_F7FF
0x2803_F000
PBridge0 FlexIO0	Non Secure	Non Secure	0x2803_C91F
0x2803_C000
PBridge0 FlexSPI0	Non Secure	Non Secure	0x2803_92FF
0x2803_9000
SSRAM P6 (alias)	Non Secure	Non Secure	0x3007_FFFF
0x3006_0000
SSRAM P5 (alias)	Non Secure	Non Secure	0x3005_FFFF
0x3004_0000
SSRAM P4 (alias)	Non Secure	Non Secure	0x3003_FFFF
0x3003_0000
SSRAM P3 (alias)	Non Secure	Non Secure	0x3002_FFFF
0x3002_0000
SSRAM P2 (alias)	Non Secure	Non Secure	0x3001_FFFF
0x3001_0000
SSRAM P1 (alias)	Non Secure	Non Secure	0x3000_FFFF
0x3000_8000
SSRAM P0 (alias)	Non Secure	Non Secure	0x3000_7FFF
0x3000_0000
SSRAM P6	Non Secure	Non Secure	0x2007_FFFF
0x2006_0000
SSRAM P5	Non Secure	Non Secure	0x2005_FFFF
0x2004_0000
SSRAM P4	Non Secure	Non Secure	0x2003_FFFF
0x2003_0000
SSRAM P3	Non Secure	Non Secure	0x2002_FFFF
0x2002_0000
SSRAM P2	Non Secure	Non Secure	0x2001_FFFF
0x2001_0000
SSRAM P1	Non Secure	Non Secure	0x2000_FFFF
0x2000_8000
SSRAM P0	Non Secure	Non Secure	0x2000_7FFF
0x2000_0000
SSRAM P7 (alias)	Non Secure	Non Secure	0x1FFF_FFFF
0x1FFC_0000
FlexSPI0 (alias)	Non Secure	Non Secure	0x1BFF_FFFF
0x1400_0000
SSRAM P7	Non Secure	Non Secure	0x0FFF_FFFF
0x0FFC_0000
FlexSPI0	Non Secure	Non Secure	0x0BFF_FFFF
0x0400_0000

Note:

1. Assign Domain 1 for DMA1, USB0, USB1, ENET, USDHC0, USDHC1, USDHC2, and CAAM Master.

2. The bus attribute for DMA1, USB0, USB1, ENET, USDHC0, USDHC1, and USDHC2 is Non Secure.

3. The bus attribute for CAAM Master is Secure.

4. Security level of MBC/MRC settings of other memory space that are not be shown in the table for Domain 1 are Secure, so master cannot access resources that are controlled by MBC/MRC in other memory spaces when master is in Non Secure state.

|Name|MBC/MRC|Resulting access level| | |—-|:—–:|:——————–:|::| |PBridge1|Non Secure|Non Secure|0x280F_FFFF| |0x2808_0000| |SSRAM P2|Secure|No Access|0x2001FFFF| |0x20018000| |Non Secure|Non Secure|0x20017FFF| |0x20010000|

Note:

1. Assign Domain 1 for DMA1, USB0, USB1, ENET, UDSHC0, USDHC1, UDSHC2, and CAAM Master.

2. Security level of MBC/MRC settings of other memory space that are not shown in the table for Domain 1 are Secure, so the master cannot access resources that are controlled by MBC/MRC in other memory spaces.

|Name|SAU|IDAU|MBC/MRC|Resulting access level| | |—-|—|—-|——-|:——————–:|::| |GPIOC_REGS (alias)|Secure|Secure|Secure|Secure|0x3882_FFFF| |0x3882_0000| |GPIOB_REGS (alias)|Secure|Secure|Secure|Secure|0x3881_FFFF| |0x3881_0000| |GPIOA_REGS (alias)|Secure|Secure|Secure|Secure|0x3880_FFFF| |0x3880_0000| |MICFIL (alias)|Secure|Secure|Secure|Secure|0x3811_10AB| |0x3811_1000| |SAI3 (alias)|Secure|Secure|Secure|Secure|0x3811_00FF| |0x3811_0000| |SAI2 (alias)|Secure|Secure|Secure|Secure|0x3810_F0FF| |0x3810_F000| |LPSPI3 (alias)|Secure|Secure|Secure|Secure|0x3810_E7FF| |0x3810_E000| |LPSPI2 (alias)|Secure|Secure|Secure|Secure|0x3810_D7FF| |0x3810_D000| |LPUART3 (alias)|Secure|Secure|Secure|Secure|0x3810_C02F| |0x3810_C000| |LPUART2 (alias)|Secure|Secure|Secure|Secure|0x3810_B02F| |0x3810_B000| |I3C1 (alias)|Secure|Secure|Secure|Secure|0x3810_AFFF| |0x3810_A000| |LPI2C3 (alias)|Secure|Secure|Secure|Secure|0x3810_9173| |0x3810_9000| |LPI2C2 (alias)|Secure|Secure|Secure|Secure|0x3810_8173| |0x3810_8000| |MRT (alias)|Secure|Secure|Secure|Secure|0x3810_70FF| |0x3810_7000| |TPM3 (alias)|Secure|Secure|Secure|Secure|0x3810_6087| |0x3810_6000| |TPM2 (alias)|Secure|Secure|Secure|Secure|0x3810_5087| |0x3810_5000| |PCC2 (alias)|Secure|Secure|Secure|Secure|0x3810_2047| |0x3810_2000| |WDOG2 (alias)|Secure|Secure|Secure|Secure|0x3810_100F| |0x3810_1000| |MU1_B (alias)|Secure|Secure|Secure|Secure|0x3810_028F| |0x3810_0000| |FlexCAN0 (alias)|Secure|Secure|Secure|Secure|0x380A_BFFF| |0x380A_8000| |ADC1 (alias)|Secure|Secure|Secure|Secure|0x380A_2303| |0x380A_2000| |IOMUXC0 (alias)|Secure|Secure|Secure|Secure|0x380A_1AEB| |0x380A_1000| |SAI1 (alias)|Secure|Secure|Secure|Secure|0x3809_D0FF| |0x3809_D000|

Note:

1. SAU is disabled.

2. Cortex-M33 can access all of the secure resources. All of the resources (the security level of these resources that are controlled by MBC/MRC) are secure when Cortex-M33 is in secure state.

3. Assign domain 6 for Cortex-M33.

Name	MBC/MRC	Resulting access level
PBridge1 IOMUXC0	Non Secure	Non Secure	0x280A_1AEB
0x280A_1000
PBridge1 LPI2C0	Non Secure	Non Secure	0x2809_8173
0x2809_8000
PBridge1 TPM0	Non Secure	Non Secure	0x2809_5087
0x2809_5000
PBridge1 PCC1	Non Secure	Non Secure	0x2809_10BF
0x2809_1000
PBridge0 FlexSPI0	Non Secure	Non Secure	0x2803_92FF
0x2803_9000
PBridge0 SEMA42_0	Non Secure	Non Secure	0x2803_7043
0x2803_7000
PBridge0 CGC0	Non Secure	Non Secure	0x2802_FFFF
0x2802_F000
PBridge0 SIM0-S	Non Secure	Non Secure	0x2802_B3FF
0x2802_B000
S400 MU-AP of EdgeLock secure enclave	Non Secure	Non Secure	0x2702_028C
0x2702_0000
FSB of EdgeLock secure enclave	Non Secure	Non Secure	0x2701_0BFC
0x2701_0000
SSRAM P7	Non Secure	Non Secure	0x1FFF_FFFF
0x1FFF_8000
Secure	Secure	0x1FFF_7FFF
0x1FFC_0000
FlexSPI0	Non Secure	Non Secure	0x0BFF_FFFF
0x0400_0000

Note:

1. Security level of MBC/MRC settings of Other memory space that are not shown in the table for Domain 7 are Secure. The master can access resources that are controlled by MBC/MRC in other memory spaces when the master is in secure state.

2. Assign domain 7 for Cortex-A35.