MCXA153

AOI: Crossbar AND/OR/INVERT Driver

void AOI_Init(AOI_Type *base)

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Index of the event which will be set of type aoi_event_t.
config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Event which will be configured of type aoi_event_t.
eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION: Version 2.0.2.

enum _aoi_input_config

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero: Forces the input to logical zero.

enumerator kAOI_InputSignal: Passes the input signal.

enumerator kAOI_InvInputSignal: Inverts the input signal.

enumerator kAOI_LogicOne: Forces the input to logical one.

enum _aoi_event

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0: Event 0 index

enumerator kAOI_Event1: Event 1 index

enumerator kAOI_Event2: Event 2 index

enumerator kAOI_Event3: Event 3 index

typedef enum _aoi_input_config aoi_input_config_t

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t: AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI: AOI peripheral address

struct _aoi_event_config

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC: Product term 0 input A

aoi_input_config_t PT0BC: Product term 0 input B

aoi_input_config_t PT0CC: Product term 0 input C

aoi_input_config_t PT0DC: Product term 0 input D

aoi_input_config_t PT1AC: Product term 1 input A

aoi_input_config_t PT1BC: Product term 1 input B

aoi_input_config_t PT1CC: Product term 1 input C

aoi_input_config_t PT1DC: Product term 1 input D

aoi_input_config_t PT2AC: Product term 2 input A

aoi_input_config_t PT2BC: Product term 2 input B

aoi_input_config_t PT2CC: Product term 2 input C

aoi_input_config_t PT2DC: Product term 2 input D

aoi_input_config_t PT3AC: Product term 3 input A

aoi_input_config_t PT3BC: Product term 3 input B

aoi_input_config_t PT3CC: Product term 3 input C

aoi_input_config_t PT3DC: Product term 3 input D

CDOG

status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)

Initialize CDOG.

This function initializes CDOG block and setting.

Parameters:

base – CDOG peripheral base address
conf – CDOG configuration structure

Returns:

Status of the init operation

void CDOG_Deinit(CDOG_Type *base)

Deinitialize CDOG.

This function deinitializes CDOG secure counter.

Parameters:

base – CDOG peripheral base address

void CDOG_GetDefaultConfig(cdog_config_t *conf)

Sets the default configuration of CDOG.

This function initialize CDOG config structure to default values.

Parameters:

conf – CDOG configuration structure

void CDOG_Stop(CDOG_Type *base, uint32_t stop)

Stops secure counter and instruction timer.

This function stops instruction timer and secure counter. This also change state od CDOG to IDLE.

Parameters:

base – CDOG peripheral base address
stop – expected value which will be compared with value of secure counter

void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in RELOAD and START registers for instruction timer and secure counter

Parameters:

base – CDOG peripheral base address
reload – reload value
start – start value

void CDOG_Check(CDOG_Type *base, uint32_t check)

Checks secure counter.

This function compares stop value in handler with secure counter value by writting to RELOAD refister.

Parameters:

base – CDOG peripheral base address
check – expected (stop) value

void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in STOP, RELOAD and START registers for instruction timer and secure counter.

Parameters:

base – CDOG peripheral base address
stop – expected value which will be compared with value of secure counter
reload – reload value for instruction timer
start – start value for secure timer

void CDOG_Add(CDOG_Type *base, uint32_t add)

Add value to secure counter.

This function add specified value to secure counter.

Parameters:

base – CDOG peripheral base address.
add – Value to be added.

void CDOG_Add1(CDOG_Type *base)

Add 1 to secure counter.

This function add 1 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Add16(CDOG_Type *base)

Add 16 to secure counter.

This function add 16 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Add256(CDOG_Type *base)

Add 256 to secure counter.

This function add 256 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub(CDOG_Type *base, uint32_t sub)

brief Substract value to secure counter

This function substract specified value to secure counter.

param base CDOG peripheral base address. param sub Value to be substracted.

void CDOG_Sub1(CDOG_Type *base)

Substract 1 from secure counter.

This function substract specified 1 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub16(CDOG_Type *base)

Substract 16 from secure counter.

This function substract specified 16 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub256(CDOG_Type *base)

Substract 256 from secure counter.

This function substract specified 256 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)

Set the CDOG persistent word.

Parameters:

base – CDOG peripheral base address.
value – The value to be written.

uint32_t CDOG_ReadPersistent(CDOG_Type *base)

Get the CDOG persistent word.

Parameters:

base – CDOG peripheral base address.

Returns:

The persistent word.

FSL_CDOG_DRIVER_VERSION

Defines CDOG driver version 2.1.3.

Change log:

Version 2.1.3
- Re-design multiple instance IRQs and Clocks
- Add fix for RESTART command errata
Version 2.1.2
- Support multiple IRQs
- Fix default CONTROL values
Version 2.1.1
- Remove bit CONTROL[CONTROL_CTRL]
Version 2.1.0
- Rename CWT to CDOG
Version 2.0.2
- Fix MISRA-2012 issues
Version 2.0.1
- Fix doxygen issues
Version 2.0.0
- initial version

enum __cdog_debug_Action_ctrl_enum

Values:

enumerator kCDOG_DebugHaltCtrl_Run

enumerator kCDOG_DebugHaltCtrl_Pause

enum __cdog_irq_pause_ctrl_enum

Values:

enumerator kCDOG_IrqPauseCtrl_Run

enumerator kCDOG_IrqPauseCtrl_Pause

enum __cdog_fault_ctrl_enum

Values:

enumerator kCDOG_FaultCtrl_EnableReset

enumerator kCDOG_FaultCtrl_EnableInterrupt

enumerator kCDOG_FaultCtrl_NoAction

enum __code_lock_ctrl_enum

Values:

enumerator kCDOG_LockCtrl_Lock

enumerator kCDOG_LockCtrl_Unlock

typedef uint32_t secure_counter_t

SC_ADD(add)

SC_ADD1

SC_ADD16

SC_ADD256

SC_SUB(sub)

SC_SUB1

SC_SUB16

SC_SUB256

SC_CHECK(val)

struct cdog_config_t: #include <fsl_cdog.h>

Clock Driver

enum _clock_ip_name

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

Values:

enumerator kCLOCK_GateINPUTMUX0: Clock gate name: INPUTMUX0

enumerator kCLOCK_InputMux: Clock gate name: INPUTMUX0

enumerator kCLOCK_GateI3C0: Clock gate name: I3C0

enumerator kCLOCK_GateCTIMER0: Clock gate name: CTIMER0

enumerator kCLOCK_GateCTIMER1: Clock gate name: CTIMER1

enumerator kCLOCK_GateCTIMER2: Clock gate name: CTIMER2

enumerator kCLOCK_GateFREQME: Clock gate name: FREQME

enumerator kCLOCK_GateUTICK0: Clock gate name: UTICK0

enumerator kCLOCK_GateWWDT0: Clock gate name: WWDT0

enumerator kCLOCK_GateDMA: Clock gate name: DMA

enumerator kCLOCK_GateAOI0: Clock gate name: AOI0

enumerator kCLOCK_GateCRC: Clock gate name: CRC

enumerator kCLOCK_Crc0: Clock gate name: CRC

enumerator kCLOCK_GateEIM: Clock gate name: EIM

enumerator kCLOCK_GateERM: Clock gate name: ERM

enumerator kCLOCK_GateLPI2C0: Clock gate name: LPI2C0

enumerator kCLOCK_GateLPSPI0: Clock gate name: LPSPI0

enumerator kCLOCK_GateLPSPI1: Clock gate name: LPSPI1

enumerator kCLOCK_GateLPUART0: Clock gate name: LPUART0

enumerator kCLOCK_GateLPUART1: Clock gate name: LPUART1

enumerator kCLOCK_GateLPUART2: Clock gate name: LPUART2

enumerator kCLOCK_GateUSB0: Clock gate name: USB0

enumerator kCLOCK_GateQDC0: Clock gate name: QDC0

enumerator kCLOCK_GateFLEXPWM0: Clock gate name: FLEXPWM0

enumerator kCLOCK_GateOSTIMER0: Clock gate name: OSTIMER0

enumerator kCLOCK_GateADC0: Clock gate name: ADC0

enumerator kCLOCK_GateCMP0: Clock gate name: CMP0

enumerator kCLOCK_GateCMP1: Clock gate name: CMP1

enumerator kCLOCK_GatePORT0: Clock gate name: PORT0

enumerator kCLOCK_GatePORT1: Clock gate name: PORT1

enumerator kCLOCK_GatePORT2: Clock gate name: PORT2

enumerator kCLOCK_GatePORT3: Clock gate name: PORT3

enumerator kCLOCK_GateATX0: Clock gate name: ATX0

enumerator kCLOCK_GateMTR: Clock gate name: MTR

enumerator kCLOCK_GateTCU: Clock gate name: TCU

enumerator kCLOCK_GateEZRAMC_RAMA: Clock gate name: EZRAMC_RAMA

enumerator kCLOCK_GateGPIO0: Clock gate name: GPIO0

enumerator kCLOCK_GateGPIO1: Clock gate name: GPIO1

enumerator kCLOCK_GateGPIO2: Clock gate name: GPIO2

enumerator kCLOCK_GateGPIO3: Clock gate name: GPIO3

enumerator kCLOCK_GateROMCP: Clock gate name: ROMCP

enumerator kCLOCK_GatePWMSM0: Clock gate name: FlexPWM SM0

enumerator kCLOCK_GatePWMSM1: Clock gate name: FlexPWM SM1

enumerator kCLOCK_GatePWMSM2: Clock gate name: FlexPWM SM2

enumerator kCLOCK_GateNotAvail: Clock gate name: None

enum _clock_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_MainClk: MAIN_CLK

enumerator kCLOCK_CoreSysClk: Core/system clock(CPU_CLK)

enumerator kCLOCK_SYSTEM_CLK: AHB clock

enumerator kCLOCK_BusClk: Bus clock (AHB clock)

enumerator kCLOCK_ExtClk: External Clock

enumerator kCLOCK_FroHf: FRO192

enumerator kCLOCK_FroHfDiv: Divided by FRO192

enumerator kCLOCK_Clk48M: CLK48M

enumerator kCLOCK_Fro12M: FRO12M

enumerator kCLOCK_Clk1M: CLK1M

enumerator kCLOCK_Fro16K: FRO16K

enumerator kCLOCK_Clk16K0: CLK16K[0]

enumerator kCLOCK_Clk16K1: CLK16K[1]

enumerator kCLOCK_SLOW_CLK: SYSTEM_CLK divided by 4

enum _clock_select_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_SelI3C0_FCLK: I3C0_FCLK clock selection

enumerator kCLOCK_SelCTIMER0: CTIMER0 clock selection

enumerator kCLOCK_SelCTIMER1: CTIMER1 clock selection

enumerator kCLOCK_SelCTIMER2: CTIMER2 clock selection

enumerator kCLOCK_SelLPI2C0: LPI2C0 clock selection

enumerator kCLOCK_SelLPSPI0: LPSPI0 clock selection

enumerator kCLOCK_SelLPSPI1: LPSPI1 clock selection

enumerator kCLOCK_SelLPUART0: LPUART0 clock selection

enumerator kCLOCK_SelLPUART1: LPUART1 clock selection

enumerator kCLOCK_SelLPUART2: LPUART2 clock selection

enumerator kCLOCK_SelUSB0: USB0 clock selection

enumerator kCLOCK_SelLPTMR0: LPTMR0 clock selection

enumerator kCLOCK_SelOSTIMER0: OSTIMER0 clock selection

enumerator kCLOCK_SelADC0: ADC0 clock selection

enumerator kCLOCK_SelCMP0_RR: CMP0_RR clock selection

enumerator kCLOCK_SelCMP1_RR: CMP1_RR clock selection

enumerator kCLOCK_SelTRACE: TRACE clock selection

enumerator kCLOCK_SelCLKOUT: CLKOUT clock selection

enumerator kCLOCK_SelSYSTICK: SYSTICK clock selection

enumerator kCLOCK_SelSCGSCS: SCG SCS clock selection

enumerator kCLOCK_SelMax: MAX clock selection

enum _clock_attach_id

The enumerator of clock attach Id.

Values:

enumerator kCLK_IN_to_MAIN_CLK: Attach clk_in to MAIN_CLK.

enumerator kFRO12M_to_MAIN_CLK: Attach FRO_12M to MAIN_CLK.

enumerator kFRO_HF_to_MAIN_CLK: Attach FRO_HF to MAIN_CLK.

enumerator kCLK_16K_to_MAIN_CLK: Attach CLK_16K[1] to MAIN_CLK.

enumerator kNONE_to_MAIN_CLK: Attach NONE to MAIN_CLK.

enumerator kFRO12M_to_I3C0FCLK: Attach FRO12M to I3C0FCLK.

enumerator kFRO_HF_DIV_to_I3C0FCLK: Attach FRO_HF_DIV to I3C0FCLK.

enumerator kCLK_IN_to_I3C0FCLK: Attach CLK_IN to I3C0FCLK.

enumerator kCLK_1M_to_I3C0FCLK: Attach CLK_1M to I3C0FCLK.

enumerator kNONE_to_I3C0FCLK: Attach NONE to I3C0FCLK.

enumerator kFRO12M_to_CTIMER0: Attach FRO12M to CTIMER0.

enumerator kFRO_HF_to_CTIMER0: Attach FRO_HF to CTIMER0.

enumerator kCLK_IN_to_CTIMER0: Attach CLK_IN to CTIMER0.

enumerator kCLK_16K_to_CTIMER0: Attach CLK_16K to CTIMER0.

enumerator kCLK_1M_to_CTIMER0: Attach CLK_1M to CTIMER0.

enumerator kNONE_to_CTIMER0: Attach NONE to CTIMER0.

enumerator kFRO12M_to_CTIMER1: Attach FRO12M to CTIMER1.

enumerator kFRO_HF_to_CTIMER1: Attach FRO_HF to CTIMER1.

enumerator kCLK_IN_to_CTIMER1: Attach CLK_IN to CTIMER1.

enumerator kCLK_16K_to_CTIMER1: Attach CLK_16K to CTIMER1.

enumerator kCLK_1M_to_CTIMER1: Attach CLK_1M to CTIMER1.

enumerator kNONE_to_CTIMER1: Attach NONE to CTIMER1.

enumerator kFRO12M_to_CTIMER2: Attach FRO12M to CTIMER2.

enumerator kFRO_HF_to_CTIMER2: Attach FRO_HF to CTIMER2.

enumerator kCLK_IN_to_CTIMER2: Attach CLK_IN to CTIMER2.

enumerator kCLK_16K_to_CTIMER2: Attach CLK_16K to CTIMER2.

enumerator kCLK_1M_to_CTIMER2: Attach CLK_1M to CTIMER2.

enumerator kNONE_to_CTIMER2: Attach NONE to CTIMER2.

enumerator kFRO12M_to_LPI2C0: Attach FRO12M to LPI2C0.

enumerator kFRO_HF_DIV_to_LPI2C0: Attach FRO_HF_DIV to LPI2C0.

enumerator kCLK_IN_to_LPI2C0: Attach CLK_IN to LPI2C0.

enumerator kCLK_1M_to_LPI2C0: Attach CLK_1M to LPI2C0.

enumerator kNONE_to_LPI2C0: Attach NONE to LPI2C0.

enumerator kFRO12M_to_LPSPI0: Attach FRO12M to LPSPI0.

enumerator kFRO_HF_DIV_to_LPSPI0: Attach FRO_HF_DIV to LPSPI0.

enumerator kCLK_IN_to_LPSPI0: Attach CLK_IN to LPSPI0.

enumerator kCLK_1M_to_LPSPI0: Attach CLK_1M to LPSPI0.

enumerator kNONE_to_LPSPI0: Attach NONE to LPSPI0.

enumerator kFRO12M_to_LPSPI1: Attach FRO12M to LPSPI1.

enumerator kFRO_HF_DIV_to_LPSPI1: Attach FRO_HF_DIV to LPSPI1.

enumerator kCLK_IN_to_LPSPI1: Attach CLK_IN to LPSPI1.

enumerator kCLK_1M_to_LPSPI1: Attach CLK_1M to LPSPI1.

enumerator kNONE_to_LPSPI1: Attach NONE to LPSPI1.

enumerator kFRO12M_to_LPUART0: Attach FRO12M to LPUART0.

enumerator kFRO_HF_DIV_to_LPUART0: Attach FRO_HF_DIV to LPUART0.

enumerator kCLK_IN_to_LPUART0: Attach CLK_IN to LPUART0.

enumerator kCLK_16K_to_LPUART0: Attach CLK_16K to LPUART0.

enumerator kCLK_1M_to_LPUART0: Attach CLK_1M to LPUART0.

enumerator kNONE_to_LPUART0: Attach NONE to LPUART0.

enumerator kFRO12M_to_LPUART1: Attach FRO12M to LPUART1.

enumerator kFRO_HF_DIV_to_LPUART1: Attach FRO_HF_DIV to LPUART1.

enumerator kCLK_IN_to_LPUART1: Attach CLK_IN to LPUART1.

enumerator kCLK_16K_to_LPUART1: Attach CLK_16K to LPUART1.

enumerator kCLK_1M_to_LPUART1: Attach CLK_1M to LPUART1.

enumerator kNONE_to_LPUART1: Attach NONE to LPUART1.

enumerator kFRO12M_to_LPUART2: Attach FRO12M to LPUART2.

enumerator kFRO_HF_DIV_to_LPUART2: Attach FRO_HF_DIV to LPUART2.

enumerator kCLK_IN_to_LPUART2: Attach CLK_IN to LPUART2.

enumerator kCLK_16K_to_LPUART2: Attach CLK_16K to LPUART2.

enumerator kCLK_1M_to_LPUART2: Attach CLK_1M to LPUART2.

enumerator kNONE_to_LPUART2: Attach NONE to LPUART2.

enumerator kCLK_48M_to_USB0: Attach FRO12M to USB0.

enumerator kCLK_IN_to_USB0: Attach CLK_IN to USB0.

enumerator kNONE_to_USB0: Attach NONE to USB0.

enumerator kFRO12M_to_LPTMR0: Attach FRO12M to LPTMR0.

enumerator kFRO_HF_DIV_to_LPTMR0: Attach FRO_HF_DIV to LPTMR0.

enumerator kCLK_IN_to_LPTMR0: Attach CLK_IN to LPTMR0.

enumerator kCLK_1M_to_LPTMR0: Attach CLK_1M to LPTMR0.

enumerator kNONE_to_LPTMR0: Attach NONE to LPTMR0.

enumerator kCLK_16K_to_OSTIMER: Attach FRO16K to OSTIMER0.

enumerator kCLK_1M_to_OSTIMER: Attach CLK_1M to OSTIMER0.

enumerator kNONE_to_OSTIMER: Attach NONE to OSTIMER0.

enumerator kFRO12M_to_ADC0: Attach FRO12M to ADC0.

enumerator kFRO_HF_to_ADC0: Attach FRO_HF to ADC0.

enumerator kCLK_IN_to_ADC0: Attach CLK_IN to ADC0.

enumerator kCLK_1M_to_ADC0: Attach CLK_1M to ADC0.

enumerator kNONE_to_ADC0: Attach NONE to ADC0.

enumerator kFRO12M_to_CMP0: Attach FRO12M to CMP0.

enumerator kFRO_HF_DIV_to_CMP0: Attach FRO_HF_DIV to CMP0.

enumerator kCLK_IN_to_CMP0: Attach CLK_IN to CMP0.

enumerator kCLK_1M_to_CMP0: Attach CLK_1M to CMP0.

enumerator kNONE_to_CMP0: Attach NONE to CMP0.

enumerator kFRO12M_to_CMP1: Attach FRO12M to CMP1.

enumerator kFRO_HF_DIV_to_CMP1: Attach FRO_HF_DIV to CMP1.

enumerator kCLK_IN_to_CMP1: Attach CLK_IN to CMP1.

enumerator kCLK_1M_to_CMP1: Attach CLK_1M to CMP1.

enumerator kNONE_to_CMP1: Attach NONE to CMP1.

enumerator kCPU_CLK_to_TRACE: Attach CPU_CLK to TRACE.

enumerator kCLK_1M_to_TRACE: Attach CLK_1M to TRACE.

enumerator kCLK_16K_to_TRACE: Attach CLK_16K to TRACE.

enumerator kNONE_to_TRACE: Attach NONE to TRACE.

enumerator kFRO12M_to_CLKOUT: Attach FRO12M to CLKOUT.

enumerator kFRO_HF_DIV_to_CLKOUT: Attach FRO_HF_DIV to CLKOUT.

enumerator kCLK_IN_to_CLKOUT: Attach CLK_IN to CLKOUT.

enumerator kCLK_16K_to_CLKOUT: Attach CLK_16K to CLKOUT.

enumerator kSLOW_CLK_to_CLKOUT: Attach SLOW_CLK to CLKOUT.

enumerator kNONE_to_CLKOUT: Attach NONE to CLKOUT.

enumerator kCPU_CLK_to_SYSTICK: Attach CPU_CLK to SYSTICK.

enumerator kCLK_1M_to_SYSTICK: Attach CLK_1M to SYSTICK.

enumerator kCLK_16K_to_SYSTICK: Attach CLK_16K to SYSTICK.

enumerator kNONE_to_SYSTICK: Attach NONE to SYSTICK.

enumerator kNONE_to_NONE: Attach NONE to NONE.

enum _clock_div_name

Clock dividers.

Values:

enumerator kCLOCK_DivI3C0_FCLK: I3C0_FCLK clock divider

enumerator kCLOCK_DivCTIMER0: CTIMER0 clock divider

enumerator kCLOCK_DivCTIMER1: CTIMER1 clock divider

enumerator kCLOCK_DivCTIMER2: CTIMER2 clock divider

enumerator kCLOCK_DivWWDT0: WWDT0 clock divider

enumerator kCLOCK_DivLPI2C0: LPI2C0 clock divider

enumerator kCLOCK_DivLPSPI0: LPSPI0 clock divider

enumerator kCLOCK_DivLPSPI1: LPSPI1 clock divider

enumerator kCLOCK_DivLPUART0: LPUART0 clock divider

enumerator kCLOCK_DivLPUART1: LPUART1 clock divider

enumerator kCLOCK_DivLPUART2: LPUART2 clock divider

enumerator kCLOCK_DivLPTMR0: LPTMR0 clock divider

enumerator kCLOCK_DivADC0: ADC0 clock divider

enumerator kCLOCK_DivCMP0_FUNC: CMP0_FUNC clock divider

enumerator kCLOCK_DivCMP0_RR: CMP0_RR clock divider

enumerator kCLOCK_DivCMP1_FUNC: CMP1_FUNC clock divider

enumerator kCLOCK_DivCMP1_RR: CMP1_RR clock divider

enumerator kCLOCK_DivTRACE: TRACE clock divider

enumerator kCLOCK_DivCLKOUT: CLKOUT clock divider

enumerator kCLOCK_DivSYSTICK: SYSTICK clock divider

enumerator kCLOCK_DivFRO_HF_DIV: FRO_HF_DIV clock divider

enumerator kCLOCK_DivSLOWCLK: SLOWCLK clock divider

enumerator kCLOCK_DivAHBCLK: System clock divider

enumerator kCLOCK_DivMax: MAX clock divider

enum _firc_trim_mode

firc trim mode.

Values:

enumerator kSCG_FircTrimNonUpdate: Trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure firc_trim_config_t.

enumerator kSCG_FircTrimUpdate: Trim enable and trim value update enable. In this mode, the trim value is auto update.

enum _firc_trim_src

firc trim source.

Values:

enumerator kSCG_FircTrimSrcUsb0: USB0 start of frame (1kHz).

enumerator kSCG_FircTrimSrcSysOsc: System OSC.

enum _sirc_trim_mode

sirc trim mode.

Values:

enumerator kSCG_SircTrimNonUpdate: Trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure sirc_trim_config_t.

enumerator kSCG_SircTrimUpdate: Trim enable and trim value update enable. In this mode, the trim value is auto update.

enum _sirc_trim_src

sirc trim source.

Values:

enumerator kNoTrimSrc: No external tirm source.

enumerator kSCG_SircTrimSrcSysOsc: System OSC.

enum _scg_sosc_monitor_mode

SCG system OSC monitor mode.

Values:

enumerator kSCG_SysOscMonitorDisable: Monitor disabled.

enumerator kSCG_SysOscMonitorInt: Interrupt when the SOSC error is detected.

enumerator kSCG_SysOscMonitorReset: Reset when the SOSC error is detected.

enum _clke_16k

firc trim source.

Values:

enumerator kCLKE_16K_SYSTEM: To VSYS domain.

enumerator kCLKE_16K_COREMAIN: To VDD_CORE domain.

typedef enum _clock_ip_name clock_ip_name_t: Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

typedef enum _clock_name clock_name_t: Clock name used to get clock frequency.

typedef enum _clock_select_name clock_select_name_t: Clock name used to get clock frequency.

typedef enum _clock_attach_id clock_attach_id_t: The enumerator of clock attach Id.

typedef enum _clock_div_name clock_div_name_t: Clock dividers.

typedef enum _firc_trim_mode firc_trim_mode_t: firc trim mode.

typedef enum _firc_trim_src firc_trim_src_t: firc trim source.

typedef struct _firc_trim_config firc_trim_config_t: firc trim configuration.

typedef enum _sirc_trim_mode sirc_trim_mode_t: sirc trim mode.

typedef enum _sirc_trim_src sirc_trim_src_t: sirc trim source.

typedef struct _sirc_trim_config sirc_trim_config_t: sirc trim configuration.

typedef enum _scg_sosc_monitor_mode scg_sosc_monitor_mode_t: SCG system OSC monitor mode.

typedef enum _clke_16k clke_16k_t: firc trim source.

static inline void CLOCK_EnableClock(clock_ip_name_t clk)

Enable the clock for specific IP.

Parameters:

clk – : Clock to be enabled.

Returns:

Nothing

static inline void CLOCK_DisableClock(clock_ip_name_t clk)

Disable the clock for specific IP.

Parameters:

clk – : Clock to be Disabled.

Returns:

Nothing

void CLOCK_AttachClk(clock_attach_id_t connection)

Configure the clock selection muxes.

Parameters:

connection – : Clock to be configured.

Returns:

Nothing

clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection)

Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id.

Parameters:

connection – : Clock attach id to get.

Returns:

Clock source value.

void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value)

Set the clock select value. This fuction set the peripheral clock select value.

Parameters:

sel_name – : Clock select.
value – : value to be set.

uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name)

Get the clock select value. This fuction get the peripheral clock select value.

Parameters:

sel_name – : Clock select.

Returns:

Clock source value.

void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value)

Setup peripheral clock dividers.

Parameters:

div_name – : Clock divider name
value – : Value to be divided

Returns:

Nothing

uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name)

Get peripheral clock dividers.

Parameters:

div_name – : Clock divider name

Returns:

peripheral clock dividers

void CLOCK_HaltClockDiv(clock_div_name_t div_name)

Halt peripheral clock dividers.

Parameters:

div_name – : Clock divider name

Returns:

Nothing

status_t CLOCK_SetupFROHFClocking(uint32_t iFreq)

Initialize the FROHF to given frequency (48,64,96,192). This function turns on FIRC and select the given frequency as the source of fro_hf.

Parameters:

iFreq – : Desired frequency.

Returns:

returns success or fail status.

status_t CLOCK_SetupFRO12MClocking(void)

Initialize the FRO12M. This function turns on FRO12M.

Returns:: returns success or fail status.

status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)

Initialize the FRO16K. This function turns on FRO16K.

Parameters:

clk_16k_enable_mask – 0-3 0b00: disable both clk_16k0 and clk_16k1 0b01: only enable clk_16k0 0b10: only enable clk_16k1 0b11: enable both clk_16k0 and clk_16k1

Returns:

returns success or fail status.

status_t CLOCK_SetupExtClocking(uint32_t iFreq)

Initialize the external osc clock to given frequency.

Parameters:

iFreq – : Desired frequency (must be equal to exact rate in Hz)

Returns:

returns success or fail status.

status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)

Initialize the external reference clock to given frequency.

Parameters:

iFreq – : Desired frequency (must be equal to exact rate in Hz)

Returns:

returns success or fail status.

uint32_t CLOCK_GetFreq(clock_name_t clockName)

Return Frequency of selected clock.

Returns:: Frequency of selected clock

uint32_t CLOCK_GetCoreSysClkFreq(void)

Return Frequency of core.

Returns:: Frequency of the core

uint32_t CLOCK_GetI3CFClkFreq(void)

Return Frequency of I3C FCLK.

Returns:: Frequency of I3C FCLK.

uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)

Return Frequency of CTimer functional Clock.

Returns:: Frequency of CTimer functional Clock

uint32_t CLOCK_GetLpi2cClkFreq(void)

Return Frequency of LPI2C0 functional Clock.

Returns:: Frequency of LPI2C0 functional Clock

uint32_t CLOCK_GetLpspiClkFreq(uint32_t id)

Return Frequency of LPSPI functional Clock.

Returns:: Frequency of LPSPI functional Clock

uint32_t CLOCK_GetLpuartClkFreq(uint32_t id)

Return Frequency of LPUART functional Clock.

Returns:: Frequency of LPUART functional Clock

uint32_t CLOCK_GetLptmrClkFreq(void)

Return Frequency of LPTMR functional Clock.

Returns:: Frequency of LPTMR functional Clock

uint32_t CLOCK_GetOstimerClkFreq(void)

Return Frequency of OSTIMER.

Returns:: Frequency of OSTIMER Clock

uint32_t CLOCK_GetAdcClkFreq(void)

Return Frequency of Adc Clock.

Returns:: Frequency of Adc.

uint32_t CLOCK_GetCmpFClkFreq(uint32_t id)

Return Frequency of CMP Function Clock.

Returns:: Frequency of CMP Function.

uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id)

Return Frequency of CMP Round Robin Clock.

Returns:: Frequency of CMP Round Robin.

uint32_t CLOCK_GetTraceClkFreq(void)

Return Frequency of Trace Clock.

Returns:: Frequency of Trace.

uint32_t CLOCK_GetClkoutClkFreq(void)

Return Frequency of CLKOUT Clock.

Returns:: Frequency of CLKOUT.

uint32_t CLOCK_GetSystickClkFreq(void)

Return Frequency of Systick Clock.

Returns:: Frequency of Systick.

uint32_t CLOCK_GetWwdtClkFreq(void): brief Return Frequency of Systick Clock return Frequency of Systick.

status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config)

Setup FROHF trim.

Parameters:

config – : FROHF trim value

Returns:

returns success or fail status.

status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config)

Setup FRO 12M trim.

Parameters:

config – : FRO 12M trim value

Returns:

returns success or fail status.

void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)

Sets the system OSC monitor mode.

This function sets the system OSC monitor mode. The mode can be disabled, it can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters:

mode – Monitor mode to set.

bool CLOCK_EnableUsbfsClock(void): brief Enable USB FS clock. Enable USB Full Speed clock.

FSL_CLOCK_DRIVER_VERSION: CLOCK driver version 2.0.0.

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

CLK_GATE_REG_OFFSET(value): Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

CLK_GATE_BIT_SHIFT(value)

REG_PWM0SUBCTL

AOI_CLOCKS: Clock ip name array for AOI.

CRC_CLOCKS: Clock ip name array for CRC.

CTIMER_CLOCKS: Clock ip name array for CTIMER.

DMA_CLOCKS: Clock ip name array for DMA.

EDMA_CLOCKS: Clock gate name array for EDMA.

ERM_CLOCKS: Clock ip name array for ERM.

EIM_CLOCKS: Clock ip name array for EIM.

FREQME_CLOCKS: Clock ip name array for FREQME.

GPIO_CLOCKS: Clock ip name array for GPIO.

I3C_CLOCKS: Clock ip name array for I3C.

INPUTMUX_CLOCKS: Clock ip name array for INPUTMUX.

LPCMP_CLOCKS: Clock ip name array for GPIO.

LPADC_CLOCKS: Clock ip name array for LPADC.

LPUART_CLOCKS: Clock ip name array for LPUART.

LPI2C_CLOCKS: Clock ip name array for LPI2C.

LPSPI_CLOCKS: Clock ip name array for LSPI.

MTR_CLOCKS: Clock ip name array for MTR.

OSTIMER_CLOCKS: Clock ip name array for OSTIMER.

PWM_CLOCKS: Clock ip name array for PWM.

QDC_CLOCKS: Clock ip name array for QDC.

UTICK_CLOCKS: Clock ip name array for UTICK.

WWDT_CLOCKS: Clock ip name array for WWDT.

BUS_CLK: Peripherals clock source definition.

CLK_ATTACH_REG_OFFSET(value)

Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards.

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

CLK_ATTACH_CLK_SEL(value)

CLK_ATTACH_MUX(reg, sel)

firc_trim_mode_t trimMode: Trim mode.

firc_trim_src_t trimSrc: Trim source.

uint16_t trimDiv: Divider of SOSC.

uint8_t trimCoar: Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate.

uint8_t trimFine: Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate.

sirc_trim_mode_t trimMode: Trim mode.

sirc_trim_src_t trimSrc: Trim source.

uint16_t trimDiv: Divider of SOSC.

uint8_t cltrim: Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate.

uint8_t ccotrim: Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate.

struct _firc_trim_config: #include <fsl_clock.h>

firc trim configuration.

struct _sirc_trim_config: #include <fsl_clock.h>

sirc trim configuration.

CRC: Cyclic Redundancy Check Driver

FSL_CRC_DRIVER_VERSION

CRC driver version. Version 2.0.4.

Current version: 2.0.4

Change log:

Version 2.0.4
- Release peripheral from reset if necessary in init function.
Version 2.0.3
- Fix MISRA issues
Version 2.0.2
- Fix MISRA issues
Version 2.0.1
- move DATA and DATALL macro definition from header file to source file

enum _crc_bits

CRC bit width.

Values:

enumerator kCrcBits16: Generate 16-bit CRC code

enumerator kCrcBits32: Generate 32-bit CRC code

enum _crc_result

CRC result type.

Values:

enumerator kCrcFinalChecksum: CRC data register read value is the final checksum. Reflect out and final xor protocol features are applied.

enumerator kCrcIntermediateChecksum: CRC data register read value is intermediate checksum (raw value). Reflect out and final xor protocol feature are not applied. Intermediate checksum can be used as a seed for CRC_Init() to continue adding data to this checksum.

typedef enum _crc_bits crc_bits_t: CRC bit width.

typedef enum _crc_result crc_result_t: CRC result type.

typedef struct _crc_config crc_config_t

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

void CRC_Init(CRC_Type *base, const crc_config_t *config)

Enables and configures the CRC peripheral module.

This function enables the clock gate in the SIM module for the CRC peripheral. It also configures the CRC module and starts a checksum computation by writing the seed.

Parameters:

base – CRC peripheral address.
config – CRC module configuration structure.

static inline void CRC_Deinit(CRC_Type *base)

Disables the CRC peripheral module.

This function disables the clock gate in the SIM module for the CRC peripheral.

Parameters:

base – CRC peripheral address.

void CRC_GetDefaultConfig(crc_config_t *config)

Loads default values to the CRC protocol configuration structure.

Loads default values to the CRC protocol configuration structure. The default values are as follows.

config->polynomial = 0x1021;
config->seed = 0xFFFF;
config->reflectIn = false;
config->reflectOut = false;
config->complementChecksum = false;
config->crcBits = kCrcBits16;
config->crcResult = kCrcFinalChecksum;

Parameters:

config – CRC protocol configuration structure.

void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)

Writes data to the CRC module.

Writes input data buffer bytes to the CRC data register. The configured type of transpose is applied.

Parameters:

base – CRC peripheral address.
data – Input data stream, MSByte in data[0].
dataSize – Size in bytes of the input data buffer.

uint32_t CRC_Get32bitResult(CRC_Type *base)

Reads the 32-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 32-bit checksum, after configured transpose and complement operations.

uint16_t CRC_Get16bitResult(CRC_Type *base)

Reads a 16-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 16-bit checksum, after configured transpose and complement operations.

CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT: Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault.

struct _crc_config

#include <fsl_crc.h>

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

Public Members

uint32_t polynomial: CRC Polynomial, MSBit first. Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1

uint32_t seed: Starting checksum value

bool reflectIn: Reflect bits on input.

bool reflectOut: Reflect bits on output.

bool complementChecksum: True if the result shall be complement of the actual checksum.

crc_bits_t crcBits: Selects 16- or 32- bit CRC protocol.

crc_result_t crcResult: Selects final or intermediate checksum return from CRC_Get16bitResult() or CRC_Get32bitResult()

CTIMER: Standard counter/timers

void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)

Ungates the clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application before using the driver.

Parameters:

base – Ctimer peripheral base address
config – Pointer to the user configuration structure.

void CTIMER_Deinit(CTIMER_Type *base)

Gates the timer clock.

Parameters:

base – Ctimer peripheral base address

void CTIMER_GetDefaultConfig(ctimer_config_t *config)

Fills in the timers configuration structure with the default settings.

The default values are:

config->mode = kCTIMER_TimerMode;
config->input = kCTIMER_Capture_0;
config->prescale = 0;

Parameters:

config – Pointer to the user configuration structure.

status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM period

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
pwmPeriod – PWM period match value
pulsePeriod – Pulse width match value
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

Returns:

kStatus_Success on success kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle If PWM pulse width register value is larger than 0xFFFFFFFF.

status_t CTIMER_SetupPwm(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – PWM pulse width; the value should be between 0 to 100
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – Timer counter clock in Hz
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)

Updates the pulse period of an active PWM signal.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match pin to be used to output the PWM signal
pulsePeriod – New PWM pulse width match value

status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)

Updates the duty cycle of an active PWM signal.

Note

Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. This function can manually assign the specified channel to set the PWM cycle.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – New PWM pulse width; the value should be between 0 to 100

Returns:

kStatus_Success on success kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF.

static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)

Enables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)

Disables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)

Gets the enabled Timer interrupts.

Parameters:

base – Ctimer peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)

Gets the Timer status flags.

Parameters:

base – Ctimer peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)

Clears the Timer status flags.

Parameters:

base – Ctimer peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_StartTimer(CTIMER_Type *base)

Starts the Timer counter.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_StopTimer(CTIMER_Type *base)

Stops the Timer counter.

Parameters:

base – Ctimer peripheral base address

FSL_CTIMER_DRIVER_VERSION: Version 2.3.3

enum _ctimer_capture_channel

List of Timer capture channels.

Values:

enumerator kCTIMER_Capture_0: Timer capture channel 0

enumerator kCTIMER_Capture_1: Timer capture channel 1

enumerator kCTIMER_Capture_3: Timer capture channel 3

enum _ctimer_capture_edge

List of capture edge options.

Values:

enumerator kCTIMER_Capture_RiseEdge: Capture on rising edge

enumerator kCTIMER_Capture_FallEdge: Capture on falling edge

enumerator kCTIMER_Capture_BothEdge: Capture on rising and falling edge

enum _ctimer_match

List of Timer match registers.

Values:

enumerator kCTIMER_Match_0: Timer match register 0

enumerator kCTIMER_Match_1: Timer match register 1

enumerator kCTIMER_Match_2: Timer match register 2

enumerator kCTIMER_Match_3: Timer match register 3

enum _ctimer_external_match

List of external match.

Values:

enumerator kCTIMER_External_Match_0: External match 0

enumerator kCTIMER_External_Match_1: External match 1

enumerator kCTIMER_External_Match_2: External match 2

enumerator kCTIMER_External_Match_3: External match 3

enum _ctimer_match_output_control

List of output control options.

Values:

enumerator kCTIMER_Output_NoAction: No action is taken

enumerator kCTIMER_Output_Clear: Clear the EM bit/output to 0

enumerator kCTIMER_Output_Set: Set the EM bit/output to 1

enumerator kCTIMER_Output_Toggle: Toggle the EM bit/output

enum _ctimer_timer_mode

List of Timer modes.

Values:

enumerator kCTIMER_TimerMode

enumerator kCTIMER_IncreaseOnRiseEdge

enumerator kCTIMER_IncreaseOnFallEdge

enumerator kCTIMER_IncreaseOnBothEdge

enum _ctimer_interrupt_enable

List of Timer interrupts.

Values:

enumerator kCTIMER_Match0InterruptEnable: Match 0 interrupt

enumerator kCTIMER_Match1InterruptEnable: Match 1 interrupt

enumerator kCTIMER_Match2InterruptEnable: Match 2 interrupt

enumerator kCTIMER_Match3InterruptEnable: Match 3 interrupt

enum _ctimer_status_flags

List of Timer flags.

Values:

enumerator kCTIMER_Match0Flag: Match 0 interrupt flag

enumerator kCTIMER_Match1Flag: Match 1 interrupt flag

enumerator kCTIMER_Match2Flag: Match 2 interrupt flag

enumerator kCTIMER_Match3Flag: Match 3 interrupt flag

enum ctimer_callback_type_t

Callback type when registering for a callback. When registering a callback an array of function pointers is passed the size could be 1 or 8, the callback type will tell that.

Values:

enumerator kCTIMER_SingleCallback: Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently

enumerator kCTIMER_MultipleCallback: Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture

typedef enum _ctimer_capture_channel ctimer_capture_channel_t: List of Timer capture channels.

typedef enum _ctimer_capture_edge ctimer_capture_edge_t: List of capture edge options.

typedef enum _ctimer_match ctimer_match_t: List of Timer match registers.

typedef enum _ctimer_external_match ctimer_external_match_t: List of external match.

typedef enum _ctimer_match_output_control ctimer_match_output_control_t: List of output control options.

typedef enum _ctimer_timer_mode ctimer_timer_mode_t: List of Timer modes.

typedef enum _ctimer_interrupt_enable ctimer_interrupt_enable_t: List of Timer interrupts.

typedef enum _ctimer_status_flags ctimer_status_flags_t: List of Timer flags.

typedef void (*ctimer_callback_t)(uint32_t flags)

typedef struct _ctimer_match_config ctimer_match_config_t

Match configuration.

This structure holds the configuration settings for each match register.

typedef struct _ctimer_config ctimer_config_t

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)

Setup the match register.

User configuration is used to setup the match value and action to be taken when a match occurs.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match register to configure
config – Pointer to the match configuration structure

uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)

Get the status of output match.

This function gets the status of output MAT, whether or not this output is connected to a pin. This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

Parameters:

base – Ctimer peripheral base address
matchChannel – External match channel, user can obtain the status of multiple match channels at the same time by using the logic of “|” enumeration ctimer_external_match_t

Returns:

The mask of external match channel status flags. Users need to use the _ctimer_external_match type to decode the return variables.

void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, ctimer_capture_edge_t edge, bool enableInt)

Setup the capture.

Parameters:

base – Ctimer peripheral base address
capture – Capture channel to configure
edge – Edge on the channel that will trigger a capture
enableInt – Flag to enable channel interrupts, if enabled then the registered call back is called upon capture

static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)

Get the timer count value from TC register.

Parameters:

base – Ctimer peripheral base address.

Returns:

return the timer count value.

void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)

Register callback.

Parameters:

base – Ctimer peripheral base address
cb_func – callback function
cb_type – callback function type, singular or multiple

static inline void CTIMER_Reset(CTIMER_Type *base)

Reset the counter.

The timer counter and prescale counter are reset on the next positive edge of the APB clock.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale)

Setup the timer prescale value.

Specifies the maximum value for the Prescale Counter.

Parameters:

base – Ctimer peripheral base address
prescale – Prescale value

static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture)

Get capture channel value.

Get the counter/timer value on the corresponding capture channel.

Parameters:

base – Ctimer peripheral base address
capture – Select capture channel

Returns:

The timer count capture value.

static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable reset match channel.

Set the specified match channel reset operation.

Parameters:

base – Ctimer peripheral base address
match – match channel used
enable – Enable match channel reset operation.

static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable stop match channel.

Set the specified match channel stop operation.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
enable – Enable match channel stop operation.

static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable reload channel falling edge.

Enable the specified match channel reload match shadow value.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
enable – Enable .

static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel rising edge.

Sets the specified capture channel for rising edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable rising edge capture.

static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel falling edge.

Sets the specified capture channel for falling edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable falling edge capture.

static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue)

Set the specified match shadow channel.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
matchvalue – Reload the value of the corresponding match register.

struct _ctimer_match_config

#include <fsl_ctimer.h>

Match configuration.

This structure holds the configuration settings for each match register.

Public Members

uint32_t matchValue: This is stored in the match register

bool enableCounterReset: true: Match will reset the counter false: Match will not reser the counter

bool enableCounterStop: true: Match will stop the counter false: Match will not stop the counter

ctimer_match_output_control_t outControl: Action to be taken on a match on the EM bit/output

bool outPinInitState: Initial value of the EM bit/output

bool enableInterrupt: true: Generate interrupt upon match false: Do not generate interrupt on match

struct _ctimer_config

#include <fsl_ctimer.h>

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

Public Members

ctimer_timer_mode_t mode: Timer mode

ctimer_capture_channel_t input: Input channel to increment the timer, used only in timer modes that rely on this input signal to increment TC

uint32_t prescale: Prescale value

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)

EDMA Channel initialization.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)

Set channel memory attribute.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)

Set channel sign extension.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)

Set channel swap size.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)

Set channel access type.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)

Set channel request source.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)

Gets the channel identification and attribute information on the system bus interface.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)

Set channel master ID replication.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an async request for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

submit single transfer

edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit static link transfer,

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

submit dynamic link transfer

edma_tcd_t tcdpool[2];
EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit loop transfer

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

handle – eDMA handle pointer.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.10.4.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull: TCD queue is full.

enumerator kStatus_EDMA_Busy: Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes: Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes: Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes: Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes: Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes: Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes: Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes: Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes: Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable: Disable modulo

enumerator kEDMA_Modulo2bytes: Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes: Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes: Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes: Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes: Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes: Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes: Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes: Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes: Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes: Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes: Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes: Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes: Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes: Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes: Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes: Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes: Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes: Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes: Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes: Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes: Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes: Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes: Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes: Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes: Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes: Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes: Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes: Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes: Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes: Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes: Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone: No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle: eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle: eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone: No channel link

enumerator kEDMA_MinorLink: Channel link after each minor loop

enumerator kEDMA_MajorLink: Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag: DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag: eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag: eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag: Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag: Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag: Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag: NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag: Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag: Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag: Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag: Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag: Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag: Transfer cancelled

enumerator kEDMA_ValidFlag: No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable: Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable: Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable: Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory: Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory: Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral: Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral: Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer: No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable: No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer: No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable: No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer: No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable: No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer: No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable: No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer: write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable: write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer: write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable: write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer: write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable: write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer: write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable: write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled: Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap: Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap: Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap: Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap: Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap: Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap: Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel: Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId: DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess: Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess: Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser: user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged: Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t: eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t: eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t: Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t: Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t: eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t: eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t: eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t: eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t: eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t: eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t: eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t: eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

typedef struct _edma_config edma_config_t: eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:: EDMA handle pointer, users shall not touch the values inside.
Param userData:: The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
Param transferDone:: If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
Param tcds:: How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t: eDMA transfer handle structure

FSL_EDMA_DRIVER_EDMA4: eDMA driver name

EDMA_ALLOCATE_TCD(name, number): Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel): Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption: If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility: If true: a channel can suspend other channel with low priority

uint8_t channelPriority: Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset: Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset: Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset: Offset for a minor loop mapping.

struct _edma_channel_config

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig: channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute: channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute: channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize: channel swap size configuration

edma_channel_access_type_t channelAccessType: channel access type configuration

uint8_t channelDataSignExtensionBitPosition: channel data sign extension bit psition configuration

uint32_t channelRequestSource: hardware service request source for the channel

bool enableMasterIDReplication: enable master ID replication

edma_channel_protection_level_t protectionLevel: protection level

struct _edma_transfer_config

#include <fsl_edma.h>

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

Public Members

uint32_t srcAddr: Source data address.

uint32_t destAddr: Destination data address.

edma_transfer_size_t srcTransferSize: Source data transfer size.

edma_transfer_size_t destTransferSize: Destination data transfer size.

int16_t srcOffset: Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset: Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes: bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts: minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask: channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo: source circular data queue range

int32_t srcMajorLoopOffset: source major loop offset

edma_modulo_t dstAddrModulo: destination circular data queue range

int32_t dstMajorLoopOffset: destination major loop offset

bool enableSrcMinorLoopOffset: enable source minor loop offset

bool enableDstMinorLoopOffset: enable dest minor loop offset

int32_t minorLoopOffset: burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink: channel link when major loop complete

uint32_t majorLoopLinkChannel: major loop link channel number

bool enableChannelMinorLoopLink: channel link when minor loop complete

uint32_t minorLoopLinkChannel: minor loop link channel number

edma_tcd_t *linkTCD: pointer to the link transfer control descriptor

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableMasterIdReplication: Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink: Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError: Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode: Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration: Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]: channel preemption configuration

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback: Callback function for major count exhausted.

void *userData: Callback function parameter.

EDMA_ChannelType *channelBase: eDMA peripheral channel base address.

EDMA_Type *base: eDMA peripheral base address

EDMA_TCDType *tcdBase: eDMA peripheral tcd base address.

edma_tcd_t *tcdPool: Pointer to memory stored TCDs.

uint32_t channel: eDMA channel number.

volatile int8_t header: The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail: The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed: The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize: The total number of TCD slots in the queue.

eDMA core Driver

enum _edma_tcd_type

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag: Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag: Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t: edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t: edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t: eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t: edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t: edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t: edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType: EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType

typedef void EDMA_Type

DMA_CORE_MP_CSR_EDBG_MASK

DMA_CORE_MP_CSR_ERCA_MASK

DMA_CORE_MP_CSR_HAE_MASK

DMA_CORE_MP_CSR_HALT_MASK

DMA_CORE_MP_CSR_GCLC_MASK

DMA_CORE_MP_CSR_GMRC_MASK

DMA_CORE_MP_CSR_EDBG(x)

DMA_CORE_MP_CSR_ERCA(x)

DMA_CORE_MP_CSR_HAE(x)

DMA_CORE_MP_CSR_HALT(x)

DMA_CORE_MP_CSR_GCLC(x)

DMA_CORE_MP_CSR_GMRC(x)

DMA_CSR_INTMAJOR_MASK

DMA_CSR_INTHALF_MASK

DMA_CSR_DREQ_MASK

DMA_CSR_ESG_MASK

DMA_CSR_BWC_MASK

DMA_CSR_BWC(x)

DMA_CSR_START_MASK

DMA_CITER_ELINKNO_CITER_MASK

DMA_BITER_ELINKNO_BITER_MASK

DMA_CITER_ELINKNO_CITER_SHIFT

DMA_CITER_ELINKYES_CITER_MASK

DMA_CITER_ELINKYES_CITER_SHIFT

DMA_ATTR_SMOD_MASK

DMA_ATTR_DMOD_MASK

DMA_CITER_ELINKNO_ELINK_MASK

DMA_CSR_MAJORELINK_MASK

DMA_BITER_ELINKYES_ELINK_MASK

DMA_CITER_ELINKYES_ELINK_MASK

DMA_CSR_MAJORLINKCH_MASK

DMA_BITER_ELINKYES_LINKCH_MASK

DMA_CITER_ELINKYES_LINKCH_MASK

DMA_NBYTES_MLOFFYES_MLOFF_MASK

DMA_NBYTES_MLOFFYES_DMLOE_MASK

DMA_NBYTES_MLOFFYES_SMLOE_MASK

DMA_NBYTES_MLOFFNO_NBYTES_MASK

DMA_ATTR_DMOD(x)

DMA_ATTR_SMOD(x)

DMA_BITER_ELINKYES_LINKCH(x)

DMA_CITER_ELINKYES_LINKCH(x)

DMA_NBYTES_MLOFFYES_MLOFF(x)

DMA_NBYTES_MLOFFYES_DMLOE(x)

DMA_NBYTES_MLOFFYES_SMLOE(x)

DMA_NBYTES_MLOFFNO_NBYTES(x)

DMA_NBYTES_MLOFFYES_NBYTES(x)

DMA_ATTR_DSIZE(x)

DMA_ATTR_SSIZE(x)

DMA_CSR_DREQ(x)

DMA_CSR_MAJORLINKCH(x)

DMA_CH_MATTR_WCACHE(x)

DMA_CH_MATTR_RCACHE(x)

DMA_CH_CSR_SIGNEXT_MASK

DMA_CH_CSR_SIGNEXT_SHIFT

DMA_CH_CSR_SWAP_MASK

DMA_CH_CSR_SWAP_SHIFT

DMA_CH_SBR_INSTR_MASK

DMA_CH_SBR_INSTR_SHIFT

DMA_CH_MUX_SOURCE(x)

DMA_ERR_DBE_FLAG: DMA error flag.

DMA_ERR_SBE_FLAG

DMA_ERR_SGE_FLAG

DMA_ERR_NCE_FLAG

DMA_ERR_DOE_FLAG

DMA_ERR_DAE_FLAG

DMA_ERR_SOE_FLAG

DMA_ERR_SAE_FLAG

DMA_ERR_ERRCHAN_FLAG

DMA_ERR_ECX_FLAG

DMA_ERR_FLAG

DMA_CLEAR_DONE_STATUS(base, channel): get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)

DMA_ENABLE_ERROR_INT(base, channel): enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)

DMA_CLEAR_ERROR_STATUS(base, channel): get/clear error status

DMA_GET_ERROR_STATUS(base, channel)

DMA_CLEAR_INT_STATUS(base, channel): get/clear INT status

DMA_GET_INT_STATUS(base, channel)

DMA_ENABLE_MAJOR_INT(base, channel): enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)

DMA_DISABLE_MAJOR_INT(base, channel)

DMA_DISABLE_HALF_INT(base, channel)

EDMA_TCD_ALIGN_SIZE: EDMA tcd align size.

EDMA_CORE_BASE(base): EDMA base address convert macro.

EDMA_MP_BASE(base)

EDMA_CHANNEL_BASE(base, channel)

EDMA_TCD_BASE(base, channel)

EDMA_TCD_TYPE(x): EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag): EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)

EDMA_TCD_ATTR(tcd, flag)

EDMA_TCD_NBYTES(tcd, flag)

EDMA_TCD_SLAST(tcd, flag)

EDMA_TCD_DADDR(tcd, flag)

EDMA_TCD_DOFF(tcd, flag)

EDMA_TCD_CITER(tcd, flag)

EDMA_TCD_DLAST_SGA(tcd, flag)

EDMA_TCD_CSR(tcd, flag)

EDMA_TCD_BITER(tcd, flag)

struct _edma_core_mp

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT: Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR: Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI: Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint32_t SADDR_HIGH: SADDR HIGH register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t SLAST_SDA_HIGH: SLAST SDA HIGH register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint32_t DADDR_HIGH: DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH: DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

uint8_t RESERVED[16]: Aligned 64 bytes

struct _edma4_core_tcd

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

struct _edma_core_tcd: #include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS

Public Members

struct _edma_core_mp EDMA5_REG

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW: Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH: Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW: Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH: Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH: Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW: Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH: Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]: Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]: Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]: Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS

Public Members

struct _edma_core_channel EDMA5_REG

struct _edma_core_channel EDMA4_REG

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX: Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS

Public Members

edma4_core_tcd_t edma4_tcd

eDMA soc Driver

FSL_EDMA_SOC_DRIVER_VERSION: Driver version 2.0.0.

FSL_EDMA_SOC_IP_DMA3: DMA IP version.

FSL_EDMA_SOC_IP_DMA4

EDMA_BASE_PTRS: DMA base table.

EDMA_CHN_IRQS

EDMA_CHANNEL_OFFSET: EDMA base address convert macro.

EDMA_CHANNEL_ARRAY_STEP(base)

EIM: error injection module

FSL_ERM_DRIVER_VERSION: Driver version.

void EIM_Init(EIM_Type *base)

EIM module initialization function.

Parameters:

base – EIM base address.

void EIM_Deinit(EIM_Type *base): De-initializes the EIM.

EQDC: Enhanced Quadrature Encoder/Decoder

void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)

Initializes the EQDC module.

This function initializes the EQDC by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
psConfig – Pointer to configuration structure.

void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)

Gets an available pre-defined configuration.

The default value are:

psConfig->enableReverseDirection              = false;
psConfig->countOnce                           = false;
psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
psConfig->countMode                           = kEQDC_QuadratureX4;
psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
psConfig->enableIndexInitPositionCounter      = false;
psConfig->enableDma                           = false;
psConfig->bufferedRegisterLoadMode            = false;
psConfig->enableTriggerInitPositionCounter    = false;
psConfig->enableTriggerClearPositionRegisters = false;
psConfig->enableTriggerHoldPositionRegisters  = false;
psConfig->enableWatchdog                      = false;
psConfig->watchdogTimeoutValue                = 0xFFFFU;
psConfig->filterPhaseA                        = 0U;
psConfig->filterPhaseB                        = 0U;
psConfig->filterIndPre                        = 0U;
psConfig->filterHomEna                        = 0U;
psConfig->filterClockSourceselection          = false;
psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
psConfig->filterSamplePeriod                  = 0U;
psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
psConfig->positionCompareValue[0]                = 0xFFFFFFFFU;
psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
psConfig->positionModulusValue                = 0U;
psConfig->positionInitialValue                = 0U;
psConfig->positionCounterValue                = 0U;
psConfig->enablePeriodMeasurement             = false;
psConfig->prescaler                           = kEQDC_Prescaler1;
psConfig->enabledInterruptsMask               = 0U;

Parameters:

psConfig – Pointer to configuration structure.

void EQDC_Deinit(EQDC_Type *base)

De-initializes the EQDC module.

This function deinitializes the EQDC by disabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.

void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)

Initializes the mode of operation.

This function initializes mode of operation by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
operateMode – Select operation mode.

static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode)

Initializes the mode of count.

These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved

Parameters:

base – EQDC peripheral base address.
countMode – Select count mode.

static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable)

Enable watchdog for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the watchdog

static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout)

Set watchdog timeout value.

Parameters:

base – EQDC peripheral base address
u16Timeout – Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out

static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable)

Enable DMA for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the DMA

static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Set Buffered Register Load (Update) Mode.

This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Clear Buffered Register Load (Update) Mode.

Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_SetEqdcLdok(EQDC_Type *base)

Set load okay.

Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.

Parameters:

base – EQDC peripheral base address.

static inline uint8_t EQDC_GetEqdcLdok(EQDC_Type *base)

Get load okay.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_ClearEqdcLdok(EQDC_Type *base)

Clear load okay.

Parameters:

base – EQDC peripheral base address.

static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base)

Get the status flags.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the status flags, _eqdc_status_flags.

static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags)

Clear the status flags.

Parameters:

base – EQDC peripheral base address.
u32Flags – Logical OR’ed value of the flags to clear, _eqdc_status_flags.

static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base)

Get the signals’ real-time status.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the real-time signal status, _eqdc_signal_status.

static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base)

Get the direction of the last count.

Parameters:

base – EQDC peripheral base address.

Returns:

Direction of the last count.

static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Enable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Disable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base)

Load the initial position value to position counter.

Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue)

Set initial position value for EQDC module.

Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionInitValue – Position initial value

static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue)

Set position counter value.

Set the position counter value (POS or UPOS, LPOS).

Parameters:

base – EQDC peripheral base address
positionCounterValue – Position counter value

static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue)

Set position counter modulus value.

Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
positionModulusValue – Position modulus value

static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value)

Set position counter compare 0 value.

Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp0Value – Position modulus value

static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value)

Set position counter compare 1 value.

Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp1Value – Position modulus value

static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value)

Set position counter compare 2 value.

Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp2Value – Position modulus value

static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value)

Set position counter compare 3 value.

Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp3Value – Position modulus value

static inline uint32_t EQDC_GetPosition(EQDC_Type *base)

Get the current position counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

Current position counter’s value.

static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base)

Get the hold position counter’s value.

The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter’s value.

static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base)

Get the hold position counter1’s value.

The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter1’s value.

static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base)

Get the hold position counter2’s value.

The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter2’s value.

static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base)

Get the hold position counter3’s value.

The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter3’s value.

static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base)

Get the position difference counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference counter’s value.

static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base)

Get the hold position difference counter’s value.

The position difference (POSD) value is loaded to hold position difference (POSDH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position difference counter’s value.

static inline uint16_t EQDC_GetRevolution(EQDC_Type *base)

Get the revolution counter’s value.

Get the revolution counter (REV) value.

Parameters:

base – EQDC peripheral base address.

Returns:

The revolution counter’s value.

static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base)

Get the hold revolution counter’s value.

The revolution counter (REV) value is loaded to hold revolution (REVH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position revolution counter’s value.

static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base)

Get the last edge time.

Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The last edge time.

static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base)

Get the hold last edge time.

The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold of last edge time.

static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base)

Get the Position Difference Period counter value.

The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference period counter value.

static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base)

Get buffered Position Difference Period counter value.

The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The buffered position difference period counter value.

static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)

Get Hold Position Difference Period counter value.

The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.

Parameters:

base – EQDC peripheral base address.

Returns:

The hold position difference period counter value.

enum _eqdc_status_flags

EQDC status flags, these flags indicate the counter’s events. .

Values:

enumerator kEQDC_HomeEnableTransitionFlag: HOME/ENABLE signal transition occured.

enumerator kEQDC_IndexPresetPulseFlag: INDEX/PRESET pulse occured.

enumerator kEQDC_WatchdogTimeoutFlag: Watchdog timeout occured.

enumerator kEQDC_SimultPhaseChangeFlag: Simultaneous change of PHASEA and PHASEB occured.

enumerator kEQDC_CountDirectionChangeFlag: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverFlag: Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.

enumerator kEQDC_PositionRollUnderFlag: Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.

enumerator kEQDC_PositionCompare0Flag: Position counter match the COMP0 value.

enumerator kEQDC_PositionCompare1Flag: Position counter match the COMP1 value.

enumerator kEQDC_PositionCompare2Flag: Position counter match the COMP2 value.

enumerator kEQDC_PositionCompare3Flag: Position counter match the COMP3 value.

enumerator kEQDC_StatusAllFlags

enum _eqdc_signal_status

Signal status, these flags indicate the raw and filtered input signal status. .

Values:

enumerator kEQDC_SignalStatusRawHomeEnable: Raw HOME/ENABLE input.

enumerator kEQDC_SignalStatusRawIndexPreset: Raw INDEX/PRESET input.

enumerator kEQDC_SignalStatusRawPhaseB: Raw PHASEB input.

enumerator kEQDC_SignalStatusRawPhaseA: Raw PHASEA input.

enumerator kEQDC_SignalStatusFilteredHomeEnable: The filtered HOME/ENABLE input.

enumerator kEQDC_SignalStatusFilteredIndexPreset: The filtered INDEX/PRESET input.

enumerator kEQDC_SignalStatusFilteredPhaseB: The filtered PHASEB input.

enumerator kEQDC_SignalStatusFilteredPhaseA: The filtered PHASEA input.

enumerator kEQDC_SignalStatusPositionCompare0Flag: Position Compare 0 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare1Flag: Position Compare 1 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare2Flag: Position Compare 2 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare3Flag: Position Compare 3 Flag Output.

enumerator kEQDC_SignalStatusCountDirectionFlagHold: Count Direction Flag Hold.

enumerator kEQDC_SignalStatusCountDirectionFlag: Count Direction Flag Output.

enumerator kEQDC_SignalStatusAllFlags

enum _eqdc_interrupt_enable

Interrupt enable/disable mask. .

Values:

enumerator kEQDC_HomeEnableTransitionInterruptEnable: HOME/ENABLE signal transition interrupt enable.

enumerator kEQDC_IndexPresetPulseInterruptEnable: INDEX/PRESET pulse interrupt enable.

enumerator kEQDC_WatchdogTimeoutInterruptEnable: Watchdog timeout interrupt enable.

enumerator kEQDC_SimultPhaseChangeInterruptEnable: Simultaneous PHASEA and PHASEB change interrupt enable.

enumerator kEQDC_CountDirectionChangeInterruptEnable: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverInterruptEnable: Roll-over interrupt enable.

enumerator kEQDC_PositionRollUnderInterruptEnable: Roll-under interrupt enable.

enumerator kEQDC_PositionCompare0InterruptEnable: Position compare 0 interrupt enable.

enumerator kEQDC_PositionCompare1InterruptEnable: Position compare 1 interrupt enable.

enumerator kEQDC_PositionCompare2InterruptEnable: Position compare 2 interrupt enable.

enumerator kEQDC_PositionCompare3InterruptEnable: Position compare 3 interrupt enable.

enumerator kEQDC_AllInterruptEnable

enum _eqdc_home_enable_init_pos_counter_mode

Define HOME/ENABLE signal’s trigger mode.

Values:

enumerator kEQDC_HomeInitPosCounterDisabled: Don’t use HOME/ENABLE signal to initialize the position counter.

enumerator kEQDC_HomeInitPosCounterOnRisingEdge: Use positive going edge to trigger initialization of position counters.

enumerator kEQDC_HomeInitPosCounterOnFallingEdge: Use negative going edge to trigger initialization of position counters.

enum _eqdc_index_preset_init_pos_counter_mode

Define INDEX/PRESET signal’s trigger mode.

Values:

enumerator kEQDC_IndexInitPosCounterDisabled: INDEX/PRESET pulse does not initialize the position counter.

enumerator kEQDC_IndexInitPosCounterOnRisingEdge: Use INDEX/PRESET pulse rising edge to initialize position counter.

enumerator kEQDC_IndexInitPosCounterOnFallingEdge: Use INDEX/PRESET pulse falling edge to initialize position counter.

enum _eqdc_operate_mode

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

Values:

enumerator kEQDC_QuadratureDecodeOperationMode: Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_QuadratureCountOperationMode: Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.

enumerator kEQDC_SinglePhaseDecodeOperationMode: Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_SinglePhaseCountOperationMode: Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.

enum _eqdc_count_mode

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

Values:

enumerator kEQDC_QuadratureX4: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX2: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX1: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_UpDownPulseCount: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountDoubleEdge: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountSingleEdge: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enum _eqdc_output_pulse_mode

Define type for the condition of POSMATCH pulses.

Values:

enumerator kEQDC_OutputPulseOnCounterEqualCompare: POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).

enumerator kEQDC_OutputPulseOnReadingPositionCounter: POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).

enum _eqdc_revolution_count_condition

Define type for determining how the revolution counter (REV) is incremented/decremented.

Values:

enumerator kEQDC_RevolutionCountOnIndexPulse: Use INDEX pulse to increment/decrement revolution counter.

enumerator kEQDC_RevolutionCountOnRollOverModulus: Use modulus counting roll-over/under to increment/decrement revolution counter.

enum _eqdc_filter_sample_count

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

Values:

enumerator kEQDC_Filter3Samples: 3 samples.

enumerator kEQDC_Filter4Samples: 4 samples.

enumerator kEQDC_Filter5Samples: 5 samples.

enumerator kEQDC_Filter6Samples: 6 samples.

enumerator kEQDC_Filter7Samples: 7 samples.

enumerator kEQDC_Filter8Samples: 8 samples.

enumerator kEQDC_Filter9Samples: 9 samples.

enumerator kEQDC_Filter10Samples: 10 samples.

enum _eqdc_count_direction_flag

Count direction.

Values:

enumerator kEQDC_CountDirectionDown: Last count was in down direction.

enumerator kEQDC_CountDirectionUp: Last count was in up direction.

enum _eqdc_prescaler

Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

Values:

enumerator kEQDC_Prescaler1: Prescaler value 1.

enumerator kEQDC_Prescaler2: Prescaler value 2.

enumerator kEQDC_Prescaler4: Prescaler value 4.

enumerator kEQDC_Prescaler8: Prescaler value 8.

enumerator kEQDC_Prescaler16: Prescaler value 16.

enumerator kEQDC_Prescaler32: Prescaler value 32.

enumerator kEQDC_Prescaler64: Prescaler value 64.

enumerator kEQDC_Prescaler128: Prescaler value 128.

enumerator kEQDC_Prescaler256: Prescaler value 256.

enumerator kEQDC_Prescaler512: Prescaler value 512.

enumerator kEQDC_Prescaler1024: Prescaler value 1024.

enumerator kEQDC_Prescaler2048: Prescaler value 2048.

enumerator kEQDC_Prescaler4096: Prescaler value 4096.

enumerator kEQDC_Prescaler8192: Prescaler value 8192.

enumerator kEQDC_Prescaler16384: Prescaler value 16384.

enumerator kEQDC_Prescaler32768: Prescaler value 32768.

typedef enum _eqdc_home_enable_init_pos_counter_mode eqdc_home_enable_init_pos_counter_mode_t: Define HOME/ENABLE signal’s trigger mode.

typedef enum _eqdc_index_preset_init_pos_counter_mode eqdc_index_preset_init_pos_counter_mode_t: Define INDEX/PRESET signal’s trigger mode.

typedef enum _eqdc_operate_mode eqdc_operate_mode_t

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

typedef enum _eqdc_count_mode eqdc_count_mode_t

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

typedef enum _eqdc_output_pulse_mode eqdc_output_pulse_mode_t: Define type for the condition of POSMATCH pulses.

typedef enum _eqdc_revolution_count_condition eqdc_revolution_count_condition_t: Define type for determining how the revolution counter (REV) is incremented/decremented.

typedef enum _eqdc_filter_sample_count eqdc_filter_sample_count_t

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

typedef enum _eqdc_count_direction_flag eqdc_count_direction_flag_t: Count direction.

typedef enum _eqdc_prescaler eqdc_prescaler_t: Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

typedef struct _eqdc_config eqdc_config_t: Define user configuration structure for EQDC module.

FSL_EQDC_DRIVER_VERSION

EQDC_CTRL_W1C_FLAGS: W1C bits in EQDC CTRL registers.

EQDC_INTCTRL_W1C_FLAGS: W1C bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_EN: Interrupt enable bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_EN: Interrupt enable bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_FLAGS: Interrupt flag bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_FLAGS: Interrupt flag bits in EQDC INTCTRL registers.

kEQDC_PositionCompare0InerruptEnable

kEQDC_PositionCompare1InerruptEnable

kEQDC_PositionCompare2InerruptEnable

kEQDC_PositionCompare3InerruptEnable

struct _eqdc_config

#include <fsl_eqdc.h>

Define user configuration structure for EQDC module.

Public Members

bool enableReverseDirection: Enable reverse direction counting.

bool countOnce: Selects modulo loop or one shot counting mode.

bool enableDma: Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)

bool bufferedRegisterLoadMode: selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD).

bool enableTriggerInitPositionCounter: Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER’s rising edge.

bool enableIndexInitPositionCounter

Enables the feature that the position counter to be initialized by Index Event Edge Mark.

This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:

When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.

When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.

bool enableTriggerClearPositionRegisters: Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER’s rising edge.

bool enableTriggerHoldPositionRegisters: Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER’s rising edge.

bool filterPhaseA: Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed.

bool filterPhaseB: Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed.

bool filterIndPre: Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed.

bool filterHomEna: Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed.

bool enableWatchdog: Enable the watchdog to detect if the target is moving or not.

uint16_t watchdogTimeoutValue: Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer.

eqdc_prescaler_t prescaler: Prescaler.

bool filterClockSourceselection: Filter Clock Source selection.

eqdc_filter_sample_count_t filterSampleCount: Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.

uint8_t filterSamplePeriod: Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

eqdc_operate_mode_t operateMode: Selects operation mode.

eqdc_count_mode_t countMode: Selects count mode.

eqdc_home_enable_init_pos_counter_mode_t homeEnableInitPosCounterMode: Select how HOME/Enable signal used to initialize position counters.

eqdc_index_preset_init_pos_counter_mode_t indexPresetInitPosCounterMode: Select how INDEX/Preset signal used to initialize position counters.

eqdc_output_pulse_mode_t outputPulseMode: The condition of POSMATCH pulses.

uint32_t positionCompareValue[4]: Position compare 0 ~ 3 value. The available value is a 32-bit number.

eqdc_revolution_count_condition_t revolutionCountCondition: Revolution Counter Modulus Enable.

uint32_t positionModulusValue: Position modulus value. The available value is a 32-bit number.

uint32_t positionInitialValue: Position initial value. The available value is a 32-bit number.

uint32_t positionCounterValue: Position counter value. When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.

bool enablePeriodMeasurement: Enable period measurement. When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.

uint16_t enabledInterruptsMask: Mask of interrupts to be enabled, should be OR’ed value of _eqdc_interrupt_enable.

ERM: error recording module

void ERM_Init(ERM_Type *base)

ERM module initialization function.

Parameters:

base – ERM base address.

void ERM_Deinit(ERM_Type *base): De-initializes the ERM.

static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)

ERM enable interrupts.

Parameters:

base – ERM peripheral base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)

ERM module disable interrupts.

Parameters:

base – ERM base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel)

Gets ERM interrupt flags.

Parameters:

base – ERM peripheral base address.

Returns:

ERM event flags.

static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)

ERM module clear interrupt status flag.

Parameters:

base – ERM base address.
mask – event flag to clear. Refer to “_erm_interrupt_flag” enumeration.

uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel)

ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.

Parameters:

base – ERM base address.
channel – memory channel.

Return values:

memory – error absolute address.

uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel)

ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic information on non-correctable, multi-bit inversions.

Parameters:

base – ERM base address.
channel – memory channel.

Return values:

syndrome – value.

uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)

ERM get error count, which records the count value of the number of correctable ECC error events for Memory n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count non-correctable errors. Only correctable errors are counted.

Parameters:

base – ERM base address.
channel – memory channel.

Return values:

error – count.

void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel)

ERM reset error count.

Parameters:

base – ERM base address.
channel – memory channel.

FSL_ERM_DRIVER_VERSION: Driver version.

ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.

This structure contains the settings for all of the ERM interrupt configurations.

Values:

enumerator kERM_SingleCorrectionIntEnable: Single Correction Interrupt Notification enable.

enumerator kERM_NonCorrectableIntEnable: Non-Correction Interrupt Notification enable.

enumerator kERM_AllInterruptsEnable: All Interrupts enable

ERM interrupt status, _erm_interrupt_flag.

This provides constants for the ERM event status for use in the ERM functions.

Values:

enumerator kERM_SingleBitCorrectionIntFlag: Single-Bit Correction Event.

enumerator kERM_NonCorrectableErrorIntFlag: Non-Correctable Error Event.

enumerator kERM_AllIntsFlag: All Events.

FGPIO Driver

FREQME: Frequency Measurement

GLIKEY

Values:

enumerator kStatus_GLIKEY_LockedError: GLIKEY status for locked SFR registers (unexpected) .

enumerator kStatus_GLIKEY_NotLocked: GLIKEY status for unlocked SFR registers.

enumerator kStatus_GLIKEY_Locked: GLIKEY status for locked SFR registers.

enumerator kStatus_GLIKEY_DisabledError: GLIKEY status for disabled error.

FSL_GLIKEY_DRIVER_VERSION

Defines GLIKEY driver version 2.0.1.

Change log:

Version 2.0.1
- Implement INIT state recovery from the LOCKED state after a reset when the previous index was locked.
Version 2.0.0
- Initial version

GLIKEY_CODEWORD_STEP1

GLIKEY_CODEWORD_STEP2

GLIKEY_CODEWORD_STEP3

GLIKEY_CODEWORD_STEP4

GLIKEY_CODEWORD_STEP5

GLIKEY_CODEWORD_STEP6

GLIKEY_CODEWORD_STEP7

GLIKEY_CODEWORD_STEP_EN

GLIKEY_FSM_WR_DIS

GLIKEY_FSM_INIT

GLIKEY_FSM_STEP1

GLIKEY_FSM_STEP2

GLIKEY_FSM_STEP3

GLIKEY_FSM_STEP4

GLIKEY_FSM_LOCKED

GLIKEY_FSM_WR_EN

GLIKEY_FSM_SSR_RESET

uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)

Retreives the current status of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Glikey status information

status_t GLIKEY_IsLocked(GLIKEY_Type *base)

Get if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

kStatus_GLIKEY_Locked – if locked
kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status

status_t GLIKEY_CheckLock(GLIKEY_Type *base)

Check if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

kStatus_GLIKEY_LockedError – if locked
kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status kStatus_Success if success

status_t GLIKEY_SyncReset(GLIKEY_Type *base)

Perform a synchronous reset of Glikey.

This function performs a synchrounous reset of the Glikey. This results in:

Glikey will return to the INIT state, unless it is in the LOCK state

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)

Set interrupt enable flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance
value – [in] Value to set the interrupt enable flag to, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)

Get interrupt enable flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance
value – [out] Pointer which will be filled with the interrupt enable status, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success

status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)

Clear the interrupt status flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)

Set the interrupt status flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_Lock(GLIKEY_Type *base)

Lock Glikey SFR (Special Function Registers) interface.

This operation locks the Glikey SFR interface if it is not locked yet.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success

status_t GLIKEY_LockIndex(GLIKEY_Type *base)

Lock Glikey index.

This operation is used to lock a Glikey index. It can only be executed from the WR_EN state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)

Check if Glikey index is locked.

This operation returns the locking status of Glikey index.

Parameters:

base – [in] The base address of the Glikey instance
index – [in] The index of the Glikey instance

Returns:

kStatus_GLIKEY_Locked if locked, kStatus_GLIKEY_NotLocked if unlocked Possible errors: kStatus_Fail

status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)

Start Glikey enable.

This operation is used to set a new index and start a the sequence to enable it. It needs to be started from the INIT state. If the new index is already locked Glikey will go to LOCKED state, otherwise it will go to STEP1 state. If this operation is used when Glikey is in any state other than INIT Glikey will go to WR_DIS state. It can only recover from this state through a reset (synchrounous or asyncrhonous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance
index – [in] The index of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail

status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)

Continue Glikey enable.

This operation is used to progress through the different states of the state machine, starting from STEP1 until the state WR_EN is reached. Each next state of the state machine can only be reached by providing the right codeword to this function. If anything goes wrong the state machine will go to WR_DIS state and can only recover from it through a reset (synchrous or asynchronous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance
codeword – [in] Encoded word for progressing to next FSM state (see GLIKEY_CODEWORD_STEPx/EN)

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail, kStatus_GLIKEY_DisabledError

status_t GLIKEY_EndOperation(GLIKEY_Type *base)

End Glikey operation.

This operation is used to end a Glikey operation. It can only be executed from the WR_EN, LOCKED and RESET states. Executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. After this operation Glikey will go to INIT state or stay in LOCKED state when the index was locked. If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

A code-flow protected error code (see nxpCsslFlowProtection)

Returns:

Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)

Reset Glikey index.

This operation is used to reset a Glikey index. It can only be executed from the INIT state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active or the index is locked this operation will return an error.

Returns:: A code-flow protected error code (see nxpCsslFlowProtection)
Returns:: Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

GPIO: General-Purpose Input/Output Driver

FSL_GPIO_DRIVER_VERSION: GPIO driver version.

enum _gpio_pin_direction

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput: Set current pin as digital input

enumerator kGPIO_DigitalOutput: Set current pin as digital output

enum _gpio_checker_attribute

GPIO checker attribute.

Values:

enumerator kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW: User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW: User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW: User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW: User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW: User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW: User nonsecure:None; User Secure:None; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR: User nonsecure:None; User Secure:None; Privileged Secure:Read

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN: User nonsecure:None; User Secure:None; Privileged Secure:None

enumerator kGPIO_IgnoreAttributeCheck: Ignores the attribute check

enum _gpio_interrupt_config

Configures the interrupt generation condition.

Values:

enumerator kGPIO_InterruptStatusFlagDisabled: Interrupt status flag is disabled.

enumerator kGPIO_DMARisingEdge: ISF flag and DMA request on rising edge.

enumerator kGPIO_DMAFallingEdge: ISF flag and DMA request on falling edge.

enumerator kGPIO_DMAEitherEdge: ISF flag and DMA request on either edge.

enumerator kGPIO_FlagRisingEdge: Flag sets on rising edge.

enumerator kGPIO_FlagFallingEdge: Flag sets on falling edge.

enumerator kGPIO_FlagEitherEdge: Flag sets on either edge.

enumerator kGPIO_InterruptLogicZero: Interrupt when logic zero.

enumerator kGPIO_InterruptRisingEdge: Interrupt on rising edge.

enumerator kGPIO_InterruptFallingEdge: Interrupt on falling edge.

enumerator kGPIO_InterruptEitherEdge: Interrupt on either edge.

enumerator kGPIO_InterruptLogicOne: Interrupt when logic one.

enumerator kGPIO_ActiveHighTriggerOutputEnable: Enable active high-trigger output.

enumerator kGPIO_ActiveLowTriggerOutputEnable: Enable active low-trigger output.

enum _gpio_interrupt_selection

Configures the selection of interrupt/DMA request/trigger output.

Values:

enumerator kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.

enumerator kGPIO_InterruptOutput1: Interrupt/DMA request/trigger output 1.

enum gpio_pin_interrupt_control_t

GPIO pin and interrupt control.

Values:

enumerator kGPIO_PinControlNonSecure: Pin Control Non-Secure.

enumerator kGPIO_InterruptControlNonSecure: Interrupt Control Non-Secure.

enumerator kGPIO_PinControlNonPrivilege: Pin Control Non-Privilege.

enumerator kGPIO_InterruptControlNonPrivilege: Interrupt Control Non-Privilege.

typedef enum _gpio_pin_direction gpio_pin_direction_t: GPIO direction definition.

typedef enum _gpio_checker_attribute gpio_checker_attribute_t: GPIO checker attribute.

typedef struct _gpio_pin_config gpio_pin_config_t

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

typedef enum _gpio_interrupt_config gpio_interrupt_config_t: Configures the interrupt generation condition.

typedef enum _gpio_interrupt_selection gpio_interrupt_selection_t: Configures the selection of interrupt/DMA request/trigger output.

typedef struct _gpio_version_info gpio_version_info_t: GPIO version information.

GPIO_FIT_REG(value)

struct _gpio_pin_config

#include <fsl_gpio.h>

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

Public Members

gpio_pin_direction_t pinDirection: GPIO direction, input or output

uint8_t outputLogic: Set a default output logic, which has no use in input

struct _gpio_version_info

#include <fsl_gpio.h>

GPIO version information.

Public Members

uint16_t feature: Feature Specification Number.

uint8_t minor: Minor Version Number.

uint8_t major: Major Version Number.

GPIO Driver

void GPIO_PortInit(GPIO_Type *base)

Initializes the GPIO peripheral.

This function ungates the GPIO clock.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PortDenit(GPIO_Type *base)

Denitializes the GPIO peripheral.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)

Initializes a GPIO pin used by the board.

To initialize the GPIO, define a pin configuration, as either input or output, in the user file. Then, call the GPIO_PinInit() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalOutput,
  0,
}

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO port pin number
config – GPIO pin configuration pointer

void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)

Get GPIO version information.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
info – GPIO version information

static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)

lock or unlock secure privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – pin or interrupt macro

static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)

Enable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)

Disable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Enable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Disable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)

Enable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)

Disable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Enable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Disable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)

Enable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)

Disable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple GPIO pins to the logic 1 or 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number
output – GPIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple GPIO pins.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number

Return values:

GPIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)

Configures the gpio pin interrupt/DMA request.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).

static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)

Configures the gpio pin interrupt/DMA request/trigger output channel selection.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
selection – GPIO pin interrupt output selection.
- kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
- kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.

uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)

Read the GPIO interrupt status flags.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)

Returns:

The current GPIO’s interrupt status flag. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)

Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

Returns:

The current GPIO’s interrupt status flag based on the selected interrupt channel. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)

Read individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
pin – GPIO specific pin number.

Returns:

The current selected pin’s interrupt status flag.

void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears GPIO pin interrupt status flags.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)

Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)

Clear GPIO individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
pin – GPIO specific pin number.

static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)

Sets the GPIO interrupt configuration in PCR register for multiple pins.

Parameters:

base – GPIO peripheral base pointer.
mask – GPIO pin number macro.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..

void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)

brief The GPIO module supports a device-specific number of data ports, organized as 32-bit words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the GPIO programming model. If the GPIO module’s GACR register organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
attribute – GPIO checker attribute

I3C: I3C Driver

FSL_I3C_DRIVER_VERSION: I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy: The master is already performing a transfer.

enumerator kStatus_I3C_Idle: The slave driver is idle.

enumerator kStatus_I3C_Nak: The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort: The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term: The master terminates slave read.

enumerator kStatus_I3C_HdrParityError: Parity error from DDR read.

enumerator kStatus_I3C_CrcError: CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError: Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError: Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError: Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq: Invalid use of request.

enumerator kStatus_I3C_Timeout: The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed: The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon: The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError: Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError: Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak: Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart: Slave invalid start flag

enumerator kStatus_I3C_SdrParityError: SDR parity error

enumerator kStatus_I3C_S0S1Error: S0 or S1 error

enum _i3c_hdr_mode

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone

enumerator kI3C_HDRModeDDR

enumerator kI3C_HDRModeTSP

enumerator kI3C_HDRModeTSL

typedef enum _i3c_hdr_mode i3c_hdr_mode_t: I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t: I3C device information.

I3C_RETRY_TIMES: Timeout times for waiting flag.

I3C_MAX_DEVCNT

I3C_IBI_BUFF_SIZE

struct _i3c_device_info

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr: Device dynamic address.

uint8_t staticAddr: Static address.

uint8_t dcr: Device characteristics register information.

uint8_t bcr: Bus characteristics register information.

uint16_t vendorID: Device vendor ID(manufacture ID).

uint32_t partNumber: Device part number info

uint16_t maxReadLength: Maximum read length.

uint16_t maxWriteLength: Maximum write length.

uint8_t hdrMode: Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver

typedef struct _i3c_config i3c_config_t

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)

Get which instance current I3C is used.

Parameters:

base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->disableTimeout config->hKeep config->enableOpenDrainStop config->enableOpenDrainHigh config->baudRate_Hzconfig->baudRate_Hzconfig->baudRate_Hzconfig->masterDynamicAddress config->slowClock_Hz config->enableSlave config->vendorID config->enableRandomPart config->partNumber config->dcr config->bcr config->hdrMode config->nakAllRequest config->ignoreS0S1Error config->offline config->matchSlaveStartStop 

notranslate">

config->enableMaster                 = kI3C_MasterCapable; = false; = kI3C_MasterHighKeeperNone; = true; = true; class="o">.i2cBaud          = 400000U; class="o">.i3cPushPullBaud  = 12500000U; class="o">.i3cOpenDrainBaud = 2500000U; = 0x0AU; = 1000000U; = true; = 0x11BU; = false; = 0; = 0; = 0; = (uint8_t)kI3C_HDRModeDDR; = false; = false; = false; = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

config – [out] User provided configuration structure for default values. Refer to i3c_config_t. 







void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration. 

Parameters:

base – The I3C peripheral base address. 
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







struct _i3c_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay

I3C SCL delay after Repeated START. 




uint8_t masterDynamicAddress

Main master dynamic address configuration. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 




bool enableSlave

Whether to enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed.

MCXA153

AOI: Crossbar AND/OR/INVERT Driver

CDOG

Clock Driver

CRC: Cyclic Redundancy Check Driver

CTIMER: Standard counter/timers

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver

eDMA core Driver

eDMA soc Driver

EIM: error injection module

EQDC: Enhanced Quadrature Encoder/Decoder

ERM: error recording module

FGPIO Driver

FREQME: Frequency Measurement

GLIKEY

GLIKEY

GPIO: General-Purpose Input/Output Driver

GPIO Driver

I3C: I3C Driver

I3C Common Driver

I3C Master Driver

I3C Master DMA Driver

I3C Slave Driver

I3C Slave DMA Driver

INPUTMUX: Input Multiplexing Driver

Common Driver

Lin_lpuart_driver

LPADC: 12-bit SAR Analog-to-Digital Converter Driver

Lpc_freqme

LPCMP: Low Power Analog Comparator Driver

LPI2C: Low Power Inter-Integrated Circuit Driver

LPI2C Master Driver

LPI2C Master DMA Driver

LPI2C Slave Driver

LPSPI: Low Power Serial Peripheral Interface

LPSPI Peripheral driver

LPSPI eDMA Driver

LPTMR: Low-Power Timer

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver

LPUART Driver

LPUART eDMA Driver

MCX_CMC: Core Mode Controller Driver

MCX_SPC: System Power Control driver

MCX_VBAT: Smart Power Switch

OSTIMER: OS Event Timer Driver

PORT: Port Control and Interrupts

PWM: Pulse Width Modulator

Reset Driver

ROMAPI Driver

TRDC: Trusted Resource Domain Controller

Trdc_core

Trdc_soc

UTICK: MictoTick Timer Driver

WAKETIMER: WAKETIMER Driver

WUU: Wakeup Unit driver

WWDT: Windowed Watchdog Timer Driver