ISSDK  1.8
IoT Sensing Software Development Kit
board.c
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1 /*
2  * Copyright 2020 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15 
16 /*******************************************************************************
17  * Variables
18  ******************************************************************************/
19 
20 /*******************************************************************************
21  * Code
22  ******************************************************************************/
23 
24 /* Get debug console frequency. */
25 uint32_t BOARD_DebugConsoleSrcFreq(void)
26 {
27  uint32_t freq;
28 
29  /* To make it simple, we assume default PLL and divider settings, and the only variable
30  from application is use PLL3 source or OSC source */
31  if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32  {
33  freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34  }
35  else
36  {
37  freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38  }
39 
40  return freq;
41 }
42 
43 /* Initialize debug console. */
44 void BOARD_InitDebugConsole(void)
45 {
46  uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47 
48  DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49 }
50 
51 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
52 {
53  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD,
54  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
55  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
56  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
57  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
58  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK,
59  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
60  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
61  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
62  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0,
63  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
64  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
65  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
66  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
67  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1,
68  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
69  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
70  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
71  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
72  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2,
73  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
74  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
75  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
76  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
77  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,
78  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
79  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
80  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
81  IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
82 }
83 
84 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
85 {
86 }
87 
88 /* MPU configuration. */
89 void BOARD_ConfigMPU(void)
90 {
91 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
92  extern uint32_t Image$$RW_m_ncache$$Base[];
93  /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
94  extern uint32_t Image$$RW_m_ncache_unused$$Base[];
95  extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
96  uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
97  uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
98  0 :
99  ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
100 #elif defined(__MCUXPRESSO)
101  extern uint32_t __base_NCACHE_REGION;
102  extern uint32_t __top_NCACHE_REGION;
103  uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
104  uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
105 #elif defined(__ICCARM__) || defined(__GNUC__)
106  extern uint32_t __NCACHE_REGION_START[];
107  extern uint32_t __NCACHE_REGION_SIZE[];
108  uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
109  uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
110 #endif
111  uint32_t i = 0;
112 
113  /* Disable I cache and D cache */
114  if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
115  {
116  SCB_DisableICache();
117  }
118  if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
119  {
120  SCB_DisableDCache();
121  }
122 
123  /* Disable MPU */
124  ARM_MPU_Disable();
125 
126  /* MPU configure:
127  * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
128  * SubRegionDisable, Size)
129  * API in mpu_armv7.h.
130  * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
131  * disabled.
132  * param AccessPermission Data access permissions, allows you to configure read/write access for User and
133  * Privileged mode.
134  * Use MACROS defined in mpu_armv7.h:
135  * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
136  * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
137  * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
138  * 0 x 0 0 Strongly Ordered shareable
139  * 0 x 0 1 Device shareable
140  * 0 0 1 0 Normal not shareable Outer and inner write
141  * through no write allocate
142  * 0 0 1 1 Normal not shareable Outer and inner write
143  * back no write allocate
144  * 0 1 1 0 Normal shareable Outer and inner write
145  * through no write allocate
146  * 0 1 1 1 Normal shareable Outer and inner write
147  * back no write allocate
148  * 1 0 0 0 Normal not shareable outer and inner
149  * noncache
150  * 1 1 0 0 Normal shareable outer and inner
151  * noncache
152  * 1 0 1 1 Normal not shareable outer and inner write
153  * back write/read acllocate
154  * 1 1 1 1 Normal shareable outer and inner write
155  * back write/read acllocate
156  * 2 x 0 0 Device not shareable
157  * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
158  * policy.
159  * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
160  * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
161  * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
162  * mpu_armv7.h.
163  */
164 
165  /*
166  * Add default region to deny access to whole address space to workaround speculative prefetch.
167  * Refer to Arm errata 1013783-B for more details.
168  *
169  */
170  /* Region 0 setting: No Access. */
171  MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
172  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
173 
174  /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
175  MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
176  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
177 
178  /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
179  MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
180  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
181 
182 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
183  /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
184  MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
185  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
186 #endif
187 
188  /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
189  MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
190  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
191 
192  /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
193  MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
194  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
195 
196  /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
197  MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
198  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
199 
200  /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
201  MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
202  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
203 
204  /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
205  MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
206  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
207 
208  while ((size >> i) > 0x1U)
209  {
210  i++;
211  }
212 
213  if (i != 0)
214  {
215  /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
216  assert(!(nonCacheStart % size));
217  assert(size == (uint32_t)(1 << i));
218  assert(i >= 5);
219 
220  /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
221  MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
222  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
223  }
224 
225  /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
226  MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
227  MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
228 
229  /* Enable MPU */
230  ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
231 
232  /* Enable I cache and D cache */
233  SCB_EnableDCache();
234  SCB_EnableICache();
235 }
236 
237 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
238 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
239 {
240  lpi2c_master_config_t lpi2cConfig = {0};
241 
242  /*
243  * lpi2cConfig.debugEnable = false;
244  * lpi2cConfig.ignoreAck = false;
245  * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
246  * lpi2cConfig.baudRate_Hz = 100000U;
247  * lpi2cConfig.busIdleTimeout_ns = 0;
248  * lpi2cConfig.pinLowTimeout_ns = 0;
249  * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
250  * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
251  */
252  LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
253  LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
254 }
255 
256 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
257  uint8_t deviceAddress,
258  uint32_t subAddress,
259  uint8_t subAddressSize,
260  uint8_t *txBuff,
261  uint8_t txBuffSize)
262 {
263  lpi2c_master_transfer_t xfer;
264 
265  xfer.flags = kLPI2C_TransferDefaultFlag;
266  xfer.slaveAddress = deviceAddress;
267  xfer.direction = kLPI2C_Write;
268  xfer.subaddress = subAddress;
269  xfer.subaddressSize = subAddressSize;
270  xfer.data = txBuff;
271  xfer.dataSize = txBuffSize;
272 
273  return LPI2C_MasterTransferBlocking(base, &xfer);
274 }
275 
276 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
277  uint8_t deviceAddress,
278  uint32_t subAddress,
279  uint8_t subAddressSize,
280  uint8_t *rxBuff,
281  uint8_t rxBuffSize)
282 {
283  lpi2c_master_transfer_t xfer;
284 
285  xfer.flags = kLPI2C_TransferDefaultFlag;
286  xfer.slaveAddress = deviceAddress;
287  xfer.direction = kLPI2C_Read;
288  xfer.subaddress = subAddress;
289  xfer.subaddressSize = subAddressSize;
290  xfer.data = rxBuff;
291  xfer.dataSize = rxBuffSize;
292 
293  return LPI2C_MasterTransferBlocking(base, &xfer);
294 }
295 
296 void BOARD_Accel_I2C_Init(void)
297 {
298  BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
299 }
300 
301 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
302 {
303  uint8_t data = (uint8_t)txBuff;
304 
305  return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
306 }
307 
308 status_t BOARD_Accel_I2C_Receive(
309  uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
310 {
311  return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
312 }
313 
314 void BOARD_Codec_I2C_Init(void)
315 {
316  BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
317 }
318 
319 status_t BOARD_Codec_I2C_Send(
320  uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
321 {
322  return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
323  txBuffSize);
324 }
325 
326 status_t BOARD_Codec_I2C_Receive(
327  uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
328 {
329  return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
330 }
331 #endif /* SDK_I2C_BASED_COMPONENT_USED */
size
uint32_t size
Definition: data_format_service.h:43
BOARD_ACCEL_I2C_CLOCK_FREQ
#define BOARD_ACCEL_I2C_CLOCK_FREQ
Definition: board.h:35
BOARD_CODEC_I2C_CLOCK_FREQ
#define BOARD_CODEC_I2C_CLOCK_FREQ
Definition: board.h:56
BOARD_DebugConsoleSrcFreq
uint32_t BOARD_DebugConsoleSrcFreq(void)
Definition: board.c:25
BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE
Definition: board.h:31
BOARD_ACCEL_I2C_BASEADDR
#define BOARD_ACCEL_I2C_BASEADDR
Definition: board.h:129
BOARD_SD_Pin_Config
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
Definition: board.c:51
data
uint8_t data[FXLS8962_DATA_SIZE]
Definition: fxls8962_demo.c:174
BOARD_MMC_Pin_Config
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
Definition: board.c:84
BOARD_DEBUG_UART_INSTANCE
#define BOARD_DEBUG_UART_INSTANCE
Definition: board.h:26
BOARD_CODEC_I2C_BASEADDR
#define BOARD_CODEC_I2C_BASEADDR
Definition: board.h:55
BOARD_ConfigMPU
void BOARD_ConfigMPU(void)
Definition: board.c:52
BOARD_InitDebugConsole
void BOARD_InitDebugConsole(void)
Definition: board.c:15
BOARD_DEBUG_UART_TYPE
#define BOARD_DEBUG_UART_TYPE
Definition: board.h:23
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