ISSDK  1.8
IoT Sensing Software Development Kit
clock_config.c
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1 /*
2  * Copyright (c) 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 /*
10  * How to setup clock using clock driver functions:
11  *
12  * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
13  * and flash clock are in allowed range during clock mode switch.
14  *
15  * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
16  *
17  * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
18  * internal reference clock(MCGIRCLK). Follow the steps to setup:
19  *
20  * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
21  *
22  * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
23  * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
24  * explicitly to setup MCGIRCLK.
25  *
26  * 3). Don't need to configure FLL explicitly, because if target mode is FLL
27  * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
28  * if the target mode is not FLL mode, the FLL is disabled.
29  *
30  * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
31  * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
32  * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
33  *
34  * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
35  */
36 
37 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
38 !!ClocksProfile
39 product: Clocks v1.0
40 processor: MK64FN1M0xxx12
41 package_id: MK64FN1M0VLL12
42 mcu_data: ksdk2_0
43 processor_version: 1.0.1
44 board: FRDM-K64F
45  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
46 
47 #include "fsl_smc.h"
48 #include "clock_config.h"
49 
50 /*******************************************************************************
51  * Definitions
52  ******************************************************************************/
53 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
54 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
55 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
56 #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
57 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
58 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
59 
60 /*******************************************************************************
61  * Variables
62  ******************************************************************************/
63 /* System clock frequency. */
64 extern uint32_t SystemCoreClock;
65 
66 /*******************************************************************************
67  * Code
68  ******************************************************************************/
69 /*FUNCTION**********************************************************************
70  *
71  * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
72  * Description : Configure FLL external reference divider (FRDIV).
73  * Param frdiv : The value to set FRDIV.
74  *
75  *END**************************************************************************/
76 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
77 {
78  MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
79 }
80 
81 /*******************************************************************************
82  ********************** Configuration BOARD_BootClockRUN ***********************
83  ******************************************************************************/
84 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
85 !!Configuration
86 name: BOARD_BootClockRUN
87 outputs:
88 - {id: Bus_clock.outFreq, value: 60 MHz}
89 - {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
90 - {id: Flash_clock.outFreq, value: 24 MHz}
91 - {id: FlexBus_clock.outFreq, value: 40 MHz}
92 - {id: LPO_clock.outFreq, value: 1 kHz}
93 - {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
94 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
95 - {id: OSCERCLK.outFreq, value: 50 MHz}
96 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
97 - {id: System_clock.outFreq, value: 120 MHz}
98 settings:
99 - {id: MCGMode, value: PEE}
100 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
101 - {id: MCG.FRDIV.scale, value: '32'}
102 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
103 - {id: MCG.PLLS.sel, value: MCG.PLL}
104 - {id: MCG.PRDIV.scale, value: '20', locked: true}
105 - {id: MCG.VDIV.scale, value: '48', locked: true}
106 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
107 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
108 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
109 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
110 - {id: RTCCLKOUTConfig, value: 'yes'}
111 - {id: RTC_CR_OSCE_CFG, value: Enabled}
112 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
113 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
114 - {id: SIM.OUTDIV2.scale, value: '2'}
115 - {id: SIM.OUTDIV3.scale, value: '3'}
116 - {id: SIM.OUTDIV4.scale, value: '5'}
117 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
118 - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
119 - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
120 - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
121 - {id: SIM.USBDIV.scale, value: '5'}
122 - {id: SIM.USBFRAC.scale, value: '2'}
123 - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
124 sources:
125 - {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
126  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
127 
128 /*******************************************************************************
129  * Variables for BOARD_BootClockRUN configuration
130  ******************************************************************************/
131 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
132  {
133  .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
134  .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
135  .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
136  .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
137  .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
138  .drs = kMCG_DrsLow, /* Low frequency range */
139  .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
140  .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
141  .pll0Config =
142  {
143  .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
144  .prdiv = 0x13U, /* PLL Reference divider: divided by 20 */
145  .vdiv = 0x18U, /* VCO divider: multiplied by 48 */
146  },
147  };
148 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
149  {
150  .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
151  .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
152  .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
153  };
154 const osc_config_t oscConfig_BOARD_BootClockRUN =
155  {
156  .freq = 50000000U, /* Oscillator frequency: 50000000Hz */
157  .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
158  .workMode = kOSC_ModeExt, /* Use external clock */
159  .oscerConfig =
160  {
161  .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
162  }
163  };
164 
165 /*******************************************************************************
166  * Code for BOARD_BootClockRUN configuration
167  ******************************************************************************/
169 {
170  /* Set the system clock dividers in SIM to safe value. */
171  CLOCK_SetSimSafeDivs();
172  /* Initializes OSC0 according to board configuration. */
173  CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
174  CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
175  /* Configure the Internal Reference clock (MCGIRCLK). */
176  CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
179  /* Configure FLL external reference divider (FRDIV). */
180  CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
181  /* Set MCG to PEE mode. */
182  CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
183  kMCG_PllClkSelPll0,
184  &mcgConfig_BOARD_BootClockRUN.pll0Config);
185  /* Set the clock configuration in SIM module. */
186  CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
187  /* Set SystemCoreClock variable. */
189 }
190 
191 /*******************************************************************************
192  ********************* Configuration BOARD_BootClockVLPR ***********************
193  ******************************************************************************/
194 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
195 !!Configuration
196 name: BOARD_BootClockVLPR
197 outputs:
198 - {id: Bus_clock.outFreq, value: 4 MHz}
199 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
200 - {id: Flash_clock.outFreq, value: 800 kHz}
201 - {id: FlexBus_clock.outFreq, value: 4 MHz}
202 - {id: LPO_clock.outFreq, value: 1 kHz}
203 - {id: MCGIRCLK.outFreq, value: 4 MHz}
204 - {id: System_clock.outFreq, value: 4 MHz}
205 settings:
206 - {id: MCGMode, value: BLPI}
207 - {id: powerMode, value: VLPR}
208 - {id: MCG.CLKS.sel, value: MCG.IRCS}
209 - {id: MCG.FCRDIV.scale, value: '1'}
210 - {id: MCG.FRDIV.scale, value: '32'}
211 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
212 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
213 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
214 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
215 - {id: RTC_CR_OSCE_CFG, value: Enabled}
216 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
217 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
218 - {id: SIM.OUTDIV3.scale, value: '1'}
219 - {id: SIM.OUTDIV4.scale, value: '5'}
220 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
221 - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
222 sources:
223 - {id: OSC.OSC.outFreq, value: 50 MHz}
224  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
225 
226 /*******************************************************************************
227  * Variables for BOARD_BootClockVLPR configuration
228  ******************************************************************************/
229 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
230  {
231  .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
232  .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
233  .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
234  .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
235  .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
236  .drs = kMCG_DrsLow, /* Low frequency range */
237  .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
238  .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
239  .pll0Config =
240  {
241  .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
242  .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
243  .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
244  },
245  };
246 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
247  {
248  .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
249  .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
250  .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
251  };
252 const osc_config_t oscConfig_BOARD_BootClockVLPR =
253  {
254  .freq = 0U, /* Oscillator frequency: 0Hz */
255  .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
256  .workMode = kOSC_ModeExt, /* Use external clock */
257  .oscerConfig =
258  {
259  .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
260  }
261  };
262 
263 /*******************************************************************************
264  * Code for BOARD_BootClockVLPR configuration
265  ******************************************************************************/
267 {
268  /* Set the system clock dividers in SIM to safe value. */
269  CLOCK_SetSimSafeDivs();
270  /* Set MCG to BLPI mode. */
271  CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
273  mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
274  /* Set the clock configuration in SIM module. */
275  CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
276  /* Set VLPR power mode. */
277  SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
278 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
279  SMC_SetPowerModeVlpr(SMC, false);
280 #else
282 #endif
283  while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
284  {
285  }
286  /* Set SystemCoreClock variable. */
288 }
289 
#define MCG_PLL_DISABLE
Definition: clock_config.c:53
void BOARD_BootClockVLPR(void)
This function executes configuration of clocks.
Definition: clock_config.c:266
status_t SMC_SetPowerModeVlpr(void *arg)
Configures the system to VLPR power mode. API name used from Kinetis family to maintain compatibility...
Definition: lpc54114.c:169
#define SMC
Definition: lpc54114.h:118
#define OSC_CAP0P
Definition: clock_config.c:54
#define SIM_PLLFLLSEL_IRC48MCLK_CLK
Definition: clock_config.c:57
const sim_clock_config_t simConfig_BOARD_BootClockRUN
SIM module set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:148
const osc_config_t oscConfig_BOARD_BootClockRUN
OSC set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:154
const osc_config_t oscConfig_BOARD_BootClockVLPR
OSC set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:252
#define SIM_OSC32KSEL_RTC32KCLK_CLK
Definition: clock_config.c:56
#define OSC_ER_CLK_DISABLE
Definition: clock_config.c:55
const mcg_config_t mcgConfig_BOARD_BootClockVLPR
MCG set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:229
const sim_clock_config_t simConfig_BOARD_BootClockVLPR
SIM module set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:246
#define SIM_PLLFLLSEL_MCGPLLCLK_CLK
Definition: clock_config.c:58
uint32_t SystemCoreClock
const mcg_config_t mcgConfig_BOARD_BootClockRUN
MCG set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:131
void BOARD_BootClockRUN(void)
This function executes configuration of clocks.
Definition: clock_config.c:168
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK
Definition: clock_config.h:60
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK
Definition: clock_config.h:25