MCUXpresso SDK Changelog#
Board Support Files#
board#
[25.06.00]#
Initial version
clock_config#
[25.06.00]#
Initial version
pin_mux#
[25.06.00]#
Initial version
COMMON#
[2.6.7]#
Improvements
EnableIRQ/DisableIRQ: Use IRQSTEER_GetInstIdxByIRQ() to determine IRQSTEER instance index instead of simple division. Supports multiple IRQSTEER instances with different interrupt counts.
[2.6.6]#
Improvements
Support Cortex M55.
[2.6.5]#
Bug Fixes
Fixed the issue that the function SDK_DelayAtLeastUs may underflow and cause a long delay when the input parameter is small and the system clock is low.
[2.6.4]#
New Features
Add macros to tag deprecated features and experimental features.
[2.6.3]#
New Features
Added bit mask inversion macros to avoid type promotion.
Added register operation macros.
Improvements
Make function
MSDK_EnableCpuCycleCountercompatible with CMSIS-5 and CMSIS-6.
Bug Fixes
Fixed build issue of CMSIS PACK BSP example caused by CMSIS 6.1 issue.
[2.6.2]#
Bug Fixes
Fixed violations of MISRA C-2012 rule for implicit conversions in boolean contexts
[2.6.1]#
Improvements
Support Cortex M23.
[2.6.0]#
Bug Fixes
Fix CERT-C violations.
[2.5.0]#
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]#
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]#
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]#
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]#
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]#
New Features
Added NETC into status group.
[2.3.2]#
Improvements
Make driver aarch64 compatible
[2.3.1]#
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]#
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]#
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]#
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]#
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]#
Other Change
Added MECC status group definition.
[2.2.6]#
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]#
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]#
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]#
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]#
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]#
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]#
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]#
New Features
Added OTFAD into status group.
[2.1.3]#
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]#
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]#
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]#
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]#
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]#
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]#
Initial version.
ACMP#
[2.5.0]#
New Feature
Supported the plateforms which don’t have continuous mode.
[2.4.0]#
New Feature
Supported the plateforms which don’t have continuous mode.
[2.3.0]#
Improvements
Expose C0 register FILTER_CNT bitfield and FPR bitfield to the user.
[2.2.0]#
Improvements
Updated feature macros for roundrobin mode, window mode, filter mode, and 3V domain removes.
[2.1.0]#
New Feature
Supported the plateforms which don’t have hysteresis mode.
[2.0.6]#
Bug Fixes
Fixed the wrong comments, the DAC value should range from 0 to 255.
[2.0.5]#
Bug Fixes
Fixed the out-of-bounds error of Coverity caused by missing an assert sentence to avoid the return value of ACMP_GetInstance() exceeding the array bounds.
Fixed the violations of MISRA C-2012 rules:
Rule 10.1, 14.4, 16.4, 17.7.
[2.0.4]#
Bug Fixes
Avoided changing w1c bit in ACMP_SetRoundRobinPreState().
[2.0.3]#
New Features
Added feature functions for usage of different power domains(1.8 V and 3 V). These functions are first enabled in ULP1. They are about:
ACMP_EnableLinkToDAC()
ACMP_SetDiscreteModeConfig()
ACMP_GetDefaultDiscreteModeConfig()
[2.0.2]#
Other Changes
Changed coding style of peripheral base address from “s_acmpBases” to “s_acmpBase”.
[2.0.1]#
Bug Fixes
Fixed bug regarding the function “ACMP_SetRoundRobinConfig”. It will not continue execution but returns directly after disabling round robin mode.
ASRC#
[2.1.5]#
New Features
Added common IRQ handler entry ASRC_CommonDriverIRQHandler.
[2.1.4]#
Improvements
Aligned clock source configuration for ASRC peripheral
[2.1.3]#
Bug Fixes
Fixed function did not match the specified channel pair issue.
[2.1.2]#
Improvements
Correct feature name in source file by changing FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM to FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASRPM.
Removed the asrc_clock_source_t from driver header file, as SOC header file will provide detail definition.
Bug Fixes
Fixed the ASRC_SetChannelPairConfig/ASRC_ChannelPairEnable functions missing functionality when using channel pair B/C.
Fixed violations of the MISRA C-2012 rules 10.7.
[2.1.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1，10.4, 12.2.
[2.1.0]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 10.1, 17.7, 11.9, 8.6, 12.2, 11.6.
[2.0.1]#
Improvements
Added feature macro FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM for ASRC parameter register.
Bug Fixes
Fixed the unused build warning in asrc edma driver.
[2.0.0]#
Initial version.
ASRC EDMA Driver#
[2.2.0]#
Bug Fixes
Fixed the “watermark” and “channel” was defined in struct asrc_p2p_edma_config_t but never used issue.
[2.1.0]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 10.1, 17.7, 11.9, 8.6, 12.2, 11.6.
[2.0.1]#
Improvements
Added feature macro FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM for ASRC parameter register.
Bug Fixes
Fixed the unused build warning in asrc edma driver.
[2.0.0]#
Initial version.
CRC#
[2.1.0]#
Bug fix:
Choosing CRC clocks from CRC clock array according to instance instead of hardcoded value.
[2.0.5]#
Bug fix:
Fix CERT-C issue with boolean-to-unsigned integer conversion.
[2.0.4]#
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]#
Bug fix:
Fix MISRA issues.
[2.0.2]#
Bug fix:
Fix MISRA issues.
[2.0.1]#
Bug fix:
DATA and DATALL macro definition moved from header file to source file.
[2.0.0]#
Initial version.
CSI#
[2.2.3]#
Bug Fixes
Added a DSB after the CSI CR1 interrupt-enable mask in CSI_TransferSubmitEmptyBuffer / CSI_TransferGetFullBuffer so the peripheral observes the masked state before the buffer queue is touched.
[2.2.2]#
Bug Fixes
Fixed CERT-C violations.
Fixed MISRA issues.
[2.2.1]#
New Features
Added common IRQ handler entry CSI_CommonDriverIRQHandler.
[2.2.0]#
Improvements
Update driver to invoke callback whenere there is a full frame received.
[2.1.5]#
Improvements
Updated for new CSI register and macro names.
[2.1.4]#
Improvements
Added memory address conversion to support buffers which could only be accessed using alias address by non-core masters.
[2.1.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.1.2]#
Improvements
Supported new CSI_Type register naming.
[2.1.1]#
Bug Fixes
Fixed IAR build warning Pa082.
Fixed violations of the MISRA C-2012 rules 8.4, 10.1, 10.3, 10.4, 10.6, 11.6, 14.4, 17.7.
[2.1.0]#
New Features
Added 16-bit and 24-bit data bus support.
Bug Fixes:
Fixed the bug that CSI writes to wrong buffer when empty buffer not submitted in time.
[2.0.3]#
Bug Fixes
Fixed wrong circular queue delta calculation.
Fixed double buffering capture issue where, when the transfer is ongoing and the device has empty buffer slot, the function CSI_TransferSubmitEmptyBuffer sets the empty buffer to CSI device.
[2.0.2]#
New Features
Added fragment mode support.
[2.0.1]#
Improvements
Switched DMA output buffer at the first data after each VSYNC. It originally happened when the DMA transfer was done.
[2.0.0]#
Initial version.
DAC#
[2.0.2]#
Bug Fixes
Fixed MISRA-2012 issues:
Rule 10.3, 10.8 and 17.7.
[2.0.1]#
Bug Fixes
Moved the default DAC_Enable(…, true) from DAC_Init() to the application code so that users can enable the DAC’s output.
[2.0.0]#
Initial version.
DCIF#
[2.1.1]#
Bug Fixes
Do not write the read-only CTRLDESC5_L1 register.
[2.1.0]#
Improvements
Support background layer 0.
[2.0.0]#
Initial version.
ENET#
[2.11.4]#
New Features
Added the parameterized common IRQ handlers ENET_CommonFrame0DriverIRQHandler and ENET_Ptp1588DriverIRQHandler, and bound the COMM__ENET vectors to them on i.MX RT2660.
[2.11.3]#
Bug Fixes
Fixed a condition in the receive path where software could read receive buffer descriptor fields directly while hardware/DMA could still be updating them.
[2.11.2]#
Improvements
Removed conditional compiling of kENET_RgmiiMode/kENET_MiiSpeed1000M definition.
[2.11.1]#
Bug Fixes
Fixed TX timestamp second value being incorrect when second rollover occurs between frame transmission and descriptor reclaim. The driver now reconstructs the correct second value by comparing TX nanoseconds with current nanoseconds, following the same pattern used for RX timestamps in SDK examples.
[2.11.0]#
New Features
Added function ENET_Ptp1588JumpTimer which adjusts the ENET PTP 1588 timer by jumping a relative time difference. Compared to ENET_Ptp1588SetTimer, this function yields more accurate results when the relative time difference between the PTP clock and the target clock is known.
[2.10.1]#
Bug Fixes
Fixed WAKEUP interrupt not being handled.
[2.10.0]#
New Features
Added function ENET_Ptp1588GetChannelCaptureValue to read last captured time from PTP 1588 timer.
[2.9.3]#
Bug Fixes
Fixed ENET_Ptp1588GetTimer incorrect timestamps when timer wraps occur after nanosecond capture:
Now only increments second field when nanosecond value is less than half a second
[2.9.2]#
Bug Fixes
RGMII mode is (temporarily) disabled before selecting between 10/100-Mbit/s and 1000-Mbit/s modes of operation. The bit RGMII_EN of RCR register must not be set while changing ECR register’s speed bit, otherwise there is a possibility of ENET IP ending in an incorrect state.
[2.9.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.4.
[2.9.0]#
Bug Fixes
Enabled collection of transfer statistics, so the function ENET_GetStatistics does not always return zeroes.
New Features
Added new function ENET_EnableStatistics to enable/disable collection of transfer statistics.
Added new function ENET_ResetStatistics to reset transfer statistics.
Improvements
Renamed the function ENET_ResetHareware to ENET_ResetHardware.
[2.8.0]#
New Features
Added the function to reset hardware on certain devices.
[2.7.1]#
Bug Fixes
Fixed the issue that free wrong buffer address when one frame stores in multiple buffers and memory pool is not enough to allocate these buffers to receive one complete frame.
[2.7.0]#
Improvements
Deleted deprecated zero copy Tx/Rx functions and set callback function which can be configured in ENET_Init.
Moved the Rx zero copy buffer allocation to Rx BD initialization function to reduce unnecessary looping code.
Bug Fixes
Fixed the issue that predefined Rx buffers which should not be used when enabling Rx zero copy are still be handled by cache operation, it causes hardfault on some platforms.
Fixed the issue that zero-copy Rx function doesn’t check Rx length of 0 in the BD with EMPTY bit is 0, it may occur in the corner case reported by customer. Not sure how it turns out, consider it as an ENET IP issue and drop this abnormal BD.
[2.6.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 11.6.
[2.6.2]#
Improvements
Changed ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler/ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler to ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler/ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler which represent ring 1 and ring 2.
[2.6.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 10.7, 11.6, 11.8.
[2.6.0]#
Improvements
Added MDIO access wrapper APIs for ease of use.
Fixed the build warning introduced by 64-bit compatibility patch.
[2.5.4]#
Improvements
Made the driver compatible with 64-bit platforms.
[2.5.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 11.6.
[2.5.2]#
Improvements
Updated the TXIC/RXIC register handling code according to the new header file.
[2.5.1]#
Bug Fixes
Fixed document typo.
[2.5.0]#
Bug Fixes
Fixed the SendFrame/SendFrameZeroCopy functions issue with scattered buffers.
Updated the formula of MDC calculation.
Used a feature macro to distinguish the old IP design from the new design, because old IP design always reads a value zero from ATCR->CAPTURE bit. For old IP, driver caculates and wait the necessary delay cycles after setting ATCR->CAPTURE then gets the timestamp value.
New Features
Added new zero copy Tx/Rx function.
New zero copy Tx function combines scattered and contiguous Tx buffer in one API, it also supports more Tx featrues which buffer descriptor supports but previous Tx function doesn’t support.
New zero copy Rx function use dynamic buffer mechanism and simpler interface.
Improvements
Corrected the interrupt handler for PTP timestamp IRQ and PTP1588 event IRQ since platform difference.
Added missing IRQ handlers for PTP1588 events on some platforms.
Corrected the max Tx frame length verification, it will not depend on a fixed macro. The ENET_FRAME_MAX_FRAMELEN is only an default value for driver, application can configure it. Driver caculates the limitation with the max frame length in register which may takes extended 4 or 8 bytes VLAN tag if VLAN/SVLAN enables.
Deleted deprecated Clause 45 read/write legacy APIs.
[2.4.3]#
Improvements
Aligned the IRQ handler name with header file.
[2.4.2]#
Bug Fixes
Fixed the MISRA issue of speculative out-of-bounds access.
[2.4.1]#
Bug Fixes
Fixed the PTP time capture issue.
[2.4.0]#
Improvements
Exposed API ENET_ReclaimTxDescriptor for user application to relaim tx descriptors in their application.
Added counter to record multicast hash conflict in struct _enet_handle, improved the situation that one multicast group could be left by other conflict multicast address left operation.
Improved concurrent usage of relaim and send frame operation.
[2.3.4]#
Bug Fixes
Fixed the issue that interrupt handler only checks the interrupt event flag but not checks interrupt mask flag.
[2.3.3]#
Bug Fixes
Fixed the issue that some compilers may choose the memcpy with 4-bit aligned address limitation due to the type of address pointer is ‘unsigned int *’, the data address doesn’t have to be 4-bit aligned.
[2.3.2]#
New Features
Added the feature that ENET driver can be used in the platform which integrates both 10/100M and 1G ENET IP.
Deleted duplicated code about ARM errata 838869 in first/second level IRQ handler.
[2.3.1]#
Improvements
Added function pointer checking in IRQ handler to make sure code can be used even it runs into the interrupt when the second level interupt handler is NULL.
[2.3.0]#
Bug Fixes
Fixed the issue that clause 45 MDIO read/write API doesn’t check the transmission over status between two transmissions.
Fixed violations of the MISRA C-2012 rules 2.2,10.3,10.4,10.7,11.6,11.8,13.5,14.4,15.7,17.7.
New Features
Added APIs to support send/receive frame with Zero-Copy.
Improvements
Separated the clock configuration from module configuration when init and deinit.
Added functions to set second level interrupt handler.
Provided new function to get 1588 timer count without disabling interrupt.
Improved timestamp controlling, deleted all old timestamp management APIs and data structures.
Merged the single/multiple ring(s) APIs, now these APIs can handle both.
Used base and index to control buffer descriptor, aligned with qos and lpc enet driver.
[2.2.6]#
Bug Fixes
Updated MII speed formula referring to the manual.
[2.2.5]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.7, 11.6, 11.9, 13.5, 14.4, 16.4, 17.7, 21.15, 3.1, 8.4.
Changed to use ARRAY_SIZE(s_enetBases) as the array size for s_ENETHandle, fixed the hardfault issue for using some ENET instance when ARRAY_SIZE(s_enetBases) is not same as FSL_FEATURE_SOC_ENET_COUNT.
[2.2.4]#
Improvements
Added call to Data Synchronization Barrier instruction before activating Tx/Rx buffer descriptor to ensure previous data update is completed.
Improved ENET_TransmitIRQHandler to store timestamps for multiple transmit buffer descriptors.
Bug Fixes
Fixed the issue that ENET_Ptp1588GetTimer did not handle the timer wrap situation.
[2.2.3]#
Improvements
Improved data buffer cache maintenance in the ENET driver.
[2.2.2]#
New Features
Added APIs for extended multi-ring support.
Added the AVB configure API for extended AVB feature support.
[2.2.1]#
Improvements
Changed the input data pointer attribute to const in ENET_SendFrame().
[2.1.1]#
New Features
Added the extended MDIO IEEE802.3 Clause 45 MDIO format SMI command APIs.
Added the extended interrupt coalescing feature.
Improvements
Combined all storage operations in the ENET_Init to ENET_SetHandler API.
[2.0.1]#
Bug Fixes
Used direct transmit busy check when doing data transmit.
Miscellaneous Changes
Updated IRQ handler work flow.
Changed the TX/RX interrupt macro from kENET_RxByteInterrupt to kENET_RxBufferInterrupt, from kENET_TxByteInterrupt to kENET_TxBufferInterrupt.
Deleted unnecessary parameters in ENET handler.
[2.0.0]#
Initial version.
ENET_QOS#
[2.7.7]#
Bug Fixes
Applied workaround for errata ERR050705 on MCXE32B/MCXE327: set the DDBF bit of the MTL_EST_CONTROL register when programming the gate control list to avoid incorrect Head-Of-Line blocking (HLBF) frame drops.
[2.7.6]#
New features
Added the parameterized common IRQ handler ENET_QOS_CommonDriverIRQHandler.
[2.7.5]#
New features
Added IRQ handler for the COMM__ENET_QOS peripheral on i.MX RT2660.
[2.7.4]#
Bug Fixes
Fixed ENET_QOS_EnableInterrupts to preserve already enabled interrupts.
Fixed ENET_QOS_DisableInterrupts to correctly manage interrupt summary bits.
Fixed IRQ handler to check interrupt enable status before processing events.
[2.7.3]#
Bug Fixes
Fixed the MISRA C-2012 issue rule 7.2, 17.12, 18.1.
[2.7.2]#
Bug Fixes
Not disabling ENET_QOS_ConfigureRxParser function when compiled for EMAC, as the MTL_RXP_INDIRECT_ACC_DATA register is writeable now.
[2.7.1]#
Bug Fixes
Fixed writing after DMA_CH array on platforms with smaller number of channels (EMAC).
[2.7.0]#
New features
The driver can work with EMAC IP now. EMAC is similar to ENET_QOS but doesn’t support 100 % of its features.
[2.6.5]#
Bug Fixes
Fixed ENET_QOS_GetMacAddr address byte order not matching ENET_QOS_SetMacAddr.
[2.6.4]#
Improvements
ENET_QOS_SetMII returns success or failure status now (related to i.MX RT1170 errata ERR050539 - ENET_QOS doesn’t support RMII 10Mbps mode).
Bug Fixes
Fixed the MISRA C-2012 issue rule 14.3.
[2.6.3]#
Bug Fixes
Fixed the issue that ENET_QOS_GetRxFrame, ENET_QOS_ReadFrame and ENET_QOS_DropFrame did not properly restart the receiving once it stopped.
[2.6.2]#
Bug Fixes
Fixed the issue that free wrong buffer address when one frame stores in multiple buffers and memory pool is not enough to allocate these buffers to receive one complete frame.
[2.6.1]#
Bug Fixes
Fixed the issue that ENET_QOS_ReadFrame doesn’t check timestamp available bit before check the context BD bit, it makes software update extra BD. If DMA receives new frame to this BD before software update, software will lose this frame.
[2.6.0]#
New features
Added hardware checksum acceleration support.
[2.5.3]#
Bug Fixes
Fixed the MISRA issue rule 14.3, 5.3.
[2.5.2]#
Bug Fixes
Fixed the issue that ENET_QOS_Init reset the MDIO setting of ENET_QOS_SetSMI.
[2.5.1]#
Improvements
Supported RMII mode.
[2.5.0]#
Improvements
Added MDIO access wrapper APIs for ease of use.
[2.4.1]#
Improvements
Supported cache control.
Supported BD address convertion to system address.
Make driver aarch64 compatible
Bug Fixes
Fixed the issue that driver internal interface ENET_QOS_DropFrame drops all frames in whole BD ring rather than one frame as design. Impact case: 1. Rx drop occurs in zero copy Rx API ENET_QOS_GetRxFrame. 2. Call ENET_QOS_ReadFrame with data pointer is NULL, driver will drop all Rx frames.
[2.4.0]#
New features
Added MDIO IEEE802.3 Clause 45 access support.
Added get statistics API to get some statistical data in transfer.
Added new APIs to support zero copy Rx.
Fixed the MISRA issue rule 8.4, 8.6.
[2.3.0]#
Improvements
Added counter to record multicast hash conflict in struct _enet_handle, improved the situation that one multicast group could be left by other conflict multicast address left operation.
Bug Fixes
Updated txDirtyRing maintenance in reclaim and send frame process, allow txDirtyRing to be overwritten.
Disabled carrier sensing in full duplex mode configuration in ethernet initialization
Fixed 1588 sub-second calculate issue.
[2.2.2]#
Bug Fixes
Fixed the issue that ENET_QOS_SetupTxDescriptor didn’t handle the DMA access address mapping for SoCs have feature FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET.
Fixed MISRA 2012 violations detected in examples build.
[2.2.1]#
Bug Fixes
Fixed MISRA 2012 violations, fixed doxygen warning.
Fixed the issue that cache invalidate to invalid converted memory address in ENET_QOS_ReadFrame for SoCs have feature FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET.
[2.2.0]#
Removed the ptp time data ring management, below structures and APIs are removed:
structure enet_qos_ptp_time_data_t
structure enet_qos_ptp_time_data_ring_t
API ENET_QOS_GetRxFrameTime
API ENET_QOS_GetTxFrameTime
Added API for GCL list read and AVB configuration
ENET_QOS_EstReadGcl
ENET_QOS_AVBConfigure
Improved driver for PTP system time configuration, timestamp read.
Added IRQ lock and memory barrier instruction for descriptor operation.
Fixed MISRA 2012 violations
[2.1.1]#
Bug Fixes
Fixed the bug that data pointer is not converted to local memory address in the call to ENET_QOS_Ptp1588ParseFrame.
[2.1.0]#
New feature
Update driver to support feature FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET which convert buffer address to visible address for DMA.
Require user to provide implementation for ENET_QOS_SetSYSControl API, which set the PHY interface and enable clock generation for IP.
[2.0.0]#
Initial version.
EQDC#
[2.3.2]#
Bug Fix
Fixed violations of the CERT INT31-C.
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.8.
[2.3.1]#
Bug Fix
Fixed CTRL2[CMODE] field overwritten in API EQDC_Init.
[2.3.0]#
Improvements
Add feature macro to support platforms which do not have compare interrupt.
[2.2.3]#
Bug Fix
Clear Revolution Counter Register(REV) in init function to prevent its value not equal to zero after reset.
[2.2.2]#
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]#
Bug Fix
Fixed violations of the MISRA C-2012 rules 20.9.
[2.2.0]#
New features
Supported the feature that the position counter to be initialized by Index Event Edge Mark.
[2.1.0]#
Bug Fix
Fixed typo in interrupt enumeration values.
Improvements
Supported Count Direct Change interrupt.
Removed unused parameter in user configuration.
Supported ERRATA_051383 check, the CTRL[DMAEN] can’t be cleared.
[2.0.1]#
Bug Fix
Fixed violations of the MISRA C-2012 rules 10.3, 10.6, 10.8, 14.4, 16.4.
[2.0.0]#
Initial version.
EVTG#
[2.1.0]#
Improvements
Enabled the EVTG peripheral clock inside EVTG_Init() (guarded by EVTG_CLOCKS and FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL), so the driver no longer relies on the application to ungate the clock.
Added EVTG_Deinit() to gate the EVTG peripheral clock, as the counterpart of EVTG_Init().
[2.0.3]#
Bug Fixes
Fixed coverity issues with CERT INT30-C, CERT INT31-C compliance.
[2.0.2]#
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8.
[2.0.1]#
Bug Fixes
MISRA C-2012 issue fixed: rule 10.7,15.7,10.1,10.4,10.8,10.3,16.1,16.3 .
[2.0.0]#
Initial version.
EWM#
[2.0.4]#
Bug Fixes
Fixed CERT INT31-C violations.
[2.0.3]#
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.1, 10.3.
[2.0.2]#
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.3, 10.4.
[2.0.1]#
Bug Fixes
Fixed the hard fault in EWM_Deinit.
[2.0.0]#
Initial version.
FLEXCAN#
[2.16.0]#
Improvements
Added four new members to
flexcan_config_tso that the previously hard-coded register values can now be configured by the application:enableThreeSamplingMode- controls CTRL1[SMP]; defaulttrue(backward compatible).disableBusOffAutoRecovery- controls CTRL1[BOFFREC]; defaultfalse(backward compatible).txArbitrationStartDelay- controls CTRL2[TASD] (0–31 Tq); default0x16(backward compatible).enableEntireArbitrationCompare- controls CTRL2[EACEN]; defaulttrue(backward compatible).
Remove above unconditionally overwritten hard-coded registers value from
FLEXCAN_Reset.
[2.15.2]#
Bug Fixes
Fixed violations of the CERT INT31-C.
[2.15.1]#
Improvements
Wait for RX Message Buffer busy state cleared before reading in following APIs.
FLEXCAN_ReadRxMbFLEXCAN_ReadFDRxMb
Simplify RX Message Buffer handling sequence in interrupt handler
FLEXCAN_SubHandlerForMB.Aligned watermark comparison logic between
FLEXCAN_EnhancedRxFifoHandleIRQandFLEXCAN_TransferReceiveEnhancedFifoNonBlockingfor consistency.Fixed
Ehancedtypo issue.Remove redundant feature macro for FlexCAN engine clock selection in
FLEXCAN_Init.
Bug Fixes
Fixed Enhanced Rx FIFO filter configuration assertion
idFilterPairNuminFLEXCAN_SetEnhancedRxFifoConfig.Fixed Bus Off Done interrupt and Data Phase of Fast CAN FD Frames Error interrupt enable mask shift for CTRL2 register.
Fixed Enhanced Rx FIFO interrupt enable and status flag comparing issue in
FLEXCAN_EnhancedRxFifoHandleIRQ.
[2.15.0]#
Improvements
Add remote request and response non-blocking transfer APIs.
FLEXCAN_TransferRemoteRequestNonBlockingFLEXCAN_TransferRemoteResponseNonBlocking
Bug Fixes
Fixed improper CS code when configuring FlexCAN Remote Response Message Buffer in
FLEXCAN_SetRemoteResponseMbConfig.
[2.14.7]#
Improvements
Add Coverage Justification for uncovered code.
Bug Fixes
Fixed violations of the CERT INT30-C INT31-C.
[2.14.6]#
Bug Fixes
Fixed MCR register reconfiguration failure after FlexCAN soft reset on some platforms.
[2.14.5]#
Improvements
Make API
FLEXCAN_GetFDMailboxOffsetpublic.Add API
FLEXCAN_SetMbIDandFLEXCAN_SetFDMbIDto configure Message Buffer ID individually.
Bug Fixes
Fixed violations of the CERT INT30-C INT31-C.
Fixed violations of the CERT ARR30-C.
[2.14.4]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.1, 10.4, 18.1.
[2.14.3]#
Improvements
Add unhandled interrupt events check for following API:
FLEXCAN_MbHandleIRQFLEXCAN_EhancedRxFifoHandleIRQ
Bug Fixes
Remove
FLEXCAN_MemoryErrorHandleIRQon some platform without memory error interrupt.Add conditional compile for CTRL2[ISOCANFDEN] because some platform do not have this bit.
[2.14.2]#
Improvements
Add Coverage Justification for uncovered code.
Adjust API
FLEXCAN_TransferAbortReceiveorder.Update
FLEXCAN_Enableto enter Freeze Mode first when enter Disable mode on some platform.Added while loop timeout for following API:
FLEXCAN_EnterFreezeModeFLEXCAN_ExitFreezeModeFLEXCAN_EnableFLEXCAN_ResetFLEXCAN_TransferSendBlockingFLEXCAN_TransferReceiveBlockingFLEXCAN_TransferFDSendBlockingFLEXCAN_TransferFDReceiveBlockingFLEXCAN_TransferReceiveFifoBlockingFLEXCAN_TransferReceiveEnhancedFifoBlocking
Bug Fixes
Remove remote frame feature in CANFD mode because there is no remote frame in the CANFD format.
Remove legacy Rx FIFO disabled branch in
FLEXCAN_SubHandlerForLegacyRxFIFOandFLEXCAN_SubHandlerForDataTransfered.
[2.14.1]#
Bug Fixes
Fixed register
IMASK2-4IFLAG2-4HR_TIME_STAMPnaccess issue on FlexCAN instances with different number of MBs.Fixed bit field
MBDSR1-3access issue on FlexCAN instances with different number of MBs.
Improvements
Unified following API as same parameter and return value type:
FLEXCAN_GetMbStatusFlagsFLEXCAN_ClearMbStatusFlagsFLEXCAN_EnableMbInterruptsFLEXCAN_DisableMbInterrupts
Add workaround for ERR050443 and ERR052403.
Update message buffer read process in API
FLEXCAN_ReadRxMbandFLEXCAN_ReadFDRxMbto make critical section as short as possible.Simplify API
FLEXCAN_DriverDataIRQHandlerimplementation by remove parametertype.
[2.14.0]#
Improvements
Support external time tick feature.
Support high resolution timestamp feature.
Enter Freeze Mode first when enter Disable Mode on some platform.
Add feature macro for Pretended Networking because some FlexCAN instance do not have this feature.
Add feature macro for enhanced Rx FIFO because some FlexCAN instance do not have this feature.
Add new FlexCAN IRQ Handler FLEXCAN_DriverDataIRQHandler and FLEXCAN_DriverEventIRQHandler. Thses IRQ Handlers are used on soc which FlexCAN interrupts are grouped by specific function and assigned to different vector.
Update macro FLEXCAN_WAKE_UP_FLAG and FLEXCAN_PNWAKE_UP_FLAG to simplify code.
Replace macro FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT with FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT.
Replace macro FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT with FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER.
Bug Fixes
Fixed wrong interrupt and status flag helper macro in enumeration _flexcan_flags and API FLEXCAN_DisableInterrupts.
Fixed interrupt flag helper macro typo issue.
Remove flags which will are unassociated with interrupt in macro FLEXCAN_MEMORY_ERROR_INT_FLAG.
Remove flags which will are unassociated with interrupt in macro FLEXCAN_ERROR_AND_STATUS_INT_FLAG.
Fixed array out-of-bounds access when read enhanced Rx FIFO.
[2.13.1]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]#
Improvements
Support payload endianness selection feature.
[2.12.0]#
Improvements
Support automatic Remote Response feature.
Add API FLEXCAN_SetRemoteResponseMbConfig() to configure automatic Remote Response mailbox.
[2.11.8]#
Improvements
Synchronize flexcan driver update on s32z platform.
[2.11.7]#
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compatibility with edma5.
[2.11.6]#
Bug Fixes
Fixed ERRATA_9595 FLEXCAN_EnterFreezeMode() may result to bus fault on some platform.
[2.11.5]#
Bug Fixes
Fixed flexcan_memset() crash under high optimization compilation.
[2.11.4]#
Improvements
Update CANFD max bitrate to 10Mbps on MCXNx3x and MCXNx4x.
Release peripheral from reset if necessary in init function.
[2.11.3]#
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compile error with DMA3.
[2.11.2]#
Bug Fixes
Fixed bug that timestamp in flexcan_handle_t not updated when RX overflow happens.
[2.11.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
[2.11.0]#
Bug Fixes
Fixed wrong base address argument in FLEXCAN2 IRQ Handler.
Improvements
Add API to determine if the instance supports CAN FD mode at run time.
[2.10.1]#
Bug Fixes
Fixed HIS CCM issue.
Fixed RTOS issue by adding protection to read-modify-write operations on interrupt enable/disable API.
[2.10.0]#
Improvements
Update driver to make it able to support devices which has more than 64 8bytes MBs.
Update CAN FD transfer APIs to make them set/get edl bit according to frame content, which can make them compatible with classic CAN.
[2.9.2]#
Bug Fixes
Fixed the issue that FLEXCAN_CheckUnhandleInterruptEvents() can’t detecting the exist enhanced RX FIFO interrupt status.
Fixed the issue that FLEXCAN_ReadPNWakeUpMB() does not return fail even no existing valid wake-up frame.
Fixed the issue that FLEXCAN_ReadEnhancedRxFifo() may clear bits other than the data available bit.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8.
Improvements
Return kStatus_FLEXCAN_RxFifoDisabled instead of kStatus_Fail when read FIFO fail during IRQ handler.
Remove unreachable code from timing calculates APIs.
Update Enhanced Rx FIFO handler to make it deal with underflow/overflow status first.
[2.9.1]#
Bug Fixes
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoBlocking() API clearing Fifo data available flag more than once.
Fixed the issue that entering FLEXCAN_SubHandlerForEhancedRxFifo() even if Enhanced Rx fifo interrupts are not enabled.
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoEDMA() update handle even if previous Rx FIFO receive not finished.
Fixed the issue that FLEXCAN_SetEnhancedRxFifoConfig() not configure the ERFCR[NFE] bits to the correct value.
Fixed the issue that FLEXCAN_ReceiveFifoEDMACallback() can’t differentiate between Rx fifo and enhanced rx fifo.
Fixed the issue that FLEXCAN_TransferHandleIRQ() can’t report Legacy Rx FIFO warning status.
[2.9.0]#
Improvements
Add public set bit rate API to make driver easier to use.
Update Legacy Rx FIFO transfer APIs to make it support received multiple frames during one API call.
Optimized FLEXCAN_SubHandlerForDataTransfered() API in interrupt handling to reduce the probability of packet loss.
[2.8.7]#
Improvements
Initialized the EDMA configuration structure in the FLEXCAN EDMA driver.
[2.8.6]#
Bug Fixes
Fix Coverity overrun issues in fsl_flexcan_edma driver.
[2.8.5]#
Improvements
Make driver aarch64 compatible.
[2.8.4]#
Bug Fixes
Fixed FlexCan_Errata_6032 to disable all interrupts.
[2.8.3]#
Bug Fixes
Fixed an issue with the FLEXCAN_EnableInterrupts and FLEXCAN_DisableInterrupts interrupt enable bits in the CTRL1 register.
[2.8.2]#
Bug Fixes
Fixed errors in timing calculations and simplify the calculation process.
Fixed issue of CBT and FDCBT register may write failure.
[2.8.1]#
Bug Fixes
Fixed the issue of CAN FD three sampling points.
Added macro to support the devices that no MCR[SUPV] bit.
Remove unnecessary clear WMB operations.
[2.8.0]#
Improvements
Update config configuration.
Added enableSupervisorMode member to support enable/disable Supervisor mode.
Simplified the algorithm in CAN FD improved timing APIs.
[2.7.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.7.
[2.7.0]#
Improvements
Update config configuration.
Added enablePretendedeNetworking member to support enable/disable Pretended Networking feature.
Added enableTransceiverDelayMeasure member to support enable/disable Transceiver Delay MeasurementPretended feature.
Added bitRate/bitRateFD member to work as baudRate/baudRateFD member union.
Rename all “baud” in code or comments to “bit” to align with the CAN spec.
Added Pretended Networking mode related APIs.
FLEXCAN_SetPNConfig
FLEXCAN_GetPNMatchCount
FLEXCAN_ReadPNWakeUpMB
Added support for Enhanced Rx FIFO.
Removed independent memory error interrupt/status APIs and put all interrupt/status control operation into FLEXCAN_EnableInterrupts/FLEXCAN_DisableInterrupts and FLEXCAN_GetStatusFlags/FLEXCAN_ClearStatusFlags APIs.
Update improved timing APIs to make it calculate improved timing according to CiA doc recommended.
FLEXCAN_CalculateImprovedTimingValues.
FLEXCAN_FDCalculateImprovedTimingValues.
Update FLEXCAN_SetBitRate/FLEXCAN_SetFDBitRate to added the use of enhanced timing registers.
[2.6.2]#
Improvements
Add CANFD frame data length enumeration.
[2.6.1]#
Bug Fixes
Fixed the issue of not fully initializing memory in FLEXCAN_Reset() API.
[2.6.0]#
Improvements
Enable CANFD ISO mode in FLEXCAN_FDInit API.
Enable the transceiver delay compensation feature when enable FD operation and set bitrate switch.
Implementation memory error control in FLEXCAN_Init API.
Improve FLEXCAN_FDCalculateImprovedTimingValues API to get same value for FPRESDIV and PRESDIV.
Added memory error configuration for user.
enableMemoryErrorControl
enableNonCorrectableErrorEnterFreeze
Added memory error related APIs.
FLEXCAN_GetMemoryErrorReportStatus
FLEXCAN_GetMemoryErrorStatusFlags
FLEXCAN_ClearMemoryErrorStatusFlags
FLEXCAN_EnableMemoryErrorInterrupts
FLEXCAN_DisableMemoryErrorInterrupts
Bug Fixes
Fixed the issue of sent duff CAN frame after call FLEXCAN_FDInit() API.
[2.5.2]#
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
The bit field in CTRL1 register couldn’t calculate higher ideal SP, we set it as the lowest one(75%)
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
Fixed MISRA-C 2012 Rule 17.7 and 14.4.
Improvements
Pass EsrStatus to callback function when kStatus_FLEXCAN_ErrorStatus is comming.
[2.5.1]#
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
[2.5.0]#
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-11.8, rule-12.2, rule-13.4, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-16.4, rule-17.3, rule-5.8, rule-8.3, rule-8.5.
Fixed the issue that API FLEXCAN_SetFDRxMbConfig lacks inactive message buff.
Fixed the issue of Pa082 warning.
Fixed the issue of dead lock in the function of interruption handler.
Fixed the issue of Legacy Rx Fifo EDMA transfer data fail in evkmimxrt1060 and evkmimxrt1064.
Fixed the issue of setting CANFD Bit Rate Switch.
Fixed the issue of operating unknown pointer risk.
when used the pointer “handle->mbFrameBuf[mbIdx]” to update the timestamp in a short-live TX frame, the frame pointer became as unknown, the action of operating it would result in program stack destroyed.
Added assert to check current CAN clock source affected by other clock gates in current device.
In some chips, CAN clock sources could be selected by CCM. But for some clock sources affected by other clock gates, if user insisted on using that clock source, they had to open these gates at the same time. However, they should take into consideration the power consumption issue at system level. In RT10xx chips, CAN clock source 2 was affected by the clock gate of lpuart1. ERRATA ID: (ERR050235 in CCM).
Improvements
Implementation for new FLEXCAN with ECC feature able to exit Freeze mode.
Optimized the function of interruption handler.
Added two APIs for FLEXCAN EDMA driver.
FLEXCAN_PrepareTransfConfiguration
FLEXCAN_StartTransferDatafromRxFIFO
Added new API for FLEXCAN driver.
FLEXCAN_GetTimeStamp
For TX non-blocking API, we wrote the frame into mailbox only, so no need to register TX frame address to the pointer, and the timestamp could be updated into the new global variable handle->timestamp[mbIdx], the FLEXCAN driver provided a new API for user to get it by handle and index number after TX DONE Success.
FLEXCAN_EnterFreezeMode
FLEXCAN_ExitFreezeMode
Added new configuration for user.
disableSelfReception
enableListenOnlyMode
Renamed the two clock source enum macros based on CLKSRC bit field value directly.
The CLKSRC bit value had no property about Oscillator or Peripheral type in lots of devices, it acted as two different clock input source only, but the legacy enum macros name contained such property, that misled user to select incorrect CAN clock source.
Created two new enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrc0
kFLEXCAN_ClkSrc1
Deprecated two legacy enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrcOsc
kFLEXCAN_ClkSrcPeri
Changed the process flow for Remote request frame response..
Created a new enum macro for the FLEXCAN driver.
kStatus_FLEXCAN_RxRemote
Changed the process flow for kFLEXCAN_StateRxRemote state in the interrupt handler.
Should the TX frame not register to the pointer of frame handle, interrupt handler would not be able to read the remote response frame from the mail box to ram, so user should read the frame by manual from mail box after a complete remote frame transfer.
[2.4.0]#
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-12.1, rule-17.7, rule-16.4, rule-11.9, rule-8.4, rule-14.4, rule-10.8, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-8.3, rule-12.2 and rule-16.1.
Fixed the issue that CANFD transfer data fail when bus baudrate is 30Khz.
Fixed the issue that ERR009595 does not folllow the ERRATA document.
Fixed code error for ERR006032 work around solution.
Fixed the Coverity issue of BAD_SHIFT in FLEXCAN.
Fixed the Repo build warning issue for variable without initial.
Improvements
Fixed the run fail issue of FlexCAN RemoteRequest UT Case.
Implementation all TX and RX transfering Timestamp used in FlexCAN demos.
Fixed the issue of UT Test Fail for CANFD payload size changed from 64BperMB to 8PerMB.
Implementation for improved timing API by baud rate.
[2.3.2]#
Improvements
Implementation for ERR005959.
Implementation for ERR005829.
Implementation for ERR006032.
[2.3.1]#
Bug Fixes
Added correct handle when kStatus_FLEXCAN_TxSwitchToRx is comming.
[2.3.0]#
Improvements
Added self-wakeup support for STOP mode in the interrupt handling.
[2.2.3]#
Bug Fixes
Fixed the issue of CANFD data phase’s bit rate not set as expected.
[2.2.2]#
Improvements
Added a time stamp feature and enable it in the interrupt_transfer example.
[2.2.1]#
Improvements
Separated CANFD initialization API.
In the interrupt handling, fix the issue that the user cannot use the normal CAN API when with an FD.
[2.2.0]#
Improvements
Added FSL_FEATURE_FLEXCAN_HAS_SUPPORT_ENGINE_CLK_SEL_REMOVE feature to support SoCs without CAN Engine Clock selection in FlexCAN module.
Added FlexCAN Serial Clock Operation to support i.MX SoCs.
[2.1.0]#
Bug Fixes
Corrected the spelling error in the function name FLEXCAN_XXX().
Moved Freeze Enable/Disable setting from FLEXCAN_Enter/ExitFreezeMode() to FLEXCAN_Init().
Corrected wrong helper macro values.
Improvements
Hid FLEXCAN_Reset() from user.
Used NDEBUG macro to wrap FLEXCAN_IsMbOccupied() function instead of DEBUG macro.
[2.0.0]#
Initial version.
FLEXCAN_EDMA#
[2.12.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 18.1.
[2.12.0]#
Improvements
Support high resolution timestamp feature in enhanced Rx FIFO EDMA.
Add feature macro for enhanced Rx FIFO because some FlexCAN instance do not have this feature.
Bug Fixes
Fixed array out-of-bounds access when read enhanced Rx FIFO in EDMA.
[2.11.7]#
Refer FLEXCAN driver change log 2.7.0 to 2.11.7
FLEXIO#
[2.3.2]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.3.1]#
New Features
Added common IRQ handler entry FLEXIO_CommonDriverIRQHandler.
[2.3.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
Added more pin control functions.
[2.2.3]#
Improvements
Adapter the FLEXIO driver to platforms which don’t have system level interrupt controller, such as NVIC.
[2.2.2]#
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]#
Improvements
Added doxygen index parameter comment in FLEXIO_SetClockMode.
[2.2.0]#
New Features
Added new APIs to support FlexIO pin register.
[2.1.0]#
Improvements
Added API FLEXIO_SetClockMode to set flexio channel counter and source clock.
[2.0.4]#
Bug Fixes
Fixed MISRA 8.4 issues.
[2.0.3]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.2]#
Improvements
Split FLEXIO component which combines all flexio/flexio_uart/flexio_i2c/flexio_i2s drivers into several components: FlexIO component, flexio_uart component, flexio_i2c_master component, and flexio_i2s component.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.0.1]#
Bug Fixes
Fixed the dozen mode configuration error in FLEXIO_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
FLEXIO_A-FORMAT#
[1.0.0]#
New Features
The polling mode was added to read or configure encoder data
The interrupt mode was added to read or configure encoder data
FLEXIO_BISS#
[1.0.0]#
New Features
The polling mode was added to read or configure encoder data
The sync mode was added to read or configure encoder data
FLEXIO_CAMERA#
[2.2.1]#
Bug Fixes
Fixed INT30-C INT31-C issues.
Set SHIFTCFG[LATST]=1 on devices where the bit is available, so each shifter stores its post-shift state and captures the final byte of the chain.
[2.2.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.1.3]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.1.2]#
Improvements
Unified component full name to FLEXIO CAMERA (EDMA) driver.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.1]#
Bug Fixes
The following modifications support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.1.0]#
New Features
Added Transfer prefix in transactional APIs.
FLEXIO ENDAT2P2#
[1.0.0]#
Initial version.
FLEXIO_I2C#
[2.6.3]#
Bug Fixes
Fixed MISRA 10.4, 10.7 and 14.4 issues.
[2.6.2]#
Improvements
Added timeout for while loop in FLEXIO_I2C_MasterTransferBlocking().
Bug Fixes
Fixed build issues related to I2C_RETRY_TIMES.
[2.6.1]#
Bug Fixes
Fixed coverity issues
[2.6.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]#
Improvements
Split some functions, fixed CCM problem in file fsl_flexio_i2c_master.c.
[2.4.0]#
Improvements
Added delay of 1 clock cycle in FLEXIO_I2C_MasterTransferRunStateMachine to ensure that bus would be idle before next transfer if master is nacked.
Fixed issue that the restart setup time is less than the time in I2C spec by adding delay of 1 clock cycle before restart signal.
[2.3.0]#
Improvements
Used 3 timers instead of 2 to support transfer which is more than 14 bytes in single transfer.
Improved FLEXIO_I2C_MasterTransferGetCount so that the API can check whether the transfer is still in progress.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.2.0]#
New Features
Added timeout mechanism when waiting certain state in transfer API.
Added an API for checking bus pin status.
Bug Fixes
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
Added codes in FLEXIO_I2C_MasterTransferCreateHandle to clear pending NVIC IRQ, disable internal IRQs before enabling NVIC IRQ.
Modified code so that during master’s nonblocking transfer the start and slave address are sent after interrupts being enabled, in order to avoid potential issue of sending the start and slave address twice.
[2.1.7]#
Bug Fixes
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking did not wait for STOP bit sent.
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed the issue that I2C master did not check whether bus was busy before transfer.
[2.1.6]#
Bug Fixes
Fixed the issue that I2C Master transfer APIs(blocking/non-blocking) did not support the situation of master transfer with subaddress and transfer data size being zero, which means no data followed the subaddress.
[2.1.5]#
Improvements
Unified component full name to FLEXIO I2C Driver.
[2.1.4]#
Bug Fixes
The following modifications support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.3]#
Improvements
Changed the prototype of FLEXIO_I2C_MasterInit to return kStatus_Success if initialized successfully or to return kStatus_InvalidArgument if “(srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1” exceeds 0xFFU.
[2.1.2]#
Bug Fixes
Fixed the FLEXIO I2C issue where the master could not receive data from I2C slave in high baudrate.
Fixed the FLEXIO I2C issue where the master could not receive NAK when master sent non-existent addr.
Fixed the FLEXIO I2C issue where the master could not get transfer count successfully.
Fixed the FLEXIO I2C issue where the master could not receive data successfully when sending data first.
Fixed the Dozen mode configuration error in FLEXIO_I2C_MasterInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking API called FLEXIO_I2C_MasterTransferCreateHandle, which lead to the s_flexioHandle/s_flexioIsr/s_flexioType variable being written. Then, if calling FLEXIO_I2C_MasterTransferBlocking API multiple times, the s_flexioHandle/s_flexioIsr/s_flexioType variable would not be written any more due to it being out of range. This lead to the following situation: NonBlocking transfer APIs could not work due to the fail of register IRQ.
[2.1.1]#
Bug Fixes
Implemented the FLEXIO_I2C_MasterTransferBlocking API which is defined in header file but has no implementation in the C file.
[2.1.0]#
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S#
[2.2.2]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 12.4.
[2.2.1]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.2.0]#
New Features
Added timeout mechanism when waiting certain state in transfer API.
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed violations of the MISRA C-2012 rules 10.4, 14.4, 11.8, 11.9, 10.1, 17.7, 11.6, 10.3, 10.7.
[2.1.6]#
Bug Fixes
Added reset flexio before flexio i2s init to make sure flexio status is normal.
[2.1.5]#
Bug Fixes
Fixed the issue that I2S driver used hard code for bitwidth setting.
[2.1.4]#
Improvements
Unified component’s full name to FLEXIO I2S (DMA/EDMA) driver.
[2.1.3]#
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]#
New Features
Added configure items for all pin polarity and data valid polarity.
Added default configure for pin polarity and data valid polarity.
[2.1.1]#
Bug Fixes
Fixed FlexIO I2S RX data read error and eDMA address error.
Fixed FlexIO I2S slave timer compare setting error.
[2.1.0]#
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S_EDMA#
[2.1.9]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 12.4.
[2.1.8]#
Improvements
Applied EDMA ERRATA 51327.
FLEXIO_MCU_LCD#
[2.3.0]#
New Features
Supported passing an extra user defined parameter to GPIO functions to control the CS/RS/RDWR pin signal.
[2.2.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.1.0]#
New Features
Supported transmit only data without command.
[2.0.8]#
Bug Fixes
Fixed bug that FLEXIO_MCULCD_Init return kStatus_Success even with invalid parameter.
Fixed glitch on WR, that when initially configure the timer pin as output, or change the pin back to disabled, the pin may be driven low causing glitch on bus. Configure the pin as bidirection output first then perform a subsequent write to change to output or dsiabled to avoid the issue.
[2.0.6]#
Bug Fixes
Fixed MISRA 10.4 issues when FLEXIO_MCULCD_DATA_BUS_WIDTH defined as signed value.
[2.0.5]#
Improvements
Changed FLEXIO_MCULCD_WriteDataArrayBlocking’s data parameter to const type.
[2.0.4]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.2]#
Improvements
Unified component full name to FLEXIO_MCU_LCD (EDMA) driver.
[2.0.1]#
Bug Fixes
The following modification to support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.0.0]#
Initial version.
FLEXIO_MCU_LCD_DMA#
[2.0.6]#
New Features
Supported passing an extra user defined parameter to GPIO functions to control the RDWR pin signal.
[2.0.5]#
New Features
Supported transmit only data without command.
[2.0.4]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.2]#
Improvements
Unified component full name to FLEXIO_MCU_LCD (EDMA) driver.
[2.0.1]#
Bug Fixes
The following modification to support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.0.0]#
Initial version.
FLEXIO_MCU_LCD_EDMA#
[2.0.6]#
New Features
Supported passing an extra user defined parameter to GPIO functions to control the RDWR pin signal.
[2.0.5]#
New Features
Supported transmit only data without command.
[2.0.4]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.2]#
Improvements
Unified component full name to FLEXIO_MCU_LCD (EDMA) driver.
[2.0.1]#
Bug Fixes
The following modification to support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.0.0]#
Initial version.
FLEXIO_MCU_LCD_SMARTDMA#
[2.0.7]#
Other Changes
Add more MCXA devices support.
[2.0.6]#
Other Changes
Add more MCXA devices support.
[2.0.5]#
Other Changes
Supported the MCXA platforms.
New Features
Supported passing an extra user defined parameter to GPIO functions to control the RDWR pin signal.
[2.0.4]#
New Features
Supported the platforms which use FlexIO SHIFTER DMA to trigger SmartDMA, such as MCXN235, MCXN236.
[2.0.3]#
New Features
Supported transmit only data without command.
[2.0.2]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 14.4, 17.7.
[2.0.1]#
Other Changes
Update driver implementation due to SMARTDMA driver update.
[2.0.0]#
Initial version.
FLEXIO_QSPI#
[2.1.1]#
Bug Fixes
Fix FlexIO QSPI MDK build warning
[2.1.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.0.0]#
New Features
Simplex QSPI.
FLEXIO_QSPI_EDMA#
[2.0.0]#
New Features
Simplex QSPI.
FLEXIO_QSPI_SMARTDMA#
[2.0.2]#
Bug Fixes
Fix FlexIO QSPI MDK build warning
[2.0.1]#
Improvements
Update driver to work with SmartDMA driver 2.11.0.
[2.0.0]#
New Features
Simplex QSPI.
FLEXIO_SPI#
[2.4.4]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.4.3]#
Improvements
Make SPI_RETRY_TIMES configurable by CONFIG_SPI_RETRY_TIMES.
[2.4.2]#
Bug Fixes
Fixed
FLEXIO_SPI_MasterTransferBlockingandFLEXIO_SPI_MasterTransferNonBlockingissue in CS continuous mode, the CS might not be continuous.
[2.4.1]#
Bug Fixes
Fixed coverity issues
[2.4.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.3.5]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.4]#
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.3]#
Bugfixes
Fixed cs-continuous mode.
[2.3.2]#
Improvements
Changed FLEXIO_SPI_DUMMYDATA to 0x00.
[2.3.1]#
Bugfixes
Fixed IRQ SHIFTBUF overrun issue when one FLEXIO instance used as multiple SPIs.
[2.3.0]#
New Features
Supported FLEXIO_SPI slave transfer with continuous master CS signal and CPHA=0.
Supported FLEXIO_SPI master transfer with continuous CS signal.
Support 32 bit transfer width.
Bug Fixes
Fixed wrong timer compare configuration for dma/edma transfer.
Fixed wrong byte order of rx data if transfer width is 16 bit, since the we use shifter buffer bit swapped/byte swapped register to read in received data, so the high byte should be read from the high bits of the register when MSB.
[2.2.1]#
Bug Fixes
Fixed bug in FLEXIO_SPI_MasterTransferAbortEDMA that when aborting EDMA transfer EDMA_AbortTransfer should be used rather than EDMA_StopTransfer.
[2.2.0]#
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
Added codes in FLEXIO_SPI_MasterTransferCreateHandle and FLEXIO_SPI_SlaveTransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.1.3]#
Improvements
Unified component full name to FLEXIO SPI(DMA/EDMA) Driver.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.2]#
Bug Fixes
The following modification support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.1]#
Bug Fixes
Fixed bug where FLEXIO SPI transfer data is in 16 bit per frame mode with eDMA.
Fixed bug when FLEXIO SPI works in eDMA and interrupt mode with 16-bit per frame and Lsbfirst.
Fixed the Dozen mode configuration error in FLEXIO_SPI_MasterInit/FLEXIO_SPI_SlaveInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Improvements
Added #ifndef/#endif to allow users to change the default TX value at compile time.
[2.1.0]#
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
Bug Fixes
Fixed the error register address return for 16-bit data write in FLEXIO_SPI_GetTxDataRegisterAddress.
Provided independent IRQHandler/transfer APIs for Master and slave to fix the baudrate limit issue.
FLEXIO_T-FORMAT#
[1.0.0]#
New Features
The polling mode was added to read or configure encoder data
The interrupt mode was added to read or configure encoder data
FLEXIO_UART#
[2.6.5]#
Bug Fixes
Fixed MISRA 10.4 issues.
[2.6.4]#
Improvements
Make UART_RETRY_TIMES configurable by CONFIG_UART_RETRY_TIMES.
[2.6.3]#
Bug Fixes
Fixed coverity issues
[2.6.2]#
Bug Fixes
Fixed coverity issues
[2.6.1]#
Improvements
Improve baudrate calculation method, to support higher frequency FlexIO clock source.
[2.6.0]#
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]#
Improvements
Added API FLEXIO_UART_FlushShifters to flush UART fifo.
[2.4.0]#
Improvements
Use separate data for TX and RX in flexio_uart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling FLEXIO_UART_TransferReceiveNonBlocking, the received data count returned by FLEXIO_UART_TransferGetReceiveCount is wrong.
[2.3.0]#
Improvements
Added check for baud rate’s accuracy that returns kStatus_FLEXIO_UART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
Bug Fixes
Added codes in FLEXIO_UART_TransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.2.0]#
Improvements
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.1.6]#
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.5]#
Improvements
Triggered user callback after all the data in ringbuffer were received in FLEXIO_UART_TransferReceiveNonBlocking.
[2.1.4]#
Improvements
Unified component full name to FLEXIO UART(DMA/EDMA) Driver.
[2.1.3]#
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]#
Bug Fixes
Fixed the transfer count calculation issue in FLEXIO_UART_TransferGetReceiveCount, FLEXIO_UART_TransferGetSendCount, FLEXIO_UART_TransferGetReceiveCountDMA, FLEXIO_UART_TransferGetSendCountDMA, FLEXIO_UART_TransferGetReceiveCountEDMA and FLEXIO_UART_TransferGetSendCountEDMA.
Fixed the Dozen mode configuration error in FLEXIO_UART_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Added code to report errors if the user sets a too-low-baudrate which FLEXIO cannot reach.
Disabled FLEXIO_UART receive interrupt instead of all NVICs when reading data from ring buffer. If ring buffer is used, receive nonblocking will disable all NVIC interrupts to protect the ring buffer. This had negative effects on other IPs using interrupt.
[2.1.1]#
Bug Fixes
Changed the API name FLEXIO_UART_StopRingBuffer to FLEXIO_UART_TransferStopRingBuffer to align with the definition in C file.
[2.1.0]#
New Features
Added Transfer prefix in transactional APIs.
Added txSize/rxSize in handle structure to record the transfer size.
Bug Fixes
Added an error handle to handle the situation that data count is zero or data buffer is NULL.
FLEXIO_UART_DMA#
[2.3.0]#
Refer FLEXIO_UART driver change log to 2.3.0
FLEXIO_UART_EDMA#
[2.3.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.3.0]#
Refer FLEXIO_UART driver change log to 2.3.0
GPIO#
[2.8.6]#
Bug Fixes
Fixed CERT INT31-C violations in
GPIO_FIT_REGmacro for platforms with 8-bit register width.
[2.8.5]#
Improvements
Add AND logic in GPIO_GpioClearInterruptFlags to support clearing multiple interrupt flags simultaneously.
[2.8.4]#
Improvements
Make function
GPIO_PortGetInterruptFlagsandGPIO_PortClearInterruptFlagsavailable for all variants, they are used for all pins flags in one GPIO port.
[2.8.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 5.7.
[2.8.2]#
Bug Fixes
Fixed COVERITY issue that GPIO_GetInstance could return clock array overflow values due to GPIO base and clock being out of sync.
[2.8.1]#
Bug Fixes
Fixed CERT INT31-C issues.
[2.8.0]#
Improvements
Add API GPIO_PortInit/GPIO_PortDeinit to set GPIO clock enable and releasing GPIO reset.
[2.8.0]#
Improvements
Add API GPIO_PortInit/GPIO_PortDeinit to set GPIO clock enable and releasing GPIO reset.
Remove support for API GPIO_GetPinsDMARequestFlags with GPIO_ISFR_COUNT <= 1.
[2.7.3]#
Improvements
Release peripheral from reset if necessary in init function.
[2.7.2]#
New Features
Support devices without PORT module.
[2.7.1]#
Bug Fixes
Fixed MISRA C-2012 rule 10.4 issues in GPIO_GpioGetInterruptChannelFlags() function and GPIO_GpioClearInterruptChannelFlags() function.
[2.7.0]#
New Features
Added API to support Interrupt select (IRQS) bitfield.
[2.6.0]#
New Features
Added API to get GPIO version information.
Added API to control a pin for general purpose input.
Added some APIs to control pin in secure and previliege status.
[2.5.3]#
Bug Fixes
Correct the feature macro typo: FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTORL.
[2.5.2]#
Improvements
Improved GPIO_PortSet/GPIO_PortClear/GPIO_PortToggle functions to support devices without Set/Clear/Toggle registers.
[2.5.1]#
Bug Fixes
Fixed wrong macro definition.
Fixed MISRA C-2012 rule issues in the FGPIO_CheckAttributeBytes() function.
Defined the new macro to separate the scene when the width of registers is different.
Removed some redundant macros.
New Features
Added some APIs to get/clear the interrupt status flag when the port doesn’t control pins’ interrupt.
[2.4.1]#
Improvements
Improved GPIO_CheckAttributeBytes() function to support 8 bits width GACR register.
[2.4.0]#
Improvements
API interface added:
New APIs were added to configure the GPIO interrupt clear settings.
[2.3.2]#
Bug Fixes
Fixed the issue for MISRA-2012 check.
Fixed rule 3.1, 10.1, 8.6, 10.6, and 10.3.
[2.3.1]#
Improvements
Removed deprecated APIs.
[2.3.0]#
New Features
Updated the driver code to adapt the case of interrupt configurations in GPIO module. New APIs were added to configure the GPIO interrupt settings if the module has this feature on it.
[2.2.1]#
Improvements
API interface changes:
Refined naming of APIs while keeping all original APIs by marking them as deprecated. The original APIs will be removed in next release. The main change is updating APIs with prefix of _PinXXX() and _PortXXX.
[2.1.1]#
Improvements
API interface changes:
Added an API for the check attribute bytes.
[2.1.0]#
Improvements
API interface changes:
Added “pins” or “pin” to some APIs’ names.
Renamed “_PinConfigure” to “GPIO_PinInit”.
I3C#
[2.15.0]#
Improvements
Added new timing APIs (I3C_MasterCalcTiming, I3C_MasterSetTiming) and supporting types to provide bus-topology-aware baud rate calculation with ODHPP control and pre-computed timing switching.
New Features
Added I3C_MasterGetI2CPresetTiming to get baud rate settings which meet I2C timing.
Bug Fixes
Fixed Coverity issues.
[2.14.7]#
Bug Fixes
Fixed I3C master interrupt transfer not stopping the bus on errors other than Nak/IBIWon.
[2.14.6]#
New Features
Added common IRQ handler entry I3C_DriverIRQHandler.
[2.14.5]#
Bug Fixes
Fixed CERT INT31-C violation: cast bool field enableSlave to uint via ternary in I3C_Init.
[2.14.4]#
Improvements
Fixed MSG violations.
[2.14.3]#
Improvements
Fixed Coverity CERT-C violations.
Used I3C_RSTS instead of I3C special feature macro.
Adapted the driver to support new platform.
[2.14.2]#
Improvements
Added timeout for ENTDAA process API.
Added build system macro to control the timeout setting.
[2.14.1]#
Improvements
Split the function I3C_MasterTransferBlocking to meet the HIS-CCM requirement.
[2.14.0]#
Improvements
Added the choice to set fast start header with push-pull speed when all targets addresses have MSB 0 instead of forcing to set it.
Deleted duplicated busy check in I3C_MasterStart function.
[2.13.1]#
Bug Fixes
Disabled Rx auto-termination in repeated start interrupt event while transfer API doesn’t enable it.
Waited the completion event after loading all Tx data in Tx FIFO.
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]#
New features
Added the hot-join support for I3C bus initialization API.
Bug Fixes
Set read termination with START at the same time in case unknown issue.
Set MCTRL[TYPE] as 0 for DDR force exit.
Improvements
Added the API to reset device count assigned by ENTDAA.
Provided the method to set global macro I3C_MAX_DEVCNT to determine how many device addresses ENTDAA can allocate at one time.
Initialized target management static array based on instance number for the case that multiple instances are used at the same time.
[2.12.0]#
Improvements
Added the slow clock parameter for Controller initialization function to calculate accurate timeout.
Bug Fixes
Fixed the issue that BAMATCH field can’t be 0. BAMATCH should be 1 for 1MHz slow clock.
[2.11.1]#
Bug Fixes
Fixed the issue that interrupt API transmits extra byte when subaddress and data size are null.
Fixed the slow clock calculation issue.
[2.11.0]#
New features
Added the START/ReSTART SCL delay setting for the Soc which supports this feature.
Bug Fixes
Fixed the issue that ENTDAA process waits Rx pending flag which causes problem when Rx watermark isn’t 0. Just check the Rx FIFO count.
[2.10.8]#
Improvements
Support more instances.
[2.10.7]#
Improvements
Fixed the potential compile warning.
[2.10.6]#
New features
Added the I3C private read/write with 0x7E address as start.
[2.10.5]#
New features
Added I3C HDR-DDR transfer support.
[2.10.4]#
Improvements
Added one more option for master to not set RDTERM when doing I3C Common Command Code transfer.
[2.10.3]#
Improvements
Masked the slave IBI/MR/HJ request functions with feature macro.
[2.10.2]#
Bug Fixes
Added workaround for errata ERR051617: I3C working with I2C mode creates the unintended Repeated START before actual STOP on some platforms.
[2.10.1]#
Bug Fixes
Fixed the issue that DAA function doesn’t wait until all Rx data is read out from FIFO after master control done flag is set.
Fixed the issue that DAA function could return directly although the disabled interrupts are not enabled back.
[2.10.0]#
New features
Added I3C extended IBI data support.
[2.9.0]#
Improvements
Added adaptive termination for master blocking transfer. Set termination with start signal when receiving bytes less than 256.
[2.8.2]#
Improvements
Fixed the build warning due to armgcc strict check.
[2.8.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.8.0]#
Improvements
Added API I3C_MasterProcessDAASpecifiedBaudrate for temporary baud rate adjustment when I3C master assigns dynamic address.
[2.7.1]#
Bug Fixes
Fixed the issue that I3C slave handle STOP event before finishing data transmission.
[2.7.0]#
Fixed the CCM problem in file fsl_i3c.c.
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in I3C_GetDefaultConfig and I3C_Init.
[2.6.0]#
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in fsl_i3c.h.
Changed some static functions in fsl_i3c.c as non-static and define the functions in fsl_i3c.h to make I3C DMA driver reuse:
I3C_GetIBIType
I3C_GetIBIAddress
I3C_SlaveCheckAndClearError
Changed the handle pointer parameter in IRQ related funtions to void * type to make it reuse in I3C DMA driver.
Added new API I3C_SlaveRequestIBIWithSingleData for slave to request single data byte, this API could be used regardless slave is working in non-blocking interrupt or non-blocking dma.
Added new API I3C_MasterGetDeviceListAfterDAA for master application to get the device information list built up in DAA process.
[2.5.4]#
Improved I3C driver to avoid setting state twice in the SendCommandState of I3C_RunTransferStateMachine.
Fixed MISRA violation of rule 20.9.
Fixed the issue that I3C_MasterEmitRequest did not use Type I3C SDR.
[2.5.3]#
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH and FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND.
[2.5.2]#
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM.
Fixed the issue that call to I3C_MasterTransferBlocking API did not generate STOP signal when NAK status was returned.
[2.5.1]#
Improved the receive terminate size setting for interrupt transfer read, now it’s set at beginning of transfer if the receive size is less than 256 bytes.
[2.5.0]#
Added new API I3C_MasterRepeatedStartWithRxSize to send repeated start signal with receive terminate size specified.
Fixed the status used in I3C_RunTransferStateMachine, changed to use pending interrupts as status to be handled in the state machine.
Fixed MISRA 2012 violation of rule 10.3, 10.7.
[2.4.0]#
Bug Fixes
Fixed kI3C_SlaveMatchedFlag interrupt is not properly handled in I3C_SlaveTransferHandleIRQ when it comes together with interrupt kI3C_SlaveBusStartFlag.
Fixed the inaccurate I2C baudrate calculation in I3C_MasterSetBaudRate.
Added new API I3C_MasterGetIBIRules to get registered IBI rules.
Added new variable isReadTerm in struct _i3c_master_handle for transfer state routine to check if MCTRL.RDTERM is configured for read transfer.
Changed to emit Auto IBI in transfer state routine for slave start flag assertion.
Fixed the slave maxWriteLength and maxReadLength does not be configured into SMAXLIMITS register issue.
Fixed incorrect state for IBI in I3C master interrupt transfer IRQ handle routine.
Added isHotJoin in i3c_slave_config_t to request hot-join event during slave init.
[2.3.2]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 17.7.
Fixed incorrect HotJoin event index in I3C_GetIBIType.
[2.3.1]#
Bug Fixes
Fixed the issue that call of I3C_MasterTransferBlocking/I3C_MasterTransferNonBlocking fails for the case which receive length 1 byte of data.
Fixed the issue that STOP signal is not sent when NAK status is detected during execution of I3C_MasterTransferBlocking function.
[2.3.0]#
Improvements
Added I3C common driver APIs to initialize I3C with both master and slave configuration.
Updated I3C master transfer callback to function set structure to include callback invoke for IBI event and slave2master event.
Updated I3C master non-blocking transfer model and always enable the interrupts to be able to re-act to the slave start event and handle slave IBI.
[2.2.0]#
Bug Fixes
Fixed the issue that I3C transfer size limit to 255 bytes.
[2.1.2]#
Bug Fixes
Reset default hkeep value to kI3C_MasterHighKeeperNone in I3C_MasterGetDefaultConfig
[2.1.1]#
Bug Fixes
Fixed incorrect FIFO reset operation in I3C Master Transfer APIs.
Fixed i3c slave IRQ handler issue, slave transmit could be underrun because tx FIFO is not filled in time right after start flag detected.
[2.1.0]#
Added definitions and APIs for I3C slave functionality, updated previous I3C APIs to support I3C functionality.
[2.0.0]#
Initial version.
I3C_DMA#
[2.1.11]#
Bug Fixes
Fixed the Coverity unused value issue in I3C_MasterSetTxDMA.
[2.1.10]#
Improvements
Added DMA chain optimization for Errata 052123.
[2.1.9]#
Improvements
Fixed Coverity CERT-C violations.
[2.1.8]#
Bug Fixes
Updated the logic to handle Rx termination and complete event to adapt different situation.
Improvements
Added the MCTRLDONE flag check after STOP request to ensure the completion of whole transfer operation.
[2.1.7]#
Bug Fixes
Fixed the issue to use subaddress to read/write data with RT500/600 DMA.
[2.1.6]#
Improvements
Added the FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG to select the correct register to write data based on specific Soc.
[2.1.5]#
New features
Supported I3C HDR-DDR transfer with DMA.
Improvements
Added workaround for RT500/600 I3C DMA transfer.
Removed I3C IRQ handler calling in the Tx EDMA callback. Previously driver doesn’t use the END byte which can trigger the complete interrupt for controller sending and receiving, now let I3C event handler deal with I3C events.
Used linked DMA to transfer all I3C subaddress and data without handling of intermediate states, simplifying code logic.
Prepare the Tx DMA before I3C START to ensure there’s no time delay between START and transmitting data.
[2.1.4]#
Improvements
Used linked DMA transfer to reduce the latency between DMA transfers previous data and the END byte.
[2.1.3]#
Bug Fixes
Fixed the MISRA issue rule 10.4, 11.3.
[2.1.2]#
Bug Fixes
Fixed the issue that I3C slave send the last byte data without using the END type register.
[2.1.1]#
Bug Fixes
Fixed MISRA issue rule 9.1.
[2.1.0]#
Improvements
Deleted legacy IBI data request code.
[2.0.1]#
Bug Fixes
Fixed issue that bus STOP occurs when Tx FIFO still takes data.
Improvements
Fixed the build warning due to armgcc strict check.
[2.0.0]#
Initial version.
I3C_EDMA#
[2.2.13]#
Changed
Use linked TCD for the slave TX end byte instead of writing the last byte in the EDMA callback.
[2.2.12]#
Bug Fixes
Fixed the issue that EDMA transfer configuration use wrong parameter.
[2.2.11]#
Improvements
Fixed Coverity CERT-C violations.
[2.2.10]#
Bug Fixes
Fixed the issue that slave start event is cleared when it has not been handled.
Added
Supported I3C HDR-DDR transfer with EDMA.
Changed
Used linked EDMA to transfer all I3C subaddress and data without handling of intermediate states, simplifying code logic.
Prepare DMA before I3C START to ensure there’s no time delay between START and transmitting data.
Added the MCTRLDONE flag check after START and STOP request to ensure all states are handled properly.
[2.2.9]#
Bug Fixes
Fixed MISRA issue rule 11.3.
Added the master control done flag waiting code after STOP in case the bus is not idle when transfer function finishes.
[2.2.8]#
Improvements
Removed I3C IRQ handler calling in the EDMA callback. Previously driver doesn’t use the END byte which can trigger the STOP interrupt for controller sending and receiving, now let I3C event handler deal with all I3C events.
Bug Fixes
Fixed the bug that the END type Tx register is not used when command length or data length is one byte.
[2.2.7]#
Bug Fixes
Fixed MISRA issue rule 11.6.
[2.2.6]#
New features
Added the I3C private read/write with 0x7E address as start.
[2.2.5]#
Improvements
Added the workaround for RT1180 I3C EDMA issue ERR052086.
[2.2.4]#
Bug Fixes
Fixed the issue that I3C master sends the last byte data without using the END type register.
[2.2.3]#
Bug Fixes
Fixed issue that slave polulates the last byte when Tx FIFO may be full.
[2.2.2]#
Bug Fixes
Fixed I3C MISRA issue rule 10.4, 11.3.
[2.2.1]#
Bug Fixes
Fixed the issue that I3C slave send the last byte data without using the END type register.
Improvements
There’s no need to reserve two bytes FIFO for DMA transfer which is for IP issue workaround.
[2.2.0]#
Improvements
Deleted legacy IBI data request code.
[2.1.0]#
Bug Fixes
Fixed MISRA issue rule 8.4, 8.6, 11.8.
[2.0.1]#
Bug Fixes
Fixed MISRA issue rule 9.1.
[2.0.0]#
Initial version.
IRTC#
[2.3.4]#
Bug Fixes
Fixed CERT INT31-C violations to ensure safe integer conversions.
[2.3.3]#
Bug Fixes
Fix CERT INT31-C issue.
[2.3.2]#
Bug Fixes
Fixed API IRTC_GetDatetime read YEARMON, DAYS, HOURMIN, SECONDS registers issue.
[2.3.1]#
Bug Fixes
Fixed MISRA C-2012 issue 10.4.
[2.3.0]#
New Feature
Supported platforms with multiple IRTC instances.
[2.2.4]#
Bug Fixes
Fixed MISRA C-2012 issue 10.1, 10.3, 10.4, 10.7, 12.2.
[2.2.3]#
Bug Fixes
Updated undefined macro names by available ones.
[2.2.2]#
Bug Fixes
Fixed MISRA C-2012 issue 10.3.
[2.2.1]#
Bug Fixes
Fixed MISRA issues.
[2.2.0]#
New Feature
Add new APIs for CLK_SEL and CLKO to select RTC clock and enable/disable output to peripherals.
Supported platforms without tamper feature.
[2.1.3]#
Bug Fixes
Fixed MISRA C-2012 issue 10.1 and 10.4.
[2.1.2]#
Bug Fixes
Fixed kIRTC_TamperFlag flag can’t be cleared issue.
[2.1.1]#
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4.
[2.1.0]#
Bug Fixes
Fixed incorrect leap year check in IRTC_CheckDatetimeFormat.
New Feature
Added new APIs for new feature FSL_FEATURE_RTC_HAS_SUBSYSTEM.
Added new APIs for TAMPER, TAMPER QUEUE status get and clear.
Added new API to enable/disable 32 kHz RTC OSC clock during RTC register write.
Updated IRTC_SetTamperParams to support new feature FSL_FEATURE_RTC_HAS_FILTER23_CFG
Updated irtc_config_t to exclude member wakeupSelect for new feature FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE.
[2.0.2]#
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.6, rule-10.8, rule-11.9, rule-12.2, rule-15.5, rule-16.4, rule-17.7.
[2.0.1]#
Bug Fixes
Fixed the issue of hard code in IRTC_Init.
[2.0.0]#
Initial version.
ISI#
[2.2.5]#
Update to adapter head file
ISI interface have some channel, head file have been updated to support it, modified driver to compatible this changes.
[2.2.4]#
Bug Fixes
Fixed CERT INT31-C INT30-C violations.
[2.0.2]#
Bug Fixes
Fixed the violations of MISRA 2012 rules: 3.1, 5.6, 5.7, 10.1, 10.3, 10.4, 10.8, 12.2, 13.2, 14.4, 17.7.
[2.0.1]#
New Features
Added a control macro to enable/disable the CLOCK code in current driver.
[2.0.0]#
Initial version.
JPEGDEC#
[2.0.2]#
Other Changes
Update driver to support more resolution due to the IP bug fix.
[2.0.1]#
Bug Fixes
Fixed CERT-C violations.
[2.0.0]#
Initial version.
LPADC#
[2.11.0]#
New Features
Added the LPADC_USE_FIXED_POINT_GAIN_CALCULATION configuration macro. When set to 1, LPADC_FinishAutoCalibration() calculates the gain conversion result with integer-only arithmetic instead of the float/double software library, saving several kB of flash on code size sensitive devices. The fixed point result keeps the gain fraction in Q17.14, so the two least significant bits of the gain conversion result are always zero.
[2.10.3]#
Bug Fixes
Fixed MISRA C-2012 essential-type-model violations (Rules 10.1, 10.3, 10.4 and 10.8) in
LPADC_FinishAutoCalibrationandLPADC_GetOffsetValue.
[2.10.2]#
Improvements
Gate the trigger (TCTRL) enums and the trigger-id assert on
FSL_FEATURE_ADC_TCTRL_COUNTfor every trigger index, so devices with fewer triggers no longer expose unavailable trigger registers.
[2.10.1]#
Improvements
Reworked the gain-calibration ratio in
LPADC_FinishAutoCalibrationto use single-precision (float) arithmetic instead of double-precision, removing the dependency on the libgcc double soft-float routines (__floatsidf,__aeabi_dsub,__aeabi_ddiv,__aeabi_d2f) that were linked into every application using the LPADC driver, reducing ROM footprint.
[2.10.0]#
Improvements
Use
#if !defined(ADC_TCTRL_COUNT) || (ADC_TCTRL_COUNT > nU)to wrap some configurations because these configurations are invalid/illegal on some SoCs.
[2.9.5]#
Improvements
Fix doxygen issue, grouping command should be balanced.
[2.9.4]#
Improvements
Update LPADC_GetDefaultConfig, change default conversionAverageMode value to: kLPADC_ConversionAverage128 for 3 bit width. kLPADC_ConversionAverage1024 for 4 bit width.
[2.9.3]#
Improvements
Add timeout for while loop code.
[2.9.2]#
Improvements
Fixed CERT-C issues.
[2.9.1]#
Bug Fixes
Fixed incorrect channel B FIFO selection logic.
[2.9.0]#
Bug Fixes
Add code to handle the case where GCC[GAIN_CAL] is a signed number.
Split LPADC_FinishAutoCalibration function into two functions.
Improved LPADC driver.
[2.8.4]#
Bug Fixes
Remove function ‘LPADC_SetOffsetValue’ assert statement, this statement may cause runtime errors in existing code.
[2.8.3]#
Bug Fixes
Fixed SDK lpadc driver examples compile issue, move condition ‘commandId < ADC_CV_COUNT’ to a more appropriate location.
[2.8.2]#
Bug Fixes
Fixed the violations of MISRA C-2012 rule 18.1, 10.3, 10.1 and 10.4.
[2.8.1]#
Bug Fixes
Fixed LPADC sample mode enum name mistake.
[2.8.0]#
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed function LPADC_GetConvResult() issue.
Fixed function LPADC_SetConvCommandConfig() bugs.
[2.7.2]#
Improvements
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.1]#
Improvements
Corrected descriptions of several functions.
Improved function LPADC_GetOffsetValue and LPADC_SetOffsetValue.
Revert changes of feature macros for lpadc.
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.8.
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.0]#
Improvements
Added supports of CFG2 register.
Removed some useless macros.
[2.6.2]#
Bug Fixes
Fixed the violations of MISRA C-2012 rules.
Fixed LPADC driver code compile error issue.
[2.6.1]#
Improvements
Updated the use of macros in the driver code.
[2.6.0]#
Improvements
Added the API LPADC_SetOffset12BitValue() to configure 12bit ADC conversion offset trim value manually.
Added the API LPADC_SetOffset16BitValue() to configure 16bit ADC conversion offset trim value manually.
Added API to set offset calibration mode.
Added configuration of alternate channel.
Updated auto calibration API and added calibration value conversion API.
New feature
Added API LPADC_EnableHardwareTriggerCommandSelection() to enable trigger commands controlled by ADC_ETC.
Updated LPADC_DoAutoCalibration() to allow doing something else before the ADC inititialization to be totally complete. Enhance initialization duration time of the ADC.
Added two new APIs to get/set calibration value.
[2.5.2]#
Improvements
Added while loop, LPADC_GetConvResult() will return only when the FIFO will not be empty.
[2.5.1]#
Bug Fixes
Fixed some typos in Lpadc driver comments.
[2.5.0]#
Improvements
Added missing items to enable trigger interrupts.
[2.4.0]#
New features
Added APIs to get/clear trigger status flags.
[2.3.0]#
Improvements
Removed LPADC_MeasureTemperature() function for the LPADC supports different temperature sensor calculation equations.
[2.2.1]#
Improvements
Optimized LPADC_MeasureTemperature() function to support the specific series with flash solidified calibration value.
Clean doxygen warnings.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, rule 10.8 and rule 17.7.
[2.2.0]#
New Feature
Added API LPADC_MeasureTemperature() to get correct temperature from the internal sensor.
Improvements
Separated lpadc_conversion_resolution_mode_t with related feature macro.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.3, 10.4, 10.6, 10.7 and 17.7.
[2.1.1]#
Improvements
Updated the gain calibration formula.
Used feature to segregate the new item kLPADC_TriggerPriorityPreemptSubsequently.
[2.1.0]#
New Features
Added the API LPADC_SetOffsetValue() to support configure offset trim value manually.
Added the API LPADC_DoOffsetCalibration() to do offset calibration independently.
Improvements
Improved the usage of macros and removed invalid macros.
[2.0.2]#
Improvements
Added support for platforms with 2 FIFOs and different calibration measures.
[2.0.1]#
Bug Fixes
Ensured the API LPADC_SetConvCommandConfig configure related registers correctly.
[2.0.0]#
Initial version.
LPI2C#
[2.6.8]#
Bug Fixes
LPI2C_MasterTransferBlocking - added waiting while TX FIFO is not empty.
Added a check for an error from the previous transfer in the transfer API (when kLPI2C_TransferNoStopFlag was used).
Updated LPI2C_MasterReceive() to return kStatus_InvalidArgument when rxSize is 0.
Updated transfer API functions to return kStatus_InvalidArgument when transfer->dataSize is 0 and transfer->direction is kLPI2C_Read.
Fixed assert issue in LPI2C_MasterSetBaudRate().
Fixed CERT-C issues.
Fixed MISRA issues.
Improved HIS CCM for LPI2C_MasterTransferBlocking() and LPI2C_SlaveTransferHandleIRQ().
[2.6.7]#
Bug Fixes
Fixed MISRA 10.3 and 10.8 issues.
Fixed LPI2C_MasterStop() to send I2C STOP in case of error.
[2.6.6]#
Bug Fixes
Set handle->chunkSize to 0 in LPI2C_MasterTransferNonBlocking().
[2.6.5]#
Bug Fixes
Removed write to STAR register in LPI2C_SlaveTransferHandleIRQ handler in case of kLPI2C_SlaveRepeatedStartDetectFlag or kLPI2C_SlaveStopDetectFlag.
Removed configuration of FILTSDA from LPI2C_MasterSetBaudRate().
Set minimal possible value for FILTSDA and FILTSCL to 0.
Updated configuration of glitch filters in LPI2C_SlaveInit().
Set minimal possible value for SCFGR2[CLKHOLD] to 1.
Added error check to while loop in LPI2C_TransferStateMachineSendCommand().
Improvements
Removed receive data size limitation in LPI2C_MasterTransferBlocking() and LPI2C_MasterTransferNonBlocking().
[2.6.4]#
Bug Fixes
Limited value of filtSda in LPI2C_MasterSetBaudRate().
Updated LPI2C_MasterStop() and LPI2C_MasterTransferBlocking() to send I2C STOP also in case of error.
Removed unused flag kLPI2C_TransferRepeatedStartFlag.
[2.6.3]#
Bug Fixes
Fixed static analysis identified issues.
[2.6.2]#
Improvements
Added timeout for while loop in LPI2C_TransferStateMachineSendCommand().
[2.6.1]#
Bug Fixes
Fixed coverity issues.
[2.6.0]#
New Feature
Added common IRQ handler entry LPI2C_DriverIRQHandler.
[2.5.7]#
Improvements
Added support for separated IRQ handlers.
[2.5.6]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.5]#
Bug Fixes
Fixed LPI2C_SlaveInit() - allow to disable SDA/SCL glitch filter.
[2.5.4]#
Bug Fixes
Fixed LPI2C_MasterTransferBlocking() - the return value was sometime affected by call of LPI2C_MasterStop().
[2.5.3]#
Improvements
Added handler for LPI2C7 and LPI2C8.
[2.5.2]#
Bug Fixes
Fixed ERR051119 to ignore the nak flag when IGNACK=1 in LPI2C_MasterCheckAndClearError.
[2.5.1]#
Bug Fixes
Added bus stop incase of bus stall in LPI2C_MasterTransferBlocking.
Improvements
Release peripheral from reset if necessary in init function.
[2.5.0]#
New Features
Added new function LPI2C_SlaveEnableAckStall to enable or disable ACKSTALL.
[2.4.1]#
Improvements
Before master transfer with transactional APIs, enable master function while disable slave function and vise versa for slave transfer to avoid the one affecting the other.
[2.4.0]#
Improvements
Split some functions, fixed CCM problem in file fsl_lpi2c.c.
Bug Fixes
Fixed bug in LPI2C_MasterInit that the MCFGR2’s value set in LPI2C_MasterSetBaudRate may be overwritten by mistake.
[2.3.2]#
Improvements
Initialized the EDMA configuration structure in the LPI2C EDMA driver.
[2.3.1]#
Improvements
Updated LPI2C_GetCyclesForWidth to add the parameter of minimum cycle, because for master SDA/SCL filter, master bus idle/pin low timeout and slave SDA/SCL filter configuration, 0 means disabling the feature and cannot be used.
Bug Fixes
Fixed bug in LPI2C_SlaveTransferHandleIRQ that when restart detect event happens the transfer structure should not be cleared.
Fixed bug in LPI2C_RunTransferStateMachine, that when only slave address is transferred or there is still data remaining in tx FIFO the last byte’s nack cannot be ignored.
Fixed bug in slave filter doze enable, that when FILTDZ is set it means disable rather than enable.
Fixed bug in the usage of LPI2C_GetCyclesForWidth. First its return value cannot be used directly to configure the slave FILTSDA, FILTSCL, DATAVD or CLKHOLD, because the real cycle width for them should be FILTSDA+3, FILTSCL+3, FILTSCL+DATAVD+3 and CLKHOLD+3. Second when cycle period is not affected by the prescaler value, prescaler value should be passed as 0 rather than 1.
Fixed wrong default setting for LPI2C slave. If enabling the slave tx SCL stall, then the default clock hold time should be set to 250ns according to I2C spec for 100kHz standard mode baudrate.
Fixed bug that before pushing command to the tx FIFO the FIFO occupation should be checked first in case FIFO overflow.
[2.3.0]#
New Features
Supported reading more than 256 bytes of data in one transfer as master.
Added API LPI2C_GetInstance.
Bug Fixes
Fixed bug in LPI2C_MasterTransferAbortEDMA, LPI2C_MasterTransferAbort and LPI2C_MasterTransferHandleIRQ that before sending stop signal whether master is active and whether stop signal has been sent should be checked, to make sure no FIFO error or bus error will be caused.
Fixed bug in LPI2C master EDMA transactional layer that the bus error cannot be caught and returned by user callback, by monitoring bus error events in interrupt handler.
Fixed bug in LPI2C_GetCyclesForWidth that the parameter used to calculate clock cycle should be 2^prescaler rather than prescaler.
Fixed bug in LPI2C_MasterInit that timeout value should be configured after baudrate, since the timeout calculation needs prescaler as parameter which is changed during baudrate configuration.
Fixed bug in LPI2C_MasterTransferHandleIRQ and LPI2C_RunTransferStateMachine that when master writes with no stop signal, need to first make sure no data remains in the tx FIFO before finishes the transfer.
[2.2.0]#
Bug Fixes
Fixed issue that the SCL high time, start hold time and stop setup time do not meet I2C specification, by changing the configuration of data valid delay, setup hold delay, clock high and low parameters.
MISRA C-2012 issue fixed.
Fixed rule 8.4, 13.5, 17.7, 20.8.
[2.1.12]#
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.1.11]#
Bug Fixes
Fixed the bug that, during master non-blocking transfer, after the last byte is sent/received, the kLPI2C_MasterNackDetectFlag is expected, so master should not check and clear kLPI2C_MasterNackDetectFlag when remainingBytes is zero, in case FIFO is emptied when stop command has not been sent yet.
Fixed the bug that, during non-blocking transfer slave may nack master while master is busy filling tx FIFO, and NDF may not be handled properly.
[2.1.10]#
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rule 10.3, 14.4, 15.5.
Fixed unaligned access issue in LPI2C_RunTransferStateMachine.
Fixed uninitialized variable issue in LPI2C_MasterTransferHandleIRQ.
Used linked TCD to disable tx and enable rx in read operation to fix the issue that for platform sharing the same DMA request with tx and rx, during LPI2C read operation if interrupt with higher priority happened exactly after command was sent and before tx disabled, potentially both tx and rx could trigger dma and cause trouble.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 11.6, 11.9, 14.4, 17.7.
Fixed the waitTimes variable not re-assignment issue for each byte read.
New Features
Added the IRQHandler for LPI2C5 and LPI2C6 instances.
Improvements
Updated the LPI2C_WAIT_TIMEOUT macro to unified name I2C_RETRY_TIMES.
[2.1.9]#
Bug Fixes
Fixed Coverity issue of unchecked return value in I2C_RTOS_Transfer.
Fixed Coverity issue of operands did not affect the result in LPI2C_SlaveReceive and LPI2C_SlaveSend.
Removed STOP signal wait when NAK detected.
Cleared slave repeat start flag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved repeat start flag. This caused the next slave to send a break, and the master was always in the receive data status, but could not receive data.
[2.1.8]#
Bug Fixes
Fixed the transfer issue with LPI2C_MasterTransferNonBlocking, kLPI2C_TransferNoStopFlag, with the wait transfer done through callback in a way of not doing a blocking transfer.
Fixed the issue that STOP signal did not appear in the bus when NAK event occurred.
[2.1.7]#
Bug Fixes
Cleared the stopflag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved stop flag and caused the next slave to send a break, and the master always stayed in the receive data status but could not receive data.
[2.1.6]#
Bug Fixes
Fixed driver MISRA build error and C++ build error in LPI2C_MasterSend and LPI2C_SlaveSend.
Reset FIFO in LPI2C Master Transfer functions to avoid any byte still remaining in FIFO during last transfer.
Fixed the issue that LPI2C_MasterStop did not return the correct NAK status in the bus for second transfer to the non-existing slave address.
[2.1.5]#
Bug Fixes
Extended the Driver IRQ handler to support LPI2C4.
Changed to use ARRAY_SIZE(kLpi2cBases) instead of FEATURE COUNT to decide the array size for handle pointer array.
[2.1.4]#
Bug Fixes
Fixed the LPI2C_MasterTransferEDMA receive issue when LPI2C shared same request source with TX/RX DMA request. Previously, the API used scatter-gather method, which handled the command transfer first, then the linked TCD which was pre-set with the receive data transfer. The issue was that the TX DMA request and the RX DMA request were both enabled, so when the DMA finished the first command TCD transfer and handled the receive data TCD, the TX DMA request still happened due to empty TX FIFO. The result was that the RX DMA transfer would start without waiting on the expected RX DMA request.
Fixed the issue by enabling IntMajor interrupt for the command TCD and checking if there was a linked TCD to disable the TX DMA request in LPI2C_MasterEDMACallback API.
[2.1.3]#
Improvements
Added LPI2C_WATI_TIMEOUT macro to allow the user to specify the timeout times for waiting flags in functional API and blocking transfer API.
Added LPI2C_MasterTransferBlocking API.
[2.1.2]#
Bug Fixes
In LPI2C_SlaveTransferHandleIRQ, reset the slave status to idle when stop flag was detected.
[2.1.1]#
Bug Fixes
Disabled the auto-stop feature in eDMA driver. Previously, the auto-stop feature was enabled at transfer when transferring with stop flag. Since transfer was without stop flag and the auto-stop feature was enabled, when starting a new transfer with stop flag, the stop flag would be sent before the new transfer started, causing unsuccesful sending of the start flag, so the transfer could not start.
Changed default slave configuration with address stall false.
[2.1.0]#
Improvements
API name changed:
LPI2C_MasterTransferCreateHandle -> LPI2C_MasterCreateHandle.
LPI2C_MasterTransferGetCount -> LPI2C_MasterGetTransferCount.
LPI2C_MasterTransferAbort -> LPI2C_MasterAbortTransfer.
LPI2C_MasterTransferHandleIRQ -> LPI2C_MasterHandleInterrupt.
LPI2C_SlaveTransferCreateHandle -> LPI2C_SlaveCreateHandle.
LPI2C_SlaveTransferGetCount -> LPI2C_SlaveGetTransferCount.
LPI2C_SlaveTransferAbort -> LPI2C_SlaveAbortTransfer.
LPI2C_SlaveTransferHandleIRQ -> LPI2C_SlaveHandleInterrupt.
[2.0.0]#
Initial version.
LPI2C_EDMA#
[2.4.9]#
Bug Fixes
Fixed CERT-C issues.
Fixed MISRA issues.
[2.4.8]#
Bug Fixes
Fixed MISRA 10.6 and 14.3 issues.
[2.4.7]#
Bug Fixes
Fixed incorrect TX FIFO size (maxTxFifo) in LPI2C_MasterTransferEDMA() and LPI2C_MasterTransferEdmaHandleIRQ().
[2.4.6]#
Bug Fixes
Fixed static analysis identified issues.
[2.4.5]#
Improvements
Added condition to IRQ handler to check whether the interrupt is enabled - kLPI2C_MasterTxReadyFlag.
[2.4.4]#
Improvements
Added support for 2KB data transfer
[2.4.3]#
Improvements
Added support for separated IRQ handlers.
[2.4.2]#
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.1]#
Refer LPI2C driver change log 2.0.0 to 2.4.1
LPIT#
[2.1.3]#
Bug Fixes
Fixed doxygen generation warnings.
[2.1.2]#
Bug Fixes
Fix CERT INT31-C issues.
[2.1.1]#
Improvements
Release peripheral from reset if necessary in init function.
[2.1.0]#
Improvements
Add new function LPIT_SetTimerValue to set timeout period.
[2.0.2]#
Improvements
Improved LPIT_SetTimerPeriod implementation, configure timeout value with LPIT ticks minus 1 generate more correct interval.
Added timeout value configuration check for LPIT_SetTimerPeriod, at least input 3 ticks for calling LPIT_SetTimerPeriod.
Bug Fixes
Fixed MISRA C-2012 rule 17.7 violations.
[2.0.1]#
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rules, containing: rule-10.3, rule-14.4, rule-15.5.
[2.0.0]#
Initial version.
LPSPI#
[2.7.8]#
Bug Fixes
Fixed CERT-C issues.
Fixed MISRA issues.
Improvements
Improved HIS CCM.
[2.7.7]#
Bug Fixes
Fixed timing parameter setting sequence issue in
LPSPI_MasterInit, the timing parameter should only be configured when LPSPI master is disabled.
Improvements
Improved performance of LPSPI_MasterTransferBlocking().
[2.7.6]#
Bug Fixes
Fixed calculation of SCK-to-SCK delay.
[2.7.5]#
Bug Fixes
Fixed MISRA 10.3, 12,2 and 10.7 issues.
[2.7.4]#
Bug Fixes
Clear WIDTH bits from the TCR register before writing a new value in LPSPI_MasterTransferBlocking().
[2.7.3]#
Improvements
Added timeout for while loop in LPSPI_MasterTransferWriteAllTxData().
Make SPI_RETRY_TIMES configurable by CONFIG_SPI_RETRY_TIMES.
[2.7.2]#
Bug Fixes
Fixed coverity issues.
[2.7.1]#
Bug Fixes
Workaround for errata ERR050607
Workaround for errata ERR010655
[2.7.0]#
New Feature
Added common IRQ handler entry LPSPI_DriverIRQHandler.
[2.6.10]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.6.9]#
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.6.8]#
Bug Fixes
Fixed build error when SPI_RETRY_TIMES is defined to non-zero value.
[2.6.7]#
Bug Fixes
Fixed the txData from void * to const void * in transmit API _lpspi_master_handle and _lpspi_slave_handle.
[2.6.6]#
Bug Fixes
Added LPSPI register init in LPSPI_MasterInit incase of LPSPI register exist.
[2.6.5]#
Improvements
Introduced FSL_FEATURE_LPSPI_HAS_NO_PCSCFG and FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH for conditional compile.
Release peripheral from reset if necessary in init function.
[2.6.4]#
Bug Fixes
Added LPSPI6_DriverIRQHandler for LPSPI6 instance.
[2.6.3]#
Hot Fixes
Added macro switch in function LPSPI_Enable about ERRATA051472.
[2.6.2]#
Bug Fixes
Disabled lpspi before LPSPI_MasterSetBaudRate incase of LPSPI opened.
[2.6.1]#
Bug Fixes
Fixed return value while calling LPSPI_WaitTxFifoEmpty in function LPSPI_MasterTransferNonBlocking.
[2.6.0]#
Feature
Added the new feature of multi-IO SPI .
[2.5.3]#
Bug Fixes
Fixed 3-wire txmask of handle vaule reentrant issue.
[2.5.2]#
Bug Fixes
Workaround for errata ERR051588 by clearing FIFO after transmit underrun occurs.
[2.5.1]#
Bug Fixes
Workaround for errata ERR050456 by resetting the entire module using LPSPIn_CR[RST] bit.
[2.5.0]#
Bug Fixes
Workaround for errata ERR011097 to wait the TX FIFO to go empty when writing TCR register and TCR[TXMSK] value is 1.
Added API LPSPI_WaitTxFifoEmpty for wait the txfifo to go empty.
[2.4.7]#
Bug Fixes
Fixed bug that the SR[REF] would assert if software disabled or enabled the LPSPI module in LPSPI_Enable.
[2.4.6]#
Improvements
Moved the configuration of registers for the 3-wire lpspi mode to the LPSPI_MasterInit and LPSPI_SlaveInit function.
[2.4.5]#
Improvements
Improved LPSPI_MasterTransferBlocking send performance when frame size is 1-byte.
[2.4.4]#
Bug Fixes
Fixed LPSPI_MasterGetDefaultConfig incorrect default inter-transfer delay calculation.
[2.4.3]#
Bug Fixes
Fixed bug that the ISR response speed is too slow on some platforms, resulting in the first transmission of overflow, Set proper RX watermarks to reduce the ISR response times.
[2.4.2]#
Bug Fixes
Fixed bug that LPSPI_MasterTransferBlocking will modify the parameter txbuff and rxbuff pointer.
[2.4.1]#
Bug Fixes
Fixed bug that LPSPI_SlaveTransferNonBlocking can’t detect RX error.
[2.4.0]#
Improvements
Split some functions, fixed CCM problem in file fsl_lpspi.c.
[2.3.1]#
Improvements
Initialized the EDMA configuration structure in the LPSPI EDMA driver.
Bug Fixes
Fixed bug that function LPSPI_MasterTransferBlocking should return after the transfer complete flag is set to make sure the PCS is re-asserted.
[2.3.0]#
New Features
Supported the master configuration of sampling the input data using a delayed clock to improve slave setup time.
[2.2.1]#
Bug Fixes
Fixed bug in LPSPI_SetPCSContinous when disabling PCS continous mode.
[2.2.0]#
Bug Fixes
Fixed bug in 3-wire polling and interrupt transfer that the received data is not correct and the PCS continous mode is not working.
[2.1.0]#
Improvements
Improved LPSPI_SlaveTransferHandleIRQ to fill up TX FIFO instead of write one data to TX register which improves the slave transmit performance.
Added new functional APIs LPSPI_SelectTransferPCS and LPSPI_SetPCSContinous to support changing PCS selection and PCS continous mode.
Bug Fixes
Fixed bug in non-blocking and EDMA transfer APIs that kStatus_InvalidArgument is returned if user configures 3-wire mode and full-duplex transfer at the same time, but transfer state is already set to kLPSPI_Busy by mistake causing following transfer can not start.
Fixed bug when LPSPI slave using EDMA way to transfer, tx should be masked when tx data is null, otherwise in 3-wire mode which tx/rx use the same pin, the received data will be interfered.
[2.0.5]#
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed the bug that LPSPI can not transfer large data using EDMA.
Fixed MISRA 17.7 issues.
Fixed variable overflow issue introduced by MISRA fix.
Fixed issue that rxFifoMaxBytes should be calculated according to transfer width rather than FIFO width.
Fixed issue that completion flag was not cleared after transfer completed.
[2.0.4]#
Bug Fixes
Fixed in LPSPI_MasterTransferBlocking that master rxfifo may overflow in stall condition.
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.6, 11.9, 14.2, 14.4, 15.7, 17.7.
[2.0.3]#
Bug Fixes
Removed LPSPI_Reset from LPSPI_MasterInit and LPSPI_SlaveInit, because this API may glitch the slave select line. If needed, call this function manually.
[2.0.2]#
New Features
Added dummy data set up API to allow users to configure the dummy data to be transferred.
Enabled the 3-wire mode, SIN and SOUT pins can be configured as input/output pin.
[2.0.1]#
Bug Fixes
Fixed the bug that the clock source should be divided by the PRESCALE setting in LPSPI_MasterSetDelayTimes function.
Fixed the bug that LPSPI_MasterTransferBlocking function would hang in some corner cases.
Optimization
Added #ifndef/#endif to allow user to change the default TX value at compile time.
[2.0.0]#
Initial version.
LPSPI_EDMA#
[2.4.11]#
Bug Fixes
Fixed CERT-C issues.
Fixed MISRA issues.
Improvements
Improved HIS CCM in LPSPI_MasterTransferEDMALite() and LPSPI_SlaveTransferEDMA().
[2.4.10]#
Bug Fixes
Fixed MISRA 10.6 issues.
[2.4.9]#
Improvements
Removed unused code from LPSPI_SeparateEdmaReadData().
[2.4.8]#
Improvements
Added timeout for while loop in EDMA_LpspiMasterCallback() and EDMA_LpspiSlaveCallback().
[2.4.7]#
Bug Fixes
Add macro LPSPI_ALIGN_TCD_SIZE_MASK to align an address to edma_tcd_t size.
[2.4.6]#
Improvements
Increased transmit FIFO watermark to ensure whole transmit FIFO will be used during data transfer.
[2.4.5]#
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.4.4]#
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.3]#
Improvements
Supported 32K bytes transmit in DMA, improve the max datasize in LPSPI_MasterTransferEDMALite.
[2.4.2]#
Improvements
Added callback status in EDMA_LpspiMasterCallback and EDMA_LpspiSlaveCallback to check transferDone.
[2.4.1]#
Improvements
Add the TXMSK wait after TCR setting.
[2.4.0]#
Improvements
Separated LPSPI_MasterTransferEDMA functions to LPSPI_MasterTransferPrepareEDMA and LPSPI_MasterTransferEDMALite to optimize the process of transfer.
LPTMR#
[2.2.1]#
Bug Fixes
Fix CERT INT31-C issues.
[2.2.0]#
Improvements
Updated lptmr_prescaler_clock_select_t, only define the valid options.
[2.1.1]#
Improvements
Updated the characters from “PTMR” to “LPTMR” in “FSL_FEATURE_PTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT” feature definition.
[2.1.0]#
Improvements
Implement for some special devices’ not supporting for all clock sources.
Bug Fixes
Fixed issue when accessing CMR register.
[2.0.2]#
Bug Fixes
Fixed MISRA-2012 issues.
Rule 10.1.
[2.0.1]#
Improvements
Updated the LPTMR driver to support 32-bit CNR and CMR registers in some devices.
[2.0.0]#
Initial version.
LPUART#
[2.11.0]#
New Feature
Added support to enable transmitter RTS and configure transmitter RTS polarity.
Added support to enable Transmit Data Inversion.
Improvements
Updated to work on DSC platform.
[2.10.0]#
New Feature
Added support to configure RTS watermark.
[2.9.4]#
Improvements
Merged duplicate code.
[2.9.3]#
Improvements
Added timeout for while loops in LPUART_Deinit().
[2.9.2]#
Bug Fixes
Fixed coverity issues.
[2.9.1]#
Bug Fixes
Fixed coverity issues.
[2.9.0]#
New Feature
Added support for swap TXD and RXD pins.
Added common IRQ handler entry LPUART_DriverIRQHandler.
[2.8.3]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.8.2]#
Bug Fix
Fixed the bug that LPUART_TransferEnable16Bit controled by wrong feature macro.
[2.8.1]#
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-5.3, rule-5.8, rule-10.4, rule-11.3, rule-11.8.
[2.8.0]#
Improvements
Added support of DATA register for 9bit or 10bit data transmit in write and read API. Such as: LPUART_WriteBlocking16bit, LPUART_ReadBlocking16bit, LPUART_TransferEnable16Bit LPUART_WriteNonBlocking16bit, LPUART_ReadNonBlocking16bit.
[2.7.7]#
Bug Fixes
Fixed the bug that baud rate calculation overflow when srcClock_Hz is 528MHz.
[2.7.6]#
Bug Fixes
Fixed LPUART_EnableInterrupts and LPUART_DisableInterrupts bug that blocks if the LPUART address doesn’t support exclusive access.
[2.7.5]#
Improvements
Release peripheral from reset if necessary in init function.
[2.7.4]#
Improvements
Added support for atomic register accessing in LPUART_EnableInterrupts and LPUART_DisableInterrupts.
[2.7.3]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 15.7.
[2.7.2]#
Bug Fix
Fixed the bug that the OSR calculation error when lupart init and lpuart set baud rate.
[2.7.1]#
Improvements
Added support for LPUART_BASE_PTRS_NS in security mode in file fsl_lpuart.c.
[2.7.0]#
Improvements
Split some functions, fixed CCM problem in file fsl_lpuart.c.
[2.6.0]#
Bug Fixes
Fixed bug that when there are multiple lpuart instance, unable to support different ISR.
[2.5.3]#
Bug Fixes
Fixed comments by replacing unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag with kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag.
[2.5.2]#
Bug Fixes
Fixed bug that when setting watermark for TX or RX FIFO, the value may exceed the maximum limit.
Improvements
Added check in LPUART_TransferDMAHandleIRQ and LPUART_TransferEdmaHandleIRQ to ensure if user enables any interrupts other than transfer complete interrupt, the dma transfer is not terminated by mistake.
[2.5.1]#
Improvements
Use separate data for TX and RX in lpuart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling LPUART_TransferReceiveNonBlocking, the received data count returned by LPUART_TransferGetReceiveCount is wrong.
[2.5.0]#
Bug Fixes
Added missing interrupt enable masks kLPUART_Match1InterruptEnable and kLPUART_Match2InterruptEnable.
Fixed bug in LPUART_EnableInterrupts, LPUART_DisableInterrupts and LPUART_GetEnabledInterrupts that the BAUD[LBKDIE] bit field should be soc specific.
Fixed bug in LPUART_TransferHandleIRQ that idle line interrupt should be disabled when rx data size is zero.
Deleted unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag, since firstly their function are the same as kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag, secondly to obtain them one data word must be read out thus interfering with the receiving process.
Fixed bug in LPUART_GetStatusFlags that the STAT[LBKDIF], STAT[MA1F] and STAT[MA2F] should be soc specific.
Fixed bug in LPUART_ClearStatusFlags that tx/rx FIFO is reset by mistake when clearing flags.
Fixed bug in LPUART_TransferHandleIRQ that while clearing idle line flag the other bits should be masked in case other status bits be cleared by accident.
Fixed bug of race condition during LPUART transfer using transactional APIs, by disabling and re-enabling the global interrupt before and after critical operations on interrupt enable register.
Fixed DMA/eDMA transfer blocking issue by enabling tx idle interrupt after DMA/eDMA transmission finishes.
New Features
Added APIs LPUART_GetRxFifoCount/LPUART_GetTxFifoCount to get rx/tx FIFO data count.
Added APIs LPUART_SetRxFifoWatermark/LPUART_SetTxFifoWatermark to set rx/tx FIFO water mark.
[2.4.1]#
Bug Fixes
Fixed MISRA advisory 17.7 issues.
[2.4.0]#
New Features
Added APIs to configure 9-bit data mode, set slave address and send address.
[2.3.1]#
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.3.0]#
Improvements
Modified LPUART_TransferHandleIRQ so that txState will be set to idle only when all data has been sent out to bus.
Modified LPUART_TransferGetSendCount so that this API returns the real byte count that LPUART has sent out rather than the software buffer status.
Added timeout mechanism when waiting for certain states in transfer driver.
[2.2.8]#
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-10.3, rule-14.4, rule-15.5.
Eliminated Pa082 warnings by assigning volatile variables to local variables and using local variables instead.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.8, 14.4, 11.6, 17.7.
Improvements
Added check for kLPUART_TransmissionCompleteFlag in LPUART_WriteBlocking, LPUART_TransferHandleIRQ, LPUART_TransferSendDMACallback and LPUART_SendEDMACallback to ensure all the data would be sent out to bus.
Rounded up the calculated sbr value in LPUART_SetBaudRate and LPUART_Init to achieve more acurate baudrate setting. Changed osr from uint32_t to uint8_t since osr’s bigest value is 31.
Modified LPUART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.
[2.2.7]#
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-12.1, rule-17.7, rule-14.4, rule-13.3, rule-14.4, rule-10.4, rule-10.8, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-13.2, rule-8.3.
[2.2.6]#
Bug Fixes
Fixed the issue of register’s being in repeated reading status while dealing with the IRQ routine.
[2.2.5]#
Bug Fixes
Do not set or clear the TIE/RIE bits when using LPUART_EnableTxDMA and LPUART_EnableRxDMA.
[2.2.4]#
Improvements
Added hardware flow control function support.
Added idle-line-detecting feature in LPUART_TransferNonBlocking function. If an idle line is detected, a callback is triggered with status kStatus_LPUART_IdleLineDetected returned. This feature may be useful when the received Bytes is less than the expected received data size. Before triggering the callback, data in the FIFO (if has FIFO) is read out, and no interrupt will be disabled, except for that the receive data size reaches 0.
Enabled the RX FIFO watermark function. With the idle-line-detecting feature enabled, users can set the watermark value to whatever you want (should be less than the RX FIFO size). Data is received and a callback will be triggered when data receive ends.
[2.2.3]#
Improvements
Changed parameter type in LPUART_RTOS_Init struct from rtos_lpuart_config to lpuart_rtos_config_t.
Bug Fixes
Disabled LPUART receive interrupt instead of all NVICs when reading data from ring buffer. Otherwise when the ring buffer is used, receive nonblocking method will disable all NVICs to protect the ring buffer. This may has a negative effect on other IPs that are using the interrupt.
[2.2.2]#
Improvements
Added software reset feature support.
Added software reset API in LPUART_Init.
[2.2.1]#
Improvements
Added separate RX/TX IRQ number support.
[2.2.0]#
Improvements
Added support of 7 data bits and MSB.
[2.1.1]#
Improvements
Removed unnecessary check of event flags and assert in LPUART_RTOS_Receive.
Added code to always wait for RX event flag in LPUART_RTOS_Receive.
[2.1.0]#
Improvements
Update transactional APIs.
LPUART_DMA#
[2.4.0]#
Refer LPUART driver change log 2.1.0 to 2.4.0
LPUART_EDMA#
[2.4.0]#
Refer LPUART driver change log 2.1.0 to 2.4.0
MMU#
[2.0.1]#
Bug Fixes
Add assertions to prevent unsigned integer overflow in narrowing conversions from uint32_t to uint16_t
Add safe type conversion with temporary variables for address-to-LUT operations
Add bounds checking for unit count calculations in region mapping operations
Follow INT31-C CERT coding standard for safe narrowing conversions
[2.0.0]#
Initial version.
PDM#
[2.9.6]#
Improvements
Added instance-aware dispatch for PDM EVENT, PDM ERROR, HWVAD EVENT, and HWVAD ERROR IRQ handlers while preserving existing wrapper compatibility.
[2.9.5]#
Improvements
Updated PDM_ReadFifo shifting logic for variable dataWidth (4/3/2/1 -> shift 0/8/16/24).
[2.9.4]#
Improvements
support multiple IRQ handlers
[2.9.3]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.9.2]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.9.1]#
Bug Fixes
Fixed the issue that the driver still enters the interrupt after disabling clock.
[2.9.0]#
Improvements
Added feature FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS to config CTRL_2[DEC_BYPASS] field.
Modify code to make the OSR value is not limited to 16.
[2.8.1]#
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_DOZEN to handle nonexistent CTRL_1[DOZEN] field.
[2.8.0]#
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_HWVAD to remove the support of hadware voice activity detector.
Added feature FSL_FEATURE_PDM_HAS_NO_FILTER_BUFFER to remove the support of FIR_RDY bitfield in STAT register.
[2.7.4]#
Bug Fixes
Fixed driver can not determine the specific float number of clock divider.
Fixed PDM_ValidateSrcClockRate calculates PDM channel in wrong method issue.
[2.7.3]#
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_VADEF to remove the support of VADEF bitfield in VAD0_STAT register.
[2.7.2]#
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV to decide whether the minimum clock frequency division is required.
[2.7.1]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.3, 10.1, 10.4, 14.4
[2.7.0]#
Improvements
Added api PDM_EnableHwvadInterruptCallback to support handle hwvad IRQ in PDM driver.
Corrected the sample rate configuration for non high quality mode.
Added api PDM_SetChannelGain to support adjust the channel gain.
[2.6.0]#
Improvements
Added new features FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ/FSL_FEATURE_PDM_HAS_DC_OUT_CTRL/FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED.
[2.5.0]#
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 16.5, 10.4, 10.3, 10.1, 11.9, 17.7, 10.6, 14.4, 11.8, 11.6.
[2.4.1]#
Bug Fixes
Fixed MDK 66-D warning in pdm driver.
[2.4.0]#
Improvements
Added api PDM_TransferSetChannelConfig/PDM_ReadFifo to support read different width data.
Added feature FSL_FEATURE_PDM_HAS_RANGE_CTRL and api PDM_ClearRangeStatus/PDM_GetRangeStatus for range register.
Bug Fixes
Fixed violation of MISRA C-2012 Rule 14.4, 10.3, 10.4.
[2.3.0]#
Improvements
Enabled envelope/energy voice detect mode by adding apis PDM_SetHwvadInEnvelopeBasedMode/PDM_SetHwvadInEnergyBasedMode.
Added feature FSL_FEATURE_PDM_CHANNEL_NUM for different SOC.
[2.2.1]#
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.6, 10.7, 11.3, 11.8, 14.4, 17.7, 18.4.
Added medium quality mode support in function PDM_SetSampleRateConfig.
[2.2.0]#
Improvements
Added api PDM_SetSampleRateConfig to improve user experience and marked api PDM_SetSampleRate as deprecated.
[2.1.1]#
Improvements
Used new SDMA API SDMA_SetDoneConfig instead of SDMA_EnableSwDone for PDM SDMA driver.
[2.1.0]#
Improvements
Added software buffer queue for transactional API.
[2.0.1]#
Improvements
Improved HWVAD feature.
[2.0.0]#
Initial version.
PDM_EDMA#
[2.6.5]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8.
[2.6.4]#
Improvements
Add handling for runtime change of number of linked transfers
[2.6.3]#
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.6.2]#
Improvements
Add macro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL to let the user decide whether to enable it when calling PDM_TransferReceiveEDMA.
[2.6.1]#
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.3, 10.4.
[2.6.0]#
Improvements
Updated api PDM_TransferReceiveEDMA to support channel block interleave transfer.
Added new api PDM_TransferSetMultiChannelInterleaveType to support channel interleave type configurations.
[2.5.0]#
Refer PDM driver change log 2.1.0 to 2.5.0
PDM_SDMA#
[2.7.1]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.7.0]#
Improvements
Added new api PDM_TransferTerminateReceiveSDMA to reset all PDM SDMA internal state machine.
[2.6.0]#
Bug Fixes
Fixed burst length overflow issue when using multi fifo.
Added alignment check between transfer size and the fifo width.
[2.5.0]#
Refer PDM driver change log 2.1.0 to 2.3.1
PWM#
[2.10.1]#
Bug Fixes
Fixed MISRA C-2012 Rule 17.7, 20.6, 16.3, 10.8
[2.10.0]#
Improvements
Added API
PWM_EnableLocalForceto perform a software-controlled local force initialization, causing a FORCE_OUT event that latches all pending FORCE-buffered shadow registers (DTSRCSEL, MCTRL[IPOL], SWCOUT) into their active registers.Added API
PWM_UpdateCurrentPolarityto selecting which VAL comparator pair drives the complementary output pair. The change takes effect only after a subsequent FORCE_OUT event (e.g. via PWM_EnableLocalForce).
[2.9.4]#
Bug Fixes
Fixed CERT INT31-C issues.
[2.9.3]#
Improvements
Cherry-pick patch from hal_nxp repository. Enhanced input validation in PWM_SetupPwm by returning kStatus_InvalidArgument when the calculated pulse count exceeds UINT16_MAX, to prevent silent failures when assertions are disabled in production builds.
[2.9.2]#
Improvements
Add new API
PWM_GetInputCaptureValueto read the value captured from the submodule counter.
[2.9.1]#
Improvements
Add new API
PWM_SetupFaultsExtandPWM_SetupFaultInputFilterExtto support FlexPWM which has more than one fault input channels.Support fault 4-7 interrupt and its flag.
Bug Fixes
Fixed violations of the CERT INT31-C.
[2.9.0]#
Improvements
Support PWMX channel output for edge aligned PWM.
Forbid submodule 0 counter initialize with master sync and master reload mode.
Clarify
kPWM_BusClockmeaning.Verify
pulseCntwithin 65535 when update period register.
[2.8.4]#
Improvements
Support workaround for ERR051989. This function helps realize no phase delay between submodule 0 and other submodule.
[2.8.3]#
Bug Fixes
Fixed MISRA C-2012 Rule 15.7
[2.8.2]#
Bug Fixes
Fixed warning conversion from ‘int’ to ‘uint16_t’ on API PWM_Init.
Fixed warning unused variable ‘reg’ on API PWM_SetPwmForceOutputToZero.
[2.8.1]#
Improvements
Release peripheral from reset if necessary in init function.
[2.8.0]#
Improvements
Added API PWM_UpdatePwmPeriodAndDutycycle to update the PWM signal’s period and dutycycle for a PWM submodule.
Added API PWM_SetPeriodRegister and PWM_SetDutycycleRegister to merge duplicate code in API PWM_SetupPwm, PWM_UpdatePwmDutycycleHighAccuracy and PWM_UpdatePwmPeriodAndDutycycle
[2.7.1]#
Improvements
Supported UPDATE_MASK bit in MASK register.
[2.7.0]#
Improvements
Supported platforms which don’t have Capture feature with channel A and B.
Supported platforms which don’t have Submodule 3.
Added assert function in API PWM_SetPhaseDelay to prevent wrong argument.
[2.6.1]#
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3.
[2.6.0]#
Improvements
Added API PWM_SetPhaseDelay to set the phase delay from the master sync signal of submodule 0.
Added API PWM_SetFilterSampleCountthe to set number of consecutive samples that must agree prior to the input filter.
Added API PWM_SetFilterSamplePeriod to set set the sampling period of the fault pin input filter.
[2.5.1]#
Bug Fixes
Fixed MISRA C-2012 rules: 10.1, 10.3, 10.4 , 10.6 and 10.8.
Fixed the issue that PWM_UpdatePwmDutycycle() can’t update duty cycle status value correct.
[2.5.0]#
Improvements
Added API PWM_SetOouputToIdle to set pwm channel output to idle.
Added API PWM_GetPwmChannelState to get the pwm channel output duty cycle value.
Added API PWM_SetPwmForceOutputToZero to set the pwm channel output to zero logic.
Added API PWM_SetChannelOutput to set the pwm channel output state.
Added API PWM_SetClockMode to set the value of the clock prescaler.
Added API PWM_SetupPwmPhaseShift to set PWM which a special phase shift and 50% duty cycle.
Added API PWM_SetVALxValue/PWM_GetVALxValue to set/get PWM VALs registers values directly.
[2.4.0]#
Improvements
Supported the PWM which can’t work in wait mode.
[2.3.0]#
Improvements
Add PWM output enable&disbale API for SDK.
Bug Fixes
Fixed changing channel B configuration when parameter is kPWM_PWMX and PWMX configuration is not supported yet.
[2.2.1]#
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3, 10.4.
Bug Fixes
Fixed the issue that PWM drivers computed VAL1 improperly.
Improvements
Updated calculation accuracy of reloadValue in dutyCycleToReloadValue function.
[2.2.0]#
Improvements
Added new enumeration and two APIs to support enabling and disabling one or more PWM output triggers.
Added a new function to make the most of 16-bit resolution PWM.
Added one API to support updating fault status of PWM output.
Added one API to support PWM DMA write request.
Added three APIs to support PWM DMA capture read request.
Added one API to support get default fault config of PWM.
Added one API to support setting PWM fault disable mapping.
[2.1.0]#
Improvements
Moved the configuration of fault input filter into a new API to avoid be initialized multiple times.
Bug Fixes
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.2, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-14.4, rule-16.4.
[2.0.1]#
Bug Fixes
Fixed the issue that PWM submodule may be initialized twice in function PWM_SetupPwm().
[2.0.0]#
Initial version.
SAI#
[2.4.11]#
Bug Fixes
Fixed MSG findings for platforms with multiple FIFO size support.
[2.4.10]#
Improvements
Allow enabling/disabling implicit channel configuration.
Allow NULL FIFO watermark.
Bug Fixes
Fix compilation warnings when asserts are disabled
[2.4.9]#
Added Errata ERR051421 workaround.
[2.4.8]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.4.7]#
Added conditional support for bit clock swap feature
Added common IRQ handler entry SAI_DriverIRQHandler.
[2.4.6]#
Bug Fixes
Fixed the IAR build warning.
[2.4.5]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.4.4]#
Bug Fixes
Fixed enumeration sai_fifo_combine_t - add RX configuration.
[2.4.3]#
Bug Fixes
Fixed enumeration sai_fifo_combine_t value configuration issue.
[2.4.2]#
Improvements
Release peripheral from reset if necessary in init function.
[2.4.1]#
Bug Fixes
Fixed bitWidth incorrectly assigned issue.
[2.4.0]#
Improvements
Removed deprecated APIs.
[2.3.8]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.3.7]#
Improvements
Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.
Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function
[2.3.6]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 5.6.
[2.3.5]#
Improvements
Make driver to be aarch64 compatible.
[2.3.4]#
Bug Fixes
Corrected the fifo combine feature macro used in driver.
[2.3.3]#
Bug Fixes
Added bit clock polarity configuration when sai act as slave.
Fixed out of bound access coverity issue.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.3.2]#
Bug Fixes
Corrected the frame sync configuration when sai act as slave.
[2.3.1]#
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
Fixed violations of MISRA C-2012 rule 17.7.
[2.3.0]#
Bug Fixes
Fixed the build error caused by the SOC has no fifo feature.
[2.2.3]#
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
[2.2.2]#
Bug Fixes
Fixed the issue of MISRA 2004 rule 9.3.
Fixed sign-compare warning.
Fixed the PA082 build warning.
Fixed sign-compare warning.
Fixed violations of MISRA C-2012 rule 10.3,17.7,10.4,8.4,10.7,10.8,14.4,17.7,11.6,10.1,10.6,8.4,14.3,16.4,18.4.
Allow to reset Rx or Tx FIFO pointers only when Rx or Tx is disabled.
Improvements
Added 24bit raw audio data width support in sai sdma driver.
Disabled the interrupt/DMA request in the SAI_Init to avoid generates unexpected sai FIFO requests.
[2.2.1]#
Improvements
Added mclk post divider support in function SAI_SetMasterClockDivider.
Removed useless configuration code in SAI_RxSetSerialDataConfig.
Bug Fixes
Fixed the SAI SDMA driver build issue caused by the wrong structure member name used in the function SAI_TransferRxSetConfigSDMA/SAI_TransferTxSetConfigSDMA.
Fixed BAD BIT SHIFT OPERATION issue caused by the FSL_FEATURE_SAI_CHANNEL_COUNTn.
Applied ERR05144: not set FCONT = 1 when TMR > 0, otherwise the TX may not work.
[2.2.0]#
Improvements
Added new APIs for parameters collection and simplified user interfaces:
SAI_Init
SAI_SetMasterClockConfig
SAI_TxSetBitClockRate
SAI_TxSetSerialDataConfig
SAI_TxSetFrameSyncConfig
SAI_TxSetFifoConfig
SAI_TxSetBitclockConfig
SAI_TxSetConfig
SAI_TxSetTransferConfig
SAI_RxSetBitClockRate
SAI_RxSetSerialDataConfig
SAI_RxSetFrameSyncConfig
SAI_RxSetFifoConfig
SAI_RxSetBitclockConfig
SAI_RXSetConfig
SAI_RxSetTransferConfig
SAI_GetClassicI2SConfig
SAI_GetLeftJustifiedConfig
SAI_GetRightJustifiedConfig
SAI_GetTDMConfig
[2.1.9]#
Improvements
Improved SAI driver comment for clock polarity.
Added enumeration for SAI for sample inputs on different edges.
Changed FSL_FEATURE_SAI_CHANNEL_COUNT to FSL_FEATURE_SAI_CHANNEL_COUNTn(base) for the difference between the different SAI instances.
Added new APIs:
SAI_TxSetBitClockDirection
SAI_RxSetBitClockDirection
SAI_RxSetFrameSyncDirection
SAI_TxSetFrameSyncDirection
[2.1.8]#
Improvements
Added feature macro test for the sync mode2 and mode 3.
Added feature macro test for masterClockHz in sai_transfer_format_t.
[2.1.7]#
Improvements
Added feature macro test for the mclkSource member in sai_config_t.
Changed “FSL_FEATURE_SAI5_SAI6_SHARE_IRQ” to “FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ”.
Added #ifndef #endif check for SAI_XFER_QUEUE_SIZE to allow redefinition.
Bug Fixes
Fixed build error caused by feature macro test for mclkSource.
[2.1.6]#
Improvements
Added feature macro test for mclkSourceClockHz check.
Added bit clock source name for general devices.
Bug Fixes
Fixed incorrect channel numbers setting while calling RX/TX set format together.
[2.1.5]#
Bug Fixes
Corrected SAI3 driver IRQ handler name.
Added I2S4/5/6 IRQ handler.
Added base in handler structure to support different instances sharing one IRQ number.
New Features
Updated SAI driver for MCR bit MICS.
Added 192 KHZ/384 KHZ in the sample rate enumeration.
Added multi FIFO interrupt/SDMA transfer support for TX/RX.
Added an API to read/write multi FIFO data in a blocking method.
Added bclk bypass support when bclk is same with mclk.
[2.1.4]#
New Features
Added an API to enable/disable auto FIFO error recovery in platforms that support this feature.
Added an API to set data packing feature in platforms which support this feature.
[2.1.3]#
New Features
Added feature to make I2S frame sync length configurable according to bitWidth.
[2.1.2]#
Bug Fixes
Added 24-bit support for SAI eDMA transfer. All data shall be 32 bits for send/receive, as eDMA cannot directly handle 3-Byte transfer.
[2.1.1]#
Improvements
Reduced code size while not using transactional API.
[2.1.0]#
Improvements
API name changes:
SAI_GetSendRemainingBytes -> SAI_GetSentCount.
SAI_GetReceiveRemainingBytes -> SAI_GetReceivedCount.
All names of transactional APIs were added with “Transfer” prefix.
All transactional APIs use base and handle as input parameter.
Unified the parameter names.
Bug Fixes
Fixed WLC bug while reading TCSR/RCSR registers.
Fixed MOE enable flow issue. Moved MOE enable after MICS settings in SAI_TxInit/SAI_RxInit.
[2.0.0]#
Initial version.
SAI_DMA#
[2.4.0]#
Removed deprecated API.
[2.3.2]#
Refer SAI driver change log 2.1.0 to 2.3.2
SAI_EDMA#
[2.7.4]#
Bug Fixes
Fixed MSG finding for platforms with multiple FIFO size support.
[2.7.3]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 12.4.
[2.7.2]#
Improvements
Add macros MCUX_SDK_SAI_EDMA_TX_ENABLE_INTERNAL and MCUX_SDK_SAI_EDMA_RX_ENABLE_INTERNAL to let the user decide whether to enable SAI when calling SAI_TransferSendEDMA/SAI_TransferReceiveEDMA.
[2.7.1]#
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.7.0]#
Improvements
Updated api SAI_TransferReceiveEDMA to support voice channel block interleave transfer.
Updated api SAI_TransferSendEDMA to support voice channel block interleave transfer.
Added new api SAI_TransferSetInterleaveType to support channel interleave type configurations.
[2.6.0]#
Improvements
Removed deprecated APIs.
[2.5.1]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 20.7.
[2.5.0]#
Improvements
Added new api SAI_TransferSendLoopEDMA/SAI_TransferReceiveLoopEDMA to support loop transfer.
Added multi sai channel transfer support.
[2.4.0]#
Improvements
Added new api SAI_TransferGetValidTransferSlotsEDMA which can be used to get valid transfer slot count in the sai edma transfer queue.
Deprecated the api SAI_TransferRxSetFormatEDMA and SAI_TransferTxSetFormatEDMA.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3,10.4.
[2.3.2]#
Refer SAI driver change log 2.1.0 to 2.3.2
SAI_SDMA#
[2.6.1]#
Bug Fixes
Fixed MSG findings of INT31-C
[2.6.0]#
Improvements
Removed deprecated API (SAI_TransferTxSetFormatSDMA,SAI_TransferRxSetFormatSDMA) and replaced them with new API (SAI_TransferRxSetConfigSDMA,SAI_TransferRxSetConfigSDMA)
[2.5.3]#
Bug Fixes
Fixed the internal state of bd pool can not be reset in SAI_TransferTerminateSendSDMA.
[2.5.2]#
Improvements
Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.
Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function
[2.5.1]#
Bug Fixes
Fixed the incorrect internal queue state after abort the transfer in callback.
[2.5.0]#
Bug Fixes
Fixed the incorrect driver queue state after calling abort function.
Improvements
Added new api SAI_TransferTerminateSendSDMA/SAI_TransferTerminateReceiveSDMA.
[2.4.1]#
Bug Fixes
Fixed the handler array s_sdmaPrivateHandle overflow issue.
[2.4.0]#
Bug Fixes
Fixed burst length overflow issue when using multi fifo.
Added alignment check between transfer size and the fifo width.
Fixed violations of MISRA C-2012 rule 10.6.
[2.3.1]#
Refer SAI driver change log 2.1.0 to 2.3.1
SINC#
[2.1.5]#
Bug Fixes
Fixed building warning.
[2.1.4]#
Bug Fixes
Fixed building issue.
[2.1.3]#
Bug Fixes
Fixed function ‘SINC_SetChannelProtectionOption’ logic operation error.
[2.1.2]#
Bug Fixes
Fixed the typo issue of missing character ‘U’ in the feature macro ‘FSL_FEATRE_SINC_CACFR_HAS_NO_PTMUX’.
[2.1.1]#
Bug Fixes
Fixed MISRA C-2012 rule 10.4 and 10.8 issues.
[2.1.0]#
Improvements
Added support for chips that each instance equipped with 5 channels.
[2.0.2]#
Improvements
Added comments for over sample ratio.
[2.0.1]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 15.6, 10.4, 10.1, 10.3 and 10.7.
[2.0.0]#
Initial version.
SRAMCTL#
[3.0.0]#
Initial version.
STM#
[2.0.1]#
Bug Fixes
Fixed coverity and msg violations caused by potential out of bounds array operation.
[2.0.0]#
Initial version.
SWT#
[2.1.2]#
Bug Fixes
Wait until the timeout interrupt flag is cleared after writing W1C to avoid duplicate timeout IRQ entries.
[2.1.1]#
Improvements
Handle errata ERR052226: Toggling watchdog enable may cause unexpected timeout in some boundary conditions. Update SWT_SetTimeoutValue() update SWT with the watchdog keys to restart the counter value before setting a new timeout value.
[2.1.0]#
Bug Fixes
Fixed CERT-C violations: CERT INT31-C, CERT INT30-C
New Features
Added SWT_Refresh() API to automatically select a correct refresh service mode.
[2.0.0]#
Initial version.
TDET#
[2.4.0]#
Added support for MIMXRT2663.
[2.3.3]#
Fix MISRA and CERT-C findings.
[2.3.2]#
New Features
Added common IRQ handler entry TDET_DriverIRQHandler.
[2.3.1]#
Added support for KW43 device.
[2.3.0]#
Added enum for TIF10.
[2.2.0]#
Added support for chips without active tamper pins.
[2.1.1]#
Added clearing SR_TAF and SR_DTF into TDET_Init().
Fix typo in kTDET_ClockType64Hz comment.
[2.1.0]#
Added setting of disabling prescaler on tamper event into TDET_SetConfig() and TDET_GetDefaultConfig functions.
[2.0.0]#
Initial version.
TPM#
[2.5.0]#
Improvements
Added
TPM_GetChannelControlBitsAPI to replace the misspelledTPM_GetChannelContorlBits, which is now marked as deprecated.
[2.4.6]#
Improvements
Added feature macro
FSL_FEATURE_TPM_HAS_NO_SC_CPWMSto support SoCs whose TPM SC register does not have the CPWMS field.
[2.4.5]#
Improvements
Added branch coverage justification comments and GCOVR_EXCL_BR_LINE markers for structurally unreachable branches in
TPM_UpdatePwmDutycycle.
[2.4.4]#
Bug Fixes
Fixed CERT INT31-C: removed unsafe
(uint8_t)cast onFSL_FEATURE_TPM_HAS_32BIT_COUNTERn()(which returns int with possible value -1) inTPM_MAX_COUNTER_VALUEmacro andTPM_SetTimerPeriod; now uses direct int comparison to avoid truncation.
[2.4.3]#
Bug Fixes
Fixed CERT INT31-C Coverity issue: Casting from int to unsigned char without checking its value may result in lost or misinterpreted data.
[2.4.2]#
Bug Fixes
Fixed CERT INT30-C INT31-C issue for:
Unsigned integer operation may wrap.
Casting from “int” to “unsigned char” may result in lost or misinterpreted data.
[2.4.1]#
Improvements
Add Coverage Justification for uncovered code.
[2.4.0]#
New Feature
Added while loop timeout for MOD CnV CnSC and SC register write sequence.
Change the return type from void to status_t for following API:
TPM_DisableChannelTPM_EnableChannelTPM_SetupOutputCompareTPM_SetTimerPeriodTPM_StopTimer
[2.3.6]#
Bug Fixes
Fixed CERT INT30-C INT31-C issue for
TPM_SetupDualEdgeCapture.
[2.3.5]#
New Feature
Added IRQ handler entry for TPM2.
[2.3.4]#
New Feature
Added common IRQ handler entry TPM_DriverIRQHandler.
[2.3.3]#
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.2]#
Bug Fixes
Fixed ERR008085 TPM writing the TPMx_MOD or TPMx_CnV registers more than once may fail when the timer is disabled.
[2.3.1]#
Bug Fixes
Fixed compilation error when macro FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is 1.
[2.3.0]#
Improvements
Create callback feature for TPM match and timer overflow interrupts.
[2.2.4]#
Improvements
Add feature macros(FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN, FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC).
[2.2.3]#
Improvements
Release peripheral from reset if necessary in init function.
[2.2.2]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.2.1]#
Bug Fixes
Fixed CCM issue by splitting function from TPM_SetupPwm() function to reduce function complexity.
Fixed violations of MISRA C-2012 rule 17.7.
[2.2.0]#
Improvements
Added TPM_SetChannelPolarity to support select channel input/output polarity.
Added TPM_EnableChannelExtTrigger to support enable external trigger input to be used by channel.
Added TPM_CalculateCounterClkDiv to help calculates the counter clock prescaler.
Added TPM_GetChannelValue to support get TPM channel value.
Added new TPM configuration.
syncGlobalTimeBase
extTriggerPolarity
chnlPolarity
Added new PWM signal configuration.
secPauseLevel
Bug Fixes
Fixed TPM_SetupPwm can’t configure 0% combined PWM issues.
[2.1.1]#
Improvements
Add feature macro for PWM pause level select feature.
[2.1.0]#
Improvements
Added TPM_EnableChannel and TPM_DisableChannel APIs.
Added new PWM signal configuration.
pauseLevel - Support select output level when counter first enabled or paused.
enableComplementary - Support enable/disable generate complementary PWM signal.
deadTimeValue - Support deadtime insertion for each pair of channels in combined PWM mode.
Bug Fixes
Fixed issues about channel MSnB:MSnA and ELSnB:ELSnA bit fields and CnV register change request acknowledgement. Writes to these bits are ignored when the interval between successive writes is less than the TPM clock period.
[2.0.8]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.4 ,10.7 and 14.4.
[2.0.7]#
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4 and 17.7.
[2.0.6]#
Bug Fixes
Fixed Out-of-bounds issue.
[2.0.5]#
Bug Fixes
Fixed MISRA-2012 rules.
Rule 10.6, 10.7
[2.0.4]#
Bug Fixes
Fixed ERR050050 in functions TPM_SetupPwm/TPM_UpdatePwmDutycycle. When TPM was configured in EPWM mode as PS = 0, the compare event was missed on the first reload/overflow after writing 1 to the CnV register.
[2.0.3]#
Bug Fixes
MISRA-2012 issue fixed.
Fixed rules: rule-12.1, rule-17.7, rule-16.3, rule-14.4, rule-1.3, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-10.6, and rule-18.1.
[2.0.2]#
Bug Fixes
Fixed issues in functions TPM_SetupPwm/TPM_UpdateChnlEdgeLevelSelect /TPM_SetupInputCapture/TPM_SetupOutputCompare/TPM_SetupDualEdgeCapture, wait acknowledgement when the channel is disabled.
[2.0.1]#
Bug Fixes
Fixed TPM_UpdateChnIEdgeLevelSelect ACK wait issue.
Fixed the issue that TPM_SetupdualEdgeCapture could not set FILTER register.
Fixed TPM_UpdateChnEdgeLevelSelect ACK wait issue.
[2.0.0]#
Initial version.
TRDC#
[2.3.1]#
Improvements
Update APIs to check whether the memory access configuration can be updated.
Update APIs to mask the MRC address since only high 18 bits are valid.
[2.3.0]#
New Features
Added API TRDC_EnableProcessorDomainAssignment to disable/enable DAC.
Bug Fixes
Fixed MISRA violation of missing function declaration.
Fixed wrong operation of domain mask in TRDC_MbcNseClearAll and TRDC_MrcDomainNseClear.
[2.2.1]#
Bug Fixes
Fixed MISRA violations of rule 10.3.
[2.2.0]#
New Features
Added new APIs to support SoC with more than one processor core.
[2.1.1]#
Bug Fixes
Fixed MISRA violations of rule 10.3, 10.6, 10.7 and 18.1.
[2.1.0]#
Improvements
Modified some of the addressing method according to the device header file’s update.
Modified flash address configuration structure and default setting.
New Features
Added API to set flash logic window array address.
Bug Fixes
Fixed wrong return value of TRDC_GetFlashLogicalWindowPbase.
Fixed bug in TRDC_GetAndClearFirstSpecificDomainError that the error status is cleared by mistake before obtained by software.
Fixed MISRA violations of rule 10.3, 10.4, 10.6 and 10.8.
[2.0.0]#
Initial version.
XSPI#
[2.7.7]#
Bug Fixes
Fixed CID 51973698 NO_EFFECT in XSPI_UpdateSFPConfig() where the non-EENV FRAD word2/word3 update was redundantly executed once per target group instead of once per FRAD region.
[2.7.6]#
Bug Fixes
Fixed CERT-C INT31-C violations in XSPI_TG_REG_ADDR_xxx macros
[2.7.5]#
Bug Fixes
Fixed CERT-C INT30-C violations in
XSPI_WriteBlockingTGandXSPI_CommonIRQHandler.Fixed
XSPI1_0–XSPI1_4IRQ handlers to route throughXSPI_DriverIRQHandlerwith proper instance and envId bounds validation.
[2.7.4]#
New Features
Added common IRQ handler entry XSPI_DriverIRQHandler.
[2.7.3]#
Bug Fixes
Fixed CERT-C INT30-C and ARR30-C violations in XSPI_TransferBlocking, XSPI_WriteBlockingTG, XSPI_ReadBlockingTG, and XSPI_IRQHandler.
[2.7.2]#
Bug Fixes
Fixed typo where ptrSubBuffer2Config incorrectly used XSPI_BUFCR_SUBBUF1_DIV instead of XSPI_BUFCR_SUBBUF2_DIV.
[2.7.1]#
Bug Fixes
TGIPCRS[VLD] bit polling fix for cortex-m33 core1 in NETCMIX on i.MX943 Skip checking the TGIPCRS[VLD] bit to resolve an issue where the bit transition from 0 to 1 is extremely short, causing the master to read 0 and poll indefinitely. This issue occurs when the master is Cortex-M33 Core1 in NETCMIX on i.MX943. Note: The bit functions correctly when the master is Cortex-M7 Core0 in M7MIX0 or Cortex-M7 Core1 in M7MIX1.
[2.7.0]#
New Features
Added EENV support to setup XSPI based on diffferent target groups.
Bug Fixes
Fixed issue of XSPI_UpdateSFPConfig() function. Disabled all global MDAD and FRAD setting before updating.
[2.6.1]#
Improvements
Support for macro to place functions in RAM. Functions of file needs to be place in RAM while using XSPI1 for RT700.
Support added to place variables in RAM. Its required when code from ram is using these variables.
Bug Fixes
Add explicit boolean to integer conversions (? 1UL : 0UL) for enable flags in DLL configuration, data learning, device config, and AHB buffer settings.
Add assertions to prevent unsigned integer overflow in address increment operations.
Add assertions to prevent unsigned integer underflow in size subtraction operations.
Add safe type conversion with temporary variables for uint64_t to uint32_t operations in interrupt mask handling.
Add bounds checking for array access and enum value validation.
Add assertions for narrowing conversions in byte extraction operations.
Follow INT30-C and INT31-C CERT coding standards for safe integer operations.
[2.6.0]#
Improvements
Added feature macro support for devices with reserved register bit fields to improve compatibility across different device variants.
FSL_FEATURE_XSPI_HAS_DQS_LAT_EN
FSL_FEATURE_XSPI_HAS_END_CFG
FSL_FEATURE_XSPI_HAS_DOZE_MODE
Enhanced register access handling using conditional compilation to accommodate hardware differences.
Added supports of MAIN_XSPI0_DriverIRQHandler() and MAIN_XSPI1_DriverIRQHandler.
New Features
Added AHB write terminate functionality support for devices with FSL_FEATURE_XSPI_HAS_WRTER_EN_BIT.
New API: XSPI_EnableAhbWriteTerminate() to control AHB write termination of read-prefetch operations.
New configuration field: enableWriteTerminate in xspi_ahb_access_config_t structure.
[2.5.2]#
Improvements
Fixed an issue with incorrect cache range address calculation. It caused issue when the cache operation size is equal to a multiple of the cache line size + 1.
[2.5.1]#
Improvements
Updated default value of sfpArbitrationLockTimeoutValue and ipAccessTimeoutValue to 0xFFFFFFFFUL.
Added #if defined(CACHE64_CTRL0_BASE) … #endif section to support some devices that do not support CACHE64.
[2.5.0]#
Improvements
Updated XSPI_TransferBlocking() to support use case the transfersize bigger than page size.
Updated xspi_device_interface_type_t to support changes of page size for hyperram interface.
Updated XSPI_ReadBlocking() to fix an potential issue which cause TIMEOUT error.
[2.4.0]#
New Features
Added functions of control cache64.
[2.3.0]#
Improvements
Added new interface: XSPI_StartIpAccessNonBlocking();
Provied driver Irq handler for xspi driver;
Use ERRSTAT[ARB_WIN] to replace FSMSTAT[VLD].
[2.2.1]#
Improvements
Moved some frequently used variables(s_tgSfarsRegOffset, s_tgIpcrsRegOffset, s_sfpTgIpcrRegOffset, s_sfpTgIpSfarRegOffset, s_tgMdadRegOffset) to common code to offload of stack.
Added return status in case of timeout flag asserted during IP read access.
Bug Fixes
Fixed violations of MISRA C-2012 rules.
[2.2.0]#
Improvements
Improved xspi_device_config_t structure, removed some not-device related members.
Improved xspi_config_t structure, removed some device related settings.
Renamed XSPI_SetFlashConfig() to XSPI_SetDeviceConfig().
Decoupled settings of IP access, AHB access.
Added low-level interfaces to support IP access(including SFP), and AHB access(including performance monitor).
[2.1.0]#
Bug Fixes
Fixed issue of XSPI_Init() function, set MCR[MDIS] to disable clocks before settings of MCR register.
Unused deviceConfig in XSPI_GetDefaultConfig() function.
Improvements
Updated structure for dllconfig, added method to allow user custom dll parameters.
Updated XSPI_UpdateDllValue() function to align with changes of dllconfig.
Move device specific value to device feature file.
[2.0.1]#
Bug Fixes
Fixed the XSPI DLL function.
Added ALIGN and X16Mode macro definition in driver.
updated XSPI PSRAM example.
[2.0.0]#
Initial version.
XSPI EDMA Driver#
[2.0.4]#
Bug Fixes
Fixed violations in XSPI_TransferEDMACallback() function, avoid warning of unused parameters.
[2.0.3]#
Bug Fixes
Fixed violations of MSG.
[2.0.2]#
Bug Fixes
Fixed violations of MISRA C-2012 rules.
[2.0.1]#
Improvements
Invoked new defined interface of xspi driver.
In callback function, disable RX/TX DMA.
[2.0.0]#
Initial version.
CLOCK#
[1.1.0]#
New Features
Add CLOCK_MeasureRootClockFreq() to measure the real root clock frequency.
Add CLOCK_MeasureClockSrcFreq() to measure the real clock source frequency.
[1.0.0]#
Initial version.
EDMA SOC#
[2.0.0]#
Initial version.
INPUTMUX Connections#
[2.0.1]#
Bug Fixes
Fixed wrong number of connections for main_freq and comm_freq
[2.0.0]#
Initial version.
IOMUXC#
[2.0.0]#
Initial version.
MCM#
[1.0.0]#
Initial version.
MEMCON#
[1.0.0]#
Initial version.
MEMORY#
[1.0.0]#
Initial version.
MIPI DSI SOC#
[2.0.0]#
Initial version.
MODCON#
[1.0.0]#
Initial version.
RESETCON#
[1.0.0]#
Initial version.
TRDC SOC#
[2.0.0]#
Initial version.
VBATCON#
[1.0.0]#
Initial version.