MIMXRT1176

ACMP: Analog Comparator Driver

void ACMP_Init(CMP_Type *base, const acmp_config_t *config)

Initializes the ACMP.

The default configuration can be got by calling ACMP_GetDefaultConfig().

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to ACMP configuration structure.

void ACMP_Deinit(CMP_Type *base)

Deinitializes the ACMP.

Parameters:

• base – ACMP peripheral base address.

void ACMP_GetDefaultConfig(acmp_config_t *config)

Gets the default configuration for ACMP.

This function initializes the user configuration structure to default value. The default value are:

Example:

config->enableHighSpeed = false;
config->enableInvertOutput = false;
config->useUnfilteredOutput = false;
config->enablePinOut = false;
config->enableHysteresisBothDirections = false;
config->hysteresisMode = kACMP_hysteresisMode0;

Parameters:

• config – Pointer to ACMP configuration structure.

void ACMP_Enable(CMP_Type *base, bool enable)

Enables or disables the ACMP.

Parameters:

• base – ACMP peripheral base address.

• enable – True to enable the ACMP.

void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable)

Enables the link from CMP to DAC enable.

When this bit is set, the DAC enable/disable is controlled by the bit CMP_C0[EN] instead of CMP_C1[DACEN].

Parameters:

• base – ACMP peripheral base address.

• enable – Enable the feature or not.

void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config)

Sets the channel configuration.

Note that the plus/minus mux’s setting is only valid when the positive/negative port’s input isn’t from DAC but from channel mux.

Example:

acmp_channel_config_t configStruct = {0};
configStruct.positivePortInput = kACMP_PortInputFromDAC;
configStruct.negativePortInput = kACMP_PortInputFromMux;
configStruct.minusMuxInput = 1U;
ACMP_SetChannelConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to channel configuration structure.

void ACMP_EnableDMA(CMP_Type *base, bool enable)

Enables or disables DMA.

Parameters:

• base – ACMP peripheral base address.

• enable – True to enable DMA.

void ACMP_EnableWindowMode(CMP_Type *base, bool enable)

Enables or disables window mode.

Parameters:

• base – ACMP peripheral base address.

• enable – True to enable window mode.

void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config)

Configures the filter.

The filter can be enabled when the filter count is bigger than 1, the filter period is greater than 0 and the sample clock is from divided bus clock or the filter is bigger than 1 and the sample clock is from external clock. Detailed usage can be got from the reference manual.

Example:

acmp_filter_config_t configStruct = {0};
configStruct.filterCount = 5U;
configStruct.filterPeriod = 200U;
configStruct.enableSample = false;
ACMP_SetFilterConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to filter configuration structure.

void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config)

Configures the internal DAC.

Example:

acmp_dac_config_t configStruct = {0};
configStruct.referenceVoltageSource = kACMP_VrefSourceVin1;
configStruct.DACValue = 20U;
configStruct.enableOutput = false;
configStruct.workMode = kACMP_DACWorkLowSpeedMode;
ACMP_SetDACConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to DAC configuration structure. “NULL” is for disabling the feature.

void ACMP_SetRoundRobinConfig(CMP_Type *base, const acmp_round_robin_config_t *config)

Configures the round robin mode.

Example:

acmp_round_robin_config_t configStruct = {0};
configStruct.fixedPort = kACMP_FixedPlusPort;
configStruct.fixedChannelNumber = 3U;
configStruct.checkerChannelMask = 0xF7U;
configStruct.sampleClockCount = 0U;
configStruct.delayModulus = 0U;
ACMP_SetRoundRobinConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to round robin mode configuration structure. “NULL” is for disabling the feature.

void ACMP_SetRoundRobinPreState(CMP_Type *base, uint32_t mask)

Defines the pre-set state of channels in round robin mode.

Note: The pre-state has different circuit with get-round-robin-result in the SOC even though they are same bits. So get-round-robin-result can’t return the same value as the value are set by pre-state.

Parameters:

• base – ACMP peripheral base address.

• mask – Mask of round robin channel index. Available range is channel0:0x01 to channel7:0x80.

static inline uint32_t ACMP_GetRoundRobinStatusFlags(CMP_Type *base)

Gets the channel input changed flags in round robin mode.

Parameters:

• base – ACMP peripheral base address.

Returns:

Mask of channel input changed asserted flags. Available range is channel0:0x01 to channel7:0x80.

void ACMP_ClearRoundRobinStatusFlags(CMP_Type *base, uint32_t mask)

Clears the channel input changed flags in round robin mode.

Parameters:

• base – ACMP peripheral base address.

• mask – Mask of channel index. Available range is channel0:0x01 to channel7:0x80.

static inline uint32_t ACMP_GetRoundRobinResult(CMP_Type *base)

Gets the round robin result.

Note that the set-pre-state has different circuit with get-round-robin-result in the SOC even though they are same bits. So ACMP_GetRoundRobinResult() can’t return the same value as the value are set by ACMP_SetRoundRobinPreState.

Parameters:

• base – ACMP peripheral base address.

Returns:

Mask of round robin channel result. Available range is channel0:0x01 to channel7:0x80.

void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask)

Enables interrupts.

Parameters:

• base – ACMP peripheral base address.

• mask – Interrupts mask. See “_acmp_interrupt_enable”.

void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask)

Disables interrupts.

Parameters:

• base – ACMP peripheral base address.

• mask – Interrupts mask. See “_acmp_interrupt_enable”.

uint32_t ACMP_GetStatusFlags(CMP_Type *base)

Gets status flags.

Parameters:

• base – ACMP peripheral base address.

Returns:

Status flags asserted mask. See “_acmp_status_flags”.

void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)

Clears status flags.

Parameters:

• base – ACMP peripheral base address.

• mask – Status flags mask. See “_acmp_status_flags”.

void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config)

Configure the discrete mode.

Configure the discrete mode when supporting 3V domain with 1.8V core.

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to configuration structure. See “acmp_discrete_mode_config_t”.

void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config)

Get the default configuration for discrete mode setting.

Parameters:

• config – Pointer to configuration structure to be restored with the setting values.

FSL_ACMP_DRIVER_VERSION

ACMP driver version 2.3.0.

enum _acmp_interrupt_enable

Interrupt enable/disable mask.

Values:

enumerator kACMP_OutputRisingInterruptEnable

Enable the interrupt when comparator outputs rising.

enumerator kACMP_OutputFallingInterruptEnable

Enable the interrupt when comparator outputs falling.

enumerator kACMP_RoundRobinInterruptEnable

Enable the Round-Robin interrupt.

enum _acmp_status_flags

Status flag mask.

Values:

enumerator kACMP_OutputRisingEventFlag

Rising-edge on compare output has occurred.

enumerator kACMP_OutputFallingEventFlag

Falling-edge on compare output has occurred.

enumerator kACMP_OutputAssertEventFlag

Return the current value of the analog comparator output.

enum _acmp_offset_mode

Comparator hard block offset control.

If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.

Values:

enumerator kACMP_OffsetLevel0

The comparator hard block output has level 0 offset internally.

enumerator kACMP_OffsetLevel1

The comparator hard block output has level 1 offset internally.

enum _acmp_hysteresis_mode

Comparator hard block hysteresis control.

See chip data sheet to get the actual hysteresis value with each level.

Values:

enumerator kACMP_HysteresisLevel0

Offset is level 0 and Hysteresis is level 0.

enumerator kACMP_HysteresisLevel1

Offset is level 0 and Hysteresis is level 1.

enumerator kACMP_HysteresisLevel2

Offset is level 0 and Hysteresis is level 2.

enumerator kACMP_HysteresisLevel3

Offset is level 0 and Hysteresis is level 3.

enum _acmp_reference_voltage_source

CMP Voltage Reference source.

Values:

enumerator kACMP_VrefSourceVin1

Vin1 is selected as resistor ladder network supply reference Vin.

enumerator kACMP_VrefSourceVin2

Vin2 is selected as resistor ladder network supply reference Vin.

enum _acmp_port_input

Port input source.

Values:

enumerator kACMP_PortInputFromDAC

Port input from the 8-bit DAC output.

enumerator kACMP_PortInputFromMux

Port input from the analog 8-1 mux.

enum _acmp_fixed_port

Fixed mux port.

Values:

enumerator kACMP_FixedPlusPort

Only the inputs to the Minus port are swept in each round.

enumerator kACMP_FixedMinusPort

Only the inputs to the Plus port are swept in each round.

enum _acmp_dac_work_mode

Internal DAC’s work mode.

Values:

enumerator kACMP_DACWorkLowSpeedMode

DAC is selected to work in low speed and low power mode.

enumerator kACMP_DACWorkHighSpeedMode

DAC is selected to work in high speed high power mode.

typedef enum _acmp_offset_mode acmp_offset_mode_t

Comparator hard block offset control.

If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.

typedef enum _acmp_hysteresis_mode acmp_hysteresis_mode_t

Comparator hard block hysteresis control.

See chip data sheet to get the actual hysteresis value with each level.

typedef enum _acmp_reference_voltage_source acmp_reference_voltage_source_t

CMP Voltage Reference source.

typedef enum _acmp_port_input acmp_port_input_t

Port input source.

typedef enum _acmp_fixed_port acmp_fixed_port_t

Fixed mux port.

typedef enum _acmp_dac_work_mode acmp_dac_work_mode_t

Internal DAC’s work mode.

typedef struct _acmp_config acmp_config_t

Configuration for ACMP.

typedef struct _acmp_channel_config acmp_channel_config_t

Configuration for channel.

The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.

typedef struct _acmp_filter_config acmp_filter_config_t

Configuration for filter.

typedef struct _acmp_dac_config acmp_dac_config_t

Configuration for DAC.

typedef struct _acmp_round_robin_config acmp_round_robin_config_t

Configuration for round robin mode.

typedef struct _acmp_discrete_mode_config acmp_discrete_mode_config_t

Configuration for discrete mode.

CMP_C0_CFx_MASK

The mask of status flags cleared by writing 1.

CMP_C1_CHNn_MASK

CMP_C2_CHnF_MASK

struct _acmp_config

#include <fsl_acmp.h>

Configuration for ACMP.

Public Members

acmp_offset_mode_t offsetMode

Offset mode.

acmp_hysteresis_mode_t hysteresisMode

Hysteresis mode.

bool enableHighSpeed

Enable High Speed (HS) comparison mode.

bool enableInvertOutput

Enable inverted comparator output.

bool useUnfilteredOutput

Set compare output(COUT) to equal COUTA(true) or COUT(false).

bool enablePinOut

The comparator output is available on the associated pin.

struct _acmp_channel_config

#include <fsl_acmp.h>

Configuration for channel.

The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.

Public Members

acmp_port_input_t positivePortInput

Input source of the comparator’s positive port.

uint32_t plusMuxInput

Plus mux input channel(0~7).

acmp_port_input_t negativePortInput

Input source of the comparator’s negative port.

uint32_t minusMuxInput

Minus mux input channel(0~7).

struct _acmp_filter_config

#include <fsl_acmp.h>

Configuration for filter.

Public Members

bool enableSample

Using external SAMPLE as sampling clock input, or using divided bus clock.

uint32_t filterCount

Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.

uint32_t filterPeriod

Filter Sample Period. The divider to bus clock. Available range is 0-255.

struct _acmp_dac_config

#include <fsl_acmp.h>

Configuration for DAC.

Public Members

acmp_reference_voltage_source_t referenceVoltageSource

Supply voltage reference source.

uint32_t DACValue

Value for DAC Output Voltage. Available range is 0-255.

bool enableOutput

Enable the DAC output.

struct _acmp_round_robin_config

#include <fsl_acmp.h>

Configuration for round robin mode.

Public Members

acmp_fixed_port_t fixedPort

Fixed mux port.

uint32_t fixedChannelNumber

Indicates which channel is fixed in the fixed mux port.

uint32_t checkerChannelMask

Mask of checker channel index. Available range is channel0:0x01 to channel7:0x80 for round-robin checker.

uint32_t sampleClockCount

Specifies how many round-robin clock cycles(0~3) later the sample takes place.

uint32_t delayModulus

Comparator and DAC initialization delay modulus.

struct _acmp_discrete_mode_config

#include <fsl_acmp.h>

Configuration for discrete mode.

Public Members

bool enablePositiveChannelDiscreteMode

Positive Channel Continuous Mode Enable. By default, the continuous mode is used.

bool enableNegativeChannelDiscreteMode

Negative Channel Continuous Mode Enable. By default, the continuous mode is used.

ADC_ETC: ADC External Trigger Control

void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)

Initialize the ADC_ETC module.

Parameters:

• base – ADC_ETC peripheral base address.

• config – Pointer to “adc_etc_config_t” structure.

void ADC_ETC_Deinit(ADC_ETC_Type *base)

De-Initialize the ADC_ETC module.

Parameters:

• base – ADC_ETC peripheral base address.

void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)

Gets an available pre-defined settings for the ADC_ETC’s configuration. This function initializes the ADC_ETC’s configuration structure with available settings. The default values are:

config->enableTSCBypass = true;
config->enableTSC0Trigger = false;
config->enableTSC1Trigger = false;
config->TSC0triggerPriority = 0U;
config->TSC1triggerPriority = 0U;
config->clockPreDivider = 0U;
config->XBARtriggerMask = 0U;

Parameters:

• config – Pointer to “adc_etc_config_t” structure.

void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)

Set the external XBAR trigger configuration.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index.

• config – Pointer to “adc_etc_trigger_config_t” structure.

void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup, const adc_etc_trigger_chain_config_t *config)

Set the external XBAR trigger chain configuration. For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source’s chain1 would be configurated.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

• chainGroup – Trigger chain group index. Available number is 0~7.

• config – Pointer to “adc_etc_trigger_chain_config_t” structure.

uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)

Gets the interrupt status flags of external XBAR and TSC triggers.

Parameters:

• base – ADC_ETC peripheral base address.

• sourceIndex – trigger source index.

Returns:

Status flags mask of trigger. Refer to “_adc_etc_status_flag_mask”.

void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)

Clears the ADC_ETC’s interrupt status falgs.

Parameters:

• base – ADC_ETC peripheral base address.

• sourceIndex – trigger source index.

• mask – Status flags mask of trigger. Refer to “_adc_etc_status_flag_mask”.

static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)

Enable the DMA corresponding to each trigger source.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)

Disable the DMA corresponding to each trigger sources.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)

Get the DMA request status falgs. Only external XBAR sources support DMA request.

Parameters:

• base – ADC_ETC peripheral base address.

Returns:

Mask of external XBAR tirgger’s DMA request asserted flags. Available range is trigger0:0x01 to trigger7:0x80.

static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)

Clear the DMA request status falgs. Only external XBAR sources support DMA request.

Parameters:

• base – ADC_ETC peripheral base address.

• mask – Mask of external XBAR tirgger’s DMA request asserted flags. Available range is trigger0:0x01 to trigger7:0x80.

static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)

When enable, all logical will be reset.

Parameters:

• base – ADC_ETC peripheral base address.

• enable – Enable/Disable the software reset.

static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)

Do software trigger corresponding to each XBAR trigger sources. Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources can only work in hardware trigger mode.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

static inline void ADC_ETC_DoSoftwareTriggerBlocking(ADC_ETC_Type *base, uint32_t triggerGroup)

Do software trigger corresponding to each XBAR trigger sources.

Note

This function provides a workaround implementation for ERR052412 by using blocking way to implement SW trigger.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)

Get ADC conversion result from external XBAR sources. For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would return Trigger0 source’s chain1 conversion result.

Parameters:

• base – ADC_ETC peripheral base address.

• triggerGroup – Trigger group index. Available number is 0~7.

• chainGroup – Trigger chain group index. Available number is 0~7.

Returns:

ADC conversion result value.

enum _adc_etc_status_flag_mask

ADC_ETC customized status flags mask.

Values:

enumerator kADC_ETC_Done0StatusFlagMask

enumerator kADC_ETC_Done1StatusFlagMask

enumerator kADC_ETC_Done2StatusFlagMask

enumerator kADC_ETC_Done3StatusFlagMask

enumerator kADC_ETC_ErrorStatusFlagMask

enum _adc_etc_external_trigger_source

External triggers sources.

Values:

enumerator kADC_ETC_Trg0TriggerSource

enumerator kADC_ETC_Trg1TriggerSource

enumerator kADC_ETC_Trg2TriggerSource

enumerator kADC_ETC_Trg3TriggerSource

enumerator kADC_ETC_Trg4TriggerSource

enumerator kADC_ETC_Trg5TriggerSource

enumerator kADC_ETC_Trg6TriggerSource

enumerator kADC_ETC_Trg7TriggerSource

enumerator kADC_ETC_TSC0TriggerSource

enumerator kADC_ETC_TSC1TriggerSource

enum _adc_etc_interrupt_enable

Interrupt enable/disable mask.

Values:

enumerator kADC_ETC_Done0InterruptEnable

enumerator kADC_ETC_Done1InterruptEnable

enumerator kADC_ETC_Done2InterruptEnable

enumerator kADC_ETC_Done3InterruptEnable

enum _adc_etc_dma_mode_selection

DMA mode selection.

Values:

enumerator kADC_ETC_TrigDMAWithLatchedSignal

enumerator kADC_ETC_TrigDMAWithPulsedSignal

typedef enum _adc_etc_external_trigger_source adc_etc_external_trigger_source_t

External triggers sources.

typedef enum _adc_etc_interrupt_enable adc_etc_interrupt_enable_t

Interrupt enable/disable mask.

typedef enum _adc_etc_dma_mode_selection adc_etc_dma_mode_selection_t

DMA mode selection.

typedef struct _adc_etc_config adc_etc_config_t

ADC_ETC configuration.

typedef struct _adc_etc_trigger_chain_config adc_etc_trigger_chain_config_t

ADC_ETC trigger chain configuration.

typedef struct _adc_etc_trigger_config adc_etc_trigger_config_t

ADC_ETC trigger configuration.

FSL_ADC_ETC_DRIVER_VERSION

ADC_ETC driver version.

Version 2.3.0.

ADC_ETC_DMA_CTRL_TRGn_REQ_MASK

The mask of status flags cleared by writing 1.

struct _adc_etc_config

#include <fsl_adc_etc.h>

ADC_ETC configuration.

struct _adc_etc_trigger_chain_config

#include <fsl_adc_etc.h>

ADC_ETC trigger chain configuration.

struct _adc_etc_trigger_config

#include <fsl_adc_etc.h>

ADC_ETC trigger configuration.

Anatop_ai

enum _anatop_ai_itf

Anatop AI ITF enumeration.

Values:

enumerator kAI_Itf_Ldo

LDO ITF.

enumerator kAI_Itf_1g

1G PLL ITF.

enumerator kAI_Itf_Audio

Audio PLL ITF.

enumerator kAI_Itf_Video

Video PLL ITF.

enumerator kAI_Itf_400m

400M OSC ITF.

enumerator kAI_Itf_Temp

Temperature Sensor ITF.

enumerator kAI_Itf_Bandgap

Bandgap ITF.

enum _anatop_ai_reg

The enumeration of ANATOP AI Register.

Values:

enumerator kAI_PHY_LDO_CTRL0

PHY LDO CTRL0 Register.

enumerator kAI_PHY_LDO_CTRL0_SET

PHY LDO CTRL0 Set Register.

enumerator kAI_PHY_LDO_CTRL0_CLR

PHY LDO CTRL0 Clr Register.

enumerator kAI_PHY_LDO_CTRL0_TOG

PHY LDO CTRL0 TOG Register.

enumerator kAI_PHY_LDO_STAT0

PHY LDO STAT0 Register.

enumerator kAI_PHY_LDO_STAT0_SET

PHY LDO STAT0 Set Register.

enumerator kAI_PHY_LDO_STAT0_CLR

PHY LDO STAT0 Clr Register.

enumerator kAI_PHY_LDO_STAT0_TOG

PHY LDO STAT0 Tog Register.

enumerator kAI_BANDGAP_CTRL0

BANDGAP CTRL0 Register.

enumerator kAI_BANDGAP_STAT0

BANDGAP STAT0 Register.

enumerator kAI_RCOSC400M_CTRL0

RC OSC 400M CTRL0 Register.

enumerator kAI_RCOSC400M_CTRL0_SET

RC OSC 400M CTRL0 SET Register.

enumerator kAI_RCOSC400M_CTRL0_CLR

RC OSC 400M CTRL0 CLR Register.

enumerator kAI_RCOSC400M_CTRL0_TOG

RC OSC 400M CTRL0 TOG Register.

enumerator kAI_RCOSC400M_CTRL1

RC OSC 400M CTRL1 Register.

enumerator kAI_RCOSC400M_CTRL1_SET

RC OSC 400M CTRL1 SET Register.

enumerator kAI_RCOSC400M_CTRL1_CLR

RC OSC 400M CTRL1 CLR Register.

enumerator kAI_RCOSC400M_CTRL1_TOG

RC OSC 400M CTRL1 TOG Register.

enumerator kAI_RCOSC400M_CTRL2

RC OSC 400M CTRL2 Register.

enumerator kAI_RCOSC400M_CTRL2_SET

RC OSC 400M CTRL2 SET Register.

enumerator kAI_RCOSC400M_CTRL2_CLR

RC OSC 400M CTRL2 CLR Register.

enumerator kAI_RCOSC400M_CTRL2_TOG

RC OSC 400M CTRL2 TOG Register.

enumerator kAI_RCOSC400M_CTRL3

RC OSC 400M CTRL3 Register.

enumerator kAI_RCOSC400M_CTRL3_SET

RC OSC 400M CTRL3 SET Register.

enumerator kAI_RCOSC400M_CTRL3_CLR

RC OSC 400M CTRL3 CLR Register.

enumerator kAI_RCOSC400M_CTRL3_TOG

RC OSC 400M CTRL3 TOG Register.

enumerator kAI_RCOSC400M_STAT0

RC OSC 400M STAT0 Register.

enumerator kAI_RCOSC400M_STAT0_SET

RC OSC 400M STAT0 SET Register.

enumerator kAI_RCOSC400M_STAT0_CLR

RC OSC 400M STAT0 CLR Register.

enumerator kAI_RCOSC400M_STAT0_TOG

RC OSC 400M STAT0 TOG Register.

enumerator kAI_RCOSC400M_STAT1

RC OSC 400M STAT1 Register.

enumerator kAI_RCOSC400M_STAT1_SET

RC OSC 400M STAT1 SET Register.

enumerator kAI_RCOSC400M_STAT1_CLR

RC OSC 400M STAT1 CLR Register.

enumerator kAI_RCOSC400M_STAT1_TOG

RC OSC 400M STAT1 TOG Register.

enumerator kAI_RCOSC400M_STAT2

RC OSC 400M STAT2 Register.

enumerator kAI_RCOSC400M_STAT2_SET

RC OSC 400M STAT2 SET Register.

enumerator kAI_RCOSC400M_STAT2_CLR

RC OSC 400M STAT2 CLR Register.

enumerator kAI_RCOSC400M_STAT2_TOG

RC OSC 400M STAT2 TOG Register.

enumerator kAI_PLL1G_CTRL0

1G PLL CTRL0 Register.

enumerator kAI_PLL1G_CTRL0_SET

1G PLL CTRL0 SET Register.

enumerator kAI_PLL1G_CTRL0_CLR

1G PLL CTRL0 CLR Register.

enumerator kAI_PLL1G_CTRL1

1G PLL CTRL1 Register.

enumerator kAI_PLL1G_CTRL1_SET

1G PLL CTRL1 SET Register.

enumerator kAI_PLL1G_CTRL1_CLR

1G PLL CTRL1 CLR Register.

enumerator kAI_PLL1G_CTRL2

1G PLL CTRL2 Register.

enumerator kAI_PLL1G_CTRL2_SET

1G PLL CTRL2 SET Register.

enumerator kAI_PLL1G_CTRL2_CLR

1G PLL CTRL2 CLR Register.

enumerator kAI_PLL1G_CTRL3

1G PLL CTRL3 Register.

enumerator kAI_PLL1G_CTRL3_SET

1G PLL CTRL3 SET Register.

enumerator kAI_PLL1G_CTRL3_CLR

1G PLL CTRL3 CLR Register.

enumerator kAI_PLLAUDIO_CTRL0

AUDIO PLL CTRL0 Register.

enumerator kAI_PLLAUDIO_CTRL0_SET

AUDIO PLL CTRL0 SET Register.

enumerator kAI_PLLAUDIO_CTRL0_CLR

AUDIO PLL CTRL0 CLR Register.

enumerator kAI_PLLAUDIO_CTRL1

AUDIO PLL CTRL1 Register.

enumerator kAI_PLLAUDIO_CTRL1_SET

AUDIO PLL CTRL1 SET Register.

enumerator kAI_PLLAUDIO_CTRL1_CLR

AUDIO PLL CTRL1 CLR Register.

enumerator kAI_PLLAUDIO_CTRL2

AUDIO PLL CTRL2 Register.

enumerator kAI_PLLAUDIO_CTRL2_SET

AUDIO PLL CTRL2 SET Register.

enumerator kAI_PLLAUDIO_CTRL2_CLR

AUDIO PLL CTRL2 CLR Register.

enumerator kAI_PLLAUDIO_CTRL3

AUDIO PLL CTRL3 Register.

enumerator kAI_PLLAUDIO_CTRL3_SET

AUDIO PLL CTRL3 SET Register.

enumerator kAI_PLLAUDIO_CTRL3_CLR

AUDIO PLL CTRL3 CLR Register.

enumerator kAI_PLLVIDEO_CTRL0

VIDEO PLL CTRL0 Register.

enumerator kAI_PLLVIDEO_CTRL0_SET

VIDEO PLL CTRL0 SET Register.

enumerator kAI_PLLVIDEO_CTRL0_CLR

VIDEO PLL CTRL0 CLR Register.

enumerator kAI_PLLVIDEO_CTRL1

VIDEO PLL CTRL1 Register.

enumerator kAI_PLLVIDEO_CTRL1_SET

VIDEO PLL CTRL1 SET Register.

enumerator kAI_PLLVIDEO_CTRL1_CLR

VIDEO PLL CTRL1 CLR Register.

enumerator kAI_PLLVIDEO_CTRL2

VIDEO PLL CTRL2 Register.

enumerator kAI_PLLVIDEO_CTRL2_SET

VIDEO PLL CTRL2 SET Register.

enumerator kAI_PLLVIDEO_CTRL2_CLR

VIDEO PLL CTRL2 CLR Register.

enumerator kAI_PLLVIDEO_CTRL3

VIDEO PLL CTRL3 Register.

enumerator kAI_PLLVIDEO_CTRL3_SET

VIDEO PLL CTRL3 SET Register.

enumerator kAI_PLLVIDEO_CTRL3_CLR

VIDEO PLL CTRL3 CLR Register.

typedef enum _anatop_ai_itf anatop_ai_itf_t

Anatop AI ITF enumeration.

typedef enum _anatop_ai_reg anatop_ai_reg_t

The enumeration of ANATOP AI Register.

FSL_ANATOP_AI_DRIVER_VERSION

Anatop AI driver version 1.0.0.

AI_PHY_LDO_CTRL0_LINREG_EN(x)

AI_PHY_LDO_CTRL0_LINREG_EN_MASK

AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT

AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x)

LINREG_EN - LinReg master enable LinReg master enable. Setting this bit will enable the regular

AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK

AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT

AI_PHY_LDO_CTRL0_LIMIT_EN(x)

LINREG_PWRUPLOAD_DIS - LinReg power-up load disable 0b0..Internal pull-down enabled 0b1..Internal pull-down disabled

AI_PHY_LDO_CTRL0_LIMIT_EN_MASK

AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT

AI_PHY_LDO_CTRL0_OUTPUT_TRG(x)

LINREG_LIMIT_EN - LinReg current limit enable LinReg current-limit enable. Setting this bit will enable the current-limiter in the regulator

AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK

AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT

AI_PHY_LDO_CTRL0_PHY_ISO_B(x)

LINREG_OUTPUT_TRG - LinReg output voltage target setting 0b00000..Set output voltage to x.xV 0b10000..Set output voltage to 1.0V 0b11111..Set output voltage to x.xV

AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK

AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT

AI_BANDGAP_CTRL0_REFTOP_PWD(x)

AI_BANDGAP_CTRL0_REFTOP_PWD_MASK

AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT

AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)

REFTOP_PWD - This bit fully powers down the bandgap module. Setting this bit high will disable reference output currents and voltages from the bandgap and will affect functionality and validity of the voltage detectors.

AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK

AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT

AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x)

REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap. Setting this bit high will affect functionality and validity of the voltage detectors.

AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK

AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT

AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x)

REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap without affecting any additional functionality.

AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK

AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT

AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)

REFTOP_LOWPOWER - This bit enables the low-power operation of the bandgap by cutting the bias currents in half to the main amplifiers. This will save power but could affect the accuracy of the output voltages and currents.

AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK

AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT

AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x)

REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap. The self-bias circuit is used by the bandgap during startup. This bit should be set high after the bandgap has stabilized and is necessary for best noise performance of modules using the outputs of the bandgap. It is expected that this control bit be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed.

AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK

AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT

AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x)

REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed 000 : nominal 001 : +10mV 010 : +20mV 011 : +30mV 100 : -10mV 101 : -20mV 110 : -30mV 111 : -40mV

AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK

AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT

AI_RCOSC400M_CTRL0_REF_CLK_DIV(x)

AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK

AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT

AI_PLL1G_CTRL0_HOLD_RING_OFF(x)

AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK

AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT

AI_PLL1G_CTRL0_POWER_UP(x)

AI_PLL1G_CTRL0_POWER_UP_MASK

AI_PLL1G_CTRL0_POWER_UP_SHIFT

AI_PLL1G_CTRL0_ENABLE(x)

AI_PLL1G_CTRL0_ENABLE_MASK

AI_PLL1G_CTRL0_ENABLE_SHIFT

AI_PLL1G_CTRL0_BYPASS(x)

AI_PLL1G_CTRL0_BYPASS_MASK

AI_PLL1G_CTRL0_BYPASS_SHIFT

AI_PLL1G_CTRL0_PLL_REG_EN(x)

AI_PLL1G_CTRL0_PLL_REG_EN_MASK

AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT

AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x)

AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK

AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT

AI_PLLAUDIO_CTRL0_POWER_UP(x)

AI_PLLAUDIO_CTRL0_POWER_UP_MASK

AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT

AI_PLLAUDIO_CTRL0_ENABLE(x)

AI_PLLAUDIO_CTRL0_ENABLE_MASK

AI_PLLAUDIO_CTRL0_ENABLE_SHIFT

AI_PLLAUDIO_CTRL0_BYPASS(x)

AI_PLLAUDIO_CTRL0_BYPASS_MASK

AI_PLLAUDIO_CTRL0_BYPASS_SHIFT

AI_PLLAUDIO_CTRL0_PLL_REG_EN(x)

AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK

AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT

AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x)

AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK

AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT

AI_PLLVIDEO_CTRL0_POWER_UP(x)

AI_PLLVIDEO_CTRL0_POWER_UP_MASK

AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT

AI_PLLVIDEO_CTRL0_ENABLE(x)

AI_PLLVIDEO_CTRL0_ENABLE_MASK

AI_PLLVIDEO_CTRL0_ENABLE_SHIFT

AI_PLLVIDEO_CTRL0_BYPASS(x)

AI_PLLVIDEO_CTRL0_BYPASS_MASK

AI_PLLVIDEO_CTRL0_BYPASS_SHIFT

AI_PLLVIDEO_CTRL0_PLL_REG_EN(x)

AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK

AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT

AI_PHY_LDO_STAT0_LINREG_STAT(x)

AI_PHY_LDO_STAT0_LINREG_STAT_MASK

AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT

AI_BANDGAP_STAT0_REFTOP_VBGUP(x)

AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK

AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT

AI_RCOSC400M_STAT0_CLK1M_ERR(x)

AI_RCOSC400M_STAT0_CLK1M_ERR_MASK

AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT

AI_RCOSC400M_CTRL1_HYST_MINUS(x)

AI_RCOSC400M_CTRL1_HYST_MINUS_MASK

AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT

AI_RCOSC400M_CTRL1_HYST_PLUS(x)

AI_RCOSC400M_CTRL1_HYST_PLUS_MASK

AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT

AI_RCOSC400M_CTRL1_TARGET_COUNT(x)

AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK

AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT

AI_RCOSC400M_CTRL2_TUNE_BYP(x)

AI_RCOSC400M_CTRL2_TUNE_BYP_MASK

AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT

AI_RCOSC400M_CTRL2_TUNE_EN(x)

AI_RCOSC400M_CTRL2_TUNE_EN_MASK

AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT

AI_RCOSC400M_CTRL2_TUNE_START(x)

AI_RCOSC400M_CTRL2_TUNE_START_MASK

AI_RCOSC400M_CTRL2_TUNE_START_SHIFT

AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x)

AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK

AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT

AI_RCOSC400M_CTRL3_CLR_ERR(x)

AI_RCOSC400M_CTRL3_CLR_ERR_MASK

AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT

AI_RCOSC400M_CTRL3_EN_1M_CLK(x)

AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK

AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT

AI_RCOSC400M_CTRL3_MUX_1M_CLK(x)

AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK

AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT

AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x)

AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK

AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT

AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x)

AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK

AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT

AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x)

AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK

AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT

AOI: Crossbar AND/OR/INVERT Driver

void AOI_Init(AOI_Type *base)

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

• base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

• base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Index of the event which will be set of type aoi_event_t.

• config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Event which will be configured of type aoi_event_t.

• eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION

Version 2.0.2.

enum _aoi_input_config

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero

Forces the input to logical zero.

enumerator kAOI_InputSignal

Passes the input signal.

enumerator kAOI_InvInputSignal

Inverts the input signal.

enumerator kAOI_LogicOne

Forces the input to logical one.

enum _aoi_event

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0

Event 0 index

enumerator kAOI_Event1

Event 1 index

enumerator kAOI_Event2

Event 2 index

enumerator kAOI_Event3

Event 3 index

typedef enum _aoi_input_config aoi_input_config_t

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI

AOI peripheral address

struct _aoi_event_config

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC

Product term 0 input A

aoi_input_config_t PT0BC

Product term 0 input B

aoi_input_config_t PT0CC

Product term 0 input C

aoi_input_config_t PT0DC

Product term 0 input D

aoi_input_config_t PT1AC

Product term 1 input A

aoi_input_config_t PT1BC

Product term 1 input B

aoi_input_config_t PT1CC

Product term 1 input C

aoi_input_config_t PT1DC

Product term 1 input D

aoi_input_config_t PT2AC

Product term 2 input A

aoi_input_config_t PT2BC

Product term 2 input B

aoi_input_config_t PT2CC

Product term 2 input C

aoi_input_config_t PT2DC

Product term 2 input D

aoi_input_config_t PT3AC

Product term 3 input A

aoi_input_config_t PT3BC

Product term 3 input B

aoi_input_config_t PT3CC

Product term 3 input C

aoi_input_config_t PT3DC

Product term 3 input D

ASRC: Asynchronous sample rate converter

ASRC Driver

uint32_t ASRC_GetInstance(ASRC_Type *base)

Get instance number of the ASRC peripheral.

Parameters:

• base – ASRC base pointer.

void ASRC_Init(ASRC_Type *base, uint32_t asrcPeripheralClock_Hz)

brief Initializes the asrc peripheral.

This API gates the asrc clock. The asrc module can’t operate unless ASRC_Init is called to enable the clock.

param base asrc base pointer. param asrcPeripheralClock_Hz peripheral clock of ASRC.

void ASRC_Deinit(ASRC_Type *base)

De-initializes the ASRC peripheral.

This API gates the ASRC clock and disable ASRC module. The ASRC module can’t operate unless ASRC_Init

Parameters:

• base – ASRC base pointer.

void ASRC_SoftwareReset(ASRC_Type *base)

Do software reset .

This software reset bit is self-clear bit, it will generate a software reset signal inside ASRC. After 9 cycles of the ASRC processing clock, this reset process will stop and this bit will cleared automatically.

Parameters:

• base – ASRC base pointer

status_t ASRC_SetChannelPairConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure channel pair.

Parameters:

• base – ASRC base pointer.

• channelPair – index of channel pair, reference _asrc_channel_pair.

• config – ASRC channel pair configuration pointer.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

uint32_t ASRC_GetOutSamplesSize(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)

Get output sample buffer size.

Note

This API is depends on the ASRC output configuration, should be called after the ASRC_SetChannelPairConfig.

Parameters:

• base – asrc base pointer.

• channelPair – ASRC channel pair number.

• inSampleRate – input sample rate.

• outSampleRate – output sample rate.

• inSamplesize – input sampleS size.

Return values:

output – buffer size in byte.

uint32_t ASRC_MapSamplesWidth(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *inWidth, uint32_t *outWidth)

Map register sample width to real sample width.

Note

This API is depends on the ASRC configuration, should be called after the ASRC_SetChannelPairConfig.

Parameters:

• base – asrc base pointer.

• channelPair – asrc channel pair index.

• inWidth – ASRC channel pair number.

• outWidth – input sample rate.

Return values:

input – sample mask value.

uint32_t ASRC_GetRemainFifoSamples(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *buffer, uint32_t outSampleWidth, uint32_t remainSamples)

Get left samples in fifo.

Parameters:

• base – asrc base pointer.

• channelPair – ASRC channel pair number.

• buffer – input sample numbers.

• outSampleWidth – output sample width.

• remainSamples – output sample rate.

Return values:

remain – samples number.

static inline void ASRC_ModuleEnable(ASRC_Type *base, bool enable)

ASRC module enable.

Parameters:

• base – ASRC base pointer.

• enable – true is enable, false is disable

static inline void ASRC_ChannelPairEnable(ASRC_Type *base, asrc_channel_pair_t channelPair, bool enable)

ASRC enable channel pair.

Parameters:

• base – ASRC base pointer.

• channelPair – channel pair mask value, reference _asrc_channel_pair_mask.

• enable – true is enable, false is disable.

static inline void ASRC_EnableInterrupt(ASRC_Type *base, uint32_t mask)

ASRC interrupt enable This function enable the ASRC interrupt with the provided mask.

Parameters:

• base – ASRC peripheral base address.

• mask – The interrupts to enable. Logical OR of _asrc_interrupt_mask.

static inline void ASRC_DisableInterrupt(ASRC_Type *base, uint32_t mask)

ASRC interrupt disable This function disable the ASRC interrupt with the provided mask.

Parameters:

• base – ASRC peripheral base address.

• mask – The interrupts to disable. Logical OR of _asrc_interrupt_mask.

static inline uint32_t ASRC_GetStatus(ASRC_Type *base)

Gets the ASRC status flag state.

Parameters:

• base – ASRC base pointer

Returns:

ASRC Tx status flag value. Use the Status Mask to get the status value needed.

static inline bool ASRC_GetChannelPairInitialStatus(ASRC_Type *base, asrc_channel_pair_t channel)

Gets the ASRC channel pair initialization state.

Parameters:

• base – ASRC base pointer

• channel – ASRC channel pair.

Returns:

ASRC Tx status flag value. Use the Status Mask to get the status value needed.

static inline uint32_t ASRC_GetChannelPairFifoStatus(ASRC_Type *base, asrc_channel_pair_t channelPair)

Gets the ASRC channel A fifo a status flag state.

Parameters:

• base – ASRC base pointer

• channelPair – ASRC channel pair.

Returns:

ASRC channel pair a fifo status flag value. Use the Status Mask to get the status value needed.

static inline void ASRC_ChannelPairWriteData(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t data)

Writes data into ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

• data – Data needs to be written.

static inline uint32_t ASRC_ChannelPairReadData(ASRC_Type *base, asrc_channel_pair_t channelPair)

Read data from ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

Return values:

value – read from fifo.

static inline uint32_t ASRC_GetInputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)

Get input data fifo address. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

static inline uint32_t ASRC_GetOutputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)

Get output data fifo address. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

status_t ASRC_SetIdealRatioConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure ideal ratio. The ideal ratio should be used when input clock source is not avalible.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

status_t ASRC_TransferSetChannelPairConfig(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure channel pair.

Parameters:

• base – ASRC base pointer.

• handle – ASRC transactional handle pointer.

• config – ASRC channel pair configuration pointer.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

void ASRC_TransferCreateHandle(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_t channelPair, asrc_transfer_callback_t inCallback, asrc_transfer_callback_t outCallback, void *userData)

Initializes the ASRC handle.

This function initializes the handle for the ASRC transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – ASRC base pointer

• handle – ASRC handle pointer.

• channelPair – ASRC channel pair.

• inCallback – Pointer to the user callback function.

• outCallback – Pointer to the user callback function.

• userData – User parameter passed to the callback function

status_t ASRC_TransferNonBlocking(ASRC_Type *base, asrc_handle_t *handle, asrc_transfer_t *xfer)

Performs an interrupt non-blocking convert on asrc.

Note

This API returns immediately after the transfer initiates, application should check the wait and check the callback status.

Parameters:

• base – asrc base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

• xfer – Pointer to the ASRC_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_ASRCBusy – Previous receive still not finished.

status_t ASRC_TransferBlocking(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_transfer_t *xfer)

Performs an blocking convert on asrc.

Note

This API returns immediately after the convert finished.

Parameters:

• base – asrc base pointer.

• channelPair – channel pair index.

• xfer – Pointer to the ASRC_transfer_t structure.

Return values:

kStatus_Success – Successfully started the data receive.

status_t ASRC_TransferGetConvertedCount(ASRC_Type *base, asrc_handle_t *handle, size_t *count)

Get converted byte count.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

• count – Bytes count sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_ASRCIdle – There is not a non-blocking transaction currently in progress.

void ASRC_TransferAbortConvert(ASRC_Type *base, asrc_handle_t *handle)

Aborts the current convert.

Note

This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

void ASRC_TransferTerminateConvert(ASRC_Type *base, asrc_handle_t *handle)

Terminate all ASRC convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortConvert.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferHandleIRQ(ASRC_Type *base, asrc_handle_t *handle)

ASRC convert interrupt handler.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure.

FSL_ASRC_DRIVER_VERSION

Version 2.1.3

ASRC return status .

Values:

enumerator kStatus_ASRCIdle

ASRC is idle.

enumerator kStatus_ASRCInIdle

ASRC in is idle.

enumerator kStatus_ASRCOutIdle

ASRC out is idle.

enumerator kStatus_ASRCBusy

ASRC is busy.

enumerator kStatus_ASRCInvalidArgument

ASRC invalid argument.

enumerator kStatus_ASRCClockConfigureFailed

ASRC clock configure failed

enumerator kStatus_ASRCChannelPairConfigureFailed

ASRC clock configure failed

enumerator kStatus_ASRCConvertError

ASRC clock configure failed

enumerator kStatus_ASRCNotSupport

ASRC not support

enumerator kStatus_ASRCQueueFull

ASRC queue is full

enumerator kStatus_ASRCOutQueueIdle

ASRC out queue is idle

enumerator kStatus_ASRCInQueueIdle

ASRC in queue is idle

enum _asrc_channel_pair

ASRC channel pair mask.

Values:

enumerator kASRC_ChannelPairA

channel pair A value

enumerator kASRC_ChannelPairB

channel pair B value

enumerator kASRC_ChannelPairC

channel pair C value

ASRC support sample rate .

Values:

enumerator kASRC_SampleRate_8000HZ

asrc sample rate 8KHZ

enumerator kASRC_SampleRate_11025HZ

asrc sample rate 11.025KHZ

enumerator kASRC_SampleRate_12000HZ

asrc sample rate 12KHZ

enumerator kASRC_SampleRate_16000HZ

asrc sample rate 16KHZ

enumerator kASRC_SampleRate_22050HZ

asrc sample rate 22.05KHZ

enumerator kASRC_SampleRate_24000HZ

asrc sample rate 24KHZ

enumerator kASRC_SampleRate_30000HZ

asrc sample rate 30KHZ

enumerator kASRC_SampleRate_32000HZ

asrc sample rate 32KHZ

enumerator kASRC_SampleRate_44100HZ

asrc sample rate 44.1KHZ

enumerator kASRC_SampleRate_48000HZ

asrc sample rate 48KHZ

enumerator kASRC_SampleRate_64000HZ

asrc sample rate 64KHZ

enumerator kASRC_SampleRate_88200HZ

asrc sample rate 88.2KHZ

enumerator kASRC_SampleRate_96000HZ

asrc sample rate 96KHZ

enumerator kASRC_SampleRate_128000HZ

asrc sample rate 128KHZ

enumerator kASRC_SampleRate_176400HZ

asrc sample rate 176.4KHZ

enumerator kASRC_SampleRate_192000HZ

asrc sample rate 192KHZ

The ASRC interrupt enable flag .

Values:

enumerator kASRC_FPInWaitStateInterruptEnable

FP in wait state mask

enumerator kASRC_OverLoadInterruptMask

overload interrupt mask

enumerator kASRC_DataOutputCInterruptMask

data output c interrupt mask

enumerator kASRC_DataOutputBInterruptMask

data output b interrupt mask

enumerator kASRC_DataOutputAInterruptMask

data output a interrupt mask

enumerator kASRC_DataInputCInterruptMask

data input c interrupt mask

enumerator kASRC_DataInputBInterruptMask

data input b interrupt mask

enumerator kASRC_DataInputAInterruptMask

data input a interrupt mask

The ASRC interrupt status .

Values:

enumerator kASRC_StatusDSLCounterReady

DSL counter

enumerator kASRC_StatusTaskQueueOverLoad

task queue overload

enumerator kASRC_StatusPairCOutputOverLoad

pair c output overload

enumerator kASRC_StatusPairBOutputOverLoad

pair b output overload

enumerator kASRC_StatusPairAOutputOverLoad

pair a output overload

enumerator kASRC_StatusPairCInputOverLoad

pair c input overload

enumerator kASRC_StatusPairBInputOverLoad

pair b input overload

enumerator kASRC_StatusPairAInputOverLoad

pair a input overload

enumerator kASRC_StatusPairCOutputOverflow

pair c output overflow

enumerator kASRC_StatusPairBOutputOverflow

pair b output overflow

enumerator kASRC_StatusPairAOutputOverflow

pair a output overflow

enumerator kASRC_StatusPairCInputUnderflow

pair c input underflow

enumerator kASRC_StatusPairBInputUnderflow

pair b input under flow

enumerator kASRC_StatusPairAInputUnderflow

pair a input underflow

enumerator kASRC_StatusFPInWaitState

FP in wait state

enumerator kASRC_StatusOverloadError

overload error

enumerator kASRC_StatusInputError

input error status

enumerator kASRC_StatusOutputError

output error status

enumerator kASRC_StatusPairCOutputReady

pair c output ready

enumerator kASRC_StatusPairBOutputReady

pair b output ready

enumerator kASRC_StatusPairAOutputReady

pair a output ready

enumerator kASRC_StatusPairCInputReady

pair c input ready

enumerator kASRC_StatusPairBInputReady

pair b input ready

enumerator kASRC_StatusPairAInputReady

pair a input ready

enumerator kASRC_StatusPairAInterrupt

pair A interrupt

enumerator kASRC_StatusPairBInterrupt

pair B interrupt

enumerator kASRC_StatusPairCInterrupt

pair C interrupt

ASRC channel pair status .

Values:

enumerator kASRC_OutputFifoNearFull

channel pair output fifo near full

enumerator kASRC_InputFifoNearEmpty

channel pair input fifo near empty

enum _asrc_ratio

ASRC ideal ratio.

Values:

enumerator kASRC_RatioNotUsed

ideal ratio not used

enumerator kASRC_RatioUseInternalMeasured

ideal ratio use internal measure ratio, can be used for real time streaming audio

enumerator kASRC_RatioUseIdealRatio

ideal ratio use manual configure ratio, can be used for the non-real time streaming audio

enum _asrc_audio_channel

Number of channels in audio data.

Values:

enumerator kASRC_ChannelsNumber1

channel number is 1

enumerator kASRC_ChannelsNumber2

channel number is 2

enumerator kASRC_ChannelsNumber3

channel number is 3

enumerator kASRC_ChannelsNumber4

channel number is 4

enumerator kASRC_ChannelsNumber5

channel number is 5

enumerator kASRC_ChannelsNumber6

channel number is 6

enumerator kASRC_ChannelsNumber7

channel number is 7

enumerator kASRC_ChannelsNumber8

channel number is 8

enumerator kASRC_ChannelsNumber9

channel number is 9

enumerator kASRC_ChannelsNumber10

channel number is 10

enum _asrc_data_width

data width

Values:

enumerator kASRC_DataWidth24Bit

data width 24bit

enumerator kASRC_DataWidth16Bit

data width 16bit

enumerator kASRC_DataWidth8Bit

data width 8bit

enum _asrc_data_align

data alignment

Values:

enumerator kASRC_DataAlignMSB

data alignment MSB

enumerator kASRC_DataAlignLSB

data alignment LSB

enum _asrc_sign_extension

sign extension

Values:

enumerator kASRC_NoSignExtension

no sign extension

enumerator kASRC_SignExtension

sign extension

typedef enum _asrc_channel_pair asrc_channel_pair_t

ASRC channel pair mask.

typedef enum _asrc_ratio asrc_ratio_t

ASRC ideal ratio.

typedef enum _asrc_audio_channel asrc_audio_channel_t

Number of channels in audio data.

typedef enum _asrc_data_width asrc_data_width_t

data width

typedef enum _asrc_data_align asrc_data_align_t

data alignment

typedef enum _asrc_sign_extension asrc_sign_extension_t

sign extension

typedef struct _asrc_channel_pair_config asrc_channel_pair_config_t

asrc channel pair configuation

typedef struct _asrc_transfer asrc_transfer_t

SAI transfer structure.

typedef struct _asrc_handle asrc_handle_t

asrc handler

typedef void (*asrc_transfer_callback_t)(ASRC_Type *base, asrc_handle_t *handle, status_t status, void *userData)

ASRC transfer callback prototype.

typedef struct _asrc_in_handle asrc_in_handle_t

asrc in handler

typedef struct _asrc_out_handle asrc_out_handle_t

output handler

ASRC_XFER_QUEUE_SIZE

ASRC transfer queue size, user can refine it according to use case.

FSL_ASRC_CHANNEL_PAIR_COUNT

ASRC channel pair count.

FSL_ASRC_CHANNEL_PAIR_FIFO_DEPTH

ASRC FIFO depth.

ASRC_ASRCTR_AT_MASK(index)

ASRC register access macro.

ASRC_ASRCTR_RATIO_MASK(index)

ASRC_ASRCTR_RATIO(ratio, index)

ASRC_ASRIER_INPUT_INTERRUPT_MASK(index)

ASRC_ASRIER_OUTPUTPUT_INTERRUPT_MASK(index)

ASRC_ASRCNCR_CHANNEL_COUNTER_MASK(index)

ASRC_ASRCNCR_CHANNEL_COUNTER(counter, index)

ASRC_ASRCFG_PRE_MODE_MASK(index)

ASRC_ASRCFG_PRE_MODE(mode, index)

ASRC_ASRCFG_POST_MODE_MASK(index)

ASRC_ASRCFG_POST_MODE(mode, index)

ASRC_ASRCFG_INIT_DONE_MASK(index)

ASRC_ASRCSR_INPUT_CLOCK_SOURCE_MASK(index)

ASRC_ASRCSR_INPUT_CLOCK_SOURCE(source, index)

ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE_MASK(index)

ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE(source, index)

ASRC_ASRCDR_INPUT_PRESCALER_MASK(index)

ASRC_ASRCDR_INPUT_PRESCALER(prescaler, index)

ASRC_ASRCDR_INPUT_DIVIDER_MASK(index)

ASRC_ASRCDR_INPUT_DIVIDER(divider, index)

ASRC_ASRCDR_OUTPUT_PRESCALER_MASK(index)

ASRC_ASRCDR_OUTPUT_PRESCALER(prescaler, index)

ASRC_ASRCDR_OUTPUT_DIVIDER_MASK(index)

ASRC_ASRCDR_OUTPUT_DIVIDER(divider, index)

ASCR_ASRCDR_OUTPUT_CLOCK_DIVIDER_PRESCALER(value, index)

ASCR_ASRCDR_INPUT_CLOCK_DIVIDER_PRESCALER(value, index)

ASRC_IDEAL_RATIO_HIGH(base, index)

ASRC_IDEAL_RATIO_LOW(base, index)

ASRC_ASRMCR(base, index)

ASRC_ASRMCR1(base, index)

ASRC_ASRDI(base, index)

ASRC_ASRDO(base, index)

ASRC_ASRDI_ADDR(base, index)

ASRC_ASRDO_ADDR(base, index)

ASRC_ASRFST_ADDR(base, index)

ASRC_GET_CHANNEL_COUNTER(base, index)

struct _asrc_channel_pair_config

#include <fsl_asrc.h>

asrc channel pair configuation

Public Members

asrc_audio_channel_t audioDataChannels

audio data channel numbers

asrc_clock_source_t inClockSource

input clock source, reference the clock source definition in SOC header file

uint32_t inSourceClock_Hz

input source clock frequency

asrc_clock_source_t outClockSource

output clock source, reference the clock source definition in SOC header file

uint32_t outSourceClock_Hz

output source clock frequency

asrc_ratio_t sampleRateRatio

sample rate ratio type

asrc_data_width_t inDataWidth

input data width

asrc_data_align_t inDataAlign

input data alignment

asrc_data_width_t outDataWidth

output data width

asrc_data_align_t outDataAlign

output data alignment

asrc_sign_extension_t outSignExtension

output extension

uint8_t outFifoThreshold

output fifo threshold

uint8_t inFifoThreshold

input fifo threshold

bool bufStallWhenFifoEmptyFull

stall Pair A conversion in case of Buffer near empty full condition

struct _asrc_transfer

#include <fsl_asrc.h>

SAI transfer structure.

Public Members

void *inData

Data address to convert.

size_t inDataSize

input data size.

void *outData

Data address to store converted data

size_t outDataSize

output data size.

struct _asrc_in_handle

#include <fsl_asrc.h>

asrc in handler

Public Members

asrc_transfer_callback_t callback

Callback function called at convert complete

uint32_t sampleWidth

data width

uint32_t sampleMask

data mask

uint32_t fifoThreshold

fifo threshold

uint8_t *asrcQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSamples[(4U)]

Data bytes need to convert

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

struct _asrc_out_handle

#include <fsl_asrc.h>

output handler

Public Members

asrc_transfer_callback_t callback

Callback function called at convert complete

uint32_t sampleWidth

data width

uint32_t fifoThreshold

fifo threshold

uint8_t *asrcQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSamples[(4U)]

Data bytes need to convert

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

struct _asrc_handle

#include <fsl_asrc.h>

ASRC handle structure.

Public Members

ASRC_Type *base

base address

uint32_t state

Transfer status

void *userData

Callback parameter passed to callback function

asrc_audio_channel_t audioDataChannels

audio channel number

asrc_channel_pair_t channelPair

channel pair mask

asrc_in_handle_t in

asrc input handler

asrc_out_handle_t out

asrc output handler

ASRC EDMA Driver

void ASRC_TransferInCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *inDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)

Initializes the ASRC IN eDMA handle.

This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair

• handle – ASRC eDMA handle pointer.

• callback – Pointer to user callback function.

• inDmaHandle – DMA handler for ASRC in.

• periphConfig – peripheral configuration.

• userData – User parameter passed to the callback function.

void ASRC_TransferOutCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *outDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)

Initializes the ASRC OUT eDMA handle.

This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair

• handle – ASRC eDMA handle pointer.

• callback – Pointer to user callback function.

• outDmaHandle – DMA handler for ASRC out.

• periphConfig – peripheral configuration.

• userData – User parameter passed to the callback function.

status_t ASRC_TransferSetChannelPairConfigEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_config_t *asrcConfig, uint32_t inSampleRate, uint32_t outSampleRate)

Configures the ASRC P2P channel pair.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

• asrcConfig – asrc configurations.

• inSampleRate – ASRC input sample rate.

• outSampleRate – ASRC output sample rate.

uint32_t ASRC_GetOutSamplesSizeEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)

Get output sample buffer size can be transferred by edma.

Note

This API is depends on the ASRC output configuration, should be called after the ASRC_TransferSetChannelPairConfigEDMA.

Parameters:

• base – asrc base pointer.

• handle – ASRC channel pair edma handle.

• inSampleRate – input sample rate.

• outSampleRate – output sample rate.

• inSamplesize – input sampleS size.

Return values:

output – buffer size in byte.

status_t ASRC_TransferEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_transfer_t *xfer)

Performs a non-blocking ASRC m2m convert using EDMA.

Note

This interface returns immediately after the transfer initiates.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure.

Return values:

• kStatus_Success – Start a ASRC eDMA send successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_ASRCQueueFull – ASRC EDMA driver queue is full.

void ASRC_TransferInAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Aborts a ASRC IN transfer using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferOutAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Aborts a ASRC OUT transfer using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferInTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Terminate In ASRC Convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferOutTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Terminate Out ASRC Convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

FSL_ASRC_EDMA_DRIVER_VERSION

Version 2.2.0

typedef struct _asrc_edma_handle asrc_edma_handle_t

typedef void (*asrc_edma_callback_t)(ASRC_Type *base, asrc_edma_handle_t *handle, status_t status, void *userData)

ASRC eDMA transfer callback function for finish and error.

typedef void (*asrc_start_peripheral_t)(bool start)

ASRC trigger peripheral function pointer.

typedef struct _asrc_p2p_edma_config asrc_p2p_edma_config_t

destination peripheral configuration

typedef struct _asrc_in_edma_handle asrc_in_edma_handle_t

@ brief asrc in edma handler

typedef struct _asrc_out_edma_handle asrc_out_edma_handle_t

@ brief asrc out edma handler

ASRC_XFER_IN_QUEUE_SIZE

ASRC IN edma QUEUE size.

<

ASRC_XFER_OUT_QUEUE_SIZE

struct _asrc_p2p_edma_config

#include <fsl_asrc_edma.h>

destination peripheral configuration

Public Members

asrc_start_peripheral_t startPeripheral

trigger peripheral start

struct _asrc_in_edma_handle

#include <fsl_asrc_edma.h>

@ brief asrc in edma handler

Public Members

edma_handle_t *inDmaHandle

DMA handler for ASRC in

uint8_t tcd[(4U + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA send.

uint32_t sampleWidth

input data width

uint32_t fifoThreshold

ASRC input fifo threshold

uint32_t *asrcQueue[4U]

Transfer queue storing queued transfer.

size_t transferSize[4U]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint32_t state

Internal state for ASRC eDMA transfer

const asrc_p2p_edma_config_t *peripheralConfig

peripheral configuration pointer

struct _asrc_out_edma_handle

#include <fsl_asrc_edma.h>

@ brief asrc out edma handler

Public Members

edma_handle_t *outDmaHandle

DMA handler for ASRC out

uint8_t tcd[(((4U) * 2U) + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA send.

uint32_t sampleWidth

output data width

uint32_t fifoThreshold

ASRC output fifo threshold

uint32_t *asrcQueue[((4U) * 2U)]

Transfer queue storing queued transfer.

size_t transferSize[((4U) * 2U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint32_t state

Internal state for ASRC eDMA transfer

const asrc_p2p_edma_config_t *peripheralConfig

peripheral configuration pointer

struct _asrc_edma_handle

#include <fsl_asrc_edma.h>

ASRC DMA transfer handle.

Public Members

asrc_in_edma_handle_t in

asrc in handler

asrc_out_edma_handle_t out

asrc out handler

asrc_channel_pair_t channelPair

channel pair

void *userData

User callback parameter

asrc_edma_callback_t callback

Callback for users while transfer finish or error occurs

CAAM: Cryptographic Acceleration and Assurance Module

FSL_CAAM_DRIVER_VERSION

CAAM driver version. Version 2.3.2.

Current version: 2.3.2

Change log:

• Version 2.0.0

  • Initial version

• Version 2.0.1

  • Add Job Ring 2 and 3.

• Version 2.0.2

  • Add Data and Instruction Synchronization Barrier in caam_input_ring_set_jobs_added() to make sure that the descriptor will be loaded into CAAM correctly.

• Version 2.0.3

  • Use MACRO instead of numbers in descriptor.

  • Correct descriptor size mask.

• Version 2.1.0

  • Add return codes check and handling.

• Version 2.1.1

  • Add DCACHE support.

• Version 2.1.2

  • Add data offset feature to provide support for mirrored (high-speed) memory.

• Version 2.1.3

  • Fix MISRA-2012 issues.

• Version 2.1.4

  • Fix MISRA-2012 issues.

• Version 2.1.5

  • Support EXTENDED data size for all AES, HASH and RNG operations.

  • Support multiple De-Initialization/Initialization of CAAM driver within one POR event.

• Version 2.1.6

  • Improve DCACHE handling. Requires CAAM used and cached memory set in write-trough mode.

• Version 2.2.0

  • Added API for Blob functions and CRC

• Version 2.2.1

  • Fixed AES-CCM decrypt failing with TAG length bigger than 8 byte.

• Version 2.2.2

  • Modify RNG to not reseed with each request.

• Version 2.2.3

  • Fix DCACHE invalidation in CAAM_HASH_Finish().

• Version 2.2.4

  • Fix issue where the outputSize parameter of CAAM_HASH_Finish() has impact on hash calculation.

• Version 2.3.0

  • Add support for SHA HMAC.

• Version 2.3.1

  • Modified function caam_aes_ccm_check_input_args() to allow payload be empty as is specified in NIST800-38C Section 5.3.

• Version 2.3.2

  • Fix MISRA-2012 issues.

CAAM status return codes.

Values:

enumerator kStatus_CAAM_Again

Non-blocking function shall be called again.

enumerator kStatus_CAAM_DataOverflow

Input data too big.

enum _caam_job_ring_t

CAAM job ring selection.

Values:

enumerator kCAAM_JobRing0

CAAM Job ring 0

enumerator kCAAM_JobRing1

CAAM Job ring 1

enumerator kCAAM_JobRing2

CAAM Job ring 2

enumerator kCAAM_JobRing3

CAAM Job ring 3

enum _caam_wait_mode

CAAM driver wait mechanism.

Values:

enumerator kCAAM_Blocking

CAAM_Wait blocking mode

enumerator kCAAM_Nonblocking

CAAM Wait non-blocking mode

enum _caam_rng_sample_mode

CAAM RNG sample mode. Used by caam_config_t.

Values:

enumerator kCAAM_RNG_SampleModeVonNeumann

Use von Neumann data in both Entropy shifter and Statistical Checker.

enumerator kCAAM_RNG_SampleModeRaw

Use raw data into both Entropy shifter and Statistical Checker.

enumerator kCAAM_RNG_SampleModeVonNeumannRaw

Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker.

enum _caam_rng_ring_osc_div

CAAM RNG ring oscillator divide. Used by caam_config_t.

Values:

enumerator kCAAM_RNG_RingOscDiv0

Ring oscillator with no divide

enumerator kCAAM_RNG_RingOscDiv2

Ring oscillator divided-by-2.

enumerator kCAAM_RNG_RingOscDiv4

Ring oscillator divided-by-4.

enumerator kCAAM_RNG_RingOscDiv8

Ring oscillator divided-by-8.

enum _caam_priblob

CAAM Private Blob. Used by caam_config_t.

Values:

enumerator kCAAM_PrivSecureBootBlobs

Private secure boot software blobs.

enumerator kCAAM_PrivProvisioningBlobsType1

Private Provisioning Type 1 blobs.

enumerator kCAAM_PrivProvisioningBlobsType2

Private Provisioning Type 2 blobs.

enumerator kCAAM_NormalOperationBlobs

Normal operation blobs.

enum _caam_ext_key_xfr_source

CAAM External Key Transfer command SRC (The source from which the key will be obtained)

Values:

enumerator kCAAM_ExtKeyXfr_KeyRegisterClass1

The Class 1 Key Register is the source.

enumerator kCAAM_ExtKeyXfr_KeyRegisterClass2

The Class 2 Key Register is the source.

enumerator kCAAM_ExtKeyXfr_PkhaRamE

The PKHA E RAM is the source.

typedef struct _caam_job_callback caam_job_callback_t

CAAM callback function.

typedef enum _caam_job_ring_t caam_job_ring_t

CAAM job ring selection.

typedef struct _caam_handle_t caam_handle_t

CAAM handle Specifies jobRing and optionally the user callback function. The user callback functions is invoked only if jobRing interrupt has been enabled by the user. By default the jobRing interrupt is disabled (default job complete test is polling CAAM output ring).

typedef enum _caam_wait_mode caam_wait_mode_t

CAAM driver wait mechanism.

typedef uint32_t caam_desc_aes_ecb_t[64]

Memory buffer to hold CAAM descriptor for AESA ECB job.

typedef uint32_t caam_desc_aes_cbc_t[64]

Memory buffer to hold CAAM descriptor for AESA CBC job.

typedef uint32_t caam_desc_aes_ctr_t[64]

Memory buffer to hold CAAM descriptor for AESA CTR job.

typedef uint32_t caam_desc_aes_ccm_t[64]

Memory buffer to hold CAAM descriptor for AESA CCM job.

typedef uint32_t caam_desc_aes_gcm_t[64]

Memory buffer to hold CAAM descriptor for AESA GCM job.

typedef uint32_t caam_desc_hash_t[64]

Memory buffer to hold CAAM descriptor for MDHA job or AESA CMAC job.

typedef uint32_t caam_desc_rng_t[64]

Memory buffer to hold CAAM descriptor for RNG jobs.

typedef uint32_t caam_desc_cipher_des_t[64]

Memory buffer to hold CAAM descriptor for DESA jobs.

typedef uint32_t caam_desc_pkha_t[64]

Memory buffer to hold CAAM descriptor for PKHA jobs.

typedef uint32_t caam_desc_pkha_ecc_t[64]

Memory buffer to hold CAAM descriptor for PKHA ECC jobs.

typedef uint32_t caam_desc_key_black_t[64]

Memory buffer to hold CAAM descriptor for performing key blackening jobs.

typedef uint32_t caam_desc_gen_enc_blob_t[64]

Memory buffer to hold CAAM descriptor for performing generating dek blob jobs.

typedef uint32_t caam_desc_gen_dep_blob_t[64]

typedef struct _caam_job_ring_interface caam_job_ring_interface_t

typedef enum _caam_rng_sample_mode caam_rng_sample_mode_t

CAAM RNG sample mode. Used by caam_config_t.

typedef enum _caam_rng_ring_osc_div caam_rng_ring_osc_div_t

CAAM RNG ring oscillator divide. Used by caam_config_t.

typedef enum _caam_priblob caam_priblob_t

CAAM Private Blob. Used by caam_config_t.

typedef struct _caam_config caam_config_t

CAAM configuration structure.

typedef enum _caam_ext_key_xfr_source caam_ext_key_xfr_source_t

CAAM External Key Transfer command SRC (The source from which the key will be obtained)

status_t CAAM_Init(CAAM_Type *base, const caam_config_t *config)

Initializes the CAAM driver.

This function initializes the CAAM driver, including CAAM’s internal RNG.

Parameters:

• base – CAAM peripheral base address

• config – Pointer to configuration structure.

Returns:

kStatus_Success the CAAM Init has completed with zero termination status word

Returns:

kStatus_Fail the CAAM Init has completed with non-zero termination status word

status_t CAAM_Deinit(CAAM_Type *base)

Deinitializes the CAAM driver. This function deinitializes the CAAM driver.

Parameters:

• base – CAAM peripheral base address

Returns:

kStatus_Success the CAAM Deinit has completed with zero termination status word

Returns:

kStatus_Fail the CAAM Deinit has completed with non-zero termination status word

void CAAM_GetDefaultConfig(caam_config_t *config)

Gets the default configuration structure.

This function initializes the CAAM configuration structure to a default value. The default values are as follows. caamConfig->rngSampleMode = kCAAM_RNG_SampleModeVonNeumann; caamConfig->rngRingOscDiv = kCAAM_RNG_RingOscDiv4;

Parameters:

• config – [out] Pointer to configuration structure.

status_t CAAM_Wait(CAAM_Type *base, caam_handle_t *handle, uint32_t *descriptor, caam_wait_mode_t mode)

Wait for a CAAM job to complete.

This function polls CAAM output ring for a specific job.

The CAAM job ring is specified by the jobRing field in the caam_handle_t structure. The job to be waited is specified by it’s descriptor address.

This function has two modes, determined by the mode argument. In blocking mode, the function polls the specified jobRing until the descriptor is available in the CAAM output job ring. In non-blocking mode, it polls the output ring once and returns status immediately.

The function can be called from multiple threads or interrupt service routines, as internally it uses global critical section (global interrupt disable enable) to protect it’s operation against concurrent accesses. The global interrupt is disabled only when the descriptor is found in the output ring, for a very short time, to remove the descriptor from the output ring safely.

Parameters:

• base – CAAM peripheral base address

• handle – Data structure with CAAM jobRing used for this request

• descriptor –

• mode – Blocking and non-blocking mode. Zero is blocking. Non-zero is non-blocking.

Returns:

kStatus_Success the CAAM job has completed with zero job termination status word

Returns:

kStatus_Fail the CAAM job has completed with non-zero job termination status word

Returns:

kStatus_Again In non-blocking mode, the job is not ready in the CAAM Output Ring

status_t CAAM_ExternalKeyTransfer(CAAM_Type *base, caam_handle_t *handle, caam_ext_key_xfr_source_t keySource, size_t keySize)

External Key Transfer.

This function loads the given key source to an CAAM external destination via a private interface, such as Inline Encryption Engine IEE Private Key bus.

The CAAM job ring is specified by the jobRing field in the caam_handle_t structure.

This function is blocking.

Parameters:

• base – CAAM peripheral base address

• handle – Data structure with CAAM jobRing used for this request.

• keySource – The source from which the key will be obtained.

• keySize – Size of the key in bytes.

Returns:

kStatus_Success the CAAM job has completed with zero job termination status word

Returns:

kStatus_Fail the CAAM job has completed with non-zero job termination status word

struct _caam_job_callback

#include <fsl_caam.h>

CAAM callback function.

Public Members

void (*JobCompleted)(void *userData)

CAAM Job complete callback

struct _caam_handle_t

#include <fsl_caam.h>

CAAM handle Specifies jobRing and optionally the user callback function. The user callback functions is invoked only if jobRing interrupt has been enabled by the user. By default the jobRing interrupt is disabled (default job complete test is polling CAAM output ring).

Public Members

caam_job_callback_t callback

Callback function

void *userData

Parameter for CAAM job complete callback

struct _caam_job_ring_interface

#include <fsl_caam.h>

struct _caam_config

#include <fsl_caam.h>

CAAM configuration structure.

Public Members

caam_rng_sample_mode_t rngSampleMode

RTMCTL Sample Mode.

caam_rng_ring_osc_div_t rngRingOscDiv

RTMCTL Oscillator Divide.

bool scfgrLockTrngProgramMode

SCFGR Lock TRNG Program Mode.

bool scfgrEnableRandomDataBuffer

SCFGR Enable random data buffer.

bool scfgrRandomRngStateHandle0

SCFGR Random Number Generator State Handle 0.

bool scfgrRandomDpaResistance

SCFGR Random Differential Power Analysis Resistance.

caam_priblob_t scfgrPriblob

SCFGR Private Blob.

CAAM AES driver

status_t CAAM_AES_EncryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *key, size_t keySize)

Encrypts AES using the ECB block mode.

Encrypts AES using the ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from encrypt operation

status_t CAAM_AES_DecryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *key, size_t keySize)

Decrypts AES using ECB block mode.

Decrypts AES using ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• key – Input key.

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from decrypt operation

status_t CAAM_AES_EncryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[16], const uint8_t *key, size_t keySize)

Encrypts AES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• iv – Input initial vector to combine with the first input block.

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from encrypt operation

status_t CAAM_AES_DecryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[16], const uint8_t *key, size_t keySize)

Decrypts AES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• iv – Input initial vector to combine with the first input block.

• key – Input key to use for decryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from decrypt operation

status_t CAAM_AES_CryptCtr(CAAM_Type *base, caam_handle_t *handle, const uint8_t *input, uint8_t *output, size_t size, uint8_t counter[16], const uint8_t *key, size_t keySize, uint8_t counterlast[16], size_t *szLeft)

Encrypts or decrypts AES using CTR block mode.

Encrypts or decrypts AES using CTR block mode. AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. The only difference between encryption and decryption is that, for encryption, the input argument is plain text and the output argument is cipher text. For decryption, the input argument is cipher text and the output argument is plain text.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• input – Input data for CTR block mode

• output – [out] Output data for CTR block mode

• size – Size of input and output data in bytes

• counter – [inout] Input counter (updates on return)

• key – Input key to use for forward AES cipher

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• counterlast – [out] Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are not used.

• szLeft – [out] Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls are not used.

Returns:

Status from encrypt operation

status_t CAAM_AES_EncryptTagCcm(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, uint8_t *tag, size_t tagSize)

Encrypts AES and tags using CCM block mode.

Encrypts AES and optionally tags using CCM block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text.

• size – Size of input and output data in bytes. Zero means authentication only.

• iv – Nonce

• ivSize – Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.

• aad – Input additional authentication data. Can be NULL if aadSize is zero.

• aadSize – Input size in bytes of AAD. Zero means data mode only (authentication skipped).

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – [out] Generated output tag. Set to NULL to skip tag processing.

• tagSize – Input size of the tag to generate, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16.

Returns:

Status from encrypt operation

status_t CAAM_AES_DecryptTagCcm(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, const uint8_t *tag, size_t tagSize)

Decrypts AES and authenticates using CCM block mode.

Decrypts AES and optionally authenticates using CCM block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text.

• size – Size of input and output data in bytes. Zero means authentication data only.

• iv – Nonce

• ivSize – Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.

• aad – Input additional authentication data. Can be NULL if aadSize is zero.

• aadSize – Input size in bytes of AAD. Zero means data mode only (authentication data skipped).

• key – Input key to use for decryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – Received tag. Set to NULL to skip tag processing.

• tagSize – Input size of the received tag to compare with the computed tag, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16.

Returns:

Status from decrypt operation

status_t CAAM_AES_EncryptTagGcm(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, uint8_t *tag, size_t tagSize)

Encrypts AES and tags using GCM block mode.

Encrypts AES and optionally tags using GCM block mode. If plaintext is NULL, only the GHASH is calculated and output in the ‘tag’ field.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text.

• size – Size of input and output data in bytes

• iv – Input initial vector

• ivSize – Size of the IV

• aad – Input additional authentication data

• aadSize – Input size in bytes of AAD

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – [out] Output hash tag. Set to NULL to skip tag processing.

• tagSize – Input size of the tag to generate, in bytes. Must be 4,8,12,13,14,15 or 16.

Returns:

Status from encrypt operation

status_t CAAM_AES_DecryptTagGcm(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, const uint8_t *tag, size_t tagSize)

Decrypts AES and authenticates using GCM block mode.

Decrypts AES and optionally authenticates using GCM block mode. If ciphertext is NULL, only the GHASH is calculated and compared with the received GHASH in ‘tag’ field.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text.

• size – Size of input and output data in bytes

• iv – Input initial vector

• ivSize – Size of the IV

• aad – Input additional authentication data

• aadSize – Input size in bytes of AAD

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – Input hash tag to compare. Set to NULL to skip tag processing.

• tagSize – Input size of the tag, in bytes. Must be 4, 8, 12, 13, 14, 15, or 16.

Returns:

Status from decrypt operation

CAAM_AES_BLOCK_SIZE

AES block size in bytes

CAAM Key Blankening driver

status_t CAAM_BLACK_GetKeyBlacken(CAAM_Type *base, caam_handle_t *handle, const uint8_t *data, size_t dataSize, caam_fifost_type_t fifostType, uint8_t *blackdata)

Construct a black key.

This function constructs a job descriptor capable of performing a key blackening operation on a plaintext secure memory resident object.

Parameters:

• base – CAAM peripheral base address

• handle – jobRing used for this request

• data – Pointer address uses to pointed the plaintext.

• dataSize – Size of the buffer pointed by the data parameter

• fifostType – Type of AES-CBC or AEC-CCM to encrypt plaintext

• blackdata – [out] Pointer address uses to pointed the black key

Returns:

Status of the request

CAAM Blob driver

enum _caam_fifost_type

CAAM FIFOST types.

Values:

enumerator kCAAM_FIFOST_Type_Kek_Kek

Key Register, encrypted using AES-ECB with the job descriptor key encryption key.

enumerator kCAAM_FIFOST_Type_Kek_TKek

Key Register, encrypted using AES-ECB with the trusted descriptor key encryption key.

enumerator kCAAM_FIFOST_Type_Kek_Cmm_Jkek

Key Register, encrypted using AES-CCM with the job descriptor key encryption key.

enumerator kCAAM_FIFOST_Type_Kek_Cmm_Tkek

Key register, encrypted using AES-CCM with the trusted descriptor key encryption key.

enum _caam_desc_type

CAAM descriptor types.

Values:

enumerator kCAAM_Descriptor_Type_Kek_Kek

Key Register, encrypted using AES-ECB with the job descriptor key encryption key.

enumerator kCAAM_Descriptor_Type_Kek_TKek

Key Register, encrypted using AES-ECB with the trusted descriptor key encryption key.

enumerator kCAAM_Descriptor_Type_Kek_Ccm_Jkek

Key Register, encrypted using AES-CCM with the job descriptor key encryption key.

enumerator kCAAM_Descriptor_Type_Kek_Ccm_Tkek

Key register, encrypted using AES-CCM with the trusted descriptor key encryption key.

typedef enum _caam_fifost_type caam_fifost_type_t

CAAM FIFOST types.

typedef enum _caam_desc_type caam_desc_type_t

CAAM descriptor types.

status_t CAAM_RedBlob_Encapsule(CAAM_Type *base, caam_handle_t *handle, const uint8_t *keyModifier, size_t keyModifierSize, const uint8_t *data, size_t dataSize, uint8_t *blob_data)

Construct a encrypted Red Blob.

This function constructs a job descriptor capable of performing a encrypted blob operation on a plaintext object.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• keyModifier – Address of the random key modifier generated by RNG

• keyModifierSize – Size of keyModifier buffer in bytes

• data – Data adress

• dataSize – Size of the buffer pointed by the data parameter

• blob_data – [out] Output blob data adress

Returns:

Status of the request

status_t CAAM_RedBlob_Decapsule(CAAM_Type *base, caam_handle_t *handle, const uint8_t *keyModifier, size_t keyModifierSize, const uint8_t *blob_data, uint8_t *data, size_t dataSize)

Decrypt red blob.

This function constructs a job descriptor capable of performing decrypting red blob .

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• keyModifier – Address of the random key modifier generated by RNG

• keyModifierSize – Size of keyModifier buffer in bytes

• blob_data – Address of blob data

• data – [out] Output data adress.

• dataSize – Size of the buffer pointed by the data parameter in bytes

Returns:

Status of the request

status_t CAAM_BlackBlob_Encapsule(CAAM_Type *base, caam_handle_t *handle, const uint8_t *keyModifier, size_t keyModifierSize, const uint8_t *data, size_t dataSize, uint8_t *blob_data, caam_desc_type_t blackKeyType)

Construct a encrypted Black Blob.

This function constructs a job descriptor capable of performing a encrypted blob operation on a plaintext object.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• keyModifier – Address of the random key modifier generated by RNG

• keyModifierSize – Size of keyModifier buffer in bytes

• data – Data adress

• dataSize – Size of the buffer pointed by the data parameter

• blob_data – [out] Output blob data adress

• blackKeyType – Type of black key see enum caam_desc_type_t for more info

Returns:

Status of the request

status_t CAAM_BlackBlob_Decapsule(CAAM_Type *base, caam_handle_t *handle, const uint8_t *keyModifier, size_t keyModifierSize, const uint8_t *blob_data, uint8_t *data, size_t dataSize, caam_desc_type_t blackKeyType)

Construct a decrypted black blob.

This function constructs a job descriptor capable of performing decrypting black blob.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• keyModifier – Address of the random key modifier generated by RNG

• keyModifierSize – Size of keyModifier buffer in bytes

• blob_data – Address of blob data

• data – [out] Output data adress.

• dataSize – Size of the buffer pointed by the data parameter in bytes

• blackKeyType – Type of black key see enum caam_desc_type_t for more info

Returns:

Status of the request

CAAM CRC driver

status_t CAAM_CRC_Init(CAAM_Type *base, caam_handle_t *handle, caam_hash_ctx_t *ctx, caam_crc_algo_t algo, const uint8_t *polynomial, size_t polynomialSize, caam_aai_crc_alg_t mode)

Initialize CRC context.

This function initializes the CRC context. polynomial shall be supplied if the underlaying algoritm is kCAAM_CrcCUSTPOLY. polynomial shall be NULL if the underlaying algoritm is kCAAM_CrcIEEE or kCAAM_CrciSCSI.

This functions is used to initialize the context for CAAM_CRC API

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• ctx – [out] Output crc context

• algo – Underlaying algorithm to use for CRC computation

• polynomial – CRC polynomial (NULL if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• polynomialSize – Size of polynomial in bytes (0u if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• mode – Specify how CRC engine manipulates its input and output data

Returns:

Status of initialization

status_t CAAM_CRC_Update(caam_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)

Add data to current CRC.

Add data to current CRC. This can be called repeatedly. The functions blocks. If it returns kStatus_Success, the running CRC has been updated (CAAM has processed the input data), so the memory at input pointer can be released back to system. The context is updated with the running CRC and with all necessary information to support possible context switch.

Parameters:

• ctx – [inout] CRC context

• input – Input data

• inputSize – Size of input data in bytes

Returns:

Status of the crc update operation

status_t CAAM_CRC_Finish(caam_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)

Finalize CRC.

Outputs the final CRC (computed by CAAM_CRC_Update()) and erases the context.

Parameters:

• ctx – [inout] Input crc context

• output – [out] Output crc data

• outputSize – [out] Output parameter storing the size of the output crc in bytes

Returns:

Status of the crc finish operation

status_t CAAM_CRC(CAAM_Type *base, caam_handle_t *handle, caam_crc_algo_t algo, caam_aai_crc_alg_t mode, const uint8_t *input, size_t inputSize, const uint8_t *polynomial, size_t polynomialSize, uint8_t *output, size_t *outputSize)

Create CRC on given data.

Perform CRC in one function call.

Polynomial shall be supplied if underlaying algorithm is kCAAM_CrcCUSTPOLY. Polynomial shall be NULL if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI.

The function is blocking.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• algo – Underlaying algorithm to use for crc computation.

• mode – Specify how CRC engine manipulates its input and output data.

• input – Input data

• inputSize – Size of input data in bytes

• polynomial – CRC polynomial (NULL if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• polynomialSize – Size of input polynomial in bytes (0U if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• output – [out] Output crc data

• outputSize – [out] Output parameter storing the size of the output crc in bytes

Returns:

Status of the one call crc operation.

status_t CAAM_CRC_NonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_hash_t descriptor, caam_crc_algo_t algo, caam_aai_crc_alg_t mode, const uint8_t *input, size_t inputSize, const uint8_t *polynomial, size_t polynomialSize, uint8_t *output, size_t *outputSize)

Create CRC on given data.

Perform CRC in one function call.

Polynomial shall be supplied if underlaying algorithm is kCAAM_CrcCUSTPOLY. Polynomial shall be NULL if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI.

The function is non-blocking. The request is scheduled at CAAM.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• descriptor – [out] Memory for the CAAM descriptor.

• algo – Underlaying algorithm to use for crc computation.

• mode – Specify how CRC engine manipulates its input and output data.

• input – Input data

• inputSize – Size of input data in bytes

• polynomial – CRC polynomial (NULL if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• polynomialSize – Size of input polynomial in bytes (0U if underlaying algorithm is kCAAM_CrcIEEE or kCAAM_CrciSCSI)

• output – [out] Output crc data

• outputSize – [out] Output parameter storing the size of the output crc in bytes

Returns:

Status of the one call crc operation.

CAAM DES driver

status_t CAAM_DES_EncryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key[8U])

Encrypts DES using ECB block mode.

Encrypts DES using ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key – Input key to use for encryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_DecryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key[8U])

Decrypts DES using ECB block mode.

Decrypts DES using ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key – Input key to use for decryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_EncryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using CBC block mode.

Encrypts DES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Ouput ciphertext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key – Input key to use for encryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_DecryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using CBC block mode.

Decrypts DES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key – Input key to use for decryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_EncryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using CFB block mode.

Encrypts DES using CFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• size – Size of input data in bytes

• iv – Input initial block.

• key – Input key to use for encryption

• ciphertext – [out] Output ciphertext

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_DecryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using CFB block mode.

Decrypts DES using CFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key – Input key to use for decryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_EncryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using OFB block mode.

Encrypts DES using OFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key – Input key to use for encryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES_DecryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using OFB block mode.

Decrypts DES using OFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key – Input key to use for decryption

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_EncryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using ECB block mode with two keys.

Encrypts triple DES using ECB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_DecryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using ECB block mode with two keys.

Decrypts triple DES using ECB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_EncryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using CBC block mode with two keys.

Encrypts triple DES using CBC block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_DecryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using CBC block mode with two keys.

Decrypts triple DES using CBC block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_EncryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using CFB block mode with two keys.

Encrypts triple DES using CFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_DecryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using CFB block mode with two keys.

Decrypts triple DES using CFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_EncryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using OFB block mode with two keys.

Encrypts triple DES using OFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES2_DecryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using OFB block mode with two keys.

Decrypts triple DES using OFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_EncryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using ECB block mode with three keys.

Encrypts triple DES using ECB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_DecryptEcb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using ECB block mode with three keys.

Decrypts triple DES using ECB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_EncryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using CBC block mode with three keys.

Encrypts triple DES using CBC block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_DecryptCbc(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using CBC block mode with three keys.

Decrypts triple DES using CBC block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_EncryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using CFB block mode with three keys.

Encrypts triple DES using CFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and ouput data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_DecryptCfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using CFB block mode with three keys.

Decrypts triple DES using CFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_EncryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using OFB block mode with three keys.

Encrypts triple DES using OFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

status_t CAAM_DES3_DecryptOfb(CAAM_Type *base, caam_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using OFB block mode with three keys.

Decrypts triple DES using OFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from encrypt/decrypt operation

CAAM_DES_KEY_SIZE

CAAM DES key size - 64 bits.

CAAM_DES_IV_SIZE

CAAM DES IV size - 8 bytes.

CAAM HASH driver

enum _caam_hash_algo_t

Supported cryptographic block cipher functions for HASH creation.

Values:

enumerator kCAAM_XcbcMac

XCBC-MAC (AES engine)

enumerator kCAAM_Cmac

CMAC (AES engine)

enumerator kCAAM_Sha1

SHA_1 (MDHA engine)

enumerator kCAAM_Sha224

SHA_224 (MDHA engine)

enumerator kCAAM_Sha256

SHA_256 (MDHA engine)

enumerator kCAAM_Sha384

SHA_384 (MDHA engine)

enumerator kCAAM_Sha512

SHA_512 (MDHA engine)

enumerator kCAAM_HmacSha1

HMAC_SHA_1 (MDHA engine)

enumerator kCAAM_HmacSha224

HMAC_SHA_224 (MDHA engine)

enumerator kCAAM_HmacSha256

HMAC_SHA_256 (MDHA engine)

enumerator kCAAM_HmacSha384

HMAC_SHA_384 (MDHA engine)

enumerator kCAAM_HmacSha512

HMAC_SHA_512 (MDHA engine)

typedef enum _caam_hash_algo_t caam_hash_algo_t

Supported cryptographic block cipher functions for HASH creation.

typedef uint32_t caam_hash_ctx_t[83]

Storage type used to save hash context.

status_t CAAM_HASH_Init(CAAM_Type *base, caam_handle_t *handle, caam_hash_ctx_t *ctx, caam_hash_algo_t algo, const uint8_t *key, size_t keySize)

Initialize HASH context.

This function initializes the HASH. Key shall be supplied if the underlaying algoritm is AES XCBC-MAC or CMAC. Key shall be NULL if the underlaying algoritm is SHA.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For MDHA the key length argument is ignored.

This functions is used to initialize the context for both blocking and non-blocking CAAM_HASH API. For blocking CAAM HASH API, the HASH context contains all information required for context switch, such as running hash or MAC. For non-blocking CAAM HASH API, the HASH context is used to hold SGT. Therefore, the HASH context cannot be shared between blocking and non-blocking HASH API. With one HASH context, either use only blocking HASH API or only non-blocking HASH API.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• ctx – [out] Output hash context

• algo – Underlaying algorithm to use for hash computation.

• key – Input key (NULL if underlaying algorithm is SHA)

• keySize – Size of input key in bytes

Returns:

Status of initialization

status_t CAAM_HASH_Update(caam_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)

Add data to current HASH.

Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be hashed. The functions blocks. If it returns kStatus_Success, the running hash or mac has been updated (CAAM has processed the input data), so the memory at input pointer can be released back to system. The context is updated with the running hash or mac and with all necessary information to support possible context switch.

Parameters:

• ctx – [inout] HASH context

• input – Input data

• inputSize – Size of input data in bytes

Returns:

Status of the hash update operation

status_t CAAM_HASH_Finish(caam_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)

Finalize hashing.

Outputs the final hash (computed by CAAM_HASH_Update()) and erases the context.

Parameters:

• ctx – [inout] Input hash context

• output – [out] Output hash data

• outputSize – [out] Output parameter storing the size of the output hash in bytes

Returns:

Status of the hash finish operation

status_t CAAM_HASH(CAAM_Type *base, caam_handle_t *handle, caam_hash_algo_t algo, const uint8_t *input, size_t inputSize, const uint8_t *key, size_t keySize, uint8_t *output, size_t *outputSize)

Create HASH on given data.

Perform the full keyed XCBC-MAC/CMAC or SHA in one function call.

Key shall be supplied if the underlaying algoritm is AES XCBC-MAC or CMAC. Key shall be NULL if the underlaying algoritm is SHA.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For MDHA the key length argument is ignored.

The function is blocking.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• algo – Underlaying algorithm to use for hash computation.

• input – Input data

• inputSize – Size of input data in bytes

• key – Input key (NULL if underlaying algorithm is SHA)

• keySize – Size of input key in bytes

• output – [out] Output hash data

• outputSize – [out] Output parameter storing the size of the output hash in bytes

Returns:

Status of the one call hash operation.

CAAM_SHA_BLOCK_SIZE

CAAM HASH Context size.

up to SHA-512 block size

CAAM_HASH_BLOCK_SIZE

CAAM hash block size

CAAM_HASH_CTX_SIZE

CAAM HASH Context size.

Caam_driver_hmac

status_t CAAM_HMAC_Init(CAAM_Type *base, caam_handle_t *handle, caam_hash_ctx_t *ctx, caam_hash_algo_t algo, const uint8_t *key, size_t keySize)

Initialize HMAC context.

This function initializes the HMAC.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For MDHA the key length argument is ignored.

This functions is used to initialize the context for both blocking and non-blocking CAAM_HMAC API.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• ctx – [out] Output HMAC context

• algo – Underlaying algorithm to use for HMAC computation.

• key – Input key

• keySize – Size of input key in bytes

Returns:

Status of initialization

status_t CAAM_HMAC(CAAM_Type *base, caam_handle_t *handle, caam_hash_algo_t algo, const uint8_t *input, size_t inputSize, const uint8_t *key, size_t keySize, uint8_t *output, size_t *outputSize)

Create Message Authentication Code (MAC) on given data.

Perform the full keyed XCBC-MAC/CMAC, or HMAC-SHA in one function call.

Key shall be supplied if the underlaying algoritm is AES XCBC-MAC, CMAC, or SHA HMAC.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For HMAC, the key can have any size.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• algo – Underlaying algorithm to use for MAC computation.

• input – Input data

• inputSize – Size of input data in bytes

• key – Input key

• keySize – Size of input key in bytes

• output – [out] Output MAC data

• outputSize – [out] Output parameter storing the size of the output MAC in bytes

Returns:

Status of the one call hash operation.

CAAM PKHA driver

enum _caam_pkha_timing_t

Use of timing equalized version of a PKHA function.

Values:

enumerator kCAAM_PKHA_NoTimingEqualized

Normal version of a PKHA operation

enumerator kCAAM_PKHA_TimingEqualized

Timing-equalized version of a PKHA operation

enum _caam_pkha_f2m_t

Integer vs binary polynomial arithmetic selection.

Values:

enumerator kCAAM_PKHA_IntegerArith

Use integer arithmetic

enumerator kCAAM_PKHA_F2mArith

Use binary polynomial arithmetic

enum _caam_pkha_montgomery_form_t

Montgomery or normal PKHA input format.

Values:

enumerator kCAAM_PKHA_NormalValue

PKHA number is normal integer

enumerator kCAAM_PKHA_MontgomeryFormat

PKHA number is in montgomery format

typedef struct _caam_pkha_ecc_point_t caam_pkha_ecc_point_t

PKHA ECC point structure

typedef enum _caam_pkha_timing_t caam_pkha_timing_t

Use of timing equalized version of a PKHA function.

typedef enum _caam_pkha_f2m_t caam_pkha_f2m_t

Integer vs binary polynomial arithmetic selection.

typedef enum _caam_pkha_montgomery_form_t caam_pkha_montgomery_form_t

Montgomery or normal PKHA input format.

int CAAM_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB)

status_t CAAM_PKHA_NormalToMontgomery(CAAM_Type *base, caam_handle_t *handle, const uint8_t *N, size_t sizeN, uint8_t *A, size_t *sizeA, uint8_t *B, size_t *sizeB, uint8_t *R2, size_t *sizeR2, caam_pkha_timing_t equalTime, caam_pkha_f2m_t arithType)

Converts from integer to Montgomery format.

This function computes R2 mod N and optionally converts A or B into Montgomery format of A or B.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• N – modulus

• sizeN – size of N in bytes

• A – [inout] The first input in non-Montgomery format. Output Montgomery format of the first input.

• sizeA – [inout] pointer to size variable. On input it holds size of input A in bytes. On output it holds size of Montgomery format of A in bytes.

• B – [inout] Second input in non-Montgomery format. Output Montgomery format of the second input.

• sizeB – [inout] pointer to size variable. On input it holds size of input B in bytes. On output it holds size of Montgomery format of B in bytes.

• R2 – [out] Output Montgomery factor R2 mod N.

• sizeR2 – [out] pointer to size variable. On output it holds size of Montgomery factor R2 mod N in bytes.

• equalTime – Run the function time equalized or no timing equalization.

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_MontgomeryToNormal(CAAM_Type *base, caam_handle_t *handle, const uint8_t *N, size_t sizeN, uint8_t *A, size_t *sizeA, uint8_t *B, size_t *sizeB, caam_pkha_timing_t equalTime, caam_pkha_f2m_t arithType)

Converts from Montgomery format to int.

This function converts Montgomery format of A or B into int A or B.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• N – modulus.

• sizeN – size of N modulus in bytes.

• A – [inout] Input first number in Montgomery format. Output is non-Montgomery format.

• sizeA – [inout] pointer to size variable. On input it holds size of the input A in bytes. On output it holds size of non-Montgomery A in bytes.

• B – [inout] Input first number in Montgomery format. Output is non-Montgomery format.

• sizeB – [inout] pointer to size variable. On input it holds size of the input B in bytes. On output it holds size of non-Montgomery B in bytes.

• equalTime – Run the function time equalized or no timing equalization.

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_ModAdd(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *B, size_t sizeB, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType)

Performs modular addition - (A + B) mod N.

This function performs modular addition of (A + B) mod N, with either integer or binary polynomial (F2m) inputs. In the F2m form, this function is equivalent to a bitwise XOR and it is functionally the same as subtraction.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• B – second addend (integer or binary polynomial)

• sizeB – Size of B in bytes

• N – modulus.

• sizeN – Size of N in bytes.

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_ModSub1(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *B, size_t sizeB, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize)

Performs modular subtraction - (A - B) mod N.

This function performs modular subtraction of (A - B) mod N with integer inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• B – second addend (integer or binary polynomial)

• sizeB – Size of B in bytes

• N – modulus

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

Returns:

Operation status.

status_t CAAM_PKHA_ModSub2(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *B, size_t sizeB, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize)

Performs modular subtraction - (B - A) mod N.

This function performs modular subtraction of (B - A) mod N, with integer inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• B – second addend (integer or binary polynomial)

• sizeB – Size of B in bytes

• N – modulus

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

Returns:

Operation status.

status_t CAAM_PKHA_ModMul(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *B, size_t sizeB, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType, caam_pkha_montgomery_form_t montIn, caam_pkha_montgomery_form_t montOut, caam_pkha_timing_t equalTime)

Performs modular multiplication - (A x B) mod N.

This function performs modular multiplication with either integer or binary polynomial (F2m) inputs. It can optionally specify whether inputs and/or outputs will be in Montgomery form or not.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• B – second addend (integer or binary polynomial)

• sizeB – Size of B in bytes

• N – modulus.

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

• montIn – Format of inputs

• montOut – Format of output

• equalTime – Run the function time equalized or no timing equalization. This argument is ignored for F2m modular multiplication.

Returns:

Operation status.

status_t CAAM_PKHA_ModExp(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *N, size_t sizeN, const uint8_t *E, size_t sizeE, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType, caam_pkha_montgomery_form_t montIn, caam_pkha_timing_t equalTime)

Performs modular exponentiation - (A^E) mod N.

This function performs modular exponentiation with either integer or binary polynomial (F2m) inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• N – modulus

• sizeN – Size of N in bytes

• E – exponent

• sizeE – Size of E in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• montIn – Format of A input (normal or Montgomery)

• arithType – Type of arithmetic to perform (integer or F2m)

• equalTime – Run the function time equalized or no timing equalization.

Returns:

Operation status.

status_t CAAM_PKHA_ModRed(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType)

Performs modular reduction - (A) mod N.

This function performs modular reduction with either integer or binary polynomial (F2m) inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• N – modulus

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_ModInv(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType)

Performs modular inversion - (A^-1) mod N.

This function performs modular inversion with either integer or binary polynomial (F2m) inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first addend (integer or binary polynomial)

• sizeA – Size of A in bytes

• N – modulus

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_ModR2(CAAM_Type *base, caam_handle_t *handle, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType)

Computes integer Montgomery factor R^2 mod N.

This function computes a constant to assist in converting operands into the Montgomery residue system representation.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• N – modulus

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_ModGcd(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, caam_pkha_f2m_t arithType)

Calculates the greatest common divisor - GCD (A, N).

This function calculates the greatest common divisor of two inputs with either integer or binary polynomial (F2m) inputs.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – first value (must be smaller than or equal to N)

• sizeA – Size of A in bytes

• N – second value (must be non-zero)

• sizeN – Size of N in bytes

• result – [out] Output array to store result of operation

• resultSize – [out] Output size of operation in bytes

• arithType – Type of arithmetic to perform (integer or F2m)

Returns:

Operation status.

status_t CAAM_PKHA_PrimalityTest(CAAM_Type *base, caam_handle_t *handle, const uint8_t *A, size_t sizeA, const uint8_t *B, size_t sizeB, const uint8_t *N, size_t sizeN, bool *res)

Executes Miller-Rabin primality test.

This function calculates whether or not a candidate prime number is likely to be a prime.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – initial random seed

• sizeA – Size of A in bytes

• B – number of trial runs

• sizeB – Size of B in bytes

• N – candidate prime integer

• sizeN – Size of N in bytes

• res – [out] True if the value is likely prime or false otherwise

Returns:

Operation status.

status_t CAAM_PKHA_ECC_PointAdd(CAAM_Type *base, caam_handle_t *handle, const caam_pkha_ecc_point_t *A, const caam_pkha_ecc_point_t *B, const uint8_t *N, const uint8_t *R2modN, const uint8_t *aCurveParam, const uint8_t *bCurveParam, size_t size, caam_pkha_f2m_t arithType, caam_pkha_ecc_point_t *result)

Adds elliptic curve points - A + B.

This function performs ECC point addition over a prime field (Fp) or binary field (F2m) using affine coordinates.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – Left-hand point

• B – Right-hand point

• N – Prime modulus of the field

• R2modN – NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from CAAM_PKHA_ModR2() function).

• aCurveParam – A parameter from curve equation

• bCurveParam – B parameter from curve equation (constant)

• size – Size in bytes of curve points and parameters

• arithType – Type of arithmetic to perform (integer or F2m)

• result – [out] Result point

Returns:

Operation status.

status_t CAAM_PKHA_ECC_PointDouble(CAAM_Type *base, caam_handle_t *handle, const caam_pkha_ecc_point_t *B, const uint8_t *N, const uint8_t *aCurveParam, const uint8_t *bCurveParam, size_t size, caam_pkha_f2m_t arithType, caam_pkha_ecc_point_t *result)

Doubles elliptic curve points - B + B.

This function performs ECC point doubling over a prime field (Fp) or binary field (F2m) using affine coordinates.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• B – Point to double

• N – Prime modulus of the field

• aCurveParam – A parameter from curve equation

• bCurveParam – B parameter from curve equation (constant)

• size – Size in bytes of curve points and parameters

• arithType – Type of arithmetic to perform (integer or F2m)

• result – [out] Result point

Returns:

Operation status.

status_t CAAM_PKHA_ECC_PointMul(CAAM_Type *base, caam_handle_t *handle, const caam_pkha_ecc_point_t *A, const uint8_t *E, size_t sizeE, const uint8_t *N, const uint8_t *R2modN, const uint8_t *aCurveParam, const uint8_t *bCurveParam, size_t size, caam_pkha_timing_t equalTime, caam_pkha_f2m_t arithType, caam_pkha_ecc_point_t *result)

Multiplies an elliptic curve point by a scalar - E x (A0, A1).

This function performs ECC point multiplication to multiply an ECC point by a scalar integer multiplier over a prime field (Fp) or a binary field (F2m).

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• A – Point as multiplicand

• E – Scalar multiple

• sizeE – The size of E, in bytes

• N – Modulus, a prime number for the Fp field or Irreducible polynomial for F2m field.

• R2modN – NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from CAAM_PKHA_ModR2() function).

• aCurveParam – A parameter from curve equation

• bCurveParam – B parameter from curve equation (C parameter for operation over F2m).

• size – Size in bytes of curve points and parameters

• equalTime – Run the function time equalized or no timing equalization.

• arithType – Type of arithmetic to perform (integer or F2m)

• result – [out] Result point

Returns:

Operation status.

struct _caam_pkha_ecc_point_t

#include <fsl_caam.h>

PKHA ECC point structure

Public Members

uint8_t *X

X coordinate (affine)

uint8_t *Y

Y coordinate (affine)

CAAM RNG driver

enum _caam_rng_state_handle

CAAM RNG state handle.

Values:

enumerator kCAAM_RngStateHandle0

CAAM RNG state handle 0

enumerator kCAAM_RngStateHandle1

CAAM RNG state handle 1

enum _caam_rng_random_type

Type of random data to generate.

Values:

enumerator kCAAM_RngDataAny

CAAM RNG any random data bytes

enumerator kCAAM_RngDataOddParity

CAAM RNG odd parity random data bytes

enumerator kCAAM_RngDataNonZero

CAAM RNG non zero random data bytes

typedef enum _caam_rng_state_handle caam_rng_state_handle_t

CAAM RNG state handle.

typedef enum _caam_rng_random_type caam_rng_random_type_t

Type of random data to generate.

typedef uint32_t caam_rng_generic256_t[256 / sizeof(uint32_t)]

256-bit value used as optional additional entropy input

typedef struct _caam_rng_user_config caam_rng_config_t

CAAM RNG configuration.

status_t CAAM_RNG_GetDefaultConfig(caam_rng_config_t *config)

Initializes user configuration structure to default.

This function initializes the configure structure to default value. the default value are:

config->autoReseedInterval = 0;
config->personalString = NULL;

Parameters:

• config – User configuration structure.

Returns:

status of the request

status_t CAAM_RNG_Init(CAAM_Type *base, caam_handle_t *handle, caam_rng_state_handle_t stateHandle, const caam_rng_config_t *config)

Instantiate the CAAM RNG state handle.

This function instantiates CAAM RNG state handle. The function is blocking and returns after CAAM has processed the request.

Parameters:

• base – CAAM peripheral base address

• handle – CAAM jobRing used for this request

• stateHandle – RNG state handle to instantiate

• config – Pointer to configuration structure.

Returns:

Status of the request

status_t CAAM_RNG_Deinit(CAAM_Type *base, caam_handle_t *handle, caam_rng_state_handle_t stateHandle)

Uninstantiate the CAAM RNG state handle.

This function uninstantiates CAAM RNG state handle. The function is blocking and returns after CAAM has processed the request.

Parameters:

• base – CAAM peripheral base address

• handle – jobRing used for this request.

• stateHandle – RNG state handle to uninstantiate

Returns:

Status of the request

status_t CAAM_RNG_GenerateSecureKey(CAAM_Type *base, caam_handle_t *handle, caam_rng_generic256_t additionalEntropy)

Generate Secure Key.

This function generates random data writes it to Secure Key registers. The function is blocking and returns after CAAM has processed the request. RNG state handle 0 is always used.

Parameters:

• base – CAAM peripheral base address

• handle – jobRing used for this request

• additionalEntropy – NULL or Pointer to optional 256-bit additional entropy.

Returns:

Status of the request

status_t CAAM_RNG_Reseed(CAAM_Type *base, caam_handle_t *handle, caam_rng_state_handle_t stateHandle, caam_rng_generic256_t additionalEntropy)

Reseed the CAAM RNG state handle.

This function reseeds the CAAM RNG state handle. For a state handle in nondeterministic mode, the DRNG is seeded with 384 bits of entropy from the TRNG and an optional 256-bit additional input from the descriptor via the Class 1 Context Register.

The function is blocking and returns after CAAM has processed the request.

Parameters:

• base – CAAM peripheral base address

• handle – jobRing used for this request

• stateHandle – RNG state handle to reseed

• additionalEntropy – NULL or Pointer to optional 256-bit additional entropy.

Returns:

Status of the request

status_t CAAM_RNG_GetRandomData(CAAM_Type *base, caam_handle_t *handle, caam_rng_state_handle_t stateHandle, uint8_t *data, size_t dataSize, caam_rng_random_type_t dataType, caam_rng_generic256_t additionalEntropy)

Get random data.

This function gets random data from CAAM RNG.

The function is blocking and returns after CAAM has generated the requested data or an error occurred.

Parameters:

• base – CAAM peripheral base address

• handle – jobRing used for this request

• stateHandle – RNG state handle used to generate random data

• data – [out] Pointer address used to store random data

• dataSize – Size of the buffer pointed by the data parameter

• dataType – Type of random data to be generated

• additionalEntropy – NULL or Pointer to optional 256-bit additional entropy.

Returns:

Status of the request

struct _caam_rng_user_config

#include <fsl_caam.h>

CAAM RNG configuration.

Public Members

uint32_t autoReseedInterval

Automatic reseed internal. If set to zero, CAAM RNG will use hardware default interval of 10.000.000 generate requests.

caam_rng_generic256_t *personalString

NULL or pointer to optional personalization string

CAAM Blocking APIs

CAAM Non-blocking APIs

CAAM Non-blocking AES driver

status_t CAAM_AES_EncryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_ecb_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *key, size_t keySize)

Encrypts AES using the ECB block mode.

Puts AES ECB encrypt descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• plaintext – Input plain text to encrypt

• descriptor – [out] Memory for the CAAM descriptor.

• ciphertext – [out] Output cipher text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from job descriptor push

status_t CAAM_AES_DecryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_ecb_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *key, size_t keySize)

Decrypts AES using ECB block mode.

Puts AES ECB decrypt descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• key – Input key.

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from job descriptor push

status_t CAAM_AES_EncryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_cbc_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *iv, const uint8_t *key, size_t keySize)

Encrypts AES using CBC block mode.

Puts AES CBC encrypt descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• iv – Input initial vector to combine with the first input block.

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from job descriptor push

status_t CAAM_AES_DecryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_cbc_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *iv, const uint8_t *key, size_t keySize)

Decrypts AES using CBC block mode.

Puts AES CBC decrypt descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text

• size – Size of input and output data in bytes. Must be multiple of 16 bytes.

• iv – Input initial vector to combine with the first input block.

• key – Input key to use for decryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

Returns:

Status from job descriptor push

status_t CAAM_AES_CryptCtrNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_ctr_t descriptor, const uint8_t *input, uint8_t *output, size_t size, uint8_t *counter, const uint8_t *key, size_t keySize, uint8_t *counterlast, size_t *szLeft)

Encrypts or decrypts AES using CTR block mode.

Encrypts or decrypts AES using CTR block mode. AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. The only difference between encryption and decryption is that, for encryption, the input argument is plain text and the output argument is cipher text. For decryption, the input argument is cipher text and the output argument is plain text.

Puts AES CTR crypt descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• input – Input data for CTR block mode

• output – [out] Output data for CTR block mode

• size – Size of input and output data in bytes

• counter – [inout] Input counter (updates on return)

• key – Input key to use for forward AES cipher

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• counterlast – [out] Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are not used.

• szLeft – [out] Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls are not used.

Returns:

Status from job descriptor push

status_t CAAM_AES_EncryptTagCcmNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_ccm_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, uint8_t *tag, size_t tagSize)

Encrypts AES and tags using CCM block mode.

Puts AES CCM encrypt and tag descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text.

• size – Size of input and output data in bytes. Zero means authentication only.

• iv – Nonce

• ivSize – Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.

• aad – Input additional authentication data. Can be NULL if aadSize is zero.

• aadSize – Input size in bytes of AAD. Zero means data mode only (authentication skipped).

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – [out] Generated output tag. Set to NULL to skip tag processing.

• tagSize – Input size of the tag to generate, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16.

Returns:

Status from job descriptor push

status_t CAAM_AES_DecryptTagCcmNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_ccm_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, const uint8_t *tag, size_t tagSize)

Decrypts AES and authenticates using CCM block mode.

Puts AES CCM decrypt and check tag descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text.

• size – Size of input and output data in bytes. Zero means authentication data only.

• iv – Nonce

• ivSize – Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.

• aad – Input additional authentication data. Can be NULL if aadSize is zero.

• aadSize – Input size in bytes of AAD. Zero means data mode only (authentication data skipped).

• key – Input key to use for decryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – Received tag. Set to NULL to skip tag processing.

• tagSize – Input size of the received tag to compare with the computed tag, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16.

Returns:

Status from job descriptor push

status_t CAAM_AES_EncryptTagGcmNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_gcm_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, uint8_t *tag, size_t tagSize)

Encrypts AES and tags using GCM block mode.

Encrypts AES and optionally tags using GCM block mode. If plaintext is NULL, only the GHASH is calculated and output in the ‘tag’ field. Puts AES GCM encrypt and tag descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• plaintext – Input plain text to encrypt

• ciphertext – [out] Output cipher text.

• size – Size of input and output data in bytes

• iv – Input initial vector

• ivSize – Size of the IV

• aad – Input additional authentication data

• aadSize – Input size in bytes of AAD

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – [out] Output hash tag. Set to NULL to skip tag processing.

• tagSize – Input size of the tag to generate, in bytes. Must be 4,8,12,13,14,15 or 16.

Returns:

Status from job descriptor push

status_t CAAM_AES_DecryptTagGcmNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_aes_gcm_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t *iv, size_t ivSize, const uint8_t *aad, size_t aadSize, const uint8_t *key, size_t keySize, const uint8_t *tag, size_t tagSize)

Decrypts AES and authenticates using GCM block mode.

Decrypts AES and optionally authenticates using GCM block mode. If ciphertext is NULL, only the GHASH is calculated and compared with the received GHASH in ‘tag’ field. Puts AES GCM decrypt and check tag descriptor to CAAM input job ring.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] Memory for the CAAM descriptor.

• ciphertext – Input cipher text to decrypt

• plaintext – [out] Output plain text.

• size – Size of input and output data in bytes

• iv – Input initial vector

• ivSize – Size of the IV

• aad – Input additional authentication data

• aadSize – Input size in bytes of AAD

• key – Input key to use for encryption

• keySize – Size of the input key, in bytes. Must be 16, 24, or 32.

• tag – Input hash tag to compare. Set to NULL to skip tag processing.

• tagSize – Input size of the tag, in bytes. Must be 4, 8, 12, 13, 14, 15, or 16.

Returns:

Status from job descriptor push

CAAM Non-blocking DES driver

status_t CAAM_DES_EncryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key[8U])

Encrypts DES using ECB block mode.

Encrypts DES using ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key – Input key to use for encryption

Returns:

Status from descriptor push

status_t CAAM_DES_DecryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key[8U])

Decrypts DES using ECB block mode.

Decrypts DES using ECB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key – Input key to use for decryption

Returns:

Status from descriptor push

status_t CAAM_DES_EncryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using CBC block mode.

Encrypts DES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Ouput ciphertext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key – Input key to use for encryption

Returns:

Status from descriptor push

status_t CAAM_DES_DecryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using CBC block mode.

Decrypts DES using CBC block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key – Input key to use for decryption

Returns:

Status from descriptor push

status_t CAAM_DES_EncryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using CFB block mode.

Encrypts DES using CFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• size – Size of input data in bytes

• iv – Input initial block.

• key – Input key to use for encryption

• ciphertext – [out] Output ciphertext

Returns:

Status from descriptor push

status_t CAAM_DES_DecryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using CFB block mode.

Decrypts DES using CFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key – Input key to use for decryption

Returns:

Status from descriptor push

status_t CAAM_DES_EncryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Encrypts DES using OFB block mode.

Encrypts DES using OFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key – Input key to use for encryption

Returns:

Status from descriptor push

status_t CAAM_DES_DecryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key[8U])

Decrypts DES using OFB block mode.

Decrypts DES using OFB block mode.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key – Input key to use for decryption

Returns:

Status from descriptor push

status_t CAAM_DES2_EncryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using ECB block mode with two keys.

Encrypts triple DES using ECB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_DecryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using ECB block mode with two keys.

Decrypts triple DES using ECB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_EncryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using CBC block mode with two keys.

Encrypts triple DES using CBC block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_DecryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using CBC block mode with two keys.

Decrypts triple DES using CBC block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_EncryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using CFB block mode with two keys.

Encrypts triple DES using CFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_DecryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using CFB block mode with two keys.

Decrypts triple DES using CFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_EncryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Encrypts triple DES using OFB block mode with two keys.

Encrypts triple DES using OFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES2_DecryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U])

Decrypts triple DES using OFB block mode with two keys.

Decrypts triple DES using OFB block mode with two keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_EncryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using ECB block mode with three keys.

Encrypts triple DES using ECB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_DecryptEcbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using ECB block mode with three keys.

Decrypts triple DES using ECB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes. Must be multiple of 8 bytes.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_EncryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using CBC block mode with three keys.

Encrypts triple DES using CBC block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_DecryptCbcNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using CBC block mode with three keys.

Decrypts triple DES using CBC block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input initial vector to combine with the first plaintext block. The iv does not need to be secret, but it must be unpredictable.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_EncryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using CFB block mode with three keys.

Encrypts triple DES using CFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and ouput data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_DecryptCfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using CFB block mode with three keys.

Decrypts triple DES using CFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input data in bytes

• iv – Input initial block.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_EncryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Encrypts triple DES using OFB block mode with three keys.

Encrypts triple DES using OFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• plaintext – Input plaintext to encrypt

• ciphertext – [out] Output ciphertext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

status_t CAAM_DES3_DecryptOfbNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_cipher_des_t descriptor, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[8], const uint8_t key1[8U], const uint8_t key2[8U], const uint8_t key3[8U])

Decrypts triple DES using OFB block mode with three keys.

Decrypts triple DES using OFB block mode with three keys.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request. Specifies jobRing.

• descriptor – [out] memory for CAAM commands

• ciphertext – Input ciphertext to decrypt

• plaintext – [out] Output plaintext

• size – Size of input and output data in bytes

• iv – Input unique input vector. The OFB mode requires that the IV be unique for each execution of the mode under the given key.

• key1 – First input key for key bundle

• key2 – Second input key for key bundle

• key3 – Third input key for key bundle

Returns:

Status from descriptor push

CAAM Non-blocking HASH driver

status_t CAAM_HASH_UpdateNonBlocking(caam_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)

Add input address and size to input data table.

Add data input pointer to a table maintained internally in the context. Each call of this function creates one entry in the table. The entry consists of the input pointer and inputSize. All entries created by one or multiple calls of this function can be processed in one call to CAAM_HASH_FinishNonBlocking() function. Individual entries can point to non-continuous data in the memory. The processing will occur in the order in which the CAAM_HASH_UpdateNonBlocking() have been called.

Memory pointers will be later accessed by CAAM (at time of CAAM_HASH_FinishNonBlocking()), so the memory must stay valid until CAAM_HASH_FinishNonBlocking() has been called and CAAM completes the processing.

Parameters:

• ctx – [inout] HASH context

• input – Input data

• inputSize – Size of input data in bytes

Returns:

Status of the hash update operation

status_t CAAM_HASH_FinishNonBlocking(caam_hash_ctx_t *ctx, caam_desc_hash_t descriptor, uint8_t *output, size_t *outputSize)

Finalize hashing.

The actual algorithm is computed with all input data, the memory pointers are accessed by CAAM after the function returns. The input data chunks have been specified by prior calls to CAAM_HASH_UpdateNonBlocking(). The function schedules the request at CAAM, then returns. After a while, when the CAAM completes processing of the input data chunks, the result is written to the output[] array, outputSize is written and the context is cleared.

Parameters:

• ctx – [inout] Input hash context

• descriptor – [out] Memory for the CAAM descriptor.

• output – [out] Output hash data

• outputSize – [out] Output parameter storing the size of the output hash in bytes

Returns:

Status of the hash finish operation

status_t CAAM_HASH_NonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_hash_t descriptor, caam_hash_algo_t algo, const uint8_t *input, size_t inputSize, const uint8_t *key, size_t keySize, uint8_t *output, size_t *outputSize)

Create HASH on given data.

Perform the full keyed XCBC-MAC/CMAC or SHA in one function call.

Key shall be supplied if the underlaying algoritm is AES XCBC-MAC or CMAC. Key shall be NULL if the underlaying algoritm is SHA.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For MDHA the key length argument is ignored.

The function is non-blocking. The request is scheduled at CAAM.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• descriptor – [out] Memory for the CAAM descriptor.

• algo – Underlaying algorithm to use for hash computation.

• input – Input data

• inputSize – Size of input data in bytes

• key – Input key (NULL if underlaying algorithm is SHA)

• keySize – Size of input key in bytes

• output – [out] Output hash data

• outputSize – [out] Output parameter storing the size of the output hash in bytes

Returns:

Status of the one call hash operation.

Caam_nonblocking_driver_hmac

status_t CAAM_HMAC_NonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_desc_hash_t descriptor, caam_hash_algo_t algo, const uint8_t *input, size_t inputSize, const uint8_t *key, size_t keySize, uint8_t *output, size_t *outputSize)

Create Message Authentication Code (MAC) on given data.

Perform the full keyed XCBC-MAC/CMAC, or HMAC-SHA in one function call.

Key shall be supplied if the underlaying algoritm is AES XCBC-MAC, CMAC, or SHA HMAC.

For XCBC-MAC, the key length must be 16. For CMAC, the key length can be the AES key lengths supported by AES engine. For HMAC, the key can have any size, however the function will block if the supplied key is bigger than the block size of the underlying hashing algorithm (e.g. >64 bytes for SHA256).

The function is not blocking with the exception of supplying large key sizes. In that case the function will block until the large key is hashed down with the supplied hashing algorithm (as per FIPS 198-1), after which operation is resumed to calling non-blocking HMAC.

Parameters:

• base – CAAM peripheral base address

• handle – Handle used for this request.

• descriptor – [out] Memory for the CAAM descriptor.

• algo – Underlaying algorithm to use for MAC computation.

• input – Input data

• inputSize – Size of input data in bytes

• key – Input key

• keySize – Size of input key in bytes

• output – [out] Output MAC data

• outputSize – [out] Output parameter storing the size of the output MAC in bytes

Returns:

Status of the one call hash operation.

CAAM Non-blocking RNG driver

status_t CAAM_RNG_GetRandomDataNonBlocking(CAAM_Type *base, caam_handle_t *handle, caam_rng_state_handle_t stateHandle, caam_desc_rng_t descriptor, void *data, size_t dataSize, caam_rng_random_type_t dataType, caam_rng_generic256_t additionalEntropy)

Request random data.

This function schedules the request for random data from CAAM RNG. Memory at memory pointers will be accessed by CAAM shortly after this function returns, according to actual CAAM schedule.

Parameters:

• base – CAAM peripheral base address

• handle – RNG handle used for this request

• stateHandle – RNG state handle used to generate random data

• descriptor – [out] memory for CAAM commands

• data – [out] Pointer address used to store random data

• dataSize – Size of the buffer pointed by the data parameter, in bytes.

• dataType – Type of random data to be generated.

• additionalEntropy – NULL or Pointer to optional 256-bit additional entropy.

Returns:

status of the request

CACHE: ARMV7-M7 CACHE Memory Controller

static inline void L1CACHE_EnableICache(void)

Enables cortex-m7 L1 instruction cache.

static inline void L1CACHE_DisableICache(void)

Disables cortex-m7 L1 instruction cache.

static inline void L1CACHE_InvalidateICache(void)

Invalidate cortex-m7 L1 instruction cache.

void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)

Invalidate cortex-m7 L1 instruction cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

static inline void L1CACHE_EnableDCache(void)

Enables cortex-m7 L1 data cache.

static inline void L1CACHE_DisableDCache(void)

Disables cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCache(void)

Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_CleanDCache(void)

Cleans cortex-m7 L1 data cache.

static inline void L1CACHE_CleanInvalidateDCache(void)

Cleans and Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be cleaned.

• size_byte – The memory size.

static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be clean and invalidated.

• size_byte – The memory size.

void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be cleaned.

void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be cleaned and invalidated.

FSL_CACHE_DRIVER_VERSION

cache driver version 2.0.4.

CACHE: LMEM CACHE Memory Controller

void L1CACHE_EnableCodeCache(void)

Enables the processor code bus cache.

void L1CACHE_DisableCodeCache(void)

Disables the processor code bus cache.

void L1CACHE_InvalidateCodeCache(void)

Invalidates the processor code bus cache.

void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates processor code bus cache by range.

Note

Address and size should be aligned to “L1CODCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be invalidated.

void L1CACHE_CleanCodeCache(void)

Cleans the processor code bus cache.

void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte)

Cleans processor code bus cache by range.

Note

Address and size should be aligned to “L1CODEBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be cleaned.

void L1CACHE_CleanInvalidateCodeCache(void)

Cleans and invalidates the processor code bus cache.

void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and invalidate processor code bus cache by range.

Note

Address and size should be aligned to “L1CODEBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be Cleaned and Invalidated.

static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)

Enables/disables the processor code bus write buffer.

Parameters:

• enable – The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_EnableSystemCache(void)

Enables the processor system bus cache.

void L1CACHE_DisableSystemCache(void)

Disables the processor system bus cache.

void L1CACHE_InvalidateSystemCache(void)

Invalidates the processor system bus cache.

void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates processor system bus cache by range.

Note

Address and size should be aligned to “L1SYSTEMBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be invalidated.

void L1CACHE_CleanSystemCache(void)

Cleans the processor system bus cache.

void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte)

Cleans processor system bus cache by range.

Note

Address and size should be aligned to “L1SYSTEMBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be cleaned.

void L1CACHE_CleanInvalidateSystemCache(void)

Cleans and invalidates the processor system bus cache.

void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates processor system bus cache by range.

Note

Address and size should be aligned to “L1SYSTEMBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address of cache.

• size_byte – size of the memory to be Clean and Invalidated.

static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)

Enables/disables the processor system bus write buffer.

Parameters:

• enable – The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m4 L1 instrument cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

• address – The start address of the memory to be cleaned.

• size_byte – The memory size.

void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

• address – The start address of the memory to be clean and invalidated.

• size_byte – The memory size.

static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates instruction cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates data cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Clean data cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be cleaned.

static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates data cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be Cleaned and Invalidated.

FSL_CACHE_DRIVER_VERSION

cache driver version.

L1CODEBUSCACHE_LINESIZE_BYTE

code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too.

The code bus CACHE line size is 16B = 128b.

L1SYSTEMBUSCACHE_LINESIZE_BYTE

The system bus CACHE line size is 16B = 128b.

CDOG

status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)

Initialize CDOG.

This function initializes CDOG block and setting.

Parameters:

• base – CDOG peripheral base address

• conf – CDOG configuration structure

Returns:

Status of the init operation

void CDOG_Deinit(CDOG_Type *base)

Deinitialize CDOG.

This function deinitializes CDOG secure counter.

Parameters:

• base – CDOG peripheral base address

void CDOG_GetDefaultConfig(cdog_config_t *conf)

Sets the default configuration of CDOG.

This function initialize CDOG config structure to default values.

Parameters:

• conf – CDOG configuration structure

void CDOG_Stop(CDOG_Type *base, uint32_t stop)

Stops secure counter and instruction timer.

This function stops instruction timer and secure counter. This also change state od CDOG to IDLE.

Parameters:

• base – CDOG peripheral base address

• stop – expected value which will be compared with value of secure counter

void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in RELOAD and START registers for instruction timer and secure counter

Parameters:

• base – CDOG peripheral base address

• reload – reload value

• start – start value

void CDOG_Check(CDOG_Type *base, uint32_t check)

Checks secure counter.

This function compares stop value in handler with secure counter value by writting to RELOAD refister.

Parameters:

• base – CDOG peripheral base address

• check – expected (stop) value

void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in STOP, RELOAD and START registers for instruction timer and secure counter.

Parameters:

• base – CDOG peripheral base address

• stop – expected value which will be compared with value of secure counter

• reload – reload value for instruction timer

• start – start value for secure timer

void CDOG_Add(CDOG_Type *base, uint32_t add)

Add value to secure counter.

This function add specified value to secure counter.

Parameters:

• base – CDOG peripheral base address.

• add – Value to be added.

void CDOG_Add1(CDOG_Type *base)

Add 1 to secure counter.

This function add 1 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Add16(CDOG_Type *base)

Add 16 to secure counter.

This function add 16 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Add256(CDOG_Type *base)

Add 256 to secure counter.

This function add 256 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub(CDOG_Type *base, uint32_t sub)

brief Substract value to secure counter

This function substract specified value to secure counter.

param base CDOG peripheral base address. param sub Value to be substracted.

void CDOG_Sub1(CDOG_Type *base)

Substract 1 from secure counter.

This function substract specified 1 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub16(CDOG_Type *base)

Substract 16 from secure counter.

This function substract specified 16 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub256(CDOG_Type *base)

Substract 256 from secure counter.

This function substract specified 256 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)

Set the CDOG persistent word.

Parameters:

• base – CDOG peripheral base address.

• value – The value to be written.

uint32_t CDOG_ReadPersistent(CDOG_Type *base)

Get the CDOG persistent word.

Parameters:

• base – CDOG peripheral base address.

Returns:

The persistent word.

FSL_CDOG_DRIVER_VERSION

Defines CDOG driver version 2.1.3.

Change log:

• Version 2.1.3

  • Re-design multiple instance IRQs and Clocks

  • Add fix for RESTART command errata

• Version 2.1.2

  • Support multiple IRQs

  • Fix default CONTROL values

• Version 2.1.1

  • Remove bit CONTROL[CONTROL_CTRL]

• Version 2.1.0

  • Rename CWT to CDOG

• Version 2.0.2

  • Fix MISRA-2012 issues

• Version 2.0.1

  • Fix doxygen issues

• Version 2.0.0

  • initial version

enum __cdog_debug_Action_ctrl_enum

Values:

enumerator kCDOG_DebugHaltCtrl_Run

enumerator kCDOG_DebugHaltCtrl_Pause

enum __cdog_irq_pause_ctrl_enum

Values:

enumerator kCDOG_IrqPauseCtrl_Run

enumerator kCDOG_IrqPauseCtrl_Pause

enum __cdog_fault_ctrl_enum

Values:

enumerator kCDOG_FaultCtrl_EnableReset

enumerator kCDOG_FaultCtrl_EnableInterrupt

enumerator kCDOG_FaultCtrl_NoAction

enum __code_lock_ctrl_enum

Values:

enumerator kCDOG_LockCtrl_Lock

enumerator kCDOG_LockCtrl_Unlock

typedef uint32_t secure_counter_t

SC_ADD(add)

SC_ADD1

SC_ADD16

SC_ADD256

SC_SUB(sub)

SC_SUB1

SC_SUB16

SC_SUB256

SC_CHECK(val)

struct cdog_config_t

#include <fsl_cdog.h>

Clock Driver

enum _clock_lpcg

Clock LPCG index.

Values:

enumerator kCLOCK_M7

Clock LPCG M7.

enumerator kCLOCK_M4

Clock LPCG M4.

enumerator kCLOCK_Sim_M7

Clock LPCG SIM M7.

enumerator kCLOCK_Sim_M

Clock LPCG SIM M4.

enumerator kCLOCK_Sim_Disp

Clock LPCG SIM DISP.

enumerator kCLOCK_Sim_Per

Clock LPCG SIM PER.

enumerator kCLOCK_Sim_Lpsr

Clock LPCG SIM LPSR.

enumerator kCLOCK_Anadig

Clock LPCG Anadig.

enumerator kCLOCK_Dcdc

Clock LPCG DCDC.

enumerator kCLOCK_Src

Clock LPCG SRC.

enumerator kCLOCK_Ccm

Clock LPCG CCM.

enumerator kCLOCK_Gpc

Clock LPCG GPC.

enumerator kCLOCK_Ssarc

Clock LPCG SSARC.

enumerator kCLOCK_Sim_R

Clock LPCG SIM_R.

enumerator kCLOCK_Wdog1

Clock LPCG WDOG1.

enumerator kCLOCK_Wdog2

Clock LPCG WDOG2.

enumerator kCLOCK_Wdog3

Clock LPCG WDOG3.

enumerator kCLOCK_Wdog4

Clock LPCG WDOG4.

enumerator kCLOCK_Ewm0

Clock LPCG EWM0.

enumerator kCLOCK_Sema

Clock LPCG SEMA.

enumerator kCLOCK_Mu_A

Clock LPCG MU_A.

enumerator kCLOCK_Mu_B

Clock LPCG MU_B.

enumerator kCLOCK_Edma

Clock LPCG EDMA.

enumerator kCLOCK_Edma_Lpsr

Clock LPCG EDMA_LPSR.

enumerator kCLOCK_Romcp

Clock LPCG ROMCP.

enumerator kCLOCK_Ocram

Clock LPCG OCRAM.

enumerator kCLOCK_Flexram

Clock LPCG FLEXRAM.

enumerator kCLOCK_Lmem

Clock LPCG Lmem.

enumerator kCLOCK_Flexspi1

Clock LPCG Flexspi1.

enumerator kCLOCK_Flexspi2

Clock LPCG Flexspi2.

enumerator kCLOCK_Rdc

Clock LPCG RDC.

enumerator kCLOCK_M7_Xrdc

Clock LPCG M7 XRDC.

enumerator kCLOCK_M4_Xrdc

Clock LPCG M4 XRDC.

enumerator kCLOCK_Semc

Clock LPCG SEMC.

enumerator kCLOCK_Xecc

Clock LPCG XECC.

enumerator kCLOCK_Iee

Clock LPCG IEE.

enumerator kCLOCK_Key_Manager

Clock LPCG KEY_MANAGER.

enumerator kCLOCK_Puf

Clock LPCG PUF.

enumerator kCLOCK_Ocotp

Clock LPCG OSOTP.

enumerator kCLOCK_Snvs_Hp

Clock LPCG SNVS_HP.

enumerator kCLOCK_Snvs

Clock LPCG SNVS.

enumerator kCLOCK_Caam

Clock LPCG Caam.

enumerator kCLOCK_Jtag_Mux

Clock LPCG JTAG_MUX.

enumerator kCLOCK_Cstrace

Clock LPCG CSTRACE.

enumerator kCLOCK_Xbar1

Clock LPCG XBAR1.

enumerator kCLOCK_Xbar2

Clock LPCG XBAR2.

enumerator kCLOCK_Xbar3

Clock LPCG XBAR3.

enumerator kCLOCK_Aoi1

Clock LPCG AOI1.

enumerator kCLOCK_Aoi2

Clock LPCG AOI2.

enumerator kCLOCK_Adc_Etc

Clock LPCG ADC_ETC.

enumerator kCLOCK_Iomuxc

Clock LPCG IOMUXC.

enumerator kCLOCK_Iomuxc_Lpsr

Clock LPCG IOMUXC_LPSR.

enumerator kCLOCK_Gpio

Clock LPCG GPIO.

enumerator kCLOCK_Kpp

Clock LPCG KPP.

enumerator kCLOCK_Flexio1

Clock LPCG FLEXIO1.

enumerator kCLOCK_Flexio2

Clock LPCG FLEXIO2.

enumerator kCLOCK_Lpadc1

Clock LPCG LPADC1.

enumerator kCLOCK_Lpadc2

Clock LPCG LPADC2.

enumerator kCLOCK_Dac

Clock LPCG DAC.

enumerator kCLOCK_Acmp1

Clock LPCG ACMP1.

enumerator kCLOCK_Acmp2

Clock LPCG ACMP2.

enumerator kCLOCK_Acmp3

Clock LPCG ACMP3.

enumerator kCLOCK_Acmp4

Clock LPCG ACMP4.

enumerator kCLOCK_Pit1

Clock LPCG PIT1.

enumerator kCLOCK_Pit2

Clock LPCG PIT2.

enumerator kCLOCK_Gpt1

Clock LPCG GPT1.

enumerator kCLOCK_Gpt2

Clock LPCG GPT2.

enumerator kCLOCK_Gpt3

Clock LPCG GPT3.

enumerator kCLOCK_Gpt4

Clock LPCG GPT4.

enumerator kCLOCK_Gpt5

Clock LPCG GPT5.

enumerator kCLOCK_Gpt6

Clock LPCG GPT6.

enumerator kCLOCK_Qtimer1

Clock LPCG QTIMER1.

enumerator kCLOCK_Qtimer2

Clock LPCG QTIMER2.

enumerator kCLOCK_Qtimer3

Clock LPCG QTIMER3.

enumerator kCLOCK_Qtimer4

Clock LPCG QTIMER4.

enumerator kCLOCK_Enc1

Clock LPCG Enc1.

enumerator kCLOCK_Enc2

Clock LPCG Enc2.

enumerator kCLOCK_Enc3

Clock LPCG Enc3.

enumerator kCLOCK_Enc4

Clock LPCG Enc4.

enumerator kCLOCK_Hrtimer

Clock LPCG Hrtimer.

enumerator kCLOCK_Pwm1

Clock LPCG PWM1.

enumerator kCLOCK_Pwm2

Clock LPCG PWM2.

enumerator kCLOCK_Pwm3

Clock LPCG PWM3.

enumerator kCLOCK_Pwm4

Clock LPCG PWM4.

enumerator kCLOCK_Can1

Clock LPCG CAN1.

enumerator kCLOCK_Can2

Clock LPCG CAN2.

enumerator kCLOCK_Can3

Clock LPCG CAN3.

enumerator kCLOCK_Lpuart1

Clock LPCG LPUART1.

enumerator kCLOCK_Lpuart2

Clock LPCG LPUART2.

enumerator kCLOCK_Lpuart3

Clock LPCG LPUART3.

enumerator kCLOCK_Lpuart4

Clock LPCG LPUART4.

enumerator kCLOCK_Lpuart5

Clock LPCG LPUART5.

enumerator kCLOCK_Lpuart6

Clock LPCG LPUART6.

enumerator kCLOCK_Lpuart7

Clock LPCG LPUART7.

enumerator kCLOCK_Lpuart8

Clock LPCG LPUART8.

enumerator kCLOCK_Lpuart9

Clock LPCG LPUART9.

enumerator kCLOCK_Lpuart10

Clock LPCG LPUART10.

enumerator kCLOCK_Lpuart11

Clock LPCG LPUART11.

enumerator kCLOCK_Lpuart12

Clock LPCG LPUART12.

enumerator kCLOCK_Lpi2c1

Clock LPCG LPI2C1.

enumerator kCLOCK_Lpi2c2

Clock LPCG LPI2C2.

enumerator kCLOCK_Lpi2c3

Clock LPCG LPI2C3.

enumerator kCLOCK_Lpi2c4

Clock LPCG LPI2C4.

enumerator kCLOCK_Lpi2c5

Clock LPCG LPI2C5.

enumerator kCLOCK_Lpi2c6

Clock LPCG LPI2C6.

enumerator kCLOCK_Lpspi1

Clock LPCG LPSPI1.

enumerator kCLOCK_Lpspi2

Clock LPCG LPSPI2.

enumerator kCLOCK_Lpspi3

Clock LPCG LPSPI3.

enumerator kCLOCK_Lpspi4

Clock LPCG LPSPI4.

enumerator kCLOCK_Lpspi5

Clock LPCG LPSPI5.

enumerator kCLOCK_Lpspi6

Clock LPCG LPSPI6.

enumerator kCLOCK_Sim1

Clock LPCG SIM1.

enumerator kCLOCK_Sim2

Clock LPCG SIM2.

enumerator kCLOCK_Enet

Clock LPCG ENET.

enumerator kCLOCK_Enet_1g

Clock LPCG ENET 1G.

enumerator kCLOCK_Enet_Qos

Clock LPCG ENET QOS.

enumerator kCLOCK_Usb

Clock LPCG USB.

enumerator kCLOCK_Cdog

Clock LPCG CDOG.

enumerator kCLOCK_Usdhc1

Clock LPCG USDHC1.

enumerator kCLOCK_Usdhc2

Clock LPCG USDHC2.

enumerator kCLOCK_Asrc

Clock LPCG ASRC.

enumerator kCLOCK_Mqs

Clock LPCG MQS.

enumerator kCLOCK_Pdm

Clock LPCG PDM.

enumerator kCLOCK_Spdif

Clock LPCG SPDIF.

enumerator kCLOCK_Sai1

Clock LPCG SAI1.

enumerator kCLOCK_Sai2

Clock LPCG SAI2.

enumerator kCLOCK_Sai3

Clock LPCG SAI3.

enumerator kCLOCK_Sai4

Clock LPCG SAI4.

enumerator kCLOCK_Pxp

Clock LPCG PXP.

enumerator kCLOCK_Gpu2d

Clock LPCG GPU2D.

enumerator kCLOCK_Lcdif

Clock LPCG LCDIF.

enumerator kCLOCK_Lcdifv2

Clock LPCG LCDIFV2.

enumerator kCLOCK_Mipi_Dsi

Clock LPCG MIPI DSI.

enumerator kCLOCK_Mipi_Csi

Clock LPCG MIPI CSI.

enumerator kCLOCK_Csi

Clock LPCG CSI.

enumerator kCLOCK_Dcic_Mipi

Clock LPCG DCIC MIPI.

enumerator kCLOCK_Dcic_Lcd

Clock LPCG DCIC LCD.

enumerator kCLOCK_Video_Mux

Clock LPCG VIDEO MUX.

enumerator kCLOCK_Uniq_Edt_I

Clock LPCG Uniq_Edt_I.

enumerator kCLOCK_IpInvalid

Invalid value.

enum _clock_name

Clock name.

Values:

enumerator kCLOCK_OscRc16M

16MHz RC Oscillator.

enumerator kCLOCK_OscRc48M

48MHz RC Oscillator.

enumerator kCLOCK_OscRc48MDiv2

48MHz RC Oscillator Div2.

enumerator kCLOCK_OscRc400M

400MHz RC Oscillator.

enumerator kCLOCK_Osc24M

24MHz Oscillator.

enumerator kCLOCK_Osc24MOut

48MHz Oscillator Out.

enumerator kCLOCK_ArmPll

ARM PLL.

enumerator kCLOCK_ArmPllOut

ARM PLL Out.

enumerator kCLOCK_SysPll2

SYS PLL2.

enumerator kCLOCK_SysPll2Out

SYS PLL2 OUT.

enumerator kCLOCK_SysPll2Pfd0

SYS PLL2 PFD0.

enumerator kCLOCK_SysPll2Pfd1

SYS PLL2 PFD1.

enumerator kCLOCK_SysPll2Pfd2

SYS PLL2 PFD2.

enumerator kCLOCK_SysPll2Pfd3

SYS PLL2 PFD3.

enumerator kCLOCK_SysPll3

SYS PLL3.

enumerator kCLOCK_SysPll3Out

SYS PLL3 OUT.

enumerator kCLOCK_SysPll3Div2

SYS PLL3 DIV2

enumerator kCLOCK_SysPll3Pfd0

SYS PLL3 PFD0.

enumerator kCLOCK_SysPll3Pfd1

SYS PLL3 PFD1

enumerator kCLOCK_SysPll3Pfd2

SYS PLL3 PFD2

enumerator kCLOCK_SysPll3Pfd3

SYS PLL3 PFD3

enumerator kCLOCK_SysPll1

SYS PLL1.

enumerator kCLOCK_SysPll1Out

SYS PLL1 OUT.

enumerator kCLOCK_SysPll1Div2

SYS PLL1 DIV2.

enumerator kCLOCK_SysPll1Div5

SYS PLL1 DIV5.

enumerator kCLOCK_AudioPll

SYS AUDIO PLL.

enumerator kCLOCK_AudioPllOut

SYS AUDIO PLL OUT.

enumerator kCLOCK_VideoPll

SYS VIDEO PLL.

enumerator kCLOCK_VideoPllOut

SYS VIDEO PLL OUT.

enumerator kCLOCK_CpuClk

SYS CPU CLK.

enumerator kCLOCK_CoreSysClk

SYS CORE SYS CLK.

enum _clock_root

Root clock index.

Values:

enumerator kCLOCK_Root_M7

CLOCK Root M7.

enumerator kCLOCK_Root_M4

CLOCK Root M4.

enumerator kCLOCK_Root_Bus

CLOCK Root Bus.

enumerator kCLOCK_Root_Bus_Lpsr

CLOCK Root Bus Lpsr.

enumerator kCLOCK_Root_Semc

CLOCK Root Semc.

enumerator kCLOCK_Root_Cssys

CLOCK Root Cssys.

enumerator kCLOCK_Root_Cstrace

CLOCK Root Cstrace.

enumerator kCLOCK_Root_M4_Systick

CLOCK Root M4 Systick.

enumerator kCLOCK_Root_M7_Systick

CLOCK Root M7 Systick.

enumerator kCLOCK_Root_Adc1

CLOCK Root Adc1.

enumerator kCLOCK_Root_Adc2

CLOCK Root Adc2.

enumerator kCLOCK_Root_Acmp

CLOCK Root Acmp.

enumerator kCLOCK_Root_Flexio1

CLOCK Root Flexio1.

enumerator kCLOCK_Root_Flexio2

CLOCK Root Flexio2.

enumerator kCLOCK_Root_Gpt1

CLOCK Root Gpt1.

enumerator kCLOCK_Root_Gpt2

CLOCK Root Gpt2.

enumerator kCLOCK_Root_Gpt3

CLOCK Root Gpt3.

enumerator kCLOCK_Root_Gpt4

CLOCK Root Gpt4.

enumerator kCLOCK_Root_Gpt5

CLOCK Root Gpt5.

enumerator kCLOCK_Root_Gpt6

CLOCK Root Gpt6.

enumerator kCLOCK_Root_Flexspi1

CLOCK Root Flexspi1.

enumerator kCLOCK_Root_Flexspi2

CLOCK Root Flexspi2.

enumerator kCLOCK_Root_Can1

CLOCK Root Can1.

enumerator kCLOCK_Root_Can2

CLOCK Root Can2.

enumerator kCLOCK_Root_Can3

CLOCK Root Can3.

enumerator kCLOCK_Root_Lpuart1

CLOCK Root Lpuart1.

enumerator kCLOCK_Root_Lpuart2

CLOCK Root Lpuart2.

enumerator kCLOCK_Root_Lpuart3

CLOCK Root Lpuart3.

enumerator kCLOCK_Root_Lpuart4

CLOCK Root Lpuart4.

enumerator kCLOCK_Root_Lpuart5

CLOCK Root Lpuart5.

enumerator kCLOCK_Root_Lpuart6

CLOCK Root Lpuart6.

enumerator kCLOCK_Root_Lpuart7

CLOCK Root Lpuart7.

enumerator kCLOCK_Root_Lpuart8

CLOCK Root Lpuart8.

enumerator kCLOCK_Root_Lpuart9

CLOCK Root Lpuart9.

enumerator kCLOCK_Root_Lpuart10

CLOCK Root Lpuart10.

enumerator kCLOCK_Root_Lpuart11

CLOCK Root Lpuart11.

enumerator kCLOCK_Root_Lpuart12

CLOCK Root Lpuart12.

enumerator kCLOCK_Root_Lpi2c1

CLOCK Root Lpi2c1.

enumerator kCLOCK_Root_Lpi2c2

CLOCK Root Lpi2c2.

enumerator kCLOCK_Root_Lpi2c3

CLOCK Root Lpi2c3.

enumerator kCLOCK_Root_Lpi2c4

CLOCK Root Lpi2c4.

enumerator kCLOCK_Root_Lpi2c5

CLOCK Root Lpi2c5.

enumerator kCLOCK_Root_Lpi2c6

CLOCK Root Lpi2c6.

enumerator kCLOCK_Root_Lpspi1

CLOCK Root Lpspi1.

enumerator kCLOCK_Root_Lpspi2

CLOCK Root Lpspi2.

enumerator kCLOCK_Root_Lpspi3

CLOCK Root Lpspi3.

enumerator kCLOCK_Root_Lpspi4

CLOCK Root Lpspi4.

enumerator kCLOCK_Root_Lpspi5

CLOCK Root Lpspi5.

enumerator kCLOCK_Root_Lpspi6

CLOCK Root Lpspi6.

enumerator kCLOCK_Root_Emv1

CLOCK Root Emv1.

enumerator kCLOCK_Root_Emv2

CLOCK Root Emv2.

enumerator kCLOCK_Root_Enet1

CLOCK Root Enet1.

enumerator kCLOCK_Root_Enet2

CLOCK Root Enet2.

enumerator kCLOCK_Root_Enet_Qos

CLOCK Root Enet Qos.

enumerator kCLOCK_Root_Enet_25m

CLOCK Root Enet 25M.

enumerator kCLOCK_Root_Enet_Timer1

CLOCK Root Enet Timer1.

enumerator kCLOCK_Root_Enet_Timer2

CLOCK Root Enet Timer2.

enumerator kCLOCK_Root_Enet_Timer3

CLOCK Root Enet Timer3.

enumerator kCLOCK_Root_Usdhc1

CLOCK Root Usdhc1.

enumerator kCLOCK_Root_Usdhc2

CLOCK Root Usdhc2.

enumerator kCLOCK_Root_Asrc

CLOCK Root Asrc.

enumerator kCLOCK_Root_Mqs

CLOCK Root Mqs.

enumerator kCLOCK_Root_Mic

CLOCK Root MIC.

enumerator kCLOCK_Root_Spdif

CLOCK Root Spdif

enumerator kCLOCK_Root_Sai1

CLOCK Root Sai1.

enumerator kCLOCK_Root_Sai2

CLOCK Root Sai2.

enumerator kCLOCK_Root_Sai3

CLOCK Root Sai3.

enumerator kCLOCK_Root_Sai4

CLOCK Root Sai4.

enumerator kCLOCK_Root_Gc355

CLOCK Root Gc355.

enumerator kCLOCK_Root_Lcdif

CLOCK Root Lcdif.

enumerator kCLOCK_Root_Lcdifv2

CLOCK Root Lcdifv2.

enumerator kCLOCK_Root_Mipi_Ref

CLOCK Root Mipi Ref.

enumerator kCLOCK_Root_Mipi_Esc

CLOCK Root Mipi Esc.

enumerator kCLOCK_Root_Csi2

CLOCK Root Csi2.

enumerator kCLOCK_Root_Csi2_Esc

CLOCK Root Csi2 Esc.

enumerator kCLOCK_Root_Csi2_Ui

CLOCK Root Csi2 Ui.

enumerator kCLOCK_Root_Csi

CLOCK Root Csi.

enumerator kCLOCK_Root_Cko1

CLOCK Root CKo1.

enumerator kCLOCK_Root_Cko2

CLOCK Root CKo2.

enum _clock_root_mux_source

The enumerator of clock roots’ clock source mux value.

Values:

enumerator kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2

M7 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_M7_ClockRoot_MuxOsc24MOut

M7 mux from MuxOsc24MOut.

enumerator kCLOCK_M7_ClockRoot_MuxOscRc400M

M7 mux from MuxOscRc400M.

enumerator kCLOCK_M7_ClockRoot_MuxOscRc16M

M7 mux from MuxOscRc16M.

enumerator kCLOCK_M7_ClockRoot_MuxArmPllOut

M7 mux from MuxArmPllOut.

enumerator kCLOCK_M7_ClockRoot_MuxSysPll1Out

M7 mux from MuxSysPll1Out.

enumerator kCLOCK_M7_ClockRoot_MuxSysPll3Out

M7 mux from MuxSysPll3Out.

enumerator kCLOCK_M7_ClockRoot_MuxVideoPllOut

M7 mux from MuxVideoPllOut.

enumerator kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2

M4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_M4_ClockRoot_MuxOsc24MOut

M4 mux from MuxOsc24MOut.

enumerator kCLOCK_M4_ClockRoot_MuxOscRc400M

M4 mux from MuxOscRc400M.

enumerator kCLOCK_M4_ClockRoot_MuxOscRc16M

M4 mux from MuxOscRc16M.

enumerator kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3

M4 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_M4_ClockRoot_MuxSysPll3Out

M4 mux from MuxSysPll3Out.

enumerator kCLOCK_M4_ClockRoot_MuxSysPll2Out

M4 mux from MuxSysPll2Out.

enumerator kCLOCK_M4_ClockRoot_MuxSysPll1Div5

M4 mux from MuxSysPll1Div5.

enumerator kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2

BUS mux from MuxOscRc48MDiv2.

enumerator kCLOCK_BUS_ClockRoot_MuxOsc24MOut

BUS mux from MuxOsc24MOut.

enumerator kCLOCK_BUS_ClockRoot_MuxOscRc400M

BUS mux from MuxOscRc400M.

enumerator kCLOCK_BUS_ClockRoot_MuxOscRc16M

BUS mux from MuxOscRc16M.

enumerator kCLOCK_BUS_ClockRoot_MuxSysPll3Out

BUS mux from MuxSysPll3Out.

enumerator kCLOCK_BUS_ClockRoot_MuxSysPll1Div5

BUS mux from MuxSysPll1Div5.

enumerator kCLOCK_BUS_ClockRoot_MuxSysPll2Out

BUS mux from MuxSysPll2Out.

enumerator kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3

BUS mux from MuxSysPll2Pfd3.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2

BUS_LPSR mux from MuxOscRc48MDiv2.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut

BUS_LPSR mux from MuxOsc24MOut.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M

BUS_LPSR mux from MuxOscRc400M.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M

BUS_LPSR mux from MuxOscRc16M.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3

BUS_LPSR mux from MuxSysPll3Pfd3.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out

BUS_LPSR mux from MuxSysPll3Out.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out

BUS_LPSR mux from MuxSysPll2Out.

enumerator kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5

BUS_LPSR mux from MuxSysPll1Div5.

enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2

SEMC mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SEMC_ClockRoot_MuxOsc24MOut

SEMC mux from MuxOsc24MOut.

enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc400M

SEMC mux from MuxOscRc400M.

enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc16M

SEMC mux from MuxOscRc16M.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5

SEMC mux from MuxSysPll1Div5.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll2Out

SEMC mux from MuxSysPll2Out.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1

SEMC mux from MuxSysPll2Pfd1.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0

SEMC mux from MuxSysPll3Pfd0.

enumerator kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2

CSSYS mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut

CSSYS mux from MuxOsc24MOut.

enumerator kCLOCK_CSSYS_ClockRoot_MuxOscRc400M

CSSYS mux from MuxOscRc400M.

enumerator kCLOCK_CSSYS_ClockRoot_MuxOscRc16M

CSSYS mux from MuxOscRc16M.

enumerator kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2

CSSYS mux from MuxSysPll3Div2.

enumerator kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5

CSSYS mux from MuxSysPll1Div5.

enumerator kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out

CSSYS mux from MuxSysPll2Out.

enumerator kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3

CSSYS mux from MuxSysPll2Pfd3.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2

CSTRACE mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut

CSTRACE mux from MuxOsc24MOut.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M

CSTRACE mux from MuxOscRc400M.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M

CSTRACE mux from MuxOscRc16M.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2

CSTRACE mux from MuxSysPll3Div2.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5

CSTRACE mux from MuxSysPll1Div5.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1

CSTRACE mux from MuxSysPll2Pfd1.

enumerator kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out

CSTRACE mux from MuxSysPll2Out.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2

M4_SYSTICK mux from MuxOscRc48MDiv2.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut

M4_SYSTICK mux from MuxOsc24MOut.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M

M4_SYSTICK mux from MuxOscRc400M.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M

M4_SYSTICK mux from MuxOscRc16M.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3

M4_SYSTICK mux from MuxSysPll3Pfd3.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out

M4_SYSTICK mux from MuxSysPll3Out.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0

M4_SYSTICK mux from MuxSysPll2Pfd0.

enumerator kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5

M4_SYSTICK mux from MuxSysPll1Div5.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2

M7_SYSTICK mux from MuxOscRc48MDiv2.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut

M7_SYSTICK mux from MuxOsc24MOut.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M

M7_SYSTICK mux from MuxOscRc400M.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M

M7_SYSTICK mux from MuxOscRc16M.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out

M7_SYSTICK mux from MuxSysPll2Out.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2

M7_SYSTICK mux from MuxSysPll3Div2.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5

M7_SYSTICK mux from MuxSysPll1Div5.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0

M7_SYSTICK mux from MuxSysPll2Pfd0.

enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2

ADC1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ADC1_ClockRoot_MuxOsc24MOut

ADC1 mux from MuxOsc24MOut.

enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc400M

ADC1 mux from MuxOscRc400M.

enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc16M

ADC1 mux from MuxOscRc16M.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2

ADC1 mux from MuxSysPll3Div2.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5

ADC1 mux from MuxSysPll1Div5.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll2Out

ADC1 mux from MuxSysPll2Out.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3

ADC1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2

ADC2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ADC2_ClockRoot_MuxOsc24MOut

ADC2 mux from MuxOsc24MOut.

enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc400M

ADC2 mux from MuxOscRc400M.

enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc16M

ADC2 mux from MuxOscRc16M.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2

ADC2 mux from MuxSysPll3Div2.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5

ADC2 mux from MuxSysPll1Div5.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll2Out

ADC2 mux from MuxSysPll2Out.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3

ADC2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2

ACMP mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ACMP_ClockRoot_MuxOsc24MOut

ACMP mux from MuxOsc24MOut.

enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc400M

ACMP mux from MuxOscRc400M.

enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc16M

ACMP mux from MuxOscRc16M.

enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll3Out

ACMP mux from MuxSysPll3Out.

enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5

ACMP mux from MuxSysPll1Div5.

enumerator kCLOCK_ACMP_ClockRoot_MuxAudioPllOut

ACMP mux from MuxAudioPllOut.

enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3

ACMP mux from MuxSysPll2Pfd3.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2

FLEXIO1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut

FLEXIO1 mux from MuxOsc24MOut.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M

FLEXIO1 mux from MuxOscRc400M.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M

FLEXIO1 mux from MuxOscRc16M.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2

FLEXIO1 mux from MuxSysPll3Div2.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5

FLEXIO1 mux from MuxSysPll1Div5.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out

FLEXIO1 mux from MuxSysPll2Out.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3

FLEXIO1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2

FLEXIO2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut

FLEXIO2 mux from MuxOsc24MOut.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M

FLEXIO2 mux from MuxOscRc400M.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M

FLEXIO2 mux from MuxOscRc16M.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2

FLEXIO2 mux from MuxSysPll3Div2.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5

FLEXIO2 mux from MuxSysPll1Div5.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out

FLEXIO2 mux from MuxSysPll2Out.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3

FLEXIO2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2

GPT1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT1_ClockRoot_MuxOsc24MOut

GPT1 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc400M

GPT1 mux from MuxOscRc400M.

enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc16M

GPT1 mux from MuxOscRc16M.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2

GPT1 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5

GPT1 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2

GPT1 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3

GPT1 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2

GPT2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT2_ClockRoot_MuxOsc24MOut

GPT2 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc400M

GPT2 mux from MuxOscRc400M.

enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc16M

GPT2 mux from MuxOscRc16M.

enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2

GPT2 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5

GPT2 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT2_ClockRoot_MuxAudioPllOut

GPT2 mux from MuxAudioPllOut.

enumerator kCLOCK_GPT2_ClockRoot_MuxVideoPllOut

GPT2 mux from MuxVideoPllOut.

enumerator kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2

GPT3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT3_ClockRoot_MuxOsc24MOut

GPT3 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT3_ClockRoot_MuxOscRc400M

GPT3 mux from MuxOscRc400M.

enumerator kCLOCK_GPT3_ClockRoot_MuxOscRc16M

GPT3 mux from MuxOscRc16M.

enumerator kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2

GPT3 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5

GPT3 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT3_ClockRoot_MuxAudioPllOut

GPT3 mux from MuxAudioPllOut.

enumerator kCLOCK_GPT3_ClockRoot_MuxVideoPllOut

GPT3 mux from MuxVideoPllOut.

enumerator kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2

GPT4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT4_ClockRoot_MuxOsc24MOut

GPT4 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT4_ClockRoot_MuxOscRc400M

GPT4 mux from MuxOscRc400M.

enumerator kCLOCK_GPT4_ClockRoot_MuxOscRc16M

GPT4 mux from MuxOscRc16M.

enumerator kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2

GPT4 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5

GPT4 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2

GPT4 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3

GPT4 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2

GPT5 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT5_ClockRoot_MuxOsc24MOut

GPT5 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT5_ClockRoot_MuxOscRc400M

GPT5 mux from MuxOscRc400M.

enumerator kCLOCK_GPT5_ClockRoot_MuxOscRc16M

GPT5 mux from MuxOscRc16M.

enumerator kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2

GPT5 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5

GPT5 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2

GPT5 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3

GPT5 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2

GPT6 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GPT6_ClockRoot_MuxOsc24MOut

GPT6 mux from MuxOsc24MOut.

enumerator kCLOCK_GPT6_ClockRoot_MuxOscRc400M

GPT6 mux from MuxOscRc400M.

enumerator kCLOCK_GPT6_ClockRoot_MuxOscRc16M

GPT6 mux from MuxOscRc16M.

enumerator kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2

GPT6 mux from MuxSysPll3Div2.

enumerator kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5

GPT6 mux from MuxSysPll1Div5.

enumerator kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2

GPT6 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3

GPT6 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2

FLEXSPI1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut

FLEXSPI1 mux from MuxOsc24MOut.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M

FLEXSPI1 mux from MuxOscRc400M.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M

FLEXSPI1 mux from MuxOscRc16M.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0

FLEXSPI1 mux from MuxSysPll3Pfd0.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out

FLEXSPI1 mux from MuxSysPll2Out.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2

FLEXSPI1 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out

FLEXSPI1 mux from MuxSysPll3Out.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2

FLEXSPI2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut

FLEXSPI2 mux from MuxOsc24MOut.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M

FLEXSPI2 mux from MuxOscRc400M.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M

FLEXSPI2 mux from MuxOscRc16M.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0

FLEXSPI2 mux from MuxSysPll3Pfd0.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out

FLEXSPI2 mux from MuxSysPll2Out.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2

FLEXSPI2 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out

FLEXSPI2 mux from MuxSysPll3Out.

enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2

CAN1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CAN1_ClockRoot_MuxOsc24MOut

CAN1 mux from MuxOsc24MOut.

enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc400M

CAN1 mux from MuxOscRc400M.

enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc16M

CAN1 mux from MuxOscRc16M.

enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2

CAN1 mux from MuxSysPll3Div2.

enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5

CAN1 mux from MuxSysPll1Div5.

enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll2Out

CAN1 mux from MuxSysPll2Out.

enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3

CAN1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2

CAN2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CAN2_ClockRoot_MuxOsc24MOut

CAN2 mux from MuxOsc24MOut.

enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc400M

CAN2 mux from MuxOscRc400M.

enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc16M

CAN2 mux from MuxOscRc16M.

enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2

CAN2 mux from MuxSysPll3Div2.

enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5

CAN2 mux from MuxSysPll1Div5.

enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll2Out

CAN2 mux from MuxSysPll2Out.

enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3

CAN2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2

CAN3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CAN3_ClockRoot_MuxOsc24MOut

CAN3 mux from MuxOsc24MOut.

enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc400M

CAN3 mux from MuxOscRc400M.

enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc16M

CAN3 mux from MuxOscRc16M.

enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3

CAN3 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll3Out

CAN3 mux from MuxSysPll3Out.

enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3

CAN3 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5

CAN3 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2

LPUART1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut

LPUART1 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART1_ClockRoot_MuxOscRc400M

LPUART1 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART1_ClockRoot_MuxOscRc16M

LPUART1 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2

LPUART1 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5

LPUART1 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out

LPUART1 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3

LPUART1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2

LPUART2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut

LPUART2 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART2_ClockRoot_MuxOscRc400M

LPUART2 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART2_ClockRoot_MuxOscRc16M

LPUART2 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2

LPUART2 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5

LPUART2 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out

LPUART2 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3

LPUART2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2

LPUART3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut

LPUART3 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART3_ClockRoot_MuxOscRc400M

LPUART3 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART3_ClockRoot_MuxOscRc16M

LPUART3 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2

LPUART3 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5

LPUART3 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out

LPUART3 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3

LPUART3 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2

LPUART4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut

LPUART4 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART4_ClockRoot_MuxOscRc400M

LPUART4 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART4_ClockRoot_MuxOscRc16M

LPUART4 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2

LPUART4 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5

LPUART4 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out

LPUART4 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3

LPUART4 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2

LPUART5 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut

LPUART5 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART5_ClockRoot_MuxOscRc400M

LPUART5 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART5_ClockRoot_MuxOscRc16M

LPUART5 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2

LPUART5 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5

LPUART5 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out

LPUART5 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3

LPUART5 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2

LPUART6 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut

LPUART6 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART6_ClockRoot_MuxOscRc400M

LPUART6 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART6_ClockRoot_MuxOscRc16M

LPUART6 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2

LPUART6 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5

LPUART6 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out

LPUART6 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3

LPUART6 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2

LPUART7 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut

LPUART7 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART7_ClockRoot_MuxOscRc400M

LPUART7 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART7_ClockRoot_MuxOscRc16M

LPUART7 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2

LPUART7 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5

LPUART7 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out

LPUART7 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3

LPUART7 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2

LPUART8 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut

LPUART8 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART8_ClockRoot_MuxOscRc400M

LPUART8 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART8_ClockRoot_MuxOscRc16M

LPUART8 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2

LPUART8 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5

LPUART8 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out

LPUART8 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3

LPUART8 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2

LPUART9 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut

LPUART9 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART9_ClockRoot_MuxOscRc400M

LPUART9 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART9_ClockRoot_MuxOscRc16M

LPUART9 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2

LPUART9 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5

LPUART9 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out

LPUART9 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3

LPUART9 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2

LPUART10 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut

LPUART10 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART10_ClockRoot_MuxOscRc400M

LPUART10 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART10_ClockRoot_MuxOscRc16M

LPUART10 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2

LPUART10 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5

LPUART10 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out

LPUART10 mux from MuxSysPll2Out.

enumerator kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3

LPUART10 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2

LPUART11 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut

LPUART11 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART11_ClockRoot_MuxOscRc400M

LPUART11 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART11_ClockRoot_MuxOscRc16M

LPUART11 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3

LPUART11 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out

LPUART11 mux from MuxSysPll3Out.

enumerator kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3

LPUART11 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5

LPUART11 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2

LPUART12 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut

LPUART12 mux from MuxOsc24MOut.

enumerator kCLOCK_LPUART12_ClockRoot_MuxOscRc400M

LPUART12 mux from MuxOscRc400M.

enumerator kCLOCK_LPUART12_ClockRoot_MuxOscRc16M

LPUART12 mux from MuxOscRc16M.

enumerator kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3

LPUART12 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out

LPUART12 mux from MuxSysPll3Out.

enumerator kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3

LPUART12 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5

LPUART12 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2

LPI2C1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut

LPI2C1 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M

LPI2C1 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M

LPI2C1 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2

LPI2C1 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5

LPI2C1 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out

LPI2C1 mux from MuxSysPll2Out.

enumerator kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3

LPI2C1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2

LPI2C2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut

LPI2C2 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M

LPI2C2 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M

LPI2C2 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2

LPI2C2 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5

LPI2C2 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out

LPI2C2 mux from MuxSysPll2Out.

enumerator kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3

LPI2C2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2

LPI2C3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut

LPI2C3 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M

LPI2C3 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M

LPI2C3 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2

LPI2C3 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5

LPI2C3 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out

LPI2C3 mux from MuxSysPll2Out.

enumerator kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3

LPI2C3 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2

LPI2C4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut

LPI2C4 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M

LPI2C4 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M

LPI2C4 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2

LPI2C4 mux from MuxSysPll3Div2.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5

LPI2C4 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out

LPI2C4 mux from MuxSysPll2Out.

enumerator kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3

LPI2C4 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2

LPI2C5 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut

LPI2C5 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M

LPI2C5 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M

LPI2C5 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3

LPI2C5 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out

LPI2C5 mux from MuxSysPll3Out.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3

LPI2C5 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5

LPI2C5 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2

LPI2C6 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut

LPI2C6 mux from MuxOsc24MOut.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M

LPI2C6 mux from MuxOscRc400M.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M

LPI2C6 mux from MuxOscRc16M.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3

LPI2C6 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out

LPI2C6 mux from MuxSysPll3Out.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3

LPI2C6 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5

LPI2C6 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2

LPSPI1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut

LPSPI1 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M

LPSPI1 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M

LPSPI1 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2

LPSPI1 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5

LPSPI1 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out

LPSPI1 mux from MuxSysPll2Out.

enumerator kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3

LPSPI1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2

LPSPI2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut

LPSPI2 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M

LPSPI2 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M

LPSPI2 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2

LPSPI2 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5

LPSPI2 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out

LPSPI2 mux from MuxSysPll2Out.

enumerator kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3

LPSPI2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2

LPSPI3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut

LPSPI3 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M

LPSPI3 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M

LPSPI3 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2

LPSPI3 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5

LPSPI3 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out

LPSPI3 mux from MuxSysPll2Out.

enumerator kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3

LPSPI3 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2

LPSPI4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut

LPSPI4 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M

LPSPI4 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M

LPSPI4 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2

LPSPI4 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5

LPSPI4 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out

LPSPI4 mux from MuxSysPll2Out.

enumerator kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3

LPSPI4 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2

LPSPI5 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut

LPSPI5 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M

LPSPI5 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M

LPSPI5 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3

LPSPI5 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out

LPSPI5 mux from MuxSysPll3Out.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2

LPSPI5 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5

LPSPI5 mux from MuxSysPll1Div5.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2

LPSPI6 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut

LPSPI6 mux from MuxOsc24MOut.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M

LPSPI6 mux from MuxOscRc400M.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M

LPSPI6 mux from MuxOscRc16M.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3

LPSPI6 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out

LPSPI6 mux from MuxSysPll3Out.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2

LPSPI6 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5

LPSPI6 mux from MuxSysPll1Div5.

enumerator kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2

EMV1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_EMV1_ClockRoot_MuxOsc24MOut

EMV1 mux from MuxOsc24MOut.

enumerator kCLOCK_EMV1_ClockRoot_MuxOscRc400M

EMV1 mux from MuxOscRc400M.

enumerator kCLOCK_EMV1_ClockRoot_MuxOscRc16M

EMV1 mux from MuxOscRc16M.

enumerator kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2

EMV1 mux from MuxSysPll3Div2.

enumerator kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5

EMV1 mux from MuxSysPll1Div5.

enumerator kCLOCK_EMV1_ClockRoot_MuxSysPll2Out

EMV1 mux from MuxSysPll2Out.

enumerator kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3

EMV1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2

EMV2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_EMV2_ClockRoot_MuxOsc24MOut

EMV2 mux from MuxOsc24MOut.

enumerator kCLOCK_EMV2_ClockRoot_MuxOscRc400M

EMV2 mux from MuxOscRc400M.

enumerator kCLOCK_EMV2_ClockRoot_MuxOscRc16M

EMV2 mux from MuxOscRc16M.

enumerator kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2

EMV2 mux from MuxSysPll3Div2.

enumerator kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5

EMV2 mux from MuxSysPll1Div5.

enumerator kCLOCK_EMV2_ClockRoot_MuxSysPll2Out

EMV2 mux from MuxSysPll2Out.

enumerator kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3

EMV2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2

ENET1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET1_ClockRoot_MuxOsc24MOut

ENET1 mux from MuxOsc24MOut.

enumerator kCLOCK_ENET1_ClockRoot_MuxOscRc400M

ENET1 mux from MuxOscRc400M.

enumerator kCLOCK_ENET1_ClockRoot_MuxOscRc16M

ENET1 mux from MuxOscRc16M.

enumerator kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2

ENET1 mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET1_ClockRoot_MuxAudioPllOut

ENET1 mux from MuxAudioPllOut.

enumerator kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5

ENET1 mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1

ENET1 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2

ENET2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET2_ClockRoot_MuxOsc24MOut

ENET2 mux from MuxOsc24MOut.

enumerator kCLOCK_ENET2_ClockRoot_MuxOscRc400M

ENET2 mux from MuxOscRc400M.

enumerator kCLOCK_ENET2_ClockRoot_MuxOscRc16M

ENET2 mux from MuxOscRc16M.

enumerator kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2

ENET2 mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET2_ClockRoot_MuxAudioPllOut

ENET2 mux from MuxAudioPllOut.

enumerator kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5

ENET2 mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1

ENET2 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2

ENET_QOS mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut

ENET_QOS mux from MuxOsc24MOut.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M

ENET_QOS mux from MuxOscRc400M.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M

ENET_QOS mux from MuxOscRc16M.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2

ENET_QOS mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut

ENET_QOS mux from MuxAudioPllOut.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5

ENET_QOS mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1

ENET_QOS mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2

ENET_25M mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut

ENET_25M mux from MuxOsc24MOut.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M

ENET_25M mux from MuxOscRc400M.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M

ENET_25M mux from MuxOscRc16M.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2

ENET_25M mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut

ENET_25M mux from MuxAudioPllOut.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5

ENET_25M mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1

ENET_25M mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2

ENET_TIMER1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut

ENET_TIMER1 mux from MuxOsc24MOut.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M

ENET_TIMER1 mux from MuxOscRc400M.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M

ENET_TIMER1 mux from MuxOscRc16M.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2

ENET_TIMER1 mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut

ENET_TIMER1 mux from MuxAudioPllOut.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5

ENET_TIMER1 mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1

ENET_TIMER1 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2

ENET_TIMER2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut

ENET_TIMER2 mux from MuxOsc24MOut.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M

ENET_TIMER2 mux from MuxOscRc400M.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M

ENET_TIMER2 mux from MuxOscRc16M.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2

ENET_TIMER2 mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut

ENET_TIMER2 mux from MuxAudioPllOut.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5

ENET_TIMER2 mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1

ENET_TIMER2 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2

ENET_TIMER3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut

ENET_TIMER3 mux from MuxOsc24MOut.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M

ENET_TIMER3 mux from MuxOscRc400M.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M

ENET_TIMER3 mux from MuxOscRc16M.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2

ENET_TIMER3 mux from MuxSysPll1Div2.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut

ENET_TIMER3 mux from MuxAudioPllOut.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5

ENET_TIMER3 mux from MuxSysPll1Div5.

enumerator kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1

ENET_TIMER3 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2

USDHC1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut

USDHC1 mux from MuxOsc24MOut.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc400M

USDHC1 mux from MuxOscRc400M.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc16M

USDHC1 mux from MuxOscRc16M.

enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2

USDHC1 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0

USDHC1 mux from MuxSysPll2Pfd0.

enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5

USDHC1 mux from MuxSysPll1Div5.

enumerator kCLOCK_USDHC1_ClockRoot_MuxArmPllOut

USDHC1 mux from MuxArmPllOut.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2

USDHC2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut

USDHC2 mux from MuxOsc24MOut.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc400M

USDHC2 mux from MuxOscRc400M.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc16M

USDHC2 mux from MuxOscRc16M.

enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2

USDHC2 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0

USDHC2 mux from MuxSysPll2Pfd0.

enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5

USDHC2 mux from MuxSysPll1Div5.

enumerator kCLOCK_USDHC2_ClockRoot_MuxArmPllOut

USDHC2 mux from MuxArmPllOut.

enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2

ASRC mux from MuxOscRc48MDiv2.

enumerator kCLOCK_ASRC_ClockRoot_MuxOsc24MOut

ASRC mux from MuxOsc24MOut.

enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc400M

ASRC mux from MuxOscRc400M.

enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc16M

ASRC mux from MuxOscRc16M.

enumerator kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5

ASRC mux from MuxSysPll1Div5.

enumerator kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2

ASRC mux from MuxSysPll3Div2.

enumerator kCLOCK_ASRC_ClockRoot_MuxAudioPllOut

ASRC mux from MuxAudioPllOut.

enumerator kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3

ASRC mux from MuxSysPll2Pfd3.

enumerator kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2

MQS mux from MuxOscRc48MDiv2.

enumerator kCLOCK_MQS_ClockRoot_MuxOsc24MOut

MQS mux from MuxOsc24MOut.

enumerator kCLOCK_MQS_ClockRoot_MuxOscRc400M

MQS mux from MuxOscRc400M.

enumerator kCLOCK_MQS_ClockRoot_MuxOscRc16M

MQS mux from MuxOscRc16M.

enumerator kCLOCK_MQS_ClockRoot_MuxSysPll1Div5

MQS mux from MuxSysPll1Div5.

enumerator kCLOCK_MQS_ClockRoot_MuxSysPll3Div2

MQS mux from MuxSysPll3Div2.

enumerator kCLOCK_MQS_ClockRoot_MuxAudioPllOut

MQS mux from MuxAudioPllOut.

enumerator kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3

MQS mux from MuxSysPll2Pfd3.

enumerator kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2

MIC mux from MuxOscRc48MDiv2.

enumerator kCLOCK_MIC_ClockRoot_MuxOsc24MOut

MIC mux from MuxOsc24MOut.

enumerator kCLOCK_MIC_ClockRoot_MuxOscRc400M

MIC mux from MuxOscRc400M.

enumerator kCLOCK_MIC_ClockRoot_MuxOscRc16M

MIC mux from MuxOscRc16M.

enumerator kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3

MIC mux from MuxSysPll3Pfd3.

enumerator kCLOCK_MIC_ClockRoot_MuxSysPll3Out

MIC mux from MuxSysPll3Out.

enumerator kCLOCK_MIC_ClockRoot_MuxAudioPllOut

MIC mux from MuxAudioPllOut.

enumerator kCLOCK_MIC_ClockRoot_MuxSysPll1Div5

MIC mux from MuxSysPll1Div5.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2

SPDIF mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut

SPDIF mux from MuxOsc24MOut.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc400M

SPDIF mux from MuxOscRc400M.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc16M

SPDIF mux from MuxOscRc16M.

enumerator kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut

SPDIF mux from MuxAudioPllOut.

enumerator kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out

SPDIF mux from MuxSysPll3Out.

enumerator kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2

SPDIF mux from MuxSysPll3Pfd2.

enumerator kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3

SPDIF mux from MuxSysPll2Pfd3.

enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2

SAI1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SAI1_ClockRoot_MuxOsc24MOut

SAI1 mux from MuxOsc24MOut.

enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc400M

SAI1 mux from MuxOscRc400M.

enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc16M

SAI1 mux from MuxOscRc16M.

enumerator kCLOCK_SAI1_ClockRoot_MuxAudioPllOut

SAI1 mux from MuxAudioPllOut.

enumerator kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2

SAI1 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5

SAI1 mux from MuxSysPll1Div5.

enumerator kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3

SAI1 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2

SAI2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SAI2_ClockRoot_MuxOsc24MOut

SAI2 mux from MuxOsc24MOut.

enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc400M

SAI2 mux from MuxOscRc400M.

enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc16M

SAI2 mux from MuxOscRc16M.

enumerator kCLOCK_SAI2_ClockRoot_MuxAudioPllOut

SAI2 mux from MuxAudioPllOut.

enumerator kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2

SAI2 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5

SAI2 mux from MuxSysPll1Div5.

enumerator kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3

SAI2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2

SAI3 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SAI3_ClockRoot_MuxOsc24MOut

SAI3 mux from MuxOsc24MOut.

enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc400M

SAI3 mux from MuxOscRc400M.

enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc16M

SAI3 mux from MuxOscRc16M.

enumerator kCLOCK_SAI3_ClockRoot_MuxAudioPllOut

SAI3 mux from MuxAudioPllOut.

enumerator kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2

SAI3 mux from MuxSysPll3Pfd2.

enumerator kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5

SAI3 mux from MuxSysPll1Div5.

enumerator kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3

SAI3 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2

SAI4 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_SAI4_ClockRoot_MuxOsc24MOut

SAI4 mux from MuxOsc24MOut.

enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc400M

SAI4 mux from MuxOscRc400M.

enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc16M

SAI4 mux from MuxOscRc16M.

enumerator kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3

SAI4 mux from MuxSysPll3Pfd3.

enumerator kCLOCK_SAI4_ClockRoot_MuxSysPll3Out

SAI4 mux from MuxSysPll3Out.

enumerator kCLOCK_SAI4_ClockRoot_MuxAudioPllOut

SAI4 mux from MuxAudioPllOut.

enumerator kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5

SAI4 mux from MuxSysPll1Div5.

enumerator kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2

GC355 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_GC355_ClockRoot_MuxOsc24MOut

GC355 mux from MuxOsc24MOut.

enumerator kCLOCK_GC355_ClockRoot_MuxOscRc400M

GC355 mux from MuxOscRc400M.

enumerator kCLOCK_GC355_ClockRoot_MuxOscRc16M

GC355 mux from MuxOscRc16M.

enumerator kCLOCK_GC355_ClockRoot_MuxSysPll2Out

GC355 mux from MuxSysPll2Out.

enumerator kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1

GC355 mux from MuxSysPll2Pfd1.

enumerator kCLOCK_GC355_ClockRoot_MuxSysPll3Out

GC355 mux from MuxSysPll3Out.

enumerator kCLOCK_GC355_ClockRoot_MuxVideoPllOut

GC355 mux from MuxVideoPllOut.

enumerator kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2

LCDIF mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut

LCDIF mux from MuxOsc24MOut.

enumerator kCLOCK_LCDIF_ClockRoot_MuxOscRc400M

LCDIF mux from MuxOscRc400M.

enumerator kCLOCK_LCDIF_ClockRoot_MuxOscRc16M

LCDIF mux from MuxOscRc16M.

enumerator kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out

LCDIF mux from MuxSysPll2Out.

enumerator kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2

LCDIF mux from MuxSysPll2Pfd2.

enumerator kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0

LCDIF mux from MuxSysPll3Pfd0.

enumerator kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut

LCDIF mux from MuxVideoPllOut.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2

LCDIFV2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut

LCDIFV2 mux from MuxOsc24MOut.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M

LCDIFV2 mux from MuxOscRc400M.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M

LCDIFV2 mux from MuxOscRc16M.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out

LCDIFV2 mux from MuxSysPll2Out.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2

LCDIFV2 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0

LCDIFV2 mux from MuxSysPll3Pfd0.

enumerator kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut

LCDIFV2 mux from MuxVideoPllOut.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2

MIPI_REF mux from MuxOscRc48MDiv2.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut

MIPI_REF mux from MuxOsc24MOut.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M

MIPI_REF mux from MuxOscRc400M.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M

MIPI_REF mux from MuxOscRc16M.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out

MIPI_REF mux from MuxSysPll2Out.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0

MIPI_REF mux from MuxSysPll2Pfd0.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0

MIPI_REF mux from MuxSysPll3Pfd0.

enumerator kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut

MIPI_REF mux from MuxVideoPllOut.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2

MIPI_ESC mux from MuxOscRc48MDiv2.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut

MIPI_ESC mux from MuxOsc24MOut.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M

MIPI_ESC mux from MuxOscRc400M.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M

MIPI_ESC mux from MuxOscRc16M.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out

MIPI_ESC mux from MuxSysPll2Out.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0

MIPI_ESC mux from MuxSysPll2Pfd0.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0

MIPI_ESC mux from MuxSysPll3Pfd0.

enumerator kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut

MIPI_ESC mux from MuxVideoPllOut.

enumerator kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2

CSI2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSI2_ClockRoot_MuxOsc24MOut

CSI2 mux from MuxOsc24MOut.

enumerator kCLOCK_CSI2_ClockRoot_MuxOscRc400M

CSI2 mux from MuxOscRc400M.

enumerator kCLOCK_CSI2_ClockRoot_MuxOscRc16M

CSI2 mux from MuxOscRc16M.

enumerator kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2

CSI2 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_CSI2_ClockRoot_MuxSysPll3Out

CSI2 mux from MuxSysPll3Out.

enumerator kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0

CSI2 mux from MuxSysPll2Pfd0.

enumerator kCLOCK_CSI2_ClockRoot_MuxVideoPllOut

CSI2 mux from MuxVideoPllOut.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2

CSI2_ESC mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut

CSI2_ESC mux from MuxOsc24MOut.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M

CSI2_ESC mux from MuxOscRc400M.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M

CSI2_ESC mux from MuxOscRc16M.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2

CSI2_ESC mux from MuxSysPll2Pfd2.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out

CSI2_ESC mux from MuxSysPll3Out.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0

CSI2_ESC mux from MuxSysPll2Pfd0.

enumerator kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut

CSI2_ESC mux from MuxVideoPllOut.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2

CSI2_UI mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut

CSI2_UI mux from MuxOsc24MOut.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M

CSI2_UI mux from MuxOscRc400M.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M

CSI2_UI mux from MuxOscRc16M.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2

CSI2_UI mux from MuxSysPll2Pfd2.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out

CSI2_UI mux from MuxSysPll3Out.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0

CSI2_UI mux from MuxSysPll2Pfd0.

enumerator kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut

CSI2_UI mux from MuxVideoPllOut.

enumerator kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2

CSI mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CSI_ClockRoot_MuxOsc24MOut

CSI mux from MuxOsc24MOut.

enumerator kCLOCK_CSI_ClockRoot_MuxOscRc400M

CSI mux from MuxOscRc400M.

enumerator kCLOCK_CSI_ClockRoot_MuxOscRc16M

CSI mux from MuxOscRc16M.

enumerator kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2

CSI mux from MuxSysPll2Pfd2.

enumerator kCLOCK_CSI_ClockRoot_MuxSysPll3Out

CSI mux from MuxSysPll3Out.

enumerator kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1

CSI mux from MuxSysPll3Pfd1.

enumerator kCLOCK_CSI_ClockRoot_MuxVideoPllOut

CSI mux from MuxVideoPllOut.

enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2

CKO1 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CKO1_ClockRoot_MuxOsc24MOut

CKO1 mux from MuxOsc24MOut.

enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc400M

CKO1 mux from MuxOscRc400M.

enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc16M

CKO1 mux from MuxOscRc16M.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2

CKO1 mux from MuxSysPll2Pfd2.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll2Out

CKO1 mux from MuxSysPll2Out.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1

CKO1 mux from MuxSysPll3Pfd1.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5

CKO1 mux from MuxSysPll1Div5.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2

CKO2 mux from MuxOscRc48MDiv2.

enumerator kCLOCK_CKO2_ClockRoot_MuxOsc24MOut

CKO2 mux from MuxOsc24MOut.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc400M

CKO2 mux from MuxOscRc400M.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc16M

CKO2 mux from MuxOscRc16M.

enumerator kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3

CKO2 mux from MuxSysPll2Pfd3.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc48M

CKO2 mux from MuxOscRc48M.

enumerator kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1

CKO2 mux from MuxSysPll3Pfd1.

enumerator kCLOCK_CKO2_ClockRoot_MuxAudioPllOut

CKO2 mux from MuxAudioPllOut.

enum _clock_group

Clock group enumeration.

Values:

enumerator kCLOCK_Group_FlexRAM

FlexRAM clock group.

enumerator kCLOCK_Group_MipiDsi

Mipi Dsi clock group.

enumerator kCLOCK_Group_Last

Last clock group.

enum _clock_osc

OSC 24M sorce select.

Values:

enumerator kCLOCK_RcOsc

On chip OSC.

enumerator kCLOCK_XtalOsc

24M Xtal OSC

enum _clock_gate_value

Clock gate value.

Values:

enumerator kCLOCK_Off

Clock is off.

enumerator kCLOCK_On

Clock is on

enum _clock_mode_t

System clock mode.

Values:

enumerator kCLOCK_ModeRun

Remain in run mode.

enumerator kCLOCK_ModeWait

Transfer to wait mode.

enumerator kCLOCK_ModeStop

Transfer to stop mode.

enum _clock_usb_src

USB clock source definition.

Values:

enumerator kCLOCK_Usb480M

Use 480M.

enumerator kCLOCK_UsbSrcUnused

Used when the function does not care the clock source.

enum _clock_usb_phy_src

Source of the USB HS PHY.

Values:

enumerator kCLOCK_Usbphy480M

Use 480M.

enum _clock_pll_clk_src

PLL clock source, bypass cloco source also.

Values:

enumerator kCLOCK_PllClkSrc24M

Pll clock source 24M

enumerator kCLOCK_PllSrcClkPN

Pll clock source CLK1_P and CLK1_N

enum _clock_pll_post_div

PLL post divider enumeration.

Values:

enumerator kCLOCK_PllPostDiv2

Divide by 2.

enumerator kCLOCK_PllPostDiv4

Divide by 4.

enumerator kCLOCK_PllPostDiv8

Divide by 8.

enumerator kCLOCK_PllPostDiv1

Divide by 1.

enum _clock_pll

PLL name.

Values:

enumerator kCLOCK_PllArm

ARM PLL.

enumerator kCLOCK_PllSys1

SYS1 PLL, it has a dedicated frequency of 1GHz.

enumerator kCLOCK_PllSys2

SYS2 PLL, it has a dedicated frequency of 528MHz.

enumerator kCLOCK_PllSys3

SYS3 PLL, it has a dedicated frequency of 480MHz.

enumerator kCLOCK_PllAudio

Audio PLL.

enumerator kCLOCK_PllVideo

Video PLL.

enumerator kCLOCK_PllInvalid

Invalid value.

enum _clock_pfd

PLL PFD name.

Values:

enumerator kCLOCK_Pfd0

PLL PFD0

enumerator kCLOCK_Pfd1

PLL PFD1

enumerator kCLOCK_Pfd2

PLL PFD2

enumerator kCLOCK_Pfd3

PLL PFD3

enum _clock_control_mode

The enumeration of control mode.

Values:

enumerator kCLOCK_SoftwareMode

Software control mode.

enumerator kCLOCK_GpcMode

GPC control mode.

enum _clock_24MOsc_mode

The enumeration of 24MHz crystal oscillator mode.

Values:

enumerator kCLOCK_24MOscHighGainMode

24MHz crystal oscillator work as high gain mode.

enumerator kCLOCK_24MOscBypassMode

24MHz crystal oscillator work as bypass mode.

enumerator kCLOCK_24MOscLowPowerMode

24MHz crystal oscillator work as low power mode.

enum _clock_16MOsc_source

The enumeration of 16MHz RC oscillator clock source.

Values:

enumerator kCLOCK_16MOscSourceFrom16MOsc

Source from 16MHz RC oscialltor.

enumerator kCLOCK_16MOscSourceFrom24MOsc

Source from 24MHz crystal oscillator.

enum _clock_1MHzOut_behavior

The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

Values:

enumerator kCLOCK_1MHzOutDisable

Disable 1MHz output clock.

enumerator kCLOCK_1MHzOutEnableLocked1Mhz

Enable 1MHz output clock, and select locked 1MHz to output.

enumerator kCLOCK_1MHzOutEnableFreeRunning1Mhz

Enable 1MHZ output clock, and select free-running 1MHz to output.

enum _clock_level

The clock dependence level.

Values:

enumerator kCLOCK_Level0

Not needed in any mode.

enumerator kCLOCK_Level1

Needed in RUN mode.

enumerator kCLOCK_Level2

Needed in RUN and WAIT mode.

enumerator kCLOCK_Level3

Needed in RUN, WAIT and STOP mode.

enumerator kCLOCK_Level4

Always on in any mode.

typedef enum _clock_lpcg clock_lpcg_t

Clock LPCG index.

typedef enum _clock_name clock_name_t

Clock name.

typedef enum _clock_root clock_root_t

Root clock index.

typedef enum _clock_root_mux_source clock_root_mux_source_t

The enumerator of clock roots’ clock source mux value.

typedef enum _clock_group clock_group_t

Clock group enumeration.

typedef struct _clock_group_config clock_group_config_t

The structure used to configure clock group.

typedef enum _clock_osc clock_osc_t

OSC 24M sorce select.

typedef enum _clock_gate_value clock_gate_value_t

Clock gate value.

typedef enum _clock_mode_t clock_mode_t

System clock mode.

typedef enum _clock_usb_src clock_usb_src_t

USB clock source definition.

typedef enum _clock_usb_phy_src clock_usb_phy_src_t

Source of the USB HS PHY.

typedef enum _clock_pll_post_div clock_pll_post_div_t

PLL post divider enumeration.

typedef struct _clock_arm_pll_config clock_arm_pll_config_t

PLL configuration for ARM.

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

typedef struct _clock_usb_pll_config clock_usb_pll_config_t

PLL configuration for USB.

typedef struct _clock_pll_ss_config clock_pll_ss_config_t

Spread specturm configure Pll.

typedef struct _clock_sys_pll2_config clock_sys_pll2_config_t

PLL configure for Sys Pll2.

typedef struct _clock_sys_pll1_config clock_sys_pll1_config_t

PLL configure for Sys Pll1.

typedef struct _clock_audio_pll_config clock_av_pll_config_t

PLL configuration for AUDIO and VIDEO.

typedef struct _clock_audio_pll_config clock_audio_pll_config_t

typedef struct _clock_audio_pll_config clock_video_pll_config_t

typedef struct _clock_audio_pll_gpc_config clock_audio_pll_gpc_config_t

PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.

typedef struct _clock_audio_pll_gpc_config clock_video_pll_gpc_config_t

typedef struct _clock_audio_pll_gpc_config clock_sys_pll1_gpc_config_t

typedef struct _clock_enet_pll_config clock_enet_pll_config_t

PLL configuration for ENET.

typedef struct _clock_root_config_t clock_root_config_t

Clock root configuration.

typedef struct _clock_root_setpoint_config_t clock_root_setpoint_config_t

Clock root configuration in SetPoint Mode.

typedef enum _clock_pll clock_pll_t

PLL name.

typedef enum _clock_pfd clock_pfd_t

PLL PFD name.

typedef enum _clock_control_mode clock_control_mode_t

The enumeration of control mode.

typedef enum _clock_24MOsc_mode clock_24MOsc_mode_t

The enumeration of 24MHz crystal oscillator mode.

typedef enum _clock_16MOsc_source clock_16MOsc_source_t

The enumeration of 16MHz RC oscillator clock source.

typedef enum _clock_1MHzOut_behavior clock_1MHzOut_behavior_t

The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

typedef enum _clock_level clock_level_t

The clock dependence level.

const clock_name_t s_clockSourceName[][8]

static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)

Set CCM Root Clock MUX node to certain value.

Parameters:

• root – Which root clock node to set, see clock_root_t.

• src – Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.

static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)

Get CCM Root Clock MUX value.

Parameters:

• root – Which root clock node to get, see clock_root_t.

Returns:

Clock mux value.

static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)

Get CCM Root Clock Source.

Parameters:

• root – Which root clock node to get, see clock_root_t.

• src – Clock mux value to get, see clock_root_mux_source_t.

Returns:

Clock source

static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div)

Set CCM Root Clock DIV certain value.

Parameters:

• root – Which root clock to set, see clock_root_t.

• div – Clock div value to set range is 1-256, different divider has different value range.

static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)

Get CCM DIV node value.

Parameters:

• root – Which root clock node to get, see clock_root_t.

Returns:

divider set for this root

static inline void CLOCK_PowerOffRootClock(clock_root_t root)

Power Off Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

static inline void CLOCK_PowerOnRootClock(clock_root_t root)

Power On Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)

Configure Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

• config – root clock config, see clock_root_config_t

static inline void CLOCK_ControlGate(clock_lpcg_t name, clock_gate_value_t value)

Control the clock gate for specific IP.

Note

This API will not have any effect when this clock is in CPULPM or SetPoint Mode

Parameters:

• name – Which clock to enable, see clock_lpcg_t.

• value – Clock gate value to set, see clock_gate_value_t.

static inline void CLOCK_EnableClock(clock_lpcg_t name)

Enable the clock for specific IP.

Parameters:

• name – Which clock to enable, see clock_lpcg_t.

static inline void CLOCK_DisableClock(clock_lpcg_t name)

Disable the clock for specific IP.

Parameters:

• name – Which clock to disable, see clock_lpcg_t.

void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config)

Set the clock group configuration.

Parameters:

• group – Which group to configure, see clock_group_t.

• config – Configuration to set.

uint32_t CLOCK_GetFreq(clock_name_t name)

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters:

• name – Clock names defined in clock_name_t

Returns:

Clock frequency value in hertz

static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)

Gets the clock frequency for a specific root clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.

Parameters:

• root – Clock names defined in clock_root_t

Returns:

Clock frequency value in hertz

static inline uint32_t CLOCK_GetM7Freq(void)

Get the CCM CPU/core/system frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

static inline uint32_t CLOCK_GetM4Freq(void)

Get the CCM CPU/core/system frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)

Check if PLL is bypassed.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

Returns:

PLL bypass status.

• true: The PLL is bypassed.

• false: The PLL is not bypassed.

static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)

Check if PLL is enabled.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

Returns:

PLL bypass status.

• true: The PLL is enabled.

• false: The PLL is not enabled.

FSL_CLOCK_DRIVER_VERSION

CLOCK driver version.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

CCSR_OFFSET

CCM registers offset.

CBCDR_OFFSET

CBCMR_OFFSET

CSCMR1_OFFSET

CSCMR2_OFFSET

CSCDR1_OFFSET

CDCDR_OFFSET

CSCDR2_OFFSET

CSCDR3_OFFSET

CACRR_OFFSET

CS1CDR_OFFSET

CS2CDR_OFFSET

ARM_PLL_OFFSET

CCM Analog registers offset.

PLL_SYS_OFFSET

PLL_USB1_OFFSET

PLL_AUDIO_OFFSET

PLL_VIDEO_OFFSET

PLL_ENET_OFFSET

PLL_USB2_OFFSET

CCM_TUPLE(reg, shift, mask, busyShift)

CCM_TUPLE_REG(base, tuple)

CCM_TUPLE_SHIFT(tuple)

CCM_TUPLE_MASK(tuple)

CCM_TUPLE_BUSY_SHIFT(tuple)

CCM_BUSY_WAIT

CCM_ANALOG_TUPLE(reg, shift)

CCM ANALOG tuple macros to map corresponding registers and bit fields.

CCM_ANALOG_TUPLE_SHIFT(tuple)

CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)

CCM_ANALOG_TUPLE_REG(base, tuple)

SYS_PLL1_FREQ

SYS_PLL_FREQ frequency in Hz.

SYS_PLL2_MFI

SYS_PLL2_FREQ

SYS_PLL3_MFI

SYS_PLL3_FREQ

XTAL_FREQ

LPADC_CLOCKS

Clock gate name array for ADC.

ADC_ETC_CLOCKS

Clock gate name array for ADC.

AOI_CLOCKS

Clock gate name array for AOI.

DCDC_CLOCKS

Clock gate name array for DCDC.

Clock ip name array for DCDC.

DCDC_CLOCKS

Clock gate name array for DCDC.

Clock ip name array for DCDC.

SRC_CLOCKS

Clock gate name array for SRC.

GPC_CLOCKS

Clock gate name array for GPC.

SSARC_CLOCKS

Clock gate name array for SSARC.

WDOG_CLOCKS

Clock gate name array for WDOG.

EWM_CLOCKS

Clock gate name array for EWM.

SEMA_CLOCKS

Clock gate name array for Sema.

MU_CLOCKS

Clock gate name array for MU.

EDMA_CLOCKS

Clock gate name array for EDMA.

FLEXRAM_CLOCKS

Clock gate name array for FLEXRAM.

LMEM_CLOCKS

Clock gate name array for LMEM.

FLEXSPI_CLOCKS

Clock gate name array for FLEXSPI.

RDC_CLOCKS

Clock gate name array for RDC.

SEMC_CLOCKS

Clock ip name array for SEMC.

XECC_CLOCKS

Clock ip name array for XECC.

IEE_CLOCKS

Clock ip name array for IEE.

KEYMANAGER_CLOCKS

Clock ip name array for KEY_MANAGER.

PUF_CLOCKS

Clock ip name array for PUF.

OCOTP_CLOCKS

Clock ip name array for OCOTP.

CAAM_CLOCKS

Clock ip name array for CAAM.

XBAR_CLOCKS

Clock ip name array for XBAR.

IOMUXC_CLOCKS

Clock ip name array for IOMUXC.

GPIO_CLOCKS

Clock ip name array for GPIO.

KPP_CLOCKS

Clock ip name array for KPP.

FLEXIO_CLOCKS

Clock ip name array for FLEXIO.

DAC_CLOCKS

Clock ip name array for DAC.

CMP_CLOCKS

Clock ip name array for CMP.

PIT_CLOCKS

Clock ip name array for PIT.

GPT_CLOCKS

Clock ip name array for GPT.

TMR_CLOCKS

Clock ip name array for QTIMER.

ENC_CLOCKS

Clock ip name array for ENC.

PWM_CLOCKS

Clock ip name array for PWM.

FLEXCAN_CLOCKS

Clock ip name array for FLEXCAN.

LPUART_CLOCKS

Clock ip name array for LPUART.

LPI2C_CLOCKS

Clock ip name array for LPI2C.

LPSPI_CLOCKS

Clock ip name array for LPSPI.

EMVSIM_CLOCKS

Clock ip name array for EMVSIM.

ENET_CLOCKS

Clock ip name array for ENET.

ENETQOS_CLOCKS

Clock ip name array for ENET_QOS.

USB_CLOCKS

Clock ip name array for USB.

CDOG_CLOCKS

Clock ip name array for CDOG.

USDHC_CLOCKS

Clock ip name array for USDHC.

ASRC_CLOCKS

Clock ip name array for ASRC.

MQS_CLOCKS

Clock ip name array for MQS.

PDM_CLOCKS

Clock ip name array for PDM.

SPDIF_CLOCKS

Clock ip name array for SPDIF.

SAI_CLOCKS

Clock ip name array for SAI.

PXP_CLOCKS

Clock ip name array for PXP.

GPU2D_CLOCKS

Clock ip name array for GPU2d.

LCDIF_CLOCKS

Clock ip name array for LCDIF.

LCDIFV2_CLOCKS

Clock ip name array for LCDIFV2.

MIPI_DSI_HOST_CLOCKS

Clock ip name array for MIPI_DSI.

MIPI_CSI2RX_CLOCKS

Clock ip name array for MIPI_CSI.

CSI_CLOCKS

Clock ip name array for CSI.

DCIC_CLOCKS

Clock ip name array for DCIC.

DMAMUX_CLOCKS

Clock ip name array for DMAMUX_CLOCKS.

XBARA_CLOCKS

Clock ip name array for XBARA.

XBARB_CLOCKS

Clock ip name array for XBARB.

CCM_OBS_M7_CLK_ROOT

CCM_OBS_M4_CLK_ROOT

CCM_OBS_BUS_CLK_ROOT

CCM_OBS_BUS_LPSR_CLK_ROOT

CCM_OBS_SEMC_CLK_ROOT

CCM_OBS_CSSYS_CLK_ROOT

CCM_OBS_CSTRACE_CLK_ROOT

CCM_OBS_M4_SYSTICK_CLK_ROOT

CCM_OBS_M7_SYSTICK_CLK_ROOT

CCM_OBS_ADC1_CLK_ROOT

CCM_OBS_ADC2_CLK_ROOT

CCM_OBS_ACMP_CLK_ROOT

CCM_OBS_FLEXIO1_CLK_ROOT

CCM_OBS_FLEXIO2_CLK_ROOT

CCM_OBS_GPT1_CLK_ROOT

CCM_OBS_GPT2_CLK_ROOT

CCM_OBS_GPT3_CLK_ROOT

CCM_OBS_GPT4_CLK_ROOT

CCM_OBS_GPT5_CLK_ROOT

CCM_OBS_GPT6_CLK_ROOT

CCM_OBS_FLEXSPI1_CLK_ROOT

CCM_OBS_FLEXSPI2_CLK_ROOT

CCM_OBS_CAN1_CLK_ROOT

CCM_OBS_CAN2_CLK_ROOT

CCM_OBS_CAN3_CLK_ROOT

CCM_OBS_LPUART1_CLK_ROOT

CCM_OBS_LPUART2_CLK_ROOT

CCM_OBS_LPUART3_CLK_ROOT

CCM_OBS_LPUART4_CLK_ROOT

CCM_OBS_LPUART5_CLK_ROOT

CCM_OBS_LPUART6_CLK_ROOT

CCM_OBS_LPUART7_CLK_ROOT

CCM_OBS_LPUART8_CLK_ROOT

CCM_OBS_LPUART9_CLK_ROOT

CCM_OBS_LPUART10_CLK_ROOT

CCM_OBS_LPUART11_CLK_ROOT

CCM_OBS_LPUART12_CLK_ROOT

CCM_OBS_LPI2C1_CLK_ROOT

CCM_OBS_LPI2C2_CLK_ROOT

CCM_OBS_LPI2C3_CLK_ROOT

CCM_OBS_LPI2C4_CLK_ROOT

CCM_OBS_LPI2C5_CLK_ROOT

CCM_OBS_LPI2C6_CLK_ROOT

CCM_OBS_LPSPI1_CLK_ROOT

CCM_OBS_LPSPI2_CLK_ROOT

CCM_OBS_LPSPI3_CLK_ROOT

CCM_OBS_LPSPI4_CLK_ROOT

CCM_OBS_LPSPI5_CLK_ROOT

CCM_OBS_LPSPI6_CLK_ROOT

CCM_OBS_EMV1_CLK_ROOT

CCM_OBS_EMV2_CLK_ROOT

CCM_OBS_ENET1_CLK_ROOT

CCM_OBS_ENET2_CLK_ROOT

CCM_OBS_ENET_QOS_CLK_ROOT

CCM_OBS_ENET_25M_CLK_ROOT

CCM_OBS_ENET_TIMER1_CLK_ROOT

CCM_OBS_ENET_TIMER2_CLK_ROOT

CCM_OBS_ENET_TIMER3_CLK_ROOT

CCM_OBS_USDHC1_CLK_ROOT

CCM_OBS_USDHC2_CLK_ROOT

CCM_OBS_ASRC_CLK_ROOT

CCM_OBS_MQS_CLK_ROOT

CCM_OBS_MIC_CLK_ROOT

CCM_OBS_SPDIF_CLK_ROOT

CCM_OBS_SAI1_CLK_ROOT

CCM_OBS_SAI2_CLK_ROOT

CCM_OBS_SAI3_CLK_ROOT

CCM_OBS_SAI4_CLK_ROOT

CCM_OBS_GC355_CLK_ROOT

CCM_OBS_LCDIF_CLK_ROOT

CCM_OBS_LCDIFV2_CLK_ROOT

CCM_OBS_MIPI_REF_CLK_ROOT

CCM_OBS_MIPI_ESC_CLK_ROOT

CCM_OBS_CSI2_CLK_ROOT

CCM_OBS_CSI2_ESC_CLK_ROOT

CCM_OBS_CSI2_UI_CLK_ROOT

CCM_OBS_CSI_CLK_ROOT

CCM_OBS_CCM_CKO1_CLK_ROOT

CCM_OBS_CCM_CKO2_CLK_ROOT

CCM_OBS_CM7_CORE_STCLKEN

CCM_OBS_CCM_FLEXRAM_CLK_ROOT

CCM_OBS_MIPI_DSI_TXESC

CCM_OBS_MIPI_DSI_RXESC

CCM_OBS_OSC_RC_16M

CCM_OBS_OSC_RC_48M

CCM_OBS_OSC_RC_48M_DIV2

CCM_OBS_OSC_RC_400M

CCM_OBS_OSC_24M_OUT

CCM_OBS_ARM_PLL_OUT

CCM_OBS_SYS_PLL2_OUT

CCM_OBS_SYS_PLL2_PFD0

CCM_OBS_SYS_PLL2_PFD1

CCM_OBS_SYS_PLL2_PFD2

CCM_OBS_SYS_PLL2_PFD3

CCM_OBS_SYS_PLL3_OUT

CCM_OBS_SYS_PLL3_DIV2

CCM_OBS_SYS_PLL3_PFD0

CCM_OBS_SYS_PLL3_PFD1

CCM_OBS_SYS_PLL3_PFD2

CCM_OBS_SYS_PLL3_PFD3

CCM_OBS_SYS_PLL1_OUT

CCM_OBS_SYS_PLL1_DIV2

CCM_OBS_SYS_PLL1_DIV5

CCM_OBS_PLL_AUDIO_OUT

CCM_OBS_PLL_VIDEO_OUT

CCM_OBS_DIV

clock_ip_name_t

CLOCK_GetCpuClkFreq

CLOCK_GetCoreSysClkFreq

For compatible with other platforms without CCM.

PLL_PFD_COUNT

static inline uint32_t CLOCK_GetRtcFreq(void)

Gets the RTC clock frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)

Set the control mode of 48MHz RC oscillator.

Parameters:

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

static inline void CLOCK_OSC_EnableOsc48M(bool enable)

Enable/disable 48MHz RC oscillator.

Parameters:

• enable – Used to enable or disable the 48MHz RC oscillator.

  • true Enable the 48MHz RC oscillator.

  • false Dissable the 48MHz RC oscillator.

static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)

Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator.

Parameters:

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable)

Enable/disable the 24MHz clock sourced from 48MHz RC oscillator.

Note

The 48MHz RC oscillator must be enabled before enabling this 24MHz clock.

Parameters:

• enable – Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator.

  • true Enable the 24MHz clock sourced from 48MHz.

  • false Disable the 24MHz clock sourced from 48MHz.

static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)

Set the control mode of 24MHz crystal oscillator.

Parameters:

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOsc24M(void)

Enable OSC 24Mhz.

This function enables OSC 24Mhz.

static inline void CLOCK_OSC_GateOsc24M(bool enableGate)

Gate/ungate the 24MHz crystal oscillator output.

Note

Gating the 24MHz crystal oscillator can save power.

Parameters:

• enableGate – Used to gate/ungate the 24MHz crystal oscillator.

  • true Gate the 24MHz crystal oscillator to save power.

  • false Ungate the 24MHz crystal oscillator.

void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode)

Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.

Parameters:

• workMode – The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)

Set the control mode of 400MHz RC oscillator.

Parameters:

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOscRc400M(void)

Enable OSC RC 400Mhz.

This function enables OSC RC 400Mhz.

static inline void CLOCK_OSC_GateOscRc400M(bool enableGate)

Gate/ungate 400MHz RC oscillator.

Parameters:

• enableGate – Used to gate/ungate 400MHz RC oscillator.

  • true Gate the 400MHz RC oscillator.

  • false Ungate the 400MHz RC oscillator.

void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim)

Trims OSC RC 400MHz.

Parameters:

• enable – Used to enable trim function.

• bypass – Bypass the trim function.

• trim – Trim value.

void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue)

Set the divide value for ref_clk to generate slow clock.

Note

slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters:

• divValue – The divide value to be set, the available range is 0~63.

void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount)

Set the target count for the fast clock.

Parameters:

• targetCount – The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis)

Set the negative and positive hysteresis value for the tuned clock.

Note

The hysteresis value should be set after the clock is tuned.

Parameters:

• negHysteresis – The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

• posHysteresis – The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass)

Bypass/un-bypass the tune logic.

Parameters:

• enableBypass – Used to control whether to bypass the turn logic.

  • true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.

  • false Use the output of tune logic to run the oscillator.

void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable)

Start/Stop the tune logic.

Parameters:

• enable – Used to start or stop the tune logic.

  • true Start tuning

  • false Stop tuning and reset the tuning logic.

void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze)

Freeze/Unfreeze the tuning value.

Parameters:

• enableFreeze – Used to control whether to freeze the tune value.

  • true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.

  • false Unfreezes and continues the tune operation.

void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue)

Set the 400MHz RC oscillator tune value when the tune logic is disabled.

Parameters:

• tuneValue – The tune value to determine the frequency of Oscillator.

void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior)

Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.

Note

The 1MHz clock is divided from 400M RC Oscillator.

Parameters:

• behavior – The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

void CLOCK_OSC_SetLocked1MHzCount(uint16_t count)

Set the count for the locked 1MHz clock out.

Parameters:

• count – Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void)

Check the error flag for locked 1MHz clock out.

Returns:

The error flag for locked 1MHz clock out.

• true The count value has been reached within one diviced ref clock period

• false No effect.

void CLOCK_OSC_ClearLocked1MHzErrorFlag(void)

Clear the error flag for locked 1MHz clock out.

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void)

Get current count for the fast clock during the tune process.

Returns:

The current count for the fast clock.

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void)

Get current tune value used by oscillator during tune process.

Returns:

The current tune value.

static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)

Set the control mode of 16MHz crystal oscillator.

Parameters:

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)

Configure the 16MHz oscillator.

Parameters:

• source – Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t.

• enablePowerSave – Enable/disable power save mode function at 16MHz OSC.

  • true Enable power save mode function at 16MHz osc.

  • false Disable power save mode function at 16MHz osc.

• enableClockOut – Enable/Disable clock output for 16MHz RCOSC.

  • true Enable clock output for 16MHz RCOSC.

  • false Disable clock output for 16MHz RCOSC.

void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)

Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

Parameters:

• config – configuration to set to PLL.

status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Arm PLL

Parameters:

• config – pll config structure

• freqInMhz – target frequency

status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz)

Initializes the Arm PLL with Specific Frequency (in Mhz).

This function initializes the Arm PLL with specific frequency

Parameters:

• freqInMhz – target frequency

void CLOCK_DeinitArmPll(void)

De-initialize the ARM PLL.

void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)

Calculate spread spectrum step and stop.

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/video/syspll1), the factor is denominator.

Parameters:

• factor – factor to calculate step/stop

• range – spread spectrum range

• mod – spread spectrum modulation frequency

• ss – calculated spread spectrum values

void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config)

Initialize the System PLL1.

This function initializes the System PLL1 with specific settings

Parameters:

• config – Configuration to set to PLL1.

void CLOCK_DeinitSysPll1(void)

De-initialize the System PLL1.

void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config)

Set System PLL1 output frequency in GPC mode.

Parameters:

• config – Pointer to System PLL1 configure structure.

void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config)

Initialize the System PLL2.

This function initializes the System PLL2 with specific settings

Parameters:

• config – Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

void CLOCK_DeinitSysPll2(void)

De-initialize the System PLL2.

bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd)

Check if Sys PLL2 PFD is enabled.

Note

Only useful in software control mode.

Parameters:

• pfd – PFD control name

Returns:

PFD bypass status.

• true: power on.

• false: power off.

void CLOCK_InitSysPll3(void)

Initialize the System PLL3.

This function initializes the System PLL3 with specific settings

void CLOCK_DeinitSysPll3(void)

De-initialize the System PLL3.

bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd)

Check if Sys PLL3 PFD is enabled.

Note

Only useful in software control mode.

Parameters:

• pfd – PFD control name

Returns:

PFD bypass status.

• true: power on.

• false: power off.

void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass)

PLL bypass setting.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

• bypass – Bypass the PLL.

  • true: Bypass the PLL.

  • false:Not bypass the PLL.

status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Audio/Video PLL.

Parameters:

• config – pll config structure

• freqInMhz – target frequency

status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)

Initializes the Audio PLL with Specific Frequency (in Mhz).

This function initializes the Audio PLL with specific frequency

Parameters:

• freqInMhz – target frequency

• ssEnable – enable spread spectrum or not

• ssRange – range spread spectrum range

• ssMod – spread spectrum modulation frequency

void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)

Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

Parameters:

• config – Configuration to set to PLL.

void CLOCK_DeinitAudioPll(void)

De-initialize the Audio PLL.

void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config)

Set Audio PLL output frequency in GPC mode.

Parameters:

• config – Pointer to clock_audio_pll_gpc_config_t structure.

status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)

Initializes the Video PLL with Specific Frequency (in Mhz).

This function initializes the Video PLL with specific frequency

Parameters:

• freqInMhz – target frequency

• ssEnable – enable spread spectrum or not

• ssRange – range spread spectrum range

• ssMod – spread spectrum modulation frequency

void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)

Initialize the video PLL.

This function configures the Video PLL with specific settings

Parameters:

• config – configuration to set to PLL.

void CLOCK_DeinitVideoPll(void)

De-initialize the Video PLL.

void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config)

Set Video PLL output frequency in GPC mode.

Parameters:

• config – Pointer to Vidoe PLL configure structure.

uint32_t CLOCK_GetPllFreq(clock_pll_t pll)

Get current PLL output frequency.

This function get current output frequency of specific PLL

Parameters:

• pll – pll name to get frequency.

Returns:

The PLL output frequency in hertz.

void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)

Initialize PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Note

It is recommended that PFD settings are kept between 12-35.

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – Which PFD clock to enable.

• frac – The PFD FRAC value.

void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)

De-initialize selected PLL PFD.

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – Which PFD clock to enable.

uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd)

Get current PFD output frequency.

This function get current output frequency of specific System PLL PFD

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – pfd name to get frequency.

Returns:

The PFD output frequency in hertz.

uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex)

bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters:

• src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.

• freq – USB HS does not care about the clock source, so this parameter is ignored.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters:

• src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.

• freq – USB HS does not care about the clock source, so this parameter is ignored.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters:

• src – USB HS PHY PLL clock source.

• freq – The frequency specified by src.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs0PhyPllClock(void)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters:

• src – USB HS PHY PLL clock source.

• freq – The frequency specified by src.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs1PhyPllClock(void)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name)

Lock low power and access control mode for this clock.

Note

When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• domainId – Domains that on the whitelist can change this clock.

static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)

Check whether this clock implement SetPoint control scheme.

Parameters:

• name – Clock source name, see clock_name_t.

Returns:

Clock source SetPoint implement status.

• true: SetPoint is implemented.

• false: SetPoint is not implemented.

static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)

Set this clock works in Unassigned Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue)

Set this clock works in SetPoint control Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• spValue – Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.

• stbyValue – Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• domainId – Domains that on the whitelist can change this clock.

• level1 (level0,) – Depend level of this clock.

static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level)

Set clock depend level for current accessing domain.

Note

This setting only take effects in CPU Low Power Mode.

Parameters:

• name – Clock source name, see clock_name_t.

• level – Depend level of this clock.

static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId)

Set this clock works in Domain Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• domainId – Domains that on the whitelist can change this clock.

static inline void CLOCK_ROOT_LockControlMode(clock_root_t name)

Lock low power and access control mode for this clock.

Note

When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

• domainId – Domains that on the whitelist can change this clock.

static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)

Check whether this clock implement SetPoint control scheme.

Parameters:

• name – Clock root name, see clock_root_t.

Returns:

Clock root SetPoint implement status.

• true: SetPoint is implemented.

• false: SetPoint is not implemented.

static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)

Set this clock works in Unassigned Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name, uint16_t spIndex, const clock_root_setpoint_config_t *config)

Configure one SetPoint for this clock.

Note

SetPoint value could only be changed in Unassigend Mode.

Parameters:

• name – Which clock root to set, see clock_root_t.

• spIndex – Which SetPoint of this clock root to set.

• config – SetPoint config, see clock_root_setpoint_config_t

static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name)

Enable SetPoint control for this clock root.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable)

Set this clock works in SetPoint controlled Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

• spTable – Point to the array that stores clock root settings for each setpoint. Note that the pointed array must have 16 elements.

static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

• domainId – Domains that on the whitelist can change this clock.

static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name)

Lock low power and access control mode for this clock.

Note

When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• domainId – Domains that on the whitelist can change this clock.

static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)

Check whether this clock implement SetPoint control scheme.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

Returns:

Clock gate SetPoint implement status.

• true: SetPoint is implemented.

• false: SetPoint is not implemented.

static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)

Set this clock works in Unassigned Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)

Set this clock works in SetPoint control Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• spValue – Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.

• stbyValue – Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• domainId – Domains that on the whitelist can change this clock.

• level1 (level0,) – Depend level of this clock.

static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level)

Set clock depend level for current accessing domain.

Note

This setting only take effects in CPU Low Power Mode.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• level – Depend level of this clock.

static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId)

Set this clock works in Domain Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• domainId – Domains that on the whitelist can change this clock.

bool clockOff

Turn off the clock.

uint16_t resetDiv

resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255.

uint8_t div0

Divide root clock by div0 + 1, valid range: 0 ~ 15.

clock_pll_post_div_t postDivider

Post divider.

uint32_t loopDivider

PLL loop divider. Valid range: 104-208.

uint8_t loopDivider

PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22

uint8_t src

Pll clock source, reference _clock_pll_clk_src

uint16_t stop

Spread spectrum stop value to get frequency change.

uint16_t step

Spread spectrum step value to get frequency change step.

uint32_t mfd

Denominator of spread spectrum

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

bool pllDiv2En

Enable Sys Pll1 divide-by-2 clock or not.

bool pllDiv5En

Enable Sys Pll1 divide-by-5 clock or not.

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

uint8_t loopDivider

PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

uint8_t postDivider

Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.

uint32_t numerator

30 bit numerator of fractional loop divider.

uint32_t denominator

30 bit denominator of fractional loop divider

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

uint8_t loopDivider

PLL loop divider.

uint32_t numerator

30 bit numerator of fractional loop divider.

uint32_t denominator

30 bit denominator of fractional loop divider

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

bool enableClkOutput

Power on and enable PLL clock output for ENET0 (ref_enetpll0).

bool enableClkOutput25M

Power on and enable PLL clock output for ENET2 (ref_enetpll2).

uint8_t loopDivider

Controls the frequency of the ENET0 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

uint8_t src

Pll clock source, reference _clock_pll_clk_src

bool enableClkOutput1

Power on and enable PLL clock output for ENET1 (ref_enetpll1).

uint8_t loopDivider1

Controls the frequency of the ENET1 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

bool clockOff

uint8_t mux

See clock_root_mux_source_t for details.

uint8_t div

it’s the actual divider

uint8_t grade

Indicate speed grade for each SetPoint

bool clockOff

uint8_t mux

See clock_root_mux_source_t for details.

uint8_t div

it’s the actual divider

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

struct _clock_group_config

#include <fsl_clock.h>

The structure used to configure clock group.

struct _clock_arm_pll_config

#include <fsl_clock.h>

PLL configuration for ARM.

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

struct _clock_usb_pll_config

#include <fsl_clock.h>

PLL configuration for USB.

struct _clock_pll_ss_config

#include <fsl_clock.h>

Spread specturm configure Pll.

struct _clock_sys_pll2_config

#include <fsl_clock.h>

PLL configure for Sys Pll2.

struct _clock_sys_pll1_config

#include <fsl_clock.h>

PLL configure for Sys Pll1.

struct _clock_audio_pll_config

#include <fsl_clock.h>

PLL configuration for AUDIO and VIDEO.

struct _clock_audio_pll_gpc_config

#include <fsl_clock.h>

PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.

struct _clock_enet_pll_config

#include <fsl_clock.h>

PLL configuration for ENET.

struct _clock_root_config_t

#include <fsl_clock.h>

Clock root configuration.

struct _clock_root_setpoint_config_t

#include <fsl_clock.h>

Clock root configuration in SetPoint Mode.

MIPI CSI2 RX: MIPI CSI2 RX Driver

FSL_CSI2RX_DRIVER_VERSION

CSI2RX driver version.

enum _csi2rx_data_lane

CSI2RX data lanes.

Values:

enumerator kCSI2RX_DataLane0

Data lane 0.

enumerator kCSI2RX_DataLane1

Data lane 1.

enumerator kCSI2RX_DataLane2

Data lane 2.

enumerator kCSI2RX_DataLane3

Data lane 3.

enum _csi2rx_payload

CSI2RX payload type.

Values:

enumerator kCSI2RX_PayloadGroup0Null

NULL.

enumerator kCSI2RX_PayloadGroup0Blank

Blank.

enumerator kCSI2RX_PayloadGroup0Embedded

Embedded.

enumerator kCSI2RX_PayloadGroup0YUV420_8Bit

Legacy YUV420 8 bit.

enumerator kCSI2RX_PayloadGroup0YUV422_8Bit

YUV422 8 bit.

enumerator kCSI2RX_PayloadGroup0YUV422_10Bit

YUV422 10 bit.

enumerator kCSI2RX_PayloadGroup0RGB444

RGB444.

enumerator kCSI2RX_PayloadGroup0RGB555

RGB555.

enumerator kCSI2RX_PayloadGroup0RGB565

RGB565.

enumerator kCSI2RX_PayloadGroup0RGB666

RGB666.

enumerator kCSI2RX_PayloadGroup0RGB888

RGB888.

enumerator kCSI2RX_PayloadGroup0Raw6

Raw 6.

enumerator kCSI2RX_PayloadGroup0Raw7

Raw 7.

enumerator kCSI2RX_PayloadGroup0Raw8

Raw 8.

enumerator kCSI2RX_PayloadGroup0Raw10

Raw 10.

enumerator kCSI2RX_PayloadGroup0Raw12

Raw 12.

enumerator kCSI2RX_PayloadGroup0Raw14

Raw 14.

enumerator kCSI2RX_PayloadGroup1UserDefined1

User defined 8-bit data type 1, 0x30.

enumerator kCSI2RX_PayloadGroup1UserDefined2

User defined 8-bit data type 2, 0x31.

enumerator kCSI2RX_PayloadGroup1UserDefined3

User defined 8-bit data type 3, 0x32.

enumerator kCSI2RX_PayloadGroup1UserDefined4

User defined 8-bit data type 4, 0x33.

enumerator kCSI2RX_PayloadGroup1UserDefined5

User defined 8-bit data type 5, 0x34.

enumerator kCSI2RX_PayloadGroup1UserDefined6

User defined 8-bit data type 6, 0x35.

enumerator kCSI2RX_PayloadGroup1UserDefined7

User defined 8-bit data type 7, 0x36.

enumerator kCSI2RX_PayloadGroup1UserDefined8

User defined 8-bit data type 8, 0x37.

enum _csi2rx_bit_error

MIPI CSI2RX bit errors.

Values:

enumerator kCSI2RX_BitErrorEccTwoBit

ECC two bit error has occurred.

enumerator kCSI2RX_BitErrorEccOneBit

ECC one bit error has occurred.

enum _csi2rx_ppi_error

MIPI CSI2RX PPI error types.

Values:

enumerator kCSI2RX_PpiErrorSotHs

CSI2RX DPHY PPI error ErrSotHS.

enumerator kCSI2RX_PpiErrorSotSyncHs

CSI2RX DPHY PPI error ErrSotSync_HS.

enumerator kCSI2RX_PpiErrorEsc

CSI2RX DPHY PPI error ErrEsc.

enumerator kCSI2RX_PpiErrorSyncEsc

CSI2RX DPHY PPI error ErrSyncEsc.

enumerator kCSI2RX_PpiErrorControl

CSI2RX DPHY PPI error ErrControl.

enum _csi2rx_interrupt

MIPI CSI2RX interrupt.

Values:

enumerator kCSI2RX_InterruptCrcError

enumerator kCSI2RX_InterruptEccOneBitError

enumerator kCSI2RX_InterruptEccTwoBitError

enumerator kCSI2RX_InterruptUlpsStatusChange

enumerator kCSI2RX_InterruptErrorSotHs

enumerator kCSI2RX_InterruptErrorSotSyncHs

enumerator kCSI2RX_InterruptErrorEsc

enumerator kCSI2RX_InterruptErrorSyncEsc

enumerator kCSI2RX_InterruptErrorControl

enum _csi2rx_ulps_status

MIPI CSI2RX D-PHY ULPS state.

Values:

enumerator kCSI2RX_ClockLaneUlps

Clock lane is in ULPS state.

enumerator kCSI2RX_DataLane0Ulps

Data lane 0 is in ULPS state.

enumerator kCSI2RX_DataLane1Ulps

Data lane 1 is in ULPS state.

enumerator kCSI2RX_DataLane2Ulps

Data lane 2 is in ULPS state.

enumerator kCSI2RX_DataLane3Ulps

Data lane 3 is in ULPS state.

enumerator kCSI2RX_ClockLaneMark

Clock lane is in mark state.

enumerator kCSI2RX_DataLane0Mark

Data lane 0 is in mark state.

enumerator kCSI2RX_DataLane1Mark

Data lane 1 is in mark state.

enumerator kCSI2RX_DataLane2Mark

Data lane 2 is in mark state.

enumerator kCSI2RX_DataLane3Mark

Data lane 3 is in mark state.

typedef struct _csi2rx_config csi2rx_config_t

CSI2RX configuration.

typedef enum _csi2rx_ppi_error csi2rx_ppi_error_t

MIPI CSI2RX PPI error types.

void CSI2RX_Init(MIPI_CSI2RX_Type *base, const csi2rx_config_t *config)

Enables and configures the CSI2RX peripheral module.

Parameters:

• base – CSI2RX peripheral address.

• config – CSI2RX module configuration structure.

void CSI2RX_Deinit(MIPI_CSI2RX_Type *base)

Disables the CSI2RX peripheral module.

Parameters:

• base – CSI2RX peripheral address.

static inline uint32_t CSI2RX_GetBitError(MIPI_CSI2RX_Type *base)

Gets the MIPI CSI2RX bit error status.

This function gets the RX bit error status, the return value could be compared with _csi2rx_bit_error. If one bit ECC error detected, the return value could be passed to the function CSI2RX_GetEccBitErrorPosition to get the position of the ECC error bit.

Example:

uint32_t bitError;
uint32_t bitErrorPosition;

bitError = CSI2RX_GetBitError(MIPI_CSI2RX);

if (kCSI2RX_BitErrorEccTwoBit & bitError)
{
    Two bits error;
}
else if (kCSI2RX_BitErrorEccOneBit & bitError)
{
    One bits error;
    bitErrorPosition = CSI2RX_GetEccBitErrorPosition(bitError);
}

Parameters:

• base – CSI2RX peripheral address.

Returns:

The RX bit error status.

static inline uint32_t CSI2RX_GetEccBitErrorPosition(uint32_t bitError)

Get ECC one bit error bit position.

If CSI2RX_GetBitError detects ECC one bit error, this function could extract the error bit position from the return value of CSI2RX_GetBitError.

Parameters:

• bitError – The bit error returned by CSI2RX_GetBitError.

Returns:

The position of error bit.

static inline uint32_t CSI2RX_GetUlpsStatus(MIPI_CSI2RX_Type *base)

Gets the MIPI CSI2RX D-PHY ULPS status.

Example to check whether data lane 0 is in ULPS status.

uint32_t status = CSI2RX_GetUlpsStatus(MIPI_CSI2RX);

if (kCSI2RX_DataLane0Ulps & status)
{
    Data lane 0 is in ULPS status.
}

Parameters:

• base – CSI2RX peripheral address.

Returns:

The MIPI CSI2RX D-PHY ULPS status, it is OR’ed value or _csi2rx_ulps_status.

static inline uint32_t CSI2RX_GetPpiErrorDataLanes(MIPI_CSI2RX_Type *base, csi2rx_ppi_error_t errorType)

Gets the MIPI CSI2RX D-PHY PPI error lanes.

This function checks the PPI error occurred on which data lanes, the returned value is OR’ed value of csi2rx_ppi_error_t. For example, if the ErrSotHS is detected, to check the ErrSotHS occurred on which data lanes, use like this:

uint32_t errorDataLanes = CSI2RX_GetPpiErrorDataLanes(MIPI_CSI2RX, kCSI2RX_PpiErrorSotHs);

if (kCSI2RX_DataLane0 & errorDataLanes)
{
    ErrSotHS occurred on data lane 0.
}

if (kCSI2RX_DataLane1 & errorDataLanes)
{
    ErrSotHS occurred on data lane 1.
}

Parameters:

• base – CSI2RX peripheral address.

• errorType – What kind of error to check.

Returns:

The data lane mask that error errorType occurred.

static inline void CSI2RX_EnableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)

Enable the MIPI CSI2RX interrupts.

This function enables the MIPI CSI2RX interrupts. The interrupts to enable are passed in as an OR’ed value of _csi2rx_interrupt. For example, to enable one bit and two bit ECC error interrupts, use like this:

CSI2RX_EnableInterrupts(MIPI_CSI2RX, kCSI2RX_InterruptEccOneBitError | kCSI2RX_InterruptEccTwoBitError);

Parameters:

• base – CSI2RX peripheral address.

• mask – OR’ed value of _csi2rx_interrupt.

static inline void CSI2RX_DisableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)

Disable the MIPI CSI2RX interrupts.

This function disables the MIPI CSI2RX interrupts. The interrupts to disable are passed in as an OR’ed value of _csi2rx_interrupt. For example, to disable one bit and two bit ECC error interrupts, use like this:

CSI2RX_DisableInterrupts(MIPI_CSI2RX, kCSI2RX_InterruptEccOneBitError | kCSI2RX_InterruptEccTwoBitError);

Parameters:

• base – CSI2RX peripheral address.

• mask – OR’ed value of _csi2rx_interrupt.

static inline uint32_t CSI2RX_GetInterruptStatus(MIPI_CSI2RX_Type *base)

Get the MIPI CSI2RX interrupt status.

This function returns the MIPI CSI2RX interrupts status as an OR’ed value of _csi2rx_interrupt.

Parameters:

• base – CSI2RX peripheral address.

Returns:

OR’ed value of _csi2rx_interrupt.

CSI2RX_REG_CFG_NUM_LANES(base)

CSI2RX_REG_CFG_DISABLE_DATA_LANES(base)

CSI2RX_REG_BIT_ERR(base)

CSI2RX_REG_IRQ_STATUS(base)

CSI2RX_REG_IRQ_MASK(base)

CSI2RX_REG_ULPS_STATUS(base)

CSI2RX_REG_PPI_ERRSOT_HS(base)

CSI2RX_REG_PPI_ERRSOTSYNC_HS(base)

CSI2RX_REG_PPI_ERRESC(base)

CSI2RX_REG_PPI_ERRSYNCESC(base)

CSI2RX_REG_PPI_ERRCONTROL(base)

CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base)

CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base)

CSI2RX_REG_CFG_IGNORE_VC(base)

CSI2RX_REG_CFG_VID_VC(base)

CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base)

CSI2RX_REG_CFG_VID_VSYNC(base)

CSI2RX_REG_CFG_VID_HSYNC_FP(base)

CSI2RX_REG_CFG_VID_HSYNC(base)

CSI2RX_REG_CFG_VID_HSYNC_BP(base)

MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK

MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK

struct _csi2rx_config

#include <fsl_mipi_csi2rx.h>

CSI2RX configuration.

Public Members

uint8_t laneNum

Number of active lanes used for receiving data.

uint8_t tHsSettle_EscClk

Number of rx_clk_esc clock periods for T_HS_SETTLE. The T_HS_SETTLE should be in the range of 85ns + 6UI to 145ns + 10UI.

CSI: CMOS Sensor Interface

status_t CSI_Init(CSI_Type *base, const csi_config_t *config)

Initialize the CSI.

This function enables the CSI peripheral clock, and resets the CSI registers.

Parameters:

• base – CSI peripheral base address.

• config – Pointer to the configuration structure.

Return values:

• kStatus_Success – Initialize successfully.

• kStatus_InvalidArgument – Initialize failed because of invalid argument.

void CSI_Deinit(CSI_Type *base)

De-initialize the CSI.

This function disables the CSI peripheral clock.

Parameters:

• base – CSI peripheral base address.

void CSI_Reset(CSI_Type *base)

Reset the CSI.

This function resets the CSI peripheral registers to default status.

Parameters:

• base – CSI peripheral base address.

void CSI_GetDefaultConfig(csi_config_t *config)

Get the default configuration for to initialize the CSI.

The default configuration value is:

config->width = 320U;
config->height = 240U;
config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
config->bytesPerPixel = 2U;
config->linePitch_Bytes = 320U * 2U;
config->workMode = kCSI_GatedClockMode;
config->dataBus = kCSI_DataBus8Bit;
config->useExtVsync = true;

Parameters:

• config – Pointer to the CSI configuration.

void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)

Clear the CSI FIFO.

This function clears the CSI FIFO.

Parameters:

• base – CSI peripheral base address.

• fifo – The FIFO to clear.

void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)

Reflash the CSI FIFO DMA.

This function reflashes the CSI FIFO DMA.

For RXFIFO, there are two frame buffers. When the CSI module started, it saves the frames to frame buffer 0 then frame buffer 1, the two buffers will be written by turns. After reflash DMA using this function, the CSI is reset to save frame to buffer 0.

Parameters:

• base – CSI peripheral base address.

• fifo – The FIFO DMA to reflash.

void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)

Enable or disable the CSI FIFO DMA request.

Parameters:

• base – CSI peripheral base address.

• fifo – The FIFO DMA reques to enable or disable.

• enable – True to enable, false to disable.

static inline void CSI_Start(CSI_Type *base)

Start to receive data.

Parameters:

• base – CSI peripheral base address.

static inline void CSI_Stop(CSI_Type *base)

Stop to receiving data.

Parameters:

• base – CSI peripheral base address.

void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)

Set the RX frame buffer address.

Parameters:

• base – CSI peripheral base address.

• index – Buffer index.

• addr – Frame buffer address to set.

void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)

Enables CSI interrupt requests.

Parameters:

• base – CSI peripheral base address.

• mask – The interrupts to enable, pass in as OR’ed value of _csi_interrupt_enable.

void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)

Disable CSI interrupt requests.

Parameters:

• base – CSI peripheral base address.

• mask – The interrupts to disable, pass in as OR’ed value of _csi_interrupt_enable.

static inline uint32_t CSI_GetStatusFlags(CSI_Type *base)

Gets the CSI status flags.

Parameters:

• base – CSI peripheral base address.

Returns:

status flag, it is OR’ed value of _csi_flags.

static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask)

Clears the CSI status flag.

The flags to clear are passed in as OR’ed value of _csi_flags. The following flags are cleared automatically by hardware:

• kCSI_RxFifoFullFlag,

• kCSI_StatFifoFullFlag,

• kCSI_Field0PresentFlag,

• kCSI_Field1PresentFlag,

• kCSI_RxFifoDataReadyFlag,

Parameters:

• base – CSI peripheral base address.

• statusMask – The status flags mask, OR’ed value of _csi_flags.

status_t CSI_TransferCreateHandle(CSI_Type *base, csi_handle_t *handle, csi_transfer_callback_t callback, void *userData)

Initializes the CSI handle.

This function initializes CSI handle, it should be called before any other CSI transactional functions.

Parameters:

• base – CSI peripheral base address.

• handle – Pointer to the handle structure.

• callback – Callback function for CSI transfer.

• userData – Callback function parameter.

Return values:

kStatus_Success – Handle created successfully.

status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)

Start the transfer using transactional functions.

When the empty frame buffers have been submit to CSI driver using function CSI_TransferSubmitEmptyBuffer, user could call this function to start the transfer. The incoming frame will be saved to the empty frame buffer, and user could be optionally notified through callback function.

Parameters:

• base – CSI peripheral base address.

• handle – Pointer to the handle structure.

Return values:

• kStatus_Success – Started successfully.

• kStatus_CSI_NoEmptyBuffer – Could not start because no empty frame buffer in queue.

status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)

Stop the transfer using transactional functions.

The driver does not clean the full frame buffers in queue. In other words, after calling this function, user still could get the full frame buffers in queue using function CSI_TransferGetFullBuffer.

Parameters:

• base – CSI peripheral base address.

• handle – Pointer to the handle structure.

Return values:

kStatus_Success – Stoped successfully.

status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)

Submit empty frame buffer to queue.

This function could be called before CSI_TransferStart or after CSI_TransferStart. If there is no room in queue to store the empty frame buffer, this function returns error.

Parameters:

• base – CSI peripheral base address.

• handle – Pointer to the handle structure.

• frameBuffer – Empty frame buffer to submit.

Return values:

• kStatus_Success – Started successfully.

• kStatus_CSI_QueueFull – Could not submit because there is no room in queue.

status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)

Get one full frame buffer from queue.

After the transfer started using function CSI_TransferStart, the incoming frames will be saved to the empty frame buffers in queue. This function gets the full-filled frame buffer from the queue. If there is no full frame buffer in queue, this function returns error.

Parameters:

• base – CSI peripheral base address.

• handle – Pointer to the handle structure.

• frameBuffer – Full frame buffer.

Return values:

• kStatus_Success – Started successfully.

• kStatus_CSI_NoFullBuffer – There is no full frame buffer in queue.

void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)

CSI IRQ handle function.

This function handles the CSI IRQ request to work with CSI driver transactional APIs.

Parameters:

• base – CSI peripheral base address.

• handle – CSI handle pointer.

FSL_CSI_DRIVER_VERSION

Error codes for the CSI driver.

Values:

enumerator kStatus_CSI_NoEmptyBuffer

No empty frame buffer in queue to load to CSI.

enumerator kStatus_CSI_NoFullBuffer

No full frame buffer in queue to read out.

enumerator kStatus_CSI_QueueFull

Queue is full, no room to save new empty buffer.

enumerator kStatus_CSI_FrameDone

New frame received and saved to queue.

enum _csi_work_mode

CSI work mode.

The CCIR656 interlace mode is not supported currently.

Values:

enumerator kCSI_GatedClockMode

HSYNC, VSYNC, and PIXCLK signals are used.

enumerator kCSI_NonGatedClockMode

VSYNC, and PIXCLK signals are used.

enumerator kCSI_CCIR656ProgressiveMode

CCIR656 progressive mode.

enum _csi_data_bus

CSI data bus witdh.

Values:

enumerator kCSI_DataBus8Bit

8-bit data bus.

enumerator kCSI_DataBus16Bit

16-bit data bus.

enumerator kCSI_DataBus24Bit

24-bit data bus.

enum _csi_polarity_flags

CSI signal polarity.

Values:

enumerator kCSI_HsyncActiveLow

HSYNC is active low.

enumerator kCSI_HsyncActiveHigh

HSYNC is active high.

enumerator kCSI_DataLatchOnRisingEdge

Pixel data latched at rising edge of pixel clock.

enumerator kCSI_DataLatchOnFallingEdge

Pixel data latched at falling edge of pixel clock.

enumerator kCSI_VsyncActiveHigh

VSYNC is active high.

enumerator kCSI_VsyncActiveLow

VSYNC is active low.

enum _csi_fifo

The CSI FIFO, used for FIFO operation.

Values:

enumerator kCSI_RxFifo

RXFIFO.

enumerator kCSI_StatFifo

STAT FIFO.

enumerator kCSI_AllFifo

Both RXFIFO and STAT FIFO.

enum _csi_interrupt_enable

CSI feature interrupt source.

Values:

enumerator kCSI_EndOfFrameInterruptEnable

End of frame interrupt enable.

enumerator kCSI_ChangeOfFieldInterruptEnable

Change of field interrupt enable.

enumerator kCSI_StatFifoOverrunInterruptEnable

STAT FIFO overrun interrupt enable.

enumerator kCSI_RxFifoOverrunInterruptEnable

RXFIFO overrun interrupt enable.

enumerator kCSI_StatFifoDmaDoneInterruptEnable

STAT FIFO DMA done interrupt enable.

enumerator kCSI_StatFifoFullInterruptEnable

STAT FIFO full interrupt enable.

enumerator kCSI_RxBuffer1DmaDoneInterruptEnable

RX frame buffer 1 DMA transfer done.

enumerator kCSI_RxBuffer0DmaDoneInterruptEnable

RX frame buffer 0 DMA transfer done.

enumerator kCSI_RxFifoFullInterruptEnable

RXFIFO full interrupt enable.

enumerator kCSI_StartOfFrameInterruptEnable

Start of frame (SOF) interrupt enable.

enumerator kCSI_EccErrorInterruptEnable

ECC error detection interrupt enable.

enumerator kCSI_AhbResErrorInterruptEnable

AHB response Error interrupt enable.

enumerator kCSI_BaseAddrChangeErrorInterruptEnable

The DMA output buffer base address changes before DMA completed.

enumerator kCSI_Field0DoneInterruptEnable

Field 0 done interrupt enable.

enumerator kCSI_Field1DoneInterruptEnable

Field 1 done interrupt enable.

enum _csi_flags

CSI status flags.

The following status register flags can be cleared:

• kCSI_EccErrorFlag

• kCSI_AhbResErrorFlag

• kCSI_ChangeOfFieldFlag

• kCSI_StartOfFrameFlag

• kCSI_EndOfFrameFlag

• kCSI_RxBuffer1DmaDoneFlag

• kCSI_RxBuffer0DmaDoneFlag

• kCSI_StatFifoDmaDoneFlag

• kCSI_StatFifoOverrunFlag

• kCSI_RxFifoOverrunFlag

• kCSI_Field0DoneFlag

• kCSI_Field1DoneFlag

• kCSI_BaseAddrChangeErrorFlag

Values:

enumerator kCSI_RxFifoDataReadyFlag

RXFIFO data ready.

enumerator kCSI_EccErrorFlag

ECC error detected.

enumerator kCSI_AhbResErrorFlag

Hresponse (AHB bus response) Error.

enumerator kCSI_ChangeOfFieldFlag

Change of field.

enumerator kCSI_Field0PresentFlag

Field 0 present in CCIR mode.

enumerator kCSI_Field1PresentFlag

Field 1 present in CCIR mode.

enumerator kCSI_StartOfFrameFlag

Start of frame (SOF) detected.

enumerator kCSI_EndOfFrameFlag

End of frame (EOF) detected.

enumerator kCSI_RxFifoFullFlag

RXFIFO full (Number of data reaches trigger level).

enumerator kCSI_RxBuffer1DmaDoneFlag

RX frame buffer 1 DMA transfer done.

enumerator kCSI_RxBuffer0DmaDoneFlag

RX frame buffer 0 DMA transfer done.

enumerator kCSI_StatFifoFullFlag

STAT FIFO full (Reach trigger level).

enumerator kCSI_StatFifoDmaDoneFlag

STAT FIFO DMA transfer done.

enumerator kCSI_StatFifoOverrunFlag

STAT FIFO overrun.

enumerator kCSI_RxFifoOverrunFlag

RXFIFO overrun.

enumerator kCSI_Field0DoneFlag

Field 0 transfer done.

enumerator kCSI_Field1DoneFlag

Field 1 transfer done.

enumerator kCSI_BaseAddrChangeErrorFlag

The DMA output buffer base address changes before DMA completed.

typedef enum _csi_work_mode csi_work_mode_t

CSI work mode.

The CCIR656 interlace mode is not supported currently.

typedef enum _csi_data_bus csi_data_bus_t

CSI data bus witdh.

typedef struct _csi_config csi_config_t

Configuration to initialize the CSI module.

typedef enum _csi_fifo csi_fifo_t

The CSI FIFO, used for FIFO operation.

typedef struct _csi_handle csi_handle_t

typedef void (*csi_transfer_callback_t)(CSI_Type *base, csi_handle_t *handle, status_t status, void *userData)

CSI transfer callback function.

When a new frame is received and saved to the frame buffer queue, the callback is called and the pass the status kStatus_CSI_FrameDone to upper layer.

CSI_REG_CR1(base)

CSI_REG_CR2(base)

CSI_REG_CR3(base)

CSI_REG_CR18(base)

CSI_REG_SR(base)

CSI_REG_DMASA_FB1(base)

CSI_REG_DMASA_FB2(base)

CSI_REG_IMAG_PARA(base)

CSI_REG_FBUF_PARA(base)

CSI_DRIVER_QUEUE_SIZE

Size of the frame buffer queue used in CSI transactional function.

CSI_DRIVER_FRAG_MODE

Enable fragment capture function or not.

CSI_CR1_INT_EN_MASK

CSI_CR3_INT_EN_MASK

CSI_CR18_INT_EN_MASK

struct _csi_config

#include <fsl_csi.h>

Configuration to initialize the CSI module.

Public Members

uint16_t width

Pixels of the input frame.

uint16_t height

Lines of the input frame.

uint32_t polarityFlags

Timing signal polarity flags, OR’ed value of _csi_polarity_flags.

uint8_t bytesPerPixel

Bytes per pixel, valid values are:

• 2: Used for RGB565, YUV422, and so on.

• 4: Used for XRGB8888, XYUV444, and so on.

uint16_t linePitch_Bytes

Frame buffer line pitch, must be 8-byte aligned.

csi_work_mode_t workMode

CSI work mode.

csi_data_bus_t dataBus

Data bus width.

bool useExtVsync

In CCIR656 progressive mode, set true to use external VSYNC signal, set false to use internal VSYNC signal decoded from SOF.

struct buf_queue_t

#include <fsl_csi.h>

struct _csi_handle

#include <fsl_csi.h>

CSI handle structure.

Please see the user guide for the details of the CSI driver queue mechanism.

Public Members

volatile uint8_t activeBufferNum

How many frame buffers are in progress currently.

volatile uint8_t dmaDoneBufferIdx

Index of the current full-filled framebuffer.

volatile bool transferStarted

User has called CSI_TransferStart to start frame receiving.

csi_transfer_callback_t callback

Callback function.

void *userData

CSI callback function parameter.

DAC12: 12-bit Digital-to-Analog Converter Driver

void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info)

Get hardware information about this module.

Parameters:

• base – DAC12 peripheral base address.

• info – Pointer to info structure, see to dac12_hardware_info_t.

void DAC12_Init(DAC_Type *base, const dac12_config_t *config)

Initialize the DAC12 module.

Parameters:

• base – DAC12 peripheral base address.

• config – Pointer to configuration structure, see to dac12_config_t.

void DAC12_GetDefaultConfig(dac12_config_t *config)

Initializes the DAC12 user configuration structure.

This function initializes the user configuration structure to a default value. The default values are:

config->fifoWatermarkLevel = 0U;
config->fifoWorkMode = kDAC12_FIFODisabled;
config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1;
config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode;
config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0;
config->speedMode = kDAC12_SpeedLowMode;
config->speedMode = false;
config->currentReferenceInternalTrimValue = 0x4;

Parameters:

• config – Pointer to the configuration structure. See “dac12_config_t”.

void DAC12_Deinit(DAC_Type *base)

De-initialize the DAC12 module.

Parameters:

• base – DAC12 peripheral base address.

static inline void DAC12_Enable(DAC_Type *base, bool enable)

Enable the DAC12’s converter or not.

Parameters:

• base – DAC12 peripheral base address.

• enable – Enable the DAC12’s converter or not.

static inline void DAC12_ResetConfig(DAC_Type *base)

Reset all internal logic and registers.

Parameters:

• base – DAC12 peripheral base address.

static inline void DAC12_ResetFIFO(DAC_Type *base)

Reset the FIFO pointers.

FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers to the same address to reset the FIFO as empty.

Parameters:

• base – DAC12 peripheral base address.

static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base)

Get status flags.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Mask of current status flags. See to _dac12_status_flags.

static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags)

Clear status flags.

Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to target chip’s reference manual document.

Parameters:

• base – DAC12 peripheral base address.

• flags – Mask of status flags to be cleared. See to _dac12_status_flags.

static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – DAC12 peripheral base address.

• mask – Mask value of interrupts to be enabled. See to _dac12_interrupt_enable.

static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – DAC12 peripheral base address.

• mask – Mask value of interrupts to be disabled. See to _dac12_interrupt_enable.

static inline void DAC12_EnableDMA(DAC_Type *base, bool enable)

Enable DMA or not.

When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.

static inline void DAC12_SetData(DAC_Type *base, uint32_t value)

Set data into the entry of FIFO buffer.

When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion without trigger support. When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored into the FIFO buffer.

Parameters:

• base – DAC12 peripheral base address.

• value – Setting value into FIFO buffer.

static inline void DAC12_DoSoftwareTrigger(DAC_Type *base)

Do trigger the FIFO by software.

When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the data in the entry pointed by read pointer would be converted as new output.

Parameters:

• base – DAC12 peripheral base address.

static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base)

Get the current read pointer of FIFO.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Read pointer index of FIFO buffer.

static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base)

Get the current write pointer of FIFO.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Write pointer index of FIFO buffer

FSL_DAC12_DRIVER_VERSION

DAC12 driver version 2.1.1.

enum _dac12_status_flags

DAC12 flags.

Values:

enumerator kDAC12_OverflowFlag

FIFO overflow status flag, which indicates that more data has been written into FIFO than it can hold.

enumerator kDAC12_UnderflowFlag

FIFO underflow status flag, which means that there is a new trigger after the FIFO is nearly empty.

enumerator kDAC12_WatermarkFlag

FIFO wartermark status flag, which indicates the remaining FIFO data is less than the watermark setting.

enumerator kDAC12_NearlyEmptyFlag

FIFO nearly empty flag, which means there is only one data remaining in FIFO.

enumerator kDAC12_FullFlag

FIFO full status flag, which means that the FIFO read pointer equals the write pointer, as the write pointer increase.

enum _dac12_interrupt_enable

DAC12 interrupts.

Values:

enumerator kDAC12_UnderOrOverflowInterruptEnable

Underflow and overflow interrupt enable.

enumerator kDAC12_WatermarkInterruptEnable

Watermark interrupt enable.

enumerator kDAC12_NearlyEmptyInterruptEnable

Nearly empty interrupt enable.

enumerator kDAC12_FullInterruptEnable

Full interrupt enable.

enum _dac12_fifo_size_info

DAC12 FIFO size information provided by hardware.

Values:

enumerator kDAC12_FIFOSize2

FIFO depth is 2.

enumerator kDAC12_FIFOSize4

FIFO depth is 4.

enumerator kDAC12_FIFOSize8

FIFO depth is 8.

enumerator kDAC12_FIFOSize16

FIFO depth is 16.

enumerator kDAC12_FIFOSize32

FIFO depth is 32.

enumerator kDAC12_FIFOSize64

FIFO depth is 64.

enumerator kDAC12_FIFOSize128

FIFO depth is 128.

enumerator kDAC12_FIFOSize256

FIFO depth is 256.

enum _dac12_fifo_work_mode

DAC12 FIFO work mode.

Values:

enumerator kDAC12_FIFODisabled

FIFO disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.

enumerator kDAC12_FIFOWorkAsNormalMode

Data will first read from FIFO to buffer then go to conversion.

enumerator kDAC12_FIFOWorkAsSwingMode

In Swing mode, the FIFO must be set up to be full. In Swing back mode, a trigger changes the read pointer to make it swing between the FIFO Full and Nearly Empty state. That is, the trigger increases the read pointer till FIFO is nearly empty and decreases the read pointer till the FIFO is full.

enum _dac12_reference_voltage_source

DAC12 reference voltage source.

Values:

enumerator kDAC12_ReferenceVoltageSourceAlt1

The DAC selects DACREF_1 as the reference voltage.

enumerator kDAC12_ReferenceVoltageSourceAlt2

The DAC selects DACREF_2 as the reference voltage.

enum _dac12_fifo_trigger_mode

DAC12 FIFO trigger mode.

Values:

enumerator kDAC12_FIFOTriggerByHardwareMode

Buffer would be triggered by hardware.

enumerator kDAC12_FIFOTriggerBySoftwareMode

Buffer would be triggered by software.

enum _dac12_reference_current_source

DAC internal reference current source.

Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.

Values:

enumerator kDAC12_ReferenceCurrentSourceDisabled

None of reference current source is enabled.

enumerator kDAC12_ReferenceCurrentSourceAlt0

Use the internal reference current generated by the module itself.

enumerator kDAC12_ReferenceCurrentSourceAlt1

Use the ZTC(Zero Temperature Coefficient) reference current generated by on-chip power management module.

enumerator kDAC12_ReferenceCurrentSourceAlt2

Use the PTAT(Proportional To Absolution Temperature) reference current generated by power management module.

enum _dac12_speed_mode

DAC analog buffer speed mode for conversion.

Values:

enumerator kDAC12_SpeedLowMode

Low speed mode.

enumerator kDAC12_SpeedMiddleMode

Middle speed mode.

enumerator kDAC12_SpeedHighMode

High speed mode.

typedef enum _dac12_fifo_size_info dac12_fifo_size_info_t

DAC12 FIFO size information provided by hardware.

typedef enum _dac12_fifo_work_mode dac12_fifo_work_mode_t

DAC12 FIFO work mode.

typedef enum _dac12_reference_voltage_source dac12_reference_voltage_source_t

DAC12 reference voltage source.

typedef enum _dac12_fifo_trigger_mode dac12_fifo_trigger_mode_t

DAC12 FIFO trigger mode.

typedef enum _dac12_reference_current_source dac12_reference_current_source_t

DAC internal reference current source.

Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.

typedef enum _dac12_speed_mode dac12_speed_mode_t

DAC analog buffer speed mode for conversion.

typedef struct _dac12_hardware_info dac12_hardware_info_t

DAC12 hardware information.

DAC12_CR_W1C_FLAGS_MASK

Define “write 1 to clear” flags.

DAC12_CR_ALL_FLAGS_MASK

Define all the flag bits in DACx_CR register.

struct _dac12_hardware_info

#include <fsl_dac12.h>

DAC12 hardware information.

Public Members

dac12_fifo_size_info_t fifoSizeInfo

The number of words in this device’s DAC buffer.

struct dac12_config_t

#include <fsl_dac12.h>

DAC12 module configuration.

Actually, the most fields are for FIFO buffer.

Public Members

uint32_t fifoWatermarkLevel

FIFO’s watermark, the max value can be the hardware FIFO size.

dac12_fifo_work_mode_t fifoWorkMode

FIFI’s work mode about pointers.

dac12_reference_voltage_source_t referenceVoltageSource

Select the reference voltage source.

dac12_reference_current_source_t referenceCurrentSource

Select the trigger mode for FIFO. Select the reference current source.

dac12_speed_mode_t speedMode

Select the speed mode for conversion.

bool enableAnalogBuffer

Enable analog buffer for high drive.

Dcdc_soc

void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)

Initializes the basic resource of DCDC module, such as control mode, etc.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to the dcdc_config_t structure.

void DCDC_Deinit(DCDC_Type *base)

De-initializes the DCDC module.

Parameters:

• base – DCDC peripheral base address.

void DCDC_GetDefaultConfig(dcdc_config_t *config)

Gets the default setting for DCDC, such as control mode, etc.

This function initializes the user configuration structure to a default value. The default values are:

config->controlMode                    = kDCDC_StaticControl;
config->trimInputMode                  = kDCDC_SampleTrimInput;
config->enableDcdcTimeout              = false;
config->enableSwitchingConverterOutput = false;

Parameters:

• config – Pointer to configuration structure. See to dcdc_config_t.

static inline void DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type *base, bool enable)

Makes the DCDC enter into low power mode for GPC standby request or not.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Makes DCDC enter into low power mode for GPC standby mode.

static inline void DCDC_EnterLowPowerMode(DCDC_Type *base, bool enable)

Makes DCDC enter into low power mode or not, before entering low power mode must disable stepping for VDD1P8 and VDD1P0.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Makes DCDC enter into low power mode.

static inline void DCDC_EnterStandbyMode(DCDC_Type *base, bool enable)

Makes DCDC enter into standby mode or not.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Makes DCDC enter into standby mode.

static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base, dcdc_standby_mode_1P0_target_vol_t targetVoltage)

Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in standby mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• targetVoltage – The target value of VDD1P0 in standby mode, see dcdc_standby_mode_1P0_target_vol_t.

static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P0 in standby mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P0’s voltage value in standby mode and the unit is “mV”.

static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base, dcdc_standby_mode_1P8_target_vol_t targetVoltage)

Sets the target value(ranges from 1.525V to 2.3V) of VDD1P8 in standby mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• targetVoltage – The target value of VDD1P8 in standby mode, see dcdc_standby_mode_1P8_target_vol_t.

static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P8 in standby mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P8’s voltage value in standby mode and the unit is “mV”.

static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage)

Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• targetVoltage – The target value of VDD1P0 in buck mode, see dcdc_buck_mode_1P0_target_vol_t.

static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P0 in buck mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P0’s voltage value in buck mode and the unit is “mV”.

static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage)

Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8 in buck mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• targetVoltage – The target value of VDD1P8 in buck mode, see dcdc_buck_mode_1P8_target_vol_t.

static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P8 in buck mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P8’s voltage value in buck mode and the unit is “mV”.

static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)

Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be disabled.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Enables stepping for VDD1P0.

  • false Disables stepping for VDD1P0.

static inline void DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type *base, bool enable)

Enables/Disables stepping for VDD1P8, before entering low power modes the stepping for VDD1P8 must be disabled.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Enables stepping for VDD1P8.

  • false Disables stepping for VDD1P8.

void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)

Gets the default setting for detection configuration.

The default configuration are set according to responding registers’ setting when powered on. They are:

config->enableXtalokDetection = false;
config->powerDownOverVoltageVdd1P8Detection = true;
config->powerDownOverVoltageVdd1P0Detection = true;
config->powerDownLowVoltageDetection  = false;
config->powerDownOverCurrentDetection = true;
config->powerDownPeakCurrentDetection = true;
config->powerDownZeroCrossDetection   = true;
config->OverCurrentThreshold          = kDCDC_OverCurrentThresholdAlt0;
config->PeakCurrentThreshold          = kDCDC_PeakCurrentThresholdAlt0;

Parameters:

• config – Pointer to configuration structure. See to dcdc_detection_config_t.

void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)

Configures the DCDC detection.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_detection_config_t.

static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)

Enables/Disables the output range comparator.

The output range comparator is disabled by default.

Parameters:

• base – DCDC peripheral base address.

• enable – Enable the feature or not.

  • true Enable the output range comparator.

  • false Disable the output range comparator.

void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)

Configures the DCDC clock source.

Parameters:

• base – DCDC peripheral base address.

• clockSource – Clock source for DCDC. See to dcdc_clock_source_t.

void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)

Gets the default setting for low power configuration.

The default configuration are set according to responding registers’ setting when powered on. They are:

config->enableAdjustHystereticValue = false;

Parameters:

• config – Pointer to configuration structure. See to dcdc_low_power_config_t.

void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)

Configures the DCDC low power.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_low_power_config_t.

static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)

Sets the bangap trim value(0~31) to trim bandgap voltage.

Parameters:

• base – DCDC peripheral base address.

• trimValue – The bangap trim value. Available range is 0U-31U.

void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)

Gets the default setting for loop control configuration.

The default configuration are set according to responding registers’ setting when powered on. They are:

config->enableCommonHysteresis = false;
config->enableCommonThresholdDetection = false;
config->enableInvertHysteresisSign = false;
config->enableRCThresholdDetection = false;
config->enableRCScaleCircuit = 0U;
config->complementFeedForwardStep = 0U;
config->controlParameterMagnitude = 2U;
config->integralProportionalRatio = 2U;

Parameters:

• config – Pointer to configuration structure. See to dcdc_loop_control_config_t.

void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)

Configures the DCDC loop control.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_loop_control_config_t.

void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)

Configures for the min power.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_min_power_config_t.

static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasValue)

Sets the current bias of low power comparator.

Parameters:

• base – DCDC peripheral base address.

• biasValue – The current bias of low power comparator. Refer to dcdc_comparator_current_bias_t.

void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)

Configures the DCDC internal regulator.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_internal_regulator_config_t.

static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)

Adjusts delay to reduce ground noise.

Parameters:

• base – DCDC peripheral base address.

• enable – Enable the feature or not.

static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)

Enables/Disables to improve the transition from heavy load to light load.

Note

It is valid while zero cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.

Parameters:

• base – DCDC peripheral base address.

• enable – Enable the feature or not.

void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)

Initializes DCDC module when the control mode selected as setpoint mode.

Note

The function should be invoked in the initial step to config the DCDC via setpoint control mode.

Parameters:

• base – DCDC peripheral base address.

• config – The pointer to the structure dcdc_setpoint_config_t.

static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)

Disable DCDC module when the control mode selected as setpoint mode.

Parameters:

• base – DCDC peripheral base address.

• setpointMap – The map of the setpoint to disable the DCDC module, Should be the OR’ed value of _dcdc_setpoint_map.

static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)

Get DCDC status flags.

Parameters:

• base – peripheral base address.

Returns:

Mask of asserted status flags. See to _dcdc_status_flags.

void DCDC_BootIntoDCM(DCDC_Type *base)

Boots DCDC into DCM(discontinous conduction mode).

pwd_zcd=0x0;
DM_CTRL = 1'b1;
pwd_cmp_offset=0x0;
dcdc_loopctrl_en_rcscale=0x3 or 0x5;
DCM_set_ctrl=1'b1;

Parameters:

• base – DCDC peripheral base address.

void DCDC_BootIntoCCM(DCDC_Type *base)

Boots DCDC into CCM(continous conduction mode).

pwd_zcd=0x1;
pwd_cmp_offset=0x0;
dcdc_loopctrl_en_rcscale=0x3;

Parameters:

• base – DCDC peripheral base address.

enum _dcdc_status_flags

The enumeration of DCDC status flags.

Values:

enumerator kDCDC_AlreadySettledStatusFlag

Indicate DCDC status. 1’b1: DCDC already settled 1’b0: DCDC is settling.

enum _dcdc_setpoint_map

System setpoints enumeration.

Values:

enumerator kDCDC_SetPoint0

Set point 0.

enumerator kDCDC_SetPoint1

Set point 1.

enumerator kDCDC_SetPoint2

Set point 2.

enumerator kDCDC_SetPoint3

Set point 3.

enumerator kDCDC_SetPoint4

Set point 4.

enumerator kDCDC_SetPoint5

Set point 5.

enumerator kDCDC_SetPoint6

Set point 6.

enumerator kDCDC_SetPoint7

Set point 7.

enumerator kDCDC_SetPoint8

Set point 8.

enumerator kDCDC_SetPoint9

Set point 9.

enumerator kDCDC_SetPoint10

Set point 10.

enumerator kDCDC_SetPoint11

Set point 11.

enumerator kDCDC_SetPoint12

Set point 12.

enumerator kDCDC_SetPoint13

Set point 13.

enumerator kDCDC_SetPoint14

Set point 14.

enumerator kDCDC_SetPoint15

Set point 15.

enum _dcdc_control_mode

DCDC control mode, including setpoint control mode and static control mode.

Values:

enumerator kDCDC_StaticControl

Static control.

enumerator kDCDC_SetPointControl

Controlled by GPC set points.

enum _dcdc_trim_input_mode

DCDC trim input mode, including sample trim input and hold trim input.

Values:

enumerator kDCDC_SampleTrimInput

Sample trim input.

enumerator kDCDC_HoldTrimInput

Hold trim input.

enum _dcdc_standby_mode_1P0_target_vol

The enumeration VDD1P0’s target voltage value in standby mode.

Values:

enumerator kDCDC_1P0StbyTarget0P625V

In standby mode, the target voltage value of VDD1P0 is 0.625V.

enumerator kDCDC_1P0StbyTarget0P65V

In standby mode, the target voltage value of VDD1P0 is 0.65V.

enumerator kDCDC_1P0StbyTarget0P675V

In standby mode, the target voltage value of VDD1P0 is 0.675V.

enumerator kDCDC_1P0StbyTarget0P7V

In standby mode, the target voltage value of VDD1P0 is 0.7V.

enumerator kDCDC_1P0StbyTarget0P725V

In standby mode, the target voltage value of VDD1P0 is 0.725V.

enumerator kDCDC_1P0StbyTarget0P75V

In standby mode, the target voltage value of VDD1P0 is 0.75V.

enumerator kDCDC_1P0StbyTarget0P775V

In standby mode, the target voltage value of VDD1P0 is 0.775V.

enumerator kDCDC_1P0StbyTarget0P8V

In standby mode, the target voltage value of VDD1P0 is 0.8V.

enumerator kDCDC_1P0StbyTarget0P825V

In standby mode, the target voltage value of VDD1P0 is 0.825V.

enumerator kDCDC_1P0StbyTarget0P85V

In standby mode, the target voltage value of VDD1P0 is 0.85V.

enumerator kDCDC_1P0StbyTarget0P875V

In standby mode, the target voltage value of VDD1P0 is 0.875V.

enumerator kDCDC_1P0StbyTarget0P9V

In standby mode, the target voltage value of VDD1P0 is 0.9V.

enumerator kDCDC_1P0StbyTarget0P925V

In standby mode, the target voltage value of VDD1P0 is 0.925V.

enumerator kDCDC_1P0StbyTarget0P95V

In standby mode, the target voltage value of VDD1P0 is 0.95V.

enumerator kDCDC_1P0StbyTarget0P975V

In standby mode, the target voltage value of VDD1P0 is 0.975V.

enumerator kDCDC_1P0StbyTarget1P0V

In standby mode, the target voltage value of VDD1P0 is 1.0V.

enumerator kDCDC_1P0StbyTarget1P025V

In standby mode, the target voltage value of VDD1P0 is 1.025V.

enumerator kDCDC_1P0StbyTarget1P05V

In standby mode, the target voltage value of VDD1P0 is 1.05V.

enumerator kDCDC_1P0StbyTarget1P075V

In standby mode, the target voltage value of VDD1P0 is 1.075V.

enumerator kDCDC_1P0StbyTarget1P1V

In standby mode, the target voltage value of VDD1P0 is 1.1V.

enumerator kDCDC_1P0StbyTarget1P125V

In standby mode, the target voltage value of VDD1P0 is 1.125V.

enumerator kDCDC_1P0StbyTarget1P15V

In standby mode, the target voltage value of VDD1P0 is 1.15V.

enumerator kDCDC_1P0StbyTarget1P175V

In standby mode, the target voltage value of VDD1P0 is 1.175V.

enumerator kDCDC_1P0StbyTarget1P2V

In standby mode, the target voltage value of VDD1P0 is 1.2V.

enumerator kDCDC_1P0StbyTarget1P225V

In standby mode, the target voltage value of VDD1P0 is 1.225V.

enumerator kDCDC_1P0StbyTarget1P25V

In standby mode, the target voltage value of VDD1P0 is 1.25V.

enumerator kDCDC_1P0StbyTarget1P275V

In standby mode, the target voltage value of VDD1P0 is 1.275V.

enumerator kDCDC_1P0StbyTarget1P3V

In standby mode, the target voltage value of VDD1P0 is 1.3V.

enumerator kDCDC_1P0StbyTarget1P325V

In standby mode, the target voltage value of VDD1P0 is 1.325V.

enumerator kDCDC_1P0StbyTarget1P35V

In standby mode, the target voltage value of VDD1P0 is 1.35V.

enumerator kDCDC_1P0StbyTarget1P375V

In standby mode, the target voltage value of VDD1P0 is 1.375V.

enumerator kDCDC_1P0StbyTarget1P4V

In standby mode, The target voltage value of VDD1P0 is 1.4V

enum _dcdc_standby_mode_1P8_target_vol

The enumeration VDD1P8’s target voltage value in standby mode.

Values:

enumerator kDCDC_1P8StbyTarget1P525V

In standby mode, the target voltage value of VDD1P8 is 1.525V.

enumerator kDCDC_1P8StbyTarget1P55V

In standby mode, the target voltage value of VDD1P8 is 1.55V.

enumerator kDCDC_1P8StbyTarget1P575V

In standby mode, the target voltage value of VDD1P8 is 1.575V.

enumerator kDCDC_1P8StbyTarget1P6V

In standby mode, the target voltage value of VDD1P8 is 1.6V.

enumerator kDCDC_1P8StbyTarget1P625V

In standby mode, the target voltage value of VDD1P8 is 1.625V.

enumerator kDCDC_1P8StbyTarget1P65V

In standby mode, the target voltage value of VDD1P8 is 1.65V.

enumerator kDCDC_1P8StbyTarget1P675V

In standby mode, the target voltage value of VDD1P8 is 1.675V.

enumerator kDCDC_1P8StbyTarget1P7V

In standby mode, the target voltage value of VDD1P8 is 1.7V.

enumerator kDCDC_1P8StbyTarget1P725V

In standby mode, the target voltage value of VDD1P8 is 1.725V.

enumerator kDCDC_1P8StbyTarget1P75V

In standby mode, the target voltage value of VDD1P8 is 1.75V.

enumerator kDCDC_1P8StbyTarget1P775V

In standby mode, the target voltage value of VDD1P8 is 1.775V.

enumerator kDCDC_1P8StbyTarget1P8V

In standby mode, the target voltage value of VDD1P8 is 1.8V.

enumerator kDCDC_1P8StbyTarget1P825V

In standby mode, the target voltage value of VDD1P8 is 1.825V.

enumerator kDCDC_1P8StbyTarget1P85V

In standby mode, the target voltage value of VDD1P8 is 1.85V.

enumerator kDCDC_1P8StbyTarget1P875V

In standby mode, the target voltage value of VDD1P8 is 1.875V.

enumerator kDCDC_1P8StbyTarget1P9V

In standby mode, the target voltage value of VDD1P8 is 1.9V.

enumerator kDCDC_1P8StbyTarget1P925V

In standby mode, the target voltage value of VDD1P8 is 1.925V.

enumerator kDCDC_1P8StbyTarget1P95V

In standby mode, the target voltage value of VDD1P8 is 1.95V.

enumerator kDCDC_1P8StbyTarget1P975V

In standby mode, the target voltage value of VDD1P8 is 1.975V.

enumerator kDCDC_1P8StbyTarget2P0V

In standby mode, the target voltage value of VDD1P8 is 2.0V.

enumerator kDCDC_1P8StbyTarget2P025V

In standby mode, the target voltage value of VDD1P8 is 2.025V.

enumerator kDCDC_1P8StbyTarget2P05V

In standby mode, the target voltage value of VDD1P8 is 2.05V.

enumerator kDCDC_1P8StbyTarget2P075V

In standby mode, the target voltage value of VDD1P8 is 2.075V.

enumerator kDCDC_1P8StbyTarget2P1V

In standby mode, the target voltage value of VDD1P8 is 2.1V.

enumerator kDCDC_1P8StbyTarget2P125V

In standby mode, the target voltage value of VDD1P8 is 2.125V.

enumerator kDCDC_1P8StbyTarget2P15V

In standby mode, the target voltage value of VDD1P8 is 2.15V.

enumerator kDCDC_1P8StbyTarget2P175V

In standby mode, the target voltage value of VDD1P8 is 2.175V.

enumerator kDCDC_1P8StbyTarget2P2V

In standby mode, the target voltage value of VDD1P8 is 2.2V.

enumerator kDCDC_1P8StbyTarget2P225V

In standby mode, the target voltage value of VDD1P8 is 2.225V.

enumerator kDCDC_1P8StbyTarget2P25V

In standby mode, the target voltage value of VDD1P8 is 2.25V.

enumerator kDCDC_1P8StbyTarget2P275V

In standby mode, the target voltage value of VDD1P8 is 2.275V.

enumerator kDCDC_1P8StbyTarget2P3V

In standby mode, the target voltage value is 2.3V.

enum _dcdc_buck_mode_1P0_target_vol

The enumeration VDD1P0’s target voltage value in buck mode.

Values:

enumerator kDCDC_1P0BuckTarget0P6V

In buck mode, the target voltage value of VDD1P0 is 0.6V.

enumerator kDCDC_1P0BuckTarget0P625V

In buck mode, the target voltage value of VDD1P0 is 0.625V.

enumerator kDCDC_1P0BuckTarget0P65V

In buck mode, the target voltage value of VDD1P0 is 0.65V.

enumerator kDCDC_1P0BuckTarget0P675V

In buck mode, the target voltage value of VDD1P0 is 0.675V.

enumerator kDCDC_1P0BuckTarget0P7V

In buck mode, the target voltage value of VDD1P0 is 0.7V.

enumerator kDCDC_1P0BuckTarget0P725V

In buck mode, the target voltage value of VDD1P0 is 0.725V.

enumerator kDCDC_1P0BuckTarget0P75V

In buck mode, the target voltage value of VDD1P0 is 0.75V.

enumerator kDCDC_1P0BuckTarget0P775V

In buck mode, the target voltage value of VDD1P0 is 0.775V.

enumerator kDCDC_1P0BuckTarget0P8V

In buck mode, the target voltage value of VDD1P0 is 0.8V.

enumerator kDCDC_1P0BuckTarget0P825V

In buck mode, the target voltage value of VDD1P0 is 0.825V.

enumerator kDCDC_1P0BuckTarget0P85V

In buck mode, the target voltage value of VDD1P0 is 0.85V.

enumerator kDCDC_1P0BuckTarget0P875V

In buck mode, the target voltage value of VDD1P0 is 0.875V.

enumerator kDCDC_1P0BuckTarget0P9V

In buck mode, the target voltage value of VDD1P0 is 0.9V.

enumerator kDCDC_1P0BuckTarget0P925V

In buck mode, the target voltage value of VDD1P0 is 0.925V.

enumerator kDCDC_1P0BuckTarget0P95V

In buck mode, the target voltage value of VDD1P0 is 0.95V.

enumerator kDCDC_1P0BuckTarget0P975V

In buck mode, the target voltage value of VDD1P0 is 0.975V.

enumerator kDCDC_1P0BuckTarget1P0V

In buck mode, the target voltage value of VDD1P0 is 1.0V.

enumerator kDCDC_1P0BuckTarget1P025V

In buck mode, the target voltage value of VDD1P0 is 1.025V.

enumerator kDCDC_1P0BuckTarget1P05V

In buck mode, the target voltage value of VDD1P0 is 1.05V.

enumerator kDCDC_1P0BuckTarget1P075V

In buck mode, the target voltage value of VDD1P0 is 1.075V.

enumerator kDCDC_1P0BuckTarget1P1V

In buck mode, the target voltage value of VDD1P0 is 1.1V.

enumerator kDCDC_1P0BuckTarget1P125V

In buck mode, the target voltage value of VDD1P0 is 1.125V.

enumerator kDCDC_1P0BuckTarget1P15V

In buck mode, the target voltage value of VDD1P0 is 1.15V.

enumerator kDCDC_1P0BuckTarget1P175V

In buck mode, the target voltage value of VDD1P0 is 1.175V.

enumerator kDCDC_1P0BuckTarget1P2V

In buck mode, the target voltage value of VDD1P0 is 1.2V.

enumerator kDCDC_1P0BuckTarget1P225V

In buck mode, the target voltage value of VDD1P0 is 1.225V.

enumerator kDCDC_1P0BuckTarget1P25V

In buck mode, the target voltage value of VDD1P0 is 1.25V.

enumerator kDCDC_1P0BuckTarget1P275V

In buck mode, the target voltage value of VDD1P0 is 1.275V.

enumerator kDCDC_1P0BuckTarget1P3V

In buck mode, the target voltage value of VDD1P0 is 1.3V.

enumerator kDCDC_1P0BuckTarget1P325V

In buck mode, the target voltage value of VDD1P0 is 1.325V.

enumerator kDCDC_1P0BuckTarget1P35V

In buck mode, the target voltage value of VDD1P0 is 1.35V.

enumerator kDCDC_1P0BuckTarget1P375V

In buck mode, the target voltage value of VDD1P0 is 1.375V.

enum _dcdc_buck_mode_1P8_target_vol

The enumeration VDD1P8’s target voltage value in buck mode.

Values:

enumerator kDCDC_1P8BuckTarget1P5V

In buck mode, the target voltage value of VDD1P0 is 1.5V.

enumerator kDCDC_1P8BuckTarget1P525V

In buck mode, the target voltage value of VDD1P0 is 1.525V.

enumerator kDCDC_1P8BuckTarget1P55V

In buck mode, the target voltage value of VDD1P0 is 1.55V.

enumerator kDCDC_1P8BuckTarget1P575V

In buck mode, the target voltage value of VDD1P0 is 1.575V.

enumerator kDCDC_1P8BuckTarget1P6V

In buck mode, the target voltage value of VDD1P0 is 1.6V.

enumerator kDCDC_1P8BuckTarget1P625V

In buck mode, the target voltage value of VDD1P0 is 1.625V.

enumerator kDCDC_1P8BuckTarget1P65V

In buck mode, the target voltage value of VDD1P0 is 1.65V.

enumerator kDCDC_1P8BuckTarget1P675V

In buck mode, the target voltage value of VDD1P0 is 1.675V.

enumerator kDCDC_1P8BuckTarget1P7V

In buck mode, the target voltage value of VDD1P0 is 1.7V.

enumerator kDCDC_1P8BuckTarget1P725V

In buck mode, the target voltage value of VDD1P0 is 1.725V.

enumerator kDCDC_1P8BuckTarget1P75V

In buck mode, the target voltage value of VDD1P0 is 1.75V.

enumerator kDCDC_1P8BuckTarget1P775V

In buck mode, the target voltage value of VDD1P0 is 1.775V.

enumerator kDCDC_1P8BuckTarget1P8V

In buck mode, the target voltage value of VDD1P0 is 1.8V.

enumerator kDCDC_1P8BuckTarget1P825V

In buck mode, the target voltage value of VDD1P0 is 1.825V.

enumerator kDCDC_1P8BuckTarget1P85V

In buck mode, the target voltage value of VDD1P0 is 1.85V.

enumerator kDCDC_1P8BuckTarget1P875V

In buck mode, the target voltage value of VDD1P0 is 1.875V.

enumerator kDCDC_1P8BuckTarget1P9V

In buck mode, the target voltage value of VDD1P0 is 1.9V.

enumerator kDCDC_1P8BuckTarget1P925V

In buck mode, the target voltage value of VDD1P0 is 1.925V.

enumerator kDCDC_1P8BuckTarget1P95V

In buck mode, the target voltage value of VDD1P0 is 1.95V.

enumerator kDCDC_1P8BuckTarget1P975V

In buck mode, the target voltage value of VDD1P0 is 1.975V.

enumerator kDCDC_1P8BuckTarget2P0V

In buck mode, the target voltage value of VDD1P0 is 2.0V.

enumerator kDCDC_1P8BuckTarget2P025V

In buck mode, the target voltage value of VDD1P0 is 2.025V.

enumerator kDCDC_1P8BuckTarget2P05V

In buck mode, the target voltage value of VDD1P0 is 2.05V.

enumerator kDCDC_1P8BuckTarget2P075V

In buck mode, the target voltage value of VDD1P0 is 2.075V.

enumerator kDCDC_1P8BuckTarget2P1V

In buck mode, the target voltage value of VDD1P0 is 2.1V.

enumerator kDCDC_1P8BuckTarget2P125V

In buck mode, the target voltage value of VDD1P0 is 2.125V.

enumerator kDCDC_1P8BuckTarget2P15V

In buck mode, the target voltage value of VDD1P0 is 2.15V.

enumerator kDCDC_1P8BuckTarget2P175V

In buck mode, the target voltage value of VDD1P0 is 2.175V.

enumerator kDCDC_1P8BuckTarget2P2V

In buck mode, the target voltage value of VDD1P0 is 2.2V.

enumerator kDCDC_1P8BuckTarget2P225V

In buck mode, the target voltage value of VDD1P0 is 2.225V.

enumerator kDCDC_1P8BuckTarget2P25V

In buck mode, the target voltage value of VDD1P0 is 2.25V.

enumerator kDCDC_1P8BuckTarget2P275V

In buck mode, the target voltage value of VDD1P0 is 2.275V.

enum _dcdc_comparator_current_bias

The current bias of low power comparator.

Values:

enumerator kDCDC_ComparatorCurrentBias50nA

The current bias of low power comparator is 50nA.

enumerator kDCDC_ComparatorCurrentBias100nA

The current bias of low power comparator is 100nA.

enumerator kDCDC_ComparatorCurrentBias200nA

The current bias of low power comparator is 200nA.

enumerator kDCDC_ComparatorCurrentBias400nA

The current bias of low power comparator is 400nA.

enum _dcdc_peak_current_threshold

The threshold if peak current detection.

Values:

enumerator kDCDC_PeakCurrentRunMode250mALPMode1P5A

Over peak current threshold in low power mode is 250mA, in run mode is 1.5A

enumerator kDCDC_PeakCurrentRunMode200mALPMode1P5A

Over peak current threshold in low power mode is 200mA, in run mode is 1.5A

enumerator kDCDC_PeakCurrentRunMode250mALPMode2A

Over peak current threshold in low power mode is 250mA, in run mode is 2A

enumerator kDCDC_PeakCurrentRunMode200mALPMode2A

Over peak current threshold in low power mode is 200mA, in run mode is 2A

enum _dcdc_clock_source

Oscillator clock option.

Values:

enumerator kDCDC_ClockAutoSwitch

Automatic clock switch from internal oscillator to external clock.

enumerator kDCDC_ClockInternalOsc

Use internal oscillator.

enumerator kDCDC_ClockExternalOsc

Use external 24M crystal oscillator.

enum _dcdc_voltage_output_sel

Voltage output option.

Values:

enumerator kDCDC_VoltageOutput1P8

1.8V output.

enumerator kDCDC_VoltageOutput1P0

1.0V output.

typedef enum _dcdc_control_mode dcdc_control_mode_t

DCDC control mode, including setpoint control mode and static control mode.

typedef enum _dcdc_trim_input_mode dcdc_trim_input_mode_t

DCDC trim input mode, including sample trim input and hold trim input.

typedef enum _dcdc_standby_mode_1P0_target_vol dcdc_standby_mode_1P0_target_vol_t

The enumeration VDD1P0’s target voltage value in standby mode.

typedef enum _dcdc_standby_mode_1P8_target_vol dcdc_standby_mode_1P8_target_vol_t

The enumeration VDD1P8’s target voltage value in standby mode.

typedef enum _dcdc_buck_mode_1P0_target_vol dcdc_buck_mode_1P0_target_vol_t

The enumeration VDD1P0’s target voltage value in buck mode.

typedef enum _dcdc_buck_mode_1P8_target_vol dcdc_buck_mode_1P8_target_vol_t

The enumeration VDD1P8’s target voltage value in buck mode.

typedef enum _dcdc_comparator_current_bias dcdc_comparator_current_bias_t

The current bias of low power comparator.

typedef enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t

The threshold if peak current detection.

typedef enum _dcdc_clock_source dcdc_clock_source_t

Oscillator clock option.

typedef enum _dcdc_voltage_output_sel dcdc_voltage_output_sel_t

Voltage output option.

typedef struct _dcdc_config dcdc_config_t

Configuration for DCDC.

typedef struct _dcdc_min_power_config dcdc_min_power_config_t

Configuration for min power setting.

typedef struct _dcdc_detection_config dcdc_detection_config_t

Configuration for DCDC detection.

typedef struct _dcdc_loop_control_config dcdc_loop_control_config_t

Configuration for the loop control.

typedef struct _dcdc_internal_regulator_config dcdc_internal_regulator_config_t

Configuration for DCDC internal regulator.

typedef struct _dcdc_low_power_config dcdc_low_power_config_t

Configuration for DCDC low power.

typedef struct _dcdc_setpoint_config dcdc_setpoint_config_t

DCDC configuration in set point mode.

FSL_DCDC_DRIVER_VERSION

DCDC driver version.

Version 2.1.2.

STANDBY_MODE_VDD1P0_TARGET_VOLTAGE

The array of VDD1P0 target voltage in standby mode.

STANDBY_MODE_VDD1P8_TARGET_VOLTAGE

The array of VDD1P8 target voltage in standby mode.

BUCK_MODE_VDD1P0_TARGET_VOLTAGE

The array of VDD1P0 target voltage in buck mode.

BUCK_MODE_VDD1P8_TARGET_VOLTAGE

The array of VDD1P8 target voltage in buck mode.

struct _dcdc_config

#include <fsl_dcdc.h>

Configuration for DCDC.

Public Members

dcdc_control_mode_t controlMode

DCDC control mode.

dcdc_trim_input_mode_t trimInputMode

Hold trim input.

bool enableDcdcTimeout

Enable internal count for DCDC_OK timeout.

bool enableSwitchingConverterOutput

Enable the VDDIO switching converter output.

struct _dcdc_min_power_config

#include <fsl_dcdc.h>

Configuration for min power setting.

Public Members

bool enableUseHalfFreqForContinuous

Set DCDC clock to half frequency for the continuous mode.

struct _dcdc_detection_config

#include <fsl_dcdc.h>

Configuration for DCDC detection.

Public Members

bool enableXtalokDetection

Enable xtalok detection circuit.

bool powerDownOverVoltageVdd1P8Detection

Power down over-voltage detection comparator for VDD1P8.

bool powerDownOverVoltageVdd1P0Detection

Power down over-voltage detection comparator for VDD1P0.

bool powerDownLowVoltageDetection

Power down low-voltage detection comparator.

bool powerDownOverCurrentDetection

Power down over-current detection.

bool powerDownPeakCurrentDetection

Power down peak-current detection.

bool powerDownZeroCrossDetection

Power down the zero cross detection function for discontinuous conductor mode.

dcdc_peak_current_threshold_t PeakCurrentThreshold

The threshold of peak current detection.

struct _dcdc_loop_control_config

#include <fsl_dcdc.h>

Configuration for the loop control.

Public Members

bool enableCommonHysteresis

Enable hysteresis in switching converter common mode analog comparators. This feature will improve transient supply ripple and efficiency.

bool enableCommonThresholdDetection

Increase the threshold detection for common mode analog comparator.

bool enableDifferentialHysteresis

Enable hysteresis in switching converter differential mode analog comparators. This feature will improve transient supply ripple and efficiency.

bool enableDifferentialThresholdDetection

Increase the threshold detection for differential mode analog comparators.

bool enableInvertHysteresisSign

Invert the sign of the hysteresis in DC-DC analog comparators.

bool enableRCThresholdDetection

Increase the threshold detection for RC scale circuit.

uint32_t enableRCScaleCircuit

Available range is 0~7. Enable analog circuit of DC-DC converter to respond faster under transient load conditions.

uint32_t complementFeedForwardStep

Available range is 0~7. Two’s complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional to the change. This can be used to force a certain control loop behavior, such as improving response under known heavy load transients.

uint32_t controlParameterMagnitude

Available range is 0~15. Magnitude of proportional control parameter in the switching DC-DC converter control loop.

uint32_t integralProportionalRatio

Available range is 0~3.Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response.

struct _dcdc_internal_regulator_config

#include <fsl_dcdc.h>

Configuration for DCDC internal regulator.

Public Members

uint32_t feedbackPoint

Available range is 0~3. Select the feedback point of the internal regulator.

struct _dcdc_low_power_config

#include <fsl_dcdc.h>

Configuration for DCDC low power.

Public Members

bool enableAdjustHystereticValue

Adjust hysteretic value in low power from 12.5mV to 25mV.

struct _dcdc_setpoint_config

#include <fsl_dcdc.h>

DCDC configuration in set point mode.

Public Members

uint32_t enableDCDCMap

The setpoint map that enable the DCDC module. Should be the OR’ed value of _dcdc_setpoint_map.

uint32_t enableDigLogicMap

The setpoint map that enable the DCDC dig logic. Should be the OR’ed value of _dcdc_setpoint_map.

uint32_t lowpowerMap

The setpoint map that enable the DCDC Low powermode. Should be the OR’ed value of _dcdc_setpoint_map.

uint32_t standbyMap

The setpoint map that enable the DCDC standby mode. Should be the OR’ed value of _dcdc_setpoint_map.

uint32_t standbyLowpowerMap

The setpoint map that enable the DCDC low power mode, when the related setpoint is in standby mode. Please refer to _dcdc_setpoint_map.

dcdc_buck_mode_1P8_target_vol_t *buckVDD1P8TargetVoltage

Point to the array that store the target voltage level of VDD1P8 in buck mode, please refer to dcdc_buck_mode_1P8_target_vol_t. Note that the pointed array must have 16 elements.

dcdc_buck_mode_1P0_target_vol_t *buckVDD1P0TargetVoltage

Point to the array that store the target voltage level of VDD1P0 in buck mode, please refer to dcdc_buck_mode_1P0_target_vol_t. Note that the pointed array must have 16 elements.

dcdc_standby_mode_1P8_target_vol_t *standbyVDD1P8TargetVoltage

Point to the array that store the target voltage level of VDD1P8 in standby mode, please refer to dcdc_standby_mode_1P8_target_vol_t. Note that the pointed array must have 16 elements.

dcdc_standby_mode_1P0_target_vol_t *standbyVDD1P0TargetVoltage

Point to the array that store the target voltage level of VDD1P0 in standby mode, please refer to dcdc_standby_mode_1P0_target_vol_t. Note that the pointed array must have 16 elements.

DCIC: Display Content Integrity Checker

DCIC

void DCIC_Init(DCIC_Type *base, const dcic_config_t *config)

Initializes the DCIC.

This function resets DCIC registers to default value, then set the configurations. This function does not start the DCIC to work, application should call DCIC_DisableRegion to configure regions, then call DCIC_Enable to start the DCIC to work.

Parameters:

• base – DCIC peripheral base address.

• config – Pointer to the configuration.

void DCIC_Deinit(DCIC_Type *base)

Deinitialize the DCIC.

Disable the DCIC functions.

Parameters:

• base – DCIC peripheral base address.

void DCIC_GetDefaultConfig(dcic_config_t *config)

Get the default configuration to initialize DCIC.

The default configuration is:

config->polarityFlags = kDCIC_VsyncActiveLow | kDCIC_HsyncActiveLow |
                        kDCIC_DataEnableActiveLow | kDCIC_DriveDataOnFallingClkEdge;
config->enableExternalSignal = false;
config->enableInterrupts = 0;

Parameters:

• config – Pointer to the configuration.

static inline void DCIC_Enable(DCIC_Type *base, bool enable)

Enable or disable the DCIC module.

Parameters:

• base – DCIC peripheral base address.

• enable – Use true to enable, false to disable.

static inline uint32_t DCIC_GetStatusFlags(DCIC_Type *base)

Get status flags.

The flag kDCIC_ErrorInterruptStatus is asserted if any region mismatch flag asserted.

base DCIC peripheral base address.

Returns:

Masks of asserted status flags, _DCIC_status_flags.

static inline void DCIC_ClearStatusFlags(DCIC_Type *base, uint32_t mask)

Clear status flags.

The flag kDCIC_ErrorInterruptStatus should be cleared by clearing all asserted region mismatch flags.

base DCIC peripheral base address.

mask Mask of status values that would be cleared, _DCIC_status_flags.

static inline void DCIC_LockInterruptEnabledStatus(DCIC_Type *base)

Lock the interrupt enabled status.

Once this function is called, the interrupt enabled status could not be changed until reset.

Parameters:

• base – DCIC peripheral base address.

static inline void DCIC_EnableInterrupts(DCIC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – DCIC peripheral base address.

• mask – Mask of interrupt events that would be enabled. See to “_dcic_interrupt_enable_t”.

static inline void DCIC_DisableInterrupts(DCIC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – DCIC peripheral base address.

• mask – Mask of interrupt events that would be disabled. See to “_dcic_interrupt_enable_t”.

void DCIC_EnableRegion(DCIC_Type *base, uint8_t regionIdx, const dcic_region_config_t *config)

Enable the region of interest (ROI) with configuration.

Enable the ROI with configuration. To change the configuration except reference CRC value, the region should be disabled first by DCIC_DisableRegion, then call this function again. The reference CRC value could be changed by DCIC_SetRegionRefCrc without disabling the region. If the configuration is locked, only the reference CRC value could be changed, the region size and position, enable status could not be changed until reset.

Parameters:

• base – DCIC peripheral base address.

• regionIdx – Region index, from 0 to (DCIC_REGION_COUNT - 1).

• config – Pointer to the configuration.

static inline void DCIC_DisableRegion(DCIC_Type *base, uint8_t regionIdx)

Disable the region of interest (ROI).

Parameters:

• base – DCIC peripheral base address.

• regionIdx – Region index, from 0 to (DCIC_REGION_COUNT - 1).

static inline void DCIC_SetRegionRefCrc(DCIC_Type *base, uint8_t regionIdx, uint32_t crc)

Set the reference CRC of interest (ROI).

Parameters:

• base – DCIC peripheral base address.

• regionIdx – Region index, from 0 to (DCIC_REGION_COUNT - 1).

• crc – The reference CRC value.

static inline uint32_t DCIC_GetRegionCalculatedCrc(DCIC_Type *base, uint8_t regionIdx)

Get the DCIC calculated CRC.

Parameters:

• base – DCIC peripheral base address.

• regionIdx – Region index, from 0 to (DCIC_REGION_COUNT - 1).

Returns:

The calculated CRC value.

static inline void DCIC_EnableMismatchExternalSignal(DCIC_Type *base, bool enable)

Enable or disable output the mismatch external signal.

The mismatch status can be output to external pins. If enabled:

• If kDCIC_ErrorInterruptStatus asserted, the output signal frequency is DCIC clock / 16.

• If kDCIC_ErrorInterruptStatus not asserted, the output signal frequency is DCIC clock / 4.

• If integrity check is disabled, the signal is idle.

Parameters:

• base – DCIC peripheral base address.

• enable – Use true to enable, false to disable.

enum _DCIC_polarity_flags

DCIC display signal polarity flags .

Values:

enumerator kDCIC_VsyncActiveHigh

VSYNC active high.

enumerator kDCIC_HsyncActiveHigh

HSYNC active high.

enumerator kDCIC_DataEnableActiveHigh

Data enable line active high.

enumerator kDCIC_DriveDataOnFallingClkEdge

Output data on rising clock edge, capture data on falling clock edge.

enumerator kDCIC_VsyncActiveLow

VSYNC active low.

enumerator kDCIC_HsyncActiveLow

HSYNC active low.

enumerator kDCIC_DataEnableActiveLow

Data enable line active low.

enumerator kDCIC_DriveDataOnRisingClkEdge

Output data on falling clock edge, capture data on rising clock edge.

enum _DCIC_status_flags

Status flags. .

Values:

enumerator kDCIC_FunctionalInterruptStatus

Asserted when match results ready.

enumerator kDCIC_ErrorInterruptStatus

Asserted when there is a signature mismatch.

enumerator kDCIC_Region0MismatchStatus

Region 0 CRC32 value mismatch.

enumerator kDCIC_Region1MismatchStatus

Region 1 CRC32 value mismatch.

enumerator kDCIC_Region2MismatchStatus

Region 2 CRC32 value mismatch.

enumerator kDCIC_Region3MismatchStatus

Region 3 CRC32 value mismatch.

enumerator kDCIC_Region4MismatchStatus

Region 4 CRC32 value mismatch.

enumerator kDCIC_Region5MismatchStatus

Region 5 CRC32 value mismatch.

enumerator kDCIC_Region6MismatchStatus

Region 6 CRC32 value mismatch.

enumerator kDCIC_Region7MismatchStatus

Region 7 CRC32 value mismatch.

enumerator kDCIC_Region8MismatchStatus

Region 8 CRC32 value mismatch.

enumerator kDCIC_Region9MismatchStatus

Region 9 CRC32 value mismatch.

enumerator kDCIC_Region10MismatchStatus

Region 10 CRC32 value mismatch.

enumerator kDCIC_Region11MismatchStatus

Region 11 CRC32 value mismatch.

enumerator kDCIC_Region12MismatchStatus

Region 12 CRC32 value mismatch.

enumerator kDCIC_Region13MismatchStatus

Region 13 CRC32 value mismatch.

enumerator kDCIC_Region14MismatchStatus

Region 14 CRC32 value mismatch.

enumerator kDCIC_Region15MismatchStatus

Region 15 CRC32 value mismatch.

enum _dcic_interrupt_enable

Interrupts. .

Values:

enumerator kDCIC_FunctionalInterruptEnable

Interrupt when match results ready.

enumerator kDCIC_ErrorInterruptEnable

Interrupt when there is a signature mismatch.

typedef struct _dcic_config dcic_config_t

DCIC configuration.

typedef struct _dcic_region_config dcic_region_config_t

Region of interest (ROI) configuration.

DCIC_REGION_COUNT

FSL_DCIC_DRIVER_VERSION

DCIC driver version.

DCIC_CRC32_POLYNOMIAL

CRC32 calculation polynomial.

DCIC_CRC32_INIT_VALUE

CRC32 calculation initialize value.

DCIC_REGION_MISMATCH_STATUS(region)

ROI CRC32 value mismatch status.

struct _dcic_config

#include <fsl_dcic.h>

DCIC configuration.

Public Members

bool enableExternalSignal

Enable the mismatch external signal. When enabled, the mismatch status could be monitored from the extern pin.

uint8_t polarityFlags

Display signal polarity, logical OR’ed of _DCIC_polarity_flags.

uint32_t enableInterrupts

Interrupts to enable, should be OR’ed of _dcic_interrupt_enable.

struct _dcic_region_config

#include <fsl_dcic.h>

Region of interest (ROI) configuration.

Public Members

bool lock

Lock the region configuration except reference CRC32 value setting.

uint16_t upperLeftX

X of upper left corner. Range: 0 to 2^13-1.

uint16_t upperLeftY

Y of upper left corner. Range: 0 to 2^12-1.

uint16_t lowerRightX

X of lower right corner. Range: 0 to 2^13-1.

uint16_t lowerRightY

Y of lower right corner. Range: 0 to 2^12-1.

uint32_t refCrc

Reference CRC32 value.

DMAMUX: Direct Memory Access Multiplexer Driver

void DMAMUX_Init(DMAMUX_Type *base)

Initializes the DMAMUX peripheral.

This function ungates the DMAMUX clock.

Parameters:

• base – DMAMUX peripheral base address.

void DMAMUX_Deinit(DMAMUX_Type *base)

Deinitializes the DMAMUX peripheral.

This function gates the DMAMUX clock.

Parameters:

• base – DMAMUX peripheral base address.

static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)

Enables the DMAMUX channel.

This function enables the DMAMUX channel.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)

Disables the DMAMUX channel.

This function disables the DMAMUX channel.

Note

The user must disable the DMAMUX channel before configuring it.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, int32_t source)

Configures the DMAMUX channel source.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

• source – Channel source, which is used to trigger the DMA transfer.User need to use the dma_request_source_t type as the input parameter.

static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)

Enables the DMAMUX period trigger.

This function enables the DMAMUX period trigger feature.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)

Disables the DMAMUX period trigger.

This function disables the DMAMUX period trigger.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)

Enables the DMA channel to be always ON.

This function enables the DMAMUX channel always ON feature.

Parameters:

• base – DMAMUX peripheral base address.

• channel – DMAMUX channel number.

• enable – Switcher of the always ON feature. “true” means enabled, “false” means disabled.

FSL_DMAMUX_DRIVER_VERSION

DMAMUX driver version 2.1.0.

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver

void EDMA_Init(DMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

• base – eDMA peripheral base address.

• config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(DMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

• base – eDMA peripheral base address.

void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

• base – EDMA peripheral base address.

• channel – EDMA channel number.

• tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

• config – A pointer to the eDMA configuration structure.

static inline void EDMA_EnableContinuousChannelLinkMode(DMA_Type *base, bool enable)

Enable/Disable continuous channel link mode.

Note

Do not use continuous link mode with a channel linking to itself if there is only one minor loop iteration per service request, for example, if the channel’s NBYTES value is the same as either the source or destination size. The same data transfer profile can be achieved by simply increasing the NBYTES value, which provides more efficient, faster processing.

Parameters:

• base – EDMA peripheral base address.

• enable – true is enable, false is disable.

static inline void EDMA_EnableMinorLoopMapping(DMA_Type *base, bool enable)

Enable/Disable minor loop mapping.

The TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field.

Parameters:

• base – EDMA peripheral base address.

• enable – true is enable, false is disable.

void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number

• config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• linkType – A channel link type, which can be one of the following:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)

Enables an async request for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(DMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• base – eDMA peripheral base address.

• channel – edma channel number.

• sourceOffset – source address offset will be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

• tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

• tcd – Pointer to the TCD structure.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

• tcd – A point to the TCD structure.

• config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• tcd – Point to the TCD structure.

• linkType – Channel link type, it can be one of:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• tcd – A pointer to the TCD structure.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• tcd – A pointer to the TCD structure.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• tcd – A pointer to the TCD structure.

• enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• tcd – A point to the TCD structure.

• sourceOffset – source address offset wiil be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

1. The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

• base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

• handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.

• base – eDMA peripheral base address.

• channel – eDMA channel number.

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

• handle – eDMA handle pointer.

• tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.

• tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

• handle – eDMA handle pointer.

• callback – eDMA callback function pointer.

• userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• srcOffset – source address offset.

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• destOffset – destination address offset.

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t transferType)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

• transferType – eDMA transfer type.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

• handle – eDMA handle pointer.

• config – Pointer to eDMA transfer configuration structure.

Return values:

• kStatus_EDMA_Success – It means submit transfer request succeed.

• kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.

• kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

• handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

• handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

• handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

• handle – eDMA handle pointer.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.4.4.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes

Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes

Source/Destination data transfer size is 32 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable

Disable modulo

enumerator kEDMA_Modulo2bytes

Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes

Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes

Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes

Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes

Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes

Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes

Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes

Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes

Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes

Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes

Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes

Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes

Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes

Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes

Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes

Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes

Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes

Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes

Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes

Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes

Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes

Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes

Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes

Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes

Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes

Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes

Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes

Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes

Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes

Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes

Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone

No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle

eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle

eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone

No channel link

enumerator kEDMA_MinorLink

Channel link after each minor loop

enumerator kEDMA_MajorLink

Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag

DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag

eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag

eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag

Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag

Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag

Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag

NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag

Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag

Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag

Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag

Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag

Error channel number of the cancelled channel number

enumerator kEDMA_ChannelPriorityErrorFlag

Channel priority is not unique.

enumerator kEDMA_TransferCanceledFlag

Transfer cancelled

enumerator kEDMA_ValidFlag

No error occurred, this bit is 0. Otherwise, it is 1.

enum _edma_interrupt_enable

eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable

Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable

Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable

Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory

Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory

Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral

Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral

Transfer from Peripheral to peripheral

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull

TCD queue is full.

enumerator kStatus_EDMA_Busy

Channel is busy and can’t handle the transfer request.

typedef enum _edma_transfer_size edma_transfer_size_t

eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t

eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t

Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t

Channel link type.

typedef enum _edma_interrupt_enable edma_interrupt_enable_t

eDMA interrupt source

typedef enum _edma_transfer_type edma_transfer_type_t

eDMA transfer type

typedef struct _edma_config edma_config_t

eDMA global configuration structure.

typedef struct _edma_transfer_config edma_transfer_config_t

eDMA transfer configuration

This structure configures the source/destination transfer attribute.

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t

eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t

eDMA minor offset configuration

typedef struct _edma_tcd edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:

EDMA handle pointer, users shall not touch the values inside.

Param userData:

The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.

Param transferDone:

If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.

Param tcds:

How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t

eDMA transfer handle structure

DMA_DCHPRI_INDEX(channel)

Compute the offset unit from DCHPRI3.

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableContinuousLinkMode

Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.

bool enableHaltOnError

Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableRoundRobinArbitration

Enable (true) round robin channel arbitration method or fixed priority arbitration is used for channel selection

bool enableDebugMode

Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of a new channel. Executing channels are allowed to complete.

struct _edma_transfer_config

#include <fsl_edma.h>

eDMA transfer configuration

This structure configures the source/destination transfer attribute.

Public Members

uint32_t srcAddr

Source data address.

uint32_t destAddr

Destination data address.

edma_transfer_size_t srcTransferSize

Source data transfer size.

edma_transfer_size_t destTransferSize

Destination data transfer size.

int16_t srcOffset

Sign-extended offset applied to the current source address to form the next-state value as each source read is completed.

int16_t destOffset

Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes

Bytes to transfer in a minor loop

uint32_t majorLoopCounts

Major loop iteration count.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption

If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility

If true: a channel can suspend other channel with low priority

uint8_t channelPriority

Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset

Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset

Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset

Offset for a minor loop mapping.

struct _edma_tcd

#include <fsl_edma.h>

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

Public Members

__IO uint32_t SADDR

SADDR register, used to save source address

__IO uint16_t SOFF

SOFF register, save offset bytes every transfer

__IO uint16_t ATTR

ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES

Nbytes register, minor loop length in bytes

__IO uint32_t SLAST

SLAST register

__IO uint32_t DADDR

DADDR register, used for destination address

__IO uint16_t DOFF

DOFF register, used for destination offset

__IO uint16_t CITER

CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR

CSR register, for TCD control status

__IO uint16_t BITER

BITER register, begin minor loop count.

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback

Callback function for major count exhausted.

void *userData

Callback function parameter.

DMA_Type *base

eDMA peripheral base address.

edma_tcd_t *tcdPool

Pointer to memory stored TCDs.

uint8_t channel

eDMA channel number.

volatile int8_t header

The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail

The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed

The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize

The total number of TCD slots in the queue.

uint8_t flags

The status of the current channel.

eLCDIF: Enhanced LCD Interface

void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)

Initializes the eLCDIF to work in RGB mode (DOTCLK mode).

This function ungates the eLCDIF clock and configures the eLCDIF peripheral according to the configuration structure.

Parameters:

• base – eLCDIF peripheral base address.

• config – Pointer to the configuration structure.

void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)

Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
                        kELCDIF_HsyncActiveLow |
                        kELCDIF_DataEnableActiveLow |
                        kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;

Parameters:

• config – Pointer to the eLCDIF configuration structure.

void ELCDIF_Deinit(LCDIF_Type *base)

Deinitializes the eLCDIF peripheral.

Parameters:

• base – eLCDIF peripheral base address.

void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)

Set the pixel format in RGB (DOTCLK) mode.

Parameters:

• base – eLCDIF peripheral base address.

• pixelFormat – The pixel format.

static inline void ELCDIF_RgbModeStart(LCDIF_Type *base)

Start to display in RGB (DOTCLK) mode.

Parameters:

• base – eLCDIF peripheral base address.

void ELCDIF_RgbModeStop(LCDIF_Type *base)

Stop display in RGB (DOTCLK) mode and wait until finished.

Parameters:

• base – eLCDIF peripheral base address.

static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)

Set the next frame buffer address to display.

Parameters:

• base – eLCDIF peripheral base address.

• bufferAddr – The frame buffer address to set.

void ELCDIF_Reset(LCDIF_Type *base)

Reset the eLCDIF peripheral.

Parameters:

• base – eLCDIF peripheral base address.

void ELCDIF_SetPixelComponentOrder(LCDIF_Type *base, elcdif_pixel_component_order_t order)

Set the order of the RGB components of each pixel in lines.

Parameters:

• base – eLCDIF peripheral base address.

• order – The pixel component order

static inline uint32_t ELCDIF_GetCrcValue(const LCDIF_Type *base)

Get the CRC value of the frame sent out.

When a frame is sent complete (the interrupt kELCDIF_CurFrameDone assert), this function can be used to get the CRC value of the frame sent.

Note

The CRC value is dependent on the LCD_DATABUS_WIDTH.

Parameters:

• base – eLCDIF peripheral base address.

Returns:

The CRC value.

static inline uint32_t ELCDIF_GetBusMasterErrorAddr(const LCDIF_Type *base)

Get the bus master error virtual address.

When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function can get the virtual address at which the AXI master received an error response from the slave.

Parameters:

• base – eLCDIF peripheral base address.

Returns:

The error virtual address.

static inline uint32_t ELCDIF_GetStatus(const LCDIF_Type *base)

Get the eLCDIF status.

The status flags are returned as a mask value, application could check the corresponding bit. Example:

uint32_t statusFlags;
statusFlags = ELCDIF_GetStatus(LCDIF);

if (kELCDIF_LFifoFull & statusFlags)
{
}

if (kELCDIF_TxFifoEmpty & statusFlags)
{
}

Parameters:

• base – eLCDIF peripheral base address.

Returns:

The mask value of status flags, it is OR’ed value of _elcdif_status_flags.

static inline uint32_t ELCDIF_GetLFifoCount(const LCDIF_Type *base)

Get current count in Latency buffer (LFIFO).

Parameters:

• base – eLCDIF peripheral base address.

Returns:

The LFIFO current count

static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask)

Enables eLCDIF interrupt requests.

Parameters:

• base – eLCDIF peripheral base address.

• mask – interrupt source, OR’ed value of _elcdif_interrupt_enable.

static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask)

Disables eLCDIF interrupt requests.

Parameters:

• base – eLCDIF peripheral base address.

• mask – interrupt source, OR’ed value of _elcdif_interrupt_enable.

static inline uint32_t ELCDIF_GetInterruptStatus(const LCDIF_Type *base)

Get eLCDIF interrupt peding status.

Parameters:

• base – eLCDIF peripheral base address.

Returns:

Interrupt pending status, OR’ed value of _elcdif_interrupt_flags.

static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask)

Clear eLCDIF interrupt peding status.

Parameters:

• base – eLCDIF peripheral base address.

• mask – of the flags to clear, OR’ed value of _elcdif_interrupt_flags.

static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable)

Enable or disable the LUT.

Parameters:

• base – eLCDIF peripheral base address.

• enable – True to enable, false to disable.

status_t ELCDIF_UpdateLut(LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)

Load the LUT value.

This function loads the LUT value to the specific LUT memory, user can specify the start entry index.

Parameters:

• base – eLCDIF peripheral base address.

• lut – Which LUT to load.

• startIndex – The start index of the LUT entry to update.

• lutData – The LUT data to load.

• count – Count of lutData.

Return values:

• kStatus_Success – Initialization success.

• kStatus_InvalidArgument – Wrong argument.

FSL_ELCDIF_DRIVER_VERSION

eLCDIF driver version

enum _elcdif_polarity_flags

eLCDIF signal polarity flags

Values:

enumerator kELCDIF_VsyncActiveLow

VSYNC active low.

enumerator kELCDIF_HsyncActiveLow

HSYNC active low.

enumerator kELCDIF_DataEnableActiveLow

Data enable line active low.

enumerator kELCDIF_DriveDataOnFallingClkEdge

Drive data on falling clock edge, capture data on rising clock edge.

enumerator kELCDIF_VsyncActiveHigh

VSYNC active high.

enumerator kELCDIF_HsyncActiveHigh

HSYNC active high.

enumerator kELCDIF_DataEnableActiveHigh

Data enable line active high.

enumerator kELCDIF_DriveDataOnRisingClkEdge

Drive data on falling clock edge, capture data on rising clock edge.

enum _elcdif_interrupt_enable

The eLCDIF interrupts to enable.

Values:

enumerator kELCDIF_BusMasterErrorInterruptEnable

Bus master error interrupt.

enumerator kELCDIF_TxFifoOverflowInterruptEnable

TXFIFO overflow interrupt.

enumerator kELCDIF_TxFifoUnderflowInterruptEnable

TXFIFO underflow interrupt.

enumerator kELCDIF_CurFrameDoneInterruptEnable

Interrupt when hardware enters vertical blanking state.

enumerator kELCDIF_VsyncEdgeInterruptEnable

Interrupt when hardware encounters VSYNC edge.

enum _elcdif_interrupt_flags

The eLCDIF interrupt status flags.

Values:

enumerator kELCDIF_BusMasterError

Bus master error interrupt.

enumerator kELCDIF_TxFifoOverflow

TXFIFO overflow interrupt.

enumerator kELCDIF_TxFifoUnderflow

TXFIFO underflow interrupt.

enumerator kELCDIF_CurFrameDone

Interrupt when hardware enters vertical blanking state.

enumerator kELCDIF_VsyncEdge

Interrupt when hardware encounters VSYNC edge.

enum _elcdif_status_flags

eLCDIF status flags

Values:

enumerator kELCDIF_LFifoFull

LFIFO full.

enumerator kELCDIF_LFifoEmpty

LFIFO empty.

enumerator kELCDIF_TxFifoFull

TXFIFO full.

enumerator kELCDIF_TxFifoEmpty

TXFIFO empty.

enum _elcdif_pixel_format

The pixel format.

This enumerator should be defined together with the array s_pixelFormatReg. To support new pixel format, enhance this enumerator and s_pixelFormatReg.

Values:

enumerator kELCDIF_PixelFormatRAW8

RAW 8 bit, four data use 32 bits.

enumerator kELCDIF_PixelFormatRGB565

RGB565, two pixel use 32 bits.

enumerator kELCDIF_PixelFormatRGB666

RGB666 unpacked, one pixel uses 32 bits, high byte unused, upper 2 bits of other bytes unused.

enumerator kELCDIF_PixelFormatXRGB8888

XRGB8888 unpacked, one pixel uses 32 bits, high byte unused.

enumerator kELCDIF_PixelFormatRGB888

RGB888 packed, one pixel uses 24 bits.

enum _elcdif_lcd_data_bus

The LCD data bus type.

Values:

enumerator kELCDIF_DataBus8Bit

8-bit data bus.

enumerator kELCDIF_DataBus16Bit

16-bit data bus, support RGB565.

enumerator kELCDIF_DataBus18Bit

18-bit data bus, support RGB666.

enumerator kELCDIF_DataBus24Bit

24-bit data bus, support RGB888.

enum _elcdif_as_pixel_format

eLCDIF alpha surface pixel format.

Values:

enumerator kELCDIF_AsPixelFormatARGB8888

32-bit pixels with alpha.

enumerator kELCDIF_AsPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format)

enumerator kELCDIF_AsPixelFormatARGB1555

16-bit pixels with alpha.

enumerator kELCDIF_AsPixelFormatARGB4444

16-bit pixels with alpha.

enumerator kELCDIF_AsPixelFormatRGB555

16-bit pixels without alpha.

enumerator kELCDIF_AsPixelFormatRGB444

16-bit pixels without alpha.

enumerator kELCDIF_AsPixelFormatRGB565

16-bit pixels without alpha.

enum _elcdif_alpha_mode

eLCDIF alpha mode during blending.

Values:

enumerator kELCDIF_AlphaEmbedded

The alpha surface pixel alpha value will be used for blend.

enumerator kELCDIF_AlphaOverride

The user defined alpha value will be used for blend directly.

enumerator kELCDIF_AlphaMultiply

The alpha surface pixel alpha value scaled the user defined alpha value will be used for blend, for example, pixel alpha set set to 200, user defined alpha set to 100, then the reault alpha is 200 * 100 / 255.

enumerator kELCDIF_AlphaRop

Raster operation.

enum _elcdif_rop_mode

eLCDIF ROP mode during blending.

Explanation:

• AS: Alpha surface

• PS: Process surface

• nAS: Alpha surface NOT value

• nPS: Process surface NOT value

Values:

enumerator kELCDIF_RopMaskAs

AS AND PS.

enumerator kELCDIF_RopMaskNotAs

nAS AND PS.

enumerator kELCDIF_RopMaskAsNot

AS AND nPS.

enumerator kELCDIF_RopMergeAs

AS OR PS.

enumerator kELCDIF_RopMergeNotAs

nAS OR PS.

enumerator kELCDIF_RopMergeAsNot

AS OR nPS.

enumerator kELCDIF_RopNotCopyAs

nAS.

enumerator kELCDIF_RopNot

nPS.

enumerator kELCDIF_RopNotMaskAs

AS NAND PS.

enumerator kELCDIF_RopNotMergeAs

AS NOR PS.

enumerator kELCDIF_RopXorAs

AS XOR PS.

enumerator kELCDIF_RopNotXorAs

AS XNOR PS.

enum _elcdif_lut

eLCDIF LUT

The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel before output to external displayer.

There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address determins which memory to use.

Values:

enumerator kELCDIF_Lut0

LUT 0.

enumerator kELCDIF_Lut1

LUT 1.

enum _elcdif_pixel_component_order

eLCDIF pixel component order.

Values:

enumerator kELCDIF_PixelComponentOrderRGB

Input order RGB.

enumerator kELCDIF_PixelComponentOrderRBG

Input order RBG.

enumerator kELCDIF_PixelComponentOrderGBR

Input order GBR.

enumerator kELCDIF_PixelComponentOrderGRB

Input order GRB.

enumerator kELCDIF_PixelComponentOrderBRG

Input order BRG.

enumerator kELCDIF_PixelComponentOrderBGR

Input order BGR.

typedef enum _elcdif_pixel_format elcdif_pixel_format_t

The pixel format.

This enumerator should be defined together with the array s_pixelFormatReg. To support new pixel format, enhance this enumerator and s_pixelFormatReg.

typedef enum _elcdif_lcd_data_bus elcdif_lcd_data_bus_t

The LCD data bus type.

typedef struct _elcdif_pixel_format_reg elcdif_pixel_format_reg_t

The register value when using different pixel format.

These register bits control the pixel format:

• CTRL[DATA_FORMAT_24_BIT]

• CTRL[DATA_FORMAT_18_BIT]

• CTRL[DATA_FORMAT_16_BIT]

• CTRL[WORD_LENGTH]

• CTRL1[BYTE_PACKING_FORMAT]

typedef struct _elcdif_rgb_mode_config elcdif_rgb_mode_config_t

eLCDIF configure structure for RGB mode (DOTCLK mode).

typedef enum _elcdif_as_pixel_format elcdif_as_pixel_format_t

eLCDIF alpha surface pixel format.

typedef struct _elcdif_as_buffer_config elcdif_as_buffer_config_t

eLCDIF alpha surface buffer configuration.

typedef enum _elcdif_alpha_mode elcdif_alpha_mode_t

eLCDIF alpha mode during blending.

typedef enum _elcdif_rop_mode elcdif_rop_mode_t

eLCDIF ROP mode during blending.

Explanation:

• AS: Alpha surface

• PS: Process surface

• nAS: Alpha surface NOT value

• nPS: Process surface NOT value

typedef struct _elcdif_as_blend_config elcdif_as_blend_config_t

eLCDIF alpha surface blending configuration.

typedef enum _elcdif_lut elcdif_lut_t

eLCDIF LUT

The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel before output to external displayer.

There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address determins which memory to use.

typedef enum _elcdif_pixel_component_order elcdif_pixel_component_order_t

eLCDIF pixel component order.

ELCDIF_CTRL1_IRQ_MASK

ELCDIF_CTRL1_IRQ_EN_MASK

ELCDIF_AS_CTRL_IRQ_MASK

ELCDIF_AS_CTRL_IRQ_EN_MASK

FSL_FEATURE_LCDIF_HAS_PXP_HANDSHAKE

ELCDIF_ADDR_CPU_2_IP(addr)

ELCDIF_LUT_ENTRY_NUM

struct _elcdif_pixel_format_reg

#include <fsl_elcdif.h>

The register value when using different pixel format.

These register bits control the pixel format:

• CTRL[DATA_FORMAT_24_BIT]

• CTRL[DATA_FORMAT_18_BIT]

• CTRL[DATA_FORMAT_16_BIT]

• CTRL[WORD_LENGTH]

• CTRL1[BYTE_PACKING_FORMAT]

Public Members

uint32_t regCtrl

Value of register CTRL.

uint32_t regCtrl1

Value of register CTRL1.

struct _elcdif_rgb_mode_config

#include <fsl_elcdif.h>

eLCDIF configure structure for RGB mode (DOTCLK mode).

Public Members

uint16_t panelWidth

Display panel width, pixels per line.

uint16_t panelHeight

Display panel height, how many lines per panel.

uint8_t hsw

HSYNC pulse width.

uint8_t hfp

Horizontal front porch.

uint8_t hbp

Horizontal back porch.

uint8_t vsw

VSYNC pulse width.

uint8_t vfp

Vrtical front porch.

uint8_t vbp

Vertical back porch.

uint32_t polarityFlags

OR’ed value of _elcdif_polarity_flags, used to contol the signal polarity.

uint32_t bufferAddr

Frame buffer address.

elcdif_pixel_format_t pixelFormat

Pixel format.

elcdif_lcd_data_bus_t dataBus

LCD data bus.

struct _elcdif_as_buffer_config

#include <fsl_elcdif.h>

eLCDIF alpha surface buffer configuration.

Public Members

uint32_t bufferAddr

Buffer address.

elcdif_as_pixel_format_t pixelFormat

Pixel format.

struct _elcdif_as_blend_config

#include <fsl_elcdif.h>

eLCDIF alpha surface blending configuration.

Public Members

uint8_t alpha

User defined alpha value, only used when alphaMode is kELCDIF_AlphaOverride or kELCDIF_AlphaRop.

bool invertAlpha

Set true to invert the alpha.

elcdif_alpha_mode_t alphaMode

Alpha mode.

elcdif_rop_mode_t ropMode

ROP mode, only valid when alphaMode is kELCDIF_AlphaRop.

ENC: Quadrature Encoder/Decoder

void ENC_Init(ENC_Type *base, const enc_config_t *config)

Initialization for the ENC module.

This function is to make the initialization for the ENC module. It should be called firstly before any operation to the ENC with the operations like:

• Enable the clock for ENC module.

• Configure the ENC’s working attributes.

Parameters:

• base – ENC peripheral base address.

• config – Pointer to configuration structure. See to “enc_config_t”.

void ENC_Deinit(ENC_Type *base)

De-initialization for the ENC module.

This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with the operations like:

• Disable the clock for ENC module.

Parameters:

• base – ENC peripheral base address.

void ENC_GetDefaultConfig(enc_config_t *config)

Get an available pre-defined settings for ENC’s configuration.

This function initializes the ENC configuration structure with an available settings, the default value are:

config->enableReverseDirection                = false;
config->decoderWorkMode                       = kENC_DecoderWorkAsNormalMode;
config->HOMETriggerMode                       = kENC_HOMETriggerDisabled;
config->INDEXTriggerMode                      = kENC_INDEXTriggerDisabled;
config->enableTRIGGERClearPositionCounter     = false;
config->enableTRIGGERClearHoldPositionCounter = false;
config->enableWatchdog                        = false;
config->watchdogTimeoutValue                  = 0U;
config->filterCount                           = 0U;
config->filterSamplePeriod                    = 0U;
config->positionMatchMode                     = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
config->positionCompareValue                  = 0xFFFFFFFFU;
config->revolutionCountCondition              = kENC_RevolutionCountOnINDEXPulse;
config->enableModuloCountMode                 = false;
config->positionModulusValue                  = 0U;
config->positionInitialValue                  = 0U;
config->prescalerValue                        = kENC_ClockDiv1;
config->enablePeriodMeasurementFunction       = true;

Parameters:

• config – Pointer to a variable of configuration structure. See to “enc_config_t”.

void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)

Load the initial position value to position counter.

This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters:

• base – ENC peripheral base address.

void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)

Enable and configure the self test function.

This function is to enable and configuration the self test function. It controls and sets the frequency of a quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. It is a factory test feature; however, it may be useful to customers’ software development and testing.

Parameters:

• base – ENC peripheral base address.

• config – Pointer to configuration structure. See to “enc_self_test_config_t”. Pass “NULL” to disable.

void ENC_EnableWatchdog(ENC_Type *base, bool enable)

Enable watchdog for ENC module.

Parameters:

• base – ENC peripheral base address

• enable – Enables or disables the watchdog

void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value)

Set initial position value for ENC module.

Parameters:

• base – ENC peripheral base address

• value – Positive initial value

uint32_t ENC_GetStatusFlags(ENC_Type *base)

Get the status flags.

Parameters:

• base – ENC peripheral base address.

Returns:

Mask value of status flags. For available mask, see to “_enc_status_flags”.

void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)

Clear the status flags.

Parameters:

• base – ENC peripheral base address.

• mask – Mask value of status flags to be cleared. For available mask, see to “_enc_status_flags”.

static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base)

Get the signals’ real-time status.

Parameters:

• base – ENC peripheral base address.

Returns:

Mask value of signals’ real-time status. For available mask, see to “_enc_signal_status_flags”

void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)

Enable the interrupts.

Parameters:

• base – ENC peripheral base address.

• mask – Mask value of interrupts to be enabled. For available mask, see to “_enc_interrupt_enable”.

void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)

Disable the interrupts.

Parameters:

• base – ENC peripheral base address.

• mask – Mask value of interrupts to be disabled. For available mask, see to “_enc_interrupt_enable”.

uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)

Get the enabled interrupts’ flags.

Parameters:

• base – ENC peripheral base address.

Returns:

Mask value of enabled interrupts.

uint32_t ENC_GetPositionValue(ENC_Type *base)

Get the current position counter’s value.

Parameters:

• base – ENC peripheral base address.

Returns:

Current position counter’s value.

uint32_t ENC_GetHoldPositionValue(ENC_Type *base)

Get the hold position counter’s value.

When any of the counter registers is read, the contents of each counter register is written to the corresponding hold register. Taking a snapshot of the counters’ values provides a consistent view of a system position and a velocity to be attained.

Parameters:

• base – ENC peripheral base address.

Returns:

Hold position counter’s value.

static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base)

Get the position difference counter’s value.

Parameters:

• base – ENC peripheral base address.

Returns:

The position difference counter’s value.

static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base)

Get the hold position difference counter’s value.

When any of the counter registers is read, the contents of each counter register is written to the corresponding hold register. Taking a snapshot of the counters’ values provides a consistent view of a system position and a velocity to be attained.

Parameters:

• base – ENC peripheral base address.

Returns:

Hold position difference counter’s value.

static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base)

Get the position revolution counter’s value.

Parameters:

• base – ENC peripheral base address.

Returns:

The position revolution counter’s value.

static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base)

Get the hold position revolution counter’s value.

When any of the counter registers is read, the contents of each counter register is written to the corresponding hold register. Taking a snapshot of the counters’ values provides a consistent view of a system position and a velocity to be attained.

Parameters:

• base – ENC peripheral base address.

Returns:

Hold position revolution counter’s value.

static inline uint16_t ENC_GetLastEdgeTimeValue(ENC_Type *base)

Get the last edge time value.

Parameters:

• base – ENC peripheral base address.

Returns:

The last edge time hold value.

static inline uint16_t ENC_GetHoldLastEdgeTimeValue(ENC_Type *base)

Get the last edge time hold value.

Parameters:

• base – ENC peripheral base address.

Returns:

The last edge time hold value.

static inline uint16_t ENC_GetPositionDifferencePeriodValue(ENC_Type *base)

Get the position difference period value.

Parameters:

• base – ENC peripheral base address.

Returns:

The position difference period hold value.

static inline uint16_t ENC_GetPositionDifferencePeriodBufferValue(ENC_Type *base)

Get the position difference period buffer value.

Parameters:

• base – ENC peripheral base address.

Returns:

The position difference period hold value.

static inline uint16_t ENC_GetHoldPositionDifferencePeriodValue(ENC_Type *base)

Get the position difference period hold value.

Parameters:

• base – ENC peripheral base address.

Returns:

The position difference period hold value.

enum _enc_interrupt_enable

Interrupt enable/disable mask.

Values:

enumerator kENC_HOMETransitionInterruptEnable

HOME interrupt enable.

enumerator kENC_INDEXPulseInterruptEnable

INDEX pulse interrupt enable.

enumerator kENC_WatchdogTimeoutInterruptEnable

Watchdog timeout interrupt enable.

enumerator kENC_PositionCompareInerruptEnable

Position compare interrupt enable.

enumerator kENC_PositionRollOverInterruptEnable

Roll-over interrupt enable.

enumerator kENC_PositionRollUnderInterruptEnable

Roll-under interrupt enable.

enum _enc_status_flags

Status flag mask.

These flags indicate the counter’s events.

Values:

enumerator kENC_HOMETransitionFlag

HOME signal transition interrupt request.

enumerator kENC_INDEXPulseFlag

INDEX Pulse Interrupt Request.

enumerator kENC_WatchdogTimeoutFlag

Watchdog timeout interrupt request.

enumerator kENC_PositionCompareFlag

Position compare interrupt request.

enumerator kENC_PositionRollOverFlag

Roll-over interrupt request.

enumerator kENC_PositionRollUnderFlag

Roll-under interrupt request.

enumerator kENC_LastCountDirectionFlag

Last count was in the up direction, or the down direction.

enum _enc_signal_status_flags

Signal status flag mask.

These flags indicate the counter’s signal.

Values:

enumerator kENC_RawHOMEStatusFlag

Raw HOME input.

enumerator kENC_RawINDEXStatusFlag

Raw INDEX input.

enumerator kENC_RawPHBStatusFlag

Raw PHASEB input.

enumerator kENC_RawPHAEXStatusFlag

Raw PHASEA input.

enumerator kENC_FilteredHOMEStatusFlag

The filtered version of HOME input.

enumerator kENC_FilteredINDEXStatusFlag

The filtered version of INDEX input.

enumerator kENC_FilteredPHBStatusFlag

The filtered version of PHASEB input.

enumerator kENC_FilteredPHAStatusFlag

The filtered version of PHASEA input.

enum _enc_home_trigger_mode

Define HOME signal’s trigger mode.

The ENC would count the trigger from HOME signal line.

Values:

enumerator kENC_HOMETriggerDisabled

HOME signal’s trigger is disabled.

enumerator kENC_HOMETriggerOnRisingEdge

Use positive going edge-to-trigger initialization of position counters.

enumerator kENC_HOMETriggerOnFallingEdge

Use negative going edge-to-trigger initialization of position counters.

enum _enc_index_trigger_mode

Define INDEX signal’s trigger mode.

The ENC would count the trigger from INDEX signal line.

Values:

enumerator kENC_INDEXTriggerDisabled

INDEX signal’s trigger is disabled.

enumerator kENC_INDEXTriggerOnRisingEdge

Use positive going edge-to-trigger initialization of position counters.

enumerator kENC_INDEXTriggerOnFallingEdge

Use negative going edge-to-trigger initialization of position counters.

enum _enc_decoder_work_mode

Define type for decoder work mode.

The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 means counting down. Otherwise, the direction is reversed.

Values:

enumerator kENC_DecoderWorkAsNormalMode

Use standard quadrature decoder with PHASEA and PHASEB.

enumerator kENC_DecoderWorkAsSignalPhaseCountMode

PHASEA input generates a count signal while PHASEB input control the direction.

enum _enc_position_match_mode

Define type for the condition of POSMATCH pulses.

Values:

enumerator kENC_POSMATCHOnPositionCounterEqualToComapreValue

POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).

enumerator kENC_POSMATCHOnReadingAnyPositionCounter

POSMATCH pulses when any position counter register is read.

enum _enc_revolution_count_condition

Define type for determining how the revolution counter (REV) is incremented/decremented.

Values:

enumerator kENC_RevolutionCountOnINDEXPulse

Use INDEX pulse to increment/decrement revolution counter.

enumerator kENC_RevolutionCountOnRollOverModulus

Use modulus counting roll-over/under to increment/decrement revolution counter.

enum _enc_self_test_direction

Define type for direction of self test generated signal.

Values:

enumerator kENC_SelfTestDirectionPositive

Self test generates the signal in positive direction.

enumerator kENC_SelfTestDirectionNegative

Self test generates the signal in negative direction.

enum _enc_prescaler

Define prescaler value for clock in CTRL3.

The clock is prescaled by a value of 2^PRSC which means that the prescaler logic can divide the clock by a minimum of 1 and a maximum of 32,768.

Values:

enumerator kENC_ClockDiv1

enumerator kENC_ClockDiv2

enumerator kENC_ClockDiv4

enumerator kENC_ClockDiv8

enumerator kENC_ClockDiv16

enumerator kENC_ClockDiv32

enumerator kENC_ClockDiv64

enumerator kENC_ClockDiv128

enumerator kENC_ClockDiv256

enumerator kENC_ClockDiv512

enumerator kENC_ClockDiv1024

enumerator kENC_ClockDiv2048

enumerator kENC_ClockDiv4096

enumerator kENC_ClockDiv8192

enumerator kENC_ClockDiv16384

enumerator kENC_ClockDiv32768

enum _enc_filter_prescaler

Define input filter prescaler value.

The input filter prescaler value is to prescale the IPBus clock. (Frequency of FILT clock) = (Frequency of IPBus clock) / 2^FILT_PRSC.

Values:

enumerator kENC_FilterPrescalerDiv1

Input filter prescaler is 1.

enumerator kENC_FilterPrescalerDiv2

Input filter prescaler is 2.

enumerator kENC_FilterPrescalerDiv4

Input filter prescaler is 4.

enumerator kENC_FilterPrescalerDiv8

Input filter prescaler is 8.

enumerator kENC_FilterPrescalerDiv16

Input filter prescaler is 16.

enumerator kENC_FilterPrescalerDiv32

Input filter prescaler is 32.

enumerator kENC_FilterPrescalerDiv64

Input filter prescaler is 64.

enumerator kENC_FilterPrescalerDiv128

Input filter prescaler is 128.

typedef enum _enc_home_trigger_mode enc_home_trigger_mode_t

Define HOME signal’s trigger mode.

The ENC would count the trigger from HOME signal line.

typedef enum _enc_index_trigger_mode enc_index_trigger_mode_t

Define INDEX signal’s trigger mode.

The ENC would count the trigger from INDEX signal line.

typedef enum _enc_decoder_work_mode enc_decoder_work_mode_t

Define type for decoder work mode.

The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 means counting down. Otherwise, the direction is reversed.

typedef enum _enc_position_match_mode enc_position_match_mode_t

Define type for the condition of POSMATCH pulses.

typedef enum _enc_revolution_count_condition enc_revolution_count_condition_t

Define type for determining how the revolution counter (REV) is incremented/decremented.

typedef enum _enc_self_test_direction enc_self_test_direction_t

Define type for direction of self test generated signal.

typedef enum _enc_prescaler enc_prescaler_t

Define prescaler value for clock in CTRL3.

The clock is prescaled by a value of 2^PRSC which means that the prescaler logic can divide the clock by a minimum of 1 and a maximum of 32,768.

typedef enum _enc_filter_prescaler enc_filter_prescaler_t

Define input filter prescaler value.

The input filter prescaler value is to prescale the IPBus clock. (Frequency of FILT clock) = (Frequency of IPBus clock) / 2^FILT_PRSC.

typedef struct _enc_config enc_config_t

Define user configuration structure for ENC module.

typedef struct _enc_self_test_config enc_self_test_config_t

Define configuration structure for self test module.

The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. This is a factory test feature. It is also useful to customers’ software development and testing.

FSL_ENC_DRIVER_VERSION

struct _enc_config

#include <fsl_enc.h>

Define user configuration structure for ENC module.

Public Members

bool enableReverseDirection

Enable reverse direction counting.

enc_decoder_work_mode_t decoderWorkMode

Enable signal phase count mode.

enc_home_trigger_mode_t HOMETriggerMode

Enable HOME to initialize position counters.

enc_index_trigger_mode_t INDEXTriggerMode

Enable INDEX to initialize position counters.

bool enableTRIGGERClearPositionCounter

Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not.

bool enableTRIGGERClearHoldPositionCounter

Enable update of hold registers on rising edge of TRIGGER, or not.

bool enableWatchdog

Enable the watchdog to detect if the target is moving or not.

uint16_t watchdogTimeoutValue

Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer. This field is only available when “enableWatchdog” = true. The available value is a 16-bit unsigned number.

enc_filter_prescaler_t filterPrescaler

Input filter prescaler.

uint16_t filterCount

Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 samples. The Available range is 0 - 7.

uint16_t filterSamplePeriod

Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

enc_position_match_mode_t positionMatchMode

The condition of POSMATCH pulses.

uint32_t positionCompareValue

Position compare value. The available value is a 32-bit number.

enc_revolution_count_condition_t revolutionCountCondition

Revolution Counter Modulus Enable.

bool enableModuloCountMode

Enable Modulo Counting.

uint32_t positionModulusValue

Position modulus value. This value would be available only when “enableModuloCountMode” = true. The available value is a 32-bit number.

uint32_t positionInitialValue

Position initial value. The available value is a 32-bit number.

bool enablePeriodMeasurementFunction

Enable period measurement function.

enc_prescaler_t prescalerValue

The value of prescaler.

struct _enc_self_test_config

#include <fsl_enc.h>

Define configuration structure for self test module.

The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. This is a factory test feature. It is also useful to customers’ software development and testing.

Public Members

enc_self_test_direction_t signalDirection

Direction of self test generated signal.

uint16_t signalCount

Hold the number of quadrature advances to generate. The available range is 0 - 255.

uint16_t signalPeriod

Hold the period of quadrature phase in IPBus clock cycles. The available range is 0 - 31.

ENET: Ethernet MAC Driver

void ENET_GetDefaultConfig(enet_config_t *config)

Gets the ENET default configuration structure.

The purpose of this API is to get the default ENET MAC controller configure structure for ENET_Init(). User may use the initialized structure unchanged in ENET_Init(), or modify some fields of the structure before calling ENET_Init(). Example:

enet_config_t config;
ENET_GetDefaultConfig(&config);

Parameters:

• config – The ENET mac controller configuration structure pointer.

status_t ENET_Up(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)

Initializes the ENET module.

This function initializes the module with the ENET configuration.

Note

ENET has two buffer descriptors legacy buffer descriptors and enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor by defining “ENET_ENHANCEDBUFFERDESCRIPTOR_MODE” and calling ENET_Ptp1588Configure() to configure the 1588 feature and related buffers after calling ENET_Up().

Parameters:

• base – ENET peripheral base address.

• handle – ENET handler pointer.

• config – ENET mac configuration structure pointer. The “enet_config_t” type mac configuration return from ENET_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.

• bufferConfig – ENET buffer configuration structure pointer. The buffer configuration should be prepared for ENET Initialization. It is the start address of “ringNum” enet_buffer_config structures. To support added multi-ring features in some soc and compatible with the previous enet driver version. For single ring supported, this bufferConfig is a buffer configure structure pointer, for multi-ring supported and used case, this bufferConfig pointer should be a buffer configure structure array pointer.

• macAddr – ENET mac address of Ethernet device. This MAC address should be provided.

• srcClock_Hz – The internal module clock source for MII clock.

Return values:

• kStatus_Success – Succeed to initialize the ethernet driver.

• kStatus_ENET_InitMemoryFail – Init fails since buffer memory is not enough.

status_t ENET_Init(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)

Initializes the ENET module.

This function ungates the module clock and initializes it with the ENET configuration.

Note

ENET has two buffer descriptors legacy buffer descriptors and enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor by defining “ENET_ENHANCEDBUFFERDESCRIPTOR_MODE” and calling ENET_Ptp1588Configure() to configure the 1588 feature and related buffers after calling ENET_Init().

Parameters:

• base – ENET peripheral base address.

• handle – ENET handler pointer.

• config – ENET mac configuration structure pointer. The “enet_config_t” type mac configuration return from ENET_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.

• bufferConfig – ENET buffer configuration structure pointer. The buffer configuration should be prepared for ENET Initialization. It is the start address of “ringNum” enet_buffer_config structures. To support added multi-ring features in some soc and compatible with the previous enet driver version. For single ring supported, this bufferConfig is a buffer configure structure pointer, for multi-ring supported and used case, this bufferConfig pointer should be a buffer configure structure array pointer.

• macAddr – ENET mac address of Ethernet device. This MAC address should be provided.

• srcClock_Hz – The internal module clock source for MII clock.

Return values:

• kStatus_Success – Succeed to initialize the ethernet driver.

• kStatus_ENET_InitMemoryFail – Init fails since buffer memory is not enough.

void ENET_Down(ENET_Type *base)

Stops the ENET module.

This function disables the ENET module.

Parameters:

• base – ENET peripheral base address.

void ENET_Deinit(ENET_Type *base)

Deinitializes the ENET module.

This function gates the module clock, clears ENET interrupts, and disables the ENET module.

Parameters:

• base – ENET peripheral base address.

static inline void ENET_Reset(ENET_Type *base)

Resets the ENET module.

This function restores the ENET module to reset state. Note that this function sets all registers to reset state. As a result, the ENET module can’t work after calling this function.

Parameters:

• base – ENET peripheral base address.

void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)

Sets the ENET MII speed and duplex.

This API is provided to dynamically change the speed and dulpex for MAC.

Parameters:

• base – ENET peripheral base address.

• speed – The speed of the RMII mode.

• duplex – The duplex of the RMII mode.

void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)

Sets the ENET SMI(serial management interface)- MII management interface.

Parameters:

• base – ENET peripheral base address.

• srcClock_Hz – This is the ENET module clock frequency. See clock distribution.

• isPreambleDisabled – The preamble disable flag.

  • true Enables the preamble.

  • false Disables the preamble.

static inline bool ENET_GetSMI(ENET_Type *base)

Gets the ENET SMI- MII management interface configuration.

This API is used to get the SMI configuration to check whether the MII management interface has been set.

Parameters:

• base – ENET peripheral base address.

Returns:

The SMI setup status true or false.

static inline uint32_t ENET_ReadSMIData(ENET_Type *base)

Reads data from the PHY register through an SMI interface.

Parameters:

• base – ENET peripheral base address.

Returns:

The data read from PHY

static inline void ENET_StartSMIWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data)

Sends the MDIO IEEE802.3 Clause 22 format write command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOWrite() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address. Range from 0 ~ 31.

• regAddr – The PHY register address. Range from 0 ~ 31.

• operation – The write operation.

• data – The data written to PHY.

static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation)

Sends the MDIO IEEE802.3 Clause 22 format read command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIORead() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address. Range from 0 ~ 31.

• regAddr – The PHY register address. Range from 0 ~ 31.

• operation – The read operation.

status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 22 format.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address. Range from 0 ~ 31.

• regAddr – The PHY register. Range from 0 ~ 31.

• data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 22 format.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address. Range from 0 ~ 31.

• regAddr – The PHY register. Range from 0 ~ 31.

• pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)

Sends the MDIO IEEE802.3 Clause 45 format write register command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Write()/ENET_MDIOC45Read() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 45 format write data command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Write() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• data – The data written to PHY.

static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr)

Sends the MDIO IEEE802.3 Clause 45 format read data command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Read() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 45 format.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

• data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 45 format.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

• pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled)

Control the usage of the delayed tx/rx RGMII clock.

Parameters:

• base – ENET peripheral base address.

• txEnabled – Enable or disable to generate the delayed version of RGMII_TXC.

• rxEnabled – Enable or disable to use the delayed version of RGMII_RXC.

void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)

Sets the ENET module Mac address.

Parameters:

• base – ENET peripheral base address.

• macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)

Gets the ENET module Mac address.

Parameters:

• base – ENET peripheral base address.

• macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address)

Adds the ENET device to a multicast group.

Parameters:

• base – ENET peripheral base address.

• address – The six-byte multicast group address which is provided by application.

void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address)

Moves the ENET device from a multicast group.

Parameters:

• base – ENET peripheral base address.

• address – The six-byte multicast group address which is provided by application.

static inline void ENET_ActiveRead(ENET_Type *base)

Activates frame reception for multiple rings.

This function is to active the enet read process.

Note

This must be called after the MAC configuration and state are ready. It must be called after the ENET_Init(). This should be called when the frame reception is required.

Parameters:

• base – ENET peripheral base address.

static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable)

Enables/disables the MAC to enter sleep mode. This function is used to set the MAC enter sleep mode. When entering sleep mode, the magic frame wakeup interrupt should be enabled to wake up MAC from the sleep mode and reset it to normal mode.

Parameters:

• base – ENET peripheral base address.

• enable – True enable sleep mode, false disable sleep mode.

static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)

Gets ENET transmit and receive accelerator functions from MAC controller.

Parameters:

• base – ENET peripheral base address.

• txAccelOption – The transmit accelerator option. The “enet_tx_accelerator_t” is recommended to be used to as the mask to get the exact the accelerator option.

• rxAccelOption – The receive accelerator option. The “enet_rx_accelerator_t” is recommended to be used to as the mask to get the exact the accelerator option.

static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)

Enables the ENET interrupt.

This function enables the ENET interrupt according to the provided mask. The mask is a logical OR of enumeration members. See enet_interrupt_enable_t. For example, to enable the TX frame interrupt and RX frame interrupt, do the following.

ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupts to enable. This is a logical OR of the enumeration enet_interrupt_enable_t.

static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)

Disables the ENET interrupt.

This function disables the ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See enet_interrupt_enable_t. For example, to disable the TX frame interrupt and RX frame interrupt, do the following.

ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupts to disable. This is a logical OR of the enumeration enet_interrupt_enable_t.

static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base)

Gets the ENET interrupt status flag.

Parameters:

• base – ENET peripheral base address.

Returns:

The event status of the interrupt source. This is the logical OR of members of the enumeration enet_interrupt_enable_t.

static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask)

Clears the ENET interrupt events status flag.

This function clears enabled ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See the enet_interrupt_enable_t. For example, to clear the TX frame interrupt and RX frame interrupt, do the following.

ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupt source to be cleared. This is the logical OR of members of the enumeration enet_interrupt_enable_t.

void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Rx IRQ handler.

Parameters:

• base – ENET peripheral base address.

• ISRHandler – The handler to install.

void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Tx IRQ handler.

Parameters:

• base – ENET peripheral base address.

• ISRHandler – The handler to install.

void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Err IRQ handler.

Parameters:

• base – ENET peripheral base address.

• ISRHandler – The handler to install.

void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId)

Gets the error statistics of a received frame for ENET specified ring.

This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. This is an example.

status = ENET_GetRxFrameSize(&g_handle, &length, 0);
if (status == kStatus_ENET_RxFrameError)
{
    Comments: Get the error information of the received frame.
    ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic, 0);
    Comments: update the receive buffer.
    ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0);
}

Parameters:

• handle – The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init.

• eErrorStatic – The error statistics structure pointer.

• ringId – The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1).

void ENET_EnableStatistics(ENET_Type *base, bool enable)

Enables/disables collection of transfer statistics.

Note that this function does not reset any of the already collected data, use the function ENET_ResetStatistics to clear the transfer statistics if needed.

Parameters:

• base – ENET peripheral base address.

• enable – True enable statistics collection, false disable statistics collection.

void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics)

Gets transfer statistics.

Copies the actual value of hardware counters into the provided structure. Calling this function does not reset the counters in hardware.

Parameters:

• base – ENET peripheral base address.

• statistics – The statistics structure pointer.

void ENET_ResetStatistics(ENET_Type *base)

Resets transfer statistics.

Sets the value of hardware transfer counters to zero.

Parameters:

• base – ENET peripheral base address.

status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId)

Gets the size of the read frame for specified ring.

This function gets a received frame size from the ENET buffer descriptors.

Note

The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to receive frame and update the BD if the result is not “kStatus_ENET_RxFrameEmpty”.

Parameters:

• handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.

• length – The length of the valid frame received.

• ringId – The ring index or ring number.

Return values:

• kStatus_ENET_RxFrameEmpty – No frame received. Should not call ENET_ReadFrame to read frame.

• kStatus_ENET_RxFrameError – Data error happens. ENET_ReadFrame should be called with NULL data and NULL length to update the receive buffers.

• kStatus_Success – Receive a frame Successfully then the ENET_ReadFrame should be called with the right data buffer and the captured data length input.

status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts)

Reads a frame from the ENET device. This function reads a frame (both the data and the length) from the ENET buffer descriptors. User can get timestamp through ts pointer if the ts is not NULL.

Note

It doesn’t store the timestamp in the receive timestamp queue. The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time consumption. This is an example:

uint32_t length;
enet_handle_t g_handle;
Comments: Get the received frame size firstly.
status = ENET_GetRxFrameSize(&g_handle, &length, 0);
if (length != 0)
{
    Comments: Allocate memory here with the size of "length"
    uint8_t *data = memory allocate interface;
    if (!data)
    {
        ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL);
        Comments: Add the console warning log.
    }
    else
    {
        status = ENET_ReadFrame(ENET, &g_handle, data, length, 0, NULL);
        Comments: Call stack input API to deliver the data to stack
    }
}
else if (status == kStatus_ENET_RxFrameError)
{
    Comments: Update the received buffer when a error frame is received.
    ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL);
}

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.

• data – The data buffer provided by user to store the frame which memory size should be at least “length”.

• length – The size of the data buffer which is still the length of the received frame.

• ringId – The ring index or ring number.

• ts – The timestamp address to store received timestamp.

Returns:

The execute status, successful or failure.

status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length, uint8_t ringId, bool tsFlag, void *context)

Transmits an ENET frame for specified ring.

Note

The CRC is automatically appended to the data. Input the data to send without the CRC. This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time consumption.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• data – The data buffer provided by user to send.

• length – The length of the data to send.

• ringId – The ring index or ring number.

• tsFlag – Timestamp enable flag.

• context – Used by user to handle some events after transmit over.

Return values:

• kStatus_Success – Send frame succeed.

• kStatus_ENET_TxFrameBusy – Transmit buffer descriptor is busy under transmission. The transmit busy happens when the data send rate is over the MAC capacity. The waiting mechanism is recommended to be added after each call return with kStatus_ENET_TxFrameBusy.

status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId)

Enable or disable tx descriptors reclaim mechanism.

Note

This function must be called when no pending send frame action. Set enable if you want to reclaim context or timestamp in interrupt.

Parameters:

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• isEnable – Enable or disable flag.

• ringId – The ring index or ring number.

Return values:

• kStatus_Success – Succeed to enable/disable Tx reclaim.

• kStatus_Fail – Fail to enable/disable Tx reclaim.

void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId)

Reclaim tx descriptors. This function is used to update the tx descriptor status and store the tx timestamp when the 1588 feature is enabled. This is called by the transmit interupt IRQ handler after the complete of a frame transmission.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• ringId – The ring index or ring number.

status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId)

Receives one frame in specified BD ring with zero copy.

This function uses the user-defined allocation and free callbacks. Every time application gets one frame through this function, driver stores the buffer address(es) in enet_buffer_struct_t and allocate new buffer(s) for the BD(s). If there’s no memory buffer in the pool, this function drops current one frame to keep the Rx frame in BD ring is as fresh as possible.

Note

Application must provide a memory pool including at least BD number + n buffers in order for this function to work properly, because each BD must always take one buffer while driver is running, then other extra n buffer(s) can be taken by application. Here n is the ceil(max_frame_length(set by RCR) / bd_rx_size(set by MRBR)). Application must also provide an array structure in rxFrame->rxBuffArray with n index to receive one complete frame in any case.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• rxFrame – The received frame information structure provided by user.

• ringId – The ring index or ring number.

Return values:

• kStatus_Success – Succeed to get one frame and allocate new memory for Rx buffer.

• kStatus_ENET_RxFrameEmpty – There’s no Rx frame in the BD.

• kStatus_ENET_RxFrameError – There’s issue in this receiving.

• kStatus_ENET_RxFrameDrop – There’s no new buffer memory for BD, drop this frame.

status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId)

Sends one frame in specified BD ring with zero copy.

This function supports scattered buffer transmit, user needs to provide the buffer array.

Note

Tx reclaim should be enabled to ensure the Tx buffer ownership can be given back to application after Tx is over.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• txFrame – The Tx frame structure.

• ringId – The ring index or ring number.

Return values:

• kStatus_Success – Succeed to send one frame.

• kStatus_ENET_TxFrameBusy – The BD is not ready for Tx or the reclaim operation still not finishs.

• kStatus_ENET_TxFrameOverLen – The Tx frame length is over max ethernet frame length.

void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)

The transmit IRQ handler.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer.

void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)

The receive IRQ handler.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer.

void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)

Some special IRQ handler including the error, mii, wakeup irq handler.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer.

void ENET_Ptp1588IRQHandler(ENET_Type *base)

the common IRQ handler for the 1588 irq handler.

This is used for the 1588 timer interrupt.

Parameters:

• base – ENET peripheral base address.

void ENET_CommonFrame0IRQHandler(ENET_Type *base)

the common IRQ handler for the tx/rx/error etc irq handler.

This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0).

Parameters:

• base – ENET peripheral base address.

FSL_ENET_DRIVER_VERSION

Defines the driver version.

ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK

Empty bit mask.

ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK

Software owner one mask.

ENET_BUFFDESCRIPTOR_RX_WRAP_MASK

Next buffer descriptor is the start address.

ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask

Software owner two mask.

ENET_BUFFDESCRIPTOR_RX_LAST_MASK

Last BD of the frame mask.

ENET_BUFFDESCRIPTOR_RX_MISS_MASK

Received because of the promiscuous mode.

ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK

Broadcast packet mask.

ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK

Multicast packet mask.

ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK

Length violation mask.

ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK

Non-octet aligned frame mask.

ENET_BUFFDESCRIPTOR_RX_CRC_MASK

CRC error mask.

ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK

FIFO overrun mask.

ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK

Frame is truncated mask.

ENET_BUFFDESCRIPTOR_TX_READY_MASK

Ready bit mask.

ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK

Software owner one mask.

ENET_BUFFDESCRIPTOR_TX_WRAP_MASK

Wrap buffer descriptor mask.

ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK

Software owner two mask.

ENET_BUFFDESCRIPTOR_TX_LAST_MASK

Last BD of the frame mask.

ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK

Transmit CRC mask.

ENET_FRAME_MAX_FRAMELEN

Default maximum Ethernet frame size without VLAN tag.

ENET_FRAME_VLAN_TAGLEN

Ethernet single VLAN tag size.

ENET_FRAME_CRC_LEN

CRC size in a frame.

ENET_FRAME_TX_LEN_LIMITATION(x)

ENET_FIFO_MIN_RX_FULL

ENET minimum receive FIFO full.

ENET_RX_MIN_BUFFERSIZE

ENET minimum buffer size.

ENET_PHY_MAXADDRESS

Maximum PHY address.

ENET_TX_INTERRUPT

Enet Tx interrupt flag.

ENET_RX_INTERRUPT

Enet Rx interrupt flag.

ENET_TS_INTERRUPT

Enet timestamp interrupt flag.

ENET_ERR_INTERRUPT

Enet error interrupt flag.

Defines the status return codes for transaction.

Values:

enumerator kStatus_ENET_InitMemoryFail

Init fails since buffer memory is not enough.

enumerator kStatus_ENET_RxFrameError

A frame received but data error happen.

enumerator kStatus_ENET_RxFrameFail

Failed to receive a frame.

enumerator kStatus_ENET_RxFrameEmpty

No frame arrive.

enumerator kStatus_ENET_RxFrameDrop

Rx frame is dropped since no buffer memory.

enumerator kStatus_ENET_TxFrameOverLen

Tx frame over length.

enumerator kStatus_ENET_TxFrameBusy

Tx buffer descriptors are under process.

enumerator kStatus_ENET_TxFrameFail

Transmit frame fail.

enum _enet_mii_mode

Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.

Values:

enumerator kENET_MiiMode

MII mode for data interface.

enumerator kENET_RmiiMode

RMII mode for data interface.

enumerator kENET_RgmiiMode

RGMII mode for data interface.

enum _enet_mii_speed

Defines the 10/100/1000 Mbps speed for the MII data interface.

Notice: “kENET_MiiSpeed1000M” only supported when mii mode is “kENET_RgmiiMode”.

Values:

enumerator kENET_MiiSpeed10M

Speed 10 Mbps.

enumerator kENET_MiiSpeed100M

Speed 100 Mbps.

enumerator kENET_MiiSpeed1000M

Speed 1000M bps.

enum _enet_mii_duplex

Defines the half or full duplex for the MII data interface.

Values:

enumerator kENET_MiiHalfDuplex

Half duplex mode.

enumerator kENET_MiiFullDuplex

Full duplex mode.

enum _enet_mii_write

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

Values:

enumerator kENET_MiiWriteNoCompliant

Write frame operation, but not MII-compliant.

enumerator kENET_MiiWriteValidFrame

Write frame operation for a valid MII management frame.

enum _enet_mii_read

Defines the read operation for the MII management frame.

Values:

enumerator kENET_MiiReadValidFrame

Read frame operation for a valid MII management frame.

enumerator kENET_MiiReadNoCompliant

Read frame operation, but not MII-compliant.

enum _enet_mii_extend_opcode

Define the MII opcode for extended MDIO_CLAUSES_45 Frame.

Values:

enumerator kENET_MiiAddrWrite_C45

Address Write operation.

enumerator kENET_MiiWriteFrame_C45

Write frame operation for a valid MII management frame.

enumerator kENET_MiiReadFrame_C45

Read frame operation for a valid MII management frame.

enum _enet_special_control_flag

Defines a special configuration for ENET MAC controller.

These control flags are provided for special user requirements. Normally, these control flags are unused for ENET initialization. For special requirements, set the flags to macSpecialConfig in the enet_config_t. The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store and forward. FIFO store and forward means that the FIFO read/send is started when a complete frame is stored in TX/RX FIFO. If this flag is set, configure rxFifoFullThreshold and txFifoWatermark in the enet_config_t.

Values:

enumerator kENET_ControlFlowControlEnable

Enable ENET flow control: pause frame.

enumerator kENET_ControlRxPayloadCheckEnable

Enable ENET receive payload length check.

enumerator kENET_ControlRxPadRemoveEnable

Padding is removed from received frames.

enumerator kENET_ControlRxBroadCastRejectEnable

Enable broadcast frame reject.

enumerator kENET_ControlMacAddrInsert

Enable MAC address insert.

enumerator kENET_ControlStoreAndFwdDisable

Enable FIFO store and forward.

enumerator kENET_ControlSMIPreambleDisable

Enable SMI preamble.

enumerator kENET_ControlPromiscuousEnable

Enable promiscuous mode.

enumerator kENET_ControlMIILoopEnable

Enable ENET MII loop back.

enumerator kENET_ControlVLANTagEnable

Enable normal VLAN (single vlan tag).

enumerator kENET_ControlSVLANEnable

Enable S-VLAN.

enumerator kENET_ControlVLANUseSecondTag

Enable extracting the second vlan tag for further processing.

enum _enet_interrupt_enable

List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

Values:

enumerator kENET_BabrInterrupt

Babbling receive error interrupt source

enumerator kENET_BabtInterrupt

Babbling transmit error interrupt source

enumerator kENET_GraceStopInterrupt

Graceful stop complete interrupt source

enumerator kENET_TxFrameInterrupt

TX FRAME interrupt source

enumerator kENET_TxBufferInterrupt

TX BUFFER interrupt source

enumerator kENET_RxFrameInterrupt

RX FRAME interrupt source

enumerator kENET_RxBufferInterrupt

RX BUFFER interrupt source

enumerator kENET_MiiInterrupt

MII interrupt source

enumerator kENET_EBusERInterrupt

Ethernet bus error interrupt source

enumerator kENET_LateCollisionInterrupt

Late collision interrupt source

enumerator kENET_RetryLimitInterrupt

Collision Retry Limit interrupt source

enumerator kENET_UnderrunInterrupt

Transmit FIFO underrun interrupt source

enumerator kENET_PayloadRxInterrupt

Payload Receive error interrupt source

enumerator kENET_WakeupInterrupt

WAKEUP interrupt source

enumerator kENET_TsAvailInterrupt

TS AVAIL interrupt source for PTP

enumerator kENET_TsTimerInterrupt

TS WRAP interrupt source for PTP

enum _enet_event

Defines the common interrupt event for callback use.

Values:

enumerator kENET_RxEvent

Receive event.

enumerator kENET_TxEvent

Transmit event.

enumerator kENET_ErrEvent

Error event: BABR/BABT/EBERR/LC/RL/UN/PLR .

enumerator kENET_WakeUpEvent

Wake up from sleep mode event.

enumerator kENET_TimeStampEvent

Time stamp event.

enumerator kENET_TimeStampAvailEvent

Time stamp available event.

enum _enet_idle_slope

Defines certain idle slope for bandwidth fraction.

Values:

enumerator kENET_IdleSlope1

The bandwidth fraction is about 0.002.

enumerator kENET_IdleSlope2

The bandwidth fraction is about 0.003.

enumerator kENET_IdleSlope4

The bandwidth fraction is about 0.008.

enumerator kENET_IdleSlope8

The bandwidth fraction is about 0.02.

enumerator kENET_IdleSlope16

The bandwidth fraction is about 0.03.

enumerator kENET_IdleSlope32

The bandwidth fraction is about 0.06.

enumerator kENET_IdleSlope64

The bandwidth fraction is about 0.11.

enumerator kENET_IdleSlope128

The bandwidth fraction is about 0.20.

enumerator kENET_IdleSlope256

The bandwidth fraction is about 0.33.

enumerator kENET_IdleSlope384

The bandwidth fraction is about 0.43.

enumerator kENET_IdleSlope512

The bandwidth fraction is about 0.50.

enumerator kENET_IdleSlope640

The bandwidth fraction is about 0.56.

enumerator kENET_IdleSlope768

The bandwidth fraction is about 0.60.

enumerator kENET_IdleSlope896

The bandwidth fraction is about 0.64.

enumerator kENET_IdleSlope1024

The bandwidth fraction is about 0.67.

enumerator kENET_IdleSlope1152

The bandwidth fraction is about 0.69.

enumerator kENET_IdleSlope1280

The bandwidth fraction is about 0.71.

enumerator kENET_IdleSlope1408

The bandwidth fraction is about 0.73.

enumerator kENET_IdleSlope1536

The bandwidth fraction is about 0.75.

enum _enet_tx_accelerator

Defines the transmit accelerator configuration.

Note that the hardware does not insert ICMPv6 protocol checksums as mentioned in errata ERR052152.

Values:

enumerator kENET_TxAccelIsShift16Enabled

Transmit FIFO shift-16.

enumerator kENET_TxAccelIpCheckEnabled

Insert IP header checksum.

enumerator kENET_TxAccelProtoCheckEnabled

Insert protocol checksum (TCP, UDP, ICMPv4).

enum _enet_rx_accelerator

Defines the receive accelerator configuration.

Note that the hardware does not validate ICMPv6 protocol checksums as mentioned in errata ERR052152.

Values:

enumerator kENET_RxAccelPadRemoveEnabled

Padding removal for short IP frames.

enumerator kENET_RxAccelIpCheckEnabled

Discard with wrong IP header checksum.

enumerator kENET_RxAccelProtoCheckEnabled

Discard with wrong protocol checksum (TCP, UDP, ICMPv4).

enumerator kENET_RxAccelMacCheckEnabled

Discard with Mac layer errors.

enumerator kENET_RxAccelisShift16Enabled

Receive FIFO shift-16.

typedef enum _enet_mii_mode enet_mii_mode_t

Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.

typedef enum _enet_mii_speed enet_mii_speed_t

Defines the 10/100/1000 Mbps speed for the MII data interface.

Notice: “kENET_MiiSpeed1000M” only supported when mii mode is “kENET_RgmiiMode”.

typedef enum _enet_mii_duplex enet_mii_duplex_t

Defines the half or full duplex for the MII data interface.

typedef enum _enet_mii_write enet_mii_write_t

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

typedef enum _enet_mii_read enet_mii_read_t

Defines the read operation for the MII management frame.

typedef enum _enet_mii_extend_opcode enet_mii_extend_opcode

Define the MII opcode for extended MDIO_CLAUSES_45 Frame.

typedef enum _enet_special_control_flag enet_special_control_flag_t

Defines a special configuration for ENET MAC controller.

These control flags are provided for special user requirements. Normally, these control flags are unused for ENET initialization. For special requirements, set the flags to macSpecialConfig in the enet_config_t. The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store and forward. FIFO store and forward means that the FIFO read/send is started when a complete frame is stored in TX/RX FIFO. If this flag is set, configure rxFifoFullThreshold and txFifoWatermark in the enet_config_t.

typedef enum _enet_interrupt_enable enet_interrupt_enable_t

List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

typedef enum _enet_event enet_event_t

Defines the common interrupt event for callback use.

typedef enum _enet_idle_slope enet_idle_slope_t

Defines certain idle slope for bandwidth fraction.

typedef enum _enet_tx_accelerator enet_tx_accelerator_t

Defines the transmit accelerator configuration.

Note that the hardware does not insert ICMPv6 protocol checksums as mentioned in errata ERR052152.

typedef enum _enet_rx_accelerator enet_rx_accelerator_t

Defines the receive accelerator configuration.

Note that the hardware does not validate ICMPv6 protocol checksums as mentioned in errata ERR052152.

typedef struct _enet_rx_bd_struct enet_rx_bd_struct_t

Defines the receive buffer descriptor structure for the little endian system.

typedef struct _enet_tx_bd_struct enet_tx_bd_struct_t

Defines the enhanced transmit buffer descriptor structure for the little endian system.

typedef struct _enet_data_error_stats enet_data_error_stats_t

Defines the ENET data error statistics structure.

typedef struct _enet_rx_frame_error enet_rx_frame_error_t

Defines the Rx frame error structure.

typedef struct _enet_transfer_stats enet_transfer_stats_t

Defines the ENET transfer statistics structure.

typedef struct enet_frame_info enet_frame_info_t

Defines the frame info structure.

typedef struct _enet_tx_dirty_ring enet_tx_dirty_ring_t

Defines the ENET transmit dirty addresses ring/queue structure.

typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId)

Defines the ENET Rx memory buffer alloc function pointer.

typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId)

Defines the ENET Rx memory buffer free function pointer.

typedef struct _enet_buffer_config enet_buffer_config_t

Defines the receive buffer descriptor configuration structure.

Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.

1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

2. The aligned transmit and receive buffer descriptor start address must be at least 64 bit aligned. However, it’s recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. buffer descriptors should be put in non-cacheable region when cache is enabled.

3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. Receive buffers should be continuous with the total size equal to “rxBdNumber * rxBuffSizeAlign”. Transmit buffers should be continuous with the total size equal to “txBdNumber * txBuffSizeAlign”. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

typedef struct _enet_intcoalesce_config enet_intcoalesce_config_t

Defines the interrupt coalescing configure structure.

typedef struct _enet_avb_config enet_avb_config_t

Defines the ENET AVB Configure structure.

This is used for to configure the extended ring 1 and ring 2.

1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel.

If CMP1,2,3 are not unused, please set them to the same value as CMP0.

1. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75.

typedef struct _enet_handle enet_handle_t

typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, enet_frame_info_t *frameInfo, void *userData)

ENET callback function.

typedef struct _enet_config enet_config_t

Defines the basic configuration structure for the ENET device.

Note:

1. macSpecialConfig is used for a special control configuration, A logical OR of “enet_special_control_flag_t”. For a special configuration for MAC, set this parameter to 0.

2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 2 - 128 bytes written to TX FIFO …. 3 - 192 bytes written to TX FIFO …. The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO …. txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 or for larger bus access latency 3 or larger due to contention for the system bus.

3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. If the end of the frame is stored in FIFO and the frame size if smaller than the txWatermark, the frame is still transmitted. The rule is the same for rxFifoFullThreshold in the receive direction.

4. When “kENET_ControlFlowControlEnable” is set in the macSpecialConfig, ensure that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold are set for flow control enabled case.

5. When “kENET_ControlStoreAndFwdDisabled” is set in the macSpecialConfig, ensure that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable.

6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator are disabled. The “enet_tx_accelerator_t” and “enet_rx_accelerator_t” are recommended to be used to enable the transmit and receive accelerator. After the accelerators are enabled, the store and forward feature should be enabled. As a result, kENET_ControlStoreAndFwdDisabled should not be set.

7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading.

typedef struct _enet_tx_bd_ring enet_tx_bd_ring_t

Defines the ENET transmit buffer descriptor ring/queue structure.

typedef struct _enet_rx_bd_ring enet_rx_bd_ring_t

Defines the ENET receive buffer descriptor ring/queue structure.

typedef struct _enet_buffer_struct enet_buffer_struct_t

typedef struct _enet_rx_frame_attribute_struct enet_rx_frame_attribute_t

typedef struct _enet_rx_frame_struct enet_rx_frame_struct_t

typedef struct _enet_tx_frame_struct enet_tx_frame_struct_t

typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle)

Define interrupt IRQ handler.

const clock_ip_name_t s_enetClock[]

Pointers to enet clocks for each instance.

const clock_ip_name_t s_enetExtraClock[]

uint32_t ENET_GetInstance(ENET_Type *base)

Get the ENET instance from peripheral base address.

Parameters:

• base – ENET peripheral base address.

Returns:

ENET instance.

ENET_BUFFDESCRIPTOR_RX_ERR_MASK

Defines the receive error status flag mask.

struct _enet_rx_bd_struct

#include <fsl_enet.h>

Defines the receive buffer descriptor structure for the little endian system.

Public Members

uint16_t length

Buffer descriptor data length.

uint16_t control

Buffer descriptor control and status.

uint32_t buffer

Data buffer pointer.

struct _enet_tx_bd_struct

#include <fsl_enet.h>

Defines the enhanced transmit buffer descriptor structure for the little endian system.

Public Members

uint16_t length

Buffer descriptor data length.

uint16_t control

Buffer descriptor control and status.

uint32_t buffer

Data buffer pointer.

struct _enet_data_error_stats

#include <fsl_enet.h>

Defines the ENET data error statistics structure.

Public Members

uint32_t statsRxLenGreaterErr

Receive length greater than RCR[MAX_FL].

uint32_t statsRxAlignErr

Receive non-octet alignment/

uint32_t statsRxFcsErr

Receive CRC error.

uint32_t statsRxOverRunErr

Receive over run.

uint32_t statsRxTruncateErr

Receive truncate.

struct _enet_rx_frame_error

#include <fsl_enet.h>

Defines the Rx frame error structure.

Public Members

bool statsRxTruncateErr

Receive truncate.

bool statsRxOverRunErr

Receive over run.

bool statsRxFcsErr

Receive CRC error.

bool statsRxAlignErr

Receive non-octet alignment.

bool statsRxLenGreaterErr

Receive length greater than RCR[MAX_FL].

struct _enet_transfer_stats

#include <fsl_enet.h>

Defines the ENET transfer statistics structure.

Public Members

uint32_t statsRxFrameCount

Rx frame number.

uint32_t statsRxFrameOk

Good Rx frame number.

uint32_t statsRxCrcErr

Rx frame number with CRC error.

uint32_t statsRxAlignErr

Rx frame number with alignment error.

uint32_t statsRxDropInvalidSFD

Dropped frame number due to invalid SFD.

uint32_t statsRxFifoOverflowErr

Rx FIFO overflow count.

uint32_t statsTxFrameCount

Tx frame number.

uint32_t statsTxFrameOk

Good Tx frame number.

uint32_t statsTxCrcAlignErr

The transmit frame is error.

uint32_t statsTxFifoUnderRunErr

Tx FIFO underrun count.

struct enet_frame_info

#include <fsl_enet.h>

Defines the frame info structure.

Public Members

void *context

User specified data

struct _enet_tx_dirty_ring

#include <fsl_enet.h>

Defines the ENET transmit dirty addresses ring/queue structure.

Public Members

enet_frame_info_t *txDirtyBase

Dirty buffer descriptor base address pointer.

uint16_t txGenIdx

tx generate index.

uint16_t txConsumIdx

tx consume index.

uint16_t txRingLen

tx ring length.

bool isFull

tx ring is full flag.

struct _enet_buffer_config

#include <fsl_enet.h>

Defines the receive buffer descriptor configuration structure.

Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.

1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

2. The aligned transmit and receive buffer descriptor start address must be at least 64 bit aligned. However, it’s recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. buffer descriptors should be put in non-cacheable region when cache is enabled.

3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. Receive buffers should be continuous with the total size equal to “rxBdNumber * rxBuffSizeAlign”. Transmit buffers should be continuous with the total size equal to “txBdNumber * txBuffSizeAlign”. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

Public Members

uint16_t rxBdNumber

Receive buffer descriptor number.

uint16_t txBdNumber

Transmit buffer descriptor number.

uint16_t rxBuffSizeAlign

Aligned receive data buffer size.

uint16_t txBuffSizeAlign

Aligned transmit data buffer size.

volatile enet_rx_bd_struct_t *rxBdStartAddrAlign

Aligned receive buffer descriptor start address: should be non-cacheable.

volatile enet_tx_bd_struct_t *txBdStartAddrAlign

Aligned transmit buffer descriptor start address: should be non-cacheable.

uint8_t *rxBufferAlign

Receive data buffer start address.

uint8_t *txBufferAlign

Transmit data buffer start address.

bool rxMaintainEnable

Receive buffer cache maintain.

bool txMaintainEnable

Transmit buffer cache maintain.

enet_frame_info_t *txFrameInfo

Transmit frame information start address.

struct _enet_intcoalesce_config

#include <fsl_enet.h>

Defines the interrupt coalescing configure structure.

Public Members

uint8_t txCoalesceFrameCount[1]

Transmit interrupt coalescing frame count threshold.

uint16_t txCoalesceTimeCount[1]

Transmit interrupt coalescing timer count threshold.

uint8_t rxCoalesceFrameCount[1]

Receive interrupt coalescing frame count threshold.

uint16_t rxCoalesceTimeCount[1]

Receive interrupt coalescing timer count threshold.

struct _enet_avb_config

#include <fsl_enet.h>

Defines the ENET AVB Configure structure.

This is used for to configure the extended ring 1 and ring 2.

1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel.

If CMP1,2,3 are not unused, please set them to the same value as CMP0.

1. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75.

Public Members

uint16_t rxClassifyMatch[1 - 1]

The classification match value for the ring.

enet_idle_slope_t idleSlope[1 - 1]

The idle slope for certian bandwidth fraction.

struct _enet_config

#include <fsl_enet.h>

Defines the basic configuration structure for the ENET device.

Note:

1. macSpecialConfig is used for a special control configuration, A logical OR of “enet_special_control_flag_t”. For a special configuration for MAC, set this parameter to 0.

2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 2 - 128 bytes written to TX FIFO …. 3 - 192 bytes written to TX FIFO …. The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO …. txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 or for larger bus access latency 3 or larger due to contention for the system bus.

3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. If the end of the frame is stored in FIFO and the frame size if smaller than the txWatermark, the frame is still transmitted. The rule is the same for rxFifoFullThreshold in the receive direction.

4. When “kENET_ControlFlowControlEnable” is set in the macSpecialConfig, ensure that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold are set for flow control enabled case.

5. When “kENET_ControlStoreAndFwdDisabled” is set in the macSpecialConfig, ensure that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable.

6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator are disabled. The “enet_tx_accelerator_t” and “enet_rx_accelerator_t” are recommended to be used to enable the transmit and receive accelerator. After the accelerators are enabled, the store and forward feature should be enabled. As a result, kENET_ControlStoreAndFwdDisabled should not be set.

7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading.

Public Members

uint32_t macSpecialConfig

Mac special configuration. A logical OR of “enet_special_control_flag_t”.

uint32_t interrupt

Mac interrupt source. A logical OR of “enet_interrupt_enable_t”.

uint16_t rxMaxFrameLen

Receive maximum frame length.

enet_mii_mode_t miiMode

MII mode.

enet_mii_speed_t miiSpeed

MII Speed.

enet_mii_duplex_t miiDuplex

MII duplex.

uint8_t rxAccelerConfig

Receive accelerator, A logical OR of “enet_rx_accelerator_t”.

uint8_t txAccelerConfig

Transmit accelerator, A logical OR of “enet_rx_accelerator_t”.

uint16_t pauseDuration

For flow control enabled case: Pause duration.

uint8_t rxFifoEmptyThreshold

For flow control enabled case: when RX FIFO level reaches this value, it makes MAC generate XOFF pause frame.

uint8_t rxFifoStatEmptyThreshold

For flow control enabled case: number of frames in the receive FIFO, independent of size, that can be accept. If the limit is reached, reception continues and a pause frame is triggered.

uint8_t rxFifoFullThreshold

For store and forward disable case, the data required in RX FIFO to notify the MAC receive ready status.

uint8_t txFifoWatermark

For store and forward disable case, the data required in TX FIFO before a frame transmit start.

enet_intcoalesce_config_t *intCoalesceCfg

If the interrupt coalsecence is not required in the ring n(0,1,2), please set to NULL.

uint8_t ringNum

Number of used rings. default with 1 &#8212; single ring.

enet_rx_alloc_callback_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx.

enet_rx_free_callback_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx.

enet_callback_t callback

General callback function.

void *userData

Callback function parameter.

struct _enet_tx_bd_ring

#include <fsl_enet.h>

Defines the ENET transmit buffer descriptor ring/queue structure.

Public Members

volatile enet_tx_bd_struct_t *txBdBase

Buffer descriptor base address pointer.

uint16_t txGenIdx

The current available transmit buffer descriptor pointer.

uint16_t txConsumIdx

Transmit consume index.

volatile uint16_t txDescUsed

Transmit descriptor used number.

uint16_t txRingLen

Transmit ring length.

struct _enet_rx_bd_ring

#include <fsl_enet.h>

Defines the ENET receive buffer descriptor ring/queue structure.

Public Members

volatile enet_rx_bd_struct_t *rxBdBase

Buffer descriptor base address pointer.

uint16_t rxGenIdx

The current available receive buffer descriptor pointer.

uint16_t rxRingLen

Receive ring length.

struct _enet_handle

#include <fsl_enet.h>

Defines the ENET handler structure.

Public Members

enet_rx_bd_ring_t rxBdRing[1]

Receive buffer descriptor.

enet_tx_bd_ring_t txBdRing[1]

Transmit buffer descriptor.

uint16_t rxBuffSizeAlign[1]

Receive buffer size alignment.

uint16_t txBuffSizeAlign[1]

Transmit buffer size alignment.

bool rxMaintainEnable[1]

Receive buffer cache maintain.

bool txMaintainEnable[1]

Transmit buffer cache maintain.

uint8_t ringNum

Number of used rings.

enet_callback_t callback

Callback function.

void *userData

Callback function parameter.

enet_tx_dirty_ring_t txDirtyRing[1]

Ring to store tx frame information.

bool txReclaimEnable[1]

Tx reclaim enable flag.

enet_rx_alloc_callback_t rxBuffAlloc

Callback function to alloc memory for zero copy Rx.

enet_rx_free_callback_t rxBuffFree

Callback function to free memory for zero copy Rx.

uint8_t multicastCount[64]

Multicast collisions counter

uint32_t enetClock

The clock of enet peripheral, to caculate core cycles for PTP timestamp.

uint32_t tsDelayCount

The count of core cycles for PTP timestamp capture delay.

struct _enet_buffer_struct

#include <fsl_enet.h>

Public Members

void *buffer

The buffer store the whole or partial frame.

uint16_t length

The byte length of this buffer.

struct _enet_rx_frame_attribute_struct

#include <fsl_enet.h>

Public Members

bool promiscuous

This frame is received because of promiscuous mode.

struct _enet_rx_frame_struct

#include <fsl_enet.h>

Public Members

enet_buffer_struct_t *rxBuffArray

Rx frame buffer structure.

uint16_t totLen

Rx frame total length.

enet_rx_frame_attribute_t rxAttribute

Rx frame attribute structure.

enet_rx_frame_error_t rxFrameError

Rx frame error.

struct _enet_tx_frame_struct

#include <fsl_enet.h>

Public Members

enet_buffer_struct_t *txBuffArray

Tx frame buffer structure.

uint32_t txBuffNum

Buffer number of this Tx frame.

void *context

Driver reclaims and gives it in Tx over callback, usually store network packet header.

EQOS-TSN: Ethernet QoS with TSN Driver

Enet_qos_qos

void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config)

Gets the ENET default configuration structure.

The purpose of this API is to get the default ENET configure structure for ENET_QOS_Init(). User may use the initialized structure unchanged in ENET_QOS_Init(), or modify some fields of the structure before calling ENET_QOS_Init(). Example:

enet_qos_config_t config;
ENET_QOS_GetDefaultConfig(&config);

Parameters:

• config – The ENET mac controller configuration structure pointer.

status_t ENET_QOS_Up(ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz)

Initializes the ENET module.

This function initializes it with the ENET basic configuration.

Parameters:

• base – ENET peripheral base address.

• config – ENET mac configuration structure pointer. The “enet_qos_config_t” type mac configuration return from ENET_QOS_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.

• macAddr – Pointer to ENET mac address array of Ethernet device. This MAC address should be provided.

• macCount – Count of macAddr in the ENET mac address array

• refclkSrc_Hz – ENET input reference clock.

status_t ENET_QOS_Init(ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz)

Initializes the ENET module.

This function ungates the module clock and initializes it with the ENET basic configuration.

Parameters:

• base – ENET peripheral base address.

• config – ENET mac configuration structure pointer. The “enet_qos_config_t” type mac configuration return from ENET_QOS_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.

• macAddr – Pointer to ENET mac address array of Ethernet device. This MAC address should be provided.

• macCount – Count of macAddr in the ENET mac address array

• refclkSrc_Hz – ENET input reference clock.

void ENET_QOS_Down(ENET_QOS_Type *base)

Stops the ENET module.

This function disables the ENET module.

Parameters:

• base – ENET peripheral base address.

void ENET_QOS_Deinit(ENET_QOS_Type *base)

Deinitializes the ENET module.

This function gates the module clock and disables the ENET module.

Parameters:

• base – ENET peripheral base address.

uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base)

Get the ENET instance from peripheral base address.

Parameters:

• base – ENET peripheral base address.

Returns:

ENET instance.

status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base, enet_qos_config_t *config, enet_qos_buffer_config_t *bufferConfig)

Initialize for all ENET descriptors.

Note

This function is do all tx/rx descriptors initialization. Because this API read all interrupt registers first and then set the interrupt flag for all descriptors, if the interrupt register is set. so the descriptor initialization should be called after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs are used).

Parameters:

• base – ENET peripheral base address.

• config – The configuration for ENET.

• bufferConfig – All buffers configuration.

status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle)

Allocates Rx buffers for all BDs. It’s used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken by application application should free those buffers after they’re used.

Note

This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback function should be ready.

Parameters:

• base – ENET_QOS peripheral base address.

• handle – The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.

void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle)

Frees Rx buffers in all BDs. It’s used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function will free left buffers in all BDs.

Parameters:

• base – ENET_QOS peripheral base address.

• handle – The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.

void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum)

Starts the ENET rx/tx. This function enable the tx/rx and starts the rx/tx DMA. This shall be set after ENET initialization and before starting to receive the data.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

• base – ENET peripheral base address.

• rxRingNum – The number of the used rx rings. It shall not be larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with 1, the ring 0 will be used.

• txRingNum – The number of the used tx rings. It shall not be larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with 1, the ring 0 will be used.

status_t ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex)

Sets the ENET MII speed and duplex.

This API is provided to dynamically change the speed and duplex for MAC.

Parameters:

• base – ENET peripheral base address.

• speed – The speed of the RMII mode.

• duplex – The duplex of the RMII mode.

Returns:

kStatus_Success The ENET MII speed and duplex has been set successfully.

Returns:

kStatus_InvalidArgument Could not set the desired ENET MII speed and duplex combination.

void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz)

Sets the ENET SMI(serial management interface)- MII management interface.

Parameters:

• base – ENET peripheral base address.

• csrClock_Hz – CSR clock frequency in HZ

static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)

Checks if the SMI is busy.

Parameters:

• base – ENET peripheral base address.

Returns:

The status of MII Busy status.

static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)

Reads data from the PHY register through SMI interface.

Parameters:

• base – ENET peripheral base address.

Returns:

The data read from PHY

void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 22 format write command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address.

• regAddr – The PHY register address.

• data – The data written to PHY.

void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr)

Sends the MDIO IEEE802.3 Clause 22 format read command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address.

• regAddr – The PHY register address.

void ENET_QOS_StartExtC45SMIWrite(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 45 format write command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

• data – The data written to PHY.

void ENET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)

Sends the MDIO IEEE802.3 Clause 45 format read command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

MDIO write with IEEE802.3 MDIO Clause 22 format.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address.

• regAddr – The PHY register.

• data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 MDIO Clause 22 format.

Parameters:

• base – ENET peripheral base address.

• phyAddr – The PHY address.

• regAddr – The PHY register.

• pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIOC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 45 format.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

• data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIOC45Read(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 45 format.

Parameters:

• base – ENET peripheral base address.

• portAddr – The MDIO port address(PHY address).

• devAddr – The device address.

• regAddr – The PHY register address.

• pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_QOS_SetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)

Sets the ENET module Mac address.

Parameters:

• base – ENET peripheral base address.

• macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

• index – Configure macAddr to MAC_ADDRESS[index] register.

void ENET_QOS_GetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)

Gets the ENET module Mac address.

Parameters:

• base – ENET peripheral base address.

• macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

• index – Get macAddr from MAC_ADDRESS[index] register.

void ENET_QOS_AddMulticastGroup(ENET_QOS_Type *base, uint8_t *address)

Adds the ENET_QOS device to a multicast group.

Parameters:

• base – ENET_QOS peripheral base address.

• address – The six-byte multicast group address which is provided by application.

void ENET_QOS_LeaveMulticastGroup(ENET_QOS_Type *base, uint8_t *address)

Moves the ENET_QOS device from a multicast group.

Parameters:

• base – ENET_QOS peripheral base address.

• address – The six-byte multicast group address which is provided by application.

static inline void ENET_QOS_AcceptAllMulticast(ENET_QOS_Type *base)

Enable ENET device to accept all multicast frames.

Parameters:

• base – ENET peripheral base address.

static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base)

ENET device reject to accept all multicast frames.

Parameters:

• base – ENET peripheral base address.

void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter)

Set the MAC to enter into power down mode. the remote power wake up frame and magic frame can wake up the ENET from the power down mode.

Parameters:

• base – ENET peripheral base address.

• wakeFilter – The wakeFilter provided to configure the wake up frame filter. Set the wakeFilter to NULL is not required. But if you have the filter requirement, please make sure the wakeFilter pointer shall be eight continuous 32-bits configuration.

static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base)

Set the MAC to exit power down mode. Exit from the power down mode and recover to normal work mode.

Parameters:

• base – ENET peripheral base address.

status_t ENET_QOS_EnableRxParser(ENET_QOS_Type *base, bool enable)

Enable/Disable Rx parser,please notice that for enable/disable Rx Parser, should better disable Receive first.

Parameters:

• base – ENET_QOS peripheral base address.

• enable – Enable/Disable Rx parser function

Return values:

• kStatus_Success – Configure rx parser success.

• kStatus_ENET_QOS_Timeout – Poll status flag timeout.

void ENET_QOS_EnableInterrupts(ENET_QOS_Type *base, uint32_t mask)

Enables the ENET DMA and MAC interrupts.

This function enables the ENET interrupt according to the provided mask. The mask is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t. For example, to enable the dma and mac interrupt, do the following.

ENET_QOS_EnableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupts to enable. This is a logical OR of both enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.

void ENET_QOS_DisableInterrupts(ENET_QOS_Type *base, uint32_t mask)

Disables the ENET DMA and MAC interrupts.

This function disables the ENET interrupt according to the provided mask. The mask is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t. For example, to disable the dma and mac interrupt, do the following.

ENET_QOS_DisableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupts to disables. This is a logical OR of both enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.

static inline uint32_t ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel)

Gets the ENET DMA interrupt status flag.

Parameters:

• base – ENET peripheral base address.

• channel – The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.

Returns:

The event status of the interrupt source. This is the logical OR of members of the enumeration :: enet_qos_dma_interrupt_enable_t.

static inline void ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel, uint32_t mask)

Clear the ENET DMA interrupt status flag.

Parameters:

• base – ENET peripheral base address.

• channel – The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.

• mask – The interrupt status to be cleared. This is the logical OR of members of the enumeration :: enet_qos_dma_interrupt_enable_t.

static inline uint32_t ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type *base)

Gets the ENET MAC interrupt status flag.

Parameters:

• base – ENET peripheral base address.

Returns:

The event status of the interrupt source. Use the enum in enet_qos_mac_interrupt_enable_t and right shift ENET_QOS_MACINT_ENUM_OFFSET to mask the returned value to get the exact interrupt status.

void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask)

Clears the ENET mac interrupt events status flag.

This function clears enabled ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See the enet_qos_mac_interrupt_enable_t. For example, to clear the TX frame interrupt and RX frame interrupt, do the following.

ENET_QOS_ClearMacInterruptStatus(ENET, kENET_QOS_MacPmt);

Parameters:

• base – ENET peripheral base address.

• mask – ENET interrupt source to be cleared. This is the logical OR of members of the enumeration :: enet_qos_mac_interrupt_enable_t.

static inline bool ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t *txDesc)

Get the tx descriptor DMA Own flag.

Parameters:

• txDesc – The given tx descriptor.

Return values:

True – the dma own tx descriptor, false application own tx descriptor.

void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc, void *buffer1, uint32_t bytes1, void *buffer2, uint32_t bytes2, uint32_t framelen, bool intEnable, bool tsEnable, enet_qos_desc_flag flag, uint8_t slotNum)

Setup a given tx descriptor. This function is a low level functional API to setup or prepare a given tx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required. Transmit buffers are ‘zero-copy’ buffers, so the buffer must remain in memory until the packet has been fully transmitted. The buffers should be free or requeued in the transmit interrupt irq handler.

Parameters:

• txDesc – The given tx descriptor.

• buffer1 – The first buffer address in the descriptor.

• bytes1 – The bytes in the fist buffer.

• buffer2 – The second buffer address in the descriptor.

• bytes2 – The bytes in the second buffer.

• framelen – The length of the frame to be transmitted.

• intEnable – Interrupt enable flag.

• tsEnable – The timestamp enable.

• flag – The flag of this tx descriptor, enet_qos_desc_flag .

• slotNum – The slot num used for AV only.

static inline void ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)

Update the tx descriptor tail pointer. This function is a low level functional API to update the the tx descriptor tail. This is called after you setup a new tx descriptor to update the tail pointer to make the new descriptor accessible by DMA.

Parameters:

• base – ENET peripheral base address.

• channel – The tx DMA channel.

• txDescTailAddrAlign – The new tx tail pointer address.

static inline void ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)

Update the rx descriptor tail pointer. This function is a low level functional API to update the the rx descriptor tail. This is called after you setup a new rx descriptor to update the tail pointer to make the new descriptor accessible by DMA and to anouse the rx poll command for DMA.

Parameters:

• base – ENET peripheral base address.

• channel – The rx DMA channel.

• rxDescTailAddrAlign – The new rx tail pointer address.

static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc)

Gets the context in the ENET rx descriptor. This function is a low level functional API to get the the status flag from a given rx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

• rxDesc – The given rx descriptor.

Return values:

The – RDES3 regions for write-back format rx buffer descriptor.

void ENET_QOS_UpdateRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable)

Updates the buffers and the own status for a given rx descriptor. This function is a low level functional API to Updates the buffers and the own status for a given rx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

• rxDesc – The given rx descriptor.

• buffer1 – The first buffer address in the descriptor.

• buffer2 – The second buffer address in the descriptor.

• intEnable – Interrupt enable flag.

• doubleBuffEnable – The double buffer enable flag.

status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount)

Configure flexible rx parser.

This function is used to configure the flexible rx parser table.

Parameters:

• base – ENET peripheral base address..

• rxpConfig – The rx parser configuration pointer.

• entryCount – The rx parser entry count.

Return values:

• kStatus_Success – Configure rx parser success.

• kStatus_ENET_QOS_Timeout – Poll status flag timeout.

status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryIndex)

Read flexible rx parser configuration at specified index.

This function is used to read flexible rx parser configuration at specified index.

Parameters:

• base – ENET peripheral base address..

• rxpConfig – The rx parser configuration pointer.

• entryIndex – The rx parser entry index to read, start from 0.

Return values:

• kStatus_Success – Configure rx parser success.

• kStatus_ENET_QOS_Timeout – Poll status flag timeout.

status_t ENET_QOS_EstProgramGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t ptpClk_Hz)

Program Gate Control List.

This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

• base – ENET peripheral base address..

• gcl – Pointer to the Gate Control List structure.

• ptpClk_Hz – frequency of the PTP clock.

status_t ENET_QOS_EstReadGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t listLen, bool hwList)

Read Gate Control List.

This function is used to read the Enhanced Scheduled Transmisson list. (IEEE802.1Qbv)

Parameters:

• base – ENET peripheral base address..

• gcl – Pointer to the Gate Control List structure.

• listLen – length of the provided opList array in gcl structure.

• hwList – Boolean if True read HW list, false read SW list.

static inline void ENET_QOS_FpeEnable(ENET_QOS_Type *base)

Enable Frame Preemption.

This function is used to enable frame preemption. (IEEE802.1Qbu)

Parameters:

• base – ENET peripheral base address..

static inline void ENET_QOS_FpeDisable(ENET_QOS_Type *base)

Disable Frame Preemption.

This function is used to disable frame preemption. (IEEE802.1Qbu)

Parameters:

• base – ENET peripheral base address..

static inline void ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type *base, uint8_t queueMask)

Configure preemptable transmit queues.

This function is used to configure the preemptable queues. (IEEE802.1Qbu)

Parameters:

• base – ENET peripheral base address..

• queueMask – bitmask representing queues to set in preemptable mode. The N-th bit represents the queue N.

void ENET_QOS_AVBConfigure(ENET_QOS_Type *base, const enet_qos_cbs_config_t *config, uint8_t queueIndex)

Sets the ENET AVB feature.

ENET_QOS AVB feature configuration, set transmit bandwidth. This API is called when the AVB feature is required.

Parameters:

• base – ENET_QOS peripheral base address.

• config – The ENET_QOS AVB feature configuration structure.

• queueIndex – ENET_QOS queue index.

void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *statistics)

Gets statistical data in transfer.

Parameters:

• base – ENET_QOS peripheral base address.

• statistics – The statistics structure pointer.

void ENET_QOS_CreateHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_config_t *config, enet_qos_buffer_config_t *bufferConfig, enet_qos_callback_t callback, void *userData)

Create ENET Handler.

This is a transactional API and it’s provided to store all data which are needed during the whole transactional process. This API should not be used when you use functional APIs to do data tx/rx. This is function will store many data/flag for transactional use, so all configure API such as ENET_QOS_Init(), ENET_QOS_DescriptorInit(), ENET_QOS_EnableInterrupts() etc.

Note

as our transactional transmit API use the zero-copy transmit buffer. so there are two thing we emphasize here:

1. tx buffer free/requeue for application should be done in the tx interrupt handler. Please set callback: kENET_QOS_TxIntEvent with tx buffer free/requeue process APIs.

2. the tx interrupt is forced to open.

Parameters:

• base – ENET peripheral base address.

• handle – ENET handler.

• config – ENET configuration.

• bufferConfig – ENET buffer configuration.

• callback – The callback function.

• userData – The application data.

status_t ENET_QOS_GetRxFrameSize(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint32_t *length, uint8_t channel)

Gets the size of the read frame. This function gets a received frame size from the ENET buffer descriptors.

Note

The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. After calling ENET_QOS_GetRxFrameSize, ENET_QOS_ReadFrame() should be called to update the receive buffers If the result is not “kStatus_ENET_QOS_RxFrameEmpty”.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.

• length – The length of the valid frame received.

• channel – The DMAC channel for the rx.

Return values:

• kStatus_ENET_QOS_RxFrameEmpty – No frame received. Should not call ENET_QOS_ReadFrame to read frame.

• kStatus_ENET_QOS_RxFrameError – Data error happens. ENET_QOS_ReadFrame should be called with NULL data and NULL length to update the receive buffers.

• kStatus_Success – Receive a frame Successfully then the ENET_QOS_ReadFrame should be called with the right data buffer and the captured data length input.

status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel, enet_qos_ptp_time_t *ts)

Reads a frame from the ENET device. This function reads a frame from the ENET DMA descriptors. The ENET_QOS_GetRxFrameSize should be used to get the size of the prepared data buffer. For example use rx dma channel 0:

uint32_t length;
enet_qos_handle_t g_handle;
status = ENET_QOS_GetRxFrameSize(&g_handle, &length, 0);
if (length != 0)
{
    uint8_t *data = memory allocate interface;
    if (!data)
    {
        ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
    }
    else
    {
       status = ENET_QOS_ReadFrame(ENET, &g_handle, data, length, 0);
    }
}
else if (status == kStatus_ENET_QOS_RxFrameError)
{
    ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
}

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.

• data – The data buffer provided by user to store the frame which memory size should be at least “length”.

• length – The size of the data buffer which is still the length of the received frame.

• channel – The rx DMA channel. shall not be larger than 2.

• ts – Pointer to the structure enet_qos_ptp_time_t to save frame timestamp.

Returns:

The execute status, successful or failure.

status_t ENET_QOS_SendFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel, bool isNeedTs, void *context, enet_qos_tx_offload_t txOffloadOps)

Transmits an ENET frame.

Note

The CRC is automatically appended to the data. Input the data to send without the CRC.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.

• data – The data buffer provided by user to be send.

• length – The length of the data to be send.

• channel – Channel to send the frame, same with queue index.

• isNeedTs – True to enable timestamp save for the frame

• context – pointer to user context to be kept in the tx dirty frame information.

• txOffloadOps – The Tx frame checksum offload option.

Return values:

• kStatus_Success – Send frame succeed.

• kStatus_ENET_QOS_TxFrameBusy – Transmit buffer descriptor is busy under transmission. The transmit busy happens when the data send rate is over the MAC capacity. The waiting mechanism is recommended to be added after each call return with kStatus_ENET_QOS_TxFrameBusy.

void ENET_QOS_ReclaimTxDescriptor(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t channel)

Reclaim tx descriptors. This function is used to update the tx descriptor status and store the tx timestamp when the 1588 feature is enabled. This is called by the transmit interrupt IRQ handler after the complete of a frame transmission.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.

• channel – The tx DMA channel.

void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle)

The ENET IRQ handler.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer.

void ENET_QOS_SetISRHandler(ENET_QOS_Type *base, enet_qos_isr_t ISRHandler)

Set the second level IRQ handler, allow user to overwrite the default second level weak IRQ handler.

Parameters:

• base – ENET peripheral base address.

• ISRHandler – The handler to install.

status_t ENET_QOS_Ptp1588CorrectTimerInCoarse(ENET_QOS_Type *base, enet_qos_systime_op operation, uint32_t second, uint32_t nanosecond)

Correct the ENET PTP 1588 timer in coarse method.

Parameters:

• base – ENET peripheral base address.

• operation – The system time operation, refer to “enet_qos_systime_op”

• second – The correction second.

• nanosecond – The correction nanosecond.

status_t ENET_QOS_Ptp1588CorrectTimerInFine(ENET_QOS_Type *base, uint32_t addend)

Correct the ENET PTP 1588 timer in fine method.

Note

Should take refer to the chapter “System time correction” and see the description for the “fine correction method”.

Parameters:

• base – ENET peripheral base address.

• addend – The addend value to be set in the fine method

static inline uint32_t ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type *base)

Get the ENET Time stamp current addend value.

Parameters:

• base – ENET peripheral base address.

Returns:

The addend value.

void ENET_QOS_Ptp1588GetTimerNoIRQDisable(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond)

Gets the current ENET time from the PTP 1588 timer without IRQ disable.

Parameters:

• base – ENET peripheral base address.

• second – The PTP 1588 system timer second.

• nanosecond – The PTP 1588 system timer nanosecond. For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.

static inline status_t ENET_Ptp1588PpsControl(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, enet_qos_ptp_pps_trgt_mode_t trgtMode, enet_qos_ptp_pps_cmd_t cmd)

Sets the ENET PTP 1588 PPS control. All channels operate in flexible PPS output mode.

Parameters:

• base – ENET peripheral base address.

• instance – The ENET QOS PTP PPS instance.

• trgtMode – The target time register mode.

• cmd – The target flexible PPS output control command.

status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t seconds, uint32_t nanoseconds)

Sets the ENET OQS PTP 1588 PPS target time registers.

Parameters:

• base – ENET QOS peripheral base address.

• instance – The ENET QOS PTP PPS instance.

• seconds – The target seconds.

• nanoseconds – The target nanoseconds.

static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t width)

Sets the ENET OQS PTP 1588 PPS output signal interval.

Parameters:

• base – ENET QOS peripheral base address.

• instance – The ENET QOS PTP PPS instance.

• width – Signal Width. It is stored in terms of number of units of sub-second increment value. The width value must be lesser than interval value.

static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t interval)

Sets the ENET OQS PTP 1588 PPS output signal width.

Parameters:

• base – ENET QOS peripheral base address.

• instance – The ENET QOS PTP PPS instance.

• interval – Signal Interval. It is stored in terms of number of units of sub-second increment value.

void ENET_QOS_Ptp1588GetTimer(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond)

Gets the current ENET time from the PTP 1588 timer.

Parameters:

• base – ENET peripheral base address.

• second – The PTP 1588 system timer second.

• nanosecond – The PTP 1588 system timer nanosecond. For the unit of the nanosecond is 1ns.so the nanosecond is the real nanosecond.

void ENET_QOS_GetTxFrame(enet_qos_handle_t *handle, enet_qos_frame_info_t *txFrame, uint8_t channel)

Gets the time stamp of the transmit frame.

This function is used for PTP stack to get the timestamp captured by the ENET driver.

Parameters:

• handle – The ENET handler pointer.This is the same state pointer used in ENET_QOS_Init.

• txFrame – Input parameter, pointer to enet_qos_frame_info_t for saving read out frame information.

• channel – Channel for searching the tx frame.

status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_rx_frame_struct_t *rxFrame, uint8_t channel)

Receives one frame in specified BD ring with zero copy.

This function will use the user-defined allocate and free callback. Every time application gets one frame through this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.

Note

This function will drop current frame and update related BDs as available for DMA if new buffers allocating fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer) to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there’s always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according to specific design in this case.

Parameters:

• base – ENET peripheral base address.

• handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.

• rxFrame – The received frame information structure provided by user.

• channel – Channel for searching the rx frame.

Return values:

• kStatus_Success – Succeed to get one frame and allocate new memory for Rx buffer.

• kStatus_ENET_QOS_RxFrameEmpty – There’s no Rx frame in the BD.

• kStatus_ENET_QOS_RxFrameError – There’s issue in this receiving.

• kStatus_ENET_QOS_RxFrameDrop – There’s no new buffer memory for BD, drop this frame.

FSL_ENET_QOS_DRIVER_VERSION

Defines the driver version.

ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK

Defines for read format.

Buffer1 address valid.

ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK

Buffer2 address valid.

ENET_QOS_RXDESCRIP_RD_IOC_MASK

Interrupt enable on complete.

ENET_QOS_RXDESCRIP_RD_OWN_MASK

Own bit.

ENET_QOS_RXDESCRIP_WR_ERR_MASK

Defines for write back format.

ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK

ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK

ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK

ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK

ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK

ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK

ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK

ENET_QOS_RXDESCRIP_WR_TYPE_MASK

ENET_QOS_RXDESCRIP_WR_DE_MASK

ENET_QOS_RXDESCRIP_WR_RE_MASK

ENET_QOS_RXDESCRIP_WR_OE_MASK

ENET_QOS_RXDESCRIP_WR_RWT_MASK

ENET_QOS_RXDESCRIP_WR_GP_MASK

ENET_QOS_RXDESCRIP_WR_CRC_MASK

ENET_QOS_RXDESCRIP_WR_RS0V_MASK

ENET_QOS_RXDESCRIP_WR_RS1V_MASK

ENET_QOS_RXDESCRIP_WR_RS2V_MASK

ENET_QOS_RXDESCRIP_WR_LD_MASK

ENET_QOS_RXDESCRIP_WR_FD_MASK

ENET_QOS_RXDESCRIP_WR_CTXT_MASK

ENET_QOS_RXDESCRIP_WR_OWN_MASK

ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK

ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK

ENET_QOS_TXDESCRIP_RD_BL1_MASK

Defines for read format.

ENET_QOS_TXDESCRIP_RD_BL2_MASK

ENET_QOS_TXDESCRIP_RD_BL1(n)

ENET_QOS_TXDESCRIP_RD_BL2(n)

ENET_QOS_TXDESCRIP_RD_TTSE_MASK

ENET_QOS_TXDESCRIP_RD_IOC_MASK

ENET_QOS_TXDESCRIP_RD_FL_MASK

ENET_QOS_TXDESCRIP_RD_FL(n)

ENET_QOS_TXDESCRIP_RD_CIC(n)

ENET_QOS_TXDESCRIP_RD_TSE_MASK

ENET_QOS_TXDESCRIP_RD_SLOT(n)

ENET_QOS_TXDESCRIP_RD_SAIC(n)

ENET_QOS_TXDESCRIP_RD_CPC(n)

ENET_QOS_TXDESCRIP_RD_LDFD(n)

ENET_QOS_TXDESCRIP_RD_LD_MASK

ENET_QOS_TXDESCRIP_RD_FD_MASK

ENET_QOS_TXDESCRIP_RD_CTXT_MASK

ENET_QOS_TXDESCRIP_RD_OWN_MASK

ENET_QOS_TXDESCRIP_WB_TTSS_MASK

Defines for write back format.

ENET_QOS_ABNORM_INT_MASK

ENET_QOS_NORM_INT_MASK

ENET_QOS_RING_NUM_MAX

The Maximum number of tx/rx descriptor rings.

ENET_QOS_FRAME_MAX_FRAMELEN

Default maximum Ethernet frame size.

ENET_QOS_FCS_LEN

Ethernet FCS length.

ENET_QOS_ADDR_ALIGNMENT

Recommended Ethernet buffer alignment.

ENET_QOS_BUFF_ALIGNMENT

Receive buffer alignment shall be 4bytes-aligned.

ENET_QOS_MTL_RXFIFOSIZE

The rx fifo size.

ENET_QOS_MTL_TXFIFOSIZE

The tx fifo size.

ENET_QOS_MACINT_ENUM_OFFSET

The offest for mac interrupt in enum type.

ENET_QOS_RXP_ENTRY_COUNT

RXP table entry count, implied by FRPES in MAC_HW_FEATURE3

ENET_QOS_RXP_BUFFER_SIZE

RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3

ENET_QOS_EST_WID

Width of the time interval in Gate Control List

ENET_QOS_EST_DEP

Maxmimum depth of Gate Control List

Defines the status return codes for transaction.

Values:

enumerator kStatus_ENET_QOS_InitMemoryFail

Init fails since buffer memory is not enough.

enumerator kStatus_ENET_QOS_RxFrameError

A frame received but data error happen.

enumerator kStatus_ENET_QOS_RxFrameFail

Failed to receive a frame.

enumerator kStatus_ENET_QOS_RxFrameEmpty

No frame arrive.

enumerator kStatus_ENET_QOS_RxFrameDrop

Rx frame is dropped since no buffer memory.

enumerator kStatus_ENET_QOS_TxFrameBusy

Transmit descriptors are under process.

enumerator kStatus_ENET_QOS_TxFrameFail

Transmit frame fail.

enumerator kStatus_ENET_QOS_TxFrameOverLen

Transmit oversize.

enumerator kStatus_ENET_QOS_Est_SwListBusy

SW Gcl List not yet processed by HW.

enumerator kStatus_ENET_QOS_Est_SwListWriteAbort

SW Gcl List write aborted .

enumerator kStatus_ENET_QOS_Est_InvalidParameter

Invalid parameter in Gcl List .

enumerator kStatus_ENET_QOS_Est_BtrError

Base Time Error when loading list.

enumerator kStatus_ENET_QOS_TrgtBusy

Target time register busy.

enumerator kStatus_ENET_QOS_Timeout

Target time register busy.

enumerator kStatus_ENET_QOS_PpsBusy

Pps command busy.

enum _enet_qos_mii_mode

Defines the MII/RGMII mode for data interface between the MAC and the PHY.

Values:

enumerator kENET_QOS_MiiMode

MII mode for data interface.

enumerator kENET_QOS_RgmiiMode

RGMII mode for data interface.

enumerator kENET_QOS_RmiiMode

RMII mode for data interface.

enum _enet_qos_mii_speed

Defines the 10/100/1000 Mbps speed for the MII data interface.

Values:

enumerator kENET_QOS_MiiSpeed10M

Speed 10 Mbps.

enumerator kENET_QOS_MiiSpeed100M

Speed 100 Mbps.

enumerator kENET_QOS_MiiSpeed1000M

Speed 1000 Mbps.

enumerator kENET_QOS_MiiSpeed2500M

Speed 2500 Mbps.

enum _enet_qos_mii_duplex

Defines the half or full duplex for the MII data interface.

Values:

enumerator kENET_QOS_MiiHalfDuplex

Half duplex mode.

enumerator kENET_QOS_MiiFullDuplex

Full duplex mode.

enum _enet_qos_mii_normal_opcode

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

Values:

enumerator kENET_QOS_MiiWriteFrame

Write frame operation for a valid MII management frame.

enumerator kENET_QOS_MiiReadFrame

Read frame operation for a valid MII management frame.

enum _enet_qos_dma_burstlen

Define the DMA maximum transmit burst length.

Values:

enumerator kENET_QOS_BurstLen1

DMA burst length 1.

enumerator kENET_QOS_BurstLen2

DMA burst length 2.

enumerator kENET_QOS_BurstLen4

DMA burst length 4.

enumerator kENET_QOS_BurstLen8

DMA burst length 8.

enumerator kENET_QOS_BurstLen16

DMA burst length 16.

enumerator kENET_QOS_BurstLen32

DMA burst length 32.

enumerator kENET_QOS_BurstLen64

DMA burst length 64. eight times enabled.

enumerator kENET_QOS_BurstLen128

DMA burst length 128. eight times enabled.

enumerator kENET_QOS_BurstLen256

DMA burst length 256. eight times enabled.

enum _enet_qos_desc_flag

Define the flag for the descriptor.

Values:

enumerator kENET_QOS_MiddleFlag

It’s a middle descriptor of the frame.

enumerator kENET_QOS_LastFlagOnly

It’s the last descriptor of the frame.

enumerator kENET_QOS_FirstFlagOnly

It’s the first descriptor of the frame.

enumerator kENET_QOS_FirstLastFlag

It’s the first and last descriptor of the frame.

enum _enet_qos_systime_op

Define the system time adjust operation control.

Values:

enumerator kENET_QOS_SystimeAdd

System time add to.

enumerator kENET_QOS_SystimeSubtract

System time subtract.

enum _enet_qos_ts_rollover_type

Define the system time rollover control.

Values:

enumerator kENET_QOS_BinaryRollover

System time binary rollover.

enumerator kENET_QOS_DigitalRollover

System time digital rollover.

enum _enet_qos_special_config

Defines some special configuration for ENET.

These control flags are provided for special user requirements. Normally, these is no need to set this control flags for ENET initialization. But if you have some special requirements, set the flags to specialControl in the enet_qos_config_t.

Note

“kENET_QOS_StoreAndForward” is recommended to be set.

Values:

enumerator kENET_QOS_DescDoubleBuffer

The double buffer is used in the tx/rx descriptor.

enumerator kENET_QOS_StoreAndForward

The rx/tx store and forward enable.

enumerator kENET_QOS_PromiscuousEnable

The promiscuous enabled.

enumerator kENET_QOS_FlowControlEnable

The flow control enabled.

enumerator kENET_QOS_BroadCastRxDisable

The broadcast disabled.

enumerator kENET_QOS_MulticastAllEnable

All multicast are passed.

enumerator kENET_QOS_8023AS2KPacket

8023as support for 2K packets.

enumerator kENET_QOS_HashMulticastEnable

The multicast packets are filtered through hash table.

enumerator kENET_QOS_RxChecksumOffloadEnable

The Rx checksum offload enabled.

enum _enet_qos_dma_interrupt_enable

List of DMA interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

Values:

enumerator kENET_QOS_DmaTx

Tx interrupt.

enumerator kENET_QOS_DmaTxStop

Tx stop interrupt.

enumerator kENET_QOS_DmaTxBuffUnavail

Tx buffer unavailable.

enumerator kENET_QOS_DmaRx

Rx interrupt.

enumerator kENET_QOS_DmaRxBuffUnavail

Rx buffer unavailable.

enumerator kENET_QOS_DmaRxStop

Rx stop.

enumerator kENET_QOS_DmaRxWatchdogTimeout

Rx watchdog timeout.

enumerator kENET_QOS_DmaEarlyTx

Early transmit.

enumerator kENET_QOS_DmaEarlyRx

Early receive.

enumerator kENET_QOS_DmaBusErr

Fatal bus error.

enum _enet_qos_mac_interrupt_enable

List of mac interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

Values:

enumerator kENET_QOS_MacPmt

enumerator kENET_QOS_MacTimestamp

enum _enet_qos_event

Defines the common interrupt event for callback use.

Values:

enumerator kENET_QOS_RxIntEvent

Receive interrupt event.

enumerator kENET_QOS_TxIntEvent

Transmit interrupt event.

enumerator kENET_QOS_WakeUpIntEvent

Wake up interrupt event.

enumerator kENET_QOS_TimeStampIntEvent

Time stamp interrupt event.

enum _enet_qos_queue_mode

Define the MTL mode for multiple queues/rings.

Values:

enumerator kENET_QOS_AVB_Mode

Enable queue in AVB mode.

enumerator kENET_QOS_DCB_Mode

Enable queue in DCB mode.

enum _enet_qos_mtl_multiqueue_txsche

Define the MTL tx scheduling algorithm for multiple queues/rings.

Values:

enumerator kENET_QOS_txWeightRR

Tx weight round-robin.

enumerator kENET_QOS_txWeightFQ

Tx weight fair queuing.

enumerator kENET_QOS_txDefictWeightRR

Tx deficit weighted round-robin.

enumerator kENET_QOS_txStrPrio

Tx strict priority.

enum _enet_qos_mtl_multiqueue_rxsche

Define the MTL rx scheduling algorithm for multiple queues/rings.

Values:

enumerator kENET_QOS_rxStrPrio

Rx strict priority, Queue 0 has the lowest priority.

enumerator kENET_QOS_rxWeightStrPrio

Weighted Strict Priority.

enum _enet_qos_mtl_rxqueuemap

Define the MTL rx queue and DMA channel mapping.

Values:

enumerator kENET_QOS_StaticDirctMap

The received fame in rx Qn(n = 0,1) directly map to dma channel n.

enumerator kENET_QOS_DynamicMap

The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.

enum _enet_qos_rx_queue_route

Defines the package type for receive queue routing.

Values:

enumerator kENET_QOS_PacketNoQ

enumerator kENET_QOS_PacketAVCPQ

enumerator kENET_QOS_PacketPTPQ

enumerator kENET_QOS_PacketDCBCPQ

enumerator kENET_QOS_PacketUPQ

enumerator kENET_QOS_PacketMCBCQ

enum _enet_qos_ptp_event_type

Defines the ENET PTP message related constant.

Values:

enumerator kENET_QOS_PtpEventMsgType

PTP event message type.

enumerator kENET_QOS_PtpSrcPortIdLen

PTP message sequence id length.

enumerator kENET_QOS_PtpEventPort

PTP event port number.

enumerator kENET_QOS_PtpGnrlPort

PTP general port number.

enum _enet_qos_ptp_pps_instance

Defines the PPS instance numbers.

Values:

enumerator kENET_QOS_PtpPpsIstance0

PPS instance 0.

enumerator kENET_QOS_PtpPpsIstance1

PPS instance 1.

enumerator kENET_QOS_PtpPpsIstance2

PPS instance 2.

enumerator kENET_QOS_PtpPpsIstance3

PPS instance 3.

enum _enet_qos_ptp_pps_trgt_mode

Defines the Target Time register mode.

Values:

enumerator kENET_QOS_PtpPpsTrgtModeOnlyInt

Only interrupts.

enumerator kENET_QOS_PtpPpsTrgtModeIntSt

Both interrupt and output signal.

enumerator kENET_QOS_PtpPpsTrgtModeOnlySt

Only output signal.

enum _enet_qos_ptp_pps_cmd

Defines commands for ppscmd register.

Values:

enumerator kENET_QOS_PtpPpsCmdNC

No Command.

enumerator kENET_QOS_PtpPpsCmdSSP

Start Single Pulse.

enumerator kENET_QOS_PtpPpsCmdSPT

Start Pulse Train.

enumerator kENET_QOS_PtpPpsCmdCS

Cancel Start.

enumerator kENET_QOS_PtpPpsCmdSPTAT

Stop Pulse Train At Time.

enumerator kENET_QOS_PtpPpsCmdSPTI

Stop Pulse Train Immediately.

enumerator kENET_QOS_PtpPpsCmdCSPT

Cancel Stop Pulse Train.

enum _enet_qos_ets_list_length

Defines the enmueration of ETS list length.

Values:

enumerator kENET_QOS_Ets_List_64

List length of 64

enumerator kENET_QOS_Ets_List_128

List length of 128

enumerator kENET_QOS_Ets_List_256

List length of 256

enumerator kENET_QOS_Ets_List_512

List length of 512

enumerator kENET_QOS_Ets_List_1024

List length of 1024

enum _enet_qos_ets_gccr_addr

Defines the enmueration of ETS gate control address.

Values:

enumerator kENET_QOS_Ets_btr_low

BTR Low

enumerator kENET_QOS_Ets_btr_high

BTR High

enumerator kENET_QOS_Ets_ctr_low

CTR Low

enumerator kENET_QOS_Ets_ctr_high

CTR High

enumerator kENET_QOS_Ets_ter

TER

enumerator kENET_QOS_Ets_llr

LLR

enum _enet_qos_rxp_dma_chn

Defines the enmueration of DMA channel used for rx parser entry.

Values:

enumerator kENET_QOS_Rxp_DMAChn0

DMA Channel 0 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn1

DMA Channel 1 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn2

DMA Channel 2 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn3

DMA Channel 3 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn4

DMA Channel 4 used for RXP entry match

enum _enet_qos_tx_offload

Define the Tx checksum offload options.

Values:

enumerator kENET_QOS_TxOffloadDisable

Disable Tx checksum offload.

enumerator kENET_QOS_TxOffloadIPHeader

Enable IP header checksum calculation and insertion.

enumerator kENET_QOS_TxOffloadIPHeaderPlusPayload

Enable IP header and payload checksum calculation and insertion.

enumerator kENET_QOS_TxOffloadAll

Enable IP header, payload and pseudo header checksum calculation and insertion.

typedef enum _enet_qos_mii_mode enet_qos_mii_mode_t

Defines the MII/RGMII mode for data interface between the MAC and the PHY.

typedef enum _enet_qos_mii_speed enet_qos_mii_speed_t

Defines the 10/100/1000 Mbps speed for the MII data interface.

typedef enum _enet_qos_mii_duplex enet_qos_mii_duplex_t

Defines the half or full duplex for the MII data interface.

typedef enum _enet_qos_mii_normal_opcode enet_qos_mii_normal_opcode

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

typedef enum _enet_qos_dma_burstlen enet_qos_dma_burstlen

Define the DMA maximum transmit burst length.

typedef enum _enet_qos_desc_flag enet_qos_desc_flag

Define the flag for the descriptor.

typedef enum _enet_qos_systime_op enet_qos_systime_op

Define the system time adjust operation control.

typedef enum _enet_qos_ts_rollover_type enet_qos_ts_rollover_type

Define the system time rollover control.

typedef enum _enet_qos_special_config enet_qos_special_config_t

Defines some special configuration for ENET.

These control flags are provided for special user requirements. Normally, these is no need to set this control flags for ENET initialization. But if you have some special requirements, set the flags to specialControl in the enet_qos_config_t.

Note

“kENET_QOS_StoreAndForward” is recommended to be set.

typedef enum _enet_qos_dma_interrupt_enable enet_qos_dma_interrupt_enable_t

List of DMA interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

typedef enum _enet_qos_mac_interrupt_enable enet_qos_mac_interrupt_enable_t

List of mac interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

typedef enum _enet_qos_event enet_qos_event_t

Defines the common interrupt event for callback use.

typedef enum _enet_qos_queue_mode enet_qos_queue_mode_t

Define the MTL mode for multiple queues/rings.

typedef enum _enet_qos_mtl_multiqueue_txsche enet_qos_mtl_multiqueue_txsche

Define the MTL tx scheduling algorithm for multiple queues/rings.

typedef enum _enet_qos_mtl_multiqueue_rxsche enet_qos_mtl_multiqueue_rxsche

Define the MTL rx scheduling algorithm for multiple queues/rings.

typedef enum _enet_qos_mtl_rxqueuemap enet_qos_mtl_rxqueuemap_t

Define the MTL rx queue and DMA channel mapping.

typedef enum _enet_qos_rx_queue_route enet_qos_rx_queue_route_t

Defines the package type for receive queue routing.

typedef enum _enet_qos_ptp_event_type enet_qos_ptp_event_type_t

Defines the ENET PTP message related constant.

typedef enum _enet_qos_ptp_pps_instance enet_qos_ptp_pps_instance_t

Defines the PPS instance numbers.

typedef enum _enet_qos_ptp_pps_trgt_mode enet_qos_ptp_pps_trgt_mode_t

Defines the Target Time register mode.

typedef enum _enet_qos_ptp_pps_cmd enet_qos_ptp_pps_cmd_t

Defines commands for ppscmd register.

typedef enum _enet_qos_ets_list_length enet_qos_ets_list_length_t

Defines the enmueration of ETS list length.

typedef enum _enet_qos_ets_gccr_addr enet_qos_ets_gccr_addr_t

Defines the enmueration of ETS gate control address.

typedef enum _enet_qos_rxp_dma_chn enet_qos_rxp_dma_chn_t

Defines the enmueration of DMA channel used for rx parser entry.

typedef enum _enet_qos_tx_offload enet_qos_tx_offload_t

Define the Tx checksum offload options.

typedef struct _enet_qos_rx_bd_struct enet_qos_rx_bd_struct_t

Defines the receive descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the receive descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the receive data process.

typedef struct _enet_qos_tx_bd_struct enet_qos_tx_bd_struct_t

Defines the transmit descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the transmit descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the transmit data process.

typedef struct _enet_qos_tx_bd_config_struct enet_qos_tx_bd_config_struct_t

Defines the Tx BD configuration structure.

typedef struct _enet_qos_ptp_time enet_qos_ptp_time_t

Defines the ENET PTP time stamp structure.

typedef struct enet_qos_frame_info enet_qos_frame_info_t

Defines the frame info structure.

typedef struct _enet_qos_tx_dirty_ring enet_qos_tx_dirty_ring_t

Defines the ENET transmit dirty addresses ring/queue structure.

typedef struct _enet_qos_ptp_config enet_qos_ptp_config_t

Defines the ENET PTP configuration structure.

typedef struct _enet_qos_est_gate_op enet_qos_est_gate_op_t

Defines the EST gate operation structure.

typedef struct _enet_qos_est_gcl enet_qos_est_gcl_t

Defines the EST gate control list structure.

typedef struct _enet_qos_rxp_config enet_qos_rxp_config_t

Defines the ENET_QOS Rx parser configuration structure.

typedef struct _enet_qos_buffer_config enet_qos_buffer_config_t

Defines the buffer descriptor configure structure.

Note

1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.

2. The recommended minimum tx/rx ring length is 4.

3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end of the last last descriptor. because only the descriptors between the start address and the tail address will be used by DMA.

4. The descriptor address is the start address of all used contiguous memory. for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories for rx descriptor ring 0.

5. The “*rxBufferstartAddr” is the first element of rxRingLen (2*rxRingLen for double buffers) rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the address of a rxRingLen or 2*rxRingLen array.

typedef struct _enet_qos_cbs_config enet_qos_cbs_config_t

Defines the CBS configuration for queue.

typedef struct enet_qos_tx_queue_config enet_qos_queue_tx_config_t

Defines the queue configuration structure.

typedef struct enet_qos_rx_queue_config enet_qos_queue_rx_config_t

Defines the queue configuration structure.

typedef struct enet_qos_multiqueue_config enet_qos_multiqueue_config_t

Defines the configuration when multi-queue is used.

typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel)

Defines the Rx memory buffer alloc function pointer.

typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel)

Defines the Rx memory buffer free function pointer.

typedef struct _enet_qos_config enet_qos_config_t

Defines the basic configuration structure for the ENET device.

Note

Default the signal queue is used so the “*multiqueueCfg” is set default with NULL. Set the pointer with a valid configuration pointer if the multiple queues are required. If multiple queue is enabled, please make sure the buffer configuration for all are prepared also.

typedef struct _enet_qos_handle enet_qos_handle_t

typedef void (*enet_qos_callback_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData)

ENET callback function.

typedef struct _enet_qos_tx_bd_ring enet_qos_tx_bd_ring_t

Defines the ENET transmit buffer descriptor ring/queue structure.

typedef struct _enet_qos_rx_bd_ring enet_qos_rx_bd_ring_t

Defines the ENET receive buffer descriptor ring/queue structure.

typedef struct _enet_qos_state enet_qos_state_t

Defines the ENET state structure.

Note

The structure contains saved state for the instance. It could be stored in enet_qos_handle_t, but that’s used only with the transactional API.

typedef struct _enet_qos_buffer_struct enet_qos_buffer_struct_t

Defines the frame buffer structure.

typedef struct _enet_qos_rx_frame_error enet_qos_rx_frame_error_t

Defines the Rx frame error structure.

typedef struct _enet_qos_rx_frame_attribute_struct enet_qos_rx_frame_attribute_t

typedef struct _enet_qos_rx_frame_struct enet_qos_rx_frame_struct_t

Defines the Rx frame data structure.

typedef struct _enet_qos_transfer_stats enet_qos_transfer_stats_t

Defines the ENET QOS transfer statistics structure.

typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle)

const clock_ip_name_t s_enetqosClock[]

Pointers to enet clocks for each instance.

void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode)

Set ENET system configuration.

Note

User needs to provide the implementation because the implementation is SoC specific. This function set the phy selection and enable clock. It should be called before any other ethernet operation.

Parameters:

• miiMode – The MII/RGMII/RMII mode for interface between the phy and Ethernet.

void ENET_QOS_EnableClock(bool enable)

Enable/Disable ENET qos clock.

Note

User needs to provide the implementation because the implementation is SoC specific. This function should be called before config RMII mode.

struct _enet_qos_rx_bd_struct

#include <fsl_enet_qos.h>

Defines the receive descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the receive descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the receive data process.

Public Members

__IO uint32_t buff1Addr

Buffer 1 address

__IO uint32_t reserved

Reserved

__IO uint32_t buff2Addr

Buffer 2 or next descriptor address

__IO uint32_t control

Buffer 1/2 byte counts and control

struct _enet_qos_tx_bd_struct

#include <fsl_enet_qos.h>

Defines the transmit descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the transmit descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the transmit data process.

Public Members

__IO uint32_t buff1Addr

Buffer 1 address

__IO uint32_t buff2Addr

Buffer 2 address

__IO uint32_t buffLen

Buffer 1/2 byte counts

__IO uint32_t controlStat

TDES control and status word

struct _enet_qos_tx_bd_config_struct

#include <fsl_enet_qos.h>

Defines the Tx BD configuration structure.

Public Members

void *buffer1

The first buffer address in the descriptor.

uint32_t bytes1

The bytes in the fist buffer.

void *buffer2

The second buffer address in the descriptor.

uint32_t bytes2

The bytes in the second buffer.

uint32_t framelen

The length of the frame to be transmitted.

bool intEnable

Interrupt enable flag.

bool tsEnable

The timestamp enable.

enet_qos_tx_offload_t txOffloadOps

The Tx checksum offload option.

enet_qos_desc_flag flag

The flag of this tx desciriptor, see “enet_qos_desc_flag”.

struct _enet_qos_ptp_time

#include <fsl_enet_qos.h>

Defines the ENET PTP time stamp structure.

Public Members

uint64_t second

Second.

uint32_t nanosecond

Nanosecond.

struct enet_qos_frame_info

#include <fsl_enet_qos.h>

Defines the frame info structure.

Public Members

void *context

User specified data, could be buffer address for free

bool isTsAvail

Flag indicates timestamp available status

enet_qos_ptp_time_t timeStamp

Timestamp of frame

struct _enet_qos_tx_dirty_ring

#include <fsl_enet_qos.h>

Defines the ENET transmit dirty addresses ring/queue structure.

Public Members

enet_qos_frame_info_t *txDirtyBase

Dirty buffer descriptor base address pointer.

uint16_t txGenIdx

tx generate index.

uint16_t txConsumIdx

tx consume index.

uint16_t txRingLen

tx ring length.

bool isFull

tx ring is full flag, add this parameter to avoid waste one element.

struct _enet_qos_ptp_config

#include <fsl_enet_qos.h>

Defines the ENET PTP configuration structure.

Public Members

bool fineUpdateEnable

Use the fine update.

uint32_t defaultAddend

Default addend value when fine update is enable, could be 2^32 / (refClk_Hz / ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ).

bool ptp1588V2Enable

The desired system time frequency. Must be lower than reference clock. (Only used with fine correction method). ptp 1588 version 2 is used.

enet_qos_ts_rollover_type tsRollover

1588 time nanosecond rollover.

struct _enet_qos_est_gate_op

#include <fsl_enet_qos.h>

Defines the EST gate operation structure.

struct _enet_qos_est_gcl

#include <fsl_enet_qos.h>

Defines the EST gate control list structure.

Public Members

bool enable

Enable or disable EST

uint64_t cycleTime

Base Time 32 bits seconds 32 bits nanoseconds

uint32_t extTime

Cycle Time 32 bits seconds 32 bits nanoseconds

uint32_t numEntries

Time Extension 32 bits seconds 32 bits nanoseconds

enet_qos_est_gate_op_t *opList

Number of entries

struct _enet_qos_rxp_config

#include <fsl_enet_qos.h>

Defines the ENET_QOS Rx parser configuration structure.

Public Members

uint32_t matchEnable

4-byte match data used for comparing with incoming packet

uint8_t acceptFrame

When matchEnable is set to 1, the matchData is used for comparing

uint8_t rejectFrame

When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel

uint8_t inverseMatch

When rejectFrame = 1 and data is matched, the frame will be dropped

uint8_t nextControl

Inverse match

uint8_t reserved

Next instruction indexing control

uint8_t frameOffset

Reserved control fields

uint8_t okIndex

Frame offset in the packet data to be compared for match, in terms of 4 bytes.

uint8_t dmaChannel

Memory Index to be used next.

uint32_t reserved2

The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and acceptFrame = 1

struct _enet_qos_buffer_config

#include <fsl_enet_qos.h>

Defines the buffer descriptor configure structure.

Note

1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.

2. The recommended minimum tx/rx ring length is 4.

3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end of the last last descriptor. because only the descriptors between the start address and the tail address will be used by DMA.

4. The descriptor address is the start address of all used contiguous memory. for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories for rx descriptor ring 0.

5. The “*rxBufferstartAddr” is the first element of rxRingLen (2*rxRingLen for double buffers) rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the address of a rxRingLen or 2*rxRingLen array.

Public Members

uint8_t rxRingLen

The length of receive buffer descriptor ring.

uint8_t txRingLen

The length of transmit buffer descriptor ring.

enet_qos_tx_bd_struct_t *txDescStartAddrAlign

Aligned transmit descriptor start address.

enet_qos_tx_bd_struct_t *txDescTailAddrAlign

Aligned transmit descriptor tail address.

enet_qos_frame_info_t *txDirtyStartAddr

Start address of the dirty tx frame information.

enet_qos_rx_bd_struct_t *rxDescStartAddrAlign

Aligned receive descriptor start address.

enet_qos_rx_bd_struct_t *rxDescTailAddrAlign

Aligned receive descriptor tail address.

uint32_t *rxBufferStartAddr

Start address of the rx buffers.

uint32_t rxBuffSizeAlign

Aligned receive data buffer size.

bool rxBuffNeedMaintain

Whether receive data buffer need cache maintain.

struct _enet_qos_cbs_config

#include <fsl_enet_qos.h>

Defines the CBS configuration for queue.

Public Members

uint16_t sendSlope

Send slope configuration.

uint16_t idleSlope

Idle slope configuration.

uint32_t highCredit

High credit.

uint32_t lowCredit

Low credit.

struct enet_qos_tx_queue_config

#include <fsl_enet_qos.h>

Defines the queue configuration structure.

Public Members

enet_qos_queue_mode_t mode

tx queue mode configuration.

uint32_t weight

Refer to the MTL TxQ Quantum Weight register.

uint32_t priority

Refer to Transmit Queue Priority Mapping register.

enet_qos_cbs_config_t *cbsConfig

CBS configuration if queue use AVB mode.

struct enet_qos_rx_queue_config

#include <fsl_enet_qos.h>

Defines the queue configuration structure.

Public Members

enet_qos_queue_mode_t mode

rx queue mode configuration.

uint8_t mapChannel

tx queue map dma channel.

uint32_t priority

Rx queue priority.

enet_qos_rx_queue_route_t packetRoute

Receive packet routing.

struct enet_qos_multiqueue_config

#include <fsl_enet_qos.h>

Defines the configuration when multi-queue is used.

Public Members

enet_qos_dma_burstlen burstLen

Burst len for the multi-queue.

uint8_t txQueueUse

Used Tx queue count.

enet_qos_mtl_multiqueue_txsche mtltxSche

Transmit schedule for multi-queue.

enet_qos_queue_tx_config_t txQueueConfig[(5U)]

Tx Queue configuration.

uint8_t rxQueueUse

Used Rx queue count.

enet_qos_mtl_multiqueue_rxsche mtlrxSche

Receive schedule for multi-queue.

enet_qos_queue_rx_config_t rxQueueConfig[(5U)]

Rx Queue configuration.

struct _enet_qos_config

#include <fsl_enet_qos.h>

Defines the basic configuration structure for the ENET device.

Note

Default the signal queue is used so the “*multiqueueCfg” is set default with NULL. Set the pointer with a valid configuration pointer if the multiple queues are required. If multiple queue is enabled, please make sure the buffer configuration for all are prepared also.

Public Members

uint16_t specialControl

The logic or of enet_qos_special_config_t

enet_qos_multiqueue_config_t *multiqueueCfg

Use multi-queue.

enet_qos_mii_mode_t miiMode

MII mode.

enet_qos_mii_speed_t miiSpeed

MII Speed.

enet_qos_mii_duplex_t miiDuplex

MII duplex.

uint16_t pauseDuration

Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set.

enet_qos_ptp_config_t *ptpConfig

PTP 1588 feature configuration

uint32_t csrClock_Hz

CSR clock frequency in HZ.

enet_qos_rx_alloc_callback_t rxBuffAlloc

Callback to alloc memory, must be provided for zero-copy Rx.

enet_qos_rx_free_callback_t rxBuffFree

Callback to free memory, must be provided for zero-copy Rx.

struct _enet_qos_tx_bd_ring

#include <fsl_enet_qos.h>

Defines the ENET transmit buffer descriptor ring/queue structure.

Public Members

enet_qos_tx_bd_struct_t *txBdBase

Buffer descriptor base address pointer.

uint16_t txGenIdx

tx generate index.

uint16_t txConsumIdx

tx consume index.

volatile uint16_t txDescUsed

tx descriptor used number.

uint16_t txRingLen

tx ring length.

struct _enet_qos_rx_bd_ring

#include <fsl_enet_qos.h>

Defines the ENET receive buffer descriptor ring/queue structure.

Public Members

enet_qos_rx_bd_struct_t *rxBdBase

Buffer descriptor base address pointer.

uint16_t rxGenIdx

The current available receive buffer descriptor pointer.

uint16_t rxRingLen

Receive ring length.

uint32_t rxBuffSizeAlign

Receive buffer size.

struct _enet_qos_handle

#include <fsl_enet_qos.h>

Defines the ENET handler structure.

Public Members

uint8_t txQueueUse

Used tx queue count.

uint8_t rxQueueUse

Used rx queue count.

bool doubleBuffEnable

The double buffer is used in the descriptor.

bool rxintEnable

Rx interrupt enabled.

bool rxMaintainEnable[(5U)]

Rx buffer cache maintain enabled.

enet_qos_rx_bd_ring_t rxBdRing[(5U)]

Receive buffer descriptor.

enet_qos_tx_bd_ring_t txBdRing[(5U)]

Transmit buffer descriptor.

enet_qos_tx_dirty_ring_t txDirtyRing[(5U)]

Transmit dirty buffers addresses.

uint32_t *rxBufferStartAddr[(5U)]

Rx buffer start address for reInitialize.

enet_qos_callback_t callback

Callback function.

void *userData

Callback function parameter.

uint8_t multicastCount[64]

Multicast collisions counter

enet_qos_rx_alloc_callback_t rxBuffAlloc

Callback to alloc memory, must be provided for zero-copy Rx.

enet_qos_rx_free_callback_t rxBuffFree

Callback to free memory, must be provided for zero-copy Rx.

struct _enet_qos_state

#include <fsl_enet_qos.h>

Defines the ENET state structure.

Note

The structure contains saved state for the instance. It could be stored in enet_qos_handle_t, but that’s used only with the transactional API.

Public Members

enet_qos_mii_mode_t miiMode

MII mode.

struct _enet_qos_buffer_struct

#include <fsl_enet_qos.h>

Defines the frame buffer structure.

Public Members

void *buffer

The buffer store the whole or partial frame.

uint16_t length

The byte length of this buffer.

struct _enet_qos_rx_frame_error

#include <fsl_enet_qos.h>

Defines the Rx frame error structure.

Public Members

bool rxDstAddrFilterErr

Destination Address Filter Fail.

bool rxSrcAddrFilterErr

SA Address Filter Fail.

bool rxDribbleErr

Dribble error.

bool rxReceiveErr

Receive error.

bool rxOverFlowErr

Receive over flow.

bool rxWatchDogErr

Watch dog timeout.

bool rxGaintPacketErr

Receive gaint packet.

bool rxCrcErr

Receive CRC error.

struct _enet_qos_rx_frame_attribute_struct

#include <fsl_enet_qos.h>

Public Members

bool isTsAvail

Rx frame timestamp is available or not.

enet_qos_ptp_time_t timestamp

The nanosecond part timestamp of this Rx frame.

struct _enet_qos_rx_frame_struct

#include <fsl_enet_qos.h>

Defines the Rx frame data structure.

Public Members

enet_qos_buffer_struct_t *rxBuffArray

Rx frame buffer structure.

uint16_t totLen

Rx frame total length.

enet_qos_rx_frame_attribute_t rxAttribute

Rx frame attribute structure.

enet_qos_rx_frame_error_t rxFrameError

Rx frame error.

struct _enet_qos_transfer_stats

#include <fsl_enet_qos.h>

Defines the ENET QOS transfer statistics structure.

Public Members

uint32_t statsRxFrameCount

Rx frame number.

uint32_t statsRxCrcErr

Rx frame number with CRC error.

uint32_t statsRxAlignErr

Rx frame number with alignment error.

uint32_t statsRxLengthErr

Rx frame length field doesn’t equal to packet size.

uint32_t statsRxFifoOverflowErr

Rx FIFO overflow count.

uint32_t statsTxFrameCount

Tx frame number.

uint32_t statsTxFifoUnderRunErr

Tx FIFO underrun count.

EWM: External Watchdog Monitor Driver

void EWM_Init(EWM_Type *base, const ewm_config_t *config)

Initializes the EWM peripheral.

This function is used to initialize the EWM. After calling, the EWM runs immediately according to the configuration. Note that, except for the interrupt enable control bit, other control bits and registers are write once after a CPU reset. Modifying them more than once generates a bus transfer error.

This is an example.

ewm_config_t config;
EWM_GetDefaultConfig(&config);
config.compareHighValue = 0xAAU;
EWM_Init(ewm_base,&config);

Parameters:

• base – EWM peripheral base address

• config – The configuration of the EWM

void EWM_Deinit(EWM_Type *base)

Deinitializes the EWM peripheral.

This function is used to shut down the EWM.

Parameters:

• base – EWM peripheral base address

void EWM_GetDefaultConfig(ewm_config_t *config)

Initializes the EWM configuration structure.

This function initializes the EWM configuration structure to default values. The default values are as follows.

ewmConfig->enableEwm = true;
ewmConfig->enableEwmInput = false;
ewmConfig->setInputAssertLogic = false;
ewmConfig->enableInterrupt = false;
ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
ewmConfig->prescaler = 0;
ewmConfig->compareLowValue = 0;
ewmConfig->compareHighValue = 0xFEU;

See also

ewm_config_t

Parameters:

• config – Pointer to the EWM configuration structure.

static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)

Enables the EWM interrupt.

This function enables the EWM interrupt.

Parameters:

• base – EWM peripheral base address

• mask – The interrupts to enable The parameter can be combination of the following source if defined

  • kEWM_InterruptEnable

static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)

Disables the EWM interrupt.

This function enables the EWM interrupt.

Parameters:

• base – EWM peripheral base address

• mask – The interrupts to disable The parameter can be combination of the following source if defined

  • kEWM_InterruptEnable

static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)

Gets all status flags.

This function gets all status flags.

This is an example for getting the running flag.

uint32_t status;
status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;

See also

_ewm_status_flags_t

• True: a related status flag has been set.

• False: a related status flag is not set.

Parameters:

• base – EWM peripheral base address

Returns:

State of the status flag: asserted (true) or not-asserted (false).

void EWM_Refresh(EWM_Type *base)

Services the EWM.

This function resets the EWM counter to zero.

Parameters:

• base – EWM peripheral base address

FSL_EWM_DRIVER_VERSION

EWM driver version 2.0.3.

enum _ewm_lpo_clock_source

Describes EWM clock source.

Values:

enumerator kEWM_LpoClockSource0

EWM clock sourced from lpo_clk[0]

enumerator kEWM_LpoClockSource1

EWM clock sourced from lpo_clk[1]

enumerator kEWM_LpoClockSource2

EWM clock sourced from lpo_clk[2]

enumerator kEWM_LpoClockSource3

EWM clock sourced from lpo_clk[3]

enum _ewm_interrupt_enable_t

EWM interrupt configuration structure with default settings all disabled.

This structure contains the settings for all of EWM interrupt configurations.

Values:

enumerator kEWM_InterruptEnable

Enable the EWM to generate an interrupt

enum _ewm_status_flags_t

EWM status flags.

This structure contains the constants for the EWM status flags for use in the EWM functions.

Values:

enumerator kEWM_RunningFlag

Running flag, set when EWM is enabled

typedef enum _ewm_lpo_clock_source ewm_lpo_clock_source_t

Describes EWM clock source.

typedef struct _ewm_config ewm_config_t

Data structure for EWM configuration.

This structure is used to configure the EWM.

struct _ewm_config

#include <fsl_ewm.h>

Data structure for EWM configuration.

This structure is used to configure the EWM.

Public Members

bool enableEwm

Enable EWM module

bool enableEwmInput

Enable EWM_in input

bool setInputAssertLogic

EWM_in signal assertion state

bool enableInterrupt

Enable EWM interrupt

ewm_lpo_clock_source_t clockSource

Clock source select

uint8_t prescaler

Clock prescaler value

uint8_t compareLowValue

Compare low-register value

uint8_t compareHighValue

Compare high-register value

FlexCAN: Flex Controller Area Network Driver

FlexCAN Driver

bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)

Determine whether the FlexCAN instance support CAN FD mode at run time.

Note

Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.

void FLEXCAN_EnterFreezeMode(CAN_Type *base)

Enter FlexCAN Freeze Mode.

This function makes the FlexCAN work under Freeze Mode.

Parameters:

• base – FlexCAN peripheral base address.

void FLEXCAN_ExitFreezeMode(CAN_Type *base)

Exit FlexCAN Freeze Mode.

This function makes the FlexCAN leave Freeze Mode.

Parameters:

• base – FlexCAN peripheral base address.

uint32_t FLEXCAN_GetInstance(CAN_Type *base)

Get the FlexCAN instance from peripheral base address.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN instance.

bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit Rates for classical CAN.

This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.

Parameters:

• base – FlexCAN peripheral base address.

• bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.

• sourceClock_Hz – The Source clock frequency in Hz.

• pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration.

void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the user-defined configuration structure.

• sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit rates for CANFD.

This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.

Parameters:

• base – FlexCAN peripheral base address.

• bitRate – The CANFD bus control speed in bps defined by user.

• bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.

• sourceClock_Hz – The Source clock frequency in Hz.

• pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration

void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.bitRateFD            = 2000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the user-defined configuration structure.

• sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

• dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.

• brs – True if bit rate switch is enabled in FD mode.

void FLEXCAN_Deinit(CAN_Type *base)

De-initializes a FlexCAN instance.

This function disables the FlexCAN module clock and sets all register values to the reset value.

Parameters:

• base – FlexCAN peripheral base address.

void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)

Gets the default configuration structure.

This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;

Parameters:

• pConfig – Pointer to the FlexCAN configuration structure.

void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN classical CAN protocol timing characteristic.

This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.

Note

Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)

Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.

This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.

Note

Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().

Parameters:

• base – FlexCAN peripheral base address.

• sourceClock_Hz – Source Clock in Hz.

• bitRate_Bps – Bit rate in Bps.

Returns:

kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.

void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN CANFD data phase timing characteristic.

This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.

Note

Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)

Set bit rate of FlexCAN FD frame.

This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.

Parameters:

• base – FlexCAN peripheral base address.

• sourceClock_Hz – Source Clock in Hz.

• bitRateN_Bps – Nominal bit Rate in Bps.

• bitRateD_Bps – Data bit Rate in Bps.

Returns:

kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.

void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive message buffer global mask.

This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().

Parameters:

• base – FlexCAN peripheral base address.

• mask – Rx Message Buffer Global Mask value.

void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive FIFO global mask.

This function sets the global mask for FlexCAN FIFO in a matching process.

Parameters:

• base – FlexCAN peripheral base address.

• mask – Rx Fifo Global Mask value.

void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)

Sets the FlexCAN receive individual mask.

This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.

Parameters:

• base – FlexCAN peripheral base address.

• maskIdx – The Index of individual Mask.

• mask – Rx Individual Mask value.

void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• enable – Enable/disable Tx Message Buffer.

  • true: Enable Tx Message Buffer.

  • false: Disable Tx Message Buffer.

void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.

• enable – Enable/disable Rx Message Buffer.

  • true: Enable Rx Message Buffer.

  • false: Disable Rx Message Buffer.

void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• enable – Enable/disable Tx Message Buffer.

  • true: Enable Tx Message Buffer.

  • false: Disable Tx Message Buffer.

void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.

• enable – Enable/disable Rx Message Buffer.

  • true: Enable Rx Message Buffer.

  • false: Disable Rx Message Buffer.

void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)

Configures a FlexCAN Remote Response Message Buffer.

User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pFrame – Pointer to CAN message frame structure for response.

void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)

Configures the FlexCAN Legacy Rx FIFO.

This function configures the FlexCAN Rx FIFO with given configuration.

Note

Legacy Rx FIFO only can receive classic CAN message.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.

• enable – Enable/disable Legacy Rx FIFO.

  • true: Enable Legacy Rx FIFO.

  • false: Disable Legacy Rx FIFO.

void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)

Configures the FlexCAN Pretended Networking mode.

This function configures the FlexCAN Pretended Networking mode with given configuration.

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.

static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)

Gets the FlexCAN module interrupt flags.

This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.

static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)

Clears status flags with the provided mask.

This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.

static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)

Gets the FlexCAN Bus Error Counter value.

This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.

Parameters:

• base – FlexCAN peripheral base address.

• txErrBuf – Buffer to store Tx Error Counter value.

• rxErrBuf – Buffer to store Rx Error Counter value.

static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN Message Buffer interrupt flags.

This function gets the interrupt flags of a given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN Message Buffer interrupt flags.

This function clears the interrupt flags of a given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)

Gets the FlexCAN Memory Error Report registers status.

This function gets the FlexCAN Memory Error Report registers status.

Parameters:

• base – FlexCAN peripheral base address.

• errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.

static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)

Gets the FlexCAN Number of Matches when in Pretended Networking.

This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

The number of received wake up msessages.

static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN interrupts according to the provided mask.

This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN interrupts according to the provided mask.

This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN Message Buffer interrupts.

This function enables the interrupts of given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN Message Buffer interrupts.

This function disables the interrupts of given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)

Enables or disables the FlexCAN Rx FIFO DMA request.

This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• enable – true to enable, false to disable.

static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)

Gets the Rx FIFO Head address.

This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN Rx FIFO Head address.

static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)

Enables or disables the FlexCAN module operation.

This function enables or disables the FlexCAN module.

Parameters:

• base – FlexCAN base pointer.

• enable – true to enable, false to disable.

status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)

Writes a FlexCAN Message to the Transmit Message Buffer.

This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN Message Buffer index.

• pTxFrame – Pointer to CAN message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Receive Message Buffer.

This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN Message Buffer index.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)

Writes a FlexCAN FD Message to the Transmit Message Buffer.

This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN FD Message Buffer index.

• pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN FD Message from Receive Message Buffer.

This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN FD Message Buffer index.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Legacy Rx FIFO.

This function reads a CAN message from the FlexCAN Legacy Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Wake Up MB.

This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFrame – Pointer to CAN message frame structure for reception.

• mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.

Return values:

• kStatus_Success – - Read Message from Wake up Message Buffer successfully.

• kStatus_Fail – - Wake up Message Buffer has no valid content.

status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

• pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – Start Tx Message Buffer sending process successfully.

• kStatus_Fail – Write Tx Message Buffer failed.

• kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – - Start Rx Message Buffer receiving process successfully.

• kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN Message Buffer index.

• pTxFrame – Pointer to CAN message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN Message Buffer index.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)

Initializes the FlexCAN handle.

This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• callback – The callback function.

• userData – The parameter of the callback function.

status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – Start Tx Message Buffer sending process successfully.

• kStatus_Fail – Write Tx Message Buffer failed.

• kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – - Start Rx Message Buffer receiving process successfully.

• kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.

Return values:

• kStatus_Success – - Start Rx FIFO receiving process successfully.

• kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)

Gets the detail index of Mailbox’s Timestamp by handle.

Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking

Parameters:

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

Return values:

the – index of mailbox ‘s timestamp stored in the handle.

void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Rx FIFO process.

This function aborts the interrupt driven message receive from Rx FIFO process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN IRQ handle function.

This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

FSL_FLEXCAN_DRIVER_VERSION

FlexCAN driver version.

FlexCAN transfer status.

Values:

enumerator kStatus_FLEXCAN_TxBusy

Tx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_TxIdle

Tx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_TxSwitchToRx

Remote Message is send out and Message buffer changed to Receive one.

enumerator kStatus_FLEXCAN_RxBusy

Rx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_RxIdle

Rx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_RxOverflow

Rx Message Buffer is Overflowed.

enumerator kStatus_FLEXCAN_RxFifoBusy

Rx Message FIFO is Busy.

enumerator kStatus_FLEXCAN_RxFifoIdle

Rx Message FIFO is Idle.

enumerator kStatus_FLEXCAN_RxFifoOverflow

Rx Message FIFO is overflowed.

enumerator kStatus_FLEXCAN_RxFifoWarning

Rx Message FIFO is almost overflowed.

enumerator kStatus_FLEXCAN_RxFifoDisabled

Rx Message FIFO is disabled during reading.

enumerator kStatus_FLEXCAN_ErrorStatus

FlexCAN Module Error and Status.

enumerator kStatus_FLEXCAN_WakeUp

FlexCAN is waken up from STOP mode.

enumerator kStatus_FLEXCAN_UnHandled

UnHadled Interrupt asserted.

enumerator kStatus_FLEXCAN_RxRemote

Rx Remote Message Received in Mail box.

enum _flexcan_frame_format

FlexCAN frame format.

Values:

enumerator kFLEXCAN_FrameFormatStandard

Standard frame format attribute.

enumerator kFLEXCAN_FrameFormatExtend

Extend frame format attribute.

enum _flexcan_frame_type

FlexCAN frame type.

Values:

enumerator kFLEXCAN_FrameTypeData

Data frame type attribute.

enumerator kFLEXCAN_FrameTypeRemote

Remote frame type attribute.

enum _flexcan_clock_source

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

Values:

enumerator kFLEXCAN_ClkSrcOsc

FlexCAN Protocol Engine clock from Oscillator.

enumerator kFLEXCAN_ClkSrcPeri

FlexCAN Protocol Engine clock from Peripheral Clock.

enumerator kFLEXCAN_ClkSrc0

FlexCAN Protocol Engine clock selected by user as SRC == 0.

enumerator kFLEXCAN_ClkSrc1

FlexCAN Protocol Engine clock selected by user as SRC == 1.

enum _flexcan_wake_up_source

FlexCAN wake up source.

Values:

enumerator kFLEXCAN_WakeupSrcUnfiltered

FlexCAN uses unfiltered Rx input to detect edge.

enumerator kFLEXCAN_WakeupSrcFiltered

FlexCAN uses filtered Rx input to detect edge.

enum _flexcan_rx_fifo_filter_type

FlexCAN Rx Fifo Filter type.

Values:

enumerator kFLEXCAN_RxFifoFilterTypeA

One full ID (standard and extended) per ID Filter element.

enumerator kFLEXCAN_RxFifoFilterTypeB

Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeC

Four partial 8-bit Standard or extended ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeD

All frames rejected.

enum _flexcan_mb_size

FlexCAN Message Buffer Payload size.

Values:

enumerator kFLEXCAN_8BperMB

Selects 8 bytes per Message Buffer.

enumerator kFLEXCAN_16BperMB

Selects 16 bytes per Message Buffer.

enumerator kFLEXCAN_32BperMB

Selects 32 bytes per Message Buffer.

enumerator kFLEXCAN_64BperMB

Selects 64 bytes per Message Buffer.

enum _flexcan_fd_frame_length

FlexCAN CAN FD frame supporting data length (available DLC values).

For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.

Values:

enumerator kFLEXCAN_0BperFrame

Frame contains 0 valid data bytes.

enumerator kFLEXCAN_1BperFrame

Frame contains 1 valid data bytes.

enumerator kFLEXCAN_2BperFrame

Frame contains 2 valid data bytes.

enumerator kFLEXCAN_3BperFrame

Frame contains 3 valid data bytes.

enumerator kFLEXCAN_4BperFrame

Frame contains 4 valid data bytes.

enumerator kFLEXCAN_5BperFrame

Frame contains 5 valid data bytes.

enumerator kFLEXCAN_6BperFrame

Frame contains 6 valid data bytes.

enumerator kFLEXCAN_7BperFrame

Frame contains 7 valid data bytes.

enumerator kFLEXCAN_8BperFrame

Frame contains 8 valid data bytes.

enumerator kFLEXCAN_12BperFrame

Frame contains 12 valid data bytes.

enumerator kFLEXCAN_16BperFrame

Frame contains 16 valid data bytes.

enumerator kFLEXCAN_20BperFrame

Frame contains 20 valid data bytes.

enumerator kFLEXCAN_24BperFrame

Frame contains 24 valid data bytes.

enumerator kFLEXCAN_32BperFrame

Frame contains 32 valid data bytes.

enumerator kFLEXCAN_48BperFrame

Frame contains 48 valid data bytes.

enumerator kFLEXCAN_64BperFrame

Frame contains 64 valid data bytes.

enum _flexcan_rx_fifo_priority

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

Values:

enumerator kFLEXCAN_RxFifoPrioLow

Matching process start from Rx Message Buffer first.

enumerator kFLEXCAN_RxFifoPrioHigh

Matching process start from Enhanced/Legacy Rx FIFO first.

enum _flexcan_interrupt_enable

FlexCAN interrupt enable enumerations.

This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.

Note

FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.

Values:

enumerator kFLEXCAN_BusOffInterruptEnable

Bus Off interrupt, use bit 15.

enumerator kFLEXCAN_ErrorInterruptEnable

CAN Error interrupt, use bit 14.

enumerator kFLEXCAN_TxWarningInterruptEnable

Tx Warning interrupt, use bit 11.

enumerator kFLEXCAN_RxWarningInterruptEnable

Rx Warning interrupt, use bit 10.

enumerator kFLEXCAN_WakeUpInterruptEnable

Self Wake Up interrupt, use bit 26.

enumerator kFLEXCAN_FDErrorInterruptEnable

CAN FD Error interrupt, use bit 31.

enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable

PN Match Wake Up interrupt, use high word bit 17.

enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable

PN Timeout Wake Up interrupt, use high word bit 16.

enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable

Host Access With Non-Correctable Errors interrupt, use high word bit 0.

enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable

FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.

enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable

Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.

enum _flexcan_flags

FlexCAN status flags.

This provides constants for the FlexCAN status flags for use in the FlexCAN functions.

Note

The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.

Values:

enumerator kFLEXCAN_ErrorOverrunFlag

Error Overrun Status.

enumerator kFLEXCAN_FDErrorIntFlag

CAN FD Error Interrupt Flag.

enumerator kFLEXCAN_BusoffDoneIntFlag

Bus Off process completed Interrupt Flag.

enumerator kFLEXCAN_SynchFlag

CAN Synchronization Status.

enumerator kFLEXCAN_TxWarningIntFlag

Tx Warning Interrupt Flag.

enumerator kFLEXCAN_RxWarningIntFlag

Rx Warning Interrupt Flag.

enumerator kFLEXCAN_IdleFlag

FlexCAN In IDLE Status.

enumerator kFLEXCAN_FaultConfinementFlag

FlexCAN Fault Confinement State.

enumerator kFLEXCAN_TransmittingFlag

FlexCAN In Transmission Status.

enumerator kFLEXCAN_ReceivingFlag

FlexCAN In Reception Status.

enumerator kFLEXCAN_BusOffIntFlag

Bus Off Interrupt Flag.

enumerator kFLEXCAN_ErrorIntFlag

CAN Error Interrupt Flag.

enumerator kFLEXCAN_WakeUpIntFlag

Self Wake-Up Interrupt Flag.

enumerator kFLEXCAN_ErrorFlag

enumerator kFLEXCAN_PNMatchIntFlag

PN Matching Event Interrupt Flag.

enumerator kFLEXCAN_PNTimeoutIntFlag

PN Timeout Event Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag

Host Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag

FlexCAN Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_CorrectableErrorIntFlag

Correctable Error Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag

Host Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag

FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_CorrectableErrorOverrunFlag

Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_AllMemoryErrorFlag

All Memory Error Flags.

enum _flexcan_error_flags

FlexCAN error status flags.

The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.

Values:

enumerator kFLEXCAN_FDStuffingError

Stuffing Error.

enumerator kFLEXCAN_FDFormError

Form Error.

enumerator kFLEXCAN_FDCrcError

Cyclic Redundancy Check Error.

enumerator kFLEXCAN_FDBit0Error

Unable to send dominant bit.

enumerator kFLEXCAN_FDBit1Error

Unable to send recessive bit.

enumerator kFLEXCAN_TxErrorWarningFlag

Tx Error Warning Status.

enumerator kFLEXCAN_RxErrorWarningFlag

Rx Error Warning Status.

enumerator kFLEXCAN_StuffingError

Stuffing Error.

enumerator kFLEXCAN_FormError

Form Error.

enumerator kFLEXCAN_CrcError

Cyclic Redundancy Check Error.

enumerator kFLEXCAN_AckError

Received no ACK on transmission.

enumerator kFLEXCAN_Bit0Error

Unable to send dominant bit.

enumerator kFLEXCAN_Bit1Error

Unable to send recessive bit.

FlexCAN Legacy Rx FIFO status flags.

The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.

Values:

enumerator kFLEXCAN_RxFifoOverflowFlag

Rx FIFO overflow flag.

enumerator kFLEXCAN_RxFifoWarningFlag

Rx FIFO almost full flag.

enumerator kFLEXCAN_RxFifoFrameAvlFlag

Frames available in Rx FIFO flag.

enum _flexcan_memory_error_type

FlexCAN Memory Error Type.

Values:

enumerator kFLEXCAN_CorrectableError

The memory error is correctable which means on bit error.

enumerator kFLEXCAN_NonCorrectableError

The memory error is non-correctable which means two bit errors.

enum _flexcan_memory_access_type

FlexCAN Memory Access Type.

Values:

enumerator kFLEXCAN_MoveOutFlexCanAccess

The memory error was detected during move-out FlexCAN access.

enumerator kFLEXCAN_MoveInAccess

The memory error was detected during move-in FlexCAN access.

enumerator kFLEXCAN_TxArbitrationAccess

The memory error was detected during Tx Arbitration FlexCAN access.

enumerator kFLEXCAN_RxMatchingAccess

The memory error was detected during Rx Matching FlexCAN access.

enumerator kFLEXCAN_MoveOutHostAccess

The memory error was detected during Rx Matching Host (CPU) access.

enum _flexcan_byte_error_syndrome

FlexCAN Memory Error Byte Syndrome.

Values:

enumerator kFLEXCAN_NoError

No bit error in this byte.

enumerator kFLEXCAN_ParityBits0Error

Parity bit 0 error in this byte.

enumerator kFLEXCAN_ParityBits1Error

Parity bit 1 error in this byte.

enumerator kFLEXCAN_ParityBits2Error

Parity bit 2 error in this byte.

enumerator kFLEXCAN_ParityBits3Error

Parity bit 3 error in this byte.

enumerator kFLEXCAN_ParityBits4Error

Parity bit 4 error in this byte.

enumerator kFLEXCAN_DataBits0Error

Data bit 0 error in this byte.

enumerator kFLEXCAN_DataBits1Error

Data bit 1 error in this byte.

enumerator kFLEXCAN_DataBits2Error

Data bit 2 error in this byte.

enumerator kFLEXCAN_DataBits3Error

Data bit 3 error in this byte.

enumerator kFLEXCAN_DataBits4Error

Data bit 4 error in this byte.

enumerator kFLEXCAN_DataBits5Error

Data bit 5 error in this byte.

enumerator kFLEXCAN_DataBits6Error

Data bit 6 error in this byte.

enumerator kFLEXCAN_DataBits7Error

Data bit 7 error in this byte.

enumerator kFLEXCAN_AllZeroError

All-zeros non-correctable error in this byte.

enumerator kFLEXCAN_AllOneError

All-ones non-correctable error in this byte.

enumerator kFLEXCAN_NonCorrectableErrors

Non-correctable error in this byte.

enum _flexcan_pn_match_source

FlexCAN Pretended Networking match source selection.

Values:

enumerator kFLEXCAN_PNMatSrcID

Message match with ID filtering.

enumerator kFLEXCAN_PNMatSrcIDAndData

Message match with ID filtering and payload filtering.

enum _flexcan_pn_match_mode

FlexCAN Pretended Networking mode match type.

Values:

enumerator kFLEXCAN_PNMatModeEqual

Match upon ID/Payload contents against an exact target value.

enumerator kFLEXCAN_PNMatModeGreater

Match upon an ID/Payload value greater than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeSmaller

Match upon an ID/Payload value smaller than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeRange

Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit

typedef enum _flexcan_frame_format flexcan_frame_format_t

FlexCAN frame format.

typedef enum _flexcan_frame_type flexcan_frame_type_t

FlexCAN frame type.

typedef enum _flexcan_clock_source flexcan_clock_source_t

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t

FlexCAN wake up source.

typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t

FlexCAN Rx Fifo Filter type.

typedef enum _flexcan_mb_size flexcan_mb_size_t

FlexCAN Message Buffer Payload size.

typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t

FlexCAN Memory Error Type.

typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t

FlexCAN Memory Access Type.

typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t

FlexCAN Memory Error Byte Syndrome.

typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

typedef struct _flexcan_frame flexcan_frame_t

FlexCAN message frame structure.

typedef struct _flexcan_fd_frame flexcan_fd_frame_t

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

typedef struct _flexcan_timing_config flexcan_timing_config_t

FlexCAN protocol timing characteristic configuration structure.

typedef struct _flexcan_config flexcan_config_t

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t

FlexCAN Pretended Networking match source selection.

typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t

FlexCAN Pretended Networking mode match type.

typedef struct _flexcan_pn_config flexcan_pn_config_t

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t

FlexCAN Legacy Rx FIFO configuration structure.

typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t

FlexCAN Message Buffer transfer.

typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t

FlexCAN Rx FIFO transfer.

typedef struct _flexcan_handle flexcan_handle_t

FlexCAN handle structure definition.

typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)

FLEXCAN_WAIT_TIMEOUT

DLC_LENGTH_DECODE(dlc)

FlexCAN frame length helper macro.

FLEXCAN_ID_STD(id)

FlexCAN Frame ID helper macro.

Standard Frame ID helper macro.

FLEXCAN_ID_EXT(id)

Extend Frame ID helper macro.

FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)

FlexCAN Rx Message Buffer Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide)

Extend Rx Message Buffer Mask helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)

FlexCAN Legacy Rx FIFO Mask helper macro.

Standard Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)

Standard Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)

Standard Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id)

Standard Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)

Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id)

Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id)

Standard Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id)

Extend Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id)

Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id)

Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id)

Extend Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)

FlexCAN Rx FIFO Filter helper macro.

Standard Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide)

Standard Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide)

Standard Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id)

Standard Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id)

Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id)

Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)

Standard Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)

Extend Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id)

Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id)

Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id)

Extend Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_PN_STD_MASK(id, rtr)

FlexCAN Pretended Networking ID Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_PN_EXT_MASK(id, rtr)

Extend Rx Message Buffer Mask helper macro.

FLEXCAN_PN_INT_MASK(x)

FlexCAN interrupt/status flag helper macro.

FLEXCAN_PN_INT_UNMASK(x)

FLEXCAN_PN_STATUS_MASK(x)

FLEXCAN_PN_STATUS_UNMASK(x)

FLEXCAN_MECR_INT_MASK(x)

FLEXCAN_MECR_INT_UNMASK(x)

FLEXCAN_MECR_STATUS_MASK(x)

FLEXCAN_MECR_STATUS_UNMASK(x)

FLEXCAN_ERROR_AND_STATUS_INIT_FLAG

FLEXCAN_WAKE_UP_FLAG

FLEXCAN_MEMORY_ERROR_INIT_FLAG

FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG

FlexCAN Enhanced Rx FIFO base address helper macro.

FLEXCAN_CALLBACK(x)

FlexCAN transfer callback function.

The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.

struct _flexcan_memory_error_report_status

#include <fsl_flexcan.h>

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

Public Members

flexcan_memory_error_type_t errorType

The type of memory error that giving rise to the report.

flexcan_memory_access_type_t accessType

The type of memory access that giving rise to the memory error.

uint16_t accessAddress

The address where memory error detected.

uint32_t errorData

The raw data word read from memory with error.

struct _flexcan_frame

#include <fsl_flexcan.h>

FlexCAN message frame structure.

struct _flexcan_fd_frame

#include <fsl_flexcan.h>

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

struct _flexcan_timing_config

#include <fsl_flexcan.h>

FlexCAN protocol timing characteristic configuration structure.

Public Members

uint16_t preDivider

Classic CAN or CAN FD nominal phase bit rate prescaler.

uint8_t rJumpwidth

Classic CAN or CAN FD nominal phase Re-sync Jump Width.

uint8_t phaseSeg1

Classic CAN or CAN FD nominal phase Segment 1.

uint8_t phaseSeg2

Classic CAN or CAN FD nominal phase Segment 2.

uint8_t propSeg

Classic CAN or CAN FD nominal phase Propagation Segment.

uint16_t fpreDivider

CAN FD data phase bit rate prescaler.

uint8_t frJumpwidth

CAN FD data phase Re-sync Jump Width.

uint8_t fphaseSeg1

CAN FD data phase Phase Segment 1.

uint8_t fphaseSeg2

CAN FD data phase Phase Segment 2.

uint8_t fpropSeg

CAN FD data phase Propagation Segment.

struct _flexcan_config

#include <fsl_flexcan.h>

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

Public Members

flexcan_clock_source_t clkSrc

Clock source for FlexCAN Protocol Engine.

flexcan_wake_up_source_t wakeupSrc

Wake up source selection.

uint8_t maxMbNum

The maximum number of Message Buffers used by user.

bool enableLoopBack

Enable or Disable Loop Back Self Test Mode.

bool enableTimerSync

Enable or Disable Timer Synchronization.

bool enableSelfWakeup

Enable or Disable Self Wakeup Mode.

bool enableIndividMask

Enable or Disable Rx Individual Mask and Queue feature.

bool disableSelfReception

Enable or Disable Self Reflection.

bool enableListenOnlyMode

Enable or Disable Listen Only Mode.

bool enableDoze

Enable or Disable Doze Mode.

bool enablePretendedeNetworking

Enable or Disable the Pretended Networking mode.

bool enableMemoryErrorControl

Enable or Disable the memory errors detection and correction mechanism.

bool enableNonCorrectableErrorEnterFreeze

Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.

bool enableTransceiverDelayMeasure

Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.

bool enableRemoteRequestFrameStored

true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.

struct _flexcan_rx_mb_config

#include <fsl_flexcan.h>

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

Public Members

uint32_t id

CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

flexcan_frame_format_t format

CAN Frame Identifier format(Standard of Extend).

flexcan_frame_type_t type

CAN Frame Type(Data or Remote).

struct _flexcan_pn_config

#include <fsl_flexcan.h>

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

Public Members

bool enableTimeout

Enable or Disable timeout event trigger wakeup.

uint16_t timeoutValue

The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.

bool enableMatch

Enable or Disable match event trigger wakeup.

flexcan_pn_match_source_t matchSrc

Selects the match source (ID and/or data match) to trigger wakeup.

uint8_t matchNum

The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.

flexcan_pn_match_mode_t idMatchMode

The ID match type.

flexcan_pn_match_mode_t dataMatchMode

The data match type.

uint32_t idLower

The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.

uint32_t idUpper

The ID target values 2 which used only as the upper limit value in ID match “range

detection” or used to store the ID mask in “equal to”.

uint8_t lengthLower

The lower limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

uint8_t lengthUpper

The upper limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

struct _flexcan_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Legacy Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable

Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.

uint8_t idFilterNum

The FlexCAN Legacy Rx FIFO Filter elements quantity.

flexcan_rx_fifo_filter_type_t idFilterType

The FlexCAN Legacy Rx FIFO Filter type.

flexcan_rx_fifo_priority_t priority

The FlexCAN Legacy Rx FIFO receive priority.

struct _flexcan_mb_transfer

#include <fsl_flexcan.h>

FlexCAN Message Buffer transfer.

Public Members

flexcan_frame_t *frame

The buffer of CAN Message to be transfer.

uint8_t mbIdx

The index of Message buffer used to transfer Message.

struct _flexcan_fifo_transfer

#include <fsl_flexcan.h>

FlexCAN Rx FIFO transfer.

Public Members

flexcan_frame_t *frame

The buffer of CAN Message to be received from Legacy Rx FIFO.

size_t frameNum

Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO.

struct _flexcan_handle

#include <fsl_flexcan.h>

FlexCAN handle structure.

Public Members

flexcan_transfer_callback_t callback

Callback function.

void *userData

FlexCAN callback function parameter.

flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]

The buffer for received CAN data from Message Buffers.

flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]

The buffer for received CAN FD data from Message Buffers.

flexcan_frame_t *volatile rxFifoFrameBuf

The buffer for received CAN data from Legacy Rx FIFO.

size_t rxFifoFrameNum

The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO.

size_t rxFifoTransferTotalNum

Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO.

volatile uint8_t mbState[CAN_WORD1_COUNT]

Message Buffer transfer state.

volatile uint8_t rxFifoState

Rx FIFO transfer state.

volatile uint32_t timestamp[CAN_WORD1_COUNT]

Mailbox transfer timestamp.

struct byteStatus

Public Members

bool byteIsRead

The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.

struct __unnamed33__

Public Members

uint32_t timestamp

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length

CAN frame data length in bytes (Range: 0~8).

uint32_t type

CAN Frame Type(DATA or REMOTE).

uint32_t format

CAN Frame Identifier(STD or EXT format).

uint32_t __pad0__

Reserved.

uint32_t idhit

CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).

struct __unnamed35__

Public Members

uint32_t id

CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__

Reserved.

union __unnamed37__

Public Members

struct _flexcan_frame

struct _flexcan_frame

struct __unnamed39__

Public Members

uint32_t dataWord0

CAN Frame payload word0.

uint32_t dataWord1

CAN Frame payload word1.

struct __unnamed41__

Public Members

uint8_t dataByte3

CAN Frame payload byte3.

uint8_t dataByte2

CAN Frame payload byte2.

uint8_t dataByte1

CAN Frame payload byte1.

uint8_t dataByte0

CAN Frame payload byte0.

uint8_t dataByte7

CAN Frame payload byte7.

uint8_t dataByte6

CAN Frame payload byte6.

uint8_t dataByte5

CAN Frame payload byte5.

uint8_t dataByte4

CAN Frame payload byte4.

struct __unnamed43__

Public Members

uint32_t timestamp

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length

CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t type

CAN Frame Type(DATA or REMOTE).

uint32_t format

CAN Frame Identifier(STD or EXT format).

uint32_t srr

Substitute Remote request.

uint32_t esi

Error State Indicator.

uint32_t brs

Bit Rate Switch.

uint32_t edl

Extended Data Length.

struct __unnamed45__

Public Members

uint32_t id

CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__

Reserved.

union __unnamed47__

Public Members

struct _flexcan_fd_frame

struct _flexcan_fd_frame

struct __unnamed49__

Public Members

uint32_t dataWord[16]

CAN FD Frame payload, 16 double word maximum.

struct __unnamed51__

Public Members

uint8_t dataByte3

CAN Frame payload byte3.

uint8_t dataByte2

CAN Frame payload byte2.

uint8_t dataByte1

CAN Frame payload byte1.

uint8_t dataByte0

CAN Frame payload byte0.

uint8_t dataByte7

CAN Frame payload byte7.

uint8_t dataByte6

CAN Frame payload byte6.

uint8_t dataByte5

CAN Frame payload byte5.

uint8_t dataByte4

CAN Frame payload byte4.

union __unnamed53__

Public Members

struct _flexcan_config

struct _flexcan_config

struct __unnamed55__

Public Members

uint32_t baudRate

FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t baudRateFD

FlexCAN FD bit rate in bps, for CANFD data phase.

struct __unnamed57__

Public Members

uint32_t bitRate

FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t bitRateFD

FlexCAN FD bit rate in bps, for CANFD data phase.

union __unnamed59__

Public Members

struct _flexcan_pn_config

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

struct _flexcan_pn_config

struct __unnamed63__

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

Public Members

uint32_t lowerWord0

CAN Frame payload word0.

uint32_t lowerWord1

CAN Frame payload word1.

struct __unnamed65__

Public Members

uint8_t lowerByte3

CAN Frame payload byte3.

uint8_t lowerByte2

CAN Frame payload byte2.

uint8_t lowerByte1

CAN Frame payload byte1.

uint8_t lowerByte0

CAN Frame payload byte0.

uint8_t lowerByte7

CAN Frame payload byte7.

uint8_t lowerByte6

CAN Frame payload byte6.

uint8_t lowerByte5

CAN Frame payload byte5.

uint8_t lowerByte4

CAN Frame payload byte4.

union __unnamed61__

Public Members

struct _flexcan_pn_config

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

struct _flexcan_pn_config

struct __unnamed67__

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

Public Members

uint32_t upperWord0

CAN Frame payload word0.

uint32_t upperWord1

CAN Frame payload word1.

struct __unnamed69__

Public Members

uint8_t upperByte3

CAN Frame payload byte3.

uint8_t upperByte2

CAN Frame payload byte2.

uint8_t upperByte1

CAN Frame payload byte1.

uint8_t upperByte0

CAN Frame payload byte0.

uint8_t upperByte7

CAN Frame payload byte7.

uint8_t upperByte6

CAN Frame payload byte6.

uint8_t upperByte5

CAN Frame payload byte5.

uint8_t upperByte4

CAN Frame payload byte4.

FlexCAN eDMA Driver

void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)

Initializes the FlexCAN handle, which is used in transactional functions.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• callback – The callback function.

• userData – The parameter of the callback function.

• rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.

void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)

Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.

This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

• pEdmaConfig – The user configuration structure of type edma_transfer_t.

status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)

Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.

This function to Update edma transfer confiugration and Start eDMA transfer

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• pEdmaConfig – The user configuration structure of type edma_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN Message from the Legacy Rx FIFO using eDMA.

This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)

Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

FSL_FLEXCAN_EDMA_DRIVER_VERSION

FlexCAN EDMA driver version.

typedef struct _flexcan_edma_handle flexcan_edma_handle_t

typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData)

FlexCAN transfer callback function.

struct _flexcan_edma_handle

#include <fsl_flexcan_edma.h>

FlexCAN eDMA handle.

Public Members

flexcan_edma_transfer_callback_t callback

Callback function.

void *userData

FlexCAN callback function parameter.

edma_handle_t *rxFifoEdmaHandle

The EDMA handler for Rx FIFO.

volatile uint8_t rxFifoState

Rx FIFO transfer state.

size_t frameNum

The number of messages that need to be received.

FlexIO: FlexIO Driver

FlexIO Driver

void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)

Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().

Example:

flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);

Parameters:

• userConfig – pointer to flexio_config_t structure

void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)

Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().

Example

flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);

Parameters:

• base – FlexIO peripheral base address

• userConfig – pointer to flexio_config_t structure

void FLEXIO_Deinit(FLEXIO_Type *base)

Gates the FlexIO clock. Call this API to stop the FlexIO clock.

Note

After calling this API, call the FLEXO_Init to use the FlexIO module.

Parameters:

• base – FlexIO peripheral base address

uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)

Get instance number for FLEXIO module.

Parameters:

• base – FLEXIO peripheral base address.

void FLEXIO_Reset(FLEXIO_Type *base)

Resets the FlexIO module.

Parameters:

• base – FlexIO peripheral base address

static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)

Enables the FlexIO module operation.

Parameters:

• base – FlexIO peripheral base address

• enable – true to enable, false to disable.

static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)

Reads the input data on each of the FlexIO pins.

Parameters:

• base – FlexIO peripheral base address

Returns:

FlexIO pin input data

static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)

Gets the current state pointer for state mode use.

Parameters:

• base – FlexIO peripheral base address

Returns:

current State pointer

void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)

Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.

Example

flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);

Parameters:

• base – FlexIO peripheral base address

• index – Shifter index

• shifterConfig – Pointer to flexio_shifter_config_t structure

void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)

Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.

Example

flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);

Parameters:

• base – FlexIO peripheral base address

• index – Timer index

• timerConfig – Pointer to the flexio_timer_config_t structure

static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)

This function set the value of the prescaler on flexio channels.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

• index – Timer index

• clocksource – Set clock value

static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)

Gets the shifter status flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Shifter status flags

static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter status flags.

Note

For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)

Gets the shifter error flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Shifter error flags

static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter error flags.

Note

For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)

Gets the timer status flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Timer status flags

static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the timer status flags.

Note

For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)

Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.

Note

For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

• enable – True to enable, false to disable.

uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)

Gets the shifter buffer address for the DMA transfer usage.

Parameters:

• base – FlexIO peripheral base address

• type – Shifter type of flexio_shifter_buffer_type_t

• index – Shifter index

Returns:

Corresponding shifter buffer index

status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)

Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

• handle – Pointer to the handler for FlexIO simulated peripheral.

• isr – FlexIO simulated peripheral interrupt handler.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_UnregisterHandleIRQ(void *base)

Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 0.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 1.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple FLEXIO pins.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the FLEXIO pins to the logic 1 or 0.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

• output – FLEXIO pin output logic level.

  • 0: corresponding pin output low-logic level.

  • 1: corresponding pin output high-logic level.

static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)

Enables the FLEXIO output pin function.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)

Reads the current input value of the FLEXIO pin.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

Return values:

FLEXIO – port input value

• 0: corresponding pin input low-logic level.

• 1: corresponding pin input high-logic level.

static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)

Gets the FLEXIO input pin status.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

Return values:

FLEXIO – port input status

• 0: corresponding pin input capture no status.

• 1: corresponding pin input capture rising or falling edge.

static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)

Clears the multiple FLEXIO input pins status.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

FSL_FLEXIO_DRIVER_VERSION

FlexIO driver version.

enum _flexio_timer_trigger_polarity

Define time of timer trigger polarity.

Values:

enumerator kFLEXIO_TimerTriggerPolarityActiveHigh

Active high.

enumerator kFLEXIO_TimerTriggerPolarityActiveLow

Active low.

enum _flexio_timer_trigger_source

Define type of timer trigger source.

Values:

enumerator kFLEXIO_TimerTriggerSourceExternal

External trigger selected.

enumerator kFLEXIO_TimerTriggerSourceInternal

Internal trigger selected.

enum _flexio_pin_config

Define type of timer/shifter pin configuration.

Values:

enumerator kFLEXIO_PinConfigOutputDisabled

Pin output disabled.

enumerator kFLEXIO_PinConfigOpenDrainOrBidirection

Pin open drain or bidirectional output enable.

enumerator kFLEXIO_PinConfigBidirectionOutputData

Pin bidirectional output data.

enumerator kFLEXIO_PinConfigOutput

Pin output.

enum _flexio_pin_polarity

Definition of pin polarity.

Values:

enumerator kFLEXIO_PinActiveHigh

Active high.

enumerator kFLEXIO_PinActiveLow

Active low.

enum _flexio_timer_mode

Define type of timer work mode.

Values:

enumerator kFLEXIO_TimerModeDisabled

Timer Disabled.

enumerator kFLEXIO_TimerModeDual8BitBaudBit

Dual 8-bit counters baud/bit mode.

enumerator kFLEXIO_TimerModeDual8BitPWM

Dual 8-bit counters PWM mode.

enumerator kFLEXIO_TimerModeSingle16Bit

Single 16-bit counter mode.

enum _flexio_timer_output

Define type of timer initial output or timer reset condition.

Values:

enumerator kFLEXIO_TimerOutputOneNotAffectedByReset

Logic one when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset

Logic zero when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputOneAffectedByReset

Logic one when enabled and on timer reset.

enumerator kFLEXIO_TimerOutputZeroAffectedByReset

Logic zero when enabled and on timer reset.

enum _flexio_timer_decrement_source

Define type of timer decrement.

Values:

enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput

Decrement counter on FlexIO clock, Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

enum _flexio_timer_reset_condition

Define type of timer reset condition.

Values:

enumerator kFLEXIO_TimerResetNever

Timer never reset.

enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput

Timer reset on Timer Pin equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput

Timer reset on Timer Trigger equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge

Timer reset on Timer Pin rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge

Timer reset on Trigger rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge

Timer reset on Trigger rising or falling edge.

enum _flexio_timer_disable_condition

Define type of timer disable condition.

Values:

enumerator kFLEXIO_TimerDisableNever

Timer never disabled.

enumerator kFLEXIO_TimerDisableOnPreTimerDisable

Timer disabled on Timer N-1 disable.

enumerator kFLEXIO_TimerDisableOnTimerCompare

Timer disabled on Timer compare.

enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow

Timer disabled on Timer compare and Trigger Low.

enumerator kFLEXIO_TimerDisableOnPinBothEdge

Timer disabled on Pin rising or falling edge.

enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh

Timer disabled on Pin rising or falling edge provided Trigger is high.

enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge

Timer disabled on Trigger falling edge.

enum _flexio_timer_enable_condition

Define type of timer enable condition.

Values:

enumerator kFLEXIO_TimerEnabledAlways

Timer always enabled.

enumerator kFLEXIO_TimerEnableOnPrevTimerEnable

Timer enabled on Timer N-1 enable.

enumerator kFLEXIO_TimerEnableOnTriggerHigh

Timer enabled on Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh

Timer enabled on Trigger high and Pin high.

enumerator kFLEXIO_TimerEnableOnPinRisingEdge

Timer enabled on Pin rising edge.

enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh

Timer enabled on Pin rising edge and Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge

Timer enabled on Trigger rising edge.

enumerator kFLEXIO_TimerEnableOnTriggerBothEdge

Timer enabled on Trigger rising or falling edge.

enum _flexio_timer_stop_bit_condition

Define type of timer stop bit generate condition.

Values:

enumerator kFLEXIO_TimerStopBitDisabled

Stop bit disabled.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare

Stop bit is enabled on timer compare.

enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable

Stop bit is enabled on timer disable.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable

Stop bit is enabled on timer compare and timer disable.

enum _flexio_timer_start_bit_condition

Define type of timer start bit generate condition.

Values:

enumerator kFLEXIO_TimerStartBitDisabled

Start bit disabled.

enumerator kFLEXIO_TimerStartBitEnabled

Start bit enabled.

enum _flexio_timer_output_state

FlexIO as PWM channel output state.

Values:

enumerator kFLEXIO_PwmLow

The output state of PWM channel is low

enumerator kFLEXIO_PwmHigh

The output state of PWM channel is high

enum _flexio_shifter_timer_polarity

Define type of timer polarity for shifter control.

Values:

enumerator kFLEXIO_ShifterTimerPolarityOnPositive

Shift on positive edge of shift clock.

enumerator kFLEXIO_ShifterTimerPolarityOnNegitive

Shift on negative edge of shift clock.

enum _flexio_shifter_mode

Define type of shifter working mode.

Values:

enumerator kFLEXIO_ShifterDisabled

Shifter is disabled.

enumerator kFLEXIO_ShifterModeReceive

Receive mode.

enumerator kFLEXIO_ShifterModeTransmit

Transmit mode.

enumerator kFLEXIO_ShifterModeMatchStore

Match store mode.

enumerator kFLEXIO_ShifterModeMatchContinuous

Match continuous mode.

enumerator kFLEXIO_ShifterModeState

SHIFTBUF contents are used for storing programmable state attributes.

enumerator kFLEXIO_ShifterModeLogic

SHIFTBUF contents are used for implementing programmable logic look up table.

enum _flexio_shifter_input_source

Define type of shifter input source.

Values:

enumerator kFLEXIO_ShifterInputFromPin

Shifter input from pin.

enumerator kFLEXIO_ShifterInputFromNextShifterOutput

Shifter input from Shifter N+1.

enum _flexio_shifter_stop_bit

Define of STOP bit configuration.

Values:

enumerator kFLEXIO_ShifterStopBitDisable

Disable shifter stop bit.

enumerator kFLEXIO_ShifterStopBitLow

Set shifter stop bit to logic low level.

enumerator kFLEXIO_ShifterStopBitHigh

Set shifter stop bit to logic high level.

enum _flexio_shifter_start_bit

Define type of START bit configuration.

Values:

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable

Disable shifter start bit, transmitter loads data on enable.

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift

Disable shifter start bit, transmitter loads data on first shift.

enumerator kFLEXIO_ShifterStartBitLow

Set shifter start bit to logic low level.

enumerator kFLEXIO_ShifterStartBitHigh

Set shifter start bit to logic high level.

enum _flexio_shifter_buffer_type

Define FlexIO shifter buffer type.

Values:

enumerator kFLEXIO_ShifterBuffer

Shifter Buffer N Register.

enumerator kFLEXIO_ShifterBufferBitSwapped

Shifter Buffer N Bit Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferByteSwapped

Shifter Buffer N Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferBitByteSwapped

Shifter Buffer N Bit Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleByteSwapped

Shifter Buffer N Nibble Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferHalfWordSwapped

Shifter Buffer N Half Word Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleSwapped

Shifter Buffer N Nibble Swapped Register.

enum _flexio_gpio_direction

FLEXIO gpio direction definition.

Values:

enumerator kFLEXIO_DigitalInput

Set current pin as digital input

enumerator kFLEXIO_DigitalOutput

Set current pin as digital output

enum _flexio_pin_input_config

FLEXIO gpio input config.

Values:

enumerator kFLEXIO_InputInterruptDisabled

Interrupt request is disabled.

enumerator kFLEXIO_InputInterruptEnable

Interrupt request is enable.

enumerator kFLEXIO_FlagRisingEdgeEnable

Input pin flag on rising edge.

enumerator kFLEXIO_FlagFallingEdgeEnable

Input pin flag on falling edge.

typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t

Define time of timer trigger polarity.

typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t

Define type of timer trigger source.

typedef enum _flexio_pin_config flexio_pin_config_t

Define type of timer/shifter pin configuration.

typedef enum _flexio_pin_polarity flexio_pin_polarity_t

Definition of pin polarity.

typedef enum _flexio_timer_mode flexio_timer_mode_t

Define type of timer work mode.

typedef enum _flexio_timer_output flexio_timer_output_t

Define type of timer initial output or timer reset condition.

typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t

Define type of timer decrement.

typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t

Define type of timer reset condition.

typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t

Define type of timer disable condition.

typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t

Define type of timer enable condition.

typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t

Define type of timer stop bit generate condition.

typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t

Define type of timer start bit generate condition.

typedef enum _flexio_timer_output_state flexio_timer_output_state_t

FlexIO as PWM channel output state.

typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t

Define type of timer polarity for shifter control.

typedef enum _flexio_shifter_mode flexio_shifter_mode_t

Define type of shifter working mode.

typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t

Define type of shifter input source.

typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t

Define of STOP bit configuration.

typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t

Define type of START bit configuration.

typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t

Define FlexIO shifter buffer type.

typedef struct _flexio_config_ flexio_config_t

Define FlexIO user configuration structure.

typedef struct _flexio_timer_config flexio_timer_config_t

Define FlexIO timer configuration structure.

typedef struct _flexio_shifter_config flexio_shifter_config_t

Define FlexIO shifter configuration structure.

typedef enum _flexio_gpio_direction flexio_gpio_direction_t

FLEXIO gpio direction definition.

typedef enum _flexio_pin_input_config flexio_pin_input_config_t

FLEXIO gpio input config.

typedef struct _flexio_gpio_config flexio_gpio_config_t

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

typedef void (*flexio_isr_t)(void *base, void *handle)

typedef for FlexIO simulated driver interrupt handler.

FLEXIO_Type *const s_flexioBases[]

Pointers to flexio bases for each instance.

const clock_ip_name_t s_flexioClocks[]

Pointers to flexio clocks for each instance.

void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)

Configure a FLEXIO pin used by the board.

To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
}
Define a digital output pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalOutput,
  0U,
  0U
}

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

• config – FLEXIO pin configuration pointer.

FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)

Calculate FlexIO timer trigger.

FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)

FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)

struct _flexio_config_

#include <fsl_flexio.h>

Define FlexIO user configuration structure.

Public Members

bool enableFlexio

Enable/disable FlexIO module

bool enableInDoze

Enable/disable FlexIO operation in doze mode

bool enableInDebug

Enable/disable FlexIO operation in debug mode

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_timer_config

#include <fsl_flexio.h>

Define FlexIO timer configuration structure.

Public Members

uint32_t triggerSelect

The internal trigger selection number using MACROs.

flexio_timer_trigger_polarity_t triggerPolarity

Trigger Polarity.

flexio_timer_trigger_source_t triggerSource

Trigger Source, internal (see ‘trgsel’) or external.

flexio_pin_config_t pinConfig

Timer Pin Configuration.

uint32_t pinSelect

Timer Pin number Select.

flexio_pin_polarity_t pinPolarity

Timer Pin Polarity.

flexio_timer_mode_t timerMode

Timer work Mode.

flexio_timer_output_t timerOutput

Configures the initial state of the Timer Output and whether it is affected by the Timer reset.

flexio_timer_decrement_source_t timerDecrement

Configures the source of the Timer decrement and the source of the Shift clock.

flexio_timer_reset_condition_t timerReset

Configures the condition that causes the timer counter (and optionally the timer output) to be reset.

flexio_timer_disable_condition_t timerDisable

Configures the condition that causes the Timer to be disabled and stop decrementing.

flexio_timer_enable_condition_t timerEnable

Configures the condition that causes the Timer to be enabled and start decrementing.

flexio_timer_stop_bit_condition_t timerStop

Timer STOP Bit generation.

flexio_timer_start_bit_condition_t timerStart

Timer STRAT Bit generation.

uint32_t timerCompare

Value for Timer Compare N Register.

struct _flexio_shifter_config

#include <fsl_flexio.h>

Define FlexIO shifter configuration structure.

Public Members

uint32_t timerSelect

Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.

flexio_shifter_timer_polarity_t timerPolarity

Timer Polarity.

flexio_pin_config_t pinConfig

Shifter Pin Configuration.

uint32_t pinSelect

Shifter Pin number Select.

flexio_pin_polarity_t pinPolarity

Shifter Pin Polarity.

flexio_shifter_mode_t shifterMode

Configures the mode of the Shifter.

uint32_t parallelWidth

Configures the parallel width when using parallel mode.

flexio_shifter_input_source_t inputSource

Selects the input source for the shifter.

flexio_shifter_stop_bit_t shifterStop

Shifter STOP bit.

flexio_shifter_start_bit_t shifterStart

Shifter START bit.

struct _flexio_gpio_config

#include <fsl_flexio.h>

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

Public Members

flexio_gpio_direction_t pinDirection

FLEXIO pin direction, input or output

uint8_t outputLogic

Set a default output logic, which has no use in input

uint8_t inputConfig

Set an input config

FlexIO eDMA I2S Driver

void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S eDMA handle.

This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer.

• callback – FlexIO I2S eDMA callback function called while finished a block.

• userData – User parameter for callback.

• dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S Rx eDMA handle.

This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer.

• callback – FlexIO I2S eDMA callback function called while finished a block.

• userData – User parameter for callback.

• dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S Tx audio format.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer

• format – Pointer to FlexIO I2S audio data format structure.

• srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.

status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S transfer using DMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a FlexIO I2S eDMA send successfully.

• kStatus_InvalidArgument – The input arguments is invalid.

• kStatus_TxBusy – FlexIO I2S is busy sending data.

status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S receive using eDMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a FlexIO I2S eDMA receive successfully.

• kStatus_InvalidArgument – The input arguments is invalid.

• kStatus_RxBusy – FlexIO I2S is busy receiving data.

void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S transfer using eDMA.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S receive using eDMA.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• count – Bytes sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Get the remaining bytes to be received.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• count – Bytes received.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION

FlexIO I2S EDMA driver version 2.1.8.

typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t

typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData)

FlexIO I2S eDMA transfer callback function for finish and error.

struct _flexio_i2s_edma_handle

#include <fsl_flexio_i2s_edma.h>

FlexIO I2S DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle

DMA handler for FlexIO I2S send

uint8_t bytesPerFrame

Bytes in a frame

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint32_t state

Internal state for FlexIO I2S eDMA transfer

flexio_i2s_edma_callback_t callback

Callback for users while transfer finish or error occurred

void *userData

User callback parameter

edma_tcd_t tcd[(4U) + 1U]

TCD pool for eDMA transfer.

flexio_i2s_transfer_t queue[(4U)]

Transfer queue storing queued transfer.

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

FlexIO eDMA SPI Driver

status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI master eDMA handle.

This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.

• callback – SPI callback, NULL means no callback.

• userData – callback function parameter.

• txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

• rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.

• xfer – Pointer to FlexIO SPI transfer structure.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI master eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

• count – Number of bytes transferred so far by the non-blocking transaction.

static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI slave eDMA handle.

This function initializes the FlexIO SPI slave eDMA handle.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

• callback – SPI callback, NULL means no callback.

• userData – callback function parameter.

• txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

• rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

• xfer – Pointer to FlexIO SPI transfer structure.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

• count – Number of bytes transferred so far by the non-blocking transaction.

FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION

FlexIO SPI EDMA driver version.

typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t

typedef for flexio_spi_master_edma_handle_t in advance.

typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t

Slave handle is the same with master handle.

typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData)

FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData)

FlexIO SPI slave callback for finished transmit.

struct _flexio_spi_master_edma_handle

#include <fsl_flexio_spi_edma.h>

FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.

Public Members

size_t transferSize

Total bytes to be transferred.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

bool txInProgress

Send transfer in progress

bool rxInProgress

Receive transfer in progress

edma_handle_t *txHandle

DMA handler for SPI send

edma_handle_t *rxHandle

DMA handler for SPI receive

flexio_spi_master_edma_transfer_callback_t callback

Callback for SPI DMA transfer

void *userData

User Data for SPI DMA callback

FlexIO eDMA UART Driver

status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the UART handle which is used in transactional functions.

Parameters:

• base – Pointer to FLEXIO_UART_Type.

• handle – Pointer to flexio_uart_edma_handle_t structure.

• callback – The callback function.

• userData – The parameter of the callback function.

• rxEdmaHandle – User requested DMA handle for RX DMA transfer.

• txEdmaHandle – User requested DMA handle for TX DMA transfer.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – UART handle pointer.

• xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.

status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_UART_RxBusy – Previous transfer on going.

void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the sent data which using eDMA.

This function aborts sent data which using eDMA.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the receive data which using eDMA.

This function aborts the receive data which using eDMA.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes sent out.

This function gets the number of bytes sent out.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• count – Number of bytes sent so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• count – Number of bytes received so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

FSL_FLEXIO_UART_EDMA_DRIVER_VERSION

FlexIO UART EDMA driver version.

typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t

typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData)

UART transfer callback function.

struct _flexio_uart_edma_handle

#include <fsl_flexio_uart_edma.h>

UART eDMA handle.

Public Members

flexio_uart_edma_transfer_callback_t callback

Callback function.

void *userData

UART callback function parameter.

size_t txDataSizeAll

Total bytes to be sent.

size_t rxDataSizeAll

Total bytes to be received.

edma_handle_t *txEdmaHandle

The eDMA TX channel used.

edma_handle_t *rxEdmaHandle

The eDMA RX channel used.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

FlexIO I2C Master Driver

status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)

Make sure the bus isn’t already pulled down.

Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure..

Return values:

• kStatus_Success –

• kStatus_FLEXIO_I2C_Busy –

status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.

Example

FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• masterConfig – Pointer to flexio_i2c_master_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

Return values:

• kStatus_Success – Initialization successful

• kStatus_InvalidArgument – The source clock exceed upper range limitation

void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)

De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.

Parameters:

• base – pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().

Example:

flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);

Parameters:

• masterConfig – Pointer to flexio_i2c_master_config_t structure.

static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)

Enables/disables the FlexIO module operation.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• enable – Pass true to enable module, false does not have any effect.

uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)

Gets the FlexIO I2C master status flags.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

Returns:

Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.

void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)

Clears the FlexIO I2C master status flags.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Status flag. The parameter can be any combination of the following values:

  • kFLEXIO_I2C_RxFullFlag

  • kFLEXIO_I2C_ReceiveNakFlag

void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Enables the FlexIO i2c master interrupt requests.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Interrupt source. Currently only one interrupt request source:

  • kFLEXIO_I2C_TransferCompleteInterruptEnable

void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Disables the FlexIO I2C master interrupt requests.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Interrupt source.

void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the FlexIO I2C master transfer baudrate.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• baudRate_Bps – the baud rate value in HZ

• srcClock_Hz – source clock in HZ

void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)

Sends START + 7-bit address to the bus.

Note

This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• address – 7-bit address.

• direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:

  • kFLEXIO_I2C_Write: Transmit

  • kFLEXIO_I2C_Read: Receive

void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)

Sends the stop signal on the bus.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)

Sends the repeated start signal on the bus.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)

Sends the stop signal when transfer is still on-going.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)

Configures the sent ACK/NAK for the following byte.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• enable – True to configure send ACK, false configure to send NAK.

status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)

Sets the number of bytes to be transferred from a start signal to a stop signal.

Note

Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• count – Number of bytes need to be transferred from a start signal to a re-start/stop signal

Return values:

• kStatus_Success – Successfully configured the count.

• kStatus_InvalidArgument – Input argument is invalid.

static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)

Writes one byte of data to the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• data – a byte of data.

static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)

Reads one byte of data from the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

Returns:

data byte read.

status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)

Sends a buffer of data in bytes.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• txBuff – The data bytes to send.

• txSize – The number of data bytes to send.

Return values:

• kStatus_Success – Successfully write data.

• kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• rxBuff – The buffer to store the received bytes.

• rxSize – The number of data bytes to be received.

Return values:

• kStatus_Success – Successfully read data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to receiving NAK.

Parameters:

• base – pointer to FLEXIO_I2C_Type structure.

• xfer – pointer to flexio_i2c_master_transfer_t structure.

Returns:

status of status_t.

status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.

• callback – Pointer to user callback function.

• userData – User param passed to the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.

status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

• xfer – pointer to flexio_i2c_master_transfer_t structure

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.

status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

• kStatus_Success – Successfully return the count.

void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)

Master interrupt handler.

Parameters:

• i2cType – Pointer to FLEXIO_I2C_Type structure

• i2cHandle – Pointer to flexio_i2c_master_transfer_t structure

FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION

FlexIO I2C transfer status.

Values:

enumerator kStatus_FLEXIO_I2C_Busy

I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Idle

I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Nak

NAK received during transfer.

enumerator kStatus_FLEXIO_I2C_Timeout

Timeout polling status flags.

enum _flexio_i2c_master_interrupt

Define FlexIO I2C master interrupt mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyInterruptEnable

Tx buffer empty interrupt enable.

enumerator kFLEXIO_I2C_RxFullInterruptEnable

Rx buffer full interrupt enable.

enum _flexio_i2c_master_status_flags

Define FlexIO I2C master status mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyFlag

Tx shifter empty flag.

enumerator kFLEXIO_I2C_RxFullFlag

Rx shifter full/Transfer complete flag.

enumerator kFLEXIO_I2C_ReceiveNakFlag

Receive NAK flag.

enum _flexio_i2c_direction

Direction of master transfer.

Values:

enumerator kFLEXIO_I2C_Write

Master send to slave.

enumerator kFLEXIO_I2C_Read

Master receive from slave.

typedef enum _flexio_i2c_direction flexio_i2c_direction_t

Direction of master transfer.

typedef struct _flexio_i2c_type FLEXIO_I2C_Type

Define FlexIO I2C master access structure typedef.

typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t

Define FlexIO I2C master user configuration structure.

typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t

Define FlexIO I2C master transfer structure.

typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t

FlexIO I2C master handle typedef.

typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData)

FlexIO I2C master transfer callback typedef.

I2C_RETRY_TIMES

Retry times for waiting flag.

struct _flexio_i2c_type

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t SDAPinIndex

Pin select for I2C SDA.

uint8_t SCLPinIndex

Pin select for I2C SCL.

uint8_t shifterIndex[2]

Shifter index used in FlexIO I2C.

uint8_t timerIndex[3]

Timer index used in FlexIO I2C.

uint32_t baudrate

Master transfer baudrate, used to calculate delay time.

struct _flexio_i2c_master_config

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master user configuration structure.

Public Members

bool enableMaster

Enables the FlexIO I2C peripheral at initialization time.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

struct _flexio_i2c_master_transfer

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master transfer structure.

Public Members

uint32_t flags

Transfer flag which controls the transfer, reserved for FlexIO I2C.

uint8_t slaveAddress

7-bit slave address.

flexio_i2c_direction_t direction

Transfer direction, read or write.

uint32_t subaddress

Sub address. Transferred MSB first.

uint8_t subaddressSize

Size of command buffer.

uint8_t volatile *data

Transfer buffer.

volatile size_t dataSize

Transfer size.

struct _flexio_i2c_master_handle

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master handle structure.

Public Members

flexio_i2c_master_transfer_t transfer

FlexIO I2C master transfer copy.

size_t transferSize

Total bytes to be transferred.

uint8_t state

Transfer state maintained during transfer.

flexio_i2c_master_transfer_callback_t completionCallback

Callback function called at transfer event. Callback function called at transfer event.

void *userData

Callback parameter passed to callback function.

bool needRestart

Whether master needs to send re-start signal.

FlexIO I2S Driver

void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)

Initializes the FlexIO I2S.

This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.

Parameters:

• base – FlexIO I2S base pointer

• config – FlexIO I2S configure structure.

void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)

Sets the FlexIO I2S configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().

Parameters:

• config – pointer to master configuration structure

void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)

De-initializes the FlexIO I2S.

Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.

Parameters:

• base – FlexIO I2S base pointer

static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S module operation.

Parameters:

• base – Pointer to FLEXIO_I2S_Type

• enable – True to enable, false dose not have any effect.

uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S status flags.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.

void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Enables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• mask – interrupt source

void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Disables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – pointer to FLEXIO_I2S_Type structure

• mask – interrupt source

static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Tx DMA requests.

Parameters:

• base – FlexIO I2S base pointer

• enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Rx DMA requests.

Parameters:

• base – FlexIO I2S base pointer

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S send data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s send data register address.

static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S receive data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s receive data register address.

void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format in master mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• format – Pointer to FlexIO I2S audio data format structure.

• srcClock_Hz – I2S master clock source frequency in Hz.

void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)

Configures the FlexIO I2S audio format in slave mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• format – Pointer to FlexIO I2S audio data format structure.

status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)

Sends data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

• base – FlexIO I2S base pointer.

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• txData – Pointer to the data to be written.

• size – Bytes to be written.

Return values:

• kStatus_Success – Successfully write data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)

Writes data into a data register.

Parameters:

• base – FlexIO I2S base pointer.

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• data – Data to be written.

status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)

Receives a piece of data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

• base – FlexIO I2S base pointer

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• rxData – Pointer to the data to be read.

• size – Bytes to be read.

Return values:

• kStatus_Success – Successfully read data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)

Reads a data from the data register.

Parameters:

• base – FlexIO I2S base pointer

Returns:

Data read from data register.

void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.

• callback – FlexIO I2S callback function, which is called while finished a block.

• userData – User parameter for the FlexIO I2S callback.

void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format.

Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – FlexIO I2S handle pointer.

• format – Pointer to audio data format structure.

• srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.

void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S receive handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.

• callback – FlexIO I2S callback function, which is called while finished a block.

• userData – User parameter for the FlexIO I2S callback.

status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

• kStatus_Success – Successfully start the data receive.

• kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current send.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current receive.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• count – Bytes sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be received.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• count – Bytes recieved.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

Returns:

count Bytes received.

void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)

Tx interrupt handler.

Parameters:

• i2sBase – Pointer to FLEXIO_I2S_Type structure.

• i2sHandle – Pointer to flexio_i2s_handle_t structure

void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)

Rx interrupt handler.

Parameters:

• i2sBase – Pointer to FLEXIO_I2S_Type structure.

• i2sHandle – Pointer to flexio_i2s_handle_t structure.

FSL_FLEXIO_I2S_DRIVER_VERSION

FlexIO I2S driver version 2.2.0.

FlexIO I2S transfer status.

Values:

enumerator kStatus_FLEXIO_I2S_Idle

FlexIO I2S is in idle state

enumerator kStatus_FLEXIO_I2S_TxBusy

FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_RxBusy

FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_Error

FlexIO I2S error occurred

enumerator kStatus_FLEXIO_I2S_QueueFull

FlexIO I2S transfer queue is full.

enumerator kStatus_FLEXIO_I2S_Timeout

FlexIO I2S timeout polling status flags.

enum _flexio_i2s_master_slave

Master or slave mode.

Values:

enumerator kFLEXIO_I2S_Master

Master mode

enumerator kFLEXIO_I2S_Slave

Slave mode

_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable

Receive buffer full interrupt enable.

_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_I2S_RxDataRegFullFlag

Receive buffer full flag.

enum _flexio_i2s_sample_rate

Audio sample rate.

Values:

enumerator kFLEXIO_I2S_SampleRate8KHz

Sample rate 8000Hz

enumerator kFLEXIO_I2S_SampleRate11025Hz

Sample rate 11025Hz

enumerator kFLEXIO_I2S_SampleRate12KHz

Sample rate 12000Hz

enumerator kFLEXIO_I2S_SampleRate16KHz

Sample rate 16000Hz

enumerator kFLEXIO_I2S_SampleRate22050Hz

Sample rate 22050Hz

enumerator kFLEXIO_I2S_SampleRate24KHz

Sample rate 24000Hz

enumerator kFLEXIO_I2S_SampleRate32KHz

Sample rate 32000Hz

enumerator kFLEXIO_I2S_SampleRate44100Hz

Sample rate 44100Hz

enumerator kFLEXIO_I2S_SampleRate48KHz

Sample rate 48000Hz

enumerator kFLEXIO_I2S_SampleRate96KHz

Sample rate 96000Hz

enum _flexio_i2s_word_width

Audio word width.

Values:

enumerator kFLEXIO_I2S_WordWidth8bits

Audio data width 8 bits

enumerator kFLEXIO_I2S_WordWidth16bits

Audio data width 16 bits

enumerator kFLEXIO_I2S_WordWidth24bits

Audio data width 24 bits

enumerator kFLEXIO_I2S_WordWidth32bits

Audio data width 32 bits

typedef struct _flexio_i2s_type FLEXIO_I2S_Type

Define FlexIO I2S access structure typedef.

typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t

Master or slave mode.

typedef struct _flexio_i2s_config flexio_i2s_config_t

FlexIO I2S configure structure.

typedef struct _flexio_i2s_format flexio_i2s_format_t

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t

Audio sample rate.

typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t

Audio word width.

typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t

Define FlexIO I2S transfer structure.

typedef struct _flexio_i2s_handle flexio_i2s_handle_t

typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData)

FlexIO I2S xfer callback prototype.

I2S_RETRY_TIMES

Retry times for waiting flag.

FLEXIO_I2S_XFER_QUEUE_SIZE

FlexIO I2S transfer queue size, user can refine it according to use case.

struct _flexio_i2s_type

#include <fsl_flexio_i2s.h>

Define FlexIO I2S access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer

uint8_t txPinIndex

Tx data pin index in FlexIO pins

uint8_t rxPinIndex

Rx data pin index

uint8_t bclkPinIndex

Bit clock pin index

uint8_t fsPinIndex

Frame sync pin index

uint8_t txShifterIndex

Tx data shifter index

uint8_t rxShifterIndex

Rx data shifter index

uint8_t bclkTimerIndex

Bit clock timer index

uint8_t fsTimerIndex

Frame sync timer index

struct _flexio_i2s_config

#include <fsl_flexio_i2s.h>

FlexIO I2S configure structure.

Public Members

bool enableI2S

Enable FlexIO I2S

flexio_i2s_master_slave_t masterSlave

Master or slave

flexio_pin_polarity_t txPinPolarity

Tx data pin polarity, active high or low

flexio_pin_polarity_t rxPinPolarity

Rx data pin polarity

flexio_pin_polarity_t bclkPinPolarity

Bit clock pin polarity

flexio_pin_polarity_t fsPinPolarity

Frame sync pin polarity

flexio_shifter_timer_polarity_t txTimerPolarity

Tx data valid on bclk rising or falling edge

flexio_shifter_timer_polarity_t rxTimerPolarity

Rx data valid on bclk rising or falling edge

struct _flexio_i2s_format

#include <fsl_flexio_i2s.h>

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

Public Members

uint8_t bitWidth

Bit width of audio data, always 8/16/24/32 bits

uint32_t sampleRate_Hz

Sample rate of the audio data

struct _flexio_i2s_transfer

#include <fsl_flexio_i2s.h>

Define FlexIO I2S transfer structure.

Public Members

uint8_t *data

Data buffer start pointer

size_t dataSize

Bytes to be transferred.

struct _flexio_i2s_handle

#include <fsl_flexio_i2s.h>

Define FlexIO I2S handle structure.

Public Members

uint32_t state

Internal state

flexio_i2s_callback_t callback

Callback function called at transfer event

void *userData

Callback parameter passed to callback function

uint8_t bitWidth

Bit width for transfer, 8/16/24/32bits

flexio_i2s_transfer_t queue[(4U)]

Transfer queue storing queued transfer

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

FlexIO SPI Driver

void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().

Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);

Note

1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• masterConfig – Pointer to the flexio_spi_master_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)

Resets the FlexIO SPI timer and shifter config.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:

flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

• masterConfig – Pointer to the flexio_spi_master_config_t structure.

void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().

Note

1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)

Gates the FlexIO clock.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)

Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:

flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

• slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)

Gets FlexIO SPI status flags.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

Returns:

status flag; Use the status flag to AND the following flag mask and get the status.

• kFLEXIO_SPI_TxEmptyFlag

• kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)

Clears FlexIO SPI status flags.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – status flag The parameter can be any combination of the following values:

  • kFLEXIO_SPI_TxEmptyFlag

  • kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Enables the FlexIO SPI interrupt.

This function enables the FlexIO SPI interrupt.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – interrupt source. The parameter can be any combination of the following values:

  • kFLEXIO_SPI_RxFullInterruptEnable

  • kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Disables the FlexIO SPI interrupt.

This function disables the FlexIO SPI interrupt.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – interrupt source The parameter can be any combination of the following values:

  • kFLEXIO_SPI_RxFullInterruptEnable

  • kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)

Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – SPI DMA source.

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI transmit data register address for MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI transmit data register address.

static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI receive data register address for the MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI receive data register address.

static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)

Enables/disables the FlexIO SPI module operation.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

• enable – True to enable, false does not have any effect.

void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)

Sets baud rate for the FlexIO SPI transfer, which is only used for the master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• baudRate_Bps – Baud Rate needed in Hz.

• srcClockHz – SPI source clock frequency in Hz.

static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)

Writes one byte of data, which is sent using the MSB method.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• data – 8/16/32 bit data.

static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Reads 8 bit/16 bit data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

8 bit/16 bit data received.

status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• buffer – The data bytes to send.

• size – The number of data bytes to send.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• buffer – The buffer to store the received bytes.

• size – The number of data bytes to be received.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

• base – pointer to FLEXIO_SPI_Type structure

• xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)

Flush tx/rx shifters.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Master handle, which is used in transactional functions.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)

Master transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)

Aborts the master data transfer, which used IRQ.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI master IRQ handler function.

Parameters:

• spiType – Pointer to the FLEXIO_SPI_Type structure.

• spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Slave handle, which is used in transactional functions.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)

Slave transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• base – Pointer to the FLEXIO_SPI_Type structure.

• xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)

Aborts the slave data transfer which used IRQ, share same API with master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ, share same API with master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI slave IRQ handler function.

Parameters:

• spiType – Pointer to the FLEXIO_SPI_Type structure.

• spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

FSL_FLEXIO_SPI_DRIVER_VERSION

FlexIO SPI driver version.

Error codes for the FlexIO SPI driver.

Values:

enumerator kStatus_FLEXIO_SPI_Busy

FlexIO SPI is busy.

enumerator kStatus_FLEXIO_SPI_Idle

SPI is idle

enumerator kStatus_FLEXIO_SPI_Error

FlexIO SPI error.

enumerator kStatus_FLEXIO_SPI_Timeout

FlexIO SPI timeout polling status flags.

enum _flexio_spi_clock_phase

FlexIO SPI clock phase configuration.

Values:

enumerator kFLEXIO_SPI_ClockPhaseFirstEdge

First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kFLEXIO_SPI_ClockPhaseSecondEdge

First edge on SPSCK occurs at the start of the first cycle of a data transfer.

enum _flexio_spi_shift_direction

FlexIO SPI data shifter direction options.

Values:

enumerator kFLEXIO_SPI_MsbFirst

Data transfers start with most significant bit.

enumerator kFLEXIO_SPI_LsbFirst

Data transfers start with least significant bit.

enum _flexio_spi_data_bitcount_mode

FlexIO SPI data length mode options.

Values:

enumerator kFLEXIO_SPI_8BitMode

8-bit data transmission mode.

enumerator kFLEXIO_SPI_16BitMode

16-bit data transmission mode.

enumerator kFLEXIO_SPI_32BitMode

32-bit data transmission mode.

enum _flexio_spi_interrupt_enable

Define FlexIO SPI interrupt mask.

Values:

enumerator kFLEXIO_SPI_TxEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_SPI_RxFullInterruptEnable

Receive buffer full interrupt enable.

enum _flexio_spi_status_flags

Define FlexIO SPI status mask.

Values:

enumerator kFLEXIO_SPI_TxBufferEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_SPI_RxBufferFullFlag

Receive buffer full flag.

enum _flexio_spi_dma_enable

Define FlexIO SPI DMA mask.

Values:

enumerator kFLEXIO_SPI_TxDmaEnable

Tx DMA request source

enumerator kFLEXIO_SPI_RxDmaEnable

Rx DMA request source

enumerator kFLEXIO_SPI_DmaAllEnable

All DMA request source

enum _flexio_spi_transfer_flags

Define FlexIO SPI transfer flags.

Note

Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.

Values:

enumerator kFLEXIO_SPI_8bitMsb

FlexIO SPI 8-bit MSB first

enumerator kFLEXIO_SPI_8bitLsb

FlexIO SPI 8-bit LSB first

enumerator kFLEXIO_SPI_16bitMsb

FlexIO SPI 16-bit MSB first

enumerator kFLEXIO_SPI_16bitLsb

FlexIO SPI 16-bit LSB first

enumerator kFLEXIO_SPI_32bitMsb

FlexIO SPI 32-bit MSB first

enumerator kFLEXIO_SPI_32bitLsb

FlexIO SPI 32-bit LSB first

enumerator kFLEXIO_SPI_csContinuous

Enable the CS signal continuous mode

typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t

FlexIO SPI clock phase configuration.

typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t

FlexIO SPI data shifter direction options.

typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t

FlexIO SPI data length mode options.

typedef struct _flexio_spi_type FLEXIO_SPI_Type

Define FlexIO SPI access structure typedef.

typedef struct _flexio_spi_master_config flexio_spi_master_config_t

Define FlexIO SPI master configuration structure.

typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t

Define FlexIO SPI slave configuration structure.

typedef struct _flexio_spi_transfer flexio_spi_transfer_t

Define FlexIO SPI transfer structure.

typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t

typedef for flexio_spi_master_handle_t in advance.

typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t

Slave handle is the same with master handle.

typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData)

FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData)

FlexIO SPI slave callback for finished transmit.

FLEXIO_SPI_DUMMYDATA

FlexIO SPI dummy transfer data, the data is sent while txData is NULL.

SPI_RETRY_TIMES

Retry times for waiting flag.

FLEXIO_SPI_XFER_DATA_FORMAT(flag)

Get the transfer data format of width and bit order.

struct _flexio_spi_type

#include <fsl_flexio_spi.h>

Define FlexIO SPI access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t SDOPinIndex

Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.

uint8_t SDIPinIndex

Pin select for data input.

uint8_t SCKPinIndex

Pin select for clock.

uint8_t CSnPinIndex

Pin select for enable.

uint8_t shifterIndex[2]

Shifter index used in FlexIO SPI.

uint8_t timerIndex[2]

Timer index used in FlexIO SPI.

struct _flexio_spi_master_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI master configuration structure.

Public Members

bool enableMaster

Enable/disable FlexIO SPI master after configuration.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

flexio_spi_clock_phase_t phase

Clock phase.

flexio_spi_data_bitcount_mode_t dataMode

8bit or 16bit mode.

struct _flexio_spi_slave_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI slave configuration structure.

Public Members

bool enableSlave

Enable/disable FlexIO SPI slave after configuration.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_spi_clock_phase_t phase

Clock phase.

flexio_spi_data_bitcount_mode_t dataMode

8bit or 16bit mode.

struct _flexio_spi_transfer

#include <fsl_flexio_spi.h>

Define FlexIO SPI transfer structure.

Public Members

const uint8_t *txData

Send buffer.

uint8_t *rxData

Receive buffer.

size_t dataSize

Transfer bytes.

uint8_t flags

FlexIO SPI control flag, MSB first or LSB first.

struct _flexio_spi_master_handle

#include <fsl_flexio_spi.h>

Define FlexIO SPI handle structure.

Public Members

const uint8_t *txData

Transfer buffer.

uint8_t *rxData

Receive buffer.

size_t transferSize

Total bytes to be transferred.

volatile size_t txRemainingBytes

Send data remaining in bytes.

volatile size_t rxRemainingBytes

Receive data remaining in bytes.

volatile uint32_t state

FlexIO SPI internal state.

uint8_t bytePerFrame

SPI mode, 2bytes or 1byte in a frame

flexio_spi_shift_direction_t direction

Shift direction.

flexio_spi_master_transfer_callback_t callback

FlexIO SPI callback.

void *userData

Callback parameter.

FlexIO UART Driver

status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().

Example

FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• userConfig – Pointer to the flexio_uart_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

Return values:

• kStatus_Success – Configuration success.

• kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)

Resets the FlexIO UART shifter and timer config.

Note

After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.

Parameters:

• base – Pointer to FLEXIO_UART_Type structure

void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)

Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:

flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);

Parameters:

• userConfig – Pointer to the flexio_uart_config_t structure.

uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)

Gets the FlexIO UART status flags.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART status flags.

void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)

Gets the FlexIO UART status flags.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Status flag. The parameter can be any combination of the following values:

  • kFLEXIO_UART_TxDataRegEmptyFlag

  • kFLEXIO_UART_RxEmptyFlag

  • kFLEXIO_UART_RxOverRunFlag

void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Enables the FlexIO UART interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Interrupt source.

void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Disables the FlexIO UART interrupt.

This function disables the FlexIO UART interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Interrupt source.

static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UARt transmit data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART transmit data register address.

static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UART receive data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART receive data register address.

static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• enable – True to enable, false to disable.

static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• enable – True to enable, false to disable.

static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART module operation.

Parameters:

• base – Pointer to the FLEXIO_UART_Type.

• enable – True to enable, false does not have any effect.

static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• buffer – The data bytes to send.

static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• buffer – The buffer to store the received bytes.

status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• txData – The data bytes to send.

• txSize – The number of data bytes to send.

Return values:

• kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• rxData – The buffer to store the received bytes.

• rxSize – The number of data bytes to be received.

Return values:

• kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)

Initializes the UART handle.

This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.

The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

• base – to FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.

• ringBufferSize – Size of the ring buffer.

void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.

Note

The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.

Return values:

• kStatus_Success – Successfully starts the data transmission.

• kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• count – Number of bytes sent so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• xfer – UART transfer structure. See flexio_uart_transfer_t.

• receivedBytes – Bytes received from the ring buffer directly.

Return values:

• kStatus_Success – Successfully queue the transfer into the transmit queue.

• kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.

void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• count – Number of bytes received so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)

FlexIO UART IRQ handler function.

This function processes the FlexIO UART transmit and receives the IRQ request.

Parameters:

• uartType – Pointer to the FLEXIO_UART_Type structure.

• uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)

Flush tx/rx shifters.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

FSL_FLEXIO_UART_DRIVER_VERSION

FlexIO UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_FLEXIO_UART_TxBusy

Transmitter is busy.

enumerator kStatus_FLEXIO_UART_RxBusy

Receiver is busy.

enumerator kStatus_FLEXIO_UART_TxIdle

UART transmitter is idle.

enumerator kStatus_FLEXIO_UART_RxIdle

UART receiver is idle.

enumerator kStatus_FLEXIO_UART_ERROR

ERROR happens on UART.

enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun

UART RX software ring buffer overrun.

enumerator kStatus_FLEXIO_UART_RxHardwareOverrun

UART RX receiver overrun.

enumerator kStatus_FLEXIO_UART_Timeout

UART times out.

enumerator kStatus_FLEXIO_UART_BaudrateNotSupport

Baudrate is not supported in current clock source

enum _flexio_uart_bit_count_per_char

FlexIO UART bit count per char.

Values:

enumerator kFLEXIO_UART_7BitsPerChar

7-bit data characters

enumerator kFLEXIO_UART_8BitsPerChar

8-bit data characters

enumerator kFLEXIO_UART_9BitsPerChar

9-bit data characters

enum _flexio_uart_interrupt_enable

Define FlexIO UART interrupt mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable

Receive buffer full interrupt enable.

enum _flexio_uart_status_flags

Define FlexIO UART status mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_UART_RxDataRegFullFlag

Receive buffer full flag.

enumerator kFLEXIO_UART_RxOverRunFlag

Receive buffer over run flag.

typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t

FlexIO UART bit count per char.

typedef struct _flexio_uart_type FLEXIO_UART_Type

Define FlexIO UART access structure typedef.

typedef struct _flexio_uart_config flexio_uart_config_t

Define FlexIO UART user configuration structure.

typedef struct _flexio_uart_transfer flexio_uart_transfer_t

Define FlexIO UART transfer structure.

typedef struct _flexio_uart_handle flexio_uart_handle_t

typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData)

FlexIO UART transfer callback function.

UART_RETRY_TIMES

Retry times for waiting flag.

struct _flexio_uart_type

#include <fsl_flexio_uart.h>

Define FlexIO UART access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t TxPinIndex

Pin select for UART_Tx.

uint8_t RxPinIndex

Pin select for UART_Rx.

uint8_t shifterIndex[2]

Shifter index used in FlexIO UART.

uint8_t timerIndex[2]

Timer index used in FlexIO UART.

struct _flexio_uart_config

#include <fsl_flexio_uart.h>

Define FlexIO UART user configuration structure.

Public Members

bool enableUart

Enable/disable FlexIO UART TX & RX.

bool enableInDoze

Enable/disable FlexIO operation in doze mode

bool enableInDebug

Enable/disable FlexIO operation in debug mode

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

flexio_uart_bit_count_per_char_t bitCountPerChar

number of bits, 7/8/9 -bit

struct _flexio_uart_transfer

#include <fsl_flexio_uart.h>

Define FlexIO UART transfer structure.

Public Members

size_t dataSize

Transfer size

struct _flexio_uart_handle

#include <fsl_flexio_uart.h>

Define FLEXIO UART handle structure.

Public Members

const uint8_t *volatile txData

Address of remaining data to send.

volatile size_t txDataSize

Size of the remaining data to send.

uint8_t *volatile rxData

Address of remaining data to receive.

volatile size_t rxDataSize

Size of the remaining data to receive.

size_t txDataSizeAll

Total bytes to be sent.

size_t rxDataSizeAll

Total bytes to be received.

uint8_t *rxRingBuffer

Start address of the receiver ring buffer.

size_t rxRingBufferSize

Size of the ring buffer.

volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer.

flexio_uart_transfer_callback_t callback

Callback function.

void *userData

UART callback function parameter.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

union __unnamed150__

Public Members

uint8_t *data

The buffer of data to be transfer.

uint8_t *rxData

The buffer to receive data.

const uint8_t *txData

The buffer of data to be sent.

FLEXRAM: on-chip RAM manager

FLEXRAM bank type.

Values:

enumerator kFLEXRAM_BankNotUsed

bank is not used

enumerator kFLEXRAM_BankOCRAM

bank is OCRAM

enumerator kFLEXRAM_BankDTCM

bank is DTCM

enumerator kFLEXRAM_BankITCM

bank is ITCM

enum _flexram_bank_allocate_src

FLEXRAM bank allocate source.

Values:

enumerator kFLEXRAM_BankAllocateThroughHardwareFuse

allocate ram through hardware fuse value

enumerator kFLEXRAM_BankAllocateThroughBankCfg

allocate ram through FLEXRAM_BANK_CFG

typedef enum _flexram_bank_allocate_src flexram_bank_allocate_src_t

FLEXRAM bank allocate source.

typedef struct _flexram_allocate_ram flexram_allocate_ram_t

FLEXRAM allocates OCRAM, ITCM, DTCM size.

status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)

FLEXRAM allocates an on-chip ram for OCRAM, ITCM and DTCM. This function is independent from FLEXRAM_Init, and can be called directly if ram re-allocate is needed.

Parameters:

• config – Allocate configuration.

Return values:

• kStatus_InvalidArgument – When the argument is invalid.

• kStatus_Success – Upon allocate success.

static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)

FLEXRAM set allocate on-chip ram source.

Parameters:

• src – Bank config source select value.

FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION

SOC_FLEXRAM_ALLOCATE driver version 2.0.2.

void FLEXRAM_Init(FLEXRAM_Type *base)

FLEXRAM module initialization function.

Parameters:

• base – FLEXRAM base address.

void FLEXRAM_Deinit(FLEXRAM_Type *base)

De-initializes the FLEXRAM.

static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)

FLEXRAM module gets interrupt status.

Parameters:

• base – FLEXRAM base address.

static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)

FLEXRAM module clears interrupt status.

Parameters:

• base – FLEXRAM base address.

• status – Status to be cleared.

static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)

FLEXRAM module enables interrupt status.

Parameters:

• base – FLEXRAM base address.

• status – Status to be enabled.

static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)

FLEXRAM module disable interrupt status.

Parameters:

• base – FLEXRAM base address.

• status – Status to be disabled.

static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)

FLEXRAM module enables interrupt.

Parameters:

• base – FLEXRAM base address.

• status – Status interrupt to be enabled.

static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)

FLEXRAM module disables interrupt.

Parameters:

• base – FLEXRAM base address.

• status – Status interrupt to be disabled.

FSL_FLEXRAM_DRIVER_VERSION

Driver version.

Flexram write/read selection.

Values:

enumerator kFLEXRAM_Read

read

enumerator kFLEXRAM_Write

write

Interrupt status flag mask.

Values:

enumerator kFLEXRAM_OCRAMAccessError

OCRAM accesses unallocated address

enumerator kFLEXRAM_DTCMAccessError

DTCM accesses unallocated address

enumerator kFLEXRAM_ITCMAccessError

ITCM accesses unallocated address

enumerator kFLEXRAM_OCRAMMagicAddrMatch

OCRAM magic address match

enumerator kFLEXRAM_DTCMMagicAddrMatch

DTCM magic address match

enumerator kFLEXRAM_ITCMMagicAddrMatch

ITCM magic address match

enumerator kFLEXRAM_OCRAMECCMultiError

enumerator kFLEXRAM_OCRAMECCSingleError

enumerator kFLEXRAM_ITCMECCMultiError

enumerator kFLEXRAM_ITCMECCSingleError

enumerator kFLEXRAM_D0TCMECCMultiError

enumerator kFLEXRAM_D0TCMECCSingleError

enumerator kFLEXRAM_D1TCMECCMultiError

enumerator kFLEXRAM_D1TCMECCSingleError

enumerator kFLEXRAM_InterruptStatusAll

enum _flexram_tcm_access_mode

FLEXRAM TCM access mode. Fast access mode expected to be finished in 1-cycle; Wait access mode expected to be finished in 2-cycle. Wait access mode is a feature of the flexram and it should be used when the CPU clock is too fast to finish TCM access in 1-cycle. Normally, fast mode is the default mode, the efficiency of the TCM access will better.

Values:

enumerator kFLEXRAM_TCMAccessFastMode

fast access mode

enumerator kFLEXRAM_TCMAccessWaitMode

wait access mode

FLEXRAM TCM support size.

Values:

enumerator kFLEXRAM_TCMSize32KB

TCM total size be 32KB

enumerator kFLEXRAM_TCMSize64KB

TCM total size be 64KB

enumerator kFLEXRAM_TCMSize128KB

TCM total size be 128KB

enumerator kFLEXRAM_TCMSize256KB

TCM total size be 256KB

enumerator kFLEXRAM_TCMSize512KB

TCM total size be 512KB

enum _flexram_memory_type

FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM.

Values:

enumerator kFLEXRAM_OCRAM

Memory type OCRAM

enumerator kFLEXRAM_ITCM

Memory type ITCM

enumerator kFLEXRAM_D0TCM

Memory type D0TCM

enumerator kFLEXRAM_D1TCM

Memory type D1TCM

typedef enum _flexram_tcm_access_mode flexram_tcm_access_mode_t

FLEXRAM TCM access mode. Fast access mode expected to be finished in 1-cycle; Wait access mode expected to be finished in 2-cycle. Wait access mode is a feature of the flexram and it should be used when the CPU clock is too fast to finish TCM access in 1-cycle. Normally, fast mode is the default mode, the efficiency of the TCM access will better.

typedef enum _flexram_memory_type flexram_memory_type_t

FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM.

typedef struct _flexram_ecc_error_type flexram_ecc_error_type_t

FLEXRAM error type, such as single bit error position, multi-bit error position.

typedef struct _flexram_ocram_ecc_single_error_info flexram_ocram_ecc_single_error_info_t

FLEXRAM ocram ecc single error information, including single error information, error address, error data.

typedef struct _flexram_ocram_ecc_multi_error_info flexram_ocram_ecc_multi_error_info_t

FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data.

typedef struct _flexram_itcm_ecc_single_error_info flexram_itcm_ecc_single_error_info_t

FLEXRAM itcm ecc single error information, including single error information, error address, error data.

typedef struct _flexram_itcm_ecc_multi_error_info flexram_itcm_ecc_multi_error_info_t

FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data.

typedef struct _flexram_dtcm_ecc_single_error_info flexram_dtcm_ecc_single_error_info_t

FLEXRAM dtcm ecc single error information, including single error information, error address, error data.

typedef struct _flexram_dtcm_ecc_multi_error_info flexram_dtcm_ecc_multi_error_info_t

FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data.

const uint8_t ocramBankNum

OCRAM banknumber which the SOC support.

const uint8_t dtcmBankNum

DTCM bank number to allocate, the number should be power of 2.

const uint8_t itcmBankNum

ITCM bank number to allocate, the number should be power of 2.

static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)

FLEXRAM module sets TCM read access mode.

Parameters:

• base – FLEXRAM base address.

• mode – Access mode.

static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)

FLEXRAM module set TCM write access mode.

Parameters:

• base – FLEXRAM base address.

• mode – Access mode.

static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)

FLEXRAM module force ram clock on.

Parameters:

• base – FLEXRAM base address.

• enable – Enable or disable clock force on.

static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)

FLEXRAM OCRAM magic addr configuration. When read/write access hit magic address, it will generate interrupt.

Parameters:

• base – FLEXRAM base address.

• magicAddr – Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].

• rwSel – Read/write selection. 0 for read access while 1 for write access.

static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)

FLEXRAM DTCM magic addr configuration. When read/write access hits magic address, it will generate interrupt.

Parameters:

• base – FLEXRAM base address.

• magicAddr – Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].

• rwSel – Read/write selection. 0 for read access while 1 write access.

static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)

FLEXRAM ITCM magic addr configuration. When read/write access hits magic address, it will generate interrupt.

Parameters:

• base – FLEXRAM base address.

• magicAddr – Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].

• rwSel – Read/write selection. 0 for read access while 1 for write access.

void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable)

FLEXRAM get ocram ecc single error information.

Parameters:

• base – FLEXRAM base address.

• OcramECCEnable – ocram ecc enablement.

• TcmECCEnable – tcm(itcm/d0tcm/d1tcm) ecc enablement.

void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)

FLEXRAM ECC error injection.

Parameters:

• base – FLEXRAM base address.

• memory – memory type, such as OCRAM/ITCM/DTCM.

• error – ECC error type.

void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)

FLEXRAM get ocram ecc single error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info)

FLEXRAM get ocram ecc multiple error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info)

FLEXRAM get itcm ecc single error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info)

FLEXRAM get itcm ecc multiple error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank)

FLEXRAM get d0tcm ecc single error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

• bank – DTCM bank, 0 is D0TCM, 1 is D1TCM.

void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank)

FLEXRAM get d0tcm ecc multiple error information.

Parameters:

• base – FLEXRAM base address.

• info – ecc error information.

• bank – DTCM bank, 0 is D0TCM, 1 is D1TCM.

FLEXRAM_ECC_ERROR_DETAILED_INFO

Get ECC error detailed information.

struct _flexram_allocate_ram

#include <fsl_flexram_allocate.h>

FLEXRAM allocates OCRAM, ITCM, DTCM size.

struct _flexram_ecc_error_type

#include <fsl_flexram.h>

FLEXRAM error type, such as single bit error position, multi-bit error position.

Public Members

uint8_t SingleBitPos

Bit position of the bit to inject ECC Error.

uint8_t SecondBitPos

Bit position of the second bit to inject multi-bit ECC Error

bool Fource1BitDataInversion

Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access

bool FourceOneNCDataInversion

Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write access

bool FourceConti1BitDataInversion

Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory write access

bool FourceContiNCDataInversion

Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on memory write access

struct _flexram_ocram_ecc_single_error_info

#include <fsl_flexram.h>

FLEXRAM ocram ecc single error information, including single error information, error address, error data.

Public Members

uint32_t OcramSingleErrorInfo

Ocram single error information, user should parse it by themself.

uint32_t OcramSingleErrorAddr

Ocram single error address

uint32_t OcramSingleErrorDataLSB

Ocram single error data LSB

uint32_t OcramSingleErrorDataMSB

Ocram single error data MSB

struct _flexram_ocram_ecc_multi_error_info

#include <fsl_flexram.h>

FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data.

Public Members

uint32_t OcramMultiErrorInfo

Ocram single error information, user should parse it by themself.

uint32_t OcramMultiErrorAddr

Ocram multiple error address

uint32_t OcramMultiErrorDataLSB

Ocram multiple error data LSB

uint32_t OcramMultiErrorDataMSB

Ocram multiple error data MSB

struct _flexram_itcm_ecc_single_error_info

#include <fsl_flexram.h>

FLEXRAM itcm ecc single error information, including single error information, error address, error data.

Public Members

uint32_t ItcmSingleErrorInfo

itcm single error information, user should parse it by themself.

uint32_t ItcmSingleErrorAddr

itcm single error address

uint32_t ItcmSingleErrorDataLSB

itcm single error data LSB

uint32_t ItcmSingleErrorDataMSB

itcm single error data MSB

struct _flexram_itcm_ecc_multi_error_info

#include <fsl_flexram.h>

FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data.

Public Members

uint32_t ItcmMultiErrorInfo

itcm multiple error information, user should parse it by themself.

uint32_t ItcmMultiErrorAddr

itcm multiple error address

uint32_t ItcmMultiErrorDataLSB

itcm multiple error data LSB

uint32_t ItcmMultiErrorDataMSB

itcm multiple error data MSB

struct _flexram_dtcm_ecc_single_error_info

#include <fsl_flexram.h>

FLEXRAM dtcm ecc single error information, including single error information, error address, error data.

Public Members

uint32_t DtcmSingleErrorInfo

dtcm single error information, user should parse it by themself.

uint32_t DtcmSingleErrorAddr

dtcm single error address

uint32_t DtcmSingleErrorData

dtcm single error data

struct _flexram_dtcm_ecc_multi_error_info

#include <fsl_flexram.h>

FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data.

Public Members

uint32_t DtcmMultiErrorInfo

dtcm multiple error information, user should parse it by themself.

uint32_t DtcmMultiErrorAddr

dtcm multiple error address

uint32_t DtcmMultiErrorData

dtcm multiple error data

FLEXSPI: Flexible Serial Peripheral Interface Driver

uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)

Get the instance number for FLEXSPI.

Parameters:

• base – FLEXSPI base pointer.

status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)

Check and clear IP command execution errors.

Parameters:

• base – FLEXSPI base pointer.

• status – interrupt status.

void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)

Initializes the FLEXSPI module and internal state.

This function enables the clock for FLEXSPI and also configures the FLEXSPI with the input configure parameters. Users should call this function before any FLEXSPI operations.

Parameters:

• base – FLEXSPI peripheral base address.

• config – FLEXSPI configure structure.

void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)

Gets default settings for FLEXSPI.

Parameters:

• config – FLEXSPI configuration structure.

void FLEXSPI_Deinit(FLEXSPI_Type *base)

Deinitializes the FLEXSPI module.

Clears the FLEXSPI state and FLEXSPI module registers.

Parameters:

• base – FLEXSPI peripheral base address.

void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Update FLEXSPI DLL value depending on currently flexspi root clock.

Parameters:

• base – FLEXSPI peripheral base address.

• config – Flash configuration parameters.

• port – FLEXSPI Operation port.

void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Configures the connected device parameter.

This function configures the connected device relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the connected device.

Parameters:

• base – FLEXSPI peripheral base address.

• config – Flash configuration parameters.

• port – FLEXSPI Operation port.

void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)

Software reset for the FLEXSPI logic.

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

Parameters:

• base – FLEXSPI peripheral base address.

static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)

Enables or disables the FLEXSPI module.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – True means enable FLEXSPI, false means disable.

static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Enables the FLEXSPI interrupts.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Disable the FLEXSPI interrupts.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Tx FIFO DMA requests.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – Enable flag for transmit DMA request. Pass true for enable, false for disable.

static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Rx FIFO DMA requests.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP tx fifo address for DMA transfer.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

The – tx fifo address.

static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP rx fifo address for DMA transfer.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

The – rx fifo address.

static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)

Clears the FLEXSPI IP FIFO logic.

Parameters:

• base – FLEXSPI peripheral base address.

• txFifo – Pass true to reset TX FIFO.

• rxFifo – Pass true to reset RX FIFO.

static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)

Gets the valid data entries in the FLEXSPI FIFOs.

Parameters:

• base – FLEXSPI peripheral base address.

• txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)

Get the FLEXSPI interrupt status flags.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

interrupt – status flag, use status flag to AND flexspi_flags_t could get the related status.

static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)

Get the FLEXSPI interrupt status flags.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)

Gets the trigger source of current command sequence granted by arbitrator.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

trigger – source of current command sequence.

static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when IP command error detected.

Parameters:

• base – FLEXSPI peripheral base address.

• index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when IP command error detected.

static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when AHB command error detected.

Parameters:

• base – FLEXSPI peripheral base address.

• index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when AHB command error detected.

static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)

Returns whether the bus is idle.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

• true – Bus is idle.

• false – Bus is busy.

void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)

Update read sample clock source.

Parameters:

• base – FLEXSPI peripheral base address.

• clockSource – clockSource of type flexspi_read_sample_clock_t

void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)

Updates the LUT table.

Parameters:

• base – FLEXSPI peripheral base address.

• index – From which index start to update. It could be any index of the LUT table, which also allows user to update command content inside a command. Each command consists of up to 8 instructions and occupy 4*32-bit memory.

• cmd – Command sequence array.

• count – Number of sequences.

static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)

Writes data into FIFO.

Parameters:

• base – FLEXSPI peripheral base address

• data – The data bytes to send

• fifoIndex – Destination fifo index.

static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)

Receives data from data FIFO.

Parameters:

• base – FLEXSPI peripheral base address

• fifoIndex – Source fifo index.

Returns:

The data in the FIFO.

status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Sends a buffer of data bytes using blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – FLEXSPI peripheral base address

• buffer – The data bytes to send

• size – The number of data bytes to send

Return values:

• kStatus_Success – write success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – FLEXSPI peripheral base address

• buffer – The data bytes to send

• size – The number of data bytes to receive

Return values:

• kStatus_Success – read success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequencen error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)

Execute command to transfer a buffer data bytes using a blocking method.

Parameters:

• base – FLEXSPI peripheral base address

• xfer – pointer to the transfer structure.

Return values:

• kStatus_Success – command transfer success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData)

Initializes the FLEXSPI handle which is used in transactional functions.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure to store the transfer state.

• callback – pointer to user callback function.

• userData – user parameter passed to the callback function.

status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)

Performs a interrupt non-blocking transfer on the FLEXSPI bus.

Note

Calling the API returns immediately after transfer initiates. The user needs to call FLEXSPI_GetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or FLEXSPI could not read data properly.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state.

• xfer – pointer to flexspi_transfer_t structure.

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_FLEXSPI_Busy – Previous transmission still not finished.

status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state

void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)

Master interrupt handler.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure.

FSL_FLEXSPI_DRIVER_VERSION

FLEXSPI driver version.

Status structure of FLEXSPI.

Values:

enumerator kStatus_FLEXSPI_Busy

FLEXSPI is busy

enumerator kStatus_FLEXSPI_SequenceExecutionTimeout

Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandSequenceError

IP command Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandGrantTimeout

IP command grant timeout error occurred during FLEXSPI transfer.

CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command.

Values:

enumerator kFLEXSPI_Command_STOP

Stop execution, deassert CS.

enumerator kFLEXSPI_Command_SDR

Transmit Command code to Flash, using SDR mode.

enumerator kFLEXSPI_Command_RADDR_SDR

Transmit Row Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_CADDR_SDR

Transmit Column Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE1_SDR

Transmit 1-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE2_SDR

Transmit 2-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE4_SDR

Transmit 4-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE8_SDR

Transmit 8-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_WRITE_SDR

Transmit Programming Data to Flash, using SDR mode.

enumerator kFLEXSPI_Command_READ_SDR

Receive Read Data from Flash, using SDR mode.

enumerator kFLEXSPI_Command_LEARN_SDR

Receive Read Data or Preamble bit from Flash, SDR mode.

enumerator kFLEXSPI_Command_DATSZ_SDR

Transmit Read/Program Data size (byte) to Flash, SDR mode.

enumerator kFLEXSPI_Command_DUMMY_SDR

Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_SDR

Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_DDR

Transmit Command code to Flash, using DDR mode.

enumerator kFLEXSPI_Command_RADDR_DDR

Transmit Row Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_CADDR_DDR

Transmit Column Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE1_DDR

Transmit 1-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE2_DDR

Transmit 2-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE4_DDR

Transmit 4-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE8_DDR

Transmit 8-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_WRITE_DDR

Transmit Programming Data to Flash, using DDR mode.

enumerator kFLEXSPI_Command_READ_DDR

Receive Read Data from Flash, using DDR mode.

enumerator kFLEXSPI_Command_LEARN_DDR

Receive Read Data or Preamble bit from Flash, DDR mode.

enumerator kFLEXSPI_Command_DATSZ_DDR

Transmit Read/Program Data size (byte) to Flash, DDR mode.

enumerator kFLEXSPI_Command_DUMMY_DDR

Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_DDR

Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_JUMP_ON_CS

Stop execution, deassert CS and save operand[7:0] as the instruction start pointer for next sequence

enum _flexspi_pad

pad definition of FLEXSPI, use to form LUT instruction.

Values:

enumerator kFLEXSPI_1PAD

Transmit command/address and transmit/receive data only through DATA0/DATA1.

enumerator kFLEXSPI_2PAD

Transmit command/address and transmit/receive data only through DATA[1:0].

enumerator kFLEXSPI_4PAD

Transmit command/address and transmit/receive data only through DATA[3:0].

enumerator kFLEXSPI_8PAD

Transmit command/address and transmit/receive data only through DATA[7:0].

enum _flexspi_flags

FLEXSPI interrupt status flags.

Values:

enumerator kFLEXSPI_SequenceExecutionTimeoutFlag

Sequence execution timeout.

enumerator kFLEXSPI_AhbBusErrorFlag

AHB Bus error flag.

enumerator kFLEXSPI_SckStoppedBecauseTxEmptyFlag

SCK is stopped during command sequence because Async TX FIFO empty.

enumerator kFLEXSPI_SckStoppedBecauseRxFullFlag

SCK is stopped during command sequence because Async RX FIFO full.

enumerator kFLEXSPI_IpTxFifoWatermarkEmptyFlag

IP TX FIFO WaterMark empty.

enumerator kFLEXSPI_IpRxFifoWatermarkAvailableFlag

IP RX FIFO WaterMark available.

enumerator kFLEXSPI_AhbCommandSequenceErrorFlag

AHB triggered Command Sequences Error.

enumerator kFLEXSPI_IpCommandSequenceErrorFlag

IP triggered Command Sequences Error.

enumerator kFLEXSPI_AhbCommandGrantTimeoutFlag

AHB triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandGrantTimeoutFlag

IP triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandExecutionDoneFlag

IP triggered Command Sequences Execution finished.

enumerator kFLEXSPI_AllInterruptFlags

All flags.

enum _flexspi_read_sample_clock

FLEXSPI sample clock source selection for Flash Reading.

Values:

enumerator kFLEXSPI_ReadSampleClkLoopbackInternally

Dummy Read strobe generated by FlexSPI Controller and loopback internally.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromDqsPad

Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromSckPad

SCK output clock and loopback from SCK pad.

enumerator kFLEXSPI_ReadSampleClkExternalInputFromDqsPad

Flash provided Read strobe and input from DQS pad.

enum _flexspi_cs_interval_cycle_unit

FLEXSPI interval unit for flash device select.

Values:

enumerator kFLEXSPI_CsIntervalUnit1SckCycle

Chip selection interval: CSINTERVAL * 1 serial clock cycle.

enumerator kFLEXSPI_CsIntervalUnit256SckCycle

Chip selection interval: CSINTERVAL * 256 serial clock cycle.

enum _flexspi_ahb_write_wait_unit

FLEXSPI AHB wait interval unit for writing.

Values:

enumerator kFLEXSPI_AhbWriteWaitUnit2AhbCycle

AWRWAIT unit is 2 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8AhbCycle

AWRWAIT unit is 8 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32AhbCycle

AWRWAIT unit is 32 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit128AhbCycle

AWRWAIT unit is 128 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit512AhbCycle

AWRWAIT unit is 512 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit2048AhbCycle

AWRWAIT unit is 2048 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8192AhbCycle

AWRWAIT unit is 8192 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32768AhbCycle

AWRWAIT unit is 32768 ahb clock cycle.

enum _flexspi_ip_error_code

Error Code when IP command Error detected.

Values:

enumerator kFLEXSPI_IpCmdErrorNoError

No error.

enumerator kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd

IP command with JMP_ON_CS instruction used.

enumerator kFLEXSPI_IpCmdErrorUnknownOpCode

Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence

Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence

Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_IpCmdErrorInvalidAddress

Flash access start address exceed the whole flash address range (A1/A2/B1/B2).

enumerator kFLEXSPI_IpCmdErrorSequenceExecutionTimeout

Sequence execution timeout.

enumerator kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss

Flash boundary crossed.

enum _flexspi_ahb_error_code

Error Code when AHB command Error detected.

Values:

enumerator kFLEXSPI_AhbCmdErrorNoError

No error.

enumerator kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd

AHB Write command with JMP_ON_CS instruction used in the sequence.

enumerator kFLEXSPI_AhbCmdErrorUnknownOpCode

Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence

Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence

Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_AhbCmdSequenceExecutionTimeout

Sequence execution timeout.

enum _flexspi_port

FLEXSPI operation port select.

Values:

enumerator kFLEXSPI_PortA1

Access flash on A1 port.

enumerator kFLEXSPI_PortA2

Access flash on A2 port.

enumerator kFLEXSPI_PortB1

Access flash on B1 port.

enumerator kFLEXSPI_PortB2

Access flash on B2 port.

enumerator kFLEXSPI_PortCount

enum _flexspi_arb_command_source

Trigger source of current command sequence granted by arbitrator.

Values:

enumerator kFLEXSPI_AhbReadCommand

enumerator kFLEXSPI_AhbWriteCommand

enumerator kFLEXSPI_IpCommand

enumerator kFLEXSPI_SuspendedCommand

enum _flexspi_command_type

Command type.

Values:

enumerator kFLEXSPI_Command

FlexSPI operation: Only command, both TX and Rx buffer are ignored.

enumerator kFLEXSPI_Config

FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT.

enumerator kFLEXSPI_Read

enumerator kFLEXSPI_Write

typedef enum _flexspi_pad flexspi_pad_t

pad definition of FLEXSPI, use to form LUT instruction.

typedef enum _flexspi_flags flexspi_flags_t

FLEXSPI interrupt status flags.

typedef enum _flexspi_read_sample_clock flexspi_read_sample_clock_t

FLEXSPI sample clock source selection for Flash Reading.

typedef enum _flexspi_cs_interval_cycle_unit flexspi_cs_interval_cycle_unit_t

FLEXSPI interval unit for flash device select.

typedef enum _flexspi_ahb_write_wait_unit flexspi_ahb_write_wait_unit_t

FLEXSPI AHB wait interval unit for writing.

typedef enum _flexspi_ip_error_code flexspi_ip_error_code_t

Error Code when IP command Error detected.

typedef enum _flexspi_ahb_error_code flexspi_ahb_error_code_t

Error Code when AHB command Error detected.

typedef enum _flexspi_port flexspi_port_t

FLEXSPI operation port select.

typedef enum _flexspi_arb_command_source flexspi_arb_command_source_t

Trigger source of current command sequence granted by arbitrator.

typedef enum _flexspi_command_type flexspi_command_type_t

Command type.

typedef struct _flexspi_ahbBuffer_config flexspi_ahbBuffer_config_t

typedef struct _flexspi_config flexspi_config_t

FLEXSPI configuration structure.

typedef struct _flexspi_device_config flexspi_device_config_t

External device configuration items.

typedef struct _flexspi_transfer flexspi_transfer_t

Transfer structure for FLEXSPI.

typedef struct _flexspi_handle flexspi_handle_t

typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, flexspi_handle_t *handle, status_t status, void *userData)

FLEXSPI transfer callback function.

FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT

FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)

Formula to form FLEXSPI instructions in LUT table.

struct _flexspi_ahbBuffer_config

#include <fsl_flexspi.h>

Public Members

uint8_t priority

This priority for AHB Master Read which this AHB RX Buffer is assigned.

uint8_t masterIndex

AHB Master ID the AHB RX Buffer is assigned.

uint16_t bufferSize

AHB buffer size in byte.

bool enablePrefetch

AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows prefetch disable/enable separately for each master.

struct _flexspi_config

#include <fsl_flexspi.h>

FLEXSPI configuration structure.

Public Members

flexspi_read_sample_clock_t rxSampleClock

Sample Clock source selection for Flash Reading.

bool enableSckFreeRunning

Enable/disable SCK output free-running.

bool enableCombination

Enable/disable combining PORT A and B Data Pins (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode.

bool enableDoze

Enable/disable doze mode support.

bool enableHalfSpeedAccess

Enable/disable divide by 2 of the clock for half speed commands.

bool enableSckBDiffOpt

Enable/disable SCKB pad use as SCKA differential clock output, when enable, Port B flash access is not available.

bool enableSameConfigForAll

Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all.

uint16_t seqTimeoutCycle

Timeout wait cycle for command sequence execution, timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles.

uint8_t ipGrantTimeoutCycle

Timeout wait cycle for IP command grant, timeout after ipGrantTimeoutCycle*1024 AHB clock cycles.

uint8_t txWatermark

FLEXSPI IP transmit watermark value.

uint8_t rxWatermark

FLEXSPI receive watermark value.

struct _flexspi_device_config

#include <fsl_flexspi.h>

External device configuration items.

Public Members

uint32_t flexspiRootClk

FLEXSPI serial root clock.

bool isSck2Enabled

FLEXSPI use SCK2.

uint32_t flashSize

Flash size in KByte.

bool addressShift

Address shift.

flexspi_cs_interval_cycle_unit_t CSIntervalUnit

CS interval unit, 1 or 256 cycle.

uint16_t CSInterval

CS line assert interval, multiply CS interval unit to get the CS line assert interval cycles.

uint8_t CSHoldTime

CS line hold time.

uint8_t CSSetupTime

CS line setup time.

uint8_t dataValidTime

Data valid time for external device.

uint8_t columnspace

Column space size.

bool enableWordAddress

If enable word address.

uint8_t AWRSeqIndex

Sequence ID for AHB write command.

uint8_t AWRSeqNumber

Sequence number for AHB write command.

uint8_t ARDSeqIndex

Sequence ID for AHB read command.

uint8_t ARDSeqNumber

Sequence number for AHB read command.

flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit

AHB write wait unit.

uint16_t AHBWriteWaitInterval

AHB write wait interval, multiply AHB write interval unit to get the AHB write wait cycles.

bool enableWriteMask

Enable/Disable FLEXSPI drive DQS pin as write mask when writing to external device.

struct _flexspi_transfer

#include <fsl_flexspi.h>

Transfer structure for FLEXSPI.

Public Members

uint32_t deviceAddress

Operation device address.

flexspi_port_t port

Operation port.

flexspi_command_type_t cmdType

Execution command type.

uint8_t seqIndex

Sequence ID for command.

uint8_t SeqNumber

Sequence number for command.

uint32_t *data

Data buffer.

size_t dataSize

Data size in bytes.

struct _flexspi_handle

#include <fsl_flexspi.h>

Transfer handle structure for FLEXSPI.

Public Members

uint32_t state

Internal state for FLEXSPI transfer

uint8_t *data

Data buffer.

size_t dataSize

Remaining Data size in bytes.

size_t transferTotalSize

Total Data size in bytes.

flexspi_transfer_callback_t completionCallback

Callback for users while transfer finish or error occurred

void *userData

FLEXSPI callback function parameter.

struct ahbConfig

Public Members

uint8_t ahbGrantTimeoutCycle

Timeout wait cycle for AHB command grant, timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles.

uint16_t ahbBusTimeoutCycle

Timeout wait cycle for AHB read/write access, timeout after ahbBusTimeoutCycle*1024 AHB clock cycles.

uint8_t resumeWaitCycle

Wait cycle for idle state before suspended command sequence resume, timeout after ahbBusTimeoutCycle AHB clock cycles.

flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]

AHB buffer size.

bool enableClearAHBBufferOpt

Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK.

bool enableReadAddressOpt

Enable/disable remove AHB read burst start address alignment limitation. when enable, there is no AHB read burst start address alignment limitation.

bool enableAHBPrefetch

Enable/disable AHB read prefetch feature, when enabled, FLEXSPI will fetch more data than current AHB burst.

bool enableAHBBufferable

Enable/disable AHB bufferable write access support, when enabled, FLEXSPI return before waiting for command execution finished.

bool enableAHBCachable

Enable AHB bus cachable read access support.

FLEXSPI eDMA Driver

void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)

Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.

Parameters:

• base – FLEXSPI peripheral base address

• handle – Pointer to flexspi_edma_handle_t structure

• callback – FLEXSPI callback, NULL means no callback.

• userData – User callback function data.

• txDmaHandle – User requested DMA handle for TX DMA transfer.

• rxDmaHandle – User requested DMA handle for RX DMA transfer.

void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_transfer_nsize_t nsize)

Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).

See also

flexspi_edma_transfer_nsize_t .

Parameters:

• base – FLEXSPI peripheral base address

• handle – Pointer to flexspi_edma_handle_t structure

• nsize – FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is kFLEXPSI_EDMAnSize1Bytes(one byte).

status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_transfer_t *xfer)

Transfers FLEXSPI data using an eDMA non-blocking method.

This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure

• xfer – FLEXSPI transfer structure.

Return values:

• kStatus_FLEXSPI_Busy – FLEXSPI is busy transfer.

• kStatus_InvalidArgument – The watermark configuration is invalid, the watermark should be power of 2 to do successfully EDMA transfer.

• kStatus_Success – FLEXSPI successfully start edma transfer.

void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle)

Aborts the transfer data using eDMA.

This function aborts the transfer data using eDMA.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure

status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count)

Gets the transferred counts of transfer.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure.

• count – Bytes transfer.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXSPI_EDMA_DRIVER_VERSION

FLEXSPI EDMA driver version.

enum _flexspi_edma_ntransfer_size

eDMA transfer configuration

Values:

enumerator kFLEXPSI_EDMAnSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kFLEXPSI_EDMAnSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kFLEXPSI_EDMAnSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kFLEXPSI_EDMAnSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kFLEXPSI_EDMAnSize32Bytes

Source/Destination data transfer size is 32 bytes every time

typedef struct _flexspi_edma_handle flexspi_edma_handle_t

typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)

FLEXSPI eDMA transfer callback function for finish and error.

typedef enum _flexspi_edma_ntransfer_size flexspi_edma_transfer_nsize_t

eDMA transfer configuration

struct _flexspi_edma_handle

#include <fsl_flexspi_edma.h>

FLEXSPI DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *txDmaHandle

eDMA handler for FLEXSPI Tx.

edma_handle_t *rxDmaHandle

eDMA handler for FLEXSPI Rx.

size_t transferSize

Bytes need to transfer.

flexspi_edma_transfer_nsize_t nsize

eDMA SSIZE/DSIZE in each transfer.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint8_t count

The transfer data count in a DMA request.

uint32_t state

Internal state for FLEXSPI eDMA transfer.

flexspi_edma_callback_t completionCallback

A callback function called after the eDMA transfer is finished.

void *userData

User callback parameter

Gpc

static inline void GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_Type *base, bool enable)

static inline void GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode)

Set the CPU mode on the next sleep event.

This function configures the CPU mode that the CPU core will transmit to on next sleep event.

Note

This API must be called each time before entering sleep.

Parameters:

• base – GPC CPU module base address.

• mode – The CPU mode that the core will transmit to, refer to “gpc_cpu_mode_t”.

static inline gpc_cpu_mode_t GPC_CM_GetCurrentCpuMode(GPC_CPU_MODE_CTRL_Type *base)

Get current CPU mode.

Parameters:

• base – GPC CPU module base address.

Returns:

The current CPU mode, in type of gpc_cpu_mode_t.

static inline gpc_cpu_mode_t GPC_CM_GetPreviousCpuMode(GPC_CPU_MODE_CTRL_Type *base)

Get previous CPU mode.

Parameters:

• base – GPC CPU module base address.

Returns:

The previous CPU mode, in type of gpc_cpu_mode_t.

void GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId, bool enable)

Enable IRQ wakeup request.

This function enables the IRQ request which can wakeup the CPU platform.

Parameters:

• base – GPC CPU module base address.

• irqId – ID of the IRQ, accessible range is 0-255.

• enable – Enable the IRQ request or not.

static inline void GPC_CM_EnableNonIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask, bool enable)

Enable Non-IRQ wakeup request.

This function enables the non-IRQ request which can wakeup the CPU platform.

Parameters:

• base – GPC CPU module base address.

• mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.

• enable – Enable the Non-IRQ request or not.

bool GPC_CM_GetIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId)

Get the status of the IRQ wakeup request.

Parameters:

• base – GPC CPU module base address.

• irqId – ID of the IRQ, accessible range is 0-255.

Returns:

Indicate the IRQ request is asserted or not.

static inline bool GPC_CM_GetNonIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)

Get the status of the Non-IRQ wakeup request.

Parameters:

• base – GPC CPU module base address.

• mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.

Returns:

Indicate the Non-IRQ request is asserted or not.

void GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, gpc_cm_tran_step_t step, const gpc_tran_step_config_t *config)

Config the cpu mode transition step.

Deprecated:

Please use GPC_CM_EnableCpuModeTransitionStep() and GPC_CM_DisableCpuModeTransitionStep() as instead.

Note

This function can not config the setpoint sleep/wakeup operation for those operation is controlled by setpoint control. This funcion can not config the standby sleep/wakeup too, because those operation is controlled by standby controlled.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

• config – transition step configuration, refer to “gpc_tran_step_config_t”.

void GPC_CM_EnableCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, gpc_cm_tran_step_t step)

Enable the specific cpu mode transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

void GPC_CM_DisableCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, gpc_cm_tran_step_t step)

Disable the specific cpu mode transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

void GPC_CM_RequestSleepModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointSleep, uint8_t setPointWakeup, gpc_cm_wakeup_sp_sel_t wakeupSel)

Request a set point transition before the CPU transfers into a sleep mode.

This function triggers the set point transition during a CPU Sleep/wakeup event and selects which one the CMC want to transfer to.

Parameters:

• base – GPC CPU module base address.

• setPointSleep – The set point CPU want the system to transit to on next CPU platform sleep sequence.

• setPointWakeup – The set point CPU want the system to transit to on next CPU platform wakeup sequence.

• wakeupSel – Select the set point transition on the next CPU platform wakeup sequence.

void GPC_CM_RequestRunModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointRun)

Request a set point transition during run mode.

This function triggers the set point transition and selects which one the CMC want to transfer to.

Parameters:

• base – GPC CPU module base address.

• setPointRun – The set point CPU want the system to transit in the run mode.

static inline void GPC_CM_SetSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, uint32_t setPoint, uint32_t setpoint_map)

Set the set point mapping value for each set point.

This function configures which set point is allowed after current set point. If there are multiple setpoints, use:

setpoint_map = kGPC_SetPoint0 | kGPC_SetPoint1 | ... | kGPC_SetPoint15;

Parameters:

• base – GPC CPU module base address.

• setPoint – Set point index, available range is 0-15.

• setpoint_map – Map value of the set point. Refer to “_gpc_setpoint_map”.

void GPC_CM_SetCpuModeSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode, uint32_t setpoint_map)

Set the set point mapping value for each cpu mode.

This function configures which set point is allowed when CPU enters RUN/WAIT/STOP/SUSPEND. If there are multiple setpoints, use:

setpoint_map = kGPC_SetPoint0 | kGPC_SetPoint1 | ... | kGPC_SetPoint15;

Parameters:

• base – GPC CPU module base address.

• mode – CPU mode. Refer to “gpc_cpu_mode_t”.

• setpoint_map – Map value of the set point. Refer to “_gpc_setpoint_map”.

void GPC_CM_RequestStandbyMode(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode)

Request the chip into standby mode.

Parameters:

• base – GPC CPU module base address.

• mode – CPU mode. Refer to “gpc_cpu_mode_t”.

void GPC_CM_ClearStandbyModeRequest(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode)

Clear the standby mode request.

Parameters:

• base – GPC CPU module base address.

• mode – CPU mode. Refer to “gpc_cpu_mode_t”.

static inline bool GPC_CM_GetStandbyModeStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)

Get the status of the CPU standby mode transition.

Parameters:

• base – GPC CPU module base address.

• mask – Standby mode transition status mask, refer to “gpc_cm_standby_mode_status_t”.

Returns:

Indicate the CPU’s standby transition status.

static inline uint32_t GPC_CM_GetInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base)

Get the status flags of the GPC CPU module.

Parameters:

• base – GPC CPU module base address.

Returns:

The OR’ed value of status flags.

void GPC_CM_ClearInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask)

Clears CPU module interrut status flags.

Parameters:

• base – GPC CPU module base address.

• mask – The interrupt status flags to be cleared. Should be the OR’ed value of _gpc_cm_interrupt_status_flag.

static inline void GPC_SP_SetSetpointPriority(GPC_SET_POINT_CTRL_Type *base, uint32_t setPoint, uint32_t priority)

Set the priority of set point.

This function will configure the priority of the set point. If the result of API GPC_SP_GetAllowedSetPointMap() has more than one valid bit, high priority set point will be taken.

Parameters:

• base – GPC Setpoint controller base address.

• setPoint – Set point index, available range is 0-15.

• priority – Priority level, available range is 0-15.

void GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, gpc_sp_tran_step_t step, const gpc_tran_step_config_t *config)

Config the set point transition step.

Deprecated:

Please use GPC_SP_EnableSetPointTransitionStep() and GPC_SP_DisableSetPointTransitionStep() as instead.

Parameters:

• base – GPC Setpoint controller base address.

• step – step type, refer to “gpc_sp_tran_step_t”.

• config – transition step configuration, refer to “gpc_tran_step_config_t”.

void GPC_SP_EnableSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, gpc_sp_tran_step_t step)

Enable the specific setpoint transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

void GPC_SP_DisableSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, gpc_sp_tran_step_t step)

Disable the specific setpoint transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

static inline uint8_t GPC_SP_GetCurrentSetPoint(GPC_SET_POINT_CTRL_Type *base)

Get system current setpoint, only valid when setpoint trans not busy.

Parameters:

• base – GPC Setpoint controller base address.

Returns:

The current setpoint number, range from 0 to 15.

static inline uint8_t GPC_SP_GetPreviousSetPoint(GPC_SET_POINT_CTRL_Type *base)

Get system previous setpoint, only valid when setpoint trans not busy.

Parameters:

• base – GPC Setpoint controller base address.

Returns:

The previous setpoint number, range from 0 to 15.

static inline uint8_t GPC_SP_GetTargetSetPoint(GPC_SET_POINT_CTRL_Type *base)

Get target setpoint.

Parameters:

• base – GPC Setpoint controller base address.

Returns:

The target setpoint number, range from 0 to 15.

void GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL_Type *base, gpc_stby_tran_step_t step, const gpc_tran_step_config_t *config)

Config the standby transition step.

Deprecated:

Please use GPC_STBY_EnableStandbyTransitionStep() and GPC_STBY_DisableStandbyTransitionStep() as instead.

Parameters:

• base – GPC standby controller base address.

• step – step type, refer to “gpc_stby_tran_step_t”.

• config – transition step configuration, refer to “gpc_tran_step_config_t”.

void GPC_STBY_EnableStandbyTransitionStep(GPC_STBY_CTRL_Type *base, gpc_stby_tran_step_t step)

Enable the specific standby transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

void GPC_STBY_DisableStandbyTransitionStep(GPC_STBY_CTRL_Type *base, gpc_stby_tran_step_t step)

Disable the specific standby transition step.

Parameters:

• base – GPC CPU module base address.

• step – step type, refer to “gpc_cm_tran_step_t”.

void GPC_STBY_SetPmicOutStepCountMode(GPC_STBY_CTRL_Type *base, gpc_tran_step_counter_mode_t cntMode, uint32_t stepCount)

Set count mode for PMIC_OUT Step.

Parameters:

• base – GPC CPU module base address.

• cntMode – Step counter working mode.

• stepCount – Step count, which is depended on the value of cntMode

static inline void GPC_STBY_ForceCoreRequestStandbyMode(GPC_STBY_CTRL_Type *base, gpc_cpu_domain_name_t cpuName)

Force selected CPU requesting standby mode.

Parameters:

• base – GPC standby controller base address.

• cpuName – The CPU name, refer to gpc_cpu_domain_name_t.

FSL_GPC_RIVER_VERSION

GPC driver version 2.5.0.

_gpc_cm_non_irq_wakeup_request GPC Non-IRQ wakeup request.

Values:

enumerator kGPC_CM_EventWakeupRequest

Event wakeup request.

enumerator kGPC_CM_DebugWakeupRequest

Debug wakeup request.

Values:

enumerator kGPC_SetPoint0

GPC set point 0.

enumerator kGPC_SetPoint1

GPC set point 1.

enumerator kGPC_SetPoint2

GPC set point 2.

enumerator kGPC_SetPoint3

GPC set point 3.

enumerator kGPC_SetPoint4

GPC set point 4.

enumerator kGPC_SetPoint5

GPC set point 5.

enumerator kGPC_SetPoint6

GPC set point 6.

enumerator kGPC_SetPoint7

GPC set point 7.

enumerator kGPC_SetPoint8

GPC set point 8.

enumerator kGPC_SetPoint9

GPC set point 9.

enumerator kGPC_SetPoint10

GPC set point 10.

enumerator kGPC_SetPoint11

GPC set point 11.

enumerator kGPC_SetPoint12

GPC set point 12.

enumerator kGPC_SetPoint13

GPC set point 13.

enumerator kGPC_SetPoint14

GPC set point 14.

enumerator kGPC_SetPoint15

GPC set point 15.

_gpc_cm_interrupt_status_flag

Values:

enumerator kGPC_CM_SoftSPNotAllowedStatusFlag

enumerator kGPC_CM_WaitSPNotAllowedStatusFlag

enumerator kGPC_CM_SleepSPNotAllowedStatusFlag

enum _gpc_cm_standby_mode_status

CPU standby mode status.

Values:

enumerator kGPC_CM_SleepBusy

Indicate the CPU is busy entering standby mode.

enumerator kGPC_CM_WakeupBusy

Indicate the CPU is busy exiting standby mode.

enum _gpc_cm_tran_step

CPU mode transition step in sleep/wakeup sequence.

Values:

enumerator kGPC_CM_SleepSsar

SSAR (State Save And Restore) sleep step.

enumerator kGPC_CM_SleepLpcg

LPCG (Low Power Clock Gating) sleep step.

enumerator kGPC_CM_SleepPll

PLL sleep step.

enumerator kGPC_CM_SleepIso

ISO (Isolation) sleep step.

enumerator kGPC_CM_SleepReset

Reset sleep step.

enumerator kGPC_CM_SleepPower

Power sleep step.

enumerator kGPC_CM_SleepSP

Setpoint sleep step. Note that this step is controlled by setpoint controller.

enumerator kGPC_CM_SleepSTBY

Standby sleep step. Note that this step is controlled by standby controller.

enumerator kGPC_CM_WakeupSTBY

Standby wakeup step. Note that this step is controlled by standby controller.

enumerator kGPC_CM_WakeupSP

Setpoint wakeup step. Note that this step is controlled by setpoint countroller.

enumerator kGPC_CM_WakeupPower

Power wakeup step.

enumerator kGPC_CM_WakeupReset

Reset wakeup step.

enumerator kGPC_CM_WakeupIso

ISO wakeup step.

enumerator kGPC_CM_WakeupPll

PLL wakeup step.

enumerator kGPC_CM_WakeupLpcg

LPCG wakeup step.

enumerator kGPC_CM_WakeupSsar

SSAR wakeup step.

enum _gpc_sp_tran_step

GPC set point transition steps.

Values:

enumerator kGPC_SP_SsarSave

SSAR save step.

enumerator kGPC_SP_LpcgOff

LPCG off step.

enumerator kGPC_SP_GroupDown

Group down step.

enumerator kGPC_SP_RootDown

Root down step.

enumerator kGPC_SP_PllOff

PLL off step.

enumerator kGPC_SP_IsoOn

ISO on.

enumerator kGPC_SP_ResetEarly

Reset early step.

enumerator kGPC_SP_PowerOff

Power off step.

enumerator kGPC_SP_BiasOff

Bias off step.

enumerator kGPC_SP_BandgapPllLdoOff

Bandgap and PLL_LDO off step.

enumerator kGPC_SP_LdoPre

LDO (Low-Dropout) pre step.

enumerator kGPC_SP_DcdcDown

DCDC down step.

enumerator kGPC_SP_DcdcUp

DCDC up step.

enumerator kGPC_SP_LdoPost

LDO post step.

enumerator kGPC_SP_BandgapPllLdoOn

Bandgap and PLL_LDO on step.

enumerator kGPC_SP_BiasOn

Bias on step.

enumerator kGPC_SP_PowerOn

Power on step.

enumerator kGPC_SP_ResetLate

Reset late step.

enumerator kGPC_SP_IsoOff

ISO off step.

enumerator kGPC_SP_PllOn

PLL on step

enumerator kGPC_SP_RootUp

Root up step.

enumerator kGPC_SP_GroupUp

Group up step.

enumerator kGPC_SP_LpcgOn

LPCG on step.

enumerator kGPC_SP_SsarRestore

SSAR restore step.

enum _gpc_cpu_mode

CPU mode.

Values:

enumerator kGPC_RunMode

Stay in RUN mode.

enumerator kGPC_WaitMode

Transit to WAIT mode.

enumerator kGPC_StopMode

Transit to STOP mode.

enumerator kGPC_SuspendMode

Transit to SUSPEND mode.

enum _gpc_cm_wakeup_sp_sel

CPU wakeup sequence setpoint options.

Values:

enumerator kGPC_CM_WakeupSetpoint

Request SP transition to CPU_SP_WAKEUP (param “setPointWakeup” in gpc_cm_sleep_sp_tran_config_t).

enumerator kGPC_CM_RequestPreviousSetpoint

Request SP transition to the set point when the sleep event happens.

enum _gpc_stby_tran_step

GPC standby mode transition steps.

Values:

enumerator kGPC_STBY_LpcgIn

LPCG in step.

enumerator kGPC_STBY_PllIn

PLL in step.

enumerator kGPC_STBY_BiasIn

Bias in step.

enumerator kGPC_STBY_PldoIn

PLDO in step.

enumerator kGPC_STBY_BandgapIn

Bandgap in step.

enumerator kGPC_STBY_LdoIn

LDO in step.

enumerator kGPC_STBY_DcdcIn

DCDC in step.

enumerator kGPC_STBY_PmicIn

PMIC in step.

enumerator kGPC_STBY_PmicOut

PMIC out step.

enumerator kGPC_STBY_DcdcOut

DCDC out step.

enumerator kGPC_STBY_LdoOut

LDO out step.

enumerator kGPC_STBY_BandgapOut

Bandgap out step.

enumerator kGPC_STBY_PldoOut

PLDO out step.

enumerator kGPC_STBY_BiasOut

Bias out step.

enumerator kGPC_STBY_PllOut

PLL out step.

enumerator kGPC_STBY_LpcgOut

LPCG out step.

enum _gpc_cpu_domain_name

GPC CPU domain name, used to select the CPU domain.

Values:

enumerator kGPC_CM7Core

CM7 core.

enumerator kGPC_CM4Core

CM4 core.

enum _gpc_tran_step_counter_mode

Step counter work mode.

Values:

enumerator kGPC_StepCounterDisableMode

Counter disable mode: not use step counter, step completes once receiving step_done.

enumerator kGPC_StepCounterDelayMode

Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT

enumerator kGPC_StepCounterIgnoreResponseMode

Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes.

enumerator kGPC_StepCounterTimeOutMode

Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value.

typedef enum _gpc_cm_standby_mode_status gpc_cm_standby_mode_status_t

CPU standby mode status.

typedef enum _gpc_cm_tran_step gpc_cm_tran_step_t

CPU mode transition step in sleep/wakeup sequence.

typedef enum _gpc_sp_tran_step gpc_sp_tran_step_t

GPC set point transition steps.

typedef enum _gpc_cpu_mode gpc_cpu_mode_t

CPU mode.

typedef struct _gpc_tran_step_config gpc_tran_step_config_t

Configuration for GPC transition step.

Deprecated:

Related functions are deprecated.

typedef enum _gpc_cm_wakeup_sp_sel gpc_cm_wakeup_sp_sel_t

CPU wakeup sequence setpoint options.

typedef enum _gpc_stby_tran_step gpc_stby_tran_step_t

GPC standby mode transition steps.

typedef enum _gpc_cpu_domain_name gpc_cpu_domain_name_t

GPC CPU domain name, used to select the CPU domain.

typedef enum _gpc_tran_step_counter_mode gpc_tran_step_counter_mode_t

Step counter work mode.

GPC_RESERVED_USE_MACRO

GPC_CM_SLEEP_SSAR_CTRL_OFFSET

GPC_CM_SLEEP_LPCG_CTRL_OFFSET

GPC_CM_SLEEP_PLL_CTRL_OFFSET

GPC_CM_SLEEP_ISO_CTRL_OFFSET

GPC_CM_SLEEP_RESET_CTRL_OFFSET

GPC_CM_SLEEP_POWER_CTRL_OFFSET

GPC_CM_WAKEUP_POWER_CTRL_OFFSET

GPC_CM_WAKEUP_RESET_CTRL_OFFSET

GPC_CM_WAKEUP_ISO_CTRL_OFFSET

GPC_CM_WAKEUP_PLL_CTRL_OFFSET

GPC_CM_WAKEUP_LPCG_CTRL_OFFSET

GPC_CM_WAKEUP_SSAR_CTRL_OFFSET

GPC_SP_SSAR_SAVE_CTRL_OFFSET

GPC_SP_LPCG_OFF_CTRL_OFFSET

GPC_SP_GROUP_DOWN_CTRL_OFFSET

GPC_SP_ROOT_DOWN_CTRL_OFFSET

GPC_SP_PLL_OFF_CTRL_OFFSET

GPC_SP_ISO_ON_CTRL_OFFSET

GPC_SP_RESET_EARLY_CTRL_OFFSET

GPC_SP_POWER_OFF_CTRL_OFFSET

GPC_SP_BIAS_OFF_CTRL_OFFSET

GPC_SP_BG_PLDO_OFF_CTRL_OFFSET

GPC_SP_LDO_PRE_CTRL_OFFSET

GPC_SP_DCDC_DOWN_CTRL_OFFSET

GPC_SP_DCDC_UP_CTRL_OFFSET

GPC_SP_LDO_POST_CTRL_OFFSET

GPC_SP_BG_PLDO_ON_CTRL_OFFSET

GPC_SP_BIAS_ON_CTRL_OFFSET

GPC_SP_POWER_ON_CTRL_OFFSET

GPC_SP_RESET_LATE_CTRL_OFFSET

GPC_SP_ISO_OFF_CTRL_OFFSET

GPC_SP_PLL_ON_CTRL_OFFSET

GPC_SP_ROOT_UP_CTRL_OFFSET

GPC_SP_GROUP_UP_CTRL_OFFSET

GPC_SP_LPCG_ON_CTRL_OFFSET

GPC_SP_SSAR_RESTORE_CTRL_OFFSET

GPC_STBY_LPCG_IN_CTRL_OFFSET

GPC_STBY_PLL_IN_CTRL_OFFSET

GPC_STBY_BIAS_IN_CTRL_OFFSET

GPC_STBY_PLDO_IN_CTRL_OFFSET

GPC_STBY_BANDGAP_IN_CTRL_OFFSET

GPC_STBY_LDO_IN_CTRL_OFFSET

GPC_STBY_DCDC_IN_CTRL_OFFSET

GPC_STBY_PMIC_IN_CTRL_OFFSET

GPC_STBY_PMIC_OUT_CTRL_OFFSET

GPC_STBY_DCDC_OUT_CTRL_OFFSET

GPC_STBY_LDO_OUT_CTRL_OFFSET

GPC_STBY_BANDGAP_OUT_CTRL_OFFSET

GPC_STBY_PLDO_OUT_CTRL_OFFSET

GPC_STBY_BIAS_OUT_CTRL_OFFSET

GPC_STBY_PLL_OUT_CTRL_OFFSET

GPC_STBY_LPCG_OUT_CTRL_OFFSET

GPC_CM_STEP_REG_OFFSET

GPC_SP_STEP_REG_OFFSET

GPC_STBY_STEP_REG_OFFSET

GPC_STAT(mask, shift)

GPC_CM_ALL_INTERRUPT_STATUS

struct _gpc_tran_step_config

#include <fsl_gpc.h>

Configuration for GPC transition step.

Deprecated:

Related functions are deprecated.

Public Members

bool enableStep

Enable the step.

GPIO: General-Purpose Input/Output Driver

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)

Initializes the GPIO peripheral according to the specified parameters in the initConfig.

Parameters:

• base – GPIO base pointer.

• pin – Specifies the pin number

• Config – pointer to a gpio_pin_config_t structure that contains the configuration information.

void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the individual GPIO pin to logic 1 or 0.

Parameters:

• base – GPIO base pointer.

• pin – GPIO port pin number.

• output – GPIOpin output logic level.

  • 0: corresponding pin output low-logic level.

  • 1: corresponding pin output high-logic level.

static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the individual GPIO pin to logic 1 or 0.

Deprecated:

Do not use this function. It has been superceded by GPIO_PinWrite.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

• base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Deprecated:

Do not use this function. It has been superceded by GPIO_PortSet.

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

• base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Deprecated:

Do not use this function. It has been superceded by GPIO_PortClear.

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple GPIO pins.

Parameters:

• base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)

• mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Parameters:

• base – GPIO base pointer.

• pin – GPIO port pin number.

Return values:

GPIO – port input value.

static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Deprecated:

Do not use this function. It has been superceded by GPIO_PinRead.

static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)

Reads the current GPIO pin pad status.

Parameters:

• base – GPIO base pointer.

• pin – GPIO port pin number.

Return values:

GPIO – pin pad status value.

static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)

Reads the current GPIO pin pad status.

Deprecated:

Do not use this function. It has been superceded by GPIO_PinReadPadStatus.

void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)

Sets the current pin interrupt mode.

Parameters:

• base – GPIO base pointer.

• pin – GPIO port pin number.

• pinInterruptMode – pointer to a gpio_interrupt_mode_t structure that contains the interrupt mode information.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)

Sets the current pin interrupt mode.

Deprecated:

Do not use this function. It has been superceded by GPIO_PinSetInterruptConfig.

static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)

Enables the specific pin interrupt.

Parameters:

• base – GPIO base pointer.

• mask – GPIO pin number macro.

static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)

Enables the specific pin interrupt.

Parameters:

• base – GPIO base pointer.

• mask – GPIO pin number macro.

static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)

Disables the specific pin interrupt.

Parameters:

• base – GPIO base pointer.

• mask – GPIO pin number macro.

static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)

Disables the specific pin interrupt.

Deprecated:

Do not use this function. It has been superceded by GPIO_PortDisableInterrupts.

static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)

Reads individual pin interrupt status.

Parameters:

• base – GPIO base pointer.

Return values:

current – pin interrupt status flag.

static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)

Reads individual pin interrupt status.

Parameters:

• base – GPIO base pointer.

Return values:

current – pin interrupt status flag.

static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears pin interrupt flag. Status flags are cleared by writing a 1 to the corresponding bit position.

Parameters:

• base – GPIO base pointer.

• mask – GPIO pin number macro.

static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears pin interrupt flag. Status flags are cleared by writing a 1 to the corresponding bit position.

Parameters:

• base – GPIO base pointer.

• mask – GPIO pin number macro.

FSL_GPIO_DRIVER_VERSION

GPIO driver version.

enum _gpio_pin_direction

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput

Set current pin as digital input.

enumerator kGPIO_DigitalOutput

Set current pin as digital output.

enum _gpio_interrupt_mode

GPIO interrupt mode definition.

Values:

enumerator kGPIO_NoIntmode

Set current pin general IO functionality.

enumerator kGPIO_IntLowLevel

Set current pin interrupt is low-level sensitive.

enumerator kGPIO_IntHighLevel

Set current pin interrupt is high-level sensitive.

enumerator kGPIO_IntRisingEdge

Set current pin interrupt is rising-edge sensitive.

enumerator kGPIO_IntFallingEdge

Set current pin interrupt is falling-edge sensitive.

enumerator kGPIO_IntRisingOrFallingEdge

Enable the edge select bit to override the ICR register’s configuration.

typedef enum _gpio_pin_direction gpio_pin_direction_t

GPIO direction definition.

typedef enum _gpio_interrupt_mode gpio_interrupt_mode_t

GPIO interrupt mode definition.

typedef struct _gpio_pin_config gpio_pin_config_t

GPIO Init structure definition.

struct _gpio_pin_config

#include <fsl_gpio.h>

GPIO Init structure definition.

Public Members

gpio_pin_direction_t direction

Specifies the pin direction.

uint8_t outputLogic

Set a default output logic, which has no use in input

gpio_interrupt_mode_t interruptMode

Specifies the pin interrupt mode, a value of gpio_interrupt_mode_t.

GPT: General Purpose Timer

void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)

Initialize GPT to reset state and initialize running mode.

Parameters:

• base – GPT peripheral base address.

• initConfig – GPT mode setting configuration.

void GPT_Deinit(GPT_Type *base)

Disables the module and gates the GPT clock.

Parameters:

• base – GPT peripheral base address.

void GPT_GetDefaultConfig(gpt_config_t *config)

Fills in the GPT configuration structure with default settings.

The default values are:

config->clockSource = kGPT_ClockSource_Periph;
config->divider = 1U;
config->enableRunInStop = true;
config->enableRunInWait = true;
config->enableRunInDoze = false;
config->enableRunInDbg = false;
config->enableFreeRun = false;
config->enableMode  = true;

Parameters:

• config – Pointer to the user configuration structure.

static inline void GPT_SoftwareReset(GPT_Type *base)

Software reset of GPT module.

Parameters:

• base – GPT peripheral base address.

static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)

Set clock source of GPT.

Parameters:

• base – GPT peripheral base address.

• gptClkSource – Clock source (see gpt_clock_source_t typedef enumeration).

static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)

Get clock source of GPT.

Parameters:

• base – GPT peripheral base address.

Returns:

clock source (see gpt_clock_source_t typedef enumeration).

static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)

Set pre scaler of GPT.

Parameters:

• base – GPT peripheral base address.

• divider – Divider of GPT (1-4096).

static inline uint32_t GPT_GetClockDivider(GPT_Type *base)

Get clock divider in GPT module.

Parameters:

• base – GPT peripheral base address.

Returns:

clock divider in GPT module (1-4096).

static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)

OSC 24M pre-scaler before selected by clock source.

Parameters:

• base – GPT peripheral base address.

• divider – OSC Divider(1-16).

static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)

Get OSC 24M clock divider in GPT module.

Parameters:

• base – GPT peripheral base address.

Returns:

OSC clock divider in GPT module (1-16).

static inline void GPT_StartTimer(GPT_Type *base)

Start GPT timer.

Parameters:

• base – GPT peripheral base address.

static inline void GPT_StopTimer(GPT_Type *base)

Stop GPT timer.

Parameters:

• base – GPT peripheral base address.

static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)

Reads the current GPT counting value.

Parameters:

• base – GPT peripheral base address.

Returns:

Current GPT counter value.

static inline void GPT_SetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)

Set GPT operation mode of input capture channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

• mode – GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT operation mode of input capture channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT input capture value of certain channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture value.

static inline void GPT_SetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)

Set GPT operation mode of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

• mode – GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT operation mode of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)

Set GPT output compare value of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

• value – GPT output compare value.

static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT output compare value of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output compare value.

static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)

Force GPT output action on output compare channel, ignoring comparator.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)

Enables the selected GPT interrupts.

Parameters:

• base – GPT peripheral base address.

• mask – The interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)

Disables the selected GPT interrupts.

Parameters:

• base – GPT peripheral base address

• mask – The interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)

Gets the enabled GPT interrupts.

Parameters:

• base – GPT peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Get GPT status flags.

Parameters:

• base – GPT peripheral base address.

• flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

Returns:

GPT status, each bit represents one status flag.

static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Clears the GPT status flags.

Parameters:

• base – GPT peripheral base address.

• flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

FSL_GPT_DRIVER_VERSION

enum _gpt_clock_source

List of clock sources.

Note

Actual number of clock sources is SoC dependent

Values:

enumerator kGPT_ClockSource_Off

GPT Clock Source Off.

enumerator kGPT_ClockSource_Periph

GPT Clock Source from Peripheral Clock.

enumerator kGPT_ClockSource_HighFreq

GPT Clock Source from High Frequency Reference Clock.

enumerator kGPT_ClockSource_Ext

GPT Clock Source from external pin.

enumerator kGPT_ClockSource_LowFreq

GPT Clock Source from Low Frequency Reference Clock.

enumerator kGPT_ClockSource_Osc

GPT Clock Source from Crystal oscillator.

enum _gpt_input_capture_channel

List of input capture channel number.

Values:

enumerator kGPT_InputCapture_Channel1

GPT Input Capture Channel1.

enumerator kGPT_InputCapture_Channel2

GPT Input Capture Channel2.

enum _gpt_input_operation_mode

List of input capture operation mode.

Values:

enumerator kGPT_InputOperation_Disabled

Don’t capture.

enumerator kGPT_InputOperation_RiseEdge

Capture on rising edge of input pin.

enumerator kGPT_InputOperation_FallEdge

Capture on falling edge of input pin.

enumerator kGPT_InputOperation_BothEdge

Capture on both edges of input pin.

enum _gpt_output_compare_channel

List of output compare channel number.

Values:

enumerator kGPT_OutputCompare_Channel1

Output Compare Channel1.

enumerator kGPT_OutputCompare_Channel2

Output Compare Channel2.

enumerator kGPT_OutputCompare_Channel3

Output Compare Channel3.

enum _gpt_output_operation_mode

List of output compare operation mode.

Values:

enumerator kGPT_OutputOperation_Disconnected

Don’t change output pin.

enumerator kGPT_OutputOperation_Toggle

Toggle output pin.

enumerator kGPT_OutputOperation_Clear

Set output pin low.

enumerator kGPT_OutputOperation_Set

Set output pin high.

enumerator kGPT_OutputOperation_Activelow

Generate a active low pulse on output pin.

enum _gpt_interrupt_enable

List of GPT interrupts.

Values:

enumerator kGPT_OutputCompare1InterruptEnable

Output Compare Channel1 interrupt enable

enumerator kGPT_OutputCompare2InterruptEnable

Output Compare Channel2 interrupt enable

enumerator kGPT_OutputCompare3InterruptEnable

Output Compare Channel3 interrupt enable

enumerator kGPT_InputCapture1InterruptEnable

Input Capture Channel1 interrupt enable

enumerator kGPT_InputCapture2InterruptEnable

Input Capture Channel1 interrupt enable

enumerator kGPT_RollOverFlagInterruptEnable

Counter rolled over interrupt enable

enum _gpt_status_flag

Status flag.

Values:

enumerator kGPT_OutputCompare1Flag

Output compare channel 1 event.

enumerator kGPT_OutputCompare2Flag

Output compare channel 2 event.

enumerator kGPT_OutputCompare3Flag

Output compare channel 3 event.

enumerator kGPT_InputCapture1Flag

Input Capture channel 1 event.

enumerator kGPT_InputCapture2Flag

Input Capture channel 2 event.

enumerator kGPT_RollOverFlag

Counter reaches maximum value and rolled over to 0 event.

typedef enum _gpt_clock_source gpt_clock_source_t

List of clock sources.

Note

Actual number of clock sources is SoC dependent

typedef enum _gpt_input_capture_channel gpt_input_capture_channel_t

List of input capture channel number.

typedef enum _gpt_input_operation_mode gpt_input_operation_mode_t

List of input capture operation mode.

typedef enum _gpt_output_compare_channel gpt_output_compare_channel_t

List of output compare channel number.

typedef enum _gpt_output_operation_mode gpt_output_operation_mode_t

List of output compare operation mode.

typedef enum _gpt_interrupt_enable gpt_interrupt_enable_t

List of GPT interrupts.

typedef enum _gpt_status_flag gpt_status_flag_t

Status flag.

typedef struct _gpt_init_config gpt_config_t

Structure to configure the running mode.

struct _gpt_init_config

#include <fsl_gpt.h>

Structure to configure the running mode.

Public Members

gpt_clock_source_t clockSource

clock source for GPT module.

uint32_t divider

clock divider (prescaler+1) from clock source to counter.

bool enableFreeRun

true: FreeRun mode, false: Restart mode.

bool enableRunInWait

GPT enabled in wait mode.

bool enableRunInStop

GPT enabled in stop mode.

bool enableRunInDoze

GPT enabled in doze mode.

bool enableRunInDbg

GPT enabled in debug mode.

bool enableMode

true: counter reset to 0 when enabled; false: counter retain its value when enabled.

Iee

FSL_IEE_DRIVER_VERSION

IEE driver version. Version 2.1.1.

Current version: 2.1.1

Change log:

• Version 2.0.0

  • Initial version

• Version 2.1.0

  • Add region lock function IEE_LockRegionConfig() and driver clock control

• Version 2.1.1

  • Fixed MISRA issues.

• Version 2.2.0

  • Add ELE (EdgeLock Enclave) key provisioning feature.

enum _iee_region

IEE region.

Values:

enumerator kIEE_Region0

IEE region 0

enumerator kIEE_Region1

IEE region 1

enumerator kIEE_Region2

IEE region 2

enumerator kIEE_Region3

IEE region 3

enumerator kIEE_Region4

IEE region 4

enumerator kIEE_Region5

IEE region 5

enumerator kIEE_Region6

IEE region 6

enumerator kIEE_Region7

IEE region 7

enum _iee_aes_bypass

IEE AES enablement/bypass.

Values:

enumerator kIEE_AesUseMdField

AES encryption/decryption enabled

enumerator kIEE_AesBypass

AES encryption/decryption bypass

enum _iee_aes_mode

IEE AES mode.

Values:

enumerator kIEE_ModeNone

AES NONE mode

enumerator kIEE_ModeAesXTS

AES XTS mode

enumerator kIEE_ModeAesCTRWAddress

AES CTR w address binding mode

enumerator kIEE_ModeAesCTRWOAddress

AES CTR w/o address binding mode

enumerator kIEE_ModeAesCTRkeystream

AES CTR keystream only

enum _iee_aes_key_size

IEE AES key size.

Values:

enumerator kIEE_AesCTR128XTS256

AES 128 bits (CTR), 256 bits (XTS)

enumerator kIEE_AesCTR256XTS512

AES 256 bits (CTR), 512 bits (XTS)

enum _iee_aes_key_num

IEE AES key number.

Values:

enumerator kIEE_AesKey1

AES Key 1

enumerator kIEE_AesKey2

AES Key 2

typedef enum _iee_region iee_region_t

IEE region.

typedef enum _iee_aes_bypass iee_aes_bypass_t

IEE AES enablement/bypass.

typedef enum _iee_aes_mode iee_aes_mode_t

IEE AES mode.

typedef enum _iee_aes_key_size iee_aes_key_size_t

IEE AES key size.

typedef enum _iee_aes_key_num iee_aes_key_num_t

IEE AES key number.

typedef struct _iee_config iee_config_t

IEE configuration structure.

void IEE_Init(IEE_Type *base)

Resets IEE module to factory default values.

This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared.

Parameters:

• base – IEER peripheral address.

void IEE_GetDefaultConfig(iee_config_t *config)

Loads default values to the IEE configuration structure.

Loads default values to the IEE region configuration structure. The default values are as follows.

config->bypass = kIEE_AesUseMdField;
config->mode = kIEE_ModeNone;
config->keySize = kIEE_AesCTR128XTS256;
config->pageOffset = 0U;

Parameters:

• config – Configuration for the selected IEE region.

void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config)

Sets the IEE module according to the configuration structure.

This function configures IEE region according to configuration structure.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be configured.

• config – Configuration for the selected IEE region.

status_t IEE_SetRegionKey(IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize)

Sets the IEE module key.

This function sets specified AES key for the given region.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be configured.

• keyNum – Selection of AES KEY1 or KEY2.

• key – AES key.

• keySize – Size of AES key.

static inline uint32_t IEE_GetOffset(uint32_t addressIee, uint32_t addressMemory)

Computes IEE offset to be set for specifed memory location.

This function calculates offset that must be set for IEE region to access physical memory location.

Parameters:

• addressIee – Address of IEE peripheral.

• addressMemory – Address of physical memory location.

void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region)

Lock the IEE region configuration.

This function locks IEE region registers for Key, Offset and Attribute. Only system reset can clear the Lock bit.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be locked.

struct _iee_config

#include <fsl_iee.h>

IEE configuration structure.

Public Members

iee_aes_bypass_t bypass

AES encryption/decryption bypass

iee_aes_mode_t mode

AES mode

iee_aes_key_size_t keySize

size of AES key

uint32_t pageOffset

Offset to physical memory location from IEE start address

Ieer

FSL_IEE_APC_DRIVER_VERSION

IEE_APC driver version. Version 2.0.2.

Current version: 2.0.2

Change log:

• Version 2.0.0

  • Initial version

• Version 2.0.1

  • Fixed MISRA issues.

• Version 2.0.2

  • Update to newer version of implementation in HW.

enum _iee_apc_region

APC IEE regions.

Values:

enumerator kIEE_APC_Region0

APC IEE region 0

enumerator kIEE_APC_Region1

APC IEE region 1

enumerator kIEE_APC_Region2

APC IEE region 2

enumerator kIEE_APC_Region3

APC IEE region 3

enumerator kIEE_APC_Region4

APC IEE region 4

enumerator kIEE_APC_Region5

APC IEE region 5

enumerator kIEE_APC_Region6

APC IEE region 6

enumerator kIEE_APC_Region7

APC IEE region 7

enum _apc_iee_domain

APC IEE domains.

Values:

enumerator kIEE_APC_Domain0

APC IEE region 0

enumerator kIEE_APC_Domain1

APC IEE region 1

typedef enum _iee_apc_region iee_apc_region_t

APC IEE regions.

typedef enum _apc_iee_domain iee_apc_domain_t

APC IEE domains.

void IEE_APC_GlobalEnable(IEE_APC_Type *base)

Enable the APC IEE Region setting.

This function enables IOMUXC LPSR GPR and APC IEE for setting the region.

Parameters:

• base – APC IEE peripheral address.

void IEE_APC_GlobalDisable(IEE_APC_Type *base)

Disables the APC IEE Region setting.

This function disables IOMUXC LPSR GPR and APC IEE for setting the region.

Parameters:

• base – APC IEE peripheral address.

status_t IEE_APC_SetRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, uint32_t startAddr, uint32_t endAddr)

Sets the APC IEE Memory Region Descriptors.

This function configures APC IEE Memory Region Descriptor according to region configuration structure.

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be configured.

• startAddr – Start encryption adress for the selected APC IEE region.

• endAddr – End encryption adress for the selected APC IEE region.

status_t IEE_APC_LockRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, iee_apc_domain_t domain)

Lock the LPSR GPR and APC IEE configuration.

This function locks writting to IOMUXC LPSR GPR and APC IEE encryption region setting registers. Only system reset can clear the LPSR GPR and APC IEE-RDC_D0/1 Lock bit

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be locked.

• domain – Core domain ID

void IEE_APC_RegionEnable(IEE_APC_Type *base, iee_apc_region_t region)

Enable the IEE encryption/decryption and can lock this setting.

This function enables encryption/decryption by writting to IOMUXC LPSR GPR.

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be enabled.

IOMUXC: IOMUX Controller

enum _iomuxc_gpr_saimclk

Values:

enumerator kIOMUXC_GPR_SAI1MClk1Sel

enumerator kIOMUXC_GPR_SAI1MClk2Sel

enumerator kIOMUXC_GPR_SAI1MClk3Sel

enumerator kIOMUXC_GPR_SAI2MClk3Sel

enumerator kIOMUXC_GPR_SAI3MClk3Sel

enum _iomuxc_mqs_pwm_oversample_rate

Values:

enumerator kIOMUXC_MqsPwmOverSampleRate32

enumerator kIOMUXC_MqsPwmOverSampleRate64

typedef enum _iomuxc_gpr_saimclk iomuxc_gpr_saimclk_t

typedef enum _iomuxc_mqs_pwm_oversample_rate iomuxc_mqs_pwm_oversample_rate_t

IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX

IOMUXC_GPIO_LPSR_00_MIC_CLK

IOMUXC_GPIO_LPSR_00_MQS_RIGHT

IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO

IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00

IOMUXC_GPIO_LPSR_00_LPUART12_TXD

IOMUXC_GPIO_LPSR_00_SAI4_MCLK

IOMUXC_GPIO_LPSR_00_GPIO12_IO00

IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX

IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0

IOMUXC_GPIO_LPSR_01_MQS_LEFT

IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI

IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01

IOMUXC_GPIO_LPSR_01_LPUART12_RXD

IOMUXC_GPIO_LPSR_01_GPIO12_IO01

IOMUXC_GPIO_LPSR_02_GPIO12_IO02

IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00

IOMUXC_GPIO_LPSR_02_LPSPI5_SCK

IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA

IOMUXC_GPIO_LPSR_02_MQS_RIGHT

IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02

IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01

IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0

IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC

IOMUXC_GPIO_LPSR_03_MQS_LEFT

IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03

IOMUXC_GPIO_LPSR_03_GPIO12_IO03

IOMUXC_GPIO_LPSR_04_LPI2C5_SDA

IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT

IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK

IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B

IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04

IOMUXC_GPIO_LPSR_04_LPUART11_TXD

IOMUXC_GPIO_LPSR_04_GPIO12_IO04

IOMUXC_GPIO_LPSR_05_GPIO12_IO05

IOMUXC_GPIO_LPSR_05_LPI2C5_SCL

IOMUXC_GPIO_LPSR_05_LPSPI5_SIN

IOMUXC_GPIO_LPSR_05_SAI4_MCLK

IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B

IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05

IOMUXC_GPIO_LPSR_05_LPUART11_RXD

IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI

IOMUXC_GPIO_LPSR_06_LPI2C6_SDA

IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA

IOMUXC_GPIO_LPSR_06_LPUART12_TXD

IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3

IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06

IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX

IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3

IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1

IOMUXC_GPIO_LPSR_06_GPIO12_IO06

IOMUXC_GPIO_LPSR_07_LPI2C6_SCL

IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK

IOMUXC_GPIO_LPSR_07_LPUART12_RXD

IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2

IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07

IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX

IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2

IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2

IOMUXC_GPIO_LPSR_07_GPIO12_IO07

IOMUXC_GPIO_LPSR_08_GPIO12_IO08

IOMUXC_GPIO_LPSR_08_LPUART11_TXD

IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX

IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC

IOMUXC_GPIO_LPSR_08_MIC_CLK

IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1

IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08

IOMUXC_GPIO_LPSR_08_LPI2C5_SDA

IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1

IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3

IOMUXC_GPIO_LPSR_09_GPIO12_IO09

IOMUXC_GPIO_LPSR_09_LPUART11_RXD

IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX

IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0

IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0

IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0

IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09

IOMUXC_GPIO_LPSR_09_LPI2C5_SCL

IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA

IOMUXC_GPIO_LPSR_10_GPIO12_IO10

IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB

IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B

IOMUXC_GPIO_LPSR_10_LPI2C6_SDA

IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1

IOMUXC_GPIO_LPSR_10_LPSPI6_SCK

IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10

IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS

IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC

IOMUXC_GPIO_LPSR_10_LPUART12_TXD

IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO

IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B

IOMUXC_GPIO_LPSR_11_LPI2C6_SCL

IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2

IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT

IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11

IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS

IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO

IOMUXC_GPIO_LPSR_11_LPUART12_RXD

IOMUXC_GPIO_LPSR_11_GPIO12_IO11

IOMUXC_GPIO_LPSR_12_GPIO12_IO12

IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI

IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0

IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3

IOMUXC_GPIO_LPSR_12_LPSPI6_SIN

IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12

IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ

IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK

IOMUXC_GPIO_LPSR_12_LPSPI5_SCK

IOMUXC_GPIO_LPSR_13_GPIO12_IO13

IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD

IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1

IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1

IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13

IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA

IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0

IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK

IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2

IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2

IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14

IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK

IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT

IOMUXC_GPIO_LPSR_14_GPIO12_IO14

IOMUXC_GPIO_LPSR_15_GPIO12_IO15

IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS

IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3

IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3

IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15

IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC

IOMUXC_GPIO_LPSR_15_LPSPI5_SIN

IOMUXC_WAKEUP_DIG_GPIO13_IO00

IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI

IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ

IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01

IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ

IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02

IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0

IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03

IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1

IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04

IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2

IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05

IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3

IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06

IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4

IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07

IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5

IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08

IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6

IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09

IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7

IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10

IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8

IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11

IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9

IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12

IOMUXC_TEST_MODE_DIG

IOMUXC_POR_B_DIG

IOMUXC_ONOFF_DIG

IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00

IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A

IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00

IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00

IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00

IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01

IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01

IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B

IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01

IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01

IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02

IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A

IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02

IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02

IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02

IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03

IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B

IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03

IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03

IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03

IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04

IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04

IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A

IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04

IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04

IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05

IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B

IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05

IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05

IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05

IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06

IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A

IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06

IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06

IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06

IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07

IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07

IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B

IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07

IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07

IOMUXC_GPIO_EMC_B1_08_SEMC_DM00

IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A

IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08

IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08

IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08

IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00

IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B

IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1

IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09

IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09

IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09

IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01

IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A

IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2

IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10

IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10

IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10

IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11

IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02

IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B

IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1

IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11

IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11

IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03

IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04

IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2

IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12

IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12

IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12

IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04

IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05

IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3

IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13

IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13

IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13

IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14

IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05

IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06

IOMUXC_GPIO_EMC_B1_14_GPT5_CLK

IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14

IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14

IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06

IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07

IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15

IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15

IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15

IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07

IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08

IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16

IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16

IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16

IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17

IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08

IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A

IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0

IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17

IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17

IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09

IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B

IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0

IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18

IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18

IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18

IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11

IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A

IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0

IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19

IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19

IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19

IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12

IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B

IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0

IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20

IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20

IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20

IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21

IOMUXC_GPIO_EMC_B1_21_SEMC_BA0

IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A

IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21

IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21

IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22

IOMUXC_GPIO_EMC_B1_22_SEMC_BA1

IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B

IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22

IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22

IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10

IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A

IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23

IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23

IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23

IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24

IOMUXC_GPIO_EMC_B1_24_SEMC_CAS

IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B

IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24

IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24

IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25

IOMUXC_GPIO_EMC_B1_25_SEMC_RAS

IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A

IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25

IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25

IOMUXC_GPIO_EMC_B1_26_SEMC_CLK

IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B

IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26

IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26

IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26

IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27

IOMUXC_GPIO_EMC_B1_27_SEMC_CKE

IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A

IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27

IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27

IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28

IOMUXC_GPIO_EMC_B1_28_SEMC_WE

IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B

IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28

IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28

IOMUXC_GPIO_EMC_B1_29_SEMC_CS0

IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A

IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29

IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29

IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29

IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08

IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B

IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30

IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30

IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30

IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31

IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09

IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A

IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31

IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31

IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00

IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10

IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B

IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00

IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11

IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A

IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01

IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01

IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02

IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12

IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B

IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02

IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03

IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13

IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09

IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03

IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14

IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10

IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04

IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04

IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05

IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15

IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11

IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05

IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06

IOMUXC_GPIO_EMC_B1_38_SEMC_DM01

IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A

IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1

IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06

IOMUXC_GPIO_EMC_B1_39_SEMC_DQS

IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B

IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1

IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07

IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07

IOMUXC_GPIO_EMC_B1_40_SEMC_RDY

IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12

IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT

IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD

IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08

IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC

IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1

IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08

IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09

IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00

IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13

IOMUXC_GPIO_EMC_B1_41_MQS_LEFT

IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD

IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07

IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09

IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO

IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2

IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16

IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1

IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B

IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06

IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10

IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20

IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT

IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK

IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL

IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10

IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A

IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17

IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B

IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1

IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B

IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05

IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11

IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21

IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN

IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0

IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA

IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11

IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B

IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18

IOMUXC_GPIO_EMC_B2_02_USDHC2_WP

IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23

IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04

IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12

IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22

IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN

IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT

IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12

IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A

IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19

IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT

IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22

IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03

IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13

IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23

IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03

IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN

IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13

IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B

IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20

IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B

IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK

IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21

IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02

IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14

IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24

IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02

IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK

IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14

IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A

IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21

IOMUXC_GPIO_EMC_B2_05_GPT3_CLK

IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC

IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20

IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01

IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15

IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25

IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK

IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0

IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0

IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15

IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B

IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22

IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1

IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16

IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK

IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A

IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19

IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00

IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16

IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26

IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER

IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT

IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1

IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23

IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2

IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA

IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18

IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS

IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17

IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27

IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03

IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN

IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2

IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17

IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B

IOMUXC_GPIO_EMC_B2_08_SEMC_DM02

IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1

IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA

IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17

IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B

IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18

IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28

IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02

IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1

IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3

IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18

IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19

IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24

IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2

IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK

IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16

IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK

IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19

IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29

IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS

IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2

IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0

IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20

IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25

IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3

IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC

IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD

IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK

IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20

IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30

IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL

IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3

IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1

IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26

IOMUXC_GPIO_EMC_B2_11_SPDIF_IN

IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00

IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC

IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B

IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21

IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31

IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO

IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2

IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21

IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27

IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT

IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01

IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK

IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS

IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22

IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32

IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK

IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3

IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22

IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23

IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28

IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN

IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA

IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00

IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23

IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33

IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST

IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0

IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29

IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO

IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA

IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01

IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24

IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34

IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test

IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN

IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1

IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24

IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30

IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00

IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK

IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02

IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25

IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35

IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD

IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2

IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25

IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26

IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31

IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14

IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01

IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC

IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03

IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26

IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL

IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3

IOMUXC_GPIO_EMC_B2_17_SEMC_DM03

IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15

IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN

IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK

IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04

IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27

IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY

IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0

IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27

IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4

IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16

IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER

IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B

IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05

IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28

IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS

IOMUXC_GPIO_EMC_B2_18_WDOG1_B

IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1

IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28

IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29

IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00

IOMUXC_GPIO_EMC_B2_19_ENET_MDC

IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC

IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK

IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06

IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29

IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC

IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2

IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30

IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01

IOMUXC_GPIO_EMC_B2_20_ENET_MDIO

IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO

IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK

IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07

IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30

IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO

IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3

IOMUXC_GPIO_AD_00_GPIO8_IO31

IOMUXC_GPIO_AD_00_EMVSIM1_IO

IOMUXC_GPIO_AD_00_FLEXCAN2_TX

IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN

IOMUXC_GPIO_AD_00_GPT2_CAPTURE1

IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A

IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31

IOMUXC_GPIO_AD_00_LPUART7_TXD

IOMUXC_GPIO_AD_00_FLEXIO2_D00

IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B

IOMUXC_GPIO_AD_01_GPIO9_IO00

IOMUXC_GPIO_AD_01_EMVSIM1_CLK

IOMUXC_GPIO_AD_01_FLEXCAN2_RX

IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT

IOMUXC_GPIO_AD_01_GPT2_CAPTURE2

IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B

IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00

IOMUXC_GPIO_AD_01_LPUART7_RXD

IOMUXC_GPIO_AD_01_FLEXIO2_D01

IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B

IOMUXC_GPIO_AD_02_GPIO9_IO01

IOMUXC_GPIO_AD_02_EMVSIM1_RST

IOMUXC_GPIO_AD_02_LPUART7_CTS_B

IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN

IOMUXC_GPIO_AD_02_GPT2_COMPARE1

IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A

IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01

IOMUXC_GPIO_AD_02_LPUART8_TXD

IOMUXC_GPIO_AD_02_FLEXIO2_D02

IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1

IOMUXC_GPIO_AD_03_GPIO9_IO02

IOMUXC_GPIO_AD_03_EMVSIM1_SVEN

IOMUXC_GPIO_AD_03_LPUART7_RTS_B

IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT

IOMUXC_GPIO_AD_03_GPT2_COMPARE2

IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B

IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02

IOMUXC_GPIO_AD_03_LPUART8_RXD

IOMUXC_GPIO_AD_03_FLEXIO2_D03

IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2

IOMUXC_GPIO_AD_04_EMVSIM1_PD

IOMUXC_GPIO_AD_04_LPUART8_CTS_B

IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN

IOMUXC_GPIO_AD_04_GPT2_COMPARE3

IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A

IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03

IOMUXC_GPIO_AD_04_WDOG1_B

IOMUXC_GPIO_AD_04_FLEXIO2_D04

IOMUXC_GPIO_AD_04_TMR4_TIMER0

IOMUXC_GPIO_AD_04_GPIO9_IO03

IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL

IOMUXC_GPIO_AD_05_LPUART8_RTS_B

IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT

IOMUXC_GPIO_AD_05_GPT2_CLK

IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B

IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04

IOMUXC_GPIO_AD_05_WDOG2_B

IOMUXC_GPIO_AD_05_FLEXIO2_D05

IOMUXC_GPIO_AD_05_TMR4_TIMER1

IOMUXC_GPIO_AD_05_GPIO9_IO04

IOMUXC_GPIO_AD_06_USB_OTG2_OC

IOMUXC_GPIO_AD_06_FLEXCAN1_TX

IOMUXC_GPIO_AD_06_EMVSIM2_IO

IOMUXC_GPIO_AD_06_GPT3_CAPTURE1

IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15

IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05

IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN

IOMUXC_GPIO_AD_06_FLEXIO2_D06

IOMUXC_GPIO_AD_06_TMR4_TIMER2

IOMUXC_GPIO_AD_06_GPIO9_IO05

IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X

IOMUXC_GPIO_AD_07_USB_OTG2_PWR

IOMUXC_GPIO_AD_07_FLEXCAN1_RX

IOMUXC_GPIO_AD_07_EMVSIM2_CLK

IOMUXC_GPIO_AD_07_GPT3_CAPTURE2

IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14

IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06

IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT

IOMUXC_GPIO_AD_07_FLEXIO2_D07

IOMUXC_GPIO_AD_07_TMR4_TIMER3

IOMUXC_GPIO_AD_07_GPIO9_IO06

IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X

IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID

IOMUXC_GPIO_AD_08_LPI2C1_SCL

IOMUXC_GPIO_AD_08_EMVSIM2_RST

IOMUXC_GPIO_AD_08_GPT3_COMPARE1

IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13

IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07

IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN

IOMUXC_GPIO_AD_08_FLEXIO2_D08

IOMUXC_GPIO_AD_08_GPIO9_IO07

IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X

IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID

IOMUXC_GPIO_AD_09_LPI2C1_SDA

IOMUXC_GPIO_AD_09_EMVSIM2_SVEN

IOMUXC_GPIO_AD_09_GPT3_COMPARE2

IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12

IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08

IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT

IOMUXC_GPIO_AD_09_FLEXIO2_D09

IOMUXC_GPIO_AD_09_GPIO9_IO08

IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X

IOMUXC_GPIO_AD_10_USB_OTG1_PWR

IOMUXC_GPIO_AD_10_LPI2C1_SCLS

IOMUXC_GPIO_AD_10_EMVSIM2_PD

IOMUXC_GPIO_AD_10_GPT3_COMPARE3

IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11

IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09

IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN

IOMUXC_GPIO_AD_10_FLEXIO2_D10

IOMUXC_GPIO_AD_10_GPIO9_IO09

IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X

IOMUXC_GPIO_AD_11_USB_OTG1_OC

IOMUXC_GPIO_AD_11_LPI2C1_SDAS

IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL

IOMUXC_GPIO_AD_11_GPT3_CLK

IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10

IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10

IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT

IOMUXC_GPIO_AD_11_FLEXIO2_D11

IOMUXC_GPIO_AD_11_GPIO9_IO10

IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X

IOMUXC_GPIO_AD_12_SPDIF_LOCK

IOMUXC_GPIO_AD_12_LPI2C1_HREQ

IOMUXC_GPIO_AD_12_GPT1_CAPTURE1

IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03

IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK

IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11

IOMUXC_GPIO_AD_12_ENET_TX_DATA03

IOMUXC_GPIO_AD_12_FLEXIO2_D12

IOMUXC_GPIO_AD_12_EWM_OUT_B

IOMUXC_GPIO_AD_12_GPIO9_IO11

IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X

IOMUXC_GPIO_AD_13_SPDIF_SR_CLK

IOMUXC_GPIO_AD_13_PIT1_TRIGGER0

IOMUXC_GPIO_AD_13_GPT1_CAPTURE2

IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02

IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK

IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12

IOMUXC_GPIO_AD_13_ENET_TX_DATA02

IOMUXC_GPIO_AD_13_FLEXIO2_D13

IOMUXC_GPIO_AD_13_REF_CLK_32K

IOMUXC_GPIO_AD_13_GPIO9_IO12

IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X

IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK

IOMUXC_GPIO_AD_14_REF_CLK_24M

IOMUXC_GPIO_AD_14_GPT1_COMPARE1

IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01

IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC

IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13

IOMUXC_GPIO_AD_14_ENET_RX_CLK

IOMUXC_GPIO_AD_14_FLEXIO2_D14

IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_AD_14_GPIO9_IO13

IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X

IOMUXC_GPIO_AD_15_GPIO9_IO14

IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X

IOMUXC_GPIO_AD_15_SPDIF_IN

IOMUXC_GPIO_AD_15_LPUART10_TXD

IOMUXC_GPIO_AD_15_GPT1_COMPARE2

IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00

IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC

IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14

IOMUXC_GPIO_AD_15_ENET_TX_ER

IOMUXC_GPIO_AD_15_FLEXIO2_D15

IOMUXC_GPIO_AD_16_SPDIF_OUT

IOMUXC_GPIO_AD_16_LPUART10_RXD

IOMUXC_GPIO_AD_16_GPT1_COMPARE3

IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK

IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09

IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15

IOMUXC_GPIO_AD_16_ENET_RX_DATA03

IOMUXC_GPIO_AD_16_FLEXIO2_D16

IOMUXC_GPIO_AD_16_ENET_1G_MDC

IOMUXC_GPIO_AD_16_GPIO9_IO15

IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X

IOMUXC_GPIO_AD_17_SAI1_MCLK

IOMUXC_GPIO_AD_17_ACMP1_OUT

IOMUXC_GPIO_AD_17_GPT1_CLK

IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS

IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08

IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16

IOMUXC_GPIO_AD_17_ENET_RX_DATA02

IOMUXC_GPIO_AD_17_FLEXIO2_D17

IOMUXC_GPIO_AD_17_ENET_1G_MDIO

IOMUXC_GPIO_AD_17_GPIO9_IO16

IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X

IOMUXC_GPIO_AD_18_GPIO9_IO17

IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X

IOMUXC_GPIO_AD_18_SAI1_RX_SYNC

IOMUXC_GPIO_AD_18_ACMP2_OUT

IOMUXC_GPIO_AD_18_LPSPI1_PCS1

IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B

IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07

IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17

IOMUXC_GPIO_AD_18_ENET_CRS

IOMUXC_GPIO_AD_18_FLEXIO2_D18

IOMUXC_GPIO_AD_18_LPI2C2_SCL

IOMUXC_GPIO_AD_19_SAI1_RX_BCLK

IOMUXC_GPIO_AD_19_ACMP3_OUT

IOMUXC_GPIO_AD_19_LPSPI1_PCS2

IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK

IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06

IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18

IOMUXC_GPIO_AD_19_ENET_COL

IOMUXC_GPIO_AD_19_FLEXIO2_D19

IOMUXC_GPIO_AD_19_LPI2C2_SDA

IOMUXC_GPIO_AD_19_GPIO9_IO18

IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X

IOMUXC_GPIO_AD_20_SAI1_RX_DATA00

IOMUXC_GPIO_AD_20_ACMP4_OUT

IOMUXC_GPIO_AD_20_LPSPI1_PCS3

IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00

IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05

IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19

IOMUXC_GPIO_AD_20_KPP_ROW07

IOMUXC_GPIO_AD_20_FLEXIO2_D20

IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT

IOMUXC_GPIO_AD_20_GPIO9_IO19

IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X

IOMUXC_GPIO_AD_21_SAI1_TX_DATA00

IOMUXC_GPIO_AD_21_LPSPI2_PCS1

IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01

IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04

IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20

IOMUXC_GPIO_AD_21_KPP_COL07

IOMUXC_GPIO_AD_21_FLEXIO2_D21

IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN

IOMUXC_GPIO_AD_21_GPIO9_IO20

IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X

IOMUXC_GPIO_AD_22_GPIO9_IO21

IOMUXC_GPIO_AD_22_SAI1_TX_BCLK

IOMUXC_GPIO_AD_22_LPSPI2_PCS2

IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02

IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03

IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21

IOMUXC_GPIO_AD_22_KPP_ROW06

IOMUXC_GPIO_AD_22_FLEXIO2_D22

IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT

IOMUXC_GPIO_AD_23_SAI1_TX_SYNC

IOMUXC_GPIO_AD_23_LPSPI2_PCS3

IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03

IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02

IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22

IOMUXC_GPIO_AD_23_KPP_COL06

IOMUXC_GPIO_AD_23_FLEXIO2_D23

IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN

IOMUXC_GPIO_AD_23_GPIO9_IO22

IOMUXC_GPIO_AD_24_LPUART1_TXD

IOMUXC_GPIO_AD_24_LPSPI2_SCK

IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00

IOMUXC_GPIO_AD_24_ENET_RX_EN

IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A

IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23

IOMUXC_GPIO_AD_24_KPP_ROW05

IOMUXC_GPIO_AD_24_FLEXIO2_D24

IOMUXC_GPIO_AD_24_LPI2C4_SCL

IOMUXC_GPIO_AD_24_GPIO9_IO23

IOMUXC_GPIO_AD_25_GPIO9_IO24

IOMUXC_GPIO_AD_25_LPUART1_RXD

IOMUXC_GPIO_AD_25_LPSPI2_PCS0

IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01

IOMUXC_GPIO_AD_25_ENET_RX_ER

IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B

IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24

IOMUXC_GPIO_AD_25_KPP_COL05

IOMUXC_GPIO_AD_25_FLEXIO2_D25

IOMUXC_GPIO_AD_25_LPI2C4_SDA

IOMUXC_GPIO_AD_26_LPUART1_CTS_B

IOMUXC_GPIO_AD_26_LPSPI2_SOUT

IOMUXC_GPIO_AD_26_SEMC_CSX01

IOMUXC_GPIO_AD_26_ENET_RX_DATA00

IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A

IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25

IOMUXC_GPIO_AD_26_KPP_ROW04

IOMUXC_GPIO_AD_26_FLEXIO2_D26

IOMUXC_GPIO_AD_26_ENET_QOS_MDC

IOMUXC_GPIO_AD_26_GPIO9_IO25

IOMUXC_GPIO_AD_26_USDHC2_CD_B

IOMUXC_GPIO_AD_27_LPUART1_RTS_B

IOMUXC_GPIO_AD_27_LPSPI2_SIN

IOMUXC_GPIO_AD_27_SEMC_CSX02

IOMUXC_GPIO_AD_27_ENET_RX_DATA01

IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B

IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26

IOMUXC_GPIO_AD_27_KPP_COL04

IOMUXC_GPIO_AD_27_FLEXIO2_D27

IOMUXC_GPIO_AD_27_ENET_QOS_MDIO

IOMUXC_GPIO_AD_27_GPIO9_IO26

IOMUXC_GPIO_AD_27_USDHC2_WP

IOMUXC_GPIO_AD_28_GPIO9_IO27

IOMUXC_GPIO_AD_28_USDHC2_VSELECT

IOMUXC_GPIO_AD_28_LPSPI1_SCK

IOMUXC_GPIO_AD_28_LPUART5_TXD

IOMUXC_GPIO_AD_28_SEMC_CSX03

IOMUXC_GPIO_AD_28_ENET_TX_EN

IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A

IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27

IOMUXC_GPIO_AD_28_KPP_ROW03

IOMUXC_GPIO_AD_28_FLEXIO2_D28

IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1

IOMUXC_GPIO_AD_29_LPSPI1_PCS0

IOMUXC_GPIO_AD_29_LPUART5_RXD

IOMUXC_GPIO_AD_29_ENET_REF_CLK

IOMUXC_GPIO_AD_29_ENET_TX_CLK

IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B

IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28

IOMUXC_GPIO_AD_29_KPP_COL03

IOMUXC_GPIO_AD_29_FLEXIO2_D29

IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2

IOMUXC_GPIO_AD_29_GPIO9_IO28

IOMUXC_GPIO_AD_29_USDHC2_RESET_B

IOMUXC_GPIO_AD_30_LPSPI1_SOUT

IOMUXC_GPIO_AD_30_USB_OTG2_OC

IOMUXC_GPIO_AD_30_FLEXCAN2_TX

IOMUXC_GPIO_AD_30_ENET_TX_DATA00

IOMUXC_GPIO_AD_30_LPUART3_TXD

IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29

IOMUXC_GPIO_AD_30_KPP_ROW02

IOMUXC_GPIO_AD_30_FLEXIO2_D30

IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB

IOMUXC_GPIO_AD_30_GPIO9_IO29

IOMUXC_GPIO_AD_31_LPSPI1_SIN

IOMUXC_GPIO_AD_31_USB_OTG2_PWR

IOMUXC_GPIO_AD_31_FLEXCAN2_RX

IOMUXC_GPIO_AD_31_ENET_TX_DATA01

IOMUXC_GPIO_AD_31_LPUART3_RXD

IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30

IOMUXC_GPIO_AD_31_KPP_COL02

IOMUXC_GPIO_AD_31_FLEXIO2_D31

IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB

IOMUXC_GPIO_AD_31_GPIO9_IO30

IOMUXC_GPIO_AD_32_GPIO9_IO31

IOMUXC_GPIO_AD_32_LPI2C1_SCL

IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID

IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY

IOMUXC_GPIO_AD_32_ENET_MDC

IOMUXC_GPIO_AD_32_USDHC1_CD_B

IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31

IOMUXC_GPIO_AD_32_KPP_ROW01

IOMUXC_GPIO_AD_32_LPUART10_TXD

IOMUXC_GPIO_AD_32_ENET_1G_MDC

IOMUXC_GPIO_AD_33_LPI2C1_SDA

IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID

IOMUXC_GPIO_AD_33_XBAR1_INOUT17

IOMUXC_GPIO_AD_33_ENET_MDIO

IOMUXC_GPIO_AD_33_USDHC1_WP

IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00

IOMUXC_GPIO_AD_33_KPP_COL01

IOMUXC_GPIO_AD_33_LPUART10_RXD

IOMUXC_GPIO_AD_33_ENET_1G_MDIO

IOMUXC_GPIO_AD_33_GPIO10_IO00

IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN

IOMUXC_GPIO_AD_34_USB_OTG1_PWR

IOMUXC_GPIO_AD_34_XBAR1_INOUT18

IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN

IOMUXC_GPIO_AD_34_USDHC1_VSELECT

IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01

IOMUXC_GPIO_AD_34_KPP_ROW00

IOMUXC_GPIO_AD_34_LPUART10_CTS_B

IOMUXC_GPIO_AD_34_WDOG1_ANY

IOMUXC_GPIO_AD_34_GPIO10_IO01

IOMUXC_GPIO_AD_35_GPIO10_IO02

IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT

IOMUXC_GPIO_AD_35_USB_OTG1_OC

IOMUXC_GPIO_AD_35_XBAR1_INOUT19

IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT

IOMUXC_GPIO_AD_35_USDHC1_RESET_B

IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02

IOMUXC_GPIO_AD_35_KPP_COL00

IOMUXC_GPIO_AD_35_LPUART10_RTS_B

IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B

IOMUXC_GPIO_SD_B1_00_USDHC1_CMD

IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20

IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1

IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03

IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B

IOMUXC_GPIO_SD_B1_00_KPP_ROW07

IOMUXC_GPIO_SD_B1_00_GPIO10_IO03

IOMUXC_GPIO_SD_B1_01_USDHC1_CLK

IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21

IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2

IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04

IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK

IOMUXC_GPIO_SD_B1_01_KPP_COL07

IOMUXC_GPIO_SD_B1_01_GPIO10_IO04

IOMUXC_GPIO_SD_B1_02_GPIO10_IO05

IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0

IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22

IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1

IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05

IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00

IOMUXC_GPIO_SD_B1_02_KPP_ROW06

IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B

IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1

IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23

IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2

IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06

IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01

IOMUXC_GPIO_SD_B1_03_KPP_COL06

IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B

IOMUXC_GPIO_SD_B1_03_GPIO10_IO06

IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2

IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24

IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3

IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07

IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02

IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B

IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN

IOMUXC_GPIO_SD_B1_04_GPIO10_IO07

IOMUXC_GPIO_SD_B1_05_GPIO10_IO08

IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3

IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25

IOMUXC_GPIO_SD_B1_05_GPT4_CLK

IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08

IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03

IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS

IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN

IOMUXC_GPIO_SD_B2_00_GPIO10_IO09

IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3

IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03

IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN

IOMUXC_GPIO_SD_B2_00_LPUART9_TXD

IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK

IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09

IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2

IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02

IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK

IOMUXC_GPIO_SD_B2_01_LPUART9_RXD

IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0

IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10

IOMUXC_GPIO_SD_B2_01_GPIO10_IO10

IOMUXC_GPIO_SD_B2_02_GPIO10_IO11

IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1

IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01

IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00

IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B

IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT

IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11

IOMUXC_GPIO_SD_B2_03_GPIO10_IO12

IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0

IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00

IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01

IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B

IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN

IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12

IOMUXC_GPIO_SD_B2_04_USDHC2_CLK

IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK

IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02

IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B

IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1

IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13

IOMUXC_GPIO_SD_B2_04_GPIO10_IO13

IOMUXC_GPIO_SD_B2_05_GPIO10_IO14

IOMUXC_GPIO_SD_B2_05_USDHC2_CMD

IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS

IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03

IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B

IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2

IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14

IOMUXC_GPIO_SD_B2_06_GPIO10_IO15

IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B

IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B

IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03

IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3

IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1

IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15

IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE

IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK

IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02

IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B

IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2

IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16

IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK

IOMUXC_GPIO_SD_B2_07_ENET_TX_ER

IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK

IOMUXC_GPIO_SD_B2_07_GPIO10_IO16

IOMUXC_GPIO_SD_B2_08_GPIO10_IO17

IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4

IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00

IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01

IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B

IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1

IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17

IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0

IOMUXC_GPIO_SD_B2_09_GPIO10_IO18

IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5

IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01

IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00

IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B

IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2

IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18

IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT

IOMUXC_GPIO_SD_B2_10_GPIO10_IO19

IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6

IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02

IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN

IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B

IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3

IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19

IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN

IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7

IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03

IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO

IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK

IOMUXC_GPIO_SD_B2_11_GPT6_CLK

IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20

IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1

IOMUXC_GPIO_SD_B2_11_GPIO10_IO20

IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK

IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN

IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0

IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26

IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21

IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN

IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21

IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE

IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK

IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER

IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1

IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27

IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22

IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK

IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER

IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22

IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23

IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC

IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00

IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL

IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2

IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28

IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23

IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00

IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD

IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC

IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01

IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA

IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0

IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29

IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24

IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01

IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD

IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24

IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00

IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02

IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD

IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1

IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30

IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25

IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02

IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK

IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25

IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26

IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01

IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03

IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B

IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2

IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31

IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26

IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03

IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN

IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02

IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03

IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD

IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0

IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32

IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27

IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00

IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03

IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT

IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27

IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03

IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02

IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B

IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1

IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33

IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28

IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01

IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02

IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0

IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28

IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29

IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04

IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01

IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B

IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2

IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34

IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29

IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02

IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01

IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1

IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05

IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00

IOMUXC_GPIO_DISP_B1_09_USDHC1_WP

IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0

IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35

IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30

IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03

IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00

IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2

IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30

IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06

IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN

IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B

IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1

IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36

IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31

IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04

IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN

IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3

IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31

IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07

IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO

IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK

IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2

IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37

IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00

IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05

IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK

IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK

IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00

IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01

IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08

IOMUXC_GPIO_DISP_B2_00_WDOG1_B

IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT

IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER

IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03

IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01

IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06

IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER

IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09

IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT

IOMUXC_GPIO_DISP_B2_01_MQS_LEFT

IOMUXC_GPIO_DISP_B2_01_WDOG2_B

IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02

IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02

IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07

IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B

IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02

IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03

IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10

IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00

IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3

IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00

IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01

IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03

IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08

IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00

IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04

IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11

IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01

IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2

IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01

IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK

IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04

IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09

IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01

IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12

IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN

IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1

IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02

IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC

IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05

IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10

IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN

IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05

IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06

IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13

IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK

IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK

IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03

IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK

IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06

IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11

IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK

IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07

IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14

IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00

IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD

IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK

IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00

IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07

IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00

IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15

IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01

IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD

IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO

IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00

IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08

IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01

IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08

IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09

IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16

IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN

IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD

IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO

IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK

IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09

IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN

IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD

IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10

IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17

IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER

IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD

IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI

IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC

IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10

IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER

IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD

IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11

IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18

IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO

IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD

IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB

IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38

IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11

IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL

IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER

IOMUXC_GPIO_DISP_B2_10_SPDIF_IN

IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19

IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK

IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD

IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB

IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39

IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12

IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA

IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS

IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT

IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12

IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13

IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20

IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST

IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX

IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B

IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40

IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13

IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL

IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL

IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK

IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14

IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21

IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN

IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX

IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B

IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK

IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14

IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA

IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT

IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN

IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15

IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX

IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN

IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT

IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15

IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22

IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD

IOMUXC_GPIO_DISP_B2_14_WDOG2_B

IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1

IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK

IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23

IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL

IOMUXC_GPIO_DISP_B2_15_WDOG1_B

IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2

IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0

IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16

IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX

IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN

IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0

IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16

IOMUXC_GPR_SAIMCLK_LOWBITMASK

IOMUXC_GPR_SAIMCLK_HIGHBITMASK

static inline void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)

Sets the IOMUXC pin mux mode.

This is an example to set the PTA6 as the lpuart0_tx:

IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);

This is an example to set the PTA0 as GPIOA0:

IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);

Note

The first five parameters can be filled with the pin function ID macros.

Parameters:

• muxRegister – The pin mux register.

• muxMode – The pin mux mode.

• inputRegister – The select input register.

• inputDaisy – The input daisy.

• configRegister – The config register.

• inputOnfield – Software input on field.

static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)

Sets the IOMUXC pin configuration.

This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:

IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))

Note

The previous five parameters can be filled with the pin function ID macros.

Parameters:

• muxRegister – The pin mux register.

• muxMode – The pin mux mode.

• inputRegister – The select input register.

• inputDaisy – The input daisy.

• configRegister – The config register.

• configValue – The pin config value.

static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)

Sets IOMUXC general configuration for SAI MCLK selection.

Parameters:

• base – The IOMUXC GPR base address.

• mclk – The SAI MCLK.

• clkSrc – The clock source. Take refer to register setting details for the clock source in RM.

static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)

Enters or exit MQS software reset.

Parameters:

• base – The IOMUXC GPR base address.

• enable – Enter or exit MQS software reset.

static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)

Enables or disables MQS.

Parameters:

• base – The IOMUXC GPR base address.

• enable – Enable or disable the MQS.

static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)

Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.

Parameters:

• base – The IOMUXC GPR base address.

• rate – The MQS PWM oversampling rate, refer to “iomuxc_mqs_pwm_oversample_rate_t”.

• divider – The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.

FSL_IOMUXC_DRIVER_VERSION

IOMUXC driver version 2.0.2.

FSL_COMPONENT_ID

Key_manager

FSL_KEYMGR_DRIVER_VERSION

Key Manager driver version. Version 2.0.2.

Current version: 2.0.2

Change log:

• Version 2.0.2

  • Fix MISRA-2012 issues

• Version 2.0.1

  • Fix MISRA-2012 issues

• Version 2.0.0

  • Initial version

enum _keymgr_lock

Values:

enumerator kKEYMGR_Unlock

enumerator kKEYMGR_Lock

enum _keymgr_allow

Values:

enumerator kKEYMGR_Disallow

enumerator kKEYMGR_Allow

enum _keymgr_slot

Values:

enumerator kKEYMGR_Slot0

enumerator kKEYMGR_Slot1

enumerator kKEYMGR_Slot2

enumerator kKEYMGR_Slot3

enumerator kKEYMGR_Slot4

typedef enum _keymgr_lock keymgr_lock_t

typedef enum _keymgr_allow keymgr_allow_t

typedef enum _keymgr_slot keymgr_slot_t

typedef struct _domain_slot_config domain_slot_config_t

Key Manager slot configuration structure.

status_t KEYMGR_MasterKeyControll(KEY_MANAGER_Type *base, uint8_t select, keymgr_lock_t lock)

Configures Master key settings.

This function configures Key Manager’s setting for Master key.

Parameters:

• base – Key Manager peripheral address.

• select – select source for Master key.

• lock – setting for lock Master key.

Returns:

status of Master key control operation

status_t KEYMGR_OTFAD1KeyControll(KEY_MANAGER_Type *base, uint8_t select, keymgr_lock_t lock)

Configures OTFAD1 key settings.

This function configures Key Manager’s setting for OTFAD1 key.

Parameters:

• base – Key Manager peripheral address.

• select – select source for OTFAD1 key.

• lock – setting for lock OTFAD1 key.

Returns:

status of OTFAD1 key control operation

status_t KEYMGR_OTFAD2KeyControll(KEY_MANAGER_Type *base, uint8_t select, keymgr_lock_t lock)

Configures OTFAD2 key settings.

This function configures Key Manager’s setting for OTFAD2 key.

Parameters:

• base – Key Manager peripheral address.

• select – select source for OTFAD2 key.

• lock – setting for lock OTFAD2 key.

Returns:

status of OTFAD2 key control operation

void KEYMGR_IEEKeyReload(KEY_MANAGER_Type *base)

Restart load key signal for IEE.

This function genrates Key Manager’s restart signal for IEE key.

Parameters:

• base – Key Manager peripheral address.

void KEYMGR_PUFKeyLock(KEY_MANAGER_Type *base, keymgr_lock_t lock)

Lock the key select from PUF.

This function locks selection of key for PUF.

Parameters:

• base – Key Manager peripheral address.

• lock – Setting for selection of key for PUF.

status_t KEYMGR_SlotControl(KEY_MANAGER_Type *base, domain_slot_config_t *config, keymgr_slot_t slot)

Configures Slot Domain control.

This function configures domain slot control which locks and allows writes.

Parameters:

• base – Key Manager peripheral address.

• config – Pointer to slot configuration structure.

• slot – Select slot to be configured.

Returns:

status of slot control operation

void KEYMGR_Init(KEY_MANAGER_Type *base)

Resets Key Manager module to factory default values.

This function performs hardware reset of Key Manager module.

Parameters:

• base – Key Manager peripheral address.

status_t KEYMGR_GetDefaultConfig(domain_slot_config_t *config)

Sets the default configuration of Key manager slot.

This function initialize Key Manager slot config structure to default values.

Parameters:

• config – Pointer to slot configuration structure.

KEYMGR_IEE_RELOAD

KEYMGR_SEL_OCOTP

KEYMGR_SEL_UDF

KEYMGR_SEL_PUF

keymgr_select_t

struct _domain_slot_config

#include <fsl_key_manager.h>

Key Manager slot configuration structure.

Public Members

keymgr_lock_t lockControl

Lock control register of slot.

keymgr_allow_t allowUser

Allow user write access to domain control register or domain register.

keymgr_allow_t allowNonSecure

Allow non-secure write access to domain control register or domain register.

keymgr_lock_t lockList

Lock whitelist. SLOTx_CTRL[WHITE_LIST] cannot be changed.

uint8_t whiteList

Domains that on the Whitelist can change given slot. Each field represents one domain. Bit0~Bit3 represent DOMAIN0~DOMAIN3 respectively.

KPP: KeyPad Port Driver

void KPP_Init(KPP_Type *base, kpp_config_t *configure)

KPP initialize. This function ungates the KPP clock and initializes KPP. This function must be called before calling any other KPP driver functions.

Parameters:

• base – KPP peripheral base address.

• configure – The KPP configuration structure pointer.

void KPP_Deinit(KPP_Type *base)

Deinitializes the KPP module and gates the clock. This function gates the KPP clock. As a result, the KPP module doesn’t work after calling this function.

Parameters:

• base – KPP peripheral base address.

static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask)

Enable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to enable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask)

Disable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to disable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline uint16_t KPP_GetStatusFlag(KPP_Type *base)

Gets the KPP interrupt event status.

Parameters:

• base – KPP peripheral base address.

Returns:

The status of the KPP. Application can use the enum type in the “kpp_interrupt_enable_t” to get the right status of the related event.

static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask)

Clears KPP status flag.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask)

Set KPP synchronization chain.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_sync_operation_t.

void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)

Keypad press scanning.

This function will scanning all columns and rows. so all scanning data will be stored in the data pointer.

Parameters:

• base – KPP peripheral base address.

• data – KPP key press scanning data. The data buffer should be prepared with length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. for example the data[2] = 4, that means in column 1 row 2 has a key press event.

• clockSrc_Hz – Source clock.

FSL_KPP_DRIVER_VERSION

KPP driver version.

enum _kpp_interrupt_enable

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

Values:

enumerator kKPP_keyDepressInterrupt

Keypad depress interrupt source

enumerator kKPP_keyReleaseInterrupt

Keypad release interrupt source

enum _kpp_sync_operation

Lists of KPP synchronize chain operation.

Values:

enumerator kKPP_ClearKeyDepressSyncChain

Keypad depress interrupt status.

enumerator kKPP_SetKeyReleasesSyncChain

Keypad release interrupt status.

typedef enum _kpp_interrupt_enable kpp_interrupt_enable_t

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

typedef enum _kpp_sync_operation kpp_sync_operation_t

Lists of KPP synchronize chain operation.

typedef struct _kpp_config kpp_config_t

Lists of KPP status.

KPP_KEYPAD_COLUMNNUM_MAX

KPP_KEYPAD_ROWNUM_MAX

struct _kpp_config

#include <fsl_kpp.h>

Lists of KPP status.

Public Members

uint8_t activeRow

The row number: bit 7 ~ 0 represents the row 7 ~ 0.

uint8_t activeColumn

The column number: bit 7 ~ 0 represents the column 7 ~ 0.

uint16_t interrupt

KPP interrupt source. A logical OR of “kpp_interrupt_enable_t”.

Common Driver

FSL_COMMON_DRIVER_VERSION

common driver version.

DEBUG_CONSOLE_DEVICE_TYPE_NONE

No debug console.

DEBUG_CONSOLE_DEVICE_TYPE_UART

Debug console based on UART.

DEBUG_CONSOLE_DEVICE_TYPE_LPUART

Debug console based on LPUART.

DEBUG_CONSOLE_DEVICE_TYPE_LPSCI

Debug console based on LPSCI.

DEBUG_CONSOLE_DEVICE_TYPE_USBCDC

Debug console based on USBCDC.

DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM

Debug console based on FLEXCOMM.

DEBUG_CONSOLE_DEVICE_TYPE_IUART

Debug console based on i.MX UART.

DEBUG_CONSOLE_DEVICE_TYPE_VUSART

Debug console based on LPC_VUSART.

DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART

Debug console based on LPC_USART.

DEBUG_CONSOLE_DEVICE_TYPE_SWO

Debug console based on SWO.

DEBUG_CONSOLE_DEVICE_TYPE_QSCI

Debug console based on QSCI.

MIN(a, b)

Computes the minimum of a and b.

MAX(a, b)

Computes the maximum of a and b.

UINT16_MAX

Max value of uint16_t type.

UINT32_MAX

Max value of uint32_t type.

SDK_ATOMIC_LOCAL_ADD(addr, val)

Add value val from the variable at address address.

SDK_ATOMIC_LOCAL_SUB(addr, val)

Subtract value val to the variable at address address.

SDK_ATOMIC_LOCAL_SET(addr, bits)

Set the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR(addr, bits)

Clear the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)

Toggle the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)

For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.

SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)

For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .

SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)

For the variable at address address, set as newValue value and return old value.

USEC_TO_COUNT(us, clockFreqInHz)

Macro to convert a microsecond period to raw count value

COUNT_TO_USEC(count, clockFreqInHz)

Macro to convert a raw count value to microsecond

MSEC_TO_COUNT(ms, clockFreqInHz)

Macro to convert a millisecond period to raw count value

COUNT_TO_MSEC(count, clockFreqInHz)

Macro to convert a raw count value to millisecond

SDK_ISR_EXIT_BARRIER

SDK_L1DCACHE_ALIGN(var)

Macro to define a variable with L1 d-cache line size alignment

SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L2 cache line size alignment

Macro to change a value to a given size aligned value

CACHE_LINE_DATA

enum _status_groups

Status group numbers.

Values:

enumerator kStatusGroup_Generic

Group number for generic status codes.

enumerator kStatusGroup_FLASH

Group number for FLASH status codes.

enumerator kStatusGroup_LPSPI

Group number for LPSPI status codes.

enumerator kStatusGroup_FLEXIO_SPI

Group number for FLEXIO SPI status codes.

enumerator kStatusGroup_DSPI

Group number for DSPI status codes.

enumerator kStatusGroup_FLEXIO_UART

Group number for FLEXIO UART status codes.

enumerator kStatusGroup_FLEXIO_I2C

Group number for FLEXIO I2C status codes.

enumerator kStatusGroup_LPI2C

Group number for LPI2C status codes.

enumerator kStatusGroup_UART

Group number for UART status codes.

enumerator kStatusGroup_I2C

Group number for UART status codes.

enumerator kStatusGroup_LPSCI

Group number for LPSCI status codes.

enumerator kStatusGroup_LPUART

Group number for LPUART status codes.

enumerator kStatusGroup_SPI

Group number for SPI status code.

enumerator kStatusGroup_XRDC

Group number for XRDC status code.

enumerator kStatusGroup_SEMA42

Group number for SEMA42 status code.

enumerator kStatusGroup_SDHC

Group number for SDHC status code

enumerator kStatusGroup_SDMMC

Group number for SDMMC status code

enumerator kStatusGroup_SAI

Group number for SAI status code

enumerator kStatusGroup_MCG

Group number for MCG status codes.

enumerator kStatusGroup_SCG

Group number for SCG status codes.

enumerator kStatusGroup_SDSPI

Group number for SDSPI status codes.

enumerator kStatusGroup_FLEXIO_I2S

Group number for FLEXIO I2S status codes

enumerator kStatusGroup_FLEXIO_MCULCD

Group number for FLEXIO LCD status codes

enumerator kStatusGroup_FLASHIAP

Group number for FLASHIAP status codes

enumerator kStatusGroup_FLEXCOMM_I2C

Group number for FLEXCOMM I2C status codes

enumerator kStatusGroup_I2S

Group number for I2S status codes

enumerator kStatusGroup_IUART

Group number for IUART status codes

enumerator kStatusGroup_CSI

Group number for CSI status codes

enumerator kStatusGroup_MIPI_DSI

Group number for MIPI DSI status codes

enumerator kStatusGroup_SDRAMC

Group number for SDRAMC status codes.

enumerator kStatusGroup_POWER

Group number for POWER status codes.

enumerator kStatusGroup_ENET

Group number for ENET status codes.

enumerator kStatusGroup_PHY

Group number for PHY status codes.

enumerator kStatusGroup_TRGMUX

Group number for TRGMUX status codes.

enumerator kStatusGroup_SMARTCARD

Group number for SMARTCARD status codes.

enumerator kStatusGroup_LMEM

Group number for LMEM status codes.

enumerator kStatusGroup_QSPI

Group number for QSPI status codes.

enumerator kStatusGroup_DMA

Group number for DMA status codes.

enumerator kStatusGroup_EDMA

Group number for EDMA status codes.

enumerator kStatusGroup_DMAMGR

Group number for DMAMGR status codes.

enumerator kStatusGroup_FLEXCAN

Group number for FlexCAN status codes.

enumerator kStatusGroup_LTC

Group number for LTC status codes.

enumerator kStatusGroup_FLEXIO_CAMERA

Group number for FLEXIO CAMERA status codes.

enumerator kStatusGroup_LPC_SPI

Group number for LPC_SPI status codes.

enumerator kStatusGroup_LPC_USART

Group number for LPC_USART status codes.

enumerator kStatusGroup_DMIC

Group number for DMIC status codes.

enumerator kStatusGroup_SDIF

Group number for SDIF status codes.

enumerator kStatusGroup_SPIFI

Group number for SPIFI status codes.

enumerator kStatusGroup_OTP

Group number for OTP status codes.

enumerator kStatusGroup_MCAN

Group number for MCAN status codes.

enumerator kStatusGroup_CAAM

Group number for CAAM status codes.

enumerator kStatusGroup_ECSPI

Group number for ECSPI status codes.

enumerator kStatusGroup_USDHC

Group number for USDHC status codes.

enumerator kStatusGroup_LPC_I2C

Group number for LPC_I2C status codes.

enumerator kStatusGroup_DCP

Group number for DCP status codes.

enumerator kStatusGroup_MSCAN

Group number for MSCAN status codes.

enumerator kStatusGroup_ESAI

Group number for ESAI status codes.

enumerator kStatusGroup_FLEXSPI

Group number for FLEXSPI status codes.

enumerator kStatusGroup_MMDC

Group number for MMDC status codes.

enumerator kStatusGroup_PDM

Group number for MIC status codes.

enumerator kStatusGroup_SDMA

Group number for SDMA status codes.

enumerator kStatusGroup_ICS

Group number for ICS status codes.

enumerator kStatusGroup_SPDIF

Group number for SPDIF status codes.

enumerator kStatusGroup_LPC_MINISPI

Group number for LPC_MINISPI status codes.

enumerator kStatusGroup_HASHCRYPT

Group number for Hashcrypt status codes

enumerator kStatusGroup_LPC_SPI_SSP

Group number for LPC_SPI_SSP status codes.

enumerator kStatusGroup_I3C

Group number for I3C status codes

enumerator kStatusGroup_LPC_I2C_1

Group number for LPC_I2C_1 status codes.

enumerator kStatusGroup_NOTIFIER

Group number for NOTIFIER status codes.

enumerator kStatusGroup_DebugConsole

Group number for debug console status codes.

enumerator kStatusGroup_SEMC

Group number for SEMC status codes.

enumerator kStatusGroup_ApplicationRangeStart

Starting number for application groups.

enumerator kStatusGroup_IAP

Group number for IAP status codes

enumerator kStatusGroup_SFA

Group number for SFA status codes

enumerator kStatusGroup_SPC

Group number for SPC status codes.

enumerator kStatusGroup_PUF

Group number for PUF status codes.

enumerator kStatusGroup_TOUCH_PANEL

Group number for touch panel status codes

enumerator kStatusGroup_VBAT

Group number for VBAT status codes

enumerator kStatusGroup_XSPI

Group number for XSPI status codes

enumerator kStatusGroup_PNGDEC

Group number for PNGDEC status codes

enumerator kStatusGroup_JPEGDEC

Group number for JPEGDEC status codes

enumerator kStatusGroup_HAL_GPIO

Group number for HAL GPIO status codes.

enumerator kStatusGroup_HAL_UART

Group number for HAL UART status codes.

enumerator kStatusGroup_HAL_TIMER

Group number for HAL TIMER status codes.

enumerator kStatusGroup_HAL_SPI

Group number for HAL SPI status codes.

enumerator kStatusGroup_HAL_I2C

Group number for HAL I2C status codes.

enumerator kStatusGroup_HAL_FLASH

Group number for HAL FLASH status codes.

enumerator kStatusGroup_HAL_PWM

Group number for HAL PWM status codes.

enumerator kStatusGroup_HAL_RNG

Group number for HAL RNG status codes.

enumerator kStatusGroup_HAL_I2S

Group number for HAL I2S status codes.

enumerator kStatusGroup_HAL_ADC_SENSOR

Group number for HAL ADC SENSOR status codes.

enumerator kStatusGroup_TIMERMANAGER

Group number for TiMER MANAGER status codes.

enumerator kStatusGroup_SERIALMANAGER

Group number for SERIAL MANAGER status codes.

enumerator kStatusGroup_LED

Group number for LED status codes.

enumerator kStatusGroup_BUTTON

Group number for BUTTON status codes.

enumerator kStatusGroup_EXTERN_EEPROM

Group number for EXTERN EEPROM status codes.

enumerator kStatusGroup_SHELL

Group number for SHELL status codes.

enumerator kStatusGroup_MEM_MANAGER

Group number for MEM MANAGER status codes.

enumerator kStatusGroup_LIST

Group number for List status codes.

enumerator kStatusGroup_OSA

Group number for OSA status codes.

enumerator kStatusGroup_COMMON_TASK

Group number for Common task status codes.

enumerator kStatusGroup_MSG

Group number for messaging status codes.

enumerator kStatusGroup_SDK_OCOTP

Group number for OCOTP status codes.

enumerator kStatusGroup_SDK_FLEXSPINOR

Group number for FLEXSPINOR status codes.

enumerator kStatusGroup_CODEC

Group number for codec status codes.

enumerator kStatusGroup_ASRC

Group number for codec status ASRC.

enumerator kStatusGroup_OTFAD

Group number for codec status codes.

enumerator kStatusGroup_SDIOSLV

Group number for SDIOSLV status codes.

enumerator kStatusGroup_MECC

Group number for MECC status codes.

enumerator kStatusGroup_ENET_QOS

Group number for ENET_QOS status codes.

enumerator kStatusGroup_LOG

Group number for LOG status codes.

enumerator kStatusGroup_I3CBUS

Group number for I3CBUS status codes.

enumerator kStatusGroup_QSCI

Group number for QSCI status codes.

enumerator kStatusGroup_ELEMU

Group number for ELEMU status codes.

enumerator kStatusGroup_QUEUEDSPI

Group number for QSPI status codes.

enumerator kStatusGroup_POWER_MANAGER

Group number for POWER_MANAGER status codes.

enumerator kStatusGroup_IPED

Group number for IPED status codes.

enumerator kStatusGroup_ELS_PKC

Group number for ELS PKC status codes.

enumerator kStatusGroup_CSS_PKC

Group number for CSS PKC status codes.

enumerator kStatusGroup_HOSTIF

Group number for HOSTIF status codes.

enumerator kStatusGroup_CLIF

Group number for CLIF status codes.

enumerator kStatusGroup_BMA

Group number for BMA status codes.

enumerator kStatusGroup_NETC

Group number for NETC status codes.

enumerator kStatusGroup_ELE

Group number for ELE status codes.

enumerator kStatusGroup_GLIKEY

Group number for GLIKEY status codes.

enumerator kStatusGroup_AON_POWER

Group number for AON_POWER status codes.

enumerator kStatusGroup_AON_COMMON

Group number for AON_COMMON status codes.

enumerator kStatusGroup_ENDAT3

Group number for ENDAT3 status codes.

enumerator kStatusGroup_HIPERFACE

Group number for HIPERFACE status codes.

Generic status return codes.

Values:

enumerator kStatus_Success

Generic status for Success.

enumerator kStatus_Fail

Generic status for Fail.

enumerator kStatus_ReadOnly

Generic status for read only failure.

enumerator kStatus_OutOfRange

Generic status for out of range access.

enumerator kStatus_InvalidArgument

Generic status for invalid argument check.

enumerator kStatus_Timeout

Generic status for timeout.

enumerator kStatus_NoTransferInProgress

Generic status for no transfer in progress.

enumerator kStatus_Busy

Generic status for module is busy.

enumerator kStatus_NoData

Generic status for no data is found for the operation.

typedef int32_t status_t

Type used for all status and error return values.

void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size.

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters:

• size – The length required to malloc.

• alignbytes – The alignment size.

Return values:

The – allocated memory.

void SDK_Free(void *ptr)

Free memory.

Parameters:

• ptr – The memory to be release.

void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters:

• delayTime_us – Delay time in unit of microsecond.

• coreClock_Hz – Core clock frequency with Hz.

static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt.

Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt enabled successfully

• kStatus_Fail – Failed to enable the interrupt

static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt.

Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt disabled successfully

• kStatus_Fail – Failed to disable the interrupt

static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to Enable.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to set.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The flag which IRQ to clear.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ.

Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:

Current primask value.

static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ.

Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

• primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().

static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)

static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)

FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ

Macro to use the default weak IRQ handler in drivers.

MAKE_STATUS(group, code)

Construct a status code value from a group and code number.

MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers.

The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).

| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0

ARRAY_SIZE(x)

Computes the number of elements in an array.

UINT64_H(X)

Macro to get upper 32 bits of a 64-bit value

UINT64_L(X)

Macro to get lower 32 bits of a 64-bit value

SUPPRESS_FALL_THROUGH_WARNING()

For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.

MSDK_REG_SECURE_ADDR(x)

Convert the register address to the one used in secure mode.

MSDK_REG_NONSECURE_ADDR(x)

Convert the register address to the one used in non-secure mode.

LCDIFv2: LCD Interface v2

void LCDIFV2_Init(LCDIFV2_Type *base)

Initializes the LCDIF v2.

This function ungates the LCDIF v2 clock and release the peripheral reset.

Parameters:

• base – LCDIF v2 peripheral base address.

void LCDIFV2_Deinit(LCDIFV2_Type *base)

Deinitializes the LCDIF peripheral.

Parameters:

• base – LCDIF peripheral base address.

void LCDIFV2_Reset(LCDIFV2_Type *base)

Reset the LCDIF v2.

Parameters:

• base – LCDIF peripheral base address.

void LCDIFV2_DisplayGetDefaultConfig(lcdifv2_display_config_t *config)

Gets the LCDIF display default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config->panelWidth    = 0U;
config->panelHeight   = 0U;
config->hsw           = 3U;
config->hfp           = 3U;
config->hbp           = 3U;
config->vsw           = 3U;
config->vfp           = 3U;
config->vbp           = 3U;
config->polarityFlags = kLCDIFV2_VsyncActiveHigh | kLCDIFV2_HsyncActiveHigh | kLCDIFV2_DataEnableActiveHigh |
                        kLCDIFV2_DriveDataOnRisingClkEdge | kLCDIFV2_DataActiveHigh;
config->lineOrder       = kLCDIFV2_LineOrderRGB;

Parameters:

• config – Pointer to the LCDIF configuration structure.

void LCDIFV2_SetDisplayConfig(LCDIFV2_Type *base, const lcdifv2_display_config_t *config)

Set the LCDIF v2 display configurations.

Parameters:

• base – LCDIF peripheral base address.

• config – Pointer to the LCDIF configuration structure.

static inline void LCDIFV2_EnableDisplay(LCDIFV2_Type *base, bool enable)

Enable or disable the display.

Parameters:

• base – LCDIF peripheral base address.

• enable – Enable or disable.

static inline void LCDIFV2_EnableInterrupts(LCDIFV2_Type *base, uint8_t domain, uint32_t mask)

Enables LCDIF interrupt requests.

Parameters:

• base – LCDIF peripheral base address.

• domain – CPU domain the interrupt signal routed to.

• mask – interrupt source, OR’ed value of _lcdifv2_interrupt.

static inline void LCDIFV2_DisableInterrupts(LCDIFV2_Type *base, uint8_t domain, uint32_t mask)

Disables LCDIF interrupt requests.

Parameters:

• base – LCDIF peripheral base address.

• domain – CPU domain the interrupt signal routed to.

• mask – interrupt source, OR’ed value of _lcdifv2_interrupt.

static inline uint32_t LCDIFV2_GetInterruptStatus(LCDIFV2_Type *base, uint8_t domain)

Get LCDIF interrupt peding status.

Parameters:

• base – LCDIF peripheral base address.

• domain – CPU domain the interrupt signal routed to.

Returns:

Interrupt pending status, OR’ed value of _lcdifv2_interrupt.

static inline void LCDIFV2_ClearInterruptStatus(LCDIFV2_Type *base, uint8_t domain, uint32_t mask)

Clear LCDIF interrupt peding status.

Parameters:

• base – LCDIF peripheral base address.

• domain – CPU domain the interrupt signal routed to.

• mask – of the flags to clear, OR’ed value of _lcdifv2_interrupt.

status_t LCDIFV2_SetLut(LCDIFV2_Type *base, uint8_t layerIndex, const uint32_t *lutData, uint16_t count, bool useShadowLoad)

Set the LUT data.

This function sets the specific layer LUT data, if useShadowLoad is true, call LCDIFV2_TriggerLayerShadowLoad after this function, the LUT will be loaded to the hardware during next vertical blanking period. If useShadowLoad is false, the LUT data is loaded to hardware directly.

Parameters:

• base – LCDIF v2 peripheral base address.

• layerIndex – Which layer to set.

• lutData – The LUT data to load.

• count – Count of lutData.

• useShadowLoad – Use shadow load.

Return values:

• kStatus_Success – Set success.

• kStatus_Fail – Previous LUT data is not loaded to hardware yet.

static inline void LCDIFV2_SetLayerSize(LCDIFV2_Type *base, uint8_t layerIndex, uint16_t width, uint16_t height)

Set the layer dimension.

Note

The layer width must be in multiples of the number of pixels that can be stored in 32 bits

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

• width – Layer width in pixel.

• height – Layer height.

static inline void LCDIFV2_SetLayerOffset(LCDIFV2_Type *base, uint8_t layerIndex, uint16_t offsetX, uint16_t offsetY)

Set the layer position in output frame.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

• offsetX – Horizontal offset, start from 0.

• offsetY – Vertical offset, start from 0.

void LCDIFV2_SetLayerBufferConfig(LCDIFV2_Type *base, uint8_t layerIndex, const lcdifv2_buffer_config_t *config)

Set the layer source buffer configuration.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

• config – Pointer to the configuration.

static inline void LCDIFV2_SetLayerBufferAddr(LCDIFV2_Type *base, uint8_t layerIndex, uint32_t addr)

Set the layer source buffer address.

This function is used for fast runtime source buffer change.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

• addr – The new source buffer address passed to the layer, should be 64-bit aligned.

static inline void LCDIFV2_EnableLayer(LCDIFV2_Type *base, uint8_t layerIndex, bool enable)

Enable or disable the layer.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

• enable – Pass in true to enable, false to disable.

static inline void LCDIFV2_TriggerLayerShadowLoad(LCDIFV2_Type *base, uint8_t layerIndex)

Trigger the layer configuration shadow load.

The new layer configurations are written to the shadow registers first, When all configurations written finished, call this function, then shadowed control registers are updated to the active control registers on VSYNC of next frame.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Layer layerIndex.

static inline void LCDIFV2_SetLayerBackGroundColor(LCDIFV2_Type *base, uint8_t layerIndex, uint32_t backGroundColor)

Set the layer back ground color.

The back ground color is used when layer not actived.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Index of the layer.

• backGroundColor – Background color to use when this layer is not active.

void LCDIFV2_SetLayerBlendConfig(LCDIFV2_Type *base, uint8_t layerIndex, const lcdifv2_blend_config_t *config)

Set the layer alpha blend mode.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Index of the CSC unit.

• config – Pointer to the blend configuration.

void LCDIFV2_SetCscMode(LCDIFV2_Type *base, uint8_t layerIndex, lcdifv2_csc_mode_t mode)

Set the color space conversion mode.

Supports YUV2RGB and YCbCr2RGB.

Parameters:

• base – LCDIFv2 peripheral base address.

• layerIndex – Index of the layer.

• mode – The conversion mode.

status_t LCDIFV2_GetPorterDuffConfig(lcdifv2_pd_blend_mode_t mode, lcdifv2_pd_layer_t layer, lcdifv2_blend_config_t *config)

Get the blend configuration for Porter Duff blend.

This function gets the blend configuration for Porter Duff blend, config->pdFactorMode is set according to layer and mode, other blend configurations are set to:

config->pdAlphaMode = kLCDIFV2_PD_AlphaStraight;
config->pdColorMode = kLCDIFV2_PD_ColorStraight;
config->pdGlobalAlphaMode = kLCDIFV2_PD_LocalAlpha;
config->alphaMode = kLCDIFV2_AlphaPoterDuff;

This is the basic Porter Duff blend configuration, user still could modify the configurations after this function.

Parameters:

• mode – Porter Duff blend mode.

• layer – The configuration for source layer or destination layer.

• config – Pointer to the configuration.

Return values:

• kStatus_Success – Get the configuration successfully.

• kStatus_InvalidArgument – The argument is invalid.

status_t LCDIFV2_GetMultiLayerGlobalAlpha(const uint8_t blendedAlpha[], uint8_t globalAlpha[], uint8_t layerCount)

Get the global alpha values for multiple layer blend.

This function calculates the global alpha value for each layer based on the desired blended alpha.

When all layers use the global alpha, the relationship of blended alpha and global alpha of each layer is:

Layer 7: ba7 = ga7 Layer 6: ba6 = ga6 * (1-ga7) Layer 5: ba5 = ga5 * (1-ga6) * (1-ga7) Layer 4: ba4 = ga4 * (1-ga5) * (1-ga6) * (1-ga7) Layer 3: ba3 = ga3 * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7) Layer 2: ba2 = ga2 * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7) Layer 1: ba1 = ga1 * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7) Layer 0: ba0 = 1 * (1-ga1) * (1-ga2) * (1-ga3) * (1-ga4) * (1-ga5) * (1-ga6) * (1-ga7)

Here baN is the blended alpha of layer N, gaN is the global alpha configured to layer N.

This function calculates the global alpha based on the blended alpha. The blendedAlpha and globalAlpha are all arrays of size layerCount. The first layer is a background layer, so blendedAlpha[0] is useless, globalAlpha[0] is always 255.

Parameters:

• blendedAlpha – [in] The desired blended alpha value, alpha range 0~255.

• globalAlpha – [out] Calculated global alpha set to each layer register.

• layerCount – [in] Total layer count.

Return values:

• kStatus_Success – Get successfully.

• kStatus_InvalidArgument – The argument is invalid.

FSL_LCDIFV2_DRIVER_VERSION

LCDIF v2 driver version.

enum _lcdifv2_polarity_flags

LCDIF v2 signal polarity flags.

Values:

enumerator kLCDIFV2_VsyncActiveHigh

VSYNC active high.

enumerator kLCDIFV2_HsyncActiveHigh

HSYNC active high.

enumerator kLCDIFV2_DataEnableActiveHigh

Data enable line active high.

enumerator kLCDIFV2_DriveDataOnRisingClkEdge

Output data on rising clock edge, capture data on falling clock edge.

enumerator kLCDIFV2_DataActiveHigh

Data active high.

enumerator kLCDIFV2_VsyncActiveLow

VSYNC active low.

enumerator kLCDIFV2_HsyncActiveLow

HSYNC active low.

enumerator kLCDIFV2_DataEnableActiveLow

Data enable line active low.

enumerator kLCDIFV2_DriveDataOnFallingClkEdge

Output data on falling clock edge, capture data on rising clock edge.

enumerator kLCDIFV2_DataActiveLow

Data active high.

enum _lcdifv2_interrupt

The LCDIF v2 interrupts.

Values:

enumerator kLCDIFV2_Layer0FifoEmptyInterrupt

Layer 0 FIFO empty.

enumerator kLCDIFV2_Layer1FifoEmptyInterrupt

Layer 1 FIFO empty.

enumerator kLCDIFV2_Layer2FifoEmptyInterrupt

Layer 2 FIFO empty.

enumerator kLCDIFV2_Layer3FifoEmptyInterrupt

Layer 3 FIFO empty.

enumerator kLCDIFV2_Layer4FifoEmptyInterrupt

Layer 4 FIFO empty.

enumerator kLCDIFV2_Layer5FifoEmptyInterrupt

Layer 5 FIFO empty.

enumerator kLCDIFV2_Layer6FifoEmptyInterrupt

Layer 6 FIFO empty.

enumerator kLCDIFV2_Layer7FifoEmptyInterrupt

Layer 7 FIFO empty.

enumerator kLCDIFV2_Layer0DmaDoneInterrupt

Layer 0 DMA done.

enumerator kLCDIFV2_Layer1DmaDoneInterrupt

Layer 1 DMA done.

enumerator kLCDIFV2_Layer2DmaDoneInterrupt

Layer 2 DMA done.

enumerator kLCDIFV2_Layer3DmaDoneInterrupt

Layer 3 DMA done.

enumerator kLCDIFV2_Layer4DmaDoneInterrupt

Layer 4 DMA done.

enumerator kLCDIFV2_Layer5DmaDoneInterrupt

Layer 5 DMA done.

enumerator kLCDIFV2_Layer6DmaDoneInterrupt

Layer 6 DMA done.

enumerator kLCDIFV2_Layer7DmaDoneInterrupt

Layer 7 DMA done.

enumerator kLCDIFV2_Layer0DmaErrorInterrupt

Layer 0 DMA error.

enumerator kLCDIFV2_Layer1DmaErrorInterrupt

Layer 1 DMA error.

enumerator kLCDIFV2_Layer2DmaErrorInterrupt

Layer 2 DMA error.

enumerator kLCDIFV2_Layer3DmaErrorInterrupt

Layer 3 DMA error.

enumerator kLCDIFV2_Layer4DmaErrorInterrupt

Layer 4 DMA error.

enumerator kLCDIFV2_Layer5DmaErrorInterrupt

Layer 5 DMA error.

enumerator kLCDIFV2_Layer6DmaErrorInterrupt

Layer 6 DMA error.

enumerator kLCDIFV2_Layer7DmaErrorInterrupt

Layer 7 DMA error.

enumerator kLCDIFV2_VerticalBlankingInterrupt

Start of vertical blanking period.

enumerator kLCDIFV2_OutputUnderrunInterrupt

Output buffer underrun.

enumerator kLCDIFV2_VsyncEdgeInterrupt

Interrupt at VSYNC edge.

enum _lcdifv2_line_order

The LCDIF v2 output line order.

Values:

enumerator kLCDIFV2_LineOrderRGB

RGB

enumerator kLCDIFV2_LineOrderRBG

RBG

enumerator kLCDIFV2_LineOrderGBR

GBR

enumerator kLCDIFV2_LineOrderGRB

GRB

enumerator kLCDIFV2_LineOrderBRG

BRG

enumerator kLCDIFV2_LineOrderBGR

BGR

enum _lcdifv2_csc_mode

LCDIF v2 color space conversion mode.

Values:

enumerator kLCDIFV2_CscDisable

Disable the CSC.

enumerator kLCDIFV2_CscYUV2RGB

YUV to RGB.

enumerator kLCDIFV2_CscYCbCr2RGB

YCbCr to RGB.

enum _lcdifv2_pixel_format

LCDIF v2 pixel format.

Values:

enumerator kLCDIFV2_PixelFormatIndex1BPP

LUT index 1 bit.

enumerator kLCDIFV2_PixelFormatIndex2BPP

LUT index 2 bit.

enumerator kLCDIFV2_PixelFormatIndex4BPP

LUT index 4 bit.

enumerator kLCDIFV2_PixelFormatIndex8BPP

LUT index 8 bit.

enumerator kLCDIFV2_PixelFormatRGB565

RGB565, two pixels use 32 bits.

enumerator kLCDIFV2_PixelFormatARGB1555

ARGB1555, two pixels use 32 bits.

enumerator kLCDIFV2_PixelFormatARGB4444

ARGB4444, two pixels use 32 bits.

enumerator kLCDIFV2_PixelFormatUYVY

UYVY, only layer 0 and layer 1 support this.

enumerator kLCDIFV2_PixelFormatVYUY

VYUY, only layer 0 and layer 1 support this.

enumerator kLCDIFV2_PixelFormatYUYV

YUYV, only layer 0 and layer 1 support this.

enumerator kLCDIFV2_PixelFormatYVYU

YVYU, only layer 0 and layer 1 support this.

enumerator kLCDIFV2_PixelFormatRGB888

RGB888 packed, one pixel uses 24 bits.

enumerator kLCDIFV2_PixelFormatARGB8888

ARGB8888 unpacked, one pixel uses 32 bits.

enumerator kLCDIFV2_PixelFormatABGR8888

ABGR8888 unpacked, one pixel uses 32 bits.

enum _lcdifv2_alpha_mode

LCDIF v2 layer alpha blending mode.

Values:

enumerator kLCDIFV2_AlphaDisable

Disable alpha blend.

enumerator kLCDIFV2_AlphaOverride

Use the gobal alpha value, pixel defined alpha value is overridden.

enumerator kLCDIFV2_AlphaEmbedded

Use the pixel defined alpha value.

enumerator kLCDIFV2_AlphaPoterDuff

Use the PoterDuff alpha blending.

enum _lcdifv2_pd_alpha_mode

LCDIF v2 PoterDuff alpha mode.

Values:

enumerator kLCDIFV2_PD_AlphaStraight

Straight mode.

enumerator kLCDIFV2_PD_AlphaInversed

Inversed mode.

enum _lcdifv2_pd_color_mode

LCDIF v2 PoterDuff color mode.

Values:

enumerator kLCDIFV2_PD_ColorNoAlpha

Output color directly.

enumerator kLCDIFV2_PD_ColorWithAlpha

Output color multiples alpha.

enum _lcdifv2_pd_global_alpha_mode

LCDIF v2 PoterDuff global alpha mode.

Values:

enumerator kLCDIFV2_PD_GlobalAlpha

Use global alpha.

enumerator kLCDIFV2_PD_LocalAlpha

Use local alpha.

enumerator kLCDIFV2_PD_ScaledAlpha

Use scaled alpha.

enum _lcdifv2_pd_factor_mode

LCDIF v2 PoterDuff factor mode.

Values:

enumerator kLCDIFV2_PD_FactorOne

Use 1.

enumerator kLCDIFV2_PD_FactorZero

Use 0.

enumerator kLCDIFV2_PD_FactorStraightAlpha

Use straight alpha.

enumerator kLCDIFV2_PD_FactorInversedAlpha

Use inversed alpha.

enum _lcdifv2_pd_blend_mode

LCDIFv2 Porter Duff blend mode. Note: Don’t change the enum item value.

Values:

enumerator kLCDIFV2_PD_Src

Source Only

enumerator kLCDIFV2_PD_Atop

Source Atop

enumerator kLCDIFV2_PD_Over

Source Over

enumerator kLCDIFV2_PD_In

Source In.

enumerator kLCDIFV2_PD_Out

Source Out.

enumerator kLCDIFV2_PD_Dst

Destination Only.

enumerator kLCDIFV2_PD_DstAtop

Destination Atop.

enumerator kLCDIFV2_PD_DstOver

Destination Over.

enumerator kLCDIFV2_PD_DstIn

Destination In.

enumerator kLCDIFV2_PD_DstOut

Destination Out.

enumerator kLCDIFV2_PD_Xor

XOR.

enumerator kLCDIFV2_PD_Clear

Clear.

enumerator kLCDIFV2_PD_Max

Used for boarder detection.

enum _lcdifv2_pd_layer

LCDIFv2 Porter Duff layer. Note: Don’t change the enum item value.

Values:

enumerator kLCDIFV2_PD_SrcLayer

Source layer.

enumerator kLCDIFV2_PD_DestLayer

Destination layer.

enumerator kLCDIFV2_PD_LayerMax

Used for boarder detection.

typedef enum _lcdifv2_line_order lcdifv2_line_order_t

The LCDIF v2 output line order.

typedef struct _lcdifv2_display_config lcdifv2_display_config_t

LCDIF v2 display configure structure.

typedef enum _lcdifv2_csc_mode lcdifv2_csc_mode_t

LCDIF v2 color space conversion mode.

typedef enum _lcdifv2_pixel_format lcdifv2_pixel_format_t

LCDIF v2 pixel format.

typedef struct _lcdifv2_buffer_config lcdifv2_buffer_config_t

LCDIF v2 source buffer configuration.

typedef enum _lcdifv2_alpha_mode lcdifv2_alpha_mode_t

LCDIF v2 layer alpha blending mode.

typedef enum _lcdifv2_pd_alpha_mode lcdifv2_pd_alpha_mode_t

LCDIF v2 PoterDuff alpha mode.

typedef enum _lcdifv2_pd_color_mode lcdifv2_pd_color_mode_t

LCDIF v2 PoterDuff color mode.

typedef enum _lcdifv2_pd_global_alpha_mode lcdifv2_pd_global_alpha_mode_t

LCDIF v2 PoterDuff global alpha mode.

typedef enum _lcdifv2_pd_factor_mode lcdifv2_pd_factor_mode_t

LCDIF v2 PoterDuff factor mode.

typedef struct _lcdifv2_blend_config lcdifv2_blend_config_t

LCDIF v2 layer alpha blending configuration.

typedef enum _lcdifv2_pd_blend_mode lcdifv2_pd_blend_mode_t

LCDIFv2 Porter Duff blend mode. Note: Don’t change the enum item value.

typedef enum _lcdifv2_pd_layer lcdifv2_pd_layer_t

LCDIFv2 Porter Duff layer. Note: Don’t change the enum item value.

LCDIFV2_LAYER_COUNT

LCDIFV2_LAYER_CSC_COUNT

LCDIFV2_ADDR_CPU_2_IP(addr)

LCDIFV2_MAKE_FIFO_EMPTY_INTERRUPT(layer)

LCDIF v2 FIFO empty interrupt.

LCDIFV2_MAKE_DMA_DONE_INTERRUPT(layer)

LCDIF v2 DMA done interrupt.

LCDIFV2_MAKE_DMA_ERROR_INTERRUPT(layer)

LCDIF v2 DMA error interrupt.

LCDIFV2_LUT_ENTRY_NUM

struct _lcdifv2_display_config

#include <fsl_lcdifv2.h>

LCDIF v2 display configure structure.

Public Members

uint16_t panelWidth

Display panel width, pixels per line.

uint16_t panelHeight

Display panel height, how many lines per panel.

uint8_t hsw

HSYNC pulse width.

uint8_t hfp

Horizontal front porch.

uint8_t hbp

Horizontal back porch.

uint8_t vsw

VSYNC pulse width.

uint8_t vfp

Vrtical front porch.

uint8_t vbp

Vertical back porch.

uint32_t polarityFlags

OR’ed value of _lcdifv2_polarity_flags, used to contol the signal polarity.

lcdifv2_line_order_t lineOrder

Line order.

struct _lcdifv2_buffer_config

#include <fsl_lcdifv2.h>

LCDIF v2 source buffer configuration.

Public Members

uint16_t strideBytes

Number of bytes between two vertically adjacent pixels, suggest 64-bit aligned.

lcdifv2_pixel_format_t pixelFormat

Source buffer pixel format.

struct _lcdifv2_blend_config

#include <fsl_lcdifv2.h>

LCDIF v2 layer alpha blending configuration.

Public Members

uint8_t globalAlpha

Global alpha value, only used when alphaMode is kLCDIFV2_AlphaOverride or kLCDIFV2_AlphaPoterDuff

lcdifv2_alpha_mode_t alphaMode

Alpha mode.

lcdifv2_pd_alpha_mode_t pdAlphaMode

PoterDuff alpha mode, only used when alphaMode is kLCDIFV2_AlphaPoterDuff

lcdifv2_pd_color_mode_t pdColorMode

PoterDuff color mode, only used when alphaMode is kLCDIFV2_AlphaPoterDuff

lcdifv2_pd_global_alpha_mode_t pdGlobalAlphaMode

PoterDuff global alpha mode, only used when alphaMode is kLCDIFV2_AlphaPoterDuff

lcdifv2_pd_factor_mode_t pdFactorMode

PoterDuff factor mode, only used when alphaMode is kLCDIFV2_AlphaPoterDuff

LPADC: 12-bit SAR Analog-to-Digital Converter Driver

void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)

Initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• config – Pointer to configuration structure. See “lpadc_config_t”.

void LPADC_GetDefaultConfig(lpadc_config_t *config)

Gets an available pre-defined settings for initial configuration.

This function initializes the converter configuration structure with an available settings. The default values are:

config->enableInDozeMode        = true;
config->enableAnalogPreliminary = false;
config->powerUpDelay            = 0x80;
config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
config->powerLevelMode          = kLPADC_PowerLevelAlt1;
config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
config->enableConvPause         = false;
config->convPauseDelay          = 0U;
config->FIFOWatermark           = 0U;

Parameters:

• config – Pointer to configuration structure.

void LPADC_Deinit(ADC_Type *base)

De-initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_Enable(ADC_Type *base, bool enable)

Switch on/off the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the module.

static inline void LPADC_DoResetFIFO(ADC_Type *base)

Do reset the conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_DoResetConfig(ADC_Type *base)

Do reset the module’s configuration.

Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).

Parameters:

• base – LPADC peripheral base address.

static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)

Get status flags.

Parameters:

• base – LPADC peripheral base address.

Returns:

status flags’ mask. See to _lpadc_status_flags.

static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)

Clear status flags.

Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for flags to be cleared. See to _lpadc_status_flags.

static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)

Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high priority trigger exception.

Parameters:

• base – LPADC peripheral base address.

Returns:

The OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)

Clear trigger status flags.

Parameters:

• base – LPADC peripheral base address.

• mask – The mask of trigger status flags to be cleared, should be the OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)

Switch on/off the DMA trigger for FIFO watermark event.

Parameters:

• base – LPADC peripheral base address.

• enable – Switcher to the event.

static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)

Get the count of result kept in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

Returns:

The count of result kept in conversion FIFO.

bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

Returns:

Status whether FIFO entry is valid.

void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO using blocking method.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)

Configure the conversion trigger source.

Each programmable trigger can launch the conversion command in command buffer.

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• config – Pointer to configuration structure. See to lpadc_conv_trigger_config_t.

void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)

Gets an available pre-defined settings for trigger’s configuration.

This function initializes the trigger’s configuration structure with an available settings. The default values are:

config->targetCommandId        = 0U;
config->delayPower             = 0U;
config->priority               = 0U;
config->channelAFIFOSelect     = 0U;
config->channelBFIFOSelect     = 0U;
config->enableHardwareTrigger  = false;

Parameters:

• config – Pointer to configuration structure.

static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)

Do software trigger to conversion command.

Parameters:

• base – LPADC peripheral base address.

• triggerIdMask – Mask value for software trigger indexes, which count from zero.

static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)

Enable hardware trigger command selection.

This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL].

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• enable – True to enable or flase to disable.

void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)

Configure conversion command.

Note

The number of compare value register on different chips is different, that is mean in some chips, some command buffers do not have the compare functionality.

Parameters:

• base – LPADC peripheral base address.

• commandId – ID for command in command buffer. Typically, the available value range is 1 - 15.

• config – Pointer to configuration structure. See to lpadc_conv_command_config_t.

void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)

Gets an available pre-defined settings for conversion command’s configuration.

This function initializes the conversion command’s configuration structure with an available settings. The default values are:

config->sampleScaleMode            = kLPADC_SampleFullScale;
config->channelBScaleMode          = kLPADC_SampleFullScale;
config->sampleChannelMode          = kLPADC_SampleChannelSingleEndSideA;
config->channelNumber              = 0U;
config->channelBNumber             = 0U;
config->chainedNextCommandNumber   = 0U;
config->enableAutoChannelIncrement = false;
config->loopCount                  = 0U;
config->hardwareAverageMode        = kLPADC_HardwareAverageCount1;
config->sampleTimeMode             = kLPADC_SampleTimeADCK3;
config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
config->hardwareCompareValueHigh   = 0U;
config->hardwareCompareValueLow    = 0U;
config->conversionResolutionMode   = kLPADC_ConversionResolutionStandard;
config->enableWaitTrigger          = false;
config->enableChannelB             = false;

Parameters:

• config – Pointer to configuration structure.

void LPADC_EnableCalibration(ADC_Type *base, bool enable)

Enable the calibration function.

When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)

Set proper offset value to trim ADC.

To minimize the offset during normal operation, software should read the conversion result from the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.

Parameters:

• base – LPADC peripheral base address.

• value – Setting offset value.

void LPADC_DoAutoCalibration(ADC_Type *base)

Do auto calibration.

Calibration function should be executed before using converter in application. It used the software trigger and a dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -LPADC_EnableCalibration(…) -LPADC_LPADC_SetOffsetValue(…) -LPADC_SetConvCommandConfig(…) -LPADC_SetConvTriggerConfig(…)

Parameters:

• base – LPADC peripheral base address.

• base – LPADC peripheral base address.

static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)

Enable the offset calibration function.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)

Set offset calibration mode.

Parameters:

• base – LPADC peripheral base address.

• mode – set offset calibration mode.see to lpadc_offset_calibration_mode_t .

void LPADC_DoOffsetCalibration(ADC_Type *base)

Do offset calibration.

Parameters:

• base – LPADC peripheral base address.

void LPADC_PrepareAutoCalibration(ADC_Type *base)

Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.

Parameters:

• base – LPADC peripheral base address.

void LPADC_FinishAutoCalibration(ADC_Type *base)

Finish auto calibration start with LPADC_PrepareAutoCalibration.

Note

This feature is used for LPADC with CTRL[CALOFSMODE].

Parameters:

• base – LPADC peripheral base address.

void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue)

Get calibration value into the memory which is defined by invoker.

Note

Please note the ADC will be disabled temporary.

Note

This function should be used after finish calibration.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure, this memory block should be always powered on even in low power modes.

void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue)

Set calibration value into ADC calibration registers.

Note

Please note the ADC will be disabled temporary.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure which contains ADC’s calibration value.

FSL_LPADC_DRIVER_VERSION

LPADC driver version 2.9.1.

enum _lpadc_status_flags

Define hardware flags of the module.

Values:

enumerator kLPADC_ResultFIFO0OverflowFlag

Indicates that more data has been written to the Result FIFO 0 than it can hold.

enumerator kLPADC_ResultFIFO0ReadyFlag

Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level.

enumerator kLPADC_TriggerExceptionFlag

Indicates that a trigger exception event has occurred.

enumerator kLPADC_TriggerCompletionFlag

Indicates that a trigger completion event has occurred.

enumerator kLPADC_CalibrationReadyFlag

Indicates that the calibration process is done.

enumerator kLPADC_ActiveFlag

Indicates that the ADC is in active state.

enumerator kLPADC_ResultFIFOOverflowFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowFlag as instead.

enumerator kLPADC_ResultFIFOReadyFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0ReadyFlag as instead.

enum _lpadc_interrupt_enable

Define interrupt switchers of the module.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_ResultFIFO0OverflowInterruptEnable

Configures ADC to generate overflow interrupt requests when FOF0 flag is asserted.

enumerator kLPADC_FIFO0WatermarkInterruptEnable

Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted.

enumerator kLPADC_ResultFIFOOverflowInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowInterruptEnable as instead.

enumerator kLPADC_FIFOWatermarkInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_FIFO0WatermarkInterruptEnable as instead.

enumerator kLPADC_TriggerExceptionInterruptEnable

Configures ADC to generate trigger exception interrupt.

enumerator kLPADC_Trigger0CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 0 completion.

enumerator kLPADC_Trigger1CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 1 completion.

enumerator kLPADC_Trigger2CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 2 completion.

enumerator kLPADC_Trigger3CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 3 completion.

enumerator kLPADC_Trigger4CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 4 completion.

enumerator kLPADC_Trigger5CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 5 completion.

enumerator kLPADC_Trigger6CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 6 completion.

enumerator kLPADC_Trigger7CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 7 completion.

enumerator kLPADC_Trigger8CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 8 completion.

enumerator kLPADC_Trigger9CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 9 completion.

enumerator kLPADC_Trigger10CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 10 completion.

enumerator kLPADC_Trigger11CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 11 completion.

enumerator kLPADC_Trigger12CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 12 completion.

enumerator kLPADC_Trigger13CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 13 completion.

enumerator kLPADC_Trigger14CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 14 completion.

enumerator kLPADC_Trigger15CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 15 completion.

enum _lpadc_trigger_status_flags

The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_Trigger0InterruptedFlag

Trigger 0 is interrupted by a high priority exception.

enumerator kLPADC_Trigger1InterruptedFlag

Trigger 1 is interrupted by a high priority exception.

enumerator kLPADC_Trigger2InterruptedFlag

Trigger 2 is interrupted by a high priority exception.

enumerator kLPADC_Trigger3InterruptedFlag

Trigger 3 is interrupted by a high priority exception.

enumerator kLPADC_Trigger4InterruptedFlag

Trigger 4 is interrupted by a high priority exception.

enumerator kLPADC_Trigger5InterruptedFlag

Trigger 5 is interrupted by a high priority exception.

enumerator kLPADC_Trigger6InterruptedFlag

Trigger 6 is interrupted by a high priority exception.

enumerator kLPADC_Trigger7InterruptedFlag

Trigger 7 is interrupted by a high priority exception.

enumerator kLPADC_Trigger8InterruptedFlag

Trigger 8 is interrupted by a high priority exception.

enumerator kLPADC_Trigger9InterruptedFlag

Trigger 9 is interrupted by a high priority exception.

enumerator kLPADC_Trigger10InterruptedFlag

Trigger 10 is interrupted by a high priority exception.

enumerator kLPADC_Trigger11InterruptedFlag

Trigger 11 is interrupted by a high priority exception.

enumerator kLPADC_Trigger12InterruptedFlag

Trigger 12 is interrupted by a high priority exception.

enumerator kLPADC_Trigger13InterruptedFlag

Trigger 13 is interrupted by a high priority exception.

enumerator kLPADC_Trigger14InterruptedFlag

Trigger 14 is interrupted by a high priority exception.

enumerator kLPADC_Trigger15InterruptedFlag

Trigger 15 is interrupted by a high priority exception.

enumerator kLPADC_Trigger0CompletedFlag

Trigger 0 is completed and trigger 0 has enabled completion interrupts.

enumerator kLPADC_Trigger1CompletedFlag

Trigger 1 is completed and trigger 1 has enabled completion interrupts.

enumerator kLPADC_Trigger2CompletedFlag

Trigger 2 is completed and trigger 2 has enabled completion interrupts.

enumerator kLPADC_Trigger3CompletedFlag

Trigger 3 is completed and trigger 3 has enabled completion interrupts.

enumerator kLPADC_Trigger4CompletedFlag

Trigger 4 is completed and trigger 4 has enabled completion interrupts.

enumerator kLPADC_Trigger5CompletedFlag

Trigger 5 is completed and trigger 5 has enabled completion interrupts.

enumerator kLPADC_Trigger6CompletedFlag

Trigger 6 is completed and trigger 6 has enabled completion interrupts.

enumerator kLPADC_Trigger7CompletedFlag

Trigger 7 is completed and trigger 7 has enabled completion interrupts.

enumerator kLPADC_Trigger8CompletedFlag

Trigger 8 is completed and trigger 8 has enabled completion interrupts.

enumerator kLPADC_Trigger9CompletedFlag

Trigger 9 is completed and trigger 9 has enabled completion interrupts.

enumerator kLPADC_Trigger10CompletedFlag

Trigger 10 is completed and trigger 10 has enabled completion interrupts.

enumerator kLPADC_Trigger11CompletedFlag

Trigger 11 is completed and trigger 11 has enabled completion interrupts.

enumerator kLPADC_Trigger12CompletedFlag

Trigger 12 is completed and trigger 12 has enabled completion interrupts.

enumerator kLPADC_Trigger13CompletedFlag

Trigger 13 is completed and trigger 13 has enabled completion interrupts.

enumerator kLPADC_Trigger14CompletedFlag

Trigger 14 is completed and trigger 14 has enabled completion interrupts.

enumerator kLPADC_Trigger15CompletedFlag

Trigger 15 is completed and trigger 15 has enabled completion interrupts.

enum _lpadc_sample_scale_mode

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

Values:

enumerator kLPADC_SamplePartScale

Use divided input voltage signal. (For scale select,please refer to the reference manual).

enumerator kLPADC_SampleFullScale

Full scale (Factor of 1).

enum _lpadc_sample_channel_mode

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

Values:

enumerator kLPADC_SampleChannelSingleEndSideA

Single-end mode, only A-side channel is converted.

enumerator kLPADC_SampleChannelSingleEndSideB

Single-end mode, only B-side channel is converted.

enumerator kLPADC_SampleChannelDiffBothSideAB

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDiffBothSideBA

Differential mode, the ADC result is (CHnB-CHnA).

enumerator kLPADC_SampleChannelDiffBothSide

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDualSingleEndBothSide

Dual-Single-Ended Mode. Both A side and B side channels are converted independently.

enum _lpadc_hardware_average_mode

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

Values:

enumerator kLPADC_HardwareAverageCount1

Single conversion.

enumerator kLPADC_HardwareAverageCount2

2 conversions averaged.

enumerator kLPADC_HardwareAverageCount4

4 conversions averaged.

enumerator kLPADC_HardwareAverageCount8

8 conversions averaged.

enumerator kLPADC_HardwareAverageCount16

16 conversions averaged.

enumerator kLPADC_HardwareAverageCount32

32 conversions averaged.

enumerator kLPADC_HardwareAverageCount64

64 conversions averaged.

enumerator kLPADC_HardwareAverageCount128

128 conversions averaged.

enum _lpadc_sample_time_mode

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

Values:

enumerator kLPADC_SampleTimeADCK3

3 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK5

5 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK7

7 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK11

11 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK19

19 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK35

35 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK67

69 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK131

131 ADCK cycles total sample time.

enum _lpadc_hardware_compare_mode

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

Values:

enumerator kLPADC_HardwareCompareDisabled

Compare disabled.

enumerator kLPADC_HardwareCompareStoreOnTrue

Compare enabled. Store on true.

enumerator kLPADC_HardwareCompareRepeatUntilTrue

Compare enabled. Repeat channel acquisition until true.

enum _lpadc_conversion_resolution_mode

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

Values:

enumerator kLPADC_ConversionResolutionStandard

Standard resolution. Single-ended 12-bit conversion, Differential 13-bit conversion with 2’s complement output.

enumerator kLPADC_ConversionResolutionHigh

High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2’s complement output.

enum _lpadc_conversion_average_mode

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

Values:

enumerator kLPADC_ConversionAverage1

Single conversion.

enumerator kLPADC_ConversionAverage2

2 conversions averaged.

enumerator kLPADC_ConversionAverage4

4 conversions averaged.

enumerator kLPADC_ConversionAverage8

8 conversions averaged.

enumerator kLPADC_ConversionAverage16

16 conversions averaged.

enumerator kLPADC_ConversionAverage32

32 conversions averaged.

enumerator kLPADC_ConversionAverage64

64 conversions averaged.

enumerator kLPADC_ConversionAverage128

128 conversions averaged.

enum _lpadc_reference_voltage_mode

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

Values:

enumerator kLPADC_ReferenceVoltageAlt1

Option 1 setting.

enumerator kLPADC_ReferenceVoltageAlt2

Option 2 setting.

enumerator kLPADC_ReferenceVoltageAlt3

Option 3 setting.

enum _lpadc_power_level_mode

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

Values:

enumerator kLPADC_PowerLevelAlt1

Lowest power setting.

enumerator kLPADC_PowerLevelAlt2

Next lowest power setting.

enumerator kLPADC_PowerLevelAlt3

…

enumerator kLPADC_PowerLevelAlt4

Highest power setting.

enum _lpadc_offset_calibration_mode

Define enumeration of offset calibration mode.

Values:

enumerator kLPADC_OffsetCalibration12bitMode

12 bit offset calibration mode.

enumerator kLPADC_OffsetCalibration16bitMode

16 bit offset calibration mode.

enum _lpadc_trigger_priority_policy

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

Values:

enumerator kLPADC_ConvPreemptImmediatelyNotAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion is not automatically resumed or restarted.

enumerator kLPADC_ConvPreemptSoftlyNotAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion is not resumed or restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoRestarted

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptSoftlyAutoRestarted

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be resumed.

enumerator kLPADC_ConvPreemptSoftlyAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will be automatically be resumed.

enumerator kLPADC_TriggerPriorityPreemptImmediately

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityPreemptSoftly

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityExceptionDisabled

High priority trigger exception disabled.

typedef enum _lpadc_sample_scale_mode lpadc_sample_scale_mode_t

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

typedef enum _lpadc_sample_channel_mode lpadc_sample_channel_mode_t

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

typedef enum _lpadc_hardware_average_mode lpadc_hardware_average_mode_t

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

typedef enum _lpadc_sample_time_mode lpadc_sample_time_mode_t

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

typedef enum _lpadc_hardware_compare_mode lpadc_hardware_compare_mode_t

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

typedef enum _lpadc_conversion_resolution_mode lpadc_conversion_resolution_mode_t

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

typedef enum _lpadc_conversion_average_mode lpadc_conversion_average_mode_t

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

typedef enum _lpadc_reference_voltage_mode lpadc_reference_voltage_source_t

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

typedef enum _lpadc_power_level_mode lpadc_power_level_mode_t

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

typedef enum _lpadc_offset_calibration_mode lpadc_offset_calibration_mode_t

Define enumeration of offset calibration mode.

typedef enum _lpadc_trigger_priority_policy lpadc_trigger_priority_policy_t

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

typedef struct _lpadc_calibration_value lpadc_calibration_value_t

A structure of calibration value.

LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal)

Define the MACRO function to get command status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal)

Define the MACRO function to get trigger status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

struct lpadc_config_t

#include <fsl_lpadc.h>

LPADC global configuration.

This structure would used to keep the settings for initialization.

Public Members

bool enableInternalClock

Enables the internally generated clock source. The clock source is used in clock selection logic at the chip level and is optionally used for the ADC clock source.

bool enableVref1LowVoltage

If voltage reference option1 input is below 1.8V, it should be “true”. If voltage reference option1 input is above 1.8V, it should be “false”.

bool enableInDozeMode

Control system transition to Stop and Wait power modes while ADC is converting. When enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.

lpadc_conversion_average_mode_t conversionAverageMode

Auto-Calibration Averages.

bool enableAnalogPreliminary

ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).

uint32_t powerUpDelay

When the analog circuits are not pre-enabled, the ADC analog circuits are only powered while the ADC is active and there is a counted delay defined by this field after an initial trigger transitions the ADC from its Idle state to allow time for the analog circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must result in a longer delay than the analog startup time.

lpadc_reference_voltage_source_t referenceVoltageSource

Selects the voltage reference high used for conversions.

lpadc_power_level_mode_t powerLevelMode

Power Configuration Selection.

lpadc_trigger_priority_policy_t triggerPriorityPolicy

Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t.

bool enableConvPause

Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations, between commands in a sequence, and between conversions when command is executing in “Compare Until True” configuration.

uint32_t convPauseDelay

Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing function is enabled. The available value range is in 9-bit.

uint32_t FIFOWatermark

FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold.

struct lpadc_conv_command_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion command.

Public Members

lpadc_sample_scale_mode_t sampleScaleMode

Sample scale mode.

lpadc_sample_scale_mode_t channelBScaleMode

Alternate channe B Scale mode.

lpadc_sample_channel_mode_t sampleChannelMode

Channel sample mode.

uint32_t channelNumber

Channel number, select the channel or channel pair.

uint32_t channelBNumber

Alternate Channel B number, select the channel.

uint32_t chainedNextCommandNumber

Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command.

bool enableAutoChannelIncrement

Loop with increment: when disabled, the “loopCount” field selects the number of times the selected channel is converted consecutively; when enabled, the “loopCount” field defines how many consecutive channels are converted as part of the command execution.

uint32_t loopCount

Selects how many times this command executes before finish and transition to the next command or Idle state. Command executes LOOP+1 times. 0-15 is available.

lpadc_hardware_average_mode_t hardwareAverageMode

Hardware average selection.

lpadc_sample_time_mode_t sampleTimeMode

Sample time selection.

lpadc_hardware_compare_mode_t hardwareCompareMode

Hardware compare selection.

uint32_t hardwareCompareValueHigh

Compare Value High. The available value range is in 16-bit.

uint32_t hardwareCompareValueLow

Compare Value Low. The available value range is in 16-bit.

lpadc_conversion_resolution_mode_t conversionResolutionMode

Conversion resolution mode.

bool enableWaitTrigger

Wait for trigger assertion before execution: when disabled, this command will be automatically executed; when enabled, the active trigger must be asserted again before executing this command.

struct lpadc_conv_trigger_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion trigger.

Public Members

uint32_t targetCommandId

Select the command from command buffer to execute upon detect of the associated trigger event.

uint32_t delayPower

Select the trigger delay duration to wait at the start of servicing a trigger event. When this field is clear, then no delay is incurred. When this field is set to a non-zero value, the duration for the delay is 2^delayPower ADCK cycles. The available value range is 4-bit.

uint32_t priority

Sets the priority of the associated trigger source. If two or more triggers have the same priority level setting, the lower order trigger event has the higher priority. The lower value for this field is for the higher priority, the available value range is 1-bit.

bool enableHardwareTrigger

Enable hardware trigger source to initiate conversion on the rising edge of the input trigger source or not. THe software trigger is always available.

struct lpadc_conv_result_t

#include <fsl_lpadc.h>

Define the structure to keep the conversion result.

Public Members

uint32_t commandIdSource

Indicate the command buffer being executed that generated this result.

uint32_t loopCountIndex

Indicate the loop count value during command execution that generated this result.

uint32_t triggerIdSource

Indicate the trigger source that initiated a conversion and generated this result.

uint16_t convValue

Data result.

struct _lpadc_calibration_value

#include <fsl_lpadc.h>

A structure of calibration value.

LPI2C: Low Power Inter-Integrated Circuit Driver

FSL_LPI2C_DRIVER_VERSION

LPI2C driver version.

LPI2C status return codes.

Values:

enumerator kStatus_LPI2C_Busy

The master is already performing a transfer.

enumerator kStatus_LPI2C_Idle

The slave driver is idle.

enumerator kStatus_LPI2C_Nak

The slave device sent a NAK in response to a byte.

enumerator kStatus_LPI2C_FifoError

FIFO under run or overrun.

enumerator kStatus_LPI2C_BitError

Transferred bit was not seen on the bus.

enumerator kStatus_LPI2C_ArbitrationLost

Arbitration lost error.

enumerator kStatus_LPI2C_PinLowTimeout

SCL or SDA were held low longer than the timeout.

enumerator kStatus_LPI2C_NoTransferInProgress

Attempt to abort a transfer when one is not in progress.

enumerator kStatus_LPI2C_DmaRequestFail

DMA request failed.

enumerator kStatus_LPI2C_Timeout

Timeout polling status flags.

IRQn_Type const kLpi2cIrqs[]

Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs.

lpi2c_master_isr_t s_lpi2cMasterIsr

Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

void *s_lpi2cMasterHandle[]

Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

uint32_t LPI2C_GetInstance(LPI2C_Type *base)

Returns an instance number given a base address.

If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

LPI2C instance number starting from 0.

I2C_RETRY_TIMES

Retry times for waiting flag.

LPI2C Master Driver

void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)

Provides a default configuration for the LPI2C master peripheral.

This function provides the following default configuration for the LPI2C master peripheral:

masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

• masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t.

void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C master peripheral.

This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

• base – The LPI2C peripheral base address.

• masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void LPI2C_MasterDeinit(LPI2C_Type *base)

Deinitializes the LPI2C master peripheral.

This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)

Configures LPI2C master data match feature.

Parameters:

• base – The LPI2C peripheral base address.

• matchConfig – Settings for the data match feature.

status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)

Convert provided flags to status code, and clear any errors if present.

Parameters:

• base – The LPI2C peripheral base address.

• status – Current status flags value that will be checked.

Return values:

• kStatus_Success –

• kStatus_LPI2C_PinLowTimeout –

• kStatus_LPI2C_ArbitrationLost –

• kStatus_LPI2C_Nak –

• kStatus_LPI2C_FifoError –

status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)

Make sure the bus isn’t already busy.

A busy bus is allowed if we are the one driving it.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success –

• kStatus_LPI2C_Busy –

static inline void LPI2C_MasterReset(LPI2C_Type *base)

Performs a software reset.

Restores the LPI2C master peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as master.

static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C master status flags.

A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_master_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C master status flag state.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_master_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags().

static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C master interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)

Enables or disables LPI2C master DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)

Gets LPI2C master transmit data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Transmit Data Register address.

static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)

Gets LPI2C master receive data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Receive Data Register address.

static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)

Sets the watermarks for LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated.

• rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of words in the LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required.

void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)

Sets the I2C bus frequency for master transactions.

The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note

Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.

Parameters:

• base – The LPI2C peripheral base address.

• sourceClock_Hz – LPI2C functional clock frequency in Hertz.

• baudRate_Hz – Requested bus frequency in Hertz.

static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the master mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a START signal and slave address on the I2C bus.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a repeated START signal and slave address on the I2C bus.

This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note

This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)

Performs a polling send transfer on the I2C bus.

Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was sent successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or over run.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterStop(LPI2C_Type *base)

Sends a STOP signal on the I2C bus.

This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to error happens during transfer.

Parameters:

• base – The LPI2C peripheral base address.

• transfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C master non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• lpi2cMasterHandle – Pointer to the LPI2C master driver handle.

enum _lpi2c_master_flags

LPI2C master peripheral flags.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_MasterTxReadyFlag

Transmit data flag

enumerator kLPI2C_MasterRxReadyFlag

Receive data flag

enumerator kLPI2C_MasterEndOfPacketFlag

End Packet flag

enumerator kLPI2C_MasterStopDetectFlag

Stop detect flag

enumerator kLPI2C_MasterNackDetectFlag

NACK detect flag

enumerator kLPI2C_MasterArbitrationLostFlag

Arbitration lost flag

enumerator kLPI2C_MasterFifoErrFlag

FIFO error flag

enumerator kLPI2C_MasterPinLowTimeoutFlag

Pin low timeout flag

enumerator kLPI2C_MasterDataMatchFlag

Data match flag

enumerator kLPI2C_MasterBusyFlag

Master busy flag

enumerator kLPI2C_MasterBusBusyFlag

Bus busy flag

enumerator kLPI2C_MasterClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_MasterIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_MasterErrorFlags

Errors to check for.

enum _lpi2c_direction

Direction of master and slave transfers.

Values:

enumerator kLPI2C_Write

Master transmit.

enumerator kLPI2C_Read

Master receive.

enum _lpi2c_master_pin_config

LPI2C pin configuration.

Values:

enumerator kLPI2C_2PinOpenDrain

LPI2C Configured for 2-pin open drain mode

enumerator kLPI2C_2PinOutputOnly

LPI2C Configured for 2-pin output only mode (ultra-fast mode)

enumerator kLPI2C_2PinPushPull

LPI2C Configured for 2-pin push-pull mode

enumerator kLPI2C_4PinPushPull

LPI2C Configured for 4-pin push-pull mode

enumerator kLPI2C_2PinOpenDrainWithSeparateSlave

LPI2C Configured for 2-pin open drain mode with separate LPI2C slave

enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave

LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave

enumerator kLPI2C_2PinPushPullWithSeparateSlave

LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave

enumerator kLPI2C_4PinPushPullWithInvertedOutput

LPI2C Configured for 4-pin push-pull mode(inverted outputs)

enum _lpi2c_host_request_source

LPI2C master host request selection.

Values:

enumerator kLPI2C_HostRequestExternalPin

Select the LPI2C_HREQ pin as the host request input

enumerator kLPI2C_HostRequestInputTrigger

Select the input trigger as the host request input

enum _lpi2c_host_request_polarity

LPI2C master host request pin polarity configuration.

Values:

enumerator kLPI2C_HostRequestPinActiveLow

Configure the LPI2C_HREQ pin active low

enumerator kLPI2C_HostRequestPinActiveHigh

Configure the LPI2C_HREQ pin active high

enum _lpi2c_data_match_config_mode

LPI2C master data match configuration modes.

Values:

enumerator kLPI2C_MatchDisabled

LPI2C Match Disabled

enumerator kLPI2C_1stWordEqualsM0OrM1

LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1

enumerator kLPI2C_AnyWordEqualsM0OrM1

LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1

enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1

LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1

enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1

LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1

enumerator kLPI2C_1stWordAndM1EqualsM0AndM1

LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1

enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1

LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1

enum _lpi2c_master_transfer_flags

Transfer option flags.

Note

These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field.

Values:

enumerator kLPI2C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal.

enumerator kLPI2C_TransferNoStartFlag

Don’t send a start condition, address, and sub address

enumerator kLPI2C_TransferRepeatedStartFlag

Send a repeated start condition

enumerator kLPI2C_TransferNoStopFlag

Don’t send a stop condition.

typedef enum _lpi2c_direction lpi2c_direction_t

Direction of master and slave transfers.

typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t

LPI2C pin configuration.

typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t

LPI2C master host request selection.

typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t

LPI2C master host request pin polarity configuration.

typedef struct _lpi2c_master_config lpi2c_master_config_t

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t

LPI2C master data match configuration modes.

typedef struct _lpi2c_match_config lpi2c_data_match_config_t

LPI2C master data match configuration structure.

typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t

LPI2C master descriptor of the transfer.

typedef struct _lpi2c_master_handle lpi2c_master_handle_t

LPI2C master handle of the transfer.

typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)

Master completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Pointer to the LPI2C master driver handle.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)

Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs.

struct _lpi2c_master_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableMaster

Whether to enable master mode.

bool enableDoze

Whether master is enabled in doze mode.

bool debugEnable

Enable transfers to continue when halted in debug mode.

bool ignoreAck

Whether to ignore ACK/NACK.

lpi2c_master_pin_config_t pinConfig

The pin configuration option.

uint32_t baudRate_Hz

Desired baud rate in Hertz.

uint32_t busIdleTimeout_ns

Bus idle timeout in nanoseconds. Set to 0 to disable.

uint32_t pinLowTimeout_ns

Pin low timeout in nanoseconds. Set to 0 to disable.

uint8_t sdaGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable.

uint8_t sclGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable.

struct _lpi2c_master_config hostRequest

Host request options.

struct _lpi2c_match_config

#include <fsl_lpi2c.h>

LPI2C master data match configuration structure.

Public Members

lpi2c_data_match_config_mode_t matchMode

Data match configuration setting.

bool rxDataMatchOnly

When set to true, received data is ignored until a successful match.

uint32_t match0

Match value 0.

uint32_t match1

Match value 1.

struct _lpi2c_master_transfer

#include <fsl_lpi2c.h>

Non-blocking transfer descriptor structure.

This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API.

Public Members

uint32_t flags

Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers.

uint16_t slaveAddress

The 7-bit slave address.

lpi2c_direction_t direction

Either kLPI2C_Read or kLPI2C_Write.

uint32_t subaddress

Sub address. Transferred MSB first.

size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes.

void *data

Pointer to data to transfer.

size_t dataSize

Number of bytes to transfer.

struct _lpi2c_master_handle

#include <fsl_lpi2c.h>

Driver handle for master non-blocking APIs.

Note

The contents of this structure are private and subject to change.

Public Members

uint8_t state

Transfer state machine current state.

uint16_t remainingBytes

Remaining byte count in current state.

uint8_t *buf

Buffer pointer for current state.

uint16_t commandBuffer[6]

LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

struct hostRequest

Public Members

bool enable

Enable host request.

lpi2c_host_request_source_t source

Host request source.

lpi2c_host_request_polarity_t polarity

Host request pin polarity.

LPI2C Master DMA Driver

void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)

Create a new handle for the LPI2C master DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.

For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function.

• txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I2C bus.

The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.

status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

Return values:

• kStatus_Success – A transaction was successfully aborted.

• kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress.

typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t

LPI2C master EDMA handle of the transfer.

typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)

Master DMA completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Handle associated with the completed transfer.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_master_edma_handle

#include <fsl_lpi2c_edma.h>

Driver handle for master DMA APIs.

Note

The contents of this structure are private and subject to change.

Public Members

LPI2C_Type *base

LPI2C base pointer.

bool isBusy

Transfer state machine current state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint16_t commandBuffer[10]

LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_edma_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

edma_handle_t *rx

Handle for receive DMA channel.

edma_handle_t *tx

Handle for transmit DMA channel.

edma_tcd_t tcds[3]

Software TCD. Three are allocated to provide enough room to align to 32-bytes.

LPI2C Slave Driver

void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)

Provides a default configuration for the LPI2C slave peripheral.

This function provides the following default configuration for the LPI2C slave peripheral:

slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;

After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

• slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t.

void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C slave peripheral.

This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

• base – The LPI2C peripheral base address.

• slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time.

void LPI2C_SlaveDeinit(LPI2C_Type *base)

Deinitializes the LPI2C slave peripheral.

This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveReset(LPI2C_Type *base)

Performs a software reset of the LPI2C slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as slave.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as slave.

static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C slave status flags.

A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_slave_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C status flag state.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_slave_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags().

static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C slave interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)

Enables or disables the LPI2C slave peripheral DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request.

• enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable.

• enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable.

static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the slave mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master.

Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

• ackOrNack – Pass true for an ACK or false for a NAK.

static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)

Enables or disables ACKSTALL.

When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – True will enable ACKSTALL,false will disable ACKSTALL.

static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)

Returns the slave address sent by the I2C master.

This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits.

status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)

Performs a polling send transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

• actualTxSize – [out]

Returns:

Error or success status returned by API.

status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

• actualRxSize – [out]

Returns:

Error or success status returned by API.

void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C slave non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C slave driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers.

Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

• eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.

Return values:

• kStatus_Success – Slave transfers were successfully started.

• kStatus_LPI2C_Busy – Slave transfers have already been started on this handle.

status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to i2c_slave_handle_t structure.

• count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress –

void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Aborts the slave non-blocking transfers.

Note

This API could be called at any time to stop slave for handling the bus events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

enum _lpi2c_slave_flags

LPI2C slave peripheral flags.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_SlaveTxReadyFlag

Transmit data flag

enumerator kLPI2C_SlaveRxReadyFlag

Receive data flag

enumerator kLPI2C_SlaveAddressValidFlag

Address valid flag

enumerator kLPI2C_SlaveTransmitAckFlag

Transmit ACK flag

enumerator kLPI2C_SlaveRepeatedStartDetectFlag

Repeated start detect flag

enumerator kLPI2C_SlaveStopDetectFlag

Stop detect flag

enumerator kLPI2C_SlaveBitErrFlag

Bit error flag

enumerator kLPI2C_SlaveFifoErrFlag

FIFO error flag

enumerator kLPI2C_SlaveAddressMatch0Flag

Address match 0 flag

enumerator kLPI2C_SlaveAddressMatch1Flag

Address match 1 flag

enumerator kLPI2C_SlaveGeneralCallFlag

General call flag

enumerator kLPI2C_SlaveBusyFlag

Master busy flag

enumerator kLPI2C_SlaveBusBusyFlag

Bus busy flag

enumerator kLPI2C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_SlaveIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_SlaveErrorFlags

Errors to check for.

enum _lpi2c_slave_address_match

LPI2C slave address match options.

Values:

enumerator kLPI2C_MatchAddress0

Match only address 0.

enumerator kLPI2C_MatchAddress0OrAddress1

Match either address 0 or address 1.

enumerator kLPI2C_MatchAddress0ThroughAddress1

Match a range of slave addresses from address 0 through address 1.

enum _lpi2c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kLPI2C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start.

enumerator kLPI2C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role).

enumerator kLPI2C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kLPI2C_SlaveTransmitAckEvent

Callback needs to either transmit an ACK or NACK.

enumerator kLPI2C_SlaveRepeatedStartEvent

A repeated start was detected.

enumerator kLPI2C_SlaveCompletionEvent

A stop was detected, completing the transfer.

enumerator kLPI2C_SlaveAllEvents

Bit mask of all available events.

typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t

LPI2C slave address match options.

typedef struct _lpi2c_slave_config lpi2c_slave_config_t

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t

LPI2C slave transfer structure.

typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t

LPI2C slave handle structure.

typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type.

This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:

Base address for the LPI2C instance on which the event occurred.

Param transfer:

Pointer to transfer descriptor containing values passed to and/or from the callback.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_slave_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableSlave

Enable slave mode.

uint8_t address0

Slave’s 7-bit address.

uint8_t address1

Alternate slave 7-bit address.

lpi2c_slave_address_match_t addressMatchMode

Address matching options.

bool filterDozeEnable

Enable digital glitch filter in doze mode.

bool filterEnable

Enable digital glitch filter.

bool enableGeneralCall

Enable general call address matching.

struct _lpi2c_slave_config sclStall

SCL stall enable options.

bool ignoreAck

Continue transfers after a NACK is detected.

bool enableReceivedAddressRead

Enable reading the address received address as the first byte of data.

uint32_t sdaGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable.

uint32_t sclGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable.

uint32_t dataValidDelay_ns

Width in nanoseconds of the data valid delay.

uint32_t clockHoldTime_ns

Width in nanoseconds of the clock hold time.

struct _lpi2c_slave_transfer

#include <fsl_lpi2c.h>

LPI2C slave transfer structure.

Public Members

lpi2c_slave_transfer_event_t event

Reason the callback is being invoked.

uint8_t receivedAddress

Matching address send by master.

uint8_t *data

Transfer buffer

size_t dataSize

Transfer size

status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent.

size_t transferredCount

Number of bytes actually transferred since start or last repeated start.

struct _lpi2c_slave_handle

#include <fsl_lpi2c.h>

LPI2C slave handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

lpi2c_slave_transfer_t transfer

LPI2C slave transfer copy.

bool isBusy

Whether transfer is busy.

bool wasTransmit

Whether the last transfer was a transmit.

uint32_t eventMask

Mask of enabled events.

uint32_t transferredCount

Count of bytes transferred.

lpi2c_slave_transfer_callback_t callback

Callback function called at transfer event.

void *userData

Callback parameter passed to callback.

struct sclStall

Public Members

bool enableAck

Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall.

bool enableTx

Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer.

bool enableRx

Enables SCL clock stretching when receive data flag is set during a slave-receive transfer.

bool enableAddress

Enables SCL clock stretching when the address valid flag is asserted.

LPSPI: Low Power Serial Peripheral Interface

LPSPI Peripheral driver

void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the LPSPI master.

Parameters:

• base – LPSPI peripheral address.

• masterConfig – Pointer to structure lpspi_master_config_t.

• srcClock_Hz – Module source input clock in Hertz

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)

Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:

lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

• masterConfig – pointer to lpspi_master_config_t structure

void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)

LPSPI slave configuration.

Parameters:

• base – LPSPI peripheral address.

• slaveConfig – Pointer to a structure lpspi_slave_config_t.

void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)

Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:

lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

• slaveConfig – pointer to lpspi_slave_config_t structure.

void LPSPI_Deinit(LPSPI_Type *base)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.

Parameters:

• base – LPSPI peripheral address.

void LPSPI_Reset(LPSPI_Type *base)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API.

Parameters:

• base – LPSPI peripheral address.

uint32_t LPSPI_GetInstance(LPSPI_Type *base)

Get the LPSPI instance from peripheral base address.

Parameters:

• base – LPSPI peripheral base address.

Returns:

LPSPI instance.

static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)

Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Parameters:

• base – LPSPI peripheral address.

• enable – Pass true to enable module, false to disable module.

static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)

Gets the LPSPI status flag state.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI status(in SR register).

static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)

Gets the LPSPI Tx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Tx FIFO size.

static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)

Gets the LPSPI Rx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Rx FIFO size.

static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)

Gets the LPSPI Tx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the transmit FIFO.

static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)

Gets the LPSPI Rx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the receive FIFO.

static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)

Clears the LPSPI status flag.

This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:

LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);

Parameters:

• base – LPSPI peripheral address.

• statusFlags – The status flag used from type _lpspi_flags.

static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)

static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI interrupts.

This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.

LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI interrupts.

LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Transmit Data Register address for a DMA operation.

This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Transmit Data Register address.

static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Receive Data Register address for a DMA operation.

This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Receive Data Register address.

bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)

Check the argument for transfer .

Parameters:

• base – LPSPI peripheral address.

• transfer – the transfer struct to be used.

• isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer

Returns:

Return true for right and false for wrong.

static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)

Configures the LPSPI for either master or slave.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

• base – LPSPI peripheral address.

• mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t.

static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)

Configures the peripheral chip select used for the transfer.

Parameters:

• base – LPSPI peripheral address.

• select – LPSPI Peripheral Chip Select (PCS) configuration.

static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)

Set the PCS signal to continuous or uncontinuous mode.

Note

In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).

Parameters:

• base – LPSPI peripheral address.

• IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.

static inline bool LPSPI_IsMaster(LPSPI_Type *base)

Returns whether the LPSPI module is in master mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

Returns true if the module is in master mode or false if the module is in slave mode.

static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)

Flushes the LPSPI FIFOs.

Parameters:

• base – LPSPI peripheral address.

• flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.

• flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.

static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)

Sets the transmit and receive FIFO watermark values.

This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

• base – LPSPI peripheral address.

• txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

• rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)

Configures all LPSPI peripheral chip select polarities simultaneously.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.

LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);

Parameters:

• base – LPSPI peripheral address.

• mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity.

static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)

Configures the frame size.

The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.

Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.

Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

• base – LPSPI peripheral address.

• frameSize – The frame size in number of bits.

uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)

Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• baudRate_Bps – The desired baud rate in bits per second.

• srcClock_Hz – Module source input clock in Hertz.

• tcrPrescaleValue – The TCR prescale value needed to program the TCR.

Returns:

The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• scaler – The 8-bit delay value 0x00 to 0xFF (255).

• whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.

uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.

Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).

Parameters:

• base – LPSPI peripheral address.

• delayTimeInNanoSec – The desired delay value in nano-seconds.

• whichDelay – The desired delay to configuration, which must be of type lpspi_delay_type_t.

• srcClock_Hz – Module source input clock in Hertz.

Returns:

actual Calculated delay value in nano-seconds.

static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)

Writes data into the transmit data buffer.

This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

• base – LPSPI peripheral address.

• data – The data word to be sent.

static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)

Reads data from the data buffer.

This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The data read from the data buffer.

void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)

Set up the dummy data.

Parameters:

• base – LPSPI peripheral address.

• dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)

Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_master_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)

LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)

Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)

Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_slave_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)

Wait for tx FIFO to be empty.

This function wait the tx fifo empty

Parameters:

• base – LPSPI peripheral address.

Returns:

true for the tx FIFO is ready, false is not.

FSL_LPSPI_DRIVER_VERSION

LPSPI driver version.

Status for the LPSPI driver.

Values:

enumerator kStatus_LPSPI_Busy

LPSPI transfer is busy.

enumerator kStatus_LPSPI_Error

LPSPI driver error.

enumerator kStatus_LPSPI_Idle

LPSPI is idle.

enumerator kStatus_LPSPI_OutOfRange

LPSPI transfer out Of range.

enumerator kStatus_LPSPI_Timeout

LPSPI timeout polling status flags.

enum _lpspi_flags

LPSPI status flags in SPIx_SR register.

Values:

enumerator kLPSPI_TxDataRequestFlag

Transmit data flag

enumerator kLPSPI_RxDataReadyFlag

Receive data flag

enumerator kLPSPI_WordCompleteFlag

Word Complete flag

enumerator kLPSPI_FrameCompleteFlag

Frame Complete flag

enumerator kLPSPI_TransferCompleteFlag

Transfer Complete flag

enumerator kLPSPI_TransmitErrorFlag

Transmit Error flag (FIFO underrun)

enumerator kLPSPI_ReceiveErrorFlag

Receive Error flag (FIFO overrun)

enumerator kLPSPI_DataMatchFlag

Data Match flag

enumerator kLPSPI_ModuleBusyFlag

Module Busy flag

enumerator kLPSPI_AllStatusFlag

Used for clearing all w1c status flags

enum _lpspi_interrupt_enable

LPSPI interrupt source.

Values:

enumerator kLPSPI_TxInterruptEnable

Transmit data interrupt enable

enumerator kLPSPI_RxInterruptEnable

Receive data interrupt enable

enumerator kLPSPI_WordCompleteInterruptEnable

Word complete interrupt enable

enumerator kLPSPI_FrameCompleteInterruptEnable

Frame complete interrupt enable

enumerator kLPSPI_TransferCompleteInterruptEnable

Transfer complete interrupt enable

enumerator kLPSPI_TransmitErrorInterruptEnable

Transmit error interrupt enable(FIFO underrun)

enumerator kLPSPI_ReceiveErrorInterruptEnable

Receive Error interrupt enable (FIFO overrun)

enumerator kLPSPI_DataMatchInterruptEnable

Data Match interrupt enable

enumerator kLPSPI_AllInterruptEnable

All above interrupts enable.

enum _lpspi_dma_enable

LPSPI DMA source.

Values:

enumerator kLPSPI_TxDmaEnable

Transmit data DMA enable

enumerator kLPSPI_RxDmaEnable

Receive data DMA enable

enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration.

Values:

enumerator kLPSPI_Master

LPSPI peripheral operates in master mode.

enumerator kLPSPI_Slave

LPSPI peripheral operates in slave mode.

enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Values:

enumerator kLPSPI_Pcs0

PCS[0]

enumerator kLPSPI_Pcs1

PCS[1]

enumerator kLPSPI_Pcs2

PCS[2]

enumerator kLPSPI_Pcs3

PCS[3]

enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

Values:

enumerator kLPSPI_PcsActiveHigh

PCS Active High (idles low)

enumerator kLPSPI_PcsActiveLow

PCS Active Low (idles high)

enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity.

Values:

enumerator kLPSPI_Pcs0ActiveLow

Pcs0 Active Low (idles high).

enumerator kLPSPI_Pcs1ActiveLow

Pcs1 Active Low (idles high).

enumerator kLPSPI_Pcs2ActiveLow

Pcs2 Active Low (idles high).

enumerator kLPSPI_Pcs3ActiveLow

Pcs3 Active Low (idles high).

enumerator kLPSPI_PcsAllActiveLow

Pcs0 to Pcs5 Active Low (idles high).

enum _lpspi_clock_polarity

LPSPI clock polarity configuration.

Values:

enumerator kLPSPI_ClockPolarityActiveHigh

CPOL=0. Active-high LPSPI clock (idles low)

enumerator kLPSPI_ClockPolarityActiveLow

CPOL=1. Active-low LPSPI clock (idles high)

enum _lpspi_clock_phase

LPSPI clock phase configuration.

Values:

enumerator kLPSPI_ClockPhaseFirstEdge

CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.

enumerator kLPSPI_ClockPhaseSecondEdge

CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.

enum _lpspi_shift_direction

LPSPI data shifter direction options.

Values:

enumerator kLPSPI_MsbFirst

Data transfers start with most significant bit.

enumerator kLPSPI_LsbFirst

Data transfers start with least significant bit.

enum _lpspi_host_request_select

LPSPI Host Request select configuration.

Values:

enumerator kLPSPI_HostReqExtPin

Host Request is an ext pin.

enumerator kLPSPI_HostReqInternalTrigger

Host Request is an internal trigger.

enum _lpspi_match_config

LPSPI Match configuration options.

Values:

enumerator kLPSI_MatchDisabled

LPSPI Match Disabled.

enumerator kLPSI_1stWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration.

Values:

enumerator kLPSPI_SdiInSdoOut

LPSPI SDI input, SDO output.

enumerator kLPSPI_SdiInSdiOut

LPSPI SDI input, SDI output.

enumerator kLPSPI_SdoInSdoOut

LPSPI SDO input, SDO output.

enumerator kLPSPI_SdoInSdiOut

LPSPI SDO input, SDI output.

enum _lpspi_data_out_config

LPSPI data output configuration.

Values:

enumerator kLpspiDataOutRetained

Data out retains last value when chip select is de-asserted

enumerator kLpspiDataOutTristate

Data out is tristated when chip select is de-asserted

enum _lpspi_transfer_width

LPSPI transfer width configuration.

Values:

enumerator kLPSPI_SingleBitXfer

1-bit shift at a time, data out on SDO, in on SDI (normal mode)

enumerator kLPSPI_TwoBitXfer

2-bits shift out on SDO/SDI and in on SDO/SDI

enumerator kLPSPI_FourBitXfer

4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]

enum _lpspi_delay_type

LPSPI delay type selection.

Values:

enumerator kLPSPI_PcsToSck

PCS-to-SCK delay.

enumerator kLPSPI_LastSckToPcs

Last SCK edge to PCS delay.

enumerator kLPSPI_BetweenTransfer

Delay between transfers.

enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags.

Values:

enumerator kLPSPI_MasterPcs0

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal

enumerator kLPSPI_MasterPcs1

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal

enumerator kLPSPI_MasterPcs2

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal

enumerator kLPSPI_MasterPcs3

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal

enumerator kLPSPI_MasterPcsContinuous

Is PCS signal continuous

enumerator kLPSPI_MasterByteSwap

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags.

Values:

enumerator kLPSPI_SlavePcs0

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal

enumerator kLPSPI_SlavePcs1

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal

enumerator kLPSPI_SlavePcs2

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal

enumerator kLPSPI_SlavePcs3

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal

enumerator kLPSPI_SlaveByteSwap

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine.

Values:

enumerator kLPSPI_Idle

Nothing in the transmitter/receiver.

enumerator kLPSPI_Busy

Transfer queue is not finished.

enumerator kLPSPI_Error

Transfer error.

typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration.

typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration.

typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration.

typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options.

typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration.

typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options.

typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration.

typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration.

typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration.

typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection.

typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure.

typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure.

typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs.

typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs.

typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure.

volatile uint8_t g_lpspiDummyData[]

Global variable for dummy data value setting.

LPSPI_DUMMY_DATA

LPSPI dummy data if no Tx data.

Dummy data used for tx if there is not txData.

SPI_RETRY_TIMES

Retry times for waiting flag.

LPSPI_MASTER_PCS_SHIFT

LPSPI master PCS shift macro , internal used.

LPSPI_MASTER_PCS_MASK

LPSPI master PCS shift macro , internal used.

LPSPI_SLAVE_PCS_SHIFT

LPSPI slave PCS shift macro , internal used.

LPSPI_SLAVE_PCS_MASK

LPSPI slave PCS shift macro , internal used.

struct _lpspi_master_config

#include <fsl_lpspi.h>

LPSPI master configuration structure.

Public Members

uint32_t baudRate

Baud Rate for LPSPI.

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

uint32_t pcsToSckDelayInNanoSec

PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t lastSckToPcsDelayInNanoSec

Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t betweenTransferDelayInNanoSec

After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (PCS).

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

bool enableInputDelay

Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length.

struct _lpspi_slave_config

#include <fsl_lpspi.h>

LPSPI slave configuration structure.

Public Members

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (pcs)

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

struct _lpspi_transfer

#include <fsl_lpspi.h>

LPSPI master/slave transfer structure.

Public Members

const uint8_t *txData

Send buffer.

uint8_t *rxData

Receive buffer.

volatile size_t dataSize

Transfer bytes.

uint32_t configFlags

Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.

struct _lpspi_master_handle

#include <fsl_lpspi.h>

LPSPI master transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool writeTcrInIsr

A flag that whether should write TCR in ISR.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile bool isTxMask

A flag that whether TCR[TXMSK] is set.

volatile uint16_t bytesPerFrame

Number of bytes in each frame

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if the txData is NULL.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

lpspi_master_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

struct _lpspi_slave_handle

#include <fsl_lpspi.h>

LPSPI slave transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

volatile uint32_t errorCount

Error count for slave transfer.

lpspi_slave_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

LPSPI eDMA Driver

FSL_LPSPI_EDMA_DRIVER_VERSION

LPSPI EDMA driver version.

DMA_MAX_TRANSFER_COUNT

DMA max transfer size.

typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t

Forward declaration of the _lpspi_master_edma_handle typedefs.

typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t

Forward declaration of the _lpspi_slave_edma_handle typedefs.

typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI master eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_master_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)

LPSPI master config transfer parameter while using eDMA.

This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

Returns:

Indicates whether LPSPI master transfer was successful or not.

status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA without configs.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure, config field is not uesed.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

• kStatus_InvalidArgument – The transfer structure is invalid.

Returns:

Indicates whether LPSPI master transfer was successful or not.

void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)

LPSPI master aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)

Gets the master eDMA transfer remaining bytes.

This function gets the master eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the EDMA transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI slave eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.

(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_slave_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfers data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)

LPSPI slave aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)

Gets the slave eDMA transfer remaining bytes.

This function gets the slave eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the eDMA transaction.

Returns:

status of status_t.

struct _lpspi_master_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI master eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

edma_tcd_t *lastTimeTCD

Pointer to the lastTime TCD

bool isMultiDMATransmit

Is there multi DMA transmit

volatile uint8_t dmaTransmitTime

DMA Transfer times.

uint32_t lastTimeDataBytes

DMA transmit last Time data Bytes

uint32_t dataBytesEveryTime

Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT

edma_transfer_config_t transferConfigRx

Config of DMA rx channel.

edma_transfer_config_t transferConfigTx

Config of DMA tx channel.

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

uint32_t transmitCommand

Used to write TCR for DMA purpose.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

lpspi_master_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg buff

edma_tcd_t lpspiSoftwareTCD[3]

SoftwareTCD, internal used

struct _lpspi_slave_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI slave eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

volatile uint8_t state

LPSPI transfer state.

uint32_t errorCount

Error count for slave transfer.

lpspi_slave_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg

edma_tcd_t lpspiSoftwareTCD[2]

SoftwareTCD, internal used

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver

LPUART Driver

static inline void LPUART_SoftwareReset(LPUART_Type *base)

Resets the LPUART using software.

This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

• base – LPUART peripheral base address.

status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)

Initializes an LPUART instance with the user configuration structure and the peripheral clock.

This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART.

lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• config – Pointer to a user-defined configuration structure.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source.

• kStatus_Success – LPUART initialize succeed

void LPUART_Deinit(LPUART_Type *base)

Deinitializes a LPUART instance.

This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

• base – LPUART peripheral base address.

void LPUART_GetDefaultConfig(lpuart_config_t *config)

Gets the default configuration structure.

This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

• config – Pointer to a configuration structure.

status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the LPUART instance baudrate.

This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.

LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• baudRate_Bps – LPUART baudrate to be set.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source.

• kStatus_Success – Set baudrate succeeded.

void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)

Enable 9-bit data mode for LPUART.

This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

• base – LPUART peripheral base address.

• enable – true to enable, flase to disable.

static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)

Set the LPUART address.

This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note

Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.

Parameters:

• base – LPUART peripheral base address.

• address1 – LPUART slave address1.

• address2 – LPUART slave address2.

static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)

Enable the LPUART match address feature.

Parameters:

• base – LPUART peripheral base address.

• match1 – true to enable match address1, false to disable.

• match2 – true to enable match address2, false to disable.

static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the rx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Rx FIFO watermark.

static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the tx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Tx FIFO watermark.

static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.

This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

• handle – LPUART handle pointer.

• enable – true to enable, false to disable.

uint32_t LPUART_GetStatusFlags(LPUART_Type *base)

Gets LPUART status flags.

This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty:

if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART status flags which are ORed by the enumerators in the _lpuart_flags.

status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)

Clears status flags with a provided mask.

This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

• base – LPUART peripheral base address.

• mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask.

Return values:

• kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware.

• kStatus_Success – Status in the mask are cleared.

Returns:

0 succeed, others failed.

void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)

Enables LPUART interrupts according to a provided mask.

This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt:

LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable.

void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)

Disables LPUART interrupts according to a provided mask.

This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt:

LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable.

uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)

Gets enabled LPUART interrupts.

This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable.

static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)

Gets the LPUART data register address.

This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART data register addresses which are used both by the transmitter and receiver.

static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter DMA request.

This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver DMA.

This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

uint32_t LPUART_GetInstance(LPUART_Type *base)

Get the LPUART instance from peripheral base address.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART instance.

static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter.

This function enables or disables the LPUART transmitter.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver.

This function enables or disables the LPUART receiver.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)

Writes to the transmitter register.

This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

• base – LPUART peripheral base address.

• data – Data write to the TX register.

static inline uint8_t LPUART_ReadByte(LPUART_Type *base)

Reads the receiver register.

This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

• base – LPUART peripheral base address.

Returns:

Data read from data register.

static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)

Gets the rx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

rx FIFO data count.

static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)

Gets the tx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

tx FIFO data count.

void LPUART_SendAddress(LPUART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode.

Parameters:

• base – LPUART peripheral base address.

• address – LPUART slave address.

status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)

Writes to the transmitter register using a blocking method.

This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)

Writes to the transmitter register using a blocking method in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)

Reads the receiver data register using a blocking method.

This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)

Reads the receiver data register in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data by 16bit, only 10bit is valid.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)

Initializes the LPUART handle.

This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.

The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• callback – Callback function.

• userData – User data.

status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note

The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note

When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.

• ringBufferSize – size of the ring buffer.

void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)

Get the length of received data in RX ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

Returns:

Length of received data in RX ring buffer.

void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been sent out to bus.

This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see uart_transfer_t.

• receivedBytes – Bytes received from the ring buffer directly.

Return values:

• kStatus_Success – Successfully queue the transfer into the transmit queue.

• kStatus_LPUART_RxBusy – Previous receive request is not finished.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data receiving.

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received.

This function gets the number of bytes that have been received.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)

LPUART IRQ handle function.

This function handles the LPUART transmit and receive IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)

LPUART Error IRQ handle function.

This function handles the LPUART error IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

FSL_LPUART_DRIVER_VERSION

LPUART driver version.

Error codes for the LPUART driver.

Values:

enumerator kStatus_LPUART_TxBusy

TX busy

enumerator kStatus_LPUART_RxBusy

RX busy

enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle.

enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle.

enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large

enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large

enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear

enumerator kStatus_LPUART_Error

Error happens on LPUART.

enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun.

enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun.

enumerator kStatus_LPUART_NoiseError

LPUART noise error.

enumerator kStatus_LPUART_FramingError

LPUART framing error.

enumerator kStatus_LPUART_ParityError

LPUART parity error.

enumerator kStatus_LPUART_BaudrateNotSupport

Baudrate is not support in current clock source

enumerator kStatus_LPUART_IdleLineDetected

IDLE flag.

enumerator kStatus_LPUART_Timeout

LPUART times out.

enum _lpuart_parity_mode

LPUART parity mode.

Values:

enumerator kLPUART_ParityDisabled

Parity disabled

enumerator kLPUART_ParityEven

Parity enabled, type even, bit setting: PE|PT = 10

enumerator kLPUART_ParityOdd

Parity enabled, type odd, bit setting: PE|PT = 11

enum _lpuart_data_bits

LPUART data bits count.

Values:

enumerator kLPUART_EightDataBits

Eight data bit

enumerator kLPUART_SevenDataBits

Seven data bit

enum _lpuart_stop_bit_count

LPUART stop bit count.

Values:

enumerator kLPUART_OneStopBit

One stop bit

enumerator kLPUART_TwoStopBit

Two stop bits

enum _lpuart_transmit_cts_source

LPUART transmit CTS source.

Values:

enumerator kLPUART_CtsSourcePin

CTS resource is the LPUART_CTS pin.

enumerator kLPUART_CtsSourceMatchResult

CTS resource is the match result.

enum _lpuart_transmit_cts_config

LPUART transmit CTS configure.

Values:

enumerator kLPUART_CtsSampleAtStart

CTS input is sampled at the start of each character.

enumerator kLPUART_CtsSampleAtIdle

CTS input is sampled when the transmitter is idle

enum _lpuart_idle_type_select

LPUART idle flag type defines when the receiver starts counting.

Values:

enumerator kLPUART_IdleTypeStartBit

Start counting after a valid start bit.

enumerator kLPUART_IdleTypeStopBit

Start counting after a stop bit.

enum _lpuart_idle_config

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

Values:

enumerator kLPUART_IdleCharacter1

the number of idle characters.

enumerator kLPUART_IdleCharacter2

the number of idle characters.

enumerator kLPUART_IdleCharacter4

the number of idle characters.

enumerator kLPUART_IdleCharacter8

the number of idle characters.

enumerator kLPUART_IdleCharacter16

the number of idle characters.

enumerator kLPUART_IdleCharacter32

the number of idle characters.

enumerator kLPUART_IdleCharacter64

the number of idle characters.

enumerator kLPUART_IdleCharacter128

the number of idle characters.

enum _lpuart_interrupt_enable

LPUART interrupt configuration structure, default settings all disabled.

This structure contains the settings for all LPUART interrupt configurations.

Values:

enumerator kLPUART_LinBreakInterruptEnable

LIN break detect. bit 7

enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge. bit 6

enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty. bit 23

enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete. bit 22

enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full. bit 21

enumerator kLPUART_IdleLineInterruptEnable

Idle line. bit 20

enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun. bit 27

enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag. bit 26

enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag. bit 25

enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag. bit 24

enumerator kLPUART_Match1InterruptEnable

Parity error flag. bit 15

enumerator kLPUART_Match2InterruptEnable

Parity error flag. bit 14

enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow. bit 9

enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow. bit 8

enumerator kLPUART_AllInterruptEnable

enum _lpuart_flags

LPUART status flags.

This provides constants for the LPUART status flags for use in the LPUART functions.

Values:

enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty. bit 23

enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete. bit 22

enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full. bit 21

enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected. bit 20

enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register. bit 19

enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18

enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17

enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection. bit 16

enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31

enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected. bit 30

enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start. bit 24

enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1. bit 15

enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2. bit 14

enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty. bit 7

enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty. bit 6

enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred. bit 1

enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred. bit 0

enumerator kLPUART_AllClearFlags

enumerator kLPUART_AllFlags

typedef enum _lpuart_parity_mode lpuart_parity_mode_t

LPUART parity mode.

typedef enum _lpuart_data_bits lpuart_data_bits_t

LPUART data bits count.

typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t

LPUART stop bit count.

typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t

LPUART transmit CTS source.

typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t

LPUART transmit CTS configure.

typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t

LPUART idle flag type defines when the receiver starts counting.

typedef enum _lpuart_idle_config lpuart_idle_config_t

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

typedef struct _lpuart_config lpuart_config_t

LPUART configuration structure.

typedef struct _lpuart_transfer lpuart_transfer_t

LPUART transfer structure.

typedef struct _lpuart_handle lpuart_handle_t

typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)

void *s_lpuartHandle[]

const IRQn_Type s_lpuartTxIRQ[]

lpuart_isr_t s_lpuartIsr[]

UART_RETRY_TIMES

Retry times for waiting flag.

struct _lpuart_config

#include <fsl_lpuart.h>

LPUART configuration structure.

Public Members

uint32_t baudRate_Bps

LPUART baud rate

lpuart_parity_mode_t parityMode

Parity mode, disabled (default), even, odd

lpuart_data_bits_t dataBitsCount

Data bits count, eight (default), seven

bool isMsb

Data bits order, LSB (default), MSB

lpuart_stop_bit_count_t stopBitCount

Number of stop bits, 1 stop bit (default) or 2 stop bits

uint8_t txFifoWatermark

TX FIFO watermark

uint8_t rxFifoWatermark

RX FIFO watermark

bool enableRxRTS

RX RTS enable

bool enableTxCTS

TX CTS enable

lpuart_transmit_cts_source_t txCtsSource

TX CTS source

lpuart_transmit_cts_config_t txCtsConfig

TX CTS configure

lpuart_idle_type_select_t rxIdleType

RX IDLE type.

lpuart_idle_config_t rxIdleConfig

RX IDLE configuration.

bool enableTx

Enable TX

bool enableRx

Enable RX

struct _lpuart_transfer

#include <fsl_lpuart.h>

LPUART transfer structure.

Public Members

size_t dataSize

The byte count to be transfer.

struct _lpuart_handle

#include <fsl_lpuart.h>

LPUART handle structure.

Public Members

volatile size_t txDataSize

Size of the remaining data to send.

size_t txDataSizeAll

Size of the data to send out.

volatile size_t rxDataSize

Size of the remaining data to receive.

size_t rxDataSizeAll

Size of the data to receive.

size_t rxRingBufferSize

Size of the ring buffer.

volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer.

lpuart_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state.

bool isSevenDataBits

Seven data bits flag.

bool is16bitData

16bit data bits flag, only used for 9bit or 10bit data

union __unnamed82__

Public Members

uint8_t *data

The buffer of data to be transfer.

uint8_t *rxData

The buffer to receive data.

uint16_t *rxData16

The buffer to receive data.

const uint8_t *txData

The buffer of data to be sent.

const uint16_t *txData16

The buffer of data to be sent.

union __unnamed84__

Public Members

const uint8_t *volatile txData

Address of remaining data to send.

const uint16_t *volatile txData16

Address of remaining data to send.

union __unnamed86__

Public Members

uint8_t *volatile rxData

Address of remaining data to receive.

uint16_t *volatile rxData16

Address of remaining data to receive.

union __unnamed88__

Public Members

uint8_t *rxRingBuffer

Start address of the receiver ring buffer.

uint16_t *rxRingBuffer16

Start address of the receiver ring buffer.

LPUART eDMA Driver

void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the LPUART handle which is used in transactional functions.

Note

This function disables all LPUART interrupts.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• callback – Callback function.

• userData – User data.

• txEdmaHandle – User requested DMA handle for TX DMA transfer.

• rxEdmaHandle – User requested DMA handle for RX DMA transfer.

status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART eDMA transfer structure. See lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_LPUART_TxBusy – Previous transfer on going.

• kStatus_InvalidArgument – Invalid argument.

status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• xfer – LPUART eDMA transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others fail.

• kStatus_LPUART_RxBusy – Previous transfer ongoing.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the sent data using eDMA.

This function aborts the sent data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the received data using eDMA.

This function aborts the received data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the LPUART TX register.

This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of received bytes.

This function gets the number of received bytes.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)

LPUART eDMA IRQ handle function.

This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application.

Note

This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.

Parameters:

• base – LPUART peripheral base address.

• lpuartEdmaHandle – LPUART handle pointer.

FSL_LPUART_EDMA_DRIVER_VERSION

LPUART EDMA driver version.

typedef struct _lpuart_edma_handle lpuart_edma_handle_t

typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

struct _lpuart_edma_handle

#include <fsl_lpuart_edma.h>

LPUART eDMA handle.

Public Members

lpuart_edma_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

size_t rxDataSizeAll

Size of the data to receive.

size_t txDataSizeAll

Size of the data to send out.

edma_handle_t *txEdmaHandle

The eDMA TX channel used.

edma_handle_t *rxEdmaHandle

The eDMA RX channel used.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

MCM: Miscellaneous Control Module

FSL_MCM_DRIVER_VERSION

MCM driver version.

Enum _mcm_interrupt_flag. Interrupt status flag mask. .

Values:

enumerator kMCM_CacheWriteBuffer

Cache Write Buffer Error Enable.

enumerator kMCM_ParityError

Cache Parity Error Enable.

enumerator kMCM_FPUInvalidOperation

FPU Invalid Operation Interrupt Enable.

enumerator kMCM_FPUDivideByZero

FPU Divide-by-zero Interrupt Enable.

enumerator kMCM_FPUOverflow

FPU Overflow Interrupt Enable.

enumerator kMCM_FPUUnderflow

FPU Underflow Interrupt Enable.

enumerator kMCM_FPUInexact

FPU Inexact Interrupt Enable.

enumerator kMCM_FPUInputDenormalInterrupt

FPU Input Denormal Interrupt Enable.

typedef union _mcm_buffer_fault_attribute mcm_buffer_fault_attribute_t

The union of buffer fault attribute.

typedef union _mcm_lmem_fault_attribute mcm_lmem_fault_attribute_t

The union of LMEM fault attribute.

static inline void MCM_EnableCrossbarRoundRobin(MCM_Type *base, bool enable)

Enables/Disables crossbar round robin.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable crossbar round robin.

  • true Enable crossbar round robin.

  • false disable crossbar round robin.

static inline void MCM_EnableInterruptStatus(MCM_Type *base, uint32_t mask)

Enables the interrupt.

Parameters:

• base – MCM peripheral base address.

• mask – Interrupt status flags mask(_mcm_interrupt_flag).

static inline void MCM_DisableInterruptStatus(MCM_Type *base, uint32_t mask)

Disables the interrupt.

Parameters:

• base – MCM peripheral base address.

• mask – Interrupt status flags mask(_mcm_interrupt_flag).

static inline uint16_t MCM_GetInterruptStatus(MCM_Type *base)

Gets the Interrupt status .

Parameters:

• base – MCM peripheral base address.

static inline void MCM_ClearCacheWriteBufferErroStatus(MCM_Type *base)

Clears the Interrupt status .

Parameters:

• base – MCM peripheral base address.

static inline uint32_t MCM_GetBufferFaultAddress(MCM_Type *base)

Gets buffer fault address.

Parameters:

• base – MCM peripheral base address.

static inline void MCM_GetBufferFaultAttribute(MCM_Type *base, mcm_buffer_fault_attribute_t *bufferfault)

Gets buffer fault attributes.

Parameters:

• base – MCM peripheral base address.

static inline uint32_t MCM_GetBufferFaultData(MCM_Type *base)

Gets buffer fault data.

Parameters:

• base – MCM peripheral base address.

static inline void MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type *base, bool enable)

Limit code cache peripheral write buffering.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable limit code cache peripheral write buffering.

  • true Enable limit code cache peripheral write buffering.

  • false disable limit code cache peripheral write buffering.

static inline void MCM_BypassFixedCodeCacheMap(MCM_Type *base, bool enable)

Bypass fixed code cache map.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable bypass fixed code cache map.

  • true Enable bypass fixed code cache map.

  • false disable bypass fixed code cache map.

static inline void MCM_EnableCodeBusCache(MCM_Type *base, bool enable)

Enables/Disables code bus cache.

Parameters:

• base – MCM peripheral base address.

• enable – Used to disable/enable code bus cache.

  • true Enable code bus cache.

  • false disable code bus cache.

static inline void MCM_ForceCodeCacheToNoAllocation(MCM_Type *base, bool enable)

Force code cache to no allocation.

Parameters:

• base – MCM peripheral base address.

• enable – Used to force code cache to allocation or no allocation.

  • true Force code cache to no allocation.

  • false Force code cache to allocation.

static inline void MCM_EnableCodeCacheWriteBuffer(MCM_Type *base, bool enable)

Enables/Disables code cache write buffer.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable code cache write buffer.

  • true Enable code cache write buffer.

  • false Disable code cache write buffer.

static inline void MCM_ClearCodeBusCache(MCM_Type *base)

Clear code bus cache.

Parameters:

• base – MCM peripheral base address.

static inline void MCM_EnablePcParityFaultReport(MCM_Type *base, bool enable)

Enables/Disables PC Parity Fault Report.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable PC Parity Fault Report.

  • true Enable PC Parity Fault Report.

  • false disable PC Parity Fault Report.

static inline void MCM_EnablePcParity(MCM_Type *base, bool enable)

Enables/Disables PC Parity.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable PC Parity.

  • true Enable PC Parity.

  • false disable PC Parity.

static inline void MCM_LockConfigState(MCM_Type *base)

Lock the configuration state.

Parameters:

• base – MCM peripheral base address.

static inline void MCM_EnableCacheParityReporting(MCM_Type *base, bool enable)

Enables/Disables cache parity reporting.

Parameters:

• base – MCM peripheral base address.

• enable – Used to enable/disable cache parity reporting.

  • true Enable cache parity reporting.

  • false disable cache parity reporting.

static inline uint32_t MCM_GetLmemFaultAddress(MCM_Type *base)

Gets LMEM fault address.

Parameters:

• base – MCM peripheral base address.

static inline void MCM_GetLmemFaultAttribute(MCM_Type *base, mcm_lmem_fault_attribute_t *lmemFault)

Get LMEM fault attributes.

Parameters:

• base – MCM peripheral base address.

static inline uint64_t MCM_GetLmemFaultData(MCM_Type *base)

Gets LMEM fault data.

Parameters:

• base – MCM peripheral base address.

MCM_LMFATR_TYPE_MASK

MCM_LMFATR_MODE_MASK

MCM_LMFATR_BUFF_MASK

MCM_LMFATR_CACH_MASK

MCM_ISCR_STAT_MASK

MCM_ISCR_CPEE_MASK

FSL_COMPONENT_ID

union _mcm_buffer_fault_attribute

#include <fsl_mcm.h>

The union of buffer fault attribute.

Public Members

uint32_t attribute

Indicates the faulting attributes, when a properly-enabled cache write buffer error interrupt event is detected.

struct _mcm_buffer_fault_attribute._mcm_buffer_fault_attribut attribute_memory

struct _mcm_buffer_fault_attribut

#include <fsl_mcm.h>

Public Members

uint32_t busErrorDataAccessType

Indicates the type of cache write buffer access.

uint32_t busErrorPrivilegeLevel

Indicates the privilege level of the cache write buffer access.

uint32_t busErrorSize

Indicates the size of the cache write buffer access.

uint32_t busErrorAccess

Indicates the type of system bus access.

uint32_t busErrorMasterID

Indicates the crossbar switch bus master number of the captured cache write buffer bus error.

uint32_t busErrorOverrun

Indicates if another cache write buffer bus error is detected.

union _mcm_lmem_fault_attribute

#include <fsl_mcm.h>

The union of LMEM fault attribute.

Public Members

uint32_t attribute

Indicates the attributes of the LMEM fault detected.

struct _mcm_lmem_fault_attribute._mcm_lmem_fault_attribut attribute_memory

struct _mcm_lmem_fault_attribut

#include <fsl_mcm.h>

Public Members

uint32_t parityFaultProtectionSignal

Indicates the features of parity fault protection signal.

uint32_t parityFaultMasterSize

Indicates the parity fault master size.

uint32_t parityFaultWrite

Indicates the parity fault is caused by read or write.

uint32_t backdoorAccess

Indicates the LMEM access fault is initiated by core access or backdoor access.

uint32_t parityFaultSyndrome

Indicates the parity fault syndrome.

uint32_t overrun

Indicates the number of faultss.

MECC: internal error correction code

void MECC_Init(MECC_Type *base, mecc_config_t *config)

MECC module initialization function.

Parameters:

• base – MECC base address.

• config – pointer to the MECC configuration structure.

void MECC_Deinit(MECC_Type *base)

Deinitializes the MECC.

Parameters:

• base – MECC base address.

void MECC_GetDefaultConfig(mecc_config_t *config)

Sets the MECC configuration structure to default values.

Parameters:

• config – pointer to the MECC configuration structure.

static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)

Gets MECC status flags.

Parameters:

• base – MECC peripheral base address.

Returns:

MECC status flags.

static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)

MECC module clear interrupt status.

Parameters:

• base – MECC base address.

• mask – status to clear.

static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)

MECC module enable interrupt status.

Parameters:

• base – MECC base address.

• mask – status to enable.

static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)

MECC module disable interrupt status.

Parameters:

• base – MECC base address.

• mask – status to disable.

static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)

MECC module enable interrupt.

Parameters:

• base – MECC base address.

• mask – The interrupts to enable.

static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)

MECC module disable interrupt.

Parameters:

• base – MECC base address.

• mask – The interrupts to disable.

status_t MECC_ErrorInjection(MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)

MECC module error injection.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• lowerrordata – low 32 bits data.

• higherrordata – high 32 bits data.

• eccdata – ecc code.

• banknumber – ocram bank number.

Return values:

kStatus_Success. –

status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber)

MECC module get single error information.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• info – single error information.

• banknumber – ocram bank number.

Return values:

• kStatus_Success. –

• kStatus_MECC_BankMiss. –

status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber)

MECC module get multiple error information.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• info – multiple error information.

• banknumber – ocram bank number.

Return values:

• kStatus_Success. –

• kStatus_MECC_BankMiss. –

static inline uint32_t MECC_GetPendingFlags(MECC_Type *base)

Get pending flags for OCRAM wait and pipeline enable.

Parameters:

• base – MECC base address.

Returns:

Pending flags, should be the OR’ed value of mecc_pending_flag_t.

FSL_MECC_DRIVER_VERSION

Driver version 2.1.0.

Error codes for the MECC driver.

Values:

enumerator kStatus_MECC_BankMiss

Ocram bank miss

MECC interrupt configuration structure, default settings all disabled.

This structure contains the settings for all of the MECC interrupt configurations.

Values:

enumerator kMECC_SingleError0InterruptEnable

Single Bit Error On Ocram Bank0 interrupt enable.

enumerator kMECC_SingleError1InterruptEnable

Single Bit Error On Ocram Bank1 interrupt enable

enumerator kMECC_SingleError2InterruptEnable

Single Bit Error On Ocram Bank2 interrupt enable

enumerator kMECC_SingleError3InterruptEnable

Single Bit Error On Ocram Bank3 interrupt enable

enumerator kMECC_MultiError0InterruptEnable

Multiple Bits Error On Ocram Bank0 interrupt enable

enumerator kMECC_MultiError1InterruptEnable

Multiple Bits Error On Ocram Bank1 interrupt enable

enumerator kMECC_MultiError2InterruptEnable

Multiple Bits Error On Ocram Bank2 interrupt enable

enumerator kMECC_MultiError3InterruptEnable

Multiple Bits Error On Ocram Bank3 interrupt enable

enumerator kMECC_StrobeError0InterruptEnable

AXI Strobe Error On Ocram Bank0 interrupt enable

enumerator kMECC_StrobeError1InterruptEnable

AXI Strobe Error On Ocram Bank1 interrupt enable

enumerator kMECC_StrobeError2InterruptEnable

AXI Strobe Error On Ocram Bank2 interrupt enable

enumerator kMECC_StrobeError3InterruptEnable

AXI Strobe Error On Ocram Bank3 interrupt enable

enumerator kMECC_AccessError0InterruptEnable

Ocram Access Error On Bank0 interrupt enable

enumerator kMECC_AccessError1InterruptEnable

Ocram Access Error On Bank1 interrupt enable

enumerator kMECC_AccessError2InterruptEnable

Ocram Access Error On Bank2 interrupt enable

enumerator kMECC_AccessError3InterruptEnable

Ocram Access Error On Bank3 interrupt enable

enumerator kMECC_AllInterruptsEnable

all interrupts enable

MECC interrupt status configuration structure, default settings all disabled.

This structure contains the settings for all of the MECC interrupt status configurations.

Values:

enumerator kMECC_SingleError0InterruptStatusEnable

Single Bit Error On Ocram Bank0 interrupt status enable.

enumerator kMECC_SingleError1InterruptStatusEnable

Single Bit Error On Ocram Bank1 interrupt status enable

enumerator kMECC_SingleError2InterruptStatusEnable

Single Bit Error On Ocram Bank2 interrupt status enable

enumerator kMECC_SingleError3InterruptStatusEnable

Single Bit Error On Ocram Bank3 interrupt status enable

enumerator kMECC_MultiError0InterruptStatusEnable

Multiple Bits Error On Ocram Bank0 interrupt status enable

enumerator kMECC_MultiError1InterruptStatusEnable

Multiple Bits Error On Ocram Bank1 interrupt status enable

enumerator kMECC_MultiError2InterruptStatusEnable

Multiple Bits Error On Ocram Bank2 interrupt status enable

enumerator kMECC_MultiError3InterruptStatusEnable

Multiple Bits Error On Ocram Bank3 interrupt status enable

enumerator kMECC_StrobeError0InterruptStatusEnable

AXI Strobe Error On Ocram Bank0 interrupt status enable

enumerator kMECC_StrobeError1InterruptStatusEnable

AXI Strobe Error On Ocram Bank1 interrupt status enable

enumerator kMECC_StrobeError2InterruptStatusEnable

AXI Strobe Error On Ocram Bank2 interrupt status enable

enumerator kMECC_StrobeError3InterruptStatusEnable

AXI Strobe Error On Ocram Bank3 interrupt status enable

enumerator kMECC_AccessError0InterruptStatusEnable

Ocram Access Error On Bank0 interrupt status enable

enumerator kMECC_AccessError1InterruptStatusEnable

Ocram Access Error On Bank1 interrupt status enable

enumerator kMECC_AccessError2InterruptStatusEnable

Ocram Access Error On Bank2 interrupt status enable

enumerator kMECC_AccessError3InterruptStatusEnable

Ocram Access Error On Bank3 interrupt status enable

enumerator kMECC_AllInterruptsStatusEnable

all interrupts enable

MECC status flags.

This provides constants for the MECC status flags for use in the MECC functions.

Values:

enumerator kMECC_SingleError0InterruptFlag

Single Bit Error On Ocram Bank0 interrupt flag

enumerator kMECC_SingleError1InterruptFlag

Single Bit Error On Ocram Bank1 interrupt flag

enumerator kMECC_SingleError2InterruptFlag

Single Bit Error On Ocram Bank2 interrupt flag

enumerator kMECC_SingleError3InterruptFlag

Single Bit Error On Ocram Bank3 interrupt flag

enumerator kMECC_MultiError0InterruptFlag

Multiple Bits Error On Ocram Bank0 interrupt flag

enumerator kMECC_MultiError1InterruptFlag

Multiple Bits Error On Ocram Bank1 interrupt flag

enumerator kMECC_MultiError2InterruptFlag

Multiple Bits Error On Ocram Bank2 interrupt flag

enumerator kMECC_MultiError3InterruptFlag

Multiple Bits Error On Ocram Bank3 interrupt flag

enumerator kMECC_StrobeError0InterruptFlag

AXI Strobe Error On Ocram Bank0 interrupt flag

enumerator kMECC_StrobeError1InterruptFlag

AXI Strobe Error On Ocram Bank1 interrupt flag

enumerator kMECC_StrobeError2InterruptFlag

AXI Strobe Error On Ocram Bank2 interrupt flag

enumerator kMECC_StrobeError3InterruptFlag

AXI Strobe Error On Ocram Bank3 interrupt flag

enumerator kMECC_AccessError0InterruptFlag

Ocram Access Error On Bank0 interrupt flag

enumerator kMECC_AccessError1InterruptFlag

Ocram Access Error On Bank1 interrupt flag

enumerator kMECC_AccessError2InterruptFlag

Ocram Access Error On Bank2 interrupt flag

enumerator kMECC_AccessError3InterruptFlag

Ocram Access Error On Bank3 interrupt flag

enumerator kMECC_AllInterruptsFlag

all interrupts interrupt flag

MECC ocram bank number.

Values:

enumerator kMECC_OcramBank0

ocram bank number 0: ocram_base_address+0x20*i

enumerator kMECC_OcramBank1

ocram bank number 1: ocram_base_address+0x20*i+0x8

enumerator kMECC_OcramBank2

ocram bank number 2: ocram_base_address+0x20*i+0x10

enumerator kMECC_OcramBank3

ocram bank number 3: ocram_base_address+0x20*i+0x18

enum _mecc_pending_flag

Pending flags for OCRAM wait and pipeline enable. .

Values:

enumerator kMECC_ReadDataWaitPendingFlag

Indicate an update pending status for read data wait.

enumerator kMECC_ReadAddrPipelinePendingFlag

Indicate an update pending status for read address pipeline.

enumerator kMECC_WriteDataPipelinePendingFlag

Indicate an update pending status for write data pipeline.

enumerator kMECC_WriteAddrPipelinePendingFlag

Indicate an update pending status for write address pipeline.

enumerator kMECC_AllPendingFlags

Indicate all pending status flags.

typedef struct _mecc_config mecc_config_t

MECC user configuration.

Note

Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

typedef struct _mecc_single_error_info mecc_single_error_info_t

MECC ocram single error information, including single error address, ECC code, error data and error bit position.

typedef struct _mecc_multi_error_info mecc_multi_error_info_t

MECC ocram multiple error information, including multiple error address, ECC code, error data.

struct _mecc_config

#include <fsl_mecc.h>

MECC user configuration.

Note

Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

Public Members

bool enableMecc

Enable the MECC function.

uint32_t startAddress

Start address of corresponding OCRAM memory region to enable ECC.

uint32_t endAddress

end address of corresponding OCRAM memory region to enable ECC.

bool enableReadDataWait

uint32_t Ocram1StartAddress; Ocram 1 start address, deprecated since 2.1.0

uint32_t Ocram1EndAddress; Ocram 1 end address, deprecated since 2.1.0

uint32_t Ocram2StartAddress; Ocram 2 start address, deprecated since 2.1.0.

uint32_t Ocram2EndAddress; Ocram 2 end address, deprecated since 2.1.0 If enabled, 1-cycle wait state will be inserted into each read access:

• true Enable read data wait;

• false Disable read data wait.

bool enableReadAddrPipeline

If enabled, the read address will be registered before can be applied to memory cell:

• true Enable Read address pipeline;

• false Disable Read address pipeline.

bool enableWriteDataPipeline

If enabled, the write data will be registered before can be applied to memory cell:

• true Enable write data pipeline;

• false Disable write data pipeline.

bool enableWriteAddrPipeline

If enabled, write address will be registered before can be applied to memory cell:

• true Enable write address pipeline;

• false Disable write address pipeline.

struct _mecc_single_error_info

#include <fsl_mecc.h>

MECC ocram single error information, including single error address, ECC code, error data and error bit position.

Public Members

uint32_t singleErrorAddress

Single error address on Ocram bank n

uint32_t singleErrorDataLow

Single error low 32 bits uncorrected read data on Ocram bank n

uint32_t singleErrorDataHigh

Single error high 32 bits uncorrected read data on Ocram bank n

uint32_t singleErrorPosLow

Single error bit postion of low 32 bits read data on Ocram bank n

uint32_t singleErrorPosHigh

Single error bit postion of high 32 bits read data on Ocram bank n

uint8_t singleErrorEccCode

Single error ECC code on Ocram bank n

struct _mecc_multi_error_info

#include <fsl_mecc.h>

MECC ocram multiple error information, including multiple error address, ECC code, error data.

Public Members

uint32_t multiErrorAddress

Multiple error address on Ocram bank n

uint32_t multiErrorDataLow

Multiple error low 32 bits read data on Ocram bank n

uint32_t multiErrorDataHigh

Multiple error high 32 bits read data on Ocram bank n

uint8_t multiErrorEccCode

Multiple error ECC code on Ocram bank n

MIPI DSI Driver

void DSI_Init(const MIPI_DSI_Type *base, const dsi_config_t *config)

Initializes an MIPI DSI host with the user configuration.

This function initializes the MIPI DSI host with the configuration, it should be called first before other MIPI DSI driver functions.

Parameters:

• base – MIPI DSI host peripheral base address.

• config – Pointer to a user-defined configuration structure.

void DSI_Deinit(const MIPI_DSI_Type *base)

Deinitializes an MIPI DSI host.

This function should be called after all bother MIPI DSI driver functions.

Parameters:

• base – MIPI DSI host peripheral base address.

void DSI_GetDefaultConfig(dsi_config_t *config)

Get the default configuration to initialize the MIPI DSI host.

The default value is:

config->numLanes = 4;
config->enableNonContinuousHsClk = false;
config->enableTxUlps = false;
config->autoInsertEoTp = true;
config->numExtraEoTp = 0;
config->htxTo_ByteClk = 0;
config->lrxHostTo_ByteClk = 0;
config->btaTo_ByteClk = 0;

Parameters:

• config – Pointer to a user-defined configuration structure.

void DSI_SetDpiConfig(const MIPI_DSI_Type *base, const dsi_dpi_config_t *config, uint8_t numLanes, uint32_t dpiPixelClkFreq_Hz, uint32_t dsiHsBitClkFreq_Hz)

Configure the DPI interface core.

This function sets the DPI interface configuration, it should be used in video mode.

Parameters:

• base – MIPI DSI host peripheral base address.

• config – Pointer to the DPI interface configuration.

• numLanes – Lane number, should be same with the setting in dsi_dpi_config_t.

• dpiPixelClkFreq_Hz – The DPI pixel clock frequency in Hz.

• dsiHsBitClkFreq_Hz – The DSI high speed bit clock frequency in Hz. It is the same with DPHY PLL output.

uint32_t DSI_InitDphy(const MIPI_DSI_Type *base, const dsi_dphy_config_t *config, uint32_t refClkFreq_Hz)

Initializes the D-PHY.

This function configures the D-PHY timing and setups the D-PHY PLL based on user configuration. The configuration structure could be got by the function DSI_GetDphyDefaultConfig.

For some platforms there is not dedicated D-PHY PLL, indicated by the macro FSL_FEATURE_MIPI_DSI_NO_DPHY_PLL. For these platforms, the refClkFreq_Hz is useless.

Parameters:

• base – MIPI DSI host peripheral base address.

• config – Pointer to the D-PHY configuration.

• refClkFreq_Hz – The REFCLK frequency in Hz.

Returns:

The actual D-PHY PLL output frequency. If could not configure the PLL to the target frequency, the return value is 0.

void DSI_DeinitDphy(const MIPI_DSI_Type *base)

Deinitializes the D-PHY.

Power down the D-PHY PLL and shut down D-PHY.

Parameters:

• base – MIPI DSI host peripheral base address.

void DSI_GetDphyDefaultConfig(dsi_dphy_config_t *config, uint32_t txHsBitClk_Hz, uint32_t txEscClk_Hz)

Get the default D-PHY configuration.

Gets the default D-PHY configuration, the timing parameters are set according to D-PHY specification. User could use the configuration directly, or change some parameters according to the special device.

Parameters:

• config – Pointer to the D-PHY configuration.

• txHsBitClk_Hz – High speed bit clock in Hz.

• txEscClk_Hz – Esc clock in Hz.

static inline void DSI_EnableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)

Enable the interrupts.

The interrupts to enable are passed in as OR’ed mask value of _dsi_interrupt.

Parameters:

• base – MIPI DSI host peripheral base address.

• intGroup1 – Interrupts to enable in group 1.

• intGroup2 – Interrupts to enable in group 2.

static inline void DSI_DisableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)

Disable the interrupts.

The interrupts to disable are passed in as OR’ed mask value of _dsi_interrupt.

Parameters:

• base – MIPI DSI host peripheral base address.

• intGroup1 – Interrupts to disable in group 1.

• intGroup2 – Interrupts to disable in group 2.

static inline void DSI_GetAndClearInterruptStatus(const MIPI_DSI_Type *base, uint32_t *intGroup1, uint32_t *intGroup2)

Get and clear the interrupt status.

Parameters:

• base – MIPI DSI host peripheral base address.

• intGroup1 – Group 1 interrupt status.

• intGroup2 – Group 2 interrupt status.

void DSI_SetApbPacketControl(const MIPI_DSI_Type *base, uint16_t wordCount, uint8_t virtualChannel, dsi_tx_data_type_t dataType, uint8_t flags)

Configure the APB packet to send.

This function configures the next APB packet transfer. After configuration, the packet transfer could be started with function DSI_SendApbPacket. If the packet is long packet, Use DSI_WriteApbTxPayload to fill the payload before start transfer.

Parameters:

• base – MIPI DSI host peripheral base address.

• wordCount – For long packet, this is the byte count of the payload. For short packet, this is (data1 << 8) | data0.

• virtualChannel – Virtual channel.

• dataType – The packet data type, (DI).

• flags – The transfer control flags, see _dsi_transfer_flags.

void DSI_WriteApbTxPayload(const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize)

Fill the long APB packet payload.

Write the long packet payload to TX FIFO.

Parameters:

• base – MIPI DSI host peripheral base address.

• payload – Pointer to the payload.

• payloadSize – Payload size in byte.

void DSI_WriteApbTxPayloadExt(const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDscCmd, uint8_t dscCmd)

Extended function to fill the payload to TX FIFO.

Write the long packet payload to TX FIFO. This function could be used in two ways

1. Include the DSC command in parameter payload. In this case, the DSC command is the first byte of payload. The parameter sendDscCmd is set to false, the dscCmd is not used. This function is the same as DSI_WriteApbTxPayload when used in this way.

2. The DSC command in not in parameter payload, but specified by parameter dscCmd. In this case, the parameter sendDscCmd is set to true, the dscCmd is the DSC command to send. The payload is sent after dscCmd.

Parameters:

• base – MIPI DSI host peripheral base address.

• payload – Pointer to the payload.

• payloadSize – Payload size in byte.

• sendDscCmd – If set to true, the DSC command is specified by dscCmd, otherwise the DSC command is included in the payload.

• dscCmd – The DSC command to send, only used when sendDscCmd is true.

void DSI_ReadApbRxPayload(const MIPI_DSI_Type *base, uint8_t *payload, uint16_t payloadSize)

Read the long APB packet payload.

Read the long packet payload from RX FIFO. This function reads directly but does not check the RX FIFO status. Upper layer should make sure there are available data.

Parameters:

• base – MIPI DSI host peripheral base address.

• payload – Pointer to the payload.

• payloadSize – Payload size in byte.

static inline void DSI_SendApbPacket(const MIPI_DSI_Type *base)

Trigger the controller to send out APB packet.

Send the packet set by DSI_SetApbPacketControl.

Parameters:

• base – MIPI DSI host peripheral base address.

static inline uint32_t DSI_GetApbStatus(const MIPI_DSI_Type *base)

Get the APB status.

The return value is OR’ed value of _dsi_apb_status.

Parameters:

• base – MIPI DSI host peripheral base address.

Returns:

The APB status.

static inline uint32_t DSI_GetRxErrorStatus(const MIPI_DSI_Type *base)

Get the error status during data transfer.

The return value is OR’ed value of _dsi_rx_error_status.

Parameters:

• base – MIPI DSI host peripheral base address.

Returns:

The error status.

static inline uint8_t DSI_GetEccRxErrorPosition(uint32_t rxErrorStatus)

Get the one-bit RX ECC error position.

When one-bit ECC RX error detected using DSI_GetRxErrorStatus, this function could be used to get the error bit position.

uint8_t eccErrorPos;
uint32_t rxErrorStatus = DSI_GetRxErrorStatus(MIPI_DSI);
if (kDSI_RxErrorEccOneBit & rxErrorStatus)
{
    eccErrorPos = DSI_GetEccRxErrorPosition(rxErrorStatus);
}

Parameters:

• rxErrorStatus – The error status returned by DSI_GetRxErrorStatus.

Returns:

The 1-bit ECC error position.

static inline uint32_t DSI_GetAndClearHostStatus(const MIPI_DSI_Type *base)

Get and clear the DSI host status.

The host status are returned as mask value of _dsi_host_status.

Parameters:

• base – MIPI DSI host peripheral base address.

Returns:

The DSI host status.

static inline uint32_t DSI_GetRxPacketHeader(const MIPI_DSI_Type *base)

Get the RX packet header.

Parameters:

• base – MIPI DSI host peripheral base address.

Returns:

The RX packet header.

static inline dsi_rx_data_type_t DSI_GetRxPacketType(uint32_t rxPktHeader)

Extract the RX packet type from the packet header.

Extract the RX packet type from the packet header get by DSI_GetRxPacketHeader.

Parameters:

• rxPktHeader – The RX packet header get by DSI_GetRxPacketHeader.

Returns:

The RX packet type.

static inline uint16_t DSI_GetRxPacketWordCount(uint32_t rxPktHeader)

Extract the RX packet word count from the packet header.

Extract the RX packet word count from the packet header get by DSI_GetRxPacketHeader.

Parameters:

• rxPktHeader – The RX packet header get by DSI_GetRxPacketHeader.

Returns:

For long packet, return the payload word count (byte). For short packet, return the (data0 << 8) | data1.

static inline uint8_t DSI_GetRxPacketVirtualChannel(uint32_t rxPktHeader)

Extract the RX packet virtual channel from the packet header.

Extract the RX packet virtual channel from the packet header get by DSI_GetRxPacketHeader.

Parameters:

• rxPktHeader – The RX packet header get by DSI_GetRxPacketHeader.

Returns:

The virtual channel.

status_t DSI_TransferBlocking(const MIPI_DSI_Type *base, dsi_transfer_t *xfer)

APB data transfer using blocking method.

Perform APB data transfer using blocking method. This function waits until all data send or received, or timeout happens.

When using this API to read data, the actually read data count could be got from xfer->rxDataSize.

Parameters:

• base – MIPI DSI host peripheral base address.

• xfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data transfer finished with no error.

• kStatus_Timeout – Transfer failed because of timeout.

• kStatus_DSI_RxDataError – RX data error, user could use DSI_GetRxErrorStatus to check the error details.

• kStatus_DSI_ErrorReportReceived – Error Report packet received, user could use DSI_GetAndClearHostStatus to check the error report status.

• kStatus_DSI_NotSupported – Transfer format not supported.

• kStatus_DSI_Fail – Transfer failed for other reasons.

status_t DSI_TransferCreateHandle(const MIPI_DSI_Type *base, dsi_handle_t *handle, dsi_callback_t callback, void *userData)

Create the MIPI DSI handle.

This function initializes the MIPI DSI handle which can be used for other transactional APIs.

Parameters:

• base – MIPI DSI host peripheral base address.

• handle – Handle pointer.

• callback – Callback function.

• userData – User data.

status_t DSI_TransferNonBlocking(const MIPI_DSI_Type *base, dsi_handle_t *handle, dsi_transfer_t *xfer)

APB data transfer using interrupt method.

Perform APB data transfer using interrupt method, when transfer finished, upper layer could be informed through callback function.

When using this API to read data, the actually read data count could be got from handle->xfer->rxDataSize after read finished.

Parameters:

• base – MIPI DSI host peripheral base address.

• handle – pointer to dsi_handle_t structure which stores the transfer state.

• xfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data transfer started successfully.

• kStatus_DSI_Busy – Failed to start transfer because DSI is busy with pervious transfer.

• kStatus_DSI_NotSupported – Transfer format not supported.

void DSI_TransferAbort(const MIPI_DSI_Type *base, dsi_handle_t *handle)

Abort current APB data transfer.

Parameters:

• base – MIPI DSI host peripheral base address.

• handle – pointer to dsi_handle_t structure which stores the transfer state.

void DSI_TransferHandleIRQ(const MIPI_DSI_Type *base, dsi_handle_t *handle)

Interrupt handler for the DSI.

Parameters:

• base – MIPI DSI host peripheral base address.

• handle – pointer to dsi_handle_t structure which stores the transfer state.

FSL_MIPI_DSI_DRIVER_VERSION

Error codes for the MIPI DSI driver.

Values:

enumerator kStatus_DSI_Busy

DSI is busy.

enumerator kStatus_DSI_RxDataError

Read data error.

enumerator kStatus_DSI_ErrorReportReceived

Error report package received.

enumerator kStatus_DSI_NotSupported

The transfer type not supported.

enum _dsi_dpi_color_coding

MIPI DPI interface color coding.

Values:

enumerator kDSI_Dpi16BitConfig1

16-bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB.

enumerator kDSI_Dpi16BitConfig2

16-bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB.

enumerator kDSI_Dpi16BitConfig3

16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX.

enumerator kDSI_Dpi18BitConfig1

18-bit configuration 1. RGB666: XXXXXXRR_RRRRGGGG_GGBBBBBB.

enumerator kDSI_Dpi18BitConfig2

18-bit configuration 2. RGB666: XXRRRRRR_XXGGGGGG_XXBBBBBB.

enumerator kDSI_Dpi24Bit

24-bit.

enum _dsi_dpi_pixel_packet

MIPI DSI pixel packet type send through DPI interface.

Values:

enumerator kDSI_PixelPacket16Bit

16 bit RGB565.

enumerator kDSI_PixelPacket18Bit

18 bit RGB666 packed.

enumerator kDSI_PixelPacket18BitLoosely

18 bit RGB666 loosely packed into three bytes.

enumerator kDSI_PixelPacket24Bit

24 bit RGB888, each pixel uses three bytes.

_dsi_dpi_polarity_flag DPI signal polarity.

Values:

enumerator kDSI_DpiVsyncActiveLow

VSYNC active low.

enumerator kDSI_DpiHsyncActiveLow

HSYNC active low.

enumerator kDSI_DpiVsyncActiveHigh

VSYNC active high.

enumerator kDSI_DpiHsyncActiveHigh

HSYNC active high.

enum _dsi_dpi_video_mode

DPI video mode.

Values:

enumerator kDSI_DpiNonBurstWithSyncPulse

Non-Burst mode with Sync Pulses.

enumerator kDSI_DpiNonBurstWithSyncEvent

Non-Burst mode with Sync Events.

enumerator kDSI_DpiBurst

Burst mode.

enum _dsi_dpi_bllp_mode

Behavior in BLLP (Blanking or Low-Power Interval).

Values:

enumerator kDSI_DpiBllpLowPower

LP mode used in BLLP periods.

enumerator kDSI_DpiBllpBlanking

Blanking packets used in BLLP periods.

enumerator kDSI_DpiBllpNull

Null packets used in BLLP periods.

_dsi_apb_status Status of APB to packet interface.

Values:

enumerator kDSI_ApbNotIdle

State machine not idle

enumerator kDSI_ApbTxDone

Tx packet done

enumerator kDSI_ApbRxControl

DPHY direction 0 - tx had control, 1 - rx has control

enumerator kDSI_ApbTxOverflow

TX fifo overflow

enumerator kDSI_ApbTxUnderflow

TX fifo underflow

enumerator kDSI_ApbRxOverflow

RX fifo overflow

enumerator kDSI_ApbRxUnderflow

RX fifo underflow

enumerator kDSI_ApbRxHeaderReceived

RX packet header has been received

enumerator kDSI_ApbRxPacketReceived

All RX packet payload data has been received

_dsi_rx_error_status Host receive error status.

Values:

enumerator kDSI_RxErrorEccOneBit

ECC single bit error detected.

enumerator kDSI_RxErrorEccMultiBit

ECC multi bit error detected.

enumerator kDSI_RxErrorCrc

CRC error detected.

enumerator kDSI_RxErrorHtxTo

High Speed forward TX timeout detected.

enumerator kDSI_RxErrorLrxTo

Reverse Low power data receive timeout detected.

enumerator kDSI_RxErrorBtaTo

BTA timeout detected.

enum _dsi_host_status

DSI host controller status (status_out)

Values:

enumerator kDSI_HostSoTError

SoT error from peripheral error report.

enumerator kDSI_HostSoTSyncError

SoT Sync error from peripheral error report.

enumerator kDSI_HostEoTSyncError

EoT Sync error from peripheral error report.

enumerator kDSI_HostEscEntryCmdError

Escape Mode Entry Command Error from peripheral error report.

enumerator kDSI_HostLpTxSyncError

Low-power transmit Sync Error from peripheral error report.

enumerator kDSI_HostPeriphToError

Peripheral timeout error from peripheral error report.

enumerator kDSI_HostFalseControlError

False control error from peripheral error report.

enumerator kDSI_HostContentionDetected

Contention detected from peripheral error report.

enumerator kDSI_HostEccErrorOneBit

Single bit ECC error (corrected) from peripheral error report.

enumerator kDSI_HostEccErrorMultiBit

Multi bit ECC error (not corrected) from peripheral error report.

enumerator kDSI_HostChecksumError

Checksum error from peripheral error report.

enumerator kDSI_HostInvalidDataType

DSI data type not recognized.

enumerator kDSI_HostInvalidVcId

DSI VC ID invalid.

enumerator kDSI_HostInvalidTxLength

Invalid transmission length.

enumerator kDSI_HostProtocalViolation

DSI protocal violation.

enumerator kDSI_HostResetTriggerReceived

Reset trigger received.

enumerator kDSI_HostTearTriggerReceived

Tear effect trigger receive.

enumerator kDSI_HostAckTriggerReceived

Acknowledge trigger message received.

_dsi_interrupt DSI interrupt.

Values:

enumerator kDSI_InterruptGroup1ApbNotIdle

State machine not idle

enumerator kDSI_InterruptGroup1ApbTxDone

Tx packet done

enumerator kDSI_InterruptGroup1ApbRxControl

DPHY direction 0 - tx control, 1 - rx control

enumerator kDSI_InterruptGroup1ApbTxOverflow

TX fifo overflow

enumerator kDSI_InterruptGroup1ApbTxUnderflow

TX fifo underflow

enumerator kDSI_InterruptGroup1ApbRxOverflow

RX fifo overflow

enumerator kDSI_InterruptGroup1ApbRxUnderflow

RX fifo underflow

enumerator kDSI_InterruptGroup1ApbRxHeaderReceived

RX packet header has been received

enumerator kDSI_InterruptGroup1ApbRxPacketReceived

All RX packet payload data has been received

enumerator kDSI_InterruptGroup1SoTError

SoT error from peripheral error report.

enumerator kDSI_InterruptGroup1SoTSyncError

SoT Sync error from peripheral error report.

enumerator kDSI_InterruptGroup1EoTSyncError

EoT Sync error from peripheral error report.

enumerator kDSI_InterruptGroup1EscEntryCmdError

Escape Mode Entry Command Error from peripheral error report.

enumerator kDSI_InterruptGroup1LpTxSyncError

Low-power transmit Sync Error from peripheral error report.

enumerator kDSI_InterruptGroup1PeriphToError

Peripheral timeout error from peripheral error report.

enumerator kDSI_InterruptGroup1FalseControlError

False control error from peripheral error report.

enumerator kDSI_InterruptGroup1ContentionDetected

Contention detected from peripheral error report.

enumerator kDSI_InterruptGroup1EccErrorOneBit

Single bit ECC error (corrected) from peripheral error report.

enumerator kDSI_InterruptGroup1EccErrorMultiBit

Multi bit ECC error (not corrected) from peripheral error report.

enumerator kDSI_InterruptGroup1ChecksumError

Checksum error from peripheral error report.

enumerator kDSI_InterruptGroup1InvalidDataType

DSI data type not recognized.

enumerator kDSI_InterruptGroup1InvalidVcId

DSI VC ID invalid.

enumerator kDSI_InterruptGroup1InvalidTxLength

Invalid transmission length.

enumerator kDSI_InterruptGroup1ProtocalViolation

DSI protocal violation.

enumerator kDSI_InterruptGroup1ResetTriggerReceived

Reset trigger received.

enumerator kDSI_InterruptGroup1TearTriggerReceived

Tear effect trigger receive.

enumerator kDSI_InterruptGroup1AckTriggerReceived

Acknowledge trigger message received.

enumerator kDSI_InterruptGroup1HtxTo

High speed TX timeout.

enumerator kDSI_InterruptGroup1LrxTo

Low power RX timeout.

enumerator kDSI_InterruptGroup1BtaTo

Host BTA timeout.

enumerator kDSI_InterruptGroup2EccOneBit

Sinle bit ECC error.

enumerator kDSI_InterruptGroup2EccMultiBit

Multi bit ECC error.

enumerator kDSI_InterruptGroup2CrcError

CRC error.

enum _dsi_tx_data_type

DSI TX data type.

Values:

enumerator kDSI_TxDataVsyncStart

V Sync start.

enumerator kDSI_TxDataVsyncEnd

V Sync end.

enumerator kDSI_TxDataHsyncStart

H Sync start.

enumerator kDSI_TxDataHsyncEnd

H Sync end.

enumerator kDSI_TxDataEoTp

End of transmission packet.

enumerator kDSI_TxDataCmOff

Color mode off.

enumerator kDSI_TxDataCmOn

Color mode on.

enumerator kDSI_TxDataShutDownPeriph

Shut down peripheral.

enumerator kDSI_TxDataTurnOnPeriph

Turn on peripheral.

enumerator kDSI_TxDataGenShortWrNoParam

Generic Short WRITE, no parameters.

enumerator kDSI_TxDataGenShortWrOneParam

Generic Short WRITE, one parameter.

enumerator kDSI_TxDataGenShortWrTwoParam

Generic Short WRITE, two parameter.

enumerator kDSI_TxDataGenShortRdNoParam

Generic Short READ, no parameters.

enumerator kDSI_TxDataGenShortRdOneParam

Generic Short READ, one parameter.

enumerator kDSI_TxDataGenShortRdTwoParam

Generic Short READ, two parameter.

enumerator kDSI_TxDataDcsShortWrNoParam

DCS Short WRITE, no parameters.

enumerator kDSI_TxDataDcsShortWrOneParam

DCS Short WRITE, one parameter.

enumerator kDSI_TxDataDcsShortRdNoParam

DCS Short READ, no parameters.

enumerator kDSI_TxDataSetMaxReturnPktSize

Set the Maximum Return Packet Size.

enumerator kDSI_TxDataNull

Null Packet, no data.

enumerator kDSI_TxDataBlanking

Blanking Packet, no data.

enumerator kDSI_TxDataGenLongWr

Generic long write.

enumerator kDSI_TxDataDcsLongWr

DCS Long Write/write_LUT Command Packet.

enumerator kDSI_TxDataLooselyPackedPixel20BitYCbCr

Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format.

enumerator kDSI_TxDataPackedPixel24BitYCbCr

Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format.

enumerator kDSI_TxDataPackedPixel16BitYCbCr

Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format.

enumerator kDSI_TxDataPackedPixel30BitRGB

Packed Pixel Stream, 30-bit RGB, 10-10-10 Format.

enumerator kDSI_TxDataPackedPixel36BitRGB

Packed Pixel Stream, 36-bit RGB, 12-12-12 Format.

enumerator kDSI_TxDataPackedPixel12BitYCrCb

Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format.

enumerator kDSI_TxDataPackedPixel16BitRGB

Packed Pixel Stream, 16-bit RGB, 5-6-5 Format.

enumerator kDSI_TxDataPackedPixel18BitRGB

Packed Pixel Stream, 18-bit RGB, 6-6-6 Format.

enumerator kDSI_TxDataLooselyPackedPixel18BitRGB

Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format.

enumerator kDSI_TxDataPackedPixel24BitRGB

Packed Pixel Stream, 24-bit RGB, 8-8-8 Format.

enum _dsi_rx_data_type

DSI RX data type.

Values:

enumerator kDSI_RxDataAckAndErrorReport

Acknowledge and Error Report

enumerator kDSI_RxDataEoTp

End of Transmission packet.

enumerator kDSI_RxDataGenShortRdResponseOneByte

Generic Short READ Response, 1 byte returned.

enumerator kDSI_RxDataGenShortRdResponseTwoByte

Generic Short READ Response, 2 byte returned.

enumerator kDSI_RxDataGenLongRdResponse

Generic Long READ Response.

enumerator kDSI_RxDataDcsLongRdResponse

DCS Long READ Response.

enumerator kDSI_RxDataDcsShortRdResponseOneByte

DCS Short READ Response, 1 byte returned.

enumerator kDSI_RxDataDcsShortRdResponseTwoByte

DCS Short READ Response, 2 byte returned.

_dsi_transfer_flags DSI transfer control flags.

Values:

enumerator kDSI_TransferUseHighSpeed

Use high speed mode or not.

enumerator kDSI_TransferPerformBTA

Perform BTA or not.

typedef struct _dsi_config dsi_config_t

MIPI DSI controller configuration.

typedef enum _dsi_dpi_color_coding dsi_dpi_color_coding_t

MIPI DPI interface color coding.

typedef enum _dsi_dpi_pixel_packet dsi_dpi_pixel_packet_t

MIPI DSI pixel packet type send through DPI interface.

typedef enum _dsi_dpi_video_mode dsi_dpi_video_mode_t

DPI video mode.

typedef enum _dsi_dpi_bllp_mode dsi_dpi_bllp_mode_t

Behavior in BLLP (Blanking or Low-Power Interval).

typedef struct _dsi_dpi_config dsi_dpi_config_t

MIPI DSI controller DPI interface configuration.

typedef struct _dsi_dphy_config dsi_dphy_config_t

MIPI DSI D-PHY configuration.

typedef enum _dsi_tx_data_type dsi_tx_data_type_t

DSI TX data type.

typedef enum _dsi_rx_data_type dsi_rx_data_type_t

DSI RX data type.

typedef struct _dsi_transfer dsi_transfer_t

Structure for the data transfer.

typedef struct _dsi_handle dsi_handle_t

MIPI DSI transfer handle.

typedef void (*dsi_callback_t)(const MIPI_DSI_Type *base, dsi_handle_t *handle, status_t status, void *userData)

MIPI DSI callback for finished transfer.

When transfer finished, one of these status values will be passed to the user:

• kStatus_Success Data transfer finished with no error.

• kStatus_Timeout Transfer failed because of timeout.

• kStatus_DSI_RxDataError RX data error, user could use DSI_GetRxErrorStatus to check the error details.

• kStatus_DSI_ErrorReportReceived Error Report packet received, user could use DSI_GetAndClearHostStatus to check the error report status.

• kStatus_Fail Transfer failed for other reasons.

FSL_DSI_TX_MAX_PAYLOAD_BYTE

FSL_DSI_RX_MAX_PAYLOAD_BYTE

struct MIPI_DSI_Type

#include <fsl_mipi_dsi.h>

MIPI DSI structure definition.

Public Members

DSI_HOST_Type *host

Pointer to HOST registers.

DSI_HOST_APB_PKT_IF_Type *apb

Pointer to APB registers.

DSI_HOST_DPI_INTFC_Type *dpi

Pointer to DPI registers.

DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *dphy

Pointer to DPHY registers.

struct _dsi_config

#include <fsl_mipi_dsi.h>

MIPI DSI controller configuration.

Public Members

uint8_t numLanes

Number of lanes.

bool enableNonContinuousHsClk

In enabled, the high speed clock will enter low power mode between transmissions.

bool enableTxUlps

Enable the TX ULPS.

bool autoInsertEoTp

Insert an EoTp short package when switching from HS to LP.

uint8_t numExtraEoTp

How many extra EoTp to send after the end of a packet.

uint32_t htxTo_ByteClk

HS TX timeout count (HTX_TO) in byte clock.

uint32_t lrxHostTo_ByteClk

LP RX host timeout count (LRX-H_TO) in byte clock.

uint32_t btaTo_ByteClk

Bus turn around timeout count (TA_TO) in byte clock.

struct _dsi_dpi_config

#include <fsl_mipi_dsi.h>

MIPI DSI controller DPI interface configuration.

Public Members

uint16_t pixelPayloadSize

Maximum number of pixels that should be sent as one DSI packet. Recommended that the line size (in pixels) is evenly divisible by this parameter.

dsi_dpi_color_coding_t dpiColorCoding

DPI color coding.

dsi_dpi_pixel_packet_t pixelPacket

Pixel packet format.

dsi_dpi_video_mode_t videoMode

Video mode.

dsi_dpi_bllp_mode_t bllpMode

Behavior in BLLP.

uint8_t polarityFlags

OR’ed value of _dsi_dpi_polarity_flag controls signal polarity.

uint16_t hfp

Horizontal front porch, in dpi pixel clock.

uint16_t hbp

Horizontal back porch, in dpi pixel clock.

uint16_t hsw

Horizontal sync width, in dpi pixel clock.

uint8_t vfp

Number of lines in vertical front porch.

uint8_t vbp

Number of lines in vertical back porch.

uint16_t panelHeight

Line number in vertical active area.

uint8_t virtualChannel

Virtual channel.

struct _dsi_dphy_config

#include <fsl_mipi_dsi.h>

MIPI DSI D-PHY configuration.

Public Members

uint32_t txHsBitClk_Hz

The generated HS TX bit clock in Hz.

uint8_t tClkPre_ByteClk

TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE in byte clock. Set how long the controller will wait after enabling clock lane for HS before enabling data lanes for HS.

uint8_t tClkPost_ByteClk

TCLK-POST + T_CLK-TRAIL in byte clock. Set how long the controller will wait before putting clock lane into LP mode after data lanes detected in stop state.

uint8_t tHsExit_ByteClk

THS-EXIT in byte clock. Set how long the controller will wait after the clock lane has been put into LP mode before enabling clock lane for HS again.

uint32_t tWakeup_EscClk

Number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS.

uint8_t tHsPrepare_HalfEscClk

THS-PREPARE in clk_esc/2. Set how long to drive the LP-00 state before HS transmissions, available values are 2, 3, 4, 5.

uint8_t tClkPrepare_HalfEscClk

TCLK-PREPARE in clk_esc/2. Set how long to drive the LP-00 state before HS transmissions, available values are 2, 3.

uint8_t tHsZero_ByteClk

THS-ZERO in clk_byte. Set how long that controller drives data lane HS-0 state before transmit the Sync sequence. Available values are 6, 7, …, 37.

uint8_t tClkZero_ByteClk

TCLK-ZERO in clk_byte. Set how long that controller drives clock lane HS-0 state before transmit the Sync sequence. Available values are 3, 4, …, 66.

uint8_t tHsTrail_ByteClk

THS-TRAIL + 4*UI in clk_byte. Set the time of the flipped differential state after last payload data bit of HS transmission burst. Available values are 0, 1, …, 15.

uint8_t tClkTrail_ByteClk

TCLK-TRAIL + 4*UI in clk_byte. Set the time of the flipped differential state after last payload data bit of HS transmission burst. Available values are 0, 1, …, 15.

struct _dsi_transfer

#include <fsl_mipi_dsi.h>

Structure for the data transfer.

Public Members

uint8_t virtualChannel

Virtual channel.

dsi_tx_data_type_t txDataType

TX data type.

uint8_t flags

Flags to control the transfer, see _dsi_transfer_flags.

const uint8_t *txData

The TX data buffer.

uint8_t *rxData

The TX data buffer.

uint16_t txDataSize

Size of the TX data.

uint16_t rxDataSize

Size of the RX data.

bool sendDscCmd

If set to true, the DSC command is specified by dscCmd, otherwise the DSC command is included in the txData.

uint8_t dscCmd

The DSC command to send, only valid when sendDscCmd is true.

struct _dsi_handle

#include <fsl_mipi_dsi.h>

MIPI DSI transfer handle structure.

Public Members

volatile bool isBusy

MIPI DSI is busy with APB data transfer.

dsi_transfer_t xfer

Transfer information.

dsi_callback_t callback

DSI callback

void *userData

Callback parameter

const MIPI_DSI_Type *dsi

Pointer to MIPI DSI peripheral.

MIPI_DSI: MIPI DSI Host Controller

MU: Messaging Unit

void MU_Init(MU_Type *base)

Initializes the MU module.

This function enables the MU clock only.

Parameters:

• base – MU peripheral base address.

void MU_Deinit(MU_Type *base)

De-initializes the MU module.

This function disables the MU clock only.

Parameters:

• base – MU peripheral base address.

static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register.

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – TX register index, see mu_msg_reg_index_t.

• msg – Message to send.

void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message.

This function waits until the TX register is empty and sends the message.

Parameters:

• base – MU peripheral base address.

• regIndex – MU message register, see mu_msg_reg_index_t.

• msg – Message to send.

static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register.

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message.

This function waits until the RX register is full and receives the message.

Parameters:

• base – MU peripheral base address.

• regIndex – MU message register, see mu_msg_reg_index_t

Returns:

The received message.

static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side.

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

void MU_SetFlags(MU_Type *base, uint32_t flags)

Blocks setting the 3-bit MU flags reflect on the other MU side.

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side.

This function gets the current 3-bit MU flags on the current side.

Parameters:

• base – MU peripheral base address.

Returns:

flags Current value of the 3-bit flags.

static inline uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags.

This function returns the bit mask of the MU status flags. See _mu_status_flags.

uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU status flags, see _mu_status_flags.

static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags.

This function return the RX status flags. Note: RFn bits of SR[27-24](mu status register) are mapped in reverse numerical order: RF0 -> SR[27] RF1 -> SR[26] RF2 -> SR[25] RF3 -> SR[24]

status_reg = MU_GetRxStatusFlags(base);

Parameters:

• base – MU peripheral base address.

Returns:

MU RX status

static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts.

This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU IRQs pending.

static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask)

Clears the specific MU status flags.

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);

Parameters:

• base – MU peripheral base address.

• mask – Bit mask of the MU status flags. See _mu_status_flags. The following flags are cleared by hardware, this function could not clear them.

  • kMU_Tx0EmptyFlag

  • kMU_Tx1EmptyFlag

  • kMU_Tx2EmptyFlag

  • kMU_Tx3EmptyFlag

  • kMU_Rx0FullFlag

  • kMU_Rx1FullFlag

  • kMU_Rx2FullFlag

  • kMU_Rx3FullFlag

  • kMU_EventPendingFlag

  • kMU_FlagsUpdatingFlag

  • kMU_OtherSideInResetFlag

static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask)

Enables the specific MU interrupts.

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

Parameters:

• base – MU peripheral base address.

• mask – Bit mask of the MU interrupts. See _mu_interrupt_enable.

static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask)

Disables the specific MU interrupts.

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

Parameters:

• base – MU peripheral base address.

• mask – Bit mask of the MU interrupts. See _mu_interrupt_enable.

status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask)

Triggers interrupts to the other core.

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

Parameters:

• base – MU peripheral base address.

• mask – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.

Return values:

• kStatus_Success – Interrupts have been triggered successfully.

• kStatus_Fail – Previous interrupts have not been accepted.

static inline void MU_MaskHardwareReset(MU_Type *base, bool mask)

Mask hardware reset by the other core.

The other core could call MU_HardwareResetOtherCore() to reset current core. To mask the reset, call this function and pass in true.

Parameters:

• base – MU peripheral base address.

• mask – Pass true to mask the hardware reset, pass false to unmask it.

FSL_MU_DRIVER_VERSION

MU driver version.

enum _mu_status_flags

MU status flags.

Values:

enumerator kMU_Tx0EmptyFlag

TX0 empty.

enumerator kMU_Tx1EmptyFlag

TX1 empty.

enumerator kMU_Tx2EmptyFlag

TX2 empty.

enumerator kMU_Tx3EmptyFlag

TX3 empty.

enumerator kMU_Rx0FullFlag

RX0 full.

enumerator kMU_Rx1FullFlag

RX1 full.

enumerator kMU_Rx2FullFlag

RX2 full.

enumerator kMU_Rx3FullFlag

RX3 full.

enumerator kMU_GenInt0Flag

General purpose interrupt 0 pending.

enumerator kMU_GenInt1Flag

General purpose interrupt 1 pending.

enumerator kMU_GenInt2Flag

General purpose interrupt 2 pending.

enumerator kMU_GenInt3Flag

General purpose interrupt 3 pending.

enumerator kMU_EventPendingFlag

MU event pending.

enumerator kMU_FlagsUpdatingFlag

MU flags update is on-going.

enumerator kMU_ResetAssertInterruptFlag

The other core reset assert interrupt pending.

enumerator kMU_ResetDeassertInterruptFlag

The other core reset de-assert interrupt pending.

enumerator kMU_OtherSideInResetFlag

The other side is in reset.

enumerator kMU_MuResetInterruptFlag

The other side initializes MU reset.

enumerator kMU_HardwareResetInterruptFlag

Current side has been hardware reset by the other side.

enum _mu_interrupt_enable

MU interrupt source to enable.

Values:

enumerator kMU_Tx0EmptyInterruptEnable

TX0 empty.

enumerator kMU_Tx1EmptyInterruptEnable

TX1 empty.

enumerator kMU_Tx2EmptyInterruptEnable

TX2 empty.

enumerator kMU_Tx3EmptyInterruptEnable

TX3 empty.

enumerator kMU_Rx0FullInterruptEnable

RX0 full.

enumerator kMU_Rx1FullInterruptEnable

RX1 full.

enumerator kMU_Rx2FullInterruptEnable

RX2 full.

enumerator kMU_Rx3FullInterruptEnable

RX3 full.

enumerator kMU_GenInt0InterruptEnable

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptEnable

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptEnable

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptEnable

General purpose interrupt 3.

enumerator kMU_ResetAssertInterruptEnable

The other core reset assert interrupt.

enumerator kMU_ResetDeassertInterruptEnable

The other core reset de-assert interrupt.

enumerator kMU_MuResetInterruptEnable

The other side initializes MU reset. The interrupt is ORed with the general purpose interrupt 3. The general purpose interrupt 3 is issued when the other side set the MU reset and this interrupt is enabled.

enumerator kMU_HardwareResetInterruptEnable

Current side has been hardware reset by the other side.

enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core.

Values:

enumerator kMU_GenInt0InterruptTrigger

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptTrigger

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptTrigger

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptTrigger

General purpose interrupt 3.

enum _mu_msg_reg_index

MU message register.

Values:

enumerator kMU_MsgReg0

enumerator kMU_MsgReg1

enumerator kMU_MsgReg2

enumerator kMU_MsgReg3

typedef enum _mu_msg_reg_index mu_msg_reg_index_t

MU message register.

MU_CR_NMI_MASK

MU_GET_CORE_FLAG(flags)

MU_GET_STAT_FLAG(flags)

MU_GET_TX_FLAG(flags)

MU_GET_RX_FLAG(flags)

MU_GET_GI_FLAG(flags)

Nic301

enum _nic_reg

Values:

enumerator kNIC_REG_READ_QOS_GC355

enumerator kNIC_REG_READ_QOS_PXP

enumerator kNIC_REG_READ_QOS_LCDIF

enumerator kNIC_REG_READ_QOS_LCDIFV2

enumerator kNIC_REG_READ_QOS_CSI

enumerator kNIC_REG_READ_QOS_CAAM

enumerator kNIC_REG_READ_QOS_ENET1G_RX

enumerator kNIC_REG_READ_QOS_ENET1G_TX

enumerator kNIC_REG_READ_QOS_ENET

enumerator kNIC_REG_READ_QOS_USBO2

enumerator kNIC_REG_READ_QOS_USDHC1

enumerator kNIC_REG_READ_QOS_USDHC2

enumerator kNIC_REG_READ_QOS_ENET_QOS

enumerator kNIC_REG_READ_QOS_CM7

enumerator kNIC_REG_READ_QOS_DMA

enumerator kNIC_REG_READ_QOS_IEE

enumerator kNIC_REG_WRITE_QOS_GC355

enumerator kNIC_REG_WRITE_QOS_PXP

enumerator kNIC_REG_WRITE_QOS_LCDIF

enumerator kNIC_REG_WRITE_QOS_LCDIFV2

enumerator kNIC_REG_WRITE_QOS_CSI

enumerator kNIC_REG_WRITE_QOS_CAAM

enumerator kNIC_REG_WRITE_QOS_ENET1G_RX

enumerator kNIC_REG_WRITE_QOS_ENET1G_TX

enumerator kNIC_REG_WRITE_QOS_ENET

enumerator kNIC_REG_WRITE_QOS_USBO2

enumerator kNIC_REG_WRITE_QOS_USDHC1

enumerator kNIC_REG_WRITE_QOS_USDHC2

enumerator kNIC_REG_WRITE_QOS_ENET_QOS

enumerator kNIC_REG_WRITE_QOS_CM7

enumerator kNIC_REG_WRITE_QOS_DMA

enumerator kNIC_REG_WRITE_QOS_IEE

enumerator kNIC_REG_FN_MOD_GC355

enumerator kNIC_REG_FN_MOD_PXP

enumerator kNIC_REG_FN_MOD_LCDIF

enumerator kNIC_REG_FN_MOD_LCDIFV2

enumerator kNIC_REG_FN_MOD_CSI

enumerator kNIC_REG_FN_MOD_CAAM

enumerator kNIC_REG_FN_MOD_ENET1G_RX

enumerator kNIC_REG_FN_MOD_ENET1G_TX

enumerator kNIC_REG_FN_MOD_ENET

enumerator kNIC_REG_FN_MOD_USBO2

enumerator kNIC_REG_FN_MOD_USDHC1

enumerator kNIC_REG_FN_MOD_USDHC2

enumerator kNIC_REG_FN_MOD_ENET_QOS

enumerator kNIC_REG_FN_MOD_CM7

enumerator kNIC_REG_FN_MOD_DMA

enumerator kNIC_REG_FN_MOD_IEE

enumerator kNIC_REG_FN_MOD_AHB_ENET

enumerator kNIC_REG_FN_MOD_AHB_DMA

enumerator kNIC_REG_WR_TIDEMARK_LPSRMIX_M

enum _nic_fn_mod_ahb

Values:

enumerator kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE

enumerator kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE

enumerator kNIC_FN_MOD_AHB_LOCK_OVERRIDE

enum _nic_fn_mod

Values:

enumerator kNIC_FN_MOD_ReadIssue

enumerator kNIC_FN_MOD_WriteIssue

enum _nic_qos

Values:

enumerator kNIC_QOS_0

enumerator kNIC_QOS_1

enumerator kNIC_QOS_2

enumerator kNIC_QOS_3

enumerator kNIC_QOS_4

enumerator kNIC_QOS_5

enumerator kNIC_QOS_6

enumerator kNIC_QOS_7

enumerator kNIC_QOS_8

enumerator kNIC_QOS_9

enumerator kNIC_QOS_10

enumerator kNIC_QOS_11

enumerator kNIC_QOS_12

enumerator kNIC_QOS_13

enumerator kNIC_QOS_14

enumerator kNIC_QOS_15

typedef enum _nic_reg nic_reg_t

typedef enum _nic_fn_mod_ahb nic_fn_mod_ahb_t

typedef enum _nic_fn_mod nic_fn_mod_t

typedef enum _nic_qos nic_qos_t

static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)

Set read_qos Value.

Parameters:

• base – Base address of GPV address

• value – Target value (0 - 15)

static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)

Get read_qos Value.

Parameters:

• base – Base address of GPV address

Returns:

Current value configured

static inline void NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)

Set write_qos Value.

Parameters:

• base – Base address of GPV address

• value – Target value (0 - 15)

static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)

Get write_qos Value.

Parameters:

• base – Base address of GPV address

Returns:

Current value configured

static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t value)

Set fn_mod_ahb Value.

Parameters:

• base – Base address of GPV address

• value – Target value

static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)

Get fn_mod_ahb Value.

Parameters:

• base – Base address of GPV address

Returns:

Current value configured

static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)

Set wr_tidemark Value.

Parameters:

• base – Base address of GPV address

• value – Target value (0 - 15)

static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)

Get wr_tidemark Value.

Parameters:

• base – Base address of GPV address

Returns:

Current value configured

static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)

Set fn_mod Value.

Parameters:

• base – Base address of GPV address

• value – Target value

static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)

Get fn_mod Value.

Parameters:

• base – Base address of GPV address

Returns:

Current value configured

FSL_NIC301_DRIVER_VERSION

NIC301 driver version 2.0.1.

GPV0_BASE

GPV1_BASE

GPV4_BASE

NIC_FN_MOD_AHB_OFFSET

NIC_WR_TIDEMARK_OFFSET

NIC_READ_QOS_OFFSET

NIC_WRITE_QOS_OFFSET

NIC_FN_MOD_OFFSET

NIC_GC355_BASE

NIC_PXP_BASE

NIC_LCDIF_BASE

NIC_LCDIFV2_BASE

NIC_CSI_BASE

NIC_CAAM_BASE

NIC_ENET1G_RX_BASE

NIC_ENET1G_TX_BASE

NIC_ENET_BASE

NIC_USBO2_BASE

NIC_USDHC1_BASE

NIC_USDHC2_BASE

NIC_ENET_QOS_BASE

NIC_CM7_BASE

NIC_LPSRMIX_M_BASE

NIC_DMA_BASE

NIC_IEE_BASE

NIC_QOS_MASK

NIC_WR_TIDEMARK_MASK

NIC_FN_MOD_AHB_MASK

NIC_FN_MOD_MASK

FSL_COMPONENT_ID

OCOTP: On Chip One-Time Programmable controller.

FSL_OCOTP_DRIVER_VERSION

OCOTP driver version.

_ocotp_status Error codes for the OCOTP driver.

Values:

enumerator kStatus_OCOTP_AccessError

eFuse and shadow register access error.

enumerator kStatus_OCOTP_CrcFail

CRC check failed.

enumerator kStatus_OCOTP_ReloadError

Error happens during reload shadow register.

enumerator kStatus_OCOTP_ProgramFail

Fuse programming failed.

enumerator kStatus_OCOTP_Locked

Fuse is locked and cannot be programmed.

typedef struct _ocotp_timing ocotp_timing_t

OCOTP timing structure. Note that, these value are used for calcalating the read/write timings. And the values should statisfy below rules:

Tsp_rd=(WAIT+1)/ipg_clk_freq should be >= 150ns; Tsp_pgm=(RELAX+1)/ipg_clk_freq should be >= 100ns; Trd = ((STROBE_READ+1)- 2*(RELAX_READ+1)) /ipg_clk_freq, The Trd is required to be larger than 40 ns. Tpgm = ((STROBE_PROG+1)- 2*(RELAX_PROG+1)) /ipg_clk_freq; The Tpgm should be configured within the range of 9000 ns < Tpgm < 11000 ns;

void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz)

Initializes OCOTP controller.

Parameters:

• base – OCOTP peripheral base address.

• srcClock_Hz – source clock frequency in unit of Hz. When the macro FSL_FEATURE_OCOTP_HAS_TIMING_CTRL is defined as 0, this parameter is not used, application could pass in 0 in this case.

void OCOTP_Deinit(OCOTP_Type *base)

De-initializes OCOTP controller.

Return values:

kStatus_Success – upon successful execution, error status otherwise.

static inline bool OCOTP_CheckBusyStatus(OCOTP_Type *base)

Checking the BUSY bit in CTRL register. Checking this BUSY bit will help confirm if the OCOTP controller is ready for access.

Parameters:

• base – OCOTP peripheral base address.

Return values:

true – for bit set and false for cleared.

static inline bool OCOTP_CheckErrorStatus(OCOTP_Type *base)

Checking the ERROR bit in CTRL register.

Parameters:

• base – OCOTP peripheral base address.

Return values:

true – for bit set and false for cleared.

static inline void OCOTP_ClearErrorStatus(OCOTP_Type *base)

Clear the error bit if this bit is set.

Parameters:

• base – OCOTP peripheral base address.

status_t OCOTP_ReloadShadowRegister(OCOTP_Type *base)

Reload the shadow register. This function will help reload the shadow register without reseting the OCOTP module. Please make sure the OCOTP has been initialized before calling this API.

Parameters:

• base – OCOTP peripheral base addess.

Return values:

• kStatus_Success – Reload success.

• kStatus_OCOTP_ReloadError – Reload failed.

uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address)

Read the fuse shadow register with the fuse addess.

Deprecated:

Use OCOTP_ReadFuseShadowRegisterExt instead of this function.

Parameters:

• base – OCOTP peripheral base address.

• address – the fuse address to be read from.

Returns:

The read out data.

status_t OCOTP_ReadFuseShadowRegisterExt(OCOTP_Type *base, uint32_t address, uint32_t *data, uint8_t fuseWords)

Read the fuse shadow register from the fuse addess.

This function reads fuse from address, how many words to read is specified by the parameter fuseWords. This function could read at most OCOTP_READ_FUSE_DATA_COUNT fuse word one time.

Parameters:

• base – OCOTP peripheral base address.

• address – the fuse address to be read from.

• data – Data array to save the readout fuse value.

• fuseWords – How many words to read.

Return values:

• kStatus_Success – Read success.

• kStatus_Fail – Error occurs during read.

status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data)

Write the fuse shadow register with the fuse addess and data. Please make sure the wrtie address is not locked while calling this API.

Parameters:

• base – OCOTP peripheral base address.

• address – the fuse address to be written.

• data – the value will be writen to fuse address.

Return values:

write – status, kStatus_Success for success and kStatus_Fail for failed.

status_t OCOTP_WriteFuseShadowRegisterWithLock(OCOTP_Type *base, uint32_t address, uint32_t data, bool lock)

Write the fuse shadow register and lock it.

Please make sure the wrtie address is not locked while calling this API.

Some OCOTP controller supports ECC mode and redundancy mode (see reference mananual for more details). OCOTP controller will auto select ECC or redundancy mode to program the fuse word according to fuse map definition. In ECC mode, the 32 fuse bits in one word can only be written once. In redundancy mode, the word can be written more than once as long as they are different fuse bits. Set parameter lock as true to force use ECC mode.

Parameters:

• base – OCOTP peripheral base address.

• address – The fuse address to be written.

• data – The value will be writen to fuse address.

• lock – Lock or unlock write fuse shadow register operation.

Return values:

• kStatus_Success – Program and reload success.

• kStatus_OCOTP_Locked – The eFuse word is locked and cannot be programmed.

• kStatus_OCOTP_ProgramFail – eFuse word programming failed.

• kStatus_OCOTP_ReloadError – eFuse word programming success, but error happens during reload the values.

• kStatus_OCOTP_AccessError – Cannot access eFuse word.

static inline uint32_t OCOTP_GetVersion(OCOTP_Type *base)

Get the OCOTP controller version from the register.

Parameters:

• base – OCOTP peripheral base address.

Return values:

return – the version value.

OCOTP_READ_FUSE_DATA_COUNT

struct _ocotp_timing

#include <fsl_ocotp.h>

OCOTP timing structure. Note that, these value are used for calcalating the read/write timings. And the values should statisfy below rules:

Tsp_rd=(WAIT+1)/ipg_clk_freq should be >= 150ns; Tsp_pgm=(RELAX+1)/ipg_clk_freq should be >= 100ns; Trd = ((STROBE_READ+1)- 2*(RELAX_READ+1)) /ipg_clk_freq, The Trd is required to be larger than 40 ns. Tpgm = ((STROBE_PROG+1)- 2*(RELAX_PROG+1)) /ipg_clk_freq; The Tpgm should be configured within the range of 9000 ns < Tpgm < 11000 ns;

Public Members

uint32_t wait

Wait time value to fill in the TIMING register.

uint32_t relax

Relax time value to fill in the TIMING register.

uint32_t strobe_prog

Storbe program time value to fill in the TIMING register.

uint32_t strobe_read

Storbe read time value to fill in the TIMING register.

OTFAD: On The Fly AES-128 Decryption Driver

void OTFAD_GetDefaultConfig(otfad_config_t *config)

OTFAD module initialization function.

Parameters:

• config – OTFAD configuration.

AT_QUICKACCESS_SECTION_CODE (void OTFAD_Init(OTFAD_Type *base, const otfad_config_t *config))

OTFAD module initialization function.

Parameters:

• base – OTFAD base address.

• config – OTFAD configuration.

AT_QUICKACCESS_SECTION_CODE (void OTFAD_Deinit(OTFAD_Type *base))

Deinitializes the OTFAD.

static inline uint32_t OTFAD_GetOperateMode(OTFAD_Type *base)

OTFAD module get operate mode.

Parameters:

• base – OTFAD base address.

static inline uint32_t OTFAD_GetStatus(OTFAD_Type *base)

OTFAD module get status.

Parameters:

• base – OTFAD base address.

status_t OTFAD_SetEncryptionConfig(OTFAD_Type *base, const otfad_encryption_config_t *config)

OTFAD module set encryption configuration.

Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region.

Parameters:

• base – OTFAD base address.

• config – encryption configuration.

status_t OTFAD_GetEncryptionConfig(OTFAD_Type *base, otfad_encryption_config_t *config)

OTFAD module get encryption configuration.

Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region.

Parameters:

• base – OTFAD base address.

• config – encryption configuration.

status_t OTFAD_HitDetermination(OTFAD_Type *base, uint32_t address, uint8_t *contextIndex)

OTFAD module do hit determination.

Parameters:

• base – OTFAD base address.

• address – the physical address space assigned to the QuadSPI(FlexSPI) module.

• contextIndex – hitted context region index.

Returns:

status, such as kStatus_Success or kStatus_OTFAD_ResRegAccessMode.

FSL_OTFAD_DRIVER_VERSION

Driver version.

Status codes for the OTFAD driver.

Values:

enumerator kStatus_OTFAD_ResRegAccessMode

Restricted register mode

enumerator kStatus_OTFAD_AddressError

End address less than start address

enumerator kStatus_OTFAD_RegionOverlap

the OTFAD does not support any form of memory region overlap, for system accesses that hit in multiple contexts or no contexts, the fetched data is simply bypassed

enumerator kStatus_OTFAD_RegionMiss

For accesses that hit in a single context, but not the selected one

OTFAD context type.

Values:

enumerator kOTFAD_Context_0

context 0

enumerator kOTFAD_Context_1

context 1

enumerator kOTFAD_Context_2

context 2

enumerator kOTFAD_Context_3

context 3

OTFAD operate mode.

Values:

enumerator kOTFAD_NRM

Normal Mode

enumerator kOTFAD_SVM

Security Violation Mode

enumerator kOTFAD_LDM

Logically Disabled Mode

typedef struct _otfad_encryption_config otfad_encryption_config_t

OTFAD encryption configuration structure.

typedef struct _otfad_config otfad_config_t

OTFAD configuration structure.

struct _otfad_encryption_config

#include <fsl_otfad.h>

OTFAD encryption configuration structure.

Public Members

bool valid

The context is valid or not

bool AESdecryption

AES decryption enable

uint8_t readOnly

read write attribute for the entire set of context registers

uint8_t contextIndex

OTFAD context index

uint32_t startAddr

Start address

uint32_t endAddr

End address

uint32_t key[4]

Encryption key

uint32_t counter[2]

Encryption counter

struct _otfad_config

#include <fsl_otfad.h>

OTFAD configuration structure.

Public Members

bool forceSVM

Force entry into SVM after a write

bool forceLDM

Force entry into LDM after a write

bool restrictedRegAccess

Restricted register access enable

bool enableOTFAD

OTFAD has decryption enabled

PDM: Microphone Interface

PDM Driver

void PDM_Init(PDM_Type *base, const pdm_config_t *config)

Initializes the PDM peripheral.

Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. The configuration structure can be custom filled or set with default values by PDM_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the PDM driver. Otherwise, accessing the PDM module can cause a hard fault because the clock is not enabled.

Parameters:

• base – PDM base pointer

• config – PDM configuration structure.

void PDM_Deinit(PDM_Type *base)

De-initializes the PDM peripheral.

This API gates the PDM clock. The PDM module can’t operate unless PDM_Init is called to enable the clock.

Parameters:

• base – PDM base pointer

static inline void PDM_Reset(PDM_Type *base)

Resets the PDM module.

Parameters:

• base – PDM base pointer

static inline void PDM_Enable(PDM_Type *base, bool enable)

Enables/disables PDM interface.

Parameters:

• base – PDM base pointer

• enable – True means PDM interface is enabled, false means PDM interface is disabled.

static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable)

Enables/disables debug mode for PDM. The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode.

Parameters:

• base – PDM base pointer

• enable – True means PDM interface enter debug mode, false means PDM interface in normal mode.

static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable)

Enables/disables PDM interface in debug mode.

Parameters:

• base – PDM base pointer

• enable – True means PDM interface is enabled debug mode, false means PDM interface is disabled after after completing the current frame in debug mode.

static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable)

Enables/disables PDM interface disable/Low Leakage mode.

Parameters:

• base – PDM base pointer

• enable – True means PDM interface is in disable/low leakage mode, False means PDM interface is in normal mode.

static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable)

Enables/disables the PDM channel.

Parameters:

• base – PDM base pointer

• channel – PDM channel number need to enable or disable.

• enable – True means enable PDM channel, false means disable.

void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config)

PDM one channel configurations.

Parameters:

• base – PDM base pointer

• config – PDM channel configurations.

• channel – channel number. after completing the current frame in debug mode.

status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ)

PDM set sample rate.

Note

This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is

PDM_Init(base, pdmConfig)
PDM_SetChannelConfig(base, channel, &channelConfig)
PDM_SetSampleRateConfig(base, source, sampleRate)

Parameters:

• base – PDM base pointer

• sourceClock_HZ – PDM source clock frequency.

• sampleRate_HZ – PDM sample rate.

status_t PDM_SetSampleRate(PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv)

PDM set sample rate.

Deprecated:

Do not use this function. It has been superceded by PDM_SetSampleRateConfig

Parameters:

• base – PDM base pointer

• enableChannelMask – PDM channel enable mask.

• qualityMode – quality mode.

• osr – cic oversample rate

• clkDiv – clock divider

uint32_t PDM_GetInstance(PDM_Type *base)

Get the instance number for PDM.

Parameters:

• base – PDM base pointer.

static inline uint32_t PDM_GetStatus(PDM_Type *base)

Gets the PDM internal status flag. Use the Status Mask in _pdm_internal_status to get the status value needed.

Parameters:

• base – PDM base pointer

Returns:

PDM status flag value.

static inline uint32_t PDM_GetFifoStatus(PDM_Type *base)

Gets the PDM FIFO status flag. Use the Status Mask in _pdm_fifo_status to get the status value needed.

Parameters:

• base – PDM base pointer

Returns:

FIFO status.

static inline uint32_t PDM_GetRangeStatus(PDM_Type *base)

Gets the PDM Range status flag. Use the Status Mask in _pdm_range_status to get the status value needed.

Parameters:

• base – PDM base pointer

Returns:

output status.

static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status.

Parameters:

• base – PDM base pointer

• mask – State mask. It can be a combination of the status between kPDM_StatusFrequencyLow and kPDM_StatusCh7FifoDataAvaliable.

static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status.

Parameters:

• base – PDM base pointer

• mask – State mask.It can be a combination of the status in _pdm_fifo_status.

static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask)

Clears the PDM range status.

Parameters:

• base – PDM base pointer

• mask – State mask. It can be a combination of the status in _pdm_range_status.

void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask)

Enables the PDM interrupt requests.

Parameters:

• base – PDM base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kPDM_ErrorInterruptEnable

  • kPDM_FIFOInterruptEnable

static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask)

Disables the PDM interrupt requests.

Parameters:

• base – PDM base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kPDM_ErrorInterruptEnable

  • kPDM_FIFOInterruptEnable

static inline void PDM_EnableDMA(PDM_Type *base, bool enable)

Enables/disables the PDM DMA requests.

Parameters:

• base – PDM base pointer

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel)

Gets the PDM data register address.

This API is used to provide a transfer address for the PDM DMA transfer configuration.

Parameters:

• base – PDM base pointer.

• channel – Which data channel used.

Returns:

data register address.

void PDM_ReadFifo(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth)

PDM read fifo.

Note

: This function support 16 bit only for IP version that only supports 16bit.

Parameters:

• base – PDM base pointer.

• startChannel – start channel number.

• channelNums – total enabled channelnums.

• buffer – received buffer address.

• size – number of samples to read.

• dataWidth – sample width.

void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain)

Set the PDM channel gain.

Please note for different quality mode, the valid gain value is different, reference RM for detail.

Parameters:

• base – PDM base pointer.

• channel – PDM channel index.

• gain – channel gain, the register gain value range is 0 - 15.

void PDM_SetHwvadConfig(PDM_Type *base, const pdm_hwvad_config_t *config)

Configure voice activity detector.

Parameters:

• base – PDM base pointer

• config – Voice activity detector configure structure pointer .

static inline void PDM_ForceHwvadOutputDisable(PDM_Type *base, bool enable)

PDM hwvad force output disable.

Parameters:

• base – PDM base pointer

• enable – true is output force disable, false is output not force.

static inline void PDM_ResetHwvad(PDM_Type *base)

PDM hwvad reset. It will reset VADNDATA register and will clean all internal buffers, should be called when the PDM isn’t running.

Parameters:

• base – PDM base pointer

static inline void PDM_EnableHwvad(PDM_Type *base, bool enable)

Enable/Disable Voice activity detector. Should be called when the PDM isn’t running.

Parameters:

• base – PDM base pointer.

• enable – True means enable voice activity detector, false means disable.

static inline void PDM_EnableHwvadInterrupts(PDM_Type *base, uint32_t mask)

Enables the PDM Voice Detector interrupt requests.

Parameters:

• base – PDM base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kPDM_HWVADErrorInterruptEnable

  • kPDM_HWVADInterruptEnable

static inline void PDM_DisableHwvadInterrupts(PDM_Type *base, uint32_t mask)

Disables the PDM Voice Detector interrupt requests.

Parameters:

• base – PDM base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kPDM_HWVADErrorInterruptEnable

  • kPDM_HWVADInterruptEnable

static inline void PDM_ClearHwvadInterruptStatusFlags(PDM_Type *base, uint32_t mask)

Clears the PDM voice activity detector status flags.

Parameters:

• base – PDM base pointer

• mask – State mask,reference _pdm_hwvad_int_status.

static inline uint32_t PDM_GetHwvadInterruptStatusFlags(PDM_Type *base)

Clears the PDM voice activity detector status flags.

Parameters:

• base – PDM base pointer

Returns:

status, reference _pdm_hwvad_int_status

static inline uint32_t PDM_GetHwvadInitialFlag(PDM_Type *base)

Get the PDM voice activity detector initial flags.

Parameters:

• base – PDM base pointer

Returns:

initial flag.

static inline void PDM_EnableHwvadSignalFilter(PDM_Type *base, bool enable)

Enables/disables voice activity detector signal filter.

Parameters:

• base – PDM base pointer

• enable – True means enable signal filter, false means disable.

void PDM_SetHwvadSignalFilterConfig(PDM_Type *base, bool enableMaxBlock, uint32_t signalGain)

Configure voice activity detector signal filter.

Parameters:

• base – PDM base pointer

• enableMaxBlock – If signal maximum block enabled.

• signalGain – Gain value for the signal energy.

void PDM_SetHwvadNoiseFilterConfig(PDM_Type *base, const pdm_hwvad_noise_filter_t *config)

Configure voice activity detector noise filter.

Parameters:

• base – PDM base pointer

• config – Voice activity detector noise filter configure structure pointer .

static inline void PDM_EnableHwvadZeroCrossDetector(PDM_Type *base, bool enable)

Enables/disables voice activity detector zero cross detector.

Parameters:

• base – PDM base pointer

• enable – True means enable zero cross detector, false means disable.

void PDM_SetHwvadZeroCrossDetectorConfig(PDM_Type *base, const pdm_hwvad_zero_cross_detector_t *config)

Configure voice activity detector zero cross detector.

Parameters:

• base – PDM base pointer

• config – Voice activity detector zero cross detector configure structure pointer .

static inline uint16_t PDM_GetNoiseData(PDM_Type *base)

Reads noise data.

Parameters:

• base – PDM base pointer.

Returns:

Data in PDM noise data register.

static inline void PDM_SetHwvadInternalFilterStatus(PDM_Type *base, pdm_hwvad_filter_status_t status)

set hwvad internal filter status . Note: filter initial status should be asserted for two more cycles, then set it to normal operation.

Parameters:

• base – PDM base pointer.

• status – internal filter status.

void PDM_SetHwvadInEnvelopeBasedMode(PDM_Type *base, const pdm_hwvad_config_t *hwvadConfig, const pdm_hwvad_noise_filter_t *noiseConfig, const pdm_hwvad_zero_cross_detector_t *zcdConfig, uint32_t signalGain)

set HWVAD in envelope based mode . Recommand configurations,

   static const pdm_hwvad_config_t hwvadConfig = {
     .channel           = 0,
     .initializeTime    = 10U,
     .cicOverSampleRate = 0U,
     .inputGain         = 0U,
     .frameTime         = 10U,
     .cutOffFreq        = kPDM_HwvadHpfBypassed,
     .enableFrameEnergy = false,
     .enablePreFilter   = true,
};

   static const pdm_hwvad_noise_filter_t noiseFilterConfig = {
     .enableAutoNoiseFilter = false,
     .enableNoiseMin        = true,
     .enableNoiseDecimation = true,
     .noiseFilterAdjustment = 0U,
     .noiseGain             = 7U,
     .enableNoiseDetectOR   = true,
   };

Parameters:

• base – PDM base pointer.

• hwvadConfig – internal filter status.

• noiseConfig – Voice activity detector noise filter configure structure pointer.

• zcdConfig – Voice activity detector zero cross detector configure structure pointer .

• signalGain – signal gain value.

void PDM_SetHwvadInEnergyBasedMode(PDM_Type *base, const pdm_hwvad_config_t *hwvadConfig, const pdm_hwvad_noise_filter_t *noiseConfig, const pdm_hwvad_zero_cross_detector_t *zcdConfig, uint32_t signalGain)

brief set HWVAD in energy based mode . Recommand configurations, code static const pdm_hwvad_config_t hwvadConfig = { .channel = 0, .initializeTime = 10U, .cicOverSampleRate = 0U, .inputGain = 0U, .frameTime = 10U, .cutOffFreq = kPDM_HwvadHpfBypassed, .enableFrameEnergy = true, .enablePreFilter = true, };

static const pdm_hwvad_noise_filter_t noiseFilterConfig = { .enableAutoNoiseFilter = true, .enableNoiseMin = false, .enableNoiseDecimation = false, .noiseFilterAdjustment = 0U, .noiseGain = 7U, .enableNoiseDetectOR = false, }; code param base PDM base pointer. param hwvadConfig internal filter status. param noiseConfig Voice activity detector noise filter configure structure pointer. param zcdConfig Voice activity detector zero cross detector configure structure pointer . param signalGain signal gain value, signal gain value should be properly according to application.

void PDM_EnableHwvadInterruptCallback(PDM_Type *base, pdm_hwvad_callback_t vadCallback, void *userData, bool enable)

Enable/Disable hwvad callback.

This function enable/disable the hwvad interrupt for the selected PDM peripheral.

Parameters:

• base – Base address of the PDM peripheral.

• vadCallback – callback Pointer to store callback function, should be NULL when disable.

• userData – user data.

• enable – true is enable, false is disable.

Return values:

None. –

void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData)

Initializes the PDM handle.

This function initializes the handle for the PDM transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – PDM base pointer.

• handle – PDM handle pointer.

• callback – Pointer to the user callback function.

• userData – User parameter passed to the callback function.

status_t PDM_TransferSetChannelConfig(PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format)

PDM set channel transfer config.

Parameters:

• base – PDM base pointer.

• handle – PDM handle pointer.

• channel – PDM channel.

• config – channel config.

• format – data format, support data width configurations,_pdm_data_width.

Return values:

kStatus_PDM_ChannelConfig_Failed – or kStatus_Success.

status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on PDM.

Note

This API returns immediately after the transfer initiates. Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer is finished.

Parameters:

• base – PDM base pointer

• handle – Pointer to the pdm_handle_t structure which stores the transfer state.

• xfer – Pointer to the pdm_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_PDM_Busy – Previous receive still not finished.

void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle)

Aborts the current IRQ receive.

Note

This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – PDM base pointer

• handle – Pointer to the pdm_handle_t structure which stores the transfer state.

void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle)

Tx interrupt handler.

Parameters:

• base – PDM base pointer.

• handle – Pointer to the pdm_handle_t structure.

FSL_PDM_DRIVER_VERSION

Version 2.9.1

PDM return status.

Values:

enumerator kStatus_PDM_Busy

PDM is busy.

enumerator kStatus_PDM_CLK_LOW

PDM clock frequency low

enumerator kStatus_PDM_FIFO_ERROR

PDM FIFO underrun or overflow

enumerator kStatus_PDM_QueueFull

PDM FIFO underrun or overflow

enumerator kStatus_PDM_Idle

PDM is idle

enumerator kStatus_PDM_Output_ERROR

PDM is output error

enumerator kStatus_PDM_ChannelConfig_Failed

PDM channel config failed

enumerator kStatus_PDM_HWVAD_VoiceDetected

PDM hwvad voice detected

enumerator kStatus_PDM_HWVAD_Error

PDM hwvad error

enum _pdm_interrupt_enable

The PDM interrupt enable flag.

Values:

enumerator kPDM_ErrorInterruptEnable

PDM channel error interrupt enable.

enumerator kPDM_FIFOInterruptEnable

PDM channel FIFO interrupt

enum _pdm_internal_status

The PDM status.

Values:

enumerator kPDM_StatusDfBusyFlag

Decimation filter is busy processing data

enumerator kPDM_StatusFrequencyLow

Mic app clock frequency not high enough

enumerator kPDM_StatusCh0FifoDataAvaliable

channel 0 fifo data reached watermark level

enumerator kPDM_StatusCh1FifoDataAvaliable

channel 1 fifo data reached watermark level

enumerator kPDM_StatusCh2FifoDataAvaliable

channel 2 fifo data reached watermark level

enumerator kPDM_StatusCh3FifoDataAvaliable

channel 3 fifo data reached watermark level

enum _pdm_channel_enable_mask

PDM channel enable mask.

Values:

enumerator kPDM_EnableChannel0

channgel 0 enable mask

enumerator kPDM_EnableChannel1

channgel 1 enable mask

enumerator kPDM_EnableChannel2

channgel 2 enable mask

enumerator kPDM_EnableChannel3

channgel 3 enable mask

enumerator kPDM_EnableChannelAll

enum _pdm_fifo_status

The PDM fifo status.

Values:

enumerator kPDM_FifoStatusUnderflowCh0

channel0 fifo status underflow

enumerator kPDM_FifoStatusUnderflowCh1

channel1 fifo status underflow

enumerator kPDM_FifoStatusUnderflowCh2

channel2 fifo status underflow

enumerator kPDM_FifoStatusUnderflowCh3

channel3 fifo status underflow

enumerator kPDM_FifoStatusOverflowCh0

channel0 fifo status overflow

enumerator kPDM_FifoStatusOverflowCh1

channel1 fifo status overflow

enumerator kPDM_FifoStatusOverflowCh2

channel2 fifo status overflow

enumerator kPDM_FifoStatusOverflowCh3

channel3 fifo status overflow

enum _pdm_range_status

The PDM output status.

Values:

enumerator kPDM_RangeStatusUnderFlowCh0

channel0 range status underflow

enumerator kPDM_RangeStatusUnderFlowCh1

channel1 range status underflow

enumerator kPDM_RangeStatusUnderFlowCh2

channel2 range status underflow

enumerator kPDM_RangeStatusUnderFlowCh3

channel3 range status underflow

enumerator kPDM_RangeStatusOverFlowCh0

channel0 range status overflow

enumerator kPDM_RangeStatusOverFlowCh1

channel1 range status overflow

enumerator kPDM_RangeStatusOverFlowCh2

channel2 range status overflow

enumerator kPDM_RangeStatusOverFlowCh3

channel3 range status overflow

enum _pdm_dc_remover

PDM DC remover configurations.

Values:

enumerator kPDM_DcRemoverCutOff21Hz

DC remover cut off 21HZ

enumerator kPDM_DcRemoverCutOff83Hz

DC remover cut off 83HZ

enumerator kPDM_DcRemoverCutOff152Hz

DC remover cut off 152HZ

enumerator kPDM_DcRemoverBypass

DC remover bypass

enum _pdm_df_quality_mode

PDM decimation filter quality mode.

Values:

enumerator kPDM_QualityModeMedium

quality mode memdium

enumerator kPDM_QualityModeHigh

quality mode high

enumerator kPDM_QualityModeLow

quality mode low

enumerator kPDM_QualityModeVeryLow0

quality mode very low0

enumerator kPDM_QualityModeVeryLow1

quality mode very low1

enumerator kPDM_QualityModeVeryLow2

quality mode very low2

enum _pdm_qulaity_mode_k_factor

PDM quality mode K factor.

Values:

enumerator kPDM_QualityModeHighKFactor

high quality mode K factor = 1 / 2

enumerator kPDM_QualityModeMediumKFactor

medium/very low0 quality mode K factor = 2 / 2

enumerator kPDM_QualityModeLowKFactor

low/very low1 quality mode K factor = 4 / 2

enumerator kPDM_QualityModeVeryLow2KFactor

very low2 quality mode K factor = 8 / 2

enum _pdm_df_output_gain

PDM decimation filter output gain.

Values:

enumerator kPDM_DfOutputGain0

Decimation filter output gain 0

enumerator kPDM_DfOutputGain1

Decimation filter output gain 1

enumerator kPDM_DfOutputGain2

Decimation filter output gain 2

enumerator kPDM_DfOutputGain3

Decimation filter output gain 3

enumerator kPDM_DfOutputGain4

Decimation filter output gain 4

enumerator kPDM_DfOutputGain5

Decimation filter output gain 5

enumerator kPDM_DfOutputGain6

Decimation filter output gain 6

enumerator kPDM_DfOutputGain7

Decimation filter output gain 7

enumerator kPDM_DfOutputGain8

Decimation filter output gain 8

enumerator kPDM_DfOutputGain9

Decimation filter output gain 9

enumerator kPDM_DfOutputGain10

Decimation filter output gain 10

enumerator kPDM_DfOutputGain11

Decimation filter output gain 11

enumerator kPDM_DfOutputGain12

Decimation filter output gain 12

enumerator kPDM_DfOutputGain13

Decimation filter output gain 13

enumerator kPDM_DfOutputGain14

Decimation filter output gain 14

enumerator kPDM_DfOutputGain15

Decimation filter output gain 15

enum _pdm_data_width

PDM data width.

Values:

enumerator kPDM_DataWwidth24

PDM data width 24bit

enumerator kPDM_DataWwidth32

PDM data width 32bit

enum _pdm_hwvad_interrupt_enable

PDM voice activity detector interrupt type.

Values:

enumerator kPDM_HwvadErrorInterruptEnable

PDM channel HWVAD error interrupt enable.

enumerator kPDM_HwvadInterruptEnable

PDM channel HWVAD interrupt

enum _pdm_hwvad_int_status

The PDM hwvad interrupt status flag.

Values:

enumerator kPDM_HwvadStatusInputSaturation

HWVAD saturation condition

enumerator kPDM_HwvadStatusVoiceDetectFlag

HWVAD voice detect interrupt triggered

enum _pdm_hwvad_hpf_config

High pass filter configure cut-off frequency.

Values:

enumerator kPDM_HwvadHpfBypassed

High-pass filter bypass

enumerator kPDM_HwvadHpfCutOffFreq1750Hz

High-pass filter cut off frequency 1750HZ

enumerator kPDM_HwvadHpfCutOffFreq215Hz

High-pass filter cut off frequency 215HZ

enumerator kPDM_HwvadHpfCutOffFreq102Hz

High-pass filter cut off frequency 102HZ

enum _pdm_hwvad_filter_status

HWVAD internal filter status.

Values:

enumerator kPDM_HwvadInternalFilterNormalOperation

internal filter ready for normal operation

enumerator kPDM_HwvadInternalFilterInitial

interla filter are initial

enum _pdm_hwvad_zcd_result

PDM voice activity detector zero cross detector result.

Values:

enumerator kPDM_HwvadResultOREnergyBasedDetection

zero cross detector result will be OR with energy based detection

enumerator kPDM_HwvadResultANDEnergyBasedDetection

zero cross detector result will be AND with energy based detection

typedef enum _pdm_dc_remover pdm_dc_remover_t

PDM DC remover configurations.

typedef enum _pdm_df_quality_mode pdm_df_quality_mode_t

PDM decimation filter quality mode.

typedef enum _pdm_df_output_gain pdm_df_output_gain_t

PDM decimation filter output gain.

typedef struct _pdm_channel_config pdm_channel_config_t

PDM channel configurations.

typedef struct _pdm_config pdm_config_t

PDM user configuration structure.

typedef enum _pdm_hwvad_hpf_config pdm_hwvad_hpf_config_t

High pass filter configure cut-off frequency.

typedef enum _pdm_hwvad_filter_status pdm_hwvad_filter_status_t

HWVAD internal filter status.

typedef struct _pdm_hwvad_config pdm_hwvad_config_t

PDM voice activity detector user configuration structure.

typedef struct _pdm_hwvad_noise_filter pdm_hwvad_noise_filter_t

PDM voice activity detector noise filter user configuration structure.

typedef enum _pdm_hwvad_zcd_result pdm_hwvad_zcd_result_t

PDM voice activity detector zero cross detector result.

typedef struct _pdm_hwvad_zero_cross_detector pdm_hwvad_zero_cross_detector_t

PDM voice activity detector zero cross detector configuration structure.

typedef struct _pdm_transfer pdm_transfer_t

PDM SDMA transfer structure.

typedef struct _pdm_handle pdm_handle_t

PDM handle.

typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData)

PDM transfer callback prototype.

typedef void (*pdm_hwvad_callback_t)(status_t status, void *userData)

PDM HWVAD callback prototype.

typedef struct _pdm_hwvad_notification pdm_hwvad_notification_t

PDM HWVAD notification structure.

PDM_XFER_QUEUE_SIZE

PDM XFER QUEUE SIZE.

struct _pdm_channel_config

#include <fsl_pdm.h>

PDM channel configurations.

Public Members

pdm_dc_remover_t cutOffFreq

DC remover cut off frequency

pdm_df_output_gain_t gain

Decimation Filter Output Gain

struct _pdm_config

#include <fsl_pdm.h>

PDM user configuration structure.

Public Members

bool enableDoze

This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted

bool enableFilterBypass

Switchable bypass path for the decimation filter

uint8_t fifoWatermark

Watermark value for FIFO

pdm_df_quality_mode_t qualityMode

Quality mode

uint8_t cicOverSampleRate

CIC filter over sampling rate

struct _pdm_hwvad_config

#include <fsl_pdm.h>

PDM voice activity detector user configuration structure.

Public Members

uint8_t channel

Which channel uses voice activity detector

uint8_t initializeTime

Number of frames or samples to initialize voice activity detector.

uint8_t cicOverSampleRate

CIC filter over sampling rate

uint8_t inputGain

Voice activity detector input gain

uint32_t frameTime

Voice activity frame time

pdm_hwvad_hpf_config_t cutOffFreq

High pass filter cut off frequency

bool enableFrameEnergy

If frame energy enabled, true means enable

bool enablePreFilter

If pre-filter enabled

struct _pdm_hwvad_noise_filter

#include <fsl_pdm.h>

PDM voice activity detector noise filter user configuration structure.

Public Members

bool enableAutoNoiseFilter

If noise fileter automatically activated, true means enable

bool enableNoiseMin

If Noise minimum block enabled, true means enabled

bool enableNoiseDecimation

If enable noise input decimation

bool enableNoiseDetectOR

Enables a OR logic in the output of minimum noise estimator block

uint32_t noiseFilterAdjustment

The adjustment value of the noise filter

uint32_t noiseGain

Gain value for the noise energy or envelope estimated

struct _pdm_hwvad_zero_cross_detector

#include <fsl_pdm.h>

PDM voice activity detector zero cross detector configuration structure.

Public Members

bool enableAutoThreshold

If ZCD auto-threshold enabled, true means enabled.

pdm_hwvad_zcd_result_t zcdAnd

Is ZCD result is AND’ed with energy-based detection, false means OR’ed

uint32_t threshold

The adjustment value of the noise filter

uint32_t adjustmentThreshold

Gain value for the noise energy or envelope estimated

struct _pdm_transfer

#include <fsl_pdm.h>

PDM SDMA transfer structure.

Public Members

volatile uint8_t *data

Data start address to transfer.

volatile size_t dataSize

Total Transfer bytes size.

struct _pdm_hwvad_notification

#include <fsl_pdm.h>

PDM HWVAD notification structure.

struct _pdm_handle

#include <fsl_pdm.h>

PDM handle structure.

Public Members

uint32_t state

Transfer status

pdm_transfer_callback_t callback

Callback function called at transfer event

void *userData

Callback parameter passed to callback function

pdm_transfer_t pdmQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint32_t format

data format

uint8_t watermark

Watermark value

uint8_t startChannel

end channel

uint8_t channelNums

Enabled channel number

PDM EDMA Driver

void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum)

Install EDMA descriptor memory.

Parameters:

• handle – Pointer to EDMA channel transfer handle.

• tcdAddr – EDMA head descriptor address.

• tcdNum – EDMA link descriptor address.

void PDM_TransferCreateHandleEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the PDM Rx eDMA handle.

This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. Usually, for a specified PDM instance, call this API once to get the initialized handle.

Parameters:

• base – PDM base pointer.

• handle – PDM eDMA handle pointer.

• callback – Pointer to user callback function.

• userData – User parameter passed to the callback function.

• dmaHandle – eDMA handle pointer, this handle shall be static allocated by users.

void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, pdm_edma_multi_channel_interleave_t multiChannelInterleaveType)

Initializes the multi PDM channel interleave type.

This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is kPDM_EDMAMultiChannelInterleavePerChannelSample always

Parameters:

• handle – PDM eDMA handle pointer.

• multiChannelInterleaveType – Multi channel interleave type.

void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, pdm_edma_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config)

Configures the PDM channel.

Parameters:

• base – PDM base pointer.

• handle – PDM eDMA handle pointer.

• channel – channel index.

• config – pdm channel configurations.

status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer)

Performs a non-blocking PDM receive using eDMA.

Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally.

1. Scatter gather case: This functio support dynamic scatter gather and staic scatter gather, a. for the dynamic scatter gather case: Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit before the previous one finish. b. for the static scatter gather case: Application should use the link transfer feature and make sure a loop link transfer is provided, such as:

   pdm_edma_transfer_t pdmXfer[2] =
    {
        {
        .data  = s_buffer,
        .dataSize = BUFFER_SIZE,
        .linkTransfer = &pdmXfer[1],
        },
   
        {
        .data  = &s_buffer[BUFFER_SIZE],
        .dataSize = BUFFER_SIZE,
        .linkTransfer = &pdmXfer[0]
        },
    };
   

2. Multi channel case: This function support receive multi pdm channel data, for example, if two channel is requested,

   PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig);
   PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig);
   PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer);
   

   The output data will be formatted as below if handle->interleaveType =

Note

This interface returns immediately after the transfer initiates. Call the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished.

void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Terminate all PDM receive.

This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the current transfer slot, please call PDM_TransferAbortReceiveEDMA.

Parameters:

• base – PDM base pointer.

• handle – PDM eDMA handle pointer.

void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Aborts a PDM receive using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA.

Parameters:

• base – PDM base pointer

• handle – PDM eDMA handle pointer.

status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count)

Gets byte count received by PDM.

Parameters:

• base – PDM base pointer

• handle – PDM eDMA handle pointer.

• count – Bytes count received by PDM.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.

FSL_PDM_EDMA_DRIVER_VERSION

Version 2.6.3

enum _pdm_edma_multi_channel_interleave

pdm multi channel interleave type

Values:

enumerator kPDM_EDMAMultiChannelInterleavePerChannelSample

enumerator kPDM_EDMAMultiChannelInterleavePerChannelBlock

typedef struct _pdm_edma_handle pdm_edma_handle_t

PDM edma handler.

typedef enum _pdm_edma_multi_channel_interleave pdm_edma_multi_channel_interleave_t

pdm multi channel interleave type

typedef struct _pdm_edma_transfer pdm_edma_transfer_t

PDM edma transfer.

typedef void (*pdm_edma_callback_t)(PDM_Type *base, pdm_edma_handle_t *handle, status_t status, void *userData)

PDM eDMA transfer callback function for finish and error.

MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL

the PDM enable position When calling PDM_TransferReceiveEDMA

struct _pdm_edma_transfer

#include <fsl_pdm_edma.h>

PDM edma transfer.

Public Members

volatile uint8_t *data

Data start address to transfer.

volatile size_t dataSize

Total Transfer bytes size.

struct _pdm_edma_transfer *linkTransfer

linked transfer configurations

struct _pdm_edma_handle

#include <fsl_pdm_edma.h>

PDM DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle

DMA handler for PDM send

uint8_t count

The transfer data count in a DMA request

uint32_t receivedBytes

total transfer count

uint32_t state

Internal state for PDM eDMA transfer

pdm_edma_callback_t callback

Callback for users while transfer finish or error occurs

bool isLoopTransfer

loop transfer

void *userData

User callback parameter

edma_tcd_t *tcd

TCD pool for eDMA transfer.

uint32_t tcdNum

TCD number

uint32_t tcdUser

Index for user to queue transfer.

uint32_t tcdDriver

Index for driver to get the transfer data and size

volatile uint32_t tcdUsedNum

Index for user to queue transfer.

pdm_edma_multi_channel_interleave_t interleaveType

multi channel transfer interleave type

uint8_t endChannel

The last enabled channel

uint8_t channelNums

total channel numbers

PGMC

The enumeration of setpoint. .

Values:

enumerator kPGMC_SetPoint0

The mask of set point0.

enumerator kPGMC_SetPoint1

The mask of set point1.

enumerator kPGMC_SetPoint2

The mask of set point2.

enumerator kPGMC_SetPoint3

The mask of set point3.

enumerator kPGMC_SetPoint4

The mask of set point4.

enumerator kPGMC_SetPoint5

The mask of set point5.

enumerator kPGMC_SetPoint6

The mask of set point6.

enumerator kPGMC_SetPoint7

The mask of set point7.

enumerator kPGMC_SetPoint8

The mask of set point8.

enumerator kPGMC_SetPoint9

The mask of set point9.

enumerator kPGMC_SetPoint10

The mask of set point10.

enumerator kPGMC_SetPoint11

The mask of set point11.

enumerator kPGMC_SetPoint12

The mask of set point12.

enumerator kPGMC_SetPoint13

The mask of set point13.

enumerator kPGMC_SetPoint14

The mask of set point14.

enumerator kPGMC_SetPoint15

The mask of set point15.

enum _pgmc_mif_signal_behaviour

The enumeration of MIF signal behaviour(Such as Sleep Signal, Standby Signal, and so on).

Values:

enumerator kPGMC_AssertSleepSignal

Assert Sleep signal.

enumerator kPGMC_AssertInputGateSignal

Assert InputGate signal.

enumerator kPGMC_AssetLowSpeedSignal

Assert LowSpeed signal.

enumerator kPGMC_AssertHighSpeedSignal

Assert HighSpeed signal.

enumerator kPGMC_AssertStandbySignal

Assert Standby signal.

enumerator kPGMC_AssertArrayPowerDownSignal

Assert ArrayPowerDown signal.

enumerator kPGMC_AssertPeripheralPowerDownSignal

Assert PeripheralPowerDown signal.

enumerator kPGMC_AssertInitnSignal

Assert Initn signal.

enumerator kPGMC_AssertSwitch1OffSignal

Assert Switch1Off signal.

enumerator kPGMC_AssertSwitch2OffSignal

Assert Switch2Off signal.

enumerator kPGMC_AssertIsoSignal

Assert Iso_en signal.

enum _pgmc_bpc_assign_domain

PGMC BPC assign domain enumeration.

Values:

enumerator kPGMC_CM7Core

CM7 Core domain.

enumerator kPGMC_CM4Core

CM4 Core domain.

enum _pgmc_cpu_mode

CPU mode.

Values:

enumerator kPGMC_RunMode

RUN mode.

enumerator kPGMC_WaitMode

WAIT mode.

enumerator kPGMC_StopMode

STOP mode.

enumerator kPGMC_SuspendMode

SUSPEND mode.

enum _pgmc_control_mode

PGMC control modes.

Values:

enumerator kPGMC_DisableLowPowerControl

enumerator kPGMC_ControlledByCpuPowerMode

enumerator kPGMC_ControlledBySetPoint

enum _pgmc_memory_low_power_level

The enumeration of memory low power level.

Values:

enumerator kPGMC_MLPLHighSpeed

Memory low power level: High speed.

enumerator kPGMC_MLPLNormal

Memory low power level: Normal.

enumerator kPGMC_MLPLLowSpeed

Memory low power level: Low Speed.

enumerator kPGMC_MLPLInputGating

Memory low power level: Input Gating.

enumerator kPGMC_MLPLStandby

Memory low power level: Standby.

enumerator kPGMC_MLPLSleep

Memory low power level: Sleep.

enumerator kPGMC_MLPLArrOnPerOff

Memory low power level: Arr on per off.

enumerator kPGMC_MLPLArrOffPerOn

Memory low power level: Arr off per on.

enumerator kPGMC_MLPLArrOffPerOff

Memory low power level: Arr off per off.

enumerator kPGMC_MLPLSw2

Memory low power level: SW2.

enumerator kPGMC_MLPLSw2PerOff

Memory low power level: SW2 Per off.

enumerator kPGMC_MLPLSw1PerOff

Memory low power level: SW1 Per off.

enum _pgmc_mif_signal

The enumeration of MIF signal.

Values:

enumerator kPGMC_SleepSignal

MIF Sleep signal.

enumerator kPGMC_InputGateSignal

MIF InputGate signal.

enumerator kPGMC_LowSpeedSignal

MIF LowSpeed signal.

enumerator kPGMC_HighSpeedSignal

MIF HighSpeed signal.

enumerator kPGMC_StandbySignal

MIF Standby signal.

enumerator kPGMC_ArrayPowerDownSignal

MIF ArrayPowerDown signal.

enumerator kPGMC_PeripheralPowerDownSignal

MIF PeripheralPowerDown signal.

enumerator kPGMC_InitnSignal

MIF Initn signal.

enumerator kPGMC_Switch1OffSignal

MIF Switch1Off signal.

enumerator kPGMC_Switch2OffSignal

MIF Switch2Off signal.

enumerator kPGMC_IsoSignal

MIF Iso_en signal.

typedef enum _pgmc_bpc_assign_domain pgmc_bpc_assign_domain_t

PGMC BPC assign domain enumeration.

typedef enum _pgmc_cpu_mode pgmc_cpu_mode_t

CPU mode.

typedef enum _pgmc_control_mode pgmc_control_mode_t

PGMC control modes.

typedef enum _pgmc_memory_low_power_level pgmc_memory_low_power_level_t

The enumeration of memory low power level.

typedef enum _pgmc_mif_signal pgmc_mif_signal_t

The enumeration of MIF signal.

typedef struct _pgmc_bpc_cpu_power_mode_option pgmc_bpc_cpu_power_mode_option_t

The control option of the power domain controlled by CPU power mode.

typedef struct _pgmc_bpc_setpoint_mode_option pgmc_bpc_setpoint_mode_option_t

The control option of the power domain controlled by setpoint mode.

FSL_PGMC_RIVER_VERSION

PGMC driver version 2.1.2.

void PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC_Type *base, pgmc_cpu_mode_t mode, const pgmc_bpc_cpu_power_mode_option_t *option)

Makes the BPC module controlled by the target CPU power mode, such as Wait mode.

This function makes the module controlled by four typical CPU power modes, It also configs the resource domain and set memory low power level.

Parameters:

• base – PGMC basic power controller base address.

• mode – Target CPU power mode.

• option – The pointer of pgmc_bpc_cpu_power_mode_option_t structure.

void PGMC_BPC_ControlPowerDomainBySetPointMode(PGMC_BPC_Type *base, uint32_t setPointMap, const pgmc_bpc_setpoint_mode_option_t *option)

Makes the BPC module controlled by the target set points.

This function makes the module controlled by specific set point, It also supports set memory lowe power level.

Note

When setting more than one set point, use “|” between the map values in _pgmc_setpoint_map.

Parameters:

• base – PGMC basic power controller base address.

• setPointMap – Should be the OR’ed value of _pgmc_setpoint_map.

• option – The pointer of pgmc_bpc_setpoint_mode_option_t structure.

void PGMC_BPC_ControlPowerDomainBySoftwareMode(PGMC_BPC_Type *base, bool powerOff)

Controls the selected power domain by software mode.

Note

The function is used to control power domain when the CPU is in RUN mode.

Parameters:

• base – PGMC basic power controller base address.

• powerOff – Power On/Off power domain in software mode.

  • true Power off the power domain in software mode.

  • false Power on the power domain in software mode.

static inline void PGMC_BPC_DisableLowPower(PGMC_BPC_Type *base)

Disables low power mode control.

Parameters:

• base – PGMC basic power controller base address.

static inline void PGMC_BPC_RequestStateRestoreAtRunMode(PGMC_BPC_Type *base)

Requests power domain state restore at run mode.

Parameters:

• base – PGMC basic power controller base address.

static inline void PGMC_BPC_RequestStateRestoreAtSetPoint(PGMC_BPC_Type *base, uint32_t setPointMap)

Requests power domain state restore when enters the selected set points.

Note

When setting more than one set point, use “|” between the map values in _pgmc_setpoint_map.

Parameters:

• base – PGMC basic power controller base address.

• setPointMap – Should be the OR’ed value of _pgmc_setpoint_map.

static inline void PGMC_BPC_AllowUserModeAccess(PGMC_BPC_Type *base, bool enable)

Allows user mode access or not for the BPC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – PGMC basic power controller base address.

• enable – Used to control whether allow user mode access.

  • true Allow both privilege and user mode to access CPU mode control registers.

  • false Allow only privilege mode to access CPU mode control registers.

static inline void PGMC_BPC_AllowNonSecureModeAccess(PGMC_BPC_Type *base, bool enable)

Allows non-secure mode access or not for the BPC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – PGMC basic power controller base address.

• enable – Used to control whether allow non-secure mode to access CPU mode control registers.

  • true Allow both secure and non-secure mode to access CPU mode control registers.

  • false Allow only secure mode to access CPU mode control registers.

static inline void PGMC_BPC_LockAccessSetting(PGMC_BPC_Type *base)

Locks access related settings for the BPC module, including Secure access setting and user access setting.

Note

This function used to lock access related settings. After locked the related bit field can not be written unless POR.

Parameters:

• base – PGMC basic power controller base address.

static inline void PGMC_BPC_SetDomainIdWhiteList(PGMC_BPC_Type *base, uint8_t domainId)

Sets the corrsponding domain ID that can access CPU mode control registers for the BPC module.

Note

If locked the domain ID white list, the setting via this function is useless.

Parameters:

• base – PGMC basic power controller base address.

• domainId – Should be the OR’ed value of pgmc_bpc_assign_domain_t.

static inline void PGMC_BPC_LockDomainIDWhiteList(PGMC_BPC_Type *base)

Locks the value of Domain ID white list for the BPC module.

Note

After locked the domain ID white list can not be written again unless POR.

Parameters:

• base – PGMC basic power controller base address.

static inline void PGMC_BPC_LockLowPowerConfigurationFields(PGMC_BPC_Type *base)

Locks low power configuration fields for the BPC module.

Note

After locked the low power configurations fields can not be updated unless POR.

Parameters:

• base – PGMC basic power controller base address.

void PGMC_CPC_CORE_PowerOffByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode)

Powers off the CPC core module by the target CPU power mode, such as Wait mode.

Parameters:

• base – CPC CORE module base address.

• mode – Target CPU power mode.

static inline void PGMC_CPC_CORE_PowerOffBySoftwareMode(PGMC_CPC_Type *base, bool powerOff)

Powers off/on the CPC core module by the software.

Parameters:

• base – CPC CORE module base address.

• powerOff – Used to power off/on the CPC core module.

  • true Power off the CPC core module.

  • false Power on the CPC core module.

static inline void PGMC_CPC_CORE_DisableLowPower(PGMC_CPC_Type *base)

Disables low power mode control, the CPU core will not be affected by any low power modes.

Parameters:

• base – CPC CORE module base address.

void PGMC_CPC_CACHE_ControlByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode, pgmc_memory_low_power_level_t memoryLowPowerLevel)

Makes the CPC CACHE module controlled by the target CPU power mode, such as Wait mode.

This function makes the module controlled by four typical CPU power modes, it also can set memory low power level.

Parameters:

• base – CPC CACHE module base address.

• mode – Target CPU power mode.

• memoryLowPowerLevel – Memory low power level.

void PGMC_CPC_CACHE_ControlBySetPointMode(PGMC_CPC_Type *base, uint32_t setPointMap, pgmc_memory_low_power_level_t memoryLowPowerLevel)

Makes the CPC CACHE module controlled by the target set points.

This function makes the module controlled by specific set point, It also supports set memory lowe power level.

Note

When setting more than one set point, use “|” between the map values in _pgmc_setpoint_map.

Parameters:

• base – CPC CACHE module base address.

• setPointMap – Should be the OR’ed value of _pgmc_setpoint_map.

• memoryLowPowerLevel – Memory low power level.

static inline void PGMC_CPC_CACHE_DisableLowPower(PGMC_CPC_Type *base)

Disables low power mode control, so the cache will not be affected by any low power modes.

Parameters:

• base – CPC CACHE module base address.

void PGMC_CPC_CACHE_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base)

Requests CPC cache module’s memory low power level change by software mode.

Note

If request memory low power level change, must wait the MLPL transition complete.

Parameters:

• base – CPC LMEM module base address.

void PGMC_CPC_LMEM_ControlByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode, pgmc_memory_low_power_level_t memoryLowPowerLevel)

Makes the CPC LMEM module controlled by the target CPU power mode, such as Wait mode.

This function makes the module controlled by four typical CPU power modes, it also can set memory low power level.

Parameters:

• base – CPC LMEM module base address.

• mode – Target CPU power mode.

• memoryLowPowerLevel – Memory low power level.

void PGMC_CPC_LMEM_ControlBySetPointMode(PGMC_CPC_Type *base, uint32_t setPointMap, pgmc_memory_low_power_level_t memoryLowPowerLevel)

Makes the CPC LMEM module controlled by the target set points.

This function makes the module controlled by specific set point, It also supports set memory lowe power level.

Note

When setting more than one set point, use “|” between the map values in _pgmc_setpoint_map.

Parameters:

• base – CPC LMEM module base address.

• setPointMap – Should be the OR’ed value of _pgmc_setpoint_map.

• memoryLowPowerLevel – Memory low power level.

static inline void PGMC_CPC_LMEM_DisableLowPower(PGMC_CPC_Type *base)

Disables low power mode control, so that the CPC LMEM will not be affected by any low power modes.

Parameters:

• base – CPC LMEM module base address.

void PGMC_CPC_LMEM_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base)

Requests CPC LMEM module’s memory low power level change in software mode.

Note

If request memory low power level change, must wait the MLPL transition complete.

Parameters:

• base – CPC LMEM module base address.

static inline void PGMC_CPC_AllowUserModeAccess(PGMC_CPC_Type *base, bool enable)

Allows user mode access or not for the CPC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – CPC LMEM module base address.

• enable – Used to control whether allow user mode access.

  • true Allow both privilege and user mode to access CPU mode control registers.

  • false Allow only privilege mode to access CPU mode control registers.

static inline void PGMC_CPC_AllowNonSecureModeAccess(PGMC_CPC_Type *base, bool enable)

Allows non-secure mode access or not for the CPC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – CPC LMEM module base address.

• enable – Used to control whether allow non-secure mode to access CPU mode control registers.

  • true Allow both secure and non-secure mode to access CPU mode control registers.

  • false Allow only secure mode to access CPU mode control registers.

static inline void PGMC_CPC_LockAccessSetting(PGMC_CPC_Type *base)

Locks access related settings, including secure access setting and user access setting, for the CPC module.

Note

This function used to lock access related settings. After locked the related bit field can not be written unless POR.

Parameters:

• base – CPC LMEM module base address.

static inline void PGMC_CPC_SetDomainIdWhiteList(PGMC_CPC_Type *base, uint8_t domainId)

Sets the corrsponding domain ID that can access CPU mode control registers for the CPC module.

Note

If the domain ID whitelist is locked, the setting via this function is useless.

Parameters:

• base – CPC LMEM module base address.

• domainId – Should be the OR’ed value of pgmc_bpc_assign_domain_t.

static inline void PGMC_CPC_LockDomainIDWhiteList(PGMC_CPC_Type *base)

Locks the value of Domain ID white list for CPC module.

Note

After locked the domain ID white list can not be written again unless POR.

Parameters:

• base – CPC LMEM module base address.

static inline void PGMC_CPC_LockLowPowerConfigurationFields(PGMC_CPC_Type *base)

Locks CPC realted low power configuration fields for CPC module.

Note

After locked the low power configurations fields can not be updated unless POR.

Parameters:

• base – CPC LMEM module base address.

void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask)

Sets the behaviour of each signal in MIF, such as Sleep signal.

Note

To control the memory low power operation, this function must be invoked after selecting the memory low power level. Use case:

PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC0_BASE, kPGMC_WaitMode, kPGMC_CM7Core,
    kPGMC_MLPLSleep, false);
PGMC_MIF_SetSignalBehaviour(PGMC_BPC0_MIF_BASE, kPGMC_MLPLSleep, kPGMC_AssertSleepSignal);

Parameters:

• base – PGMC MIF peripheral base address.

• memoryLevel – The selected memory low power level. For details please refer to pgmc_memory_low_power_level_t.

• mask – The mask of MIF signal behaviour. Should be the OR’ed value of _pgmc_mif_signal_behaviour

static inline void PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type *base)

Locks MIF realted low power configuration fields for MIF module.

Note

After locked the low power configurations fields can not be updated unless POR.

Parameters:

• base – PGMC MIF peripheral base address.

static inline void PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type *base, bool enable)

Trigger PMIC standby ON/OFF.

Parameters:

• base – PMIC module base address.

• enable – Trigger on/off PMIC standby.

  • true Trigger PMIC standby ON.

  • false Trigger PMIC standby OFF.

void PGMC_PPC_ControlByCpuPowerMode(PGMC_PPC_Type *base, pgmc_cpu_mode_t mode)

Makes the PMIC module controlled by the target CPU power mode, such as Wait mode.

Parameters:

• base – PMIC module base address.

• mode – Target CPU power mode.

void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby)

Makes the PMIC module controlled by the target set points.

This function makes the module controlled by specific set point, It also supports PMIC standby on.

Note

When setting more than one set point, use “|” between the map values in _pgmc_setpoint_map.

Parameters:

• base – PMIC module base address.

• setPointMap – Should be the OR’ed value of _pgmc_setpoint_map.

• enableStandby – true: PMIC standby on when system enters set point number and system is in standby mode. false: PMIC standby on when system enters set point number

static inline void PGMC_PPC_DisableLowPower(PGMC_PPC_Type *base)

Disables low power mode control.

Parameters:

• base – PMIC module bsase address.

static inline void PGMC_PPC_AllowUserModeAccess(PGMC_PPC_Type *base, bool enable)

Allows user mode access or not for PMIC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – PMIC module base address.

• enable – Used to control whether allow user mode access.

  • true Allow both privilege and user mode to access CPU mode control registers.

  • false Allow only privilege mode to access CPU mode control registers.

static inline void PGMC_PPC_AllowNonSecureModeAccess(PGMC_PPC_Type *base, bool enable)

Allows non-secure mode access or not for the PMIC module.

Note

If locked access related settings, the setting via this function is useless.

Parameters:

• base – PMIC module base address.

• enable – Used to control whether allow non-secure mode to access CPU mode control registers.

  • true Allow both secure and non-secure mode to access CPU mode control registers.

  • false Allow only secure mode to access CPU mode control registers.

static inline void PGMC_PPC_LockAccessSetting(PGMC_PPC_Type *base)

Locks access related settings, including secure access setting and user access setting, for the PMIC module.

Note

This function used to lock access related settings. After locked the related bit field can not be written unless POR.

Parameters:

• base – PMIC module base address.

static inline void PGMC_PPC_SetDomainIdWhiteList(PGMC_PPC_Type *base, uint8_t domainId)

Sets the corrsponding domain ID that can access CPU mode control registers for the PMIC module.

Note

If the domain ID whitelist is locked, the setting via this function is useless.

Parameters:

• base – PMIC module base address.

• domainId – Should be the OR’ed value of pgmc_bpc_assign_domain_t.

static inline void PGMC_PPC_LockDomainIDWhiteList(PGMC_PPC_Type *base)

Locks the value of Domain ID white list for the PMIC module.

Note

After locked the domain ID white list can not be written again unless POR.

Parameters:

• base – PMIC module base address.

static inline void PGMC_PPC_LockLowPowerConfigurationFields(PGMC_PPC_Type *base)

Locks low power configuration fields for the PMIC module.

Note

After locked the low power configurations fields can not be updated unless POR.

Parameters:

• base – PMIC module base address.

struct _pgmc_bpc_cpu_power_mode_option

#include <fsl_pgmc.h>

The control option of the power domain controlled by CPU power mode.

Public Members

pgmc_bpc_assign_domain_t assignDomain

Domain assignment of the BPC. The power mode of the selected core domain will control the selected power domain.

bool stateSave

Request save the state of power domain before entering target power mode.

• true Save data when domain enter the selected mode.

• false Do not save data when domain enter the selected mode.

bool powerOff

Request power off the power domain.

• true Power off the power domain when enter the selected mode.

• false Do not power off the power domain when enter the selected mode.

struct _pgmc_bpc_setpoint_mode_option

#include <fsl_pgmc.h>

The control option of the power domain controlled by setpoint mode.

Public Members

bool stateSave

Request save the state of power domain before entering target setpoint.

• true Save data when domain enter the selected setpoint.

• false Do not save data when domain enter the selected setpoint.

bool powerOff

Request power off the power domain.

• true Power off the power domain when enter the selected setpoint.

• false Do not power off the power domain when enter the selected setpoint.

PIT: Periodic Interrupt Timer

void PIT_Init(PIT_Type *base, const pit_config_t *config)

Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.

Note

This API should be called at the beginning of the application using the PIT driver.

Parameters:

• base – PIT peripheral base address

• config – Pointer to the user’s PIT config structure

void PIT_Deinit(PIT_Type *base)

Gates the PIT clock and disables the PIT module.

Parameters:

• base – PIT peripheral base address

static inline void PIT_GetDefaultConfig(pit_config_t *config)

Fills in the PIT configuration structure with the default settings.

The default values are as follows.

config->enableRunInDebug = false;

Parameters:

• config – Pointer to the configuration structure.

static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable)

Enables or disables chaining a timer with the previous timer.

When a timer has a chain mode enabled, it only counts after the previous timer has expired. If the timer n-1 has counted down to 0, counter n decrements the value by one. Each timer is 32-bits, which allows the developers to chain timers together and form a longer timer (64-bits and larger). The first timer (timer 0) can’t be chained to any other timer.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number which is chained with the previous timer

• enable – Enable or disable chain. true: Current timer is chained with the previous timer. false: Timer doesn’t chain with other timers.

static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)

Enables the selected PIT interrupts.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

• mask – The interrupts to enable. This is a logical OR of members of the enumeration pit_interrupt_enable_t

static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)

Disables the selected PIT interrupts.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

• mask – The interrupts to disable. This is a logical OR of members of the enumeration pit_interrupt_enable_t

static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel)

Gets the enabled PIT interrupts.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration pit_interrupt_enable_t

static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel)

Gets the PIT status flags.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

Returns:

The status flags. This is the logical OR of members of the enumeration pit_status_flags_t

static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask)

Clears the PIT status flags.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

• mask – The status flags to clear. This is a logical OR of members of the enumeration pit_status_flags_t

static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count)

Sets the timer period in units of count.

Timers begin counting from the value set by this function until it reaches 0, then it generates an interrupt and load this register value again. Writing a new value to this register does not restart the timer. Instead, the value is loaded after the timer expires.

Note

Users can call the utility macros provided in fsl_common.h to convert to ticks.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

• count – Timer period in units of ticks

static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel)

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number

Returns:

Current timer counting value in ticks

static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel)

Starts the timer counting.

After calling this function, timers load period value, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number.

static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel)

Stops the timer counting.

This function stops every timer counting. Timers reload their periods respectively after the next time they call the PIT_DRV_StartTimer.

Parameters:

• base – PIT peripheral base address

• channel – Timer channel number.

FSL_PIT_DRIVER_VERSION

PIT Driver Version 2.0.5.

enum _pit_chnl

List of PIT channels.

Note

Actual number of available channels is SoC dependent

Values:

enumerator kPIT_Chnl_0

PIT channel number 0

enumerator kPIT_Chnl_1

PIT channel number 1

enumerator kPIT_Chnl_2

PIT channel number 2

enumerator kPIT_Chnl_3

PIT channel number 3

enum _pit_interrupt_enable

List of PIT interrupts.

Values:

enumerator kPIT_TimerInterruptEnable

Timer interrupt enable

enum _pit_status_flags

List of PIT status flags.

Values:

enumerator kPIT_TimerFlag

Timer flag

typedef enum _pit_chnl pit_chnl_t

List of PIT channels.

Note

Actual number of available channels is SoC dependent

typedef enum _pit_interrupt_enable pit_interrupt_enable_t

List of PIT interrupts.

typedef enum _pit_status_flags pit_status_flags_t

List of PIT status flags.

typedef struct _pit_config pit_config_t

PIT configuration structure.

This structure holds the configuration settings for the PIT peripheral. To initialize this structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a pointer to your config structure instance.

The configuration structure can be made constant so it resides in flash.

uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)

Reads the current lifetime counter value.

The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. The period of lifetime timer is equal to the “period of timer 0 * period of timer 1”. For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit has the value of timer 0.

Parameters:

• base – PIT peripheral base address

Returns:

Current lifetime timer value

struct _pit_config

#include <fsl_pit.h>

PIT configuration structure.

This structure holds the configuration settings for the PIT peripheral. To initialize this structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a pointer to your config structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableRunInDebug

true: Timers run in debug mode; false: Timers stop in debug mode

Pmu

void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)

Selects the control mode of the PLL LDO.

Parameters:

• base – PMU peripheral base address.

• mode – The control mode of the PLL LDO. Please refer to pmu_control_mode_t.

void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base)

Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode.

Parameters:

• base – PMU peripheral base address.

void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base)

Enables PLL LDO via AI interface in Static/Software mode.

Parameters:

• base – PMU peripheral base address.

void PMU_StaticDisablePllLdo(void)

Disables PLL LDO via AI interface in Static/Software mode.

void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)

Selects the control mode of the LPSR ANA LDO.

Parameters:

• base – PMU peripheral base address.

• mode – The control mode of the LPSR ANA LDO. Please refer to pmu_control_mode_t.

void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable)

Sets the Bypass mode of the LPSR ANA LDO.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

• enable – Enable/Disable bypass mode.

  • true Enable LPSR ANA Bypass mode.

  • false Disable LPSR ANA Bypass mode.

static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)

Checks whether the LPSR ANA LDO is in bypass mode.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

Returns:

The result used to indicates whether the LPSR ANA LDO is in bypass mode.

• true The LPSR ANA LDO is in bypass mode.

• false The LPSR ANA LDO not in bypass mode.

void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config)

Fill the LPSR ANA LDO configuration structure with default settings.

The default values are:

config->mode                   = kPMU_HighPowerMode;
config->enable2mALoad          = true;
config->enable20uALoad         = false;
config->enable4mALoad          = true;
config->enableStandbyMode      = false;
config->driverStrength         = kPMU_LpsrAnaLdoDriverStrength0;
config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable;
config->chargePumpCurrent      = kPMU_LpsrAnaChargePump300nA;
config->outputRange            = kPMU_LpsrAnaLdoOutputFrom1P77To1P83;

Parameters:

• config – Pointer to the structure pmu_static_lpsr_ana_ldo_config_t.

void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config)

Initialize the LPSR ANA LDO in Static/Sofware Mode.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

• config – Pointer to the structure pmu_static_lpsr_ana_ldo_config_t.

void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base)

Disable the output of LPSR ANA LDO.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)

Selects the control mode of the LPSR DIG LDO.

Parameters:

• base – PMU peripheral base address.

• mode – The control mode of the LPSR DIG LDO. Please refer to pmu_control_mode_t.

void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable)

Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

• enable –

  • true Turns on Bypass mode of the LPSR DIG LDO.

  • false Turns off Bypass mode of the LPSR DIG LDO.

static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)

Checks whether the LPSR DIG LDO is in bypass mode.

Parameters:

• base – PMU peripheral base address.

Returns:

The result used to indicates whether the LPSR DIG LDO is in bypass mode.

• true The LPSR DIG LDO is in bypass mode.

• false The LPSR DIG LDO not in bypass mode.

void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config)

Gets the default configuration of LPSR DIG LDO.

The default values are:

config->enableStableDetect = false;
config->voltageStepTime    = kPMU_LpsrDigVoltageStepInc50us;
config->brownOutConfig     = kPMU_LpsrDigBrownOutDisable;
config->targetVoltage      = kPMU_LpsrDigTargetStableVoltage1P0V;
config->mode               = kPMU_HighPowerMode;

Parameters:

• config – Pointer to the structure pmu_static_lpsr_dig_config_t.

void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config)

Initialize the LPSR DIG LDO in static mode.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

• config – Pointer to the structure pmu_static_lpsr_dig_config_t.

void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base)

Disable the LPSR DIG LDO.

Parameters:

• base – ANADIG_LDO_SNVS peripheral base address.

void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue)

Sets the voltage step of LPSR DIG LDO in certain setpoint during GPC mode.

Note

The function provides the feature to set the voltage step to different setpoints.

Parameters:

• setpointMap – The map of setpoints should be the OR’ed Value of _pmu_setpoint_map.

• voltageValue – The voltage step to be set. See enumeration pmu_lpsr_dig_target_output_voltage_t.

void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config)

Gets the default config of the SNVS DIG LDO.

The default values are:

config->mode                   = kPMU_LowPowerMode;
config->chargePumpCurrent      = kPMU_SnvsDigChargePump12P5nA;
config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K;
config->trimValue              = 0U;
config->enablePullDown         = true;
config->enableLdoStable        = false;

Parameters:

• config – Pointer to pmu_snvs_dig_config_t.

void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode)

Initialize the SNVS DIG LDO.

Parameters:

• base – LDO SNVS DIG peripheral base address.

• mode – Used to control LDO power mode, please refer to pmu_ldo_operate_mode_t.

static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base)

Disable SNVS DIG LDO.

void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap)

Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected ldo. Please see enumeration pmu_ldo_name_t for details.

• setpointMap – The map of setpoints should be the OR’ed Value of _pmu_setpoint_map, 1b’1 means enable specific ldo in that setpoint. For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable PLL LDO in other setpoint.

void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode)

Sets the operating mode of the selected LDO in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected ldo. Please see enumeration pmu_ldo_name_t for details.

• setpointMap – The map of setpoints should be the OR’ed Value of _pmu_setpoint_map.

• mode – The operating mode of the selected ldo. Please refer to enumeration pmu_ldo_operate_mode_t for details.

void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap)

Controls the ON/OFF of the selected LDOs’ Tracking mode in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected ldo. Please see enumeration pmu_ldo_name_t for details.

• setpointMap – The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap)

Controls the ON/OFF of the selected LDOs’ Bypass mode in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected ldo. Please see enumeration pmu_ldo_name_t for details.

• setpointMap – The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap)

When STBY assert, enable/disable the selected LDO enter it’s Low power mode.

Parameters:

• name – The name of the selected ldo. Please see enumeration pmu_ldo_name_t for details.

• setpointMap – The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY assert, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)

Selects the control mode of the Bandgap Reference.

Parameters:

• base – PMU peripheral base address.

• mode – The control mode of the Bandgap Reference. Please refer to pmu_control_mode_t.

void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base)

Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode.

Parameters:

• base – PMU peripheral base address.

void PMU_DisableBandgapSelfBiasAfterPowerUp(void)

Disables Bandgap self bias for best noise performance.

This function should be invoked after powering up. This function will wait for the bandgap stable and disable the bandgap self bias. After powering up, it need to wait for the bandgap to get stable and then disable Bandgap Self bias for best noise performance.

void PMU_EnableBandgapSelfBiasBeforePowerDown(void)

Enables Bandgap self bias before power down.

This function will enable Bandgap self bias feature before powering down or there will be risk of Bandgap not starting properly.

void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config)

Initialize Bandgap.

Parameters:

• config – Pointer to the structure pmu_static_bandgap_config_t.

static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap)

Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode.

For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in setpoint0 and setpoint1 and disable bandgap in other setpoints.

Parameters:

• base – PMU peripheral base address.

• setpointMap – The map of setpoints that the bandgap will be enabled in those setpoints, this parameter should be the OR’ed Value of _pmu_setpoint_map.

static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap)

Controls the ON/OFF of the Bandgap’s Standby mode in certain setpoints with GPC mode.

Parameters:

• base – PMU peripheral base address.

• setpointMap – The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config)

Configures Well bias, such as power source, clock source and so on.

Parameters:

• base – PMU peripheral base address.

• config – Pointer to the pmu_well_bias_config_t structure.

void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config)

Gets the default configuration of well bias.

Parameters:

• config – The pointer to the pmu_well_bias_config_t structure.

void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode)

Selects the control mode of the Body Bias.

Parameters:

• base – PMU peripheral base address.

• name – The name of the body bias. Please refer to pmu_body_bias_name_t.

• mode – The control mode of the Body Bias. Please refer to pmu_control_mode_t.

void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable)

Enables/disables the selected body bias.

Parameters:

• base – PMU peripheral base address.

• name – The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t.

• enable – Used to turn on/off the specific body bias.

  • true Enable the selected body bias.

  • false Disable the selected body bias.

void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap)

Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected body bias. Please see enumeration pmu_body_bias_name_t for details.

• setpointMap – The map of setpoints that the specific body bias will be enabled in those setpoints, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap)

Controls the ON/OFF of the selected Body Bias’ Wbias power switch in certain setpoints with GPC mode.

Parameters:

• name – The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.

• setpointMap – The map of setpoints that the specific body bias’s wbias power switch will be turn on in those setpoints, this value should be the OR’ed Value of _pmu_setpoint_map.

void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config)

Gets the default config of body bias in GPC mode.

Parameters:

• config – Pointer to structure pmu_gpc_body_bias_config_t.

void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config)

Sets the config of the selected Body Bias in GPC mode.

Parameters:

• name – The name of the selected body bias. Please see enumeration pmu_body_bias_name_t for details.

• config – Pointer to structure pmu_gpc_body_bias_config_t.

FSL_PMU_DRIVER_VERSION

PMU driver version.

Version 2.1.2.

enum _pmu_setpoint_map

System setpoints enumeration.

Values:

enumerator kPMU_SetPoint0

Set point 0.

enumerator kPMU_SetPoint1

Set point 1.

enumerator kPMU_SetPoint2

Set point 2.

enumerator kPMU_SetPoint3

Set point 3.

enumerator kPMU_SetPoint4

Set point 4.

enumerator kPMU_SetPoint5

Set point 5.

enumerator kPMU_SetPoint6

Set point 6.

enumerator kPMU_SetPoint7

Set point 7.

enumerator kPMU_SetPoint8

Set point 8.

enumerator kPMU_SetPoint9

Set point 9.

enumerator kPMU_SetPoint10

Set point 10.

enumerator kPMU_SetPoint11

Set point 11.

enumerator kPMU_SetPoint12

Set point 12.

enumerator kPMU_SetPoint13

Set point 13.

enumerator kPMU_SetPoint14

Set point 14.

enumerator kPMU_SetPoint15

Set point 15.

enum _pmu_ldo_name

The name of LDOs.

Values:

enumerator kPMU_PllLdo

The PLL LDO in SOC domain.

enumerator kPMU_LpsrAnaLdo

The LPSR ANA LDO in LPSR domain.

enumerator kPMU_LpsrDigLdo

The LPSR DIG LDO in LPSR domain.

enumerator kPMU_SnvsDigLdo

The SNVS DIG LDO in SNVS domain.

enum _pmu_body_bias_name

The name of body bias.

Values:

enumerator kPMU_RBB_SOC

The RBB implemented in SOC.

enumerator kPMU_RBB_LPSR

The RBB implemented in LPSRMIX.

enum _pmu_control_mode

The control mode of LDOs/Bandgaps/Body Bias.

Values:

enumerator kPMU_StaticMode

Static/Software Control mode.

enumerator kPMU_GPCMode

GPC/Hardware Control mode.

enum _pmu_ldo_operate_mode

The operation mode for the LDOs.

Values:

enumerator kPMU_LowPowerMode

LDOs operate in Low power mode.

enumerator kPMU_HighPowerMode

LDOs operate in High power mode.

enum _pmu_lpsr_ana_ldo_charge_pump_current

The enumeration of LPSR ANA LDO’s charge pump current.

Values:

enumerator kPMU_LpsrAnaChargePump300nA

The current of the charge pump is selected as 300nA.

enumerator kPMU_LpsrAnaChargePump400nA

The current of the charge pump is selected as 400nA.

enumerator kPMU_LpsrAnaChargePump500nA

The current of the charge pump is selected as 500nA.

enumerator kPMU_LpsrAnaChargePump600nA

The current of the charge pump is selected as 600nA.

enum _pmu_lpsr_ana_ldo_output_range

The enumeration of LPSR ANA LDO’s output range.

Values:

enumerator kPMU_LpsrAnaLdoOutputFrom1P77To1P83

The output voltage varies from 1.77V to 1.83V.

enumerator kPMU_LpsrAnaLdoOutputFrom1P72To1P77

The output voltage varies from 1.72V to 1.77V.

enumerator kPMU_LpsrAnaLdoOutputFrom1P82To1P88

The output voltage varies from 1.82V to 1.88V.

enum _pmu_lpsr_dig_voltage_step_time

The enumeration of voltage step time for LPSR DIG LDO.

Values:

enumerator kPMU_LpsrDigVoltageStepInc15us

LPSR DIG LDO voltage step time selected as 15us.

enumerator kPMU_LpsrDigVoltageStepInc25us

LPSR DIG LDO voltage step time selected as 25us.

enumerator kPMU_LpsrDigVoltageStepInc50us

LPSR DIG LDO voltage step time selected as 50us.

enumerator kPMU_LpsrDigVoltageStepInc100us

LPSR DIG LDO voltage step time selected as 100us.

enum _pmu_lpsr_dig_target_output_voltage

The target output voltage of LPSR DIG LDO.

Values:

enumerator kPMU_LpsrDigTargetStableVoltage0P631V

The target voltage selected as 0.631V

enumerator kPMU_LpsrDigTargetStableVoltage0P65V

The target voltage selected as 0.65V

enumerator kPMU_LpsrDigTargetStableVoltage0P67V

The target voltage selected as 0.67V

enumerator kPMU_LpsrDigTargetStableVoltage0P689V

The target voltage selected as 0.689V

enumerator kPMU_LpsrDigTargetStableVoltage0P709V

The target voltage selected as 0.709V

enumerator kPMU_LpsrDigTargetStableVoltage0P728V

The target voltage selected as 0.728V

enumerator kPMU_LpsrDigTargetStableVoltage0P748V

The target voltage selected as 0.748V

enumerator kPMU_LpsrDigTargetStableVoltage0P767V

The target voltage selected as 0.767V

enumerator kPMU_LpsrDigTargetStableVoltage0P786V

The target voltage selected as 0.786V

enumerator kPMU_LpsrDigTargetStableVoltage0P806V

The target voltage selected as 0.806V

enumerator kPMU_LpsrDigTargetStableVoltage0P825V

The target voltage selected as 0.825V

enumerator kPMU_LpsrDigTargetStableVoltage0P845V

The target voltage selected as 0.845V

enumerator kPMU_LpsrDigTargetStableVoltage0P864V

The target voltage selected as 0.864V

enumerator kPMU_LpsrDigTargetStableVoltage0P883V

The target voltage selected as 0.883V

enumerator kPMU_LpsrDigTargetStableVoltage0P903V

The target voltage selected as 0.903V

enumerator kPMU_LpsrDigTargetStableVoltage0P922V

The target voltage selected as 0.922V

enumerator kPMU_LpsrDigTargetStableVoltage0P942V

The target voltage selected as 0.942V

enumerator kPMU_LpsrDigTargetStableVoltage0P961V

The target voltage selected as 0.961V

enumerator kPMU_LpsrDigTargetStableVoltage0P981V

The target voltage selected as 0.981V

enumerator kPMU_LpsrDigTargetStableVoltage1P0V

The target voltage selected as 1.0V

enumerator kPMU_LpsrDigTargetStableVoltage1P019V

The target voltage selected as 1.019V

enumerator kPMU_LpsrDigTargetStableVoltage1P039V

The target voltage selected as 1.039V

enumerator kPMU_LpsrDigTargetStableVoltage1P058V

The target voltage selected as 1.058V

enumerator kPMU_LpsrDigTargetStableVoltage1P078V

The target voltage selected as 1.078V

enumerator kPMU_LpsrDigTargetStableVoltage1P097V

The target voltage selected as 1.097V

enumerator kPMU_LpsrDigTargetStableVoltage1P117V

The target voltage selected as 1.117V

enumerator kPMU_LpsrDigTargetStableVoltage1P136V

The target voltage selected as 1.136V

enumerator kPMU_LpsrDigTargetStableVoltage1P155V

The target voltage selected as 1.155V

enumerator kPMU_LpsrDigTargetStableVoltage1P175V

The target voltage selected as 1.175V

enumerator kPMU_LpsrDigTargetStableVoltage1P194V

The target voltage selected as 1.194V

enumerator kPMU_LpsrDigTargetStableVoltage1P214V

The target voltage selected as 1.214V

enumerator kPMU_LpsrDigTargetStableVoltage1P233V

The target voltage selected as 1.233V

enum _pmu_snvs_dig_charge_pump_current

The enumeration of the SNVS DIG LDO’s charge pump current.

Values:

enumerator kPMU_SnvsDigChargePump12P5nA

The current of SNVS DIG LDO’s charge pump is selected as 12.5nA.

enumerator kPMU_SnvsDigChargePump6P25nA

The current of SNVS DIG LDO’s charge pump is selected as 6.25nA.

enumerator kPMU_SnvsDigChargePump18P75nA

The current of SNVS DIG LDO’s charge pump is selected as 18.75nA.

enum _pmu_snvs_dig_discharge_resistor_value

The enumeration of the SNVS DIG LDO’s discharge resistor.

Values:

enumerator kPMU_SnvsDigDischargeResistor15K

The Discharge Resistor is selected as 15K ohm

enumerator kPMU_SnvsDigDischargeResistor30K

The Discharge Resistor is selected as 30K ohm

enumerator kPMU_SnvsDigDischargeResistor9K

The Discharge Resistor is selected as 9K ohm

enum _pmu_static_bandgap_power_down_option

The enumeration of bandgap power down option.

Values:

enumerator kPMU_PowerDownBandgapFully

Fully power down the bandgap module.

enumerator kPMU_PowerDownVoltageReferenceOutputOnly

Power down only the reference output section of the bandgap

enumerator kPMU_PowerDownBandgapVBGUPDetector

Power down the VBGUP detector of the bandgap without affecting any additional functionality.

enum _pmu_bandgap_output_VBG_voltage_value

The enumeration of output VBG voltage.

Values:

enumerator kPMU_BandgapOutputVBGVoltageNominal

Output nominal voltage.

enumerator kPMU_BandgapOutputVBGVoltagePlus10mV

Output VBG voltage Plus 10mV.

enumerator kPMU_BandgapOutputVBGVoltagePlus20mV

Output VBG voltage Plus 20mV.

enumerator kPMU_BandgapOutputVBGVoltagePlus30mV

Output VBG voltage Plus 30mV.

enumerator kPMU_BandgapOutputVBGVoltageMinus10mV

Output VBG voltage Minus 10mV.

enumerator kPMU_BandgapOutputVBGVoltageMinus20mV

Output VBG voltage Minus 20mV.

enumerator kPMU_BandgapOutputVBGVoltageMinus30mV

Output VBG voltage Minus 30mV.

enumerator kPMU_BandgapOutputVBGVoltageMinus40mV

Output VBG voltage Minus 40mV.

enum _pmu_bandgap_output_current_value

The enumeration of output current.

Values:

enumerator kPMU_OutputCurrent11P5uA

Output 11.5uA current from the bandgap.

enumerator kPMU_OutputCurrent11P8uA

Output 11.8uA current from the bandgap.

enumerator kPMU_OutputCurrent12P1uA

Output 12.1uA current from the bandgap.

enumerator kPMU_OutputCurrent12P4uA

Output 12.4uA current from the bandgap.

enumerator kPMU_OutputCurrent12P7uA

Output 12.7uA current from the bandgap.

enumerator kPMU_OutputCurrent13P0uA

Output 13.0uA current from the bandgap.

enumerator kPMU_OutputCurrent13P3uA

Output 13.3uA current from the bandgap.

enum _pmu_well_bias_power_source

The enumerator of well bias power source.

Values:

enumerator kPMU_WellBiasPowerFromLpsrDigLdo

LPSR Dig LDO supplies the power stage and NWELL sampler.

enumerator kPMU_WellBiasPowerFromDCDC

DCDC supplies the power stage and NWELL sampler.

enum _pmu_bias_area_size

The enumerator of bias area size.

Values:

enumerator kPMU_180uA_6mm2At125C

Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C

enumerator kPMU_150uA_5mm2At125C

Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C

enumerator kPMU_120uA_4mm2At125C

Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C

enumerator kPMU_90uA_3mm2At125C

Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C

enumerator kPMU_60uA_2mm2At125C

Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C

enumerator kPMU_45uA_1P5mm2At125C

Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C

enumerator kPMU_30uA_1mm2At125C

Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C

enumerator kPMU_15uA_0P5mm2At125C

Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C

enum _pmu_well_bias_typical_freq

The enumerator of well bias typical frequency.

Values:

enumerator kPMU_OscFreqDiv128

Typical frequency = osc_freq / 128.

enumerator kPMU_OscFreqDiv64

Typical frequency = osc_freq / 64.

enumerator kPMU_OscFreqDiv32

Typical frequency = osc_freq / 32.

enumerator kPMU_OscFreqDiv16

Typical frequency = osc_freq / 16.

enumerator kPMU_OscFreqDiv8

Typical frequency = osc_freq / 8.

enumerator kPMU_OscFreqDiv2

Typical frequency = osc_freq / 2.

enumerator kPMU_OscFreq

Typical frequency = oscillator frequency.

enum _pmu_adaptive_clock_source

The enumerator of well bias adaptive clock source.

Values:

enumerator kPMU_AdaptiveClkSourceOscClk

The adaptive clock source is oscillator clock.

enumerator kPMU_AdaptiveClkSourceChargePumpClk

The adaptive clock source is charge pump clock.

enum _pmu_freq_reduction

The enumerator of frequency reduction due to cap increment.

Values:

enumerator kPMU_FreqReductionNone

No frequency reduction.

enumerator kPMU_FreqReduction30PCT

30% frequency reduction due to cap increment.

enumerator kPMU_FreqReduction40PCT

40% frequency reduction due to cap increment.

enumerator kPMU_FreqReduction50PCT

50% frequency reduction due to cap increment.

enum _pmu_well_bias_1P8_adjustment

The enumerator of well bias 1P8 adjustment.

Values:

enumerator kPMU_Cref0fFCspl0fFDeltaC0fF

Cref = 0fF, Cspl = 0fF, DeltaC = 0fF.

enumerator kPMU_Cref0fFCspl30fFDeltaCN30fF

Cref = 0fF, Cspl = 30fF, DeltaC = -30fF.

enumerator kPMU_Cref0fFCspl43fFDeltaCN43fF

Cref = 0fF, Cspl = 43fF, DeltaC = -43fF.

enumerator kPMU_Cref0fFCspl62fFDeltaCN62fF

Cref = 0fF, Cspl = 62fF, DeltaC = -62fF.

enumerator kPMU_Cref0fFCspl105fFDeltaCN105fF

Cref = 0fF, Cspl = 105fF, DeltaC = -105fF.

enumerator kPMU_Cref30fFCspl0fFDeltaC30fF

Cref = 30fF, Cspl = 0fF, DeltaC = 30fF.

enumerator kPMU_Cref30fFCspl43fFDeltaCN12fF

Cref = 30fF, Cspl = 43fF, DeltaC = -12fF.

enumerator kPMU_Cref30fFCspl105fFDeltaCN75fF

Cref = 30fF, Cspl = 105fF, DeltaC = -75fF.

enumerator kPMU_Cref43fFCspl0fFDeltaC43fF

Cref = 43fF, Cspl = 0fF, DeltaC = 43fF.

enumerator kPMU_Cref43fFCspl30fFDeltaC13fF

Cref = 43fF, Cspl = 30fF, DeltaC = 13fF.

enumerator kPMU_Cref43fFCspl62fFDeltaCN19fF

Cref = 43fF, Cspl = 62fF, DeltaC = -19fF.

enumerator kPMU_Cref62fFCspl0fFDeltaC62fF

Cref = 62fF, Cspl = 0fF, DeltaC = 62fF.

enumerator kPMU_Cref62fFCspl43fFDeltaC19fF

Cref = 62fF, Cspl = 43fF, DeltaC = 19fF.

enumerator kPMU_Cref105fFCspl0fFDeltaC105fF

Cref = 105fF, Cspl = 0fF, DeltaC = 105fF.

enumerator kPMU_Cref105fFCspl30fFDeltaC75fF

Cref = 105fF, Cspl = 30fF, DeltaC = 75fF.

typedef enum _pmu_ldo_name pmu_ldo_name_t

The name of LDOs.

typedef enum _pmu_body_bias_name pmu_body_bias_name_t

The name of body bias.

typedef enum _pmu_control_mode pmu_control_mode_t

The control mode of LDOs/Bandgaps/Body Bias.

typedef enum _pmu_ldo_operate_mode pmu_ldo_operate_mode_t

The operation mode for the LDOs.

typedef enum _pmu_lpsr_ana_ldo_charge_pump_current pmu_lpsr_ana_ldo_charge_pump_current_t

The enumeration of LPSR ANA LDO’s charge pump current.

typedef enum _pmu_lpsr_ana_ldo_output_range pmu_lpsr_ana_ldo_output_range_t

The enumeration of LPSR ANA LDO’s output range.

typedef enum _pmu_lpsr_dig_voltage_step_time pmu_lpsr_dig_voltage_step_time_t

The enumeration of voltage step time for LPSR DIG LDO.

typedef enum _pmu_lpsr_dig_target_output_voltage pmu_lpsr_dig_target_output_voltage_t

The target output voltage of LPSR DIG LDO.

typedef enum _pmu_snvs_dig_charge_pump_current pmu_snvs_dig_charge_pump_current_t

The enumeration of the SNVS DIG LDO’s charge pump current.

typedef enum _pmu_snvs_dig_discharge_resistor_value pmu_snvs_dig_discharge_resistor_value_t

The enumeration of the SNVS DIG LDO’s discharge resistor.

typedef enum _pmu_bandgap_output_VBG_voltage_value pmu_bandgap_output_VBG_voltage_value_t

The enumeration of output VBG voltage.

typedef enum _pmu_bandgap_output_current_value pmu_bandgap_output_current_value_t

The enumeration of output current.

typedef enum _pmu_well_bias_power_source pmu_well_bias_power_source_t

The enumerator of well bias power source.

typedef enum _pmu_bias_area_size pmu_bias_area_size_t

The enumerator of bias area size.

typedef enum _pmu_well_bias_typical_freq pmu_well_bias_typical_freq_t

The enumerator of well bias typical frequency.

typedef enum _pmu_adaptive_clock_source pmu_adaptive_clock_source_t

The enumerator of well bias adaptive clock source.

typedef enum _pmu_freq_reduction pmu_freq_reduction_t

The enumerator of frequency reduction due to cap increment.

typedef enum _pmu_well_bias_1P8_adjustment pmu_well_bias_1P8_adjustment_t

The enumerator of well bias 1P8 adjustment.

typedef struct _pmu_static_lpsr_ana_ldo_config pmu_static_lpsr_ana_ldo_config_t

LPSR ANA LDO config.

typedef struct _pmu_static_lpsr_dig_config pmu_static_lpsr_dig_config_t

LPSR DIG LDO Config in Static/Software Mode.

typedef struct _pmu_snvs_dig_config pmu_snvs_dig_config_t

SNVS DIG LDO config.

typedef struct _pmu_static_bandgap_config pmu_static_bandgap_config_t

Bandgap config in static mode.

typedef union _pmu_well_bias_option pmu_well_bias_option_t

The union of well bias basic options, such as clock source, power source and so on.

typedef struct _pmu_well_bias_config pmu_well_bias_config_t

The structure of well bias configuration.

typedef struct _pmu_gpc_body_bias_config pmu_gpc_body_bias_config_t

The stucture of body bias config in GPC mode.

PMU_HAS_FBB

struct _pmu_static_lpsr_ana_ldo_config

#include <fsl_pmu.h>

LPSR ANA LDO config.

Public Members

pmu_ldo_operate_mode_t mode

The operate mode of LPSR ANA LDO.

bool enable2mALoad

Enable/Disable 2mA load.

• true Enables 2mA loading to prevent overshoot;

• false Disables 2mA loading.

bool enable4mALoad

Enable/Disable 4mA load.

• true Enables 4mA loading to prevent dramatic voltage drop;

• false Disables 4mA load.

bool enable20uALoad

Enable/Disable 20uA load.

• true Enables 20uA loading to prevent overshoot;

• false Disables 20uA load.

bool enableStandbyMode

Enable/Disable Standby Mode.

• true Enables Standby mode, if the STBY assert, the LPSR ANA LDO enter LP mode

• false Disables Standby mode.

struct _pmu_static_lpsr_dig_config

#include <fsl_pmu.h>

LPSR DIG LDO Config in Static/Software Mode.

Public Members

bool enableStableDetect

Enable/Disable Stable Detect.

• true Enables Stable Detect.

• false Disables Stable Detect.

pmu_lpsr_dig_voltage_step_time_t voltageStepTime

Step time.

pmu_lpsr_dig_target_output_voltage_t targetVoltage

The target output voltage.

struct _pmu_snvs_dig_config

#include <fsl_pmu.h>

SNVS DIG LDO config.

Public Members

pmu_ldo_operate_mode_t mode

The operate mode the SNVS DIG LDO.

pmu_snvs_dig_charge_pump_current_t chargePumpCurrent

The current of SNVS DIG LDO’s charge pump current.

pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue

The value of SNVS DIG LDO’s Discharge Resistor.

uint8_t trimValue

The trim value.

bool enablePullDown

Enable/Disable Pull down.

• true Enables the feature of using 1M ohm resistor to discharge the LDO output.

• false Disables the feature of using 1M ohm resistor to discharge the LDO output.

bool enableLdoStable

Enable/Disable SNVS DIG LDO Stable.

struct _pmu_static_bandgap_config

#include <fsl_pmu.h>

Bandgap config in static mode.

Public Members

uint8_t powerDownOption

The OR’ed value of _pmu_static_bandgap_power_down_option. Please refer to _pmu_static_bandgap_power_down_option.

bool enableLowPowerMode

Turn on/off the Low power mode.

• true Turns on the low power operation of the bandgap.

• false Turns off the low power operation of the bandgap.

pmu_bandgap_output_VBG_voltage_value_t outputVoltage

The output VBG voltage of Bandgap.

pmu_bandgap_output_current_value_t outputCurrent

The output current from the bandgap to the temperature sensors.

union _pmu_well_bias_option

#include <fsl_pmu.h>

The union of well bias basic options, such as clock source, power source and so on.

Public Members

uint16_t wellBiasData

well bias configuration data.

struct _pmu_well_bias_option wellBiasStruct

struct _pmu_well_bias_config

#include <fsl_pmu.h>

The structure of well bias configuration.

Public Members

pmu_well_bias_option_t wellBiasOption

Well bias basic function, please refer to pmu_well_bias_option_t.

pmu_well_bias_1P8_adjustment_t adjustment

Well bias adjustment 1P8, please refer to pmu_well_bias_1P8_adjustment_t.

struct _pmu_gpc_body_bias_config

#include <fsl_pmu.h>

The stucture of body bias config in GPC mode.

Public Members

uint8_t PWELLRegulatorSize

The size of the PWELL Regulator.

uint8_t NWELLRegulatorSize

The size of the NWELL Regulator.

uint8_t oscillatorSize

The size of the oscillator bits.

uint8_t regulatorStrength

The strength of the selected regulator.

struct wellBiasStruct

Public Members

uint16_t enablePWellOnly

Turn on both PWELL and NWELL, or only trun on PWELL.

• 1b0 PWELL and NEWLL are both turned on.

• 1b1 PWELL is turned on only.

uint16_t reserved1

Reserved.

uint16_t biasAreaSize

Select size of bias area, please refer to pmu_bias_area_size_t

uint16_t disableAdaptiveFreq

Enable/Disable adaptive frequency.

• 1b0 Frequency change after each half cycle minimum frequency determined by typical frequency.

• 1b1 Adaptive frequency disabled. Frequency determined by typical frequency.

uint16_t wellBiasFreq

Set well bias typical frequency, please refer to pmu_well_bias_typical_freq_t.

uint16_t clkSource

Config the adaptive clock source, please pmu_adaptive_clock_source_t.

uint16_t freqReduction

Config the percent of frequency reduction due to cap increment, please refer to pmu_freq_reduction_t.

uint16_t enablePowerDownOption

Enable/Disable pull down option.

• false Pull down option is disabled.

• true Pull down option is enabled.

uint16_t reserved2

Reserved.

uint16_t powerSource

Set power source, please refer to pmu_well_bias_power_source_t.

uint16_t reserved3

Reserved.

PUF: Physical Unclonable Function

FSL_PUF_DRIVER_VERSION

PUF driver version. Version 2.1.6.

Current version: 2.1.6

Change log:

• 2.0.0

  • Initial version.

• 2.0.1

  • Fixed puf_wait_usec function optimization issue.

• 2.0.2

  • Add PUF configuration structure and support for PUF SRAM controller. Remove magic constants.

• 2.0.3

  • Fix MISRA C-2012 issue.

• 2.1.0

  • Align driver with PUF SRAM controller registers on LPCXpresso55s16.

  • Update initizalition logic .

• 2.1.1

  • Fix ARMGCC build warning .

• 2.1.2

  • Update: Add automatic big to little endian swap for user (pre-shared) keys destinated to secret hardware bus (PUF key index 0).

• 2.1.3

  • Fix MISRA C-2012 issue.

• 2.1.4

  • Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization out delay loop.

• 2.1.5

  • Use common SDK delay in puf_wait_usec()

• 2.1.6

  • Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If this shorter time will also fail, initialization will be tried with worst case time as before.

enum _puf_key_index_register

Values:

enumerator kPUF_KeyIndex_00

enumerator kPUF_KeyIndex_01

enumerator kPUF_KeyIndex_02

enumerator kPUF_KeyIndex_03

enumerator kPUF_KeyIndex_04

enumerator kPUF_KeyIndex_05

enumerator kPUF_KeyIndex_06

enumerator kPUF_KeyIndex_07

enumerator kPUF_KeyIndex_08

enumerator kPUF_KeyIndex_09

enumerator kPUF_KeyIndex_10

enumerator kPUF_KeyIndex_11

enumerator kPUF_KeyIndex_12

enumerator kPUF_KeyIndex_13

enumerator kPUF_KeyIndex_14

enumerator kPUF_KeyIndex_15

enum _puf_min_max

Values:

enumerator kPUF_KeySizeMin

enumerator kPUF_KeySizeMax

enumerator kPUF_KeyIndexMax

enum _puf_key_slot

PUF key slot.

Values:

enumerator kPUF_KeySlot0

PUF key slot 0

enumerator kPUF_KeySlot1

PUF key slot 1

PUF status return codes.

Values:

enumerator kStatus_EnrollNotAllowed

enumerator kStatus_StartNotAllowed

typedef enum _puf_key_index_register puf_key_index_register_t

typedef enum _puf_min_max puf_min_max_t

typedef enum _puf_key_slot puf_key_slot_t

PUF key slot.

PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x)

Get Key Code size in bytes from key size in bytes at compile time.

PUF_MIN_KEY_CODE_SIZE

PUF_ACTIVATION_CODE_SIZE

KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS

KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS

struct puf_config_t

#include <fsl_puf.h>

PWM: Pulse Width Modulator

status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)

Ungates the PWM submodule clock and configures the peripheral for basic operation.

This API should be called at the beginning of the application using the PWM driver. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. When output PWMX in center aligned mode, VAL1 register controls both PWM period and PWMX duty cycle, PWMA and PWMB output will be corrupted. But edge aligned PWMX output do not have such limit. In master reload counter initialization mode, PWM period is depended by period of set LDOK in submodule 0 because this operation will reload register. Submodule 0 counter initialization cannot be master sync or master reload.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• config – Pointer to user’s PWM config structure.

Returns:

kStatus_Success means success; else failed.

void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)

Gate the PWM submodule clock.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to deinitialize

void PWM_GetDefaultConfig(pwm_config_t *config)

Fill in the PWM config struct with the default settings.

The default values are:

config->enableDebugMode = false;
config->enableWait = false;
config->reloadSelect = kPWM_LocalReload;
config->clockSource = kPWM_BusClock;
config->prescale = kPWM_Prescale_Divide_1;
config->initializationControl = kPWM_Initialize_LocalSync;
config->forceTrigger = kPWM_Force_Local;
config->reloadFrequency = kPWM_LoadEveryOportunity;
config->reloadLogic = kPWM_ReloadImmediate;
config->pairOperation = kPWM_Independent;

Parameters:

• config – Pointer to user’s PWM config structure.

status_t PWM_SetupPwm(PWM_Type *base, pwm_submodule_t subModule, const pwm_signal_param_t *chnlParams, uint8_t numOfChnls, pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)

Sets up the PWM signals for a PWM submodule.

The function initializes the submodule according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. Due to edge aligned PWMX is negative true signal, need to configure PWMX active low true level to get correct duty cycle. The half cycle point will not be exactly in the middle of the PWM cycle when PWMX enabled.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• chnlParams – Array of PWM channel parameters to configure the channel(s).

• numOfChnls – Number of channels to configure, this should be the size of the array passed in. Array size should not be more than 3 as each submodule has 3 pins to output PWM.

• mode – PWM operation mode, options available in enumeration pwm_mode_t

• pwmFreq_Hz – PWM signal frequency in Hz

• srcClock_Hz – PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 prescaler value instead of submodule0 source clock.

Returns:

Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise

status_t PWM_SetupPwmPhaseShift(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, uint8_t shiftvalue, bool doSync)

Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• pwmFreq_Hz – PWM signal frequency in Hz

• srcClock_Hz – PWM main counter clock in Hz.

• shiftvalue – Phase shift value, range in 0 ~ 50

• doSync – true: Set LDOK bit for the submodule list; false: LDOK bit don’t set, need to call PWM_SetPwmLdok to sync update.

Returns:

Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise

void PWM_UpdatePwmDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint8_t dutyCyclePercent)

Updates the PWM signal’s dutycycle.

The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmSignal – Signal (PWM A, PWM B, PWM X) to update

• currPwmMode – The current PWM mode set during PWM setup

• dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

void PWM_UpdatePwmDutycycleHighAccuracy(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle)

Updates the PWM signal’s dutycycle with 16-bit accuracy.

The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmSignal – Signal (PWM A, PWM B, PWM X) to update

• currPwmMode – The current PWM mode set during PWM setup

• dutyCycle – New PWM pulse width, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle)

void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t pulseCnt, uint16_t dutyCycle)

Update the PWM signal’s period and dutycycle for a PWM submodule.

The function updates PWM signal period generated by a specific submodule according to the parameters passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle or update new dutycycle. Call this function in local sync control mode because PWM period is depended by

INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. PWM signal will not be generated if its period is less than dead time duration.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmSignal – Signal (PWM A or PWM B) to update

• currPwmMode – The current PWM mode set during PWM setup, options available in enumeration pwm_mode_t

• pulseCnt – New PWM period, value should be between 0 to 65535 0=minimum PWM period… 65535=maximum PWM period

• dutyCycle – New PWM pulse width of channel, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle) You can keep original duty cycle or update new duty cycle

static inline void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Enables the selected PWM interrupts.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Disables the selected PWM interrupts.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)

Gets the enabled PWM interrupts.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t

static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, pwm_submodule_t subModule, pwm_watermark_control_t pwm_watermark_control)

Capture DMA Enable Source Select.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwm_watermark_control – PWM FIFO watermark and control

static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, pwm_submodule_t subModule, pwm_dma_source_select_t pwm_dma_source_select)

Capture DMA Enable Source Select.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwm_dma_source_select – PWM capture DMA enable source select

static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate)

Enables or disables the selected PWM DMA Capture read request.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• mask – The DMA to enable or disable. This is a logical OR of members of the enumeration pwm_dma_enable_t

• activate – true: Enable DMA read request; false: Disable DMA read request

static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate)

Enables or disables the PWM DMA write request.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• activate – true: Enable DMA write request; false: Disable DMA write request

static inline uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)

Gets the PWM status flags.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

Returns:

The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t

static inline void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Clears the PWM status flags.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• mask – The status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t

static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart)

Starts the PWM counter for a single or multiple submodules.

Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple submodules at the same time.

Parameters:

• base – PWM peripheral base address

• subModulesToStart – PWM submodules to start. This is a logical OR of members of the enumeration pwm_module_control_t

static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop)

Stops the PWM counter for a single or multiple submodules.

Clears the Run bit which resets the submodule’s counter. This function can stop multiple submodules at the same time.

Parameters:

• base – PWM peripheral base address

• subModulesToStop – PWM submodules to stop. This is a logical OR of members of the enumeration pwm_module_control_t

FSL_PWM_DRIVER_VERSION

Version 2.9.0

enum _pwm_submodule

List of PWM submodules.

Values:

enumerator kPWM_Module_0

Submodule 0

enumerator kPWM_Module_1

Submodule 1

enumerator kPWM_Module_2

Submodule 2

enum _pwm_channels

List of PWM channels in each module.

Values:

enumerator kPWM_PwmB

enumerator kPWM_PwmA

enumerator kPWM_PwmX

enum _pwm_value_register

List of PWM value registers.

Values:

enumerator kPWM_ValueRegister_0

PWM Value0 register

enumerator kPWM_ValueRegister_1

PWM Value1 register

enumerator kPWM_ValueRegister_2

PWM Value2 register

enumerator kPWM_ValueRegister_3

PWM Value3 register

enumerator kPWM_ValueRegister_4

PWM Value4 register

enumerator kPWM_ValueRegister_5

PWM Value5 register

enum _pwm_value_register_mask

List of PWM value registers mask.

Values:

enumerator kPWM_ValueRegisterMask_0

PWM Value0 register mask

enumerator kPWM_ValueRegisterMask_1

PWM Value1 register mask

enumerator kPWM_ValueRegisterMask_2

PWM Value2 register mask

enumerator kPWM_ValueRegisterMask_3

PWM Value3 register mask

enumerator kPWM_ValueRegisterMask_4

PWM Value4 register mask

enumerator kPWM_ValueRegisterMask_5

PWM Value5 register mask

enum _pwm_clock_source

PWM clock source selection.

Values:

enumerator kPWM_BusClock

The IPBus clock is used as the clock

enumerator kPWM_ExternalClock

EXT_CLK is used as the clock

enumerator kPWM_Submodule0Clock

Clock of the submodule 0 (AUX_CLK) is used as the source clock

enum _pwm_clock_prescale

PWM prescaler factor selection for clock source.

Values:

enumerator kPWM_Prescale_Divide_1

PWM clock frequency = fclk/1

enumerator kPWM_Prescale_Divide_2

PWM clock frequency = fclk/2

enumerator kPWM_Prescale_Divide_4

PWM clock frequency = fclk/4

enumerator kPWM_Prescale_Divide_8

PWM clock frequency = fclk/8

enumerator kPWM_Prescale_Divide_16

PWM clock frequency = fclk/16

enumerator kPWM_Prescale_Divide_32

PWM clock frequency = fclk/32

enumerator kPWM_Prescale_Divide_64

PWM clock frequency = fclk/64

enumerator kPWM_Prescale_Divide_128

PWM clock frequency = fclk/128

enum _pwm_force_output_trigger

Options that can trigger a PWM FORCE_OUT.

Values:

enumerator kPWM_Force_Local

The local force signal, CTRL2[FORCE], from the submodule is used to force updates

enumerator kPWM_Force_Master

The master force signal from submodule 0 is used to force updates

enumerator kPWM_Force_LocalReload

The local reload signal from this submodule is used to force updates without regard to the state of LDOK

enumerator kPWM_Force_MasterReload

The master reload signal from submodule 0 is used to force updates if LDOK is set

enumerator kPWM_Force_LocalSync

The local sync signal from this submodule is used to force updates

enumerator kPWM_Force_MasterSync

The master sync signal from submodule0 is used to force updates

enumerator kPWM_Force_External

The external force signal, EXT_FORCE, from outside the PWM module causes updates

enumerator kPWM_Force_ExternalSync

The external sync signal, EXT_SYNC, from outside the PWM module causes updates

enum _pwm_output_state

PWM channel output status.

Values:

enumerator kPWM_HighState

The output state of PWM channel is high

enumerator kPWM_LowState

The output state of PWM channel is low

enumerator kPWM_NormalState

The output state of PWM channel is normal

enumerator kPWM_InvertState

The output state of PWM channel is invert

enumerator kPWM_MaskState

The output state of PWM channel is mask

enum _pwm_init_source

PWM counter initialization options.

Values:

enumerator kPWM_Initialize_LocalSync

Local sync causes initialization

enumerator kPWM_Initialize_MasterReload

Master reload from submodule 0 causes initialization

enumerator kPWM_Initialize_MasterSync

Master sync from submodule 0 causes initialization

enumerator kPWM_Initialize_ExtSync

EXT_SYNC causes initialization

enum _pwm_load_frequency

PWM load frequency selection.

Values:

enumerator kPWM_LoadEveryOportunity

Every PWM opportunity

enumerator kPWM_LoadEvery2Oportunity

Every 2 PWM opportunities

enumerator kPWM_LoadEvery3Oportunity

Every 3 PWM opportunities

enumerator kPWM_LoadEvery4Oportunity

Every 4 PWM opportunities

enumerator kPWM_LoadEvery5Oportunity

Every 5 PWM opportunities

enumerator kPWM_LoadEvery6Oportunity

Every 6 PWM opportunities

enumerator kPWM_LoadEvery7Oportunity

Every 7 PWM opportunities

enumerator kPWM_LoadEvery8Oportunity

Every 8 PWM opportunities

enumerator kPWM_LoadEvery9Oportunity

Every 9 PWM opportunities

enumerator kPWM_LoadEvery10Oportunity

Every 10 PWM opportunities

enumerator kPWM_LoadEvery11Oportunity

Every 11 PWM opportunities

enumerator kPWM_LoadEvery12Oportunity

Every 12 PWM opportunities

enumerator kPWM_LoadEvery13Oportunity

Every 13 PWM opportunities

enumerator kPWM_LoadEvery14Oportunity

Every 14 PWM opportunities

enumerator kPWM_LoadEvery15Oportunity

Every 15 PWM opportunities

enumerator kPWM_LoadEvery16Oportunity

Every 16 PWM opportunities

enum _pwm_fault_input

List of PWM fault selections.

Values:

enumerator kPWM_Fault_0

Fault 0 input pin

enumerator kPWM_Fault_1

Fault 1 input pin

enumerator kPWM_Fault_2

Fault 2 input pin

enumerator kPWM_Fault_3

Fault 3 input pin

enum _pwm_fault_disable

List of PWM fault disable mapping selections.

Values:

enumerator kPWM_FaultDisable_0

Fault 0 disable mapping

enumerator kPWM_FaultDisable_1

Fault 1 disable mapping

enumerator kPWM_FaultDisable_2

Fault 2 disable mapping

enumerator kPWM_FaultDisable_3

Fault 3 disable mapping

enum _pwm_fault_channels

List of PWM fault channels.

Values:

enumerator kPWM_faultchannel_0

enumerator kPWM_faultchannel_1

enum _pwm_input_capture_edge

PWM capture edge select.

Values:

enumerator kPWM_Disable

Disabled

enumerator kPWM_FallingEdge

Capture on falling edge only

enumerator kPWM_RisingEdge

Capture on rising edge only

enumerator kPWM_RiseAndFallEdge

Capture on rising or falling edge

enum _pwm_force_signal

PWM output options when a FORCE_OUT signal is asserted.

Values:

enumerator kPWM_UsePwm

Generated PWM signal is used by the deadtime logic.

enumerator kPWM_InvertedPwm

Inverted PWM signal is used by the deadtime logic.

enumerator kPWM_SoftwareControl

Software controlled value is used by the deadtime logic.

enumerator kPWM_UseExternal

PWM_EXTA signal is used by the deadtime logic.

enum _pwm_chnl_pair_operation

Options available for the PWM A & B pair operation.

Values:

enumerator kPWM_Independent

PWM A & PWM B operate as 2 independent channels

enumerator kPWM_ComplementaryPwmA

PWM A & PWM B are complementary channels, PWM A generates the signal

enumerator kPWM_ComplementaryPwmB

PWM A & PWM B are complementary channels, PWM B generates the signal

enum _pwm_register_reload

Options available on how to load the buffered-registers with new values.

Values:

enumerator kPWM_ReloadImmediate

Buffered-registers get loaded with new values as soon as LDOK bit is set

enumerator kPWM_ReloadPwmHalfCycle

Registers loaded on a PWM half cycle

enumerator kPWM_ReloadPwmFullCycle

Registers loaded on a PWM full cycle

enumerator kPWM_ReloadPwmHalfAndFullCycle

Registers loaded on a PWM half & full cycle

enum _pwm_fault_recovery_mode

Options available on how to re-enable the PWM output when recovering from a fault.

Values:

enumerator kPWM_NoRecovery

PWM output will stay inactive

enumerator kPWM_RecoverHalfCycle

PWM output re-enabled at the first half cycle

enumerator kPWM_RecoverFullCycle

PWM output re-enabled at the first full cycle

enumerator kPWM_RecoverHalfAndFullCycle

PWM output re-enabled at the first half or full cycle

enum _pwm_interrupt_enable

List of PWM interrupt options.

Values:

enumerator kPWM_CompareVal0InterruptEnable

PWM VAL0 compare interrupt

enumerator kPWM_CompareVal1InterruptEnable

PWM VAL1 compare interrupt

enumerator kPWM_CompareVal2InterruptEnable

PWM VAL2 compare interrupt

enumerator kPWM_CompareVal3InterruptEnable

PWM VAL3 compare interrupt

enumerator kPWM_CompareVal4InterruptEnable

PWM VAL4 compare interrupt

enumerator kPWM_CompareVal5InterruptEnable

PWM VAL5 compare interrupt

enumerator kPWM_CaptureX0InterruptEnable

PWM capture X0 interrupt

enumerator kPWM_CaptureX1InterruptEnable

PWM capture X1 interrupt

enumerator kPWM_CaptureB0InterruptEnable

PWM capture B0 interrupt

enumerator kPWM_CaptureB1InterruptEnable

PWM capture B1 interrupt

enumerator kPWM_CaptureA0InterruptEnable

PWM capture A0 interrupt

enumerator kPWM_CaptureA1InterruptEnable

PWM capture A1 interrupt

enumerator kPWM_ReloadInterruptEnable

PWM reload interrupt

enumerator kPWM_ReloadErrorInterruptEnable

PWM reload error interrupt

enumerator kPWM_Fault0InterruptEnable

PWM fault 0 interrupt

enumerator kPWM_Fault1InterruptEnable

PWM fault 1 interrupt

enumerator kPWM_Fault2InterruptEnable

PWM fault 2 interrupt

enumerator kPWM_Fault3InterruptEnable

PWM fault 3 interrupt

enum _pwm_status_flags

List of PWM status flags.

Values:

enumerator kPWM_CompareVal0Flag

PWM VAL0 compare flag

enumerator kPWM_CompareVal1Flag

PWM VAL1 compare flag

enumerator kPWM_CompareVal2Flag

PWM VAL2 compare flag

enumerator kPWM_CompareVal3Flag

PWM VAL3 compare flag

enumerator kPWM_CompareVal4Flag

PWM VAL4 compare flag

enumerator kPWM_CompareVal5Flag

PWM VAL5 compare flag

enumerator kPWM_CaptureX0Flag

PWM capture X0 flag

enumerator kPWM_CaptureX1Flag

PWM capture X1 flag

enumerator kPWM_CaptureB0Flag

PWM capture B0 flag

enumerator kPWM_CaptureB1Flag

PWM capture B1 flag

enumerator kPWM_CaptureA0Flag

PWM capture A0 flag

enumerator kPWM_CaptureA1Flag

PWM capture A1 flag

enumerator kPWM_ReloadFlag

PWM reload flag

enumerator kPWM_ReloadErrorFlag

PWM reload error flag

enumerator kPWM_RegUpdatedFlag

PWM registers updated flag

enumerator kPWM_Fault0Flag

PWM fault 0 flag

enumerator kPWM_Fault1Flag

PWM fault 1 flag

enumerator kPWM_Fault2Flag

PWM fault 2 flag

enumerator kPWM_Fault3Flag

PWM fault 3 flag

enum _pwm_dma_enable

List of PWM DMA options.

Values:

enumerator kPWM_CaptureX0DMAEnable

PWM capture X0 DMA

enumerator kPWM_CaptureX1DMAEnable

PWM capture X1 DMA

enumerator kPWM_CaptureB0DMAEnable

PWM capture B0 DMA

enumerator kPWM_CaptureB1DMAEnable

PWM capture B1 DMA

enumerator kPWM_CaptureA0DMAEnable

PWM capture A0 DMA

enumerator kPWM_CaptureA1DMAEnable

PWM capture A1 DMA

enum _pwm_dma_source_select

List of PWM capture DMA enable source select.

Values:

enumerator kPWM_DMARequestDisable

Read DMA requests disabled

enumerator kPWM_DMAWatermarksEnable

Exceeding a FIFO watermark sets the DMA read request

enumerator kPWM_DMALocalSync

A local sync (VAL1 matches counter) sets the read DMA request

enumerator kPWM_DMALocalReload

A local reload (STS[RF] being set) sets the read DMA request

enum _pwm_watermark_control

PWM FIFO Watermark AND Control.

Values:

enumerator kPWM_FIFOWatermarksOR

Selected FIFO watermarks are OR’ed together

enumerator kPWM_FIFOWatermarksAND

Selected FIFO watermarks are AND’ed together

enum _pwm_mode

PWM operation mode.

Values:

enumerator kPWM_SignedCenterAligned

Signed center-aligned

enumerator kPWM_CenterAligned

Unsigned cente-aligned

enumerator kPWM_SignedEdgeAligned

Signed edge-aligned

enumerator kPWM_EdgeAligned

Unsigned edge-aligned

enum _pwm_level_select

PWM output pulse mode, high-true or low-true.

Values:

enumerator kPWM_HighTrue

High level represents “on” or “active” state

enumerator kPWM_LowTrue

Low level represents “on” or “active” state

enum _pwm_fault_state

PWM output fault status.

Values:

enumerator kPWM_PwmFaultState0

Output is forced to logic 0 state prior to consideration of output polarity control.

enumerator kPWM_PwmFaultState1

Output is forced to logic 1 state prior to consideration of output polarity control.

enumerator kPWM_PwmFaultState2

Output is tristated.

enumerator kPWM_PwmFaultState3

Output is tristated.

enum _pwm_reload_source_select

PWM reload source select.

Values:

enumerator kPWM_LocalReload

The local reload signal is used to reload registers

enumerator kPWM_MasterReload

The master reload signal (from submodule 0) is used to reload

enum _pwm_fault_clear

PWM fault clearing options.

Values:

enumerator kPWM_Automatic

Automatic fault clearing

enumerator kPWM_ManualNormal

Manual fault clearing with no fault safety mode

enumerator kPWM_ManualSafety

Manual fault clearing with fault safety mode

enum _pwm_module_control

Options for submodule master control operation.

Values:

enumerator kPWM_Control_Module_0

Control submodule 0’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_1

Control submodule 1’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_2

Control submodule 2’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_3

Control submodule 3’s start/stop,buffer reload operation

typedef enum _pwm_submodule pwm_submodule_t

List of PWM submodules.

typedef enum _pwm_channels pwm_channels_t

List of PWM channels in each module.

typedef enum _pwm_value_register pwm_value_register_t

List of PWM value registers.

typedef enum _pwm_clock_source pwm_clock_source_t

PWM clock source selection.

typedef enum _pwm_clock_prescale pwm_clock_prescale_t

PWM prescaler factor selection for clock source.

typedef enum _pwm_force_output_trigger pwm_force_output_trigger_t

Options that can trigger a PWM FORCE_OUT.

typedef enum _pwm_output_state pwm_output_state_t

PWM channel output status.

typedef enum _pwm_init_source pwm_init_source_t

PWM counter initialization options.

typedef enum _pwm_load_frequency pwm_load_frequency_t

PWM load frequency selection.

typedef enum _pwm_fault_input pwm_fault_input_t

List of PWM fault selections.

typedef enum _pwm_fault_disable pwm_fault_disable_t

List of PWM fault disable mapping selections.

typedef enum _pwm_fault_channels pwm_fault_channels_t

List of PWM fault channels.

typedef enum _pwm_input_capture_edge pwm_input_capture_edge_t

PWM capture edge select.

typedef enum _pwm_force_signal pwm_force_signal_t

PWM output options when a FORCE_OUT signal is asserted.

typedef enum _pwm_chnl_pair_operation pwm_chnl_pair_operation_t

Options available for the PWM A & B pair operation.

typedef enum _pwm_register_reload pwm_register_reload_t

Options available on how to load the buffered-registers with new values.

typedef enum _pwm_fault_recovery_mode pwm_fault_recovery_mode_t

Options available on how to re-enable the PWM output when recovering from a fault.

typedef enum _pwm_interrupt_enable pwm_interrupt_enable_t

List of PWM interrupt options.

typedef enum _pwm_status_flags pwm_status_flags_t

List of PWM status flags.

typedef enum _pwm_dma_enable pwm_dma_enable_t

List of PWM DMA options.

typedef enum _pwm_dma_source_select pwm_dma_source_select_t

List of PWM capture DMA enable source select.

typedef enum _pwm_watermark_control pwm_watermark_control_t

PWM FIFO Watermark AND Control.

typedef enum _pwm_mode pwm_mode_t

PWM operation mode.

typedef enum _pwm_level_select pwm_level_select_t

PWM output pulse mode, high-true or low-true.

typedef enum _pwm_fault_state pwm_fault_state_t

PWM output fault status.

typedef enum _pwm_reload_source_select pwm_reload_source_select_t

PWM reload source select.

typedef enum _pwm_fault_clear pwm_fault_clear_t

PWM fault clearing options.

typedef enum _pwm_module_control pwm_module_control_t

Options for submodule master control operation.

typedef struct _pwm_signal_param pwm_signal_param_t

Structure for the user to define the PWM signal characteristics.

typedef struct _pwm_config pwm_config_t

PWM config structure.

This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef struct _pwm_fault_input_filter_param pwm_fault_input_filter_param_t

Structure for the user to configure the fault input filter.

typedef struct _pwm_fault_param pwm_fault_param_t

Structure is used to hold the parameters to configure a PWM fault.

typedef struct _pwm_input_capture_param pwm_input_capture_param_t

Structure is used to hold parameters to configure the capture capability of a signal pin.

void PWM_SetupInputCapture(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, const pwm_input_capture_param_t *inputCaptureParams)

Sets up the PWM input capture.

Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function sets up the capture parameters for each pin and enables the pin for input capture operation.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – Channel in the submodule to setup

• inputCaptureParams – Parameters passed in to set up the input pin

void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams)

Sets up the PWM fault input filter.

Parameters:

• base – PWM peripheral base address

• faultInputFilterParams – Parameters passed in to set up the fault input filter.

void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)

Sets up the PWM fault protection.

PWM has 4 fault inputs.

Parameters:

• base – PWM peripheral base address

• faultNum – PWM fault to configure.

• faultParams – Pointer to the PWM fault config structure

void PWM_FaultDefaultConfig(pwm_fault_param_t *config)

Fill in the PWM fault config struct with the default settings.

The default values are:

config->faultClearingMode = kPWM_Automatic;
config->faultLevel = false;
config->enableCombinationalPath = true;
config->recoverMode = kPWM_NoRecovery;

Parameters:

• config – Pointer to user’s PWM fault config structure.

void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)

Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted.

The user specifies which channel to configure by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – Channel to configure

• mode – Signal to output when a FORCE_OUT is triggered

static inline void PWM_SetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, uint16_t value)

Set the PWM VALx registers.

This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is reached.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• valueRegister – VALx register that will be writen new value

• value – Value that will been write into VALx register

static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister)

Get the PWM VALx registers.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• valueRegister – VALx register that will be read value

Returns:

The VALx register value

static inline void PWM_OutputTriggerEnable(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, bool activate)

Enables or disables the PWM output trigger.

This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated when the counter matches VAL 1, VAL 3, or VAL 5 register.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• valueRegister – Value register that will activate the trigger

• activate – true: Enable the trigger; false: Disable the trigger

static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)

Enables the PWM output trigger.

This function allows the user to enable one or more (VAL0-5) PWM trigger.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• valueRegisterMask – Value register mask that will activate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask

static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)

Disables the PWM output trigger.

This function allows the user to disables one or more (VAL0-5) PWM trigger.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• valueRegisterMask – Value register mask that will Deactivate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask

static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value)

Sets the software control output for a pin to high or low.

The user specifies which channel to modify by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – Channel to configure

• value – true: Supply a logic 1, false: Supply a logic 0.

static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value)

Sets or clears the PWM LDOK bit on a single or multiple submodules.

Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the values are loaded at the next PWM reload point. This function can issue the load command to multiple submodules at the same time.

Parameters:

• base – PWM peripheral base address

• subModulesToUpdate – PWM submodules to update with buffered values. This is a logical OR of members of the enumeration pwm_module_control_t

• value – true: Set LDOK bit for the submodule list; false: Clear LDOK bit

static inline void PWM_SetPwmFaultState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_state_t faultState)

Set PWM output fault status.

These bits determine the fault state for the PWM_A output in fault conditions and STOP mode. It may also define the output state in WAIT and DEBUG modes depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. This function can update PWM output fault status.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – Channel to configure

• faultState – PWM output fault status

static inline void PWM_SetupFaultDisableMap(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_channels_t pwm_fault_channels, uint16_t value)

Set PWM fault disable mapping.

Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned off if there is a logic 1 on an FAULTx input and a 1 in the corresponding bit of this field. A reset sets all bits in this field.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• pwm_fault_channels – PWM fault channel to configure

• value – Fault disable mapping mask value enumeration pwm_fault_disable_t

static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)

Set PWM output enable.

This feature allows the user to enable the PWM Output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

• base – PWM peripheral base address

• pwmChannel – PWM channel to configure

• subModule – PWM submodule to configure

static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)

Set PWM output disable.

This feature allows the user to disable the PWM output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

• base – PWM peripheral base address

• pwmChannel – PWM channel to configure

• subModule – PWM submodule to configure

uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel)

Get the dutycycle value.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

Returns:

Current channel dutycycle value.

status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus)

Set PWM output in idle status (high or low).

Note

This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported.

Parameters:

• base – PWM peripheral base address

• pwmChannel – PWM channel to configure

• subModule – PWM submodule to configure

• idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.

Returns:

kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success

void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler)

Set the pwm submodule prescaler.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• prescaler – Set prescaler value

void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero)

This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0.

Parameters:

• base – PWM peripheral base address

• pwmChannel – PWM channel to configure

• subModule – PWM submodule to configure

• forcetozero – True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal function.

void PWM_SetChannelOutput(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_output_state_t outputstate)

This function set the output state of the PWM pin as requested for the current cycle.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• outputstate – Set pwm output state, see pwm_output_state_t.

status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles)

This function set the phase delay from the master sync signal of submodule 0.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• delayCycles – Number of cycles delayed from submodule 0.

Returns:

kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; kStatus_Success if set phase delay success

static inline void PWM_SetFilterSampleCount(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSampleCount)

This function set the number of consecutive samples that must agree prior to the input filter.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• filterSampleCount – Number of consecutive samples.

static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSamplePeriod)

This function set the sampling period of the fault pin input filter.

Parameters:

• base – PWM peripheral base address

• subModule – PWM submodule to configure

• pwmChannel – PWM channel to configure

• filterSamplePeriod – Sampling period of input filter.

PWM_SUBMODULE_SWCONTROL_WIDTH

Number of bits per submodule for software output control

PWM_SUBMODULE_CHANNEL

Submodule channels include PWMA, PWMB, PWMX.

struct _pwm_signal_param

#include <fsl_pwm.h>

Structure for the user to define the PWM signal characteristics.

Public Members

pwm_channels_t pwmChannel

PWM channel being configured; PWM A or PWM B

uint8_t dutyCyclePercent

PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle)

pwm_level_select_t level

PWM output active level select

uint16_t deadtimeValue

The deadtime value; only used if channel pair is operating in complementary mode

pwm_fault_state_t faultState

PWM output fault status

bool pwmchannelenable

Enable PWM output

struct _pwm_config

#include <fsl_pwm.h>

PWM config structure.

This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

bool enableDebugMode

true: PWM continues to run in debug mode; false: PWM is paused in debug mode

pwm_init_source_t initializationControl

Option to initialize the counter

pwm_clock_source_t clockSource

Clock source for the counter

pwm_clock_prescale_t prescale

Pre-scaler to divide down the clock

pwm_chnl_pair_operation_t pairOperation

Channel pair in indepedent or complementary mode

pwm_register_reload_t reloadLogic

PWM Reload logic setup

pwm_reload_source_select_t reloadSelect

Reload source select

pwm_load_frequency_t reloadFrequency

Specifies when to reload, used when user’s choice is not immediate reload

pwm_force_output_trigger_t forceTrigger

Specify which signal will trigger a FORCE_OUT

struct _pwm_fault_input_filter_param

#include <fsl_pwm.h>

Structure for the user to configure the fault input filter.

Public Members

uint8_t faultFilterCount

Fault filter count

uint8_t faultFilterPeriod

Fault filter period;value of 0 will bypass the filter

bool faultGlitchStretch

Fault Glitch Stretch Enable: A logic 1 means that input fault signals will be stretched to at least 2 IPBus clock cycles

struct _pwm_fault_param

#include <fsl_pwm.h>

Structure is used to hold the parameters to configure a PWM fault.

Public Members

pwm_fault_clear_t faultClearingMode

Fault clearing mode to use

bool faultLevel

true: Logic 1 indicates fault; false: Logic 0 indicates fault

bool enableCombinationalPath

true: Combinational Path from fault input is enabled; false: No combination path is available

pwm_fault_recovery_mode_t recoverMode

Specify when to re-enable the PWM output

struct _pwm_input_capture_param

#include <fsl_pwm.h>

Structure is used to hold parameters to configure the capture capability of a signal pin.

Public Members

bool captureInputSel

true: Use the edge counter signal as source false: Use the raw input signal from the pin as source

uint8_t edgeCompareValue

Compare value, used only if edge counter is used as source

pwm_input_capture_edge_t edge0

Specify which edge causes a capture for input circuitry 0

pwm_input_capture_edge_t edge1

Specify which edge causes a capture for input circuitry 1

bool enableOneShotCapture

true: Use one-shot capture mode; false: Use free-running capture mode

uint8_t fifoWatermark

Watermark level for capture FIFO. The capture flags in the status register will set if the word count in the FIFO is greater than this watermark level

PXP: Pixel Pipeline

void PXP_Init(PXP_Type *base)

Initialize the PXP.

This function enables the PXP peripheral clock, and resets the PXP registers to default status.

Parameters:

• base – PXP peripheral base address.

void PXP_Deinit(PXP_Type *base)

De-initialize the PXP.

This function disables the PXP peripheral clock.

Parameters:

• base – PXP peripheral base address.

void PXP_Reset(PXP_Type *base)

Reset the PXP.

This function resets the PXP peripheral registers to default status.

Parameters:

• base – PXP peripheral base address.

void PXP_ResetControl(PXP_Type *base)

Reset the PXP and the control register to initialized state.

Parameters:

• base – PXP peripheral base address.

static inline void PXP_Start(PXP_Type *base)

Start process.

Start PXP process using current configuration.

Parameters:

• base – PXP peripheral base address.

static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)

Enable or disable LCD hand shake.

Parameters:

• base – PXP peripheral base address.

• enable – True to enable, false to disable.

static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)

Enable or disable continous run.

If continous run not enabled, PXP_Start starts the PXP process. When completed, PXP enters idle mode and flag kPXP_CompleteFlag asserts.

If continous run enabled, the PXP will repeat based on the current configuration register settings.

Parameters:

• base – PXP peripheral base address.

• enable – True to enable, false to disable.

static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)

Set the PXP processing block size.

This function chooses the pixel block size that PXP using during process. Larger block size means better performace, but be careful that when PXP is rotating, the output must be divisible by the block size selected.

Parameters:

• base – PXP peripheral base address.

• size – The pixel block size.

static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable)

Enables or disables PXP engines in the process flow.

Parameters:

• base – PXP peripheral base address.

• mask – The engines to enable. Logical OR of pxp_process_engine_name_t.

• enable – true to enable, false to disable.

static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)

Gets PXP status flags.

This function gets all PXP status flags. The flags are returned as the logical OR value of the enumerators _pxp_flags. To check a specific status, compare the return value with enumerators in _pxp_flags. For example, to check whether the PXP has completed process, use like this:

if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP))
{
    ...
}

Parameters:

• base – PXP peripheral base address.

Returns:

PXP status flags which are OR’ed by the enumerators in the _pxp_flags.

static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)

Clears status flags with the provided mask.

This function clears PXP status flags with a provided mask.

Parameters:

• base – PXP peripheral base address.

• statusMask – The status flags to be cleared; it is logical OR value of _pxp_flags.

static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)

Gets the AXI ID of the failing bus operation.

Parameters:

• base – PXP peripheral base address.

• axiIndex – Whitch AXI to get

  • 0: AXI0

  • 1: AXI1

Returns:

The AXI ID of the failing bus operation.

static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)

Enables PXP interrupts according to the provided mask.

This function enables the PXP interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _pxp_interrupt_enable. For example, to enable PXP process complete interrupt and command loaded interrupt, do the following.

PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable);

Parameters:

• base – PXP peripheral base address.

• mask – The interrupts to enable. Logical OR of _pxp_interrupt_enable.

static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)

Disables PXP interrupts according to the provided mask.

This function disables the PXP interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _pxp_interrupt_enable.

Parameters:

• base – PXP peripheral base address.

• mask – The interrupts to disable. Logical OR of _pxp_interrupt_enable.

void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config)

Set the alpha surface input buffer configuration.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration.

void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config)

Set the alpha surface blending configuration.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration structure.

void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config)

Set the alpha surface blending configuration for the secondary engine.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration structure.

void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)

Set the alpha surface overlay color key.

If a pixel in the current overlay image with a color that falls in the range from the colorKeyLow to colorKeyHigh range, it will use the process surface pixel value for that location. If no PS image is present or if the PS image also matches its colorkey range, the PS background color is used.

Note

Colorkey operations are higher priority than alpha or ROP operations

Parameters:

• base – PXP peripheral base address.

• num – instance number. 0 for alpha engine A, 1 for alpha engine B.

• colorKeyLow – Color key low range.

• colorKeyHigh – Color key high range.

static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable)

Enable or disable the alpha surface color key.

Parameters:

• base – PXP peripheral base address.

• num – instance number. 0 for alpha engine A, 1 for alpha engine B.

• enable – True to enable, false to disable.

void PXP_SetAlphaSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)

Set the alpha surface position in output buffer.

Parameters:

• base – PXP peripheral base address.

• upperLeftX – X of the upper left corner.

• upperLeftY – Y of the upper left corner.

• lowerRightX – X of the lower right corner.

• lowerRightY – Y of the lower right corner.

static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor)

Set the back ground color of PS.

Parameters:

• base – PXP peripheral base address.

• num – instance number. 0 for alpha engine A, 1 for alpha engine B.

• backGroundColor – Pixel value of the background color.

void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config)

Set the process surface input buffer configuration.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration.

void PXP_SetProcessSurfaceScaler(PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight)

Set the process surface scaler configuration.

The valid down scale fact is 1/(2^12) ~ 16.

Parameters:

• base – PXP peripheral base address.

• inputWidth – Input image width.

• inputHeight – Input image height.

• outputWidth – Output image width.

• outputHeight – Output image height.

void PXP_SetProcessSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)

Set the process surface position in output buffer.

Parameters:

• base – PXP peripheral base address.

• upperLeftX – X of the upper left corner.

• upperLeftY – Y of the upper left corner.

• lowerRightX – X of the lower right corner.

• lowerRightY – Y of the lower right corner.

void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)

Set the process surface color key.

If the PS image matches colorkey range, the PS background color is output. Set colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying.

Parameters:

• base – PXP peripheral base address.

• num – instance number. 0 for alpha engine A, 1 for alpha engine B.

• colorKeyLow – Color key low range.

• colorKeyHigh – Color key high range.

static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)

Set the process surface input pixel format YUV or YCbCr.

If process surface input pixel format is YUV and CSC1 is not enabled, in other words, the process surface output pixel format is also YUV, then this function should be called to set whether input pixel format is YUV or YCbCr.

Parameters:

• base – PXP peripheral base address.

• format – The YUV format.

void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config)

Set the PXP outpt buffer configuration.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration.

static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)

Set the global overwritten alpha value.

If global overwritten alpha is enabled, the alpha component in output buffer pixels will be overwritten, otherwise the computed alpha value is used.

Parameters:

• base – PXP peripheral base address.

• alpha – The alpha value.

static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)

Enable or disable the global overwritten alpha value.

If global overwritten alpha is enabled, the alpha component in output buffer pixels will be overwritten, otherwise the computed alpha value is used.

Parameters:

• base – PXP peripheral base address.

• enable – True to enable, false to disable.

static inline void PXP_SetRotateConfig(PXP_Type *base, pxp_rotate_position_t position, pxp_rotate_degree_t degree, pxp_flip_mode_t flipMode)

Set the rotation configuration.

The PXP could rotate the process surface or the output buffer. There are two PXP versions:

• Version 1: Only has one rotate sub module, the output buffer and process surface share the same rotate sub module, which means the process surface and output buffer could not be rotate at the same time. When pass in kPXP_RotateOutputBuffer, the process surface could not use the rotate, Also when pass in kPXP_RotateProcessSurface, output buffer could not use the rotate.

• Version 2: Has two seperate rotate sub modules, the output buffer and process surface could configure the rotation independently.

Upper layer could use the macro PXP_SHARE_ROTATE to check which version is. PXP_SHARE_ROTATE=1 means version 1.

Note

This function is different depends on the macro PXP_SHARE_ROTATE.

Parameters:

• base – PXP peripheral base address.

• position – Rotate process surface or output buffer.

• degree – Rotate degree.

• flipMode – Flip mode.

void PXP_BuildRect(PXP_Type *base, pxp_output_pixel_format_t outFormat, uint32_t value, uint16_t width, uint16_t height, uint16_t pitch, uint32_t outAddr)

Build a solid rectangle of given pixel value.

Parameters:

• base – PXP peripheral base address.

• outFormat – output pixel format.

• value – The value of the pixel to be filled in the rectangle in ARGB8888 format.

• width – width of the rectangle.

• height – height of the rectangle.

• pitch – output pitch in byte.

• outAddr – address of the memory to store the rectangle.

void PXP_SetNextCommand(PXP_Type *base, void *commandAddr)

Set the next command.

The PXP supports a primitive ability to queue up one operation while the current operation is running. Workflow:

1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory in the order they appear in the register map.

2. Call this function sets the new operation to PXP.

3. There are two methods to check whether the PXP has loaded the new operation. The first method is using PXP_IsNextCommandPending. If there is new operation not loaded by the PXP, this function returns true. The second method is checking the flag kPXP_CommandLoadFlag, if command loaded, this flag asserts. User could enable interrupt kPXP_CommandLoadInterruptEnable to get the loaded signal in interrupt way.

4. When command loaded by PXP, a new command could be set using this function.

uint32_t pxp_command1[48];
uint32_t pxp_command2[48];

pxp_command1[0] = ...;
pxp_command1[1] = ...;
...
pxp_command2[0] = ...;
pxp_command2[1] = ...;
...

while (PXP_IsNextCommandPending(PXP))
{
}

PXP_SetNextCommand(PXP, pxp_command1);

while (PXP_IsNextCommandPending(PXP))
{
}

PXP_SetNextCommand(PXP, pxp_command2);

Parameters:

• base – PXP peripheral base address.

• commandAddr – Address of the new command.

static inline bool PXP_IsNextCommandPending(PXP_Type *base)

Check whether the next command is pending.

Parameters:

• base – UART peripheral base address.

Returns:

True is pending, false is not.

static inline void PXP_CancelNextCommand(PXP_Type *base)

Cancel command set by PXP_SetNextCommand.

Parameters:

• base – UART peripheral base address.

void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)

Set the CSC1 mode.

The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and converts the pixels to the RGB888 color space. It could only be used by process surface.

Parameters:

• base – PXP peripheral base address.

• mode – The conversion mode.

static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)

Enable or disable the CSC1.

Parameters:

• base – PXP peripheral base address.

• enable – True to enable, false to disable.

void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr)

Write data to the PXP internal memory.

Parameters:

• base – PXP peripheral base address.

• ram – Which internal memory to write.

• bytesNum – How many bytes to write.

• data – Pointer to the data to write.

• memStartAddr – The start address in the internal memory to write the data.

void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data)

Set the dither final LUT data.

The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] of the output pixel and looks up and 8 bit value from the 16 value LUT to generate the final output pixel to the next process module.

Parameters:

• base – PXP peripheral base address.

• data – Pointer to the LUT data to set.

static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)

Set the configuration for the dither block.

If the pre-dither LUT, post-dither LUT or ordered dither is used, please call PXP_SetInternalRamData to set the LUT data to internal memory.

If the final LUT is used, please call PXP_SetDitherFinalLutData to set the LUT data.

Note

When using ordered dithering, please set the PXP process block size same with the ordered dithering matrix size using function PXP_SetProcessBlockSize.

Parameters:

• base – PXP peripheral base address.

• config – Pointer to the configuration.

void PXP_EnableDither(PXP_Type *base, bool enable)

Enable or disable dither engine in the PXP process path.

After the initialize function PXP_Init, the dither engine is disabled and not use in the PXP processing path. This function enables the dither engine and routes the dither engine output to the output buffer. When the dither engine is enabled using this function, PXP_SetDitherConfig must be called to configure dither engine correctly, otherwise there is not output to the output buffer.

Parameters:

• base – PXP peripheral base address.

• enable – Pass in true to enable, false to disable.

void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config)

Set the Porter Duff configuration for one of the alpha process engine.

Parameters:

• base – PXP peripheral base address.

• num – instance number.

• config – Pointer to the configuration.

status_t PXP_GetPorterDuffConfigExt(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config, uint8_t dstGlobalAlphaMode, uint8_t dstAlphaMode, uint8_t dstColorMode, uint8_t srcGlobalAlphaMode, uint8_t srcAlphaMode, uint8_t srcColorMode, uint8_t dstGlobalAlpha, uint8_t srcGlobalAlpha)

Get the Porter Duff configuration.

The FactorMode are selected based on blend mode, the other values are set based on input parameters. These values could be modified after calling this function. This function is extened PXP_GetPorterDuffConfig.

Parameters:

• mode – The blend mode.

• config – Pointer to the configuration.

• dstGlobalAlphaMode – Destination layer (or PS, s0) global alpha mode, see pxp_porter_duff_global_alpha_mode

• dstAlphaMode – Destination layer (or PS, s0) alpha mode, see pxp_porter_duff_alpha_mode.

• dstColorMode – Destination layer (or PS, s0) color mode, see pxp_porter_duff_color_mode.

• srcGlobalAlphaMode – Source layer (or AS, s1) global alpha mode, see pxp_porter_duff_global_alpha_mode

• srcAlphaMode – Source layer (or AS, s1) alpha mode, see pxp_porter_duff_alpha_mode.

• srcColorMode – Source layer (or AS, s1) color mode, see pxp_porter_duff_color_mode.

• dstGlobalAlpha – Destination layer (or PS, s0) global alpha value, 0~255

• srcGlobalAlpha – Source layer (or AS, s1) global alpha value, 0~255

Return values:

• kStatus_Success – Successfully get the configuratoin.

• kStatus_InvalidArgument – The blend mode not supported.

static inline status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config)

Get the Porter Duff configuration by blend mode.

The FactorMode are selected based on blend mode, the AlphaMode are set to kPXP_PorterDuffAlphaStraight, the ColorMode are set to kPXP_PorterDuffColorWithAlpha, the GlobalAlphaMode are set to kPXP_PorterDuffLocalAlpha. These values could be modified after calling this function.

Parameters:

• mode – The blend mode.

• config – Pointer to the configuration.

Return values:

• kStatus_Success – Successfully get the configuratoin.

• kStatus_InvalidArgument – The blend mode not supported.

FSL_PXP_DRIVER_VERSION

enum _pxp_interrupt_enable

PXP interrupts to enable.

Values:

enumerator kPXP_CompleteInterruptEnable

PXP process completed. bit 1

enumerator kPXP_CommandLoadInterruptEnable

Interrupt to show that the command set by PXP_SetNextCommand has been loaded. bit 2

enumerator kPXP_CompressDoneInterruptEnable

Compress done interrupt enable. bit 15

enumerator kPXP_InputFetchCh0InterruptEnable

Input fetch channel 0 completed. bit 16

enumerator kPXP_InputFetchCh1InterruptEnable

Input fetch channel 1 completed. bit 17

enumerator kPXP_InputStoreCh0InterruptEnable

Input store channel 0 completed. bit 18

enumerator kPXP_InputStoreCh1InterruptEnable

Input store channel 1 completed. bit 19

enumerator kPXP_DitherFetchCh0InterruptEnable

Dither fetch channel 0 completed. bit 20

enumerator kPXP_DitherFetchCh1InterruptEnable

Dither fetch channel 1 completed. bit 21

enumerator kPXP_DitherStoreCh0InterruptEnable

Dither store channle 0 completed. bit 22

enumerator kPXP_DitherStoreCh1InterruptEnable

Dither store channle 1 completed. bit 23

enumerator kPXP_WfeaStoreCh0InterruptEnable

WFE-A store channel 0 completed. bit 24

enumerator kPXP_WfeaStoreCh1InterruptEnable

WFE-A store channel 1 completed. bit 25

enumerator kPXP_WfebStoreCh0InterruptEnable

WFE-B store channel 0 completed. bit 26

enumerator kPXP_WfebStoreCh1InterruptEnable

WFE-B store channel 1 completed. bit 27

enumerator kPXP_InputStoreInterruptEnable

Input store completed. bit 28

enumerator kPXP_DitherStoreInterruptEnable

Dither store completed. bit 29

enumerator kPXP_WfeaStoreInterruptEnable

WFE-A store completed. bit 30

enumerator kPXP_WfebStoreInterruptEnable

WFE-B store completed. bit 31

enum _pxp_flags

PXP status flags.

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kPXP_CompleteFlag

PXP process completed. bit 0

enumerator kPXP_Axi0WriteErrorFlag

PXP encountered an AXI write error and processing has been terminated. bit 1

enumerator kPXP_Axi0ReadErrorFlag

PXP encountered an AXI read error and processing has been terminated. bit 2

enumerator kPXP_CommandLoadFlag

The command set by PXP_SetNextCommand has been loaded, could set new command. bit 3

enumerator kPXP_CompressDoneFlag

Compress done. bit 15

enumerator kPXP_InputFetchCh0CompleteFlag

Input fetch channel 0 completed. bit 16

enumerator kPXP_InputFetchCh1CompleteFlag

Input fetch channel 1 completed. bit 17

enumerator kPXP_InputStoreCh0CompleteFlag

Input store channel 0 completed. bit 18

enumerator kPXP_InputStoreCh1CompleteFlag

Input store channel 1 completed. bit 19

enumerator kPXP_DitherFetchCh0CompleteFlag

Dither fetch channel 0 completed. bit 20

enumerator kPXP_DitherFetchCh1CompleteFlag

Dither fetch channel 1 completed. bit 21

enumerator kPXP_DitherStoreCh0CompleteFlag

Dither store channel 0 completed. bit 22

enumerator kPXP_DitherStoreCh1CompleteFlag

Dither store channel 1 completed. bit 23

enumerator kPXP_WfeaStoreCh0CompleteFlag

WFE-A store channel 0 completed. bit 24

enumerator kPXP_WfeaStoreCh1CompleteFlag

WFE-A store channel 1 completed. bit 25

enumerator kPXP_WfebStoreCh0CompleteFlag

WFE-B store channel 0 completed. bit 26

enumerator kPXP_WfebStoreCh1CompleteFlag

WFE-B store channel 1 completed. bit 27

enumerator kPXP_InputStoreCompleteFlag

Input store completed. bit 28

enumerator kPXP_DitherStoreCompleteFlag

Dither store completed. bit 29

enumerator kPXP_WfeaStoreCompleteFlag

WFE-A store completed. bit 30

enumerator kPXP_WfebStoreCompleteFlag

WFE-B store completed. bit 31

enum _pxp_flip_mode

PXP output flip mode.

Values:

enumerator kPXP_FlipDisable

Flip disable.

enumerator kPXP_FlipHorizontal

Horizontal flip.

enumerator kPXP_FlipVertical

Vertical flip.

enumerator kPXP_FlipBoth

Flip both directions.

enum _pxp_rotate_position

PXP rotate mode.

Values:

enumerator kPXP_RotateOutputBuffer

Rotate the output buffer.

enumerator kPXP_RotateProcessSurface

Rotate the process surface. Cannot be used together with flip, scale, or decimation function.

enum _pxp_rotate_degree

PXP rotate degree.

Values:

enumerator kPXP_Rotate0

Clock wise rotate 0 deg.

enumerator kPXP_Rotate90

Clock wise rotate 90 deg.

enumerator kPXP_Rotate180

Clock wise rotate 180 deg.

enumerator kPXP_Rotate270

Clock wise rotate 270 deg.

enum _pxp_interlaced_output_mode

PXP interlaced output mode.

Values:

enumerator kPXP_OutputProgressive

All data written in progressive format to output buffer 0.

enumerator kPXP_OutputField0

Only write field 0 data to output buffer 0.

enumerator kPXP_OutputField1

Only write field 1 data to output buffer 0.

enumerator kPXP_OutputInterlaced

Field 0 write to buffer 0, field 1 write to buffer 1.

enum _pxp_output_pixel_format

PXP output buffer format.

Values:

enumerator kPXP_OutputPixelFormatARGB8888

32-bit pixels with alpha.

enumerator kPXP_OutputPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format)

enumerator kPXP_OutputPixelFormatRGB888P

24-bit pixels without alpha (packed 24-bit format)

enumerator kPXP_OutputPixelFormatARGB1555

16-bit pixels with alpha.

enumerator kPXP_OutputPixelFormatARGB4444

16-bit pixels with alpha.

enumerator kPXP_OutputPixelFormatRGB555

16-bit pixels without alpha.

enumerator kPXP_OutputPixelFormatRGB444

16-bit pixels without alpha.

enumerator kPXP_OutputPixelFormatRGB565

16-bit pixels without alpha.

enumerator kPXP_OutputPixelFormatYUV1P444

32-bit pixels (1-plane XYUV unpacked).

enumerator kPXP_OutputPixelFormatUYVY1P422

16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)

enumerator kPXP_OutputPixelFormatVYUY1P422

16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)

enumerator kPXP_OutputPixelFormatY8

8-bit monochrome pixels (1-plane Y luma output)

enumerator kPXP_OutputPixelFormatY4

4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)

enumerator kPXP_OutputPixelFormatYUV2P422

16-bit pixels (2-plane UV interleaved bytes)

enumerator kPXP_OutputPixelFormatYUV2P420

16-bit pixels (2-plane UV)

enumerator kPXP_OutputPixelFormatYVU2P422

16-bit pixels (2-plane VU interleaved bytes)

enumerator kPXP_OutputPixelFormatYVU2P420

16-bit pixels (2-plane VU)

enum _pxp_ps_pixel_format

PXP process surface buffer pixel format.

Values:

enumerator kPXP_PsPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format)

enumerator kPXP_PsPixelFormatRGB555

16-bit pixels without alpha.

enumerator kPXP_PsPixelFormatRGB444

16-bit pixels without alpha.

enumerator kPXP_PsPixelFormatRGB565

16-bit pixels without alpha.

enumerator kPXP_PsPixelFormatYUV1P444

32-bit pixels (1-plane XYUV unpacked).

enumerator kPXP_PsPixelFormatUYVY1P422

16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)

enumerator kPXP_PsPixelFormatVYUY1P422

16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)

enumerator kPXP_PsPixelFormatY8

8-bit monochrome pixels (1-plane Y luma output)

enumerator kPXP_PsPixelFormatY4

4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)

enumerator kPXP_PsPixelFormatYUV2P422

16-bit pixels (2-plane UV interleaved bytes)

enumerator kPXP_PsPixelFormatYUV2P420

16-bit pixels (2-plane UV)

enumerator kPXP_PsPixelFormatYVU2P422

16-bit pixels (2-plane VU interleaved bytes)

enumerator kPXP_PsPixelFormatYVU2P420

16-bit pixels (2-plane VU)

enumerator kPXP_PsPixelFormatYVU422

16-bit pixels (3-plane)

enumerator kPXP_PsPixelFormatYVU420

16-bit pixels (3-plane)

enum _pxp_ps_yuv_format

PXP process surface buffer YUV format.

Values:

enumerator kPXP_PsYUVFormatYUV

YUV format.

enumerator kPXP_PsYUVFormatYCbCr

YCbCr format.

enum _pxp_as_pixel_format

PXP alpha surface buffer pixel format.

Values:

enumerator kPXP_AsPixelFormatARGB8888

32-bit pixels with alpha.

enumerator kPXP_AsPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format)

enumerator kPXP_AsPixelFormatARGB1555

16-bit pixels with alpha.

enumerator kPXP_AsPixelFormatARGB4444

16-bit pixels with alpha.

enumerator kPXP_AsPixelFormatRGB555

16-bit pixels without alpha.

enumerator kPXP_AsPixelFormatRGB444

16-bit pixels without alpha.

enumerator kPXP_AsPixelFormatRGB565

16-bit pixels without alpha.

enum _pxp_alpha_mode

PXP alpha mode during blending.

Values:

enumerator kPXP_AlphaEmbedded

The alpha surface pixel alpha value will be used for blend.

enumerator kPXP_AlphaOverride

The user defined alpha value will be used for blend directly.

enumerator kPXP_AlphaMultiply

The alpha surface pixel alpha value scaled the user defined alpha value will be used for blend, for example, pixel alpha set set to 200, user defined alpha set to 100, then the reault alpha is 200 * 100 / 255.

enumerator kPXP_AlphaRop

Raster operation.

enum _pxp_rop_mode

PXP ROP mode during blending.

Explanation:

• AS: Alpha surface

• PS: Process surface

• nAS: Alpha surface NOT value

• nPS: Process surface NOT value

Values:

enumerator kPXP_RopMaskAs

AS AND PS.

enumerator kPXP_RopMaskNotAs

nAS AND PS.

enumerator kPXP_RopMaskAsNot

AS AND nPS.

enumerator kPXP_RopMergeAs

AS OR PS.

enumerator kPXP_RopMergeNotAs

nAS OR PS.

enumerator kPXP_RopMergeAsNot

AS OR nPS.

enumerator kPXP_RopNotCopyAs

nAS.

enumerator kPXP_RopNot

nPS.

enumerator kPXP_RopNotMaskAs

AS NAND PS.

enumerator kPXP_RopNotMergeAs

AS NOR PS.

enumerator kPXP_RopXorAs

AS XOR PS.

enumerator kPXP_RopNotXorAs

AS XNOR PS.

enum _pxp_block_size

PXP process block size.

Values:

enumerator kPXP_BlockSize8

Process 8x8 pixel blocks.

enumerator kPXP_BlockSize16

Process 16x16 pixel blocks.

enum _pxp_csc1_mode

PXP CSC1 mode.

Values:

enumerator kPXP_Csc1YUV2RGB

YUV to RGB.

enumerator kPXP_Csc1YCbCr2RGB

YCbCr to RGB.

enum _pxp_csc2_mode

PXP CSC2 mode.

Values:

enumerator kPXP_Csc2YUV2RGB

YUV to RGB.

enumerator kPXP_Csc2YCbCr2RGB

YCbCr to RGB.

enumerator kPXP_Csc2RGB2YUV

RGB to YUV.

enumerator kPXP_Csc2RGB2YCbCr

RGB to YCbCr.

enum _pxp_ram

PXP internal memory.

Values:

enumerator kPXP_RamDither0Lut

Dither 0 LUT memory.

enumerator kPXP_RamDither1Lut

Dither 1 LUT memory.

enumerator kPXP_RamDither2Lut

Dither 2 LUT memory.

enumerator kPXP_RamDither0Err0

Dither 0 ERR0 memory.

enumerator kPXP_RamDither0Err1

Dither 0 ERR1 memory.

enumerator kPXP_RamAluA

ALU A instr memory.

enumerator kPXP_RamAluB

ALU B instr memory.

enumerator kPXP_WfeAFetch

WFE-A fetch memory.

enumerator kPXP_WfeBFetch

WFE-B fetch memory.

enum _pxp_dither_mode

PXP dither mode.

Values:

enumerator kPXP_DitherPassThrough

Pass through, no dither.

enumerator kPXP_DitherFloydSteinberg

Floyd-Steinberg. For dither engine 0 only.

enumerator kPXP_DitherAtkinson

Atkinson. For dither engine 0 only.

enumerator kPXP_DitherOrdered

Ordered dither.

enumerator kPXP_DitherQuantOnly

No dithering, only quantization.

enumerator kPXP_DitherSierra

Sierra. For dither engine 0 only.

enum _pxp_dither_lut_mode

PXP dither LUT mode.

Values:

enumerator kPXP_DitherLutOff

The LUT memory is not used for LUT, could be used as ordered dither index matrix.

enumerator kPXP_DitherLutPreDither

Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode or Atkinson mode, which are not supported by current PXP module.

enumerator kPXP_DitherLutPostDither

Use LUT at the post-dither stage.

enum _pxp_dither_matrix_size

PXP dither matrix size.

Values:

enumerator kPXP_DitherMatrix4

The dither index matrix is 4x4.

enumerator kPXP_DitherMatrix8

The dither index matrix is 8x8.

enumerator kPXP_DitherMatrix16

The dither index matrix is 16x16.

Porter Duff factor mode. .

Values:

enumerator kPXP_PorterDuffFactorOne

Use 1.

enumerator kPXP_PorterDuffFactorZero

Use 0.

enumerator kPXP_PorterDuffFactorStraight

Use straight alpha.

enumerator kPXP_PorterDuffFactorInversed

Use inversed alpha.

Porter Duff global alpha mode. .

Values:

enumerator kPXP_PorterDuffGlobalAlpha

Use global alpha.

enumerator kPXP_PorterDuffLocalAlpha

Use local alpha in each pixel.

enumerator kPXP_PorterDuffScaledAlpha

Use global alpha * local alpha.

Porter Duff alpha mode. .

Values:

enumerator kPXP_PorterDuffAlphaStraight

Use straight alpha, s0_alpha’ = s0_alpha.

enumerator kPXP_PorterDuffAlphaInversed

Use inversed alpha, s0_alpha’ = 0xFF - s0_alpha.

Porter Duff color mode. .

Values:

enumerator kPXP_PorterDuffColorStraight

Deprecated:

Use kPXP_PorterDuffColorNoAlpha.

enumerator kPXP_PorterDuffColorInversed

Deprecated:

Use kPXP_PorterDuffColorWithAlpha.

enumerator kPXP_PorterDuffColorNoAlpha

s0_pixel’ = s0_pixel.

enumerator kPXP_PorterDuffColorWithAlpha

s0_pixel’ = s0_pixel * s0_alpha”.

enum _pxp_porter_duff_blend_mode

PXP Porter Duff blend mode. Note: don’t change the enum item value.

Values:

enumerator kPXP_PorterDuffSrc

Source Only

enumerator kPXP_PorterDuffAtop

Source Atop

enumerator kPXP_PorterDuffOver

Source Over

enumerator kPXP_PorterDuffIn

Source In.

enumerator kPXP_PorterDuffOut

Source Out.

enumerator kPXP_PorterDuffDst

Destination Only.

enumerator kPXP_PorterDuffDstAtop

Destination Atop.

enumerator kPXP_PorterDuffDstOver

Destination Over.

enumerator kPXP_PorterDuffDstIn

Destination In.

enumerator kPXP_PorterDuffDstOut

Destination Out.

enumerator kPXP_PorterDuffXor

XOR.

enumerator kPXP_PorterDuffClear

Clear.

enumerator kPXP_PorterDuffMax

enum _pxp_process_engine_name

PXP process engine enumeration.

Values:

enumerator kPXP_PsAsOutEngine

enumerator kPXP_DitherEngine

enumerator kPXP_WfeaEngine

enumerator kPXP_WfebEngine

enumerator kPXP_InputFetchStoreEngine

enumerator kPXP_Alpha1Engine

enumerator kPXP_Csc2Engine

enumerator kPXP_LutEngine

enumerator kPXP_Rotate0Engine

enumerator kPXP_Rotate1Engine

enum _pxp_fetch_engine_name

PXP fetch engine enumeration.

There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, whose registers are reserved from developer.

Values:

enumerator kPXP_FetchInput

enumerator kPXP_FetchDither

enum _pxp_fetch_interface_mode

PXP fetch engine interface mode with the upstream store engine.

Values:

enumerator kPXP_FetchModeNormal

enumerator kPXP_FetchModeHandshake

enumerator kPXP_FetchModeBypass

enum _pxp_scanline_burst

PXP fetch/store engine burst length for scanline mode.

Values:

enumerator kPXP_Scanline8bytes

enumerator kPXP_Scanline16bytes

enumerator kPXP_Scanline32bytes

enumerator kPXP_Scanline64bytes

enum _pxp_activeBits

PXP fetch/store engine input/output active bits configuration.

Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input mode. And expand configuration will have no effect.

Values:

enumerator kPXP_Active8Bits

enumerator kPXP_Active16Bits

enumerator kPXP_Active32Bits

enumerator kPXP_Active64Bits

enum _pxp_fetch_output_word_order

PXP fetch engine output word order when using 2 channels for 64-bit mode.

Values:

enumerator kPXP_FetchOutputChannel1channel0

In 64bit mode, channel 1 output high byte.

enumerator kPXP_FetchOutputChannel0channel1

In 64bit mode, channel 0 output high byte.

enum _pxp_fetch_pixel_format

PXP fetch engine input pixel format.

Values:

enumerator kPXP_FetchFormatRGB565

enumerator kPXP_FetchFormatRGB555

enumerator kPXP_FetchFormatARGB1555

enumerator kPXP_FetchFormatRGB444

enumerator kPXP_FetchFormatARGB4444

enumerator kPXP_FetchFormatYUYVorYVYU

enumerator kPXP_FetchFormatUYVYorVYUY

enumerator kPXP_FetchFormatYUV422_2P

enum _pxp_store_engine_name

PXP store engine enumeration.

There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, whose registers are reserved from developer.

Values:

enumerator kPXP_StoreInput

enumerator kPXP_StoreDither

enum _pxp_store_interface_mode

PXP store engine interface mode with the downstream fetch engine.

Values:

enumerator kPXP_StoreModeBypass

Store engine output the input data, after the shift function directly to the downstream Fetch Engine.

enumerator kPXP_StoreModeNormal

Store engine stores the input data to memory.

enumerator kPXP_StoreModeHandshake

Downstream fetch engine fetch data per scanline from memory using buffer sharing with store engine.

enumerator kPXP_StoreModeDual

Store engine outputs data directly to downstream fetch engine(Bypass) but also storing it to memory at the same time.

enum _pxp_store_yuv_mode

PXP store engine YUV output mode.

Values:

enumerator kPXP_StoreYUVDisable

Do not output YUV pixel format.

enumerator kPXP_StoreYUVPlane1

Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}.

enumerator kPXP_StoreYUVPlane2

Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}.

enum _pxp_cfa_input_format

PXP pre-dither CFA engine input pixel format.

Values:

enumerator kPXP_CfaRGB888

enumerator kPXP_CfaRGB444

enum _pxp_histogram_mask_condition

PXP histogram mask condition.

Values:

enumerator kPXP_HistogramMaskEqual

Value that equal to value0 will pass the mask operation.

enumerator kPXP_HistogramMaskNotequal

Value that not equal to value0 will pass the mask operation.

enumerator kPXP_HistogramMaskIn

Value that within the range of value0-value1 will pass the mask operation.

enumerator kPXP_HistogramMaskOut

Value that without the range of value0-value1 will pass the mask operation.

enum _pxp_histgram_flags

PXP Histogram operation result flags.

Values:

enumerator kPXP_Histogram2levelMatch

enumerator kPXP_Histogram4levelMatch

enumerator kPXP_Histogram8levelMatch

enumerator kPXP_Histogram16levelMatch

enumerator kPXP_Histogram32levelMatch

typedef enum _pxp_flip_mode pxp_flip_mode_t

PXP output flip mode.

typedef enum _pxp_rotate_position pxp_rotate_position_t

PXP rotate mode.

typedef enum _pxp_rotate_degree pxp_rotate_degree_t

PXP rotate degree.

typedef enum _pxp_interlaced_output_mode pxp_interlaced_output_mode_t

PXP interlaced output mode.

typedef enum _pxp_output_pixel_format pxp_output_pixel_format_t

PXP output buffer format.

typedef struct _pxp_output_buffer_config pxp_output_buffer_config_t

PXP output buffer configuration.

typedef enum _pxp_ps_pixel_format pxp_ps_pixel_format_t

PXP process surface buffer pixel format.

typedef enum _pxp_ps_yuv_format pxp_ps_yuv_format_t

PXP process surface buffer YUV format.

typedef struct _pxp_ps_buffer_config pxp_ps_buffer_config_t

PXP process surface buffer configuration.

typedef enum _pxp_as_pixel_format pxp_as_pixel_format_t

PXP alpha surface buffer pixel format.

typedef struct _pxp_as_buffer_config pxp_as_buffer_config_t

PXP alphs surface buffer configuration.

typedef enum _pxp_alpha_mode pxp_alpha_mode_t

PXP alpha mode during blending.

typedef enum _pxp_rop_mode pxp_rop_mode_t

PXP ROP mode during blending.

Explanation:

• AS: Alpha surface

• PS: Process surface

• nAS: Alpha surface NOT value

• nPS: Process surface NOT value

typedef struct _pxp_as_blend_config pxp_as_blend_config_t

PXP alpha surface blending configuration.

typedef struct _pxp_as_blend_secondary_config pxp_as_blend_secondary_config_t

PXP secondary alpha surface blending engine configuration.

typedef enum _pxp_block_size pxp_block_size_t

PXP process block size.

typedef enum _pxp_csc1_mode pxp_csc1_mode_t

PXP CSC1 mode.

typedef enum _pxp_csc2_mode pxp_csc2_mode_t

PXP CSC2 mode.

typedef struct _pxp_csc2_config pxp_csc2_config_t

PXP CSC2 configuration.

Converting from YUV/YCbCr color spaces to the RGB color space uses the following equation structure:

R = A1(Y+D1) + A2(U+D2) + A3(V+D3) G = B1(Y+D1) + B2(U+D2) + B3(V+D3) B = C1(Y+D1) + C2(U+D2) + C3(V+D3)

Converting from the RGB color space to YUV/YCbCr color spaces uses the following equation structure:

Y = A1*R + A2*G + A3*B + D1 U = B1*R + B2*G + B3*B + D2 V = C1*R + C2*G + C3*B + D3

typedef enum _pxp_ram pxp_ram_t

PXP internal memory.

typedef struct _pxp_dither_final_lut_data pxp_dither_final_lut_data_t

PXP dither final LUT data.

typedef struct _pxp_dither_config pxp_dither_config_t

PXP dither configuration.

typedef enum _pxp_porter_duff_blend_mode pxp_porter_duff_blend_mode_t

PXP Porter Duff blend mode. Note: don’t change the enum item value.

typedef struct _pxp_pic_copy_config pxp_pic_copy_config_t

PXP Porter Duff blend mode. Note: don’t change the enum item value.

typedef enum _pxp_process_engine_name pxp_process_engine_name_t

PXP process engine enumeration.

typedef enum _pxp_fetch_engine_name pxp_fetch_engine_name_t

PXP fetch engine enumeration.

There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, whose registers are reserved from developer.

typedef enum _pxp_fetch_interface_mode pxp_fetch_interface_mode_t

PXP fetch engine interface mode with the upstream store engine.

typedef enum _pxp_scanline_burst pxp_scanline_burst_t

PXP fetch/store engine burst length for scanline mode.

typedef struct _pxp_block_format_config pxp_block_config_t

PXP fetch engine block configuration.

typedef enum _pxp_activeBits pxp_active_bits_t

PXP fetch/store engine input/output active bits configuration.

Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input mode. And expand configuration will have no effect.

typedef enum _pxp_fetch_output_word_order pxp_fetch_output_word_order_t

PXP fetch engine output word order when using 2 channels for 64-bit mode.

typedef struct _pxp_fetch_shift_component pxp_fetch_shift_component_t

PXP fetch engine shift component configuration.

Fetch engine can divded each word into 4 components and shift them.

typedef struct _pxp_fetch_shift_config pxp_fetch_shift_config_t

PXP fetch engine shift configuration.

Fetch engine can divded each word into 4 components and shift them. For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, OFFSET3=24, WIDTH0/1/2/3=8

typedef enum _pxp_fetch_pixel_format pxp_fetch_pixel_format_t

PXP fetch engine input pixel format.

typedef struct _pxp_fetch_engine_config pxp_fetch_engine_config_t

PXP fetch engine configuration for one of the channel.

typedef enum _pxp_store_engine_name pxp_store_engine_name_t

PXP store engine enumeration.

There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, whose registers are reserved from developer.

typedef enum _pxp_store_interface_mode pxp_store_interface_mode_t

PXP store engine interface mode with the downstream fetch engine.

typedef enum _pxp_store_yuv_mode pxp_store_yuv_mode_t

PXP store engine YUV output mode.

typedef struct _pxp_store_shift_config pxp_store_shift_config_t

Shift configuration for PXP store engine.

typedef struct _pxp_store_engine_config pxp_store_engine_config_t

PXP store engine configuration for one of the channel.

typedef enum _pxp_cfa_input_format pxp_cfa_input_format_t

PXP pre-dither CFA engine input pixel format.

typedef struct _pxp_cfa_config pxp_cfa_config_t

PXP pre-dither CFA engine configuration.

typedef enum _pxp_histogram_mask_condition pxp_histogram_mask_condition_t

PXP histogram mask condition.

typedef struct _pxp_histogram_config pxp_histogram_config_t

PXP Histogram configuration.

typedef struct _pxp_histogram_mask_result pxp_histogram_mask_result_t

PXP Histogram mask result.

typedef struct _pxp_wfea_engine_config pxp_wfea_engine_config_t

PXP WFE-A engine configuration.

PXP_LUT_TABLE_BYTE

PXP_INTERNAL_RAM_LUT_BYTE

PXP_SHARE_ROTATE

PXP_USE_PATH

PXP_COMBINE_BYTE_TO_WORD(dataAddr)

struct _pxp_output_buffer_config

#include <fsl_pxp.h>

PXP output buffer configuration.

Public Members

pxp_output_pixel_format_t pixelFormat

Output buffer pixel format.

pxp_interlaced_output_mode_t interlacedMode

Interlaced output mode.

uint32_t buffer0Addr

Output buffer 0 address.

uint32_t buffer1Addr

Output buffer 1 address, used for UV data in YUV 2-plane mode, or field 1 in output interlaced mode.

uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels.

uint16_t width

Pixels per line.

uint16_t height

How many lines in output buffer.

struct _pxp_ps_buffer_config

#include <fsl_pxp.h>

PXP process surface buffer configuration.

Public Members

pxp_ps_pixel_format_t pixelFormat

PS buffer pixel format.

bool swapByte

For each 16 bit word, set true to swap the two bytes.

uint32_t bufferAddr

Input buffer address for the first panel.

uint32_t bufferAddrU

Input buffer address for the second panel.

uint32_t bufferAddrV

Input buffer address for the third panel.

uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels.

struct _pxp_as_buffer_config

#include <fsl_pxp.h>

PXP alphs surface buffer configuration.

Public Members

pxp_as_pixel_format_t pixelFormat

AS buffer pixel format.

uint32_t bufferAddr

Input buffer address.

uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels.

struct _pxp_as_blend_config

#include <fsl_pxp.h>

PXP alpha surface blending configuration.

Public Members

uint8_t alpha

User defined alpha value, only used when alphaMode is kPXP_AlphaOverride or kPXP_AlphaRop.

bool invertAlpha

Set true to invert the alpha.

pxp_alpha_mode_t alphaMode

Alpha mode.

pxp_rop_mode_t ropMode

ROP mode, only valid when alphaMode is kPXP_AlphaRop.

struct _pxp_as_blend_secondary_config

#include <fsl_pxp.h>

PXP secondary alpha surface blending engine configuration.

Public Members

bool invertAlpha

Set true to invert the alpha.

bool ropEnable

Enable rop mode.

pxp_rop_mode_t ropMode

ROP mode, only valid when ropEnable is true.

struct _pxp_csc2_config

#include <fsl_pxp.h>

PXP CSC2 configuration.

Converting from YUV/YCbCr color spaces to the RGB color space uses the following equation structure:

R = A1(Y+D1) + A2(U+D2) + A3(V+D3) G = B1(Y+D1) + B2(U+D2) + B3(V+D3) B = C1(Y+D1) + C2(U+D2) + C3(V+D3)

Converting from the RGB color space to YUV/YCbCr color spaces uses the following equation structure:

Y = A1*R + A2*G + A3*B + D1 U = B1*R + B2*G + B3*B + D2 V = C1*R + C2*G + C3*B + D3

Public Members

pxp_csc2_mode_t mode

Convertion mode.

float A1

A1.

float A2

A2.

float A3

A3.

float B1

B1.

float B2

B2.

float B3

B3.

float C1

C1.

float C2

C2.

float C3

C3.

int16_t D1

D1.

int16_t D2

D2.

int16_t D3

D3.

struct _pxp_dither_final_lut_data

#include <fsl_pxp.h>

PXP dither final LUT data.

Public Members

uint32_t data_3_0

Data 3 to data 0. Data 0 is the least significant byte.

uint32_t data_7_4

Data 7 to data 4. Data 4 is the least significant byte.

uint32_t data_11_8

Data 11 to data 8. Data 8 is the least significant byte.

uint32_t data_15_12

Data 15 to data 12. Data 12 is the least significant byte.

struct _pxp_dither_config

#include <fsl_pxp.h>

PXP dither configuration.

Public Members

uint32_t enableDither0

Enable dither engine 0 or not, set 1 to enable, 0 to disable.

uint32_t enableDither1

Enable dither engine 1 or not, set 1 to enable, 0 to disable.

uint32_t enableDither2

Enable dither engine 2 or not, set 1 to enable, 0 to disable.

uint32_t ditherMode0

Dither mode for dither engine 0. See _pxp_dither_mode.

uint32_t ditherMode1

Dither mode for dither engine 1. See _pxp_dither_mode.

uint32_t ditherMode2

Dither mode for dither engine 2. See _pxp_dither_mode.

uint32_t quantBitNum

Number of bits quantize down to, the valid value is 1~7.

uint32_t lutMode

How to use the memory LUT, see _pxp_dither_lut_mode. This must be set to kPXP_DitherLutOff if any dither engine uses kPXP_DitherOrdered mode.

uint32_t idxMatrixSize0

Size of index matrix used for dither for dither engine 0, see _pxp_dither_matrix_size.

uint32_t idxMatrixSize1

Size of index matrix used for dither for dither engine 1, see _pxp_dither_matrix_size.

uint32_t idxMatrixSize2

Size of index matrix used for dither for dither engine 2, see _pxp_dither_matrix_size.

uint32_t enableFinalLut

Enable the final LUT, set 1 to enable, 0 to disable.

struct pxp_porter_duff_config_t

#include <fsl_pxp.h>

PXP Porter Duff configuration.

Public Members

uint32_t enable

Enable or disable Porter Duff.

uint32_t srcFactorMode

Source layer (or AS, s1) factor mode, see pxp_porter_duff_factor_mode.

uint32_t dstGlobalAlphaMode

Destination layer (or PS, s0) global alpha mode, see pxp_porter_duff_global_alpha_mode.

uint32_t dstAlphaMode

Destination layer (or PS, s0) alpha mode, see pxp_porter_duff_alpha_mode.

uint32_t dstColorMode

Destination layer (or PS, s0) color mode, see pxp_porter_duff_color_mode.

uint32_t dstFactorMode

Destination layer (or PS, s0) factor mode, see pxp_porter_duff_factor_mode.

uint32_t srcGlobalAlphaMode

Source layer (or AS, s1) global alpha mode, see pxp_porter_duff_global_alpha_mode.

uint32_t srcAlphaMode

Source layer (or AS, s1) alpha mode, see pxp_porter_duff_alpha_mode.

uint32_t srcColorMode

Source layer (or AS, s1) color mode, see pxp_porter_duff_color_mode.

uint32_t dstGlobalAlpha

Destination layer (or PS, s0) global alpha value, 0~255.

uint32_t srcGlobalAlpha

Source layer (or AS, s1) global alpha value, 0~255.

struct _pxp_pic_copy_config

#include <fsl_pxp.h>

PXP Porter Duff blend mode. Note: don’t change the enum item value.

Public Members

uint32_t srcPicBaseAddr

Source picture base address.

uint16_t srcPitchBytes

Pitch of the source buffer.

uint16_t srcOffsetX

Copy position in source picture.

uint16_t srcOffsetY

Copy position in source picture.

uint32_t destPicBaseAddr

Destination picture base address.

uint16_t destPitchBytes

Pitch of the destination buffer.

uint16_t destOffsetX

Copy position in destination picture.

uint16_t destOffsetY

Copy position in destination picture.

uint16_t width

Pixel number each line to copy.

uint16_t height

Lines to copy.

pxp_as_pixel_format_t pixelFormat

Buffer pixel format.

struct _pxp_block_format_config

#include <fsl_pxp.h>

PXP fetch engine block configuration.

Public Members

bool enableblock

Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If LUT processing is in the path between the fetch and store engind, block mode must be enabled.

bool blockSize16

Enable to use 16*16 block, otherwise it will be 8*8 block.

pxp_scanline_burst_t burstLength

When using scanline mode, configure this for burst length.

struct _pxp_fetch_shift_component

#include <fsl_pxp.h>

PXP fetch engine shift component configuration.

Fetch engine can divded each word into 4 components and shift them.

struct _pxp_fetch_shift_config

#include <fsl_pxp.h>

PXP fetch engine shift configuration.

Fetch engine can divded each word into 4 components and shift them. For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, OFFSET3=24, WIDTH0/1/2/3=8

struct _pxp_fetch_engine_config

#include <fsl_pxp.h>

PXP fetch engine configuration for one of the channel.

Public Members

bool channelEnable

Enable channel.

uint32_t inputBaseAddr0

The input base address. Used for Y plane input when pixel format is YUV422_2p.

uint32_t inputBaseAddr1

Must configure this for UV plane when input pixel format is YUV422_2p.

uint16_t totalHeight

Total height for the actual fetch size.

uint16_t totalWidth

Total width for the actual fetch size.

uint16_t pitchBytes

Channel input pitch

uint16_t ulcX

X coordinate of upper left coordinate in pixels of the active area of the total input memory

uint16_t ulcY

Y coordinate of upper left coordinate in pixels of the active area of the total input memory

uint16_t lrcX

X coordinate of Lower right coordinate in pixels of the active area of the total input memory

uint16_t lrcY

Y coordinate of Lower right coordinate in pixels of the active area of the total input memory

uint32_t backGroundColor

Pixel value of the background color for the space outside the active area.

pxp_fetch_interface_mode_t interface

Interface mode, normal/bypass/handshake

pxp_active_bits_t activeBits

Input active bits.

pxp_fetch_pixel_format_t pixelFormat

Input pixel fetch format

bool expandEnable

If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at the output.

pxp_flip_mode_t flipMode

Flip the fetched input.

pxp_rotate_degree_t rotateDegree

Rotate the fetched input.

pxp_block_config_t fetchFormat

Block mode configuration. Make sure to enable block if rotate or flip mode is enabled.

pxp_fetch_shift_config_t shiftConfig

Shift operation configuration.

pxp_fetch_output_word_order_t wordOrder

Output word order when using 2 channels for 64-bit mode.

struct _pxp_store_shift_config

#include <fsl_pxp.h>

Shift configuration for PXP store engine.

Public Members

bool shiftBypass

Bypass the data shift

uint64_t *pDataShiftMask

Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then shifted according to width.

uint8_t *pDataShiftWidth

Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for shift width.

uint8_t *pFlagShiftMask

Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then shifted according to width.

uint8_t *pFlagShiftWidth

Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for shift width.

struct _pxp_store_engine_config

#include <fsl_pxp.h>

PXP store engine configuration for one of the channel.

Public Members

bool channelEnable

Enable channel.

uint32_t outputBaseAddr0

The channel 0 output address if using 2 channels. If using 1 channel(must be channel

0) and YUV422_2p output format, is for Y plane address.

uint32_t outputBaseAddr1

The channel 1 output address if using 2 channels. If using 1 channel(must be channel

0) and YUV422_2p output format, is for UV plane address.

uint16_t totalHeight

Total height for the actual store size.

uint16_t totalWidth

Total width for the actual store size.

uint16_t pitchBytes

Channel input pitch

pxp_store_interface_mode_t interface

Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use the same mode if both enabled.

pxp_active_bits_t activeBits

Output active bits.

pxp_store_yuv_mode_t yuvMode

Whether to output YUV pixel format.

bool useFixedData

Whether to use fixed value for the output data. Can be used to write fixed value to specific memory location for memory initialization.

uint32_t fixedData

The value of the fixed data.

bool packInSelect

When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select high 32 bit, otherwise all 64-bit of data will be selected.

pxp_block_config_t storeFormat

The format to store data, block or otherwise.

pxp_store_shift_config_t shiftConfig

Shift operation configuration.

struct _pxp_cfa_config

#include <fsl_pxp.h>

PXP pre-dither CFA engine configuration.

Public Members

bool bypass

Bypass the CFA process

pxp_cfa_input_format_t pixelInFormat

The pixel input format for CFA.

uint8_t arrayWidth

CFA array vertical size in pixels, min 3 max 15.

uint8_t arrayHeight

CFA array horizontal size in pixels, min 3 max 15.

uint16_t totalHeight

Total height for the buffer size, make sure it is aligned with the dither fetch engine and dither engine.

uint16_t totalWidth

Total width for the buffer size, make sure it is aligned with the dither fetch engine and dither engine.

uint32_t *cfaValue

Pointer to the value for the CFA array. 2-bit per component: 00-R,01-G,10-B,11-W. For a 4x4 array, 32 bits are need.

struct _pxp_histogram_config

#include <fsl_pxp.h>

PXP Histogram configuration.

Public Members

bool enable

Enable histogram process.

uint8_t *pParamValue

Pointer to the 62(2+4+8+16+32) byte of param value for 2-level, 4-level…..32-level parameters. Only low 5-bit of each byte is valid.

uint8_t lutValueOffset

The starting bit position of the LUT value.

uint8_t lutValueWidth

The bit width of the LUT value, should be no more than 6 bits since only 63 LUTs are supported.

bool enableMask

Enable mask operation.

uint8_t maskValue0

Value 0 for the condition judgement.

uint8_t maskValue1

Value 1 for the condition judgement.

uint8_t maskOffset

The starting bit position of the field to be checked against mask condition.

uint8_t maskWidth

The width of the field to be checked against mask condition.

pxp_histogram_mask_condition_t condition

The mask condition.

uint16_t totalHeight

Total height for the buffer size, make sure it is aligned with the output of legacy flow or the WFE-A/B engine.

uint16_t totalWidth

Total width for the buffer size, make sure it is aligned with the output of legacy flow or the WFE-A/B engine.

struct _pxp_histogram_mask_result

#include <fsl_pxp.h>

PXP Histogram mask result.

Public Members

uint32_t pixelCount

The total count of the pixels that pass the mask(collided pixels).

uint32_t minX

The x offset of the ULC of the minimal histogram that covers all passed pixels.

uint32_t minY

The y offset of the ULC of the minimal histogram that covers all passed pixels.

uint32_t maxX

The x offset of the LRC of the minimal histogram that covers all passed pixels.

uint32_t maxY

The y offset of the LRC of the minimal histogram that covers all passed pixels.

uint64_t lutlist

The 64-bit LUT list of collided pixels, if pixel of LUT17 is collided, bit17 in the list is set.

struct _pxp_wfea_engine_config

#include <fsl_pxp.h>

PXP WFE-A engine configuration.

Public Members

uint32_t y4Addr

Address for Y4 buffer.

uint32_t y4cAddr

Address for Y4C buffer, {Y4[3:0],3’b000,collision}, 8bpp.

uint32_t wbAddr

Address for EPDC working buffer.

uint16_t updateWidth

Width of the update area.

uint16_t updateHeight

Height of the update area.

uint16_t updatePitch

Pitch of the update area.

uint16_t ulcX

X coordinate of upper left coordinate of the total input memory

uint16_t ulcY

Y coordinate of upper left coordinate of the total input memory

uint16_t resX

Horizontal resolution in pixels.

uint8_t lutNum

The EPDC LUT number for the update.

bool fullUpdateEnable

Enable full update.

bool alphaEnable

Enable alpha field, upd is {Y4[3:0],3’b000,alpha} format, otherwise its {Y4[3:0],4’b0000}.

bool detectionOnly

Detection only, do not write working buffer.

QTMR: Quad Timer Driver

void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)

Ungates the Quad Timer clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the Quad Timer driver.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• config – Pointer to user’s Quad Timer config structure

void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the counter and gates the Quad Timer clock.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

void QTMR_GetDefaultConfig(qtmr_config_t *config)

Fill in the Quad Timer config struct with the default settings.

The default values are:

config->debugMode = kQTMR_RunNormalInDebug;
config->enableExternalForce = false;
config->enableMasterMode = false;
config->faultFilterCount = 0;
config->faultFilterPeriod = 0;
config->primarySource = kQTMR_ClockDivide_2;
config->secondarySource = kQTMR_Counter0InputPin;

Parameters:

• config – Pointer to user’s Quad Timer config structure.

void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Enables the selected Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Disables the selected Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base addres

• channel – Quad Timer channel number

• mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the enabled Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the Quad Timer status flags.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

The status flags. This is the logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Clears the Quad Timer status flags.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The status flags to clear. This is a logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)

Sets the timer period in ticks.

Timers counts from initial value till it equals the count value set here. The counter will then reinitialize to the value specified in the Load register.

Note

1. This function will write the time period in ticks to COMP1 or COMP2 register depending on the count direction

2. User can call the utility macros provided in fsl_common.h to convert to ticks

3. This function supports cases, providing only primary source clock without secondary source clock.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• ticks – Timer period in units of ticks

void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)

Set compare value.

This function sets the value used for comparison with the counter value.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• ticks – Timer period in units of ticks.

static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value)

Set load value.

This function sets the value used to initialize the counter after a counter comparison.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• value – Load register initialization value.

static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current counter value in ticks

static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)

Starts the Quad Timer counter.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• clockSource – Quad Timer clock source

static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the Quad Timer counter.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Enable the Quad Timer DMA.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t

void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Disable the Quad Timer DMA.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t

void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus)

Set PWM output in idle status (high or low).

Note

When the PWM is set again, the counting needs to be restarted.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.

static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the channel output status.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current channel output status.

uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the PWM channel dutycycle value.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current channel dutycycle value.

void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler)

This function set the value of the prescaler on QTimer channels.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• prescaler – Set prescaler value

FSL_QTMR_DRIVER_VERSION

Version

enum _qtmr_primary_count_source

Quad Timer primary clock source selection.

Values:

enumerator kQTMR_ClockCounter0InputPin

Use counter 0 input pin

enumerator kQTMR_ClockCounter1InputPin

Use counter 1 input pin

enumerator kQTMR_ClockCounter2InputPin

Use counter 2 input pin

enumerator kQTMR_ClockCounter3InputPin

Use counter 3 input pin

enumerator kQTMR_ClockCounter0Output

Use counter 0 output

enumerator kQTMR_ClockCounter1Output

Use counter 1 output

enumerator kQTMR_ClockCounter2Output

Use counter 2 output

enumerator kQTMR_ClockCounter3Output

Use counter 3 output

enumerator kQTMR_ClockDivide_1

IP bus clock divide by 1 prescaler

enumerator kQTMR_ClockDivide_2

IP bus clock divide by 2 prescaler

enumerator kQTMR_ClockDivide_4

IP bus clock divide by 4 prescaler

enumerator kQTMR_ClockDivide_8

IP bus clock divide by 8 prescaler

enumerator kQTMR_ClockDivide_16

IP bus clock divide by 16 prescaler

enumerator kQTMR_ClockDivide_32

IP bus clock divide by 32 prescaler

enumerator kQTMR_ClockDivide_64

IP bus clock divide by 64 prescaler

enumerator kQTMR_ClockDivide_128

IP bus clock divide by 128 prescaler

enum _qtmr_input_source

Quad Timer input sources selection.

Values:

enumerator kQTMR_Counter0InputPin

Use counter 0 input pin

enumerator kQTMR_Counter1InputPin

Use counter 1 input pin

enumerator kQTMR_Counter2InputPin

Use counter 2 input pin

enumerator kQTMR_Counter3InputPin

Use counter 3 input pin

enum _qtmr_counting_mode

Quad Timer counting mode selection.

Values:

enumerator kQTMR_NoOperation

No operation

enumerator kQTMR_PriSrcRiseEdge

Count rising edges of primary source

enumerator kQTMR_PriSrcRiseAndFallEdge

Count rising and falling edges of primary source

enumerator kQTMR_PriSrcRiseEdgeSecInpHigh

Count rise edges of pri SRC while sec inp high active

enumerator kQTMR_QuadCountMode

Quadrature count mode, uses pri and sec sources

enumerator kQTMR_PriSrcRiseEdgeSecDir

Count rising edges of pri SRC; sec SRC specifies dir

enumerator kQTMR_SecSrcTrigPriCnt

Edge of sec SRC trigger primary count until compare

enumerator kQTMR_CascadeCount

Cascaded count mode (up/down)

enum _qtmr_pwm_out_state

Quad Timer PWM output state.

Values:

enumerator kQTMR_PwmLow

The output state of PWM channel is low

enumerator kQTMR_PwmHigh

The output state of PWM channel is low

enum _qtmr_output_mode

Quad Timer output mode selection.

Values:

enumerator kQTMR_AssertWhenCountActive

Assert OFLAG while counter is active

enumerator kQTMR_ClearOnCompare

Clear OFLAG on successful compare

enumerator kQTMR_SetOnCompare

Set OFLAG on successful compare

enumerator kQTMR_ToggleOnCompare

Toggle OFLAG on successful compare

enumerator kQTMR_ToggleOnAltCompareReg

Toggle OFLAG using alternating compare registers

enumerator kQTMR_SetOnCompareClearOnSecSrcInp

Set OFLAG on compare, clear on sec SRC input edge

enumerator kQTMR_SetOnCompareClearOnCountRoll

Set OFLAG on compare, clear on counter rollover

enumerator kQTMR_EnableGateClock

Enable gated clock output while count is active

enum _qtmr_input_capture_edge

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoCapture

Capture is disabled

enumerator kQTMR_RisingEdge

Capture on rising edge (IPS=0) or falling edge (IPS=1)

enumerator kQTMR_FallingEdge

Capture on falling edge (IPS=0) or rising edge (IPS=1)

enumerator kQTMR_RisingAndFallingEdge

Capture on both edges

enum _qtmr_preload_control

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoPreload

Never preload

enumerator kQTMR_LoadOnComp1

Load upon successful compare with value in COMP1

enumerator kQTMR_LoadOnComp2

Load upon successful compare with value in COMP2

enum _qtmr_debug_action

List of Quad Timer run options when in Debug mode.

Values:

enumerator kQTMR_RunNormalInDebug

Continue with normal operation

enumerator kQTMR_HaltCounter

Halt counter

enumerator kQTMR_ForceOutToZero

Force output to logic 0

enumerator kQTMR_HaltCountForceOutZero

Halt counter and force output to logic 0

enum _qtmr_interrupt_enable

List of Quad Timer interrupts.

Values:

enumerator kQTMR_CompareInterruptEnable

Compare interrupt.

enumerator kQTMR_Compare1InterruptEnable

Compare 1 interrupt.

enumerator kQTMR_Compare2InterruptEnable

Compare 2 interrupt.

enumerator kQTMR_OverflowInterruptEnable

Timer overflow interrupt.

enumerator kQTMR_EdgeInterruptEnable

Input edge interrupt.

enum _qtmr_status_flags

List of Quad Timer flags.

Values:

enumerator kQTMR_CompareFlag

Compare flag

enumerator kQTMR_Compare1Flag

Compare 1 flag

enumerator kQTMR_Compare2Flag

Compare 2 flag

enumerator kQTMR_OverflowFlag

Timer overflow flag

enumerator kQTMR_EdgeFlag

Input edge flag

enum _qtmr_channel_selection

List of channel selection.

Values:

enumerator kQTMR_Channel_0

TMR Channel 0

enumerator kQTMR_Channel_1

TMR Channel 1

enumerator kQTMR_Channel_2

TMR Channel 2

enumerator kQTMR_Channel_3

TMR Channel 3

enum _qtmr_dma_enable

List of Quad Timer DMA enable.

Values:

enumerator kQTMR_InputEdgeFlagDmaEnable

Input Edge Flag DMA Enable.

enumerator kQTMR_ComparatorPreload1DmaEnable

Comparator Preload Register 1 DMA Enable.

enumerator kQTMR_ComparatorPreload2DmaEnable

Comparator Preload Register 2 DMA Enable.

typedef enum _qtmr_primary_count_source qtmr_primary_count_source_t

Quad Timer primary clock source selection.

typedef enum _qtmr_input_source qtmr_input_source_t

Quad Timer input sources selection.

typedef enum _qtmr_counting_mode qtmr_counting_mode_t

Quad Timer counting mode selection.

typedef enum _qtmr_pwm_out_state qtmr_pwm_out_state_t

Quad Timer PWM output state.

typedef enum _qtmr_output_mode qtmr_output_mode_t

Quad Timer output mode selection.

typedef enum _qtmr_input_capture_edge qtmr_input_capture_edge_t

Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_preload_control qtmr_preload_control_t

Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_debug_action qtmr_debug_action_t

List of Quad Timer run options when in Debug mode.

typedef enum _qtmr_interrupt_enable qtmr_interrupt_enable_t

List of Quad Timer interrupts.

typedef enum _qtmr_status_flags qtmr_status_flags_t

List of Quad Timer flags.

typedef enum _qtmr_channel_selection qtmr_channel_selection_t

List of channel selection.

typedef enum _qtmr_dma_enable qtmr_dma_enable_t

List of Quad Timer DMA enable.

typedef struct _qtmr_config qtmr_config_t

Quad Timer config structure.

This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

status_t QTMR_SetupPwm(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)

Sets up Quad timer module for PWM signal output.

The function initializes the timer module according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• pwmFreqHz – PWM signal frequency in Hz

• dutyCyclePercent – PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

• outputPolarity – true: invert polarity of the output signal, false: no inversion

• srcClock_Hz – Main counter clock in Hz.

Returns:

Returns an error if there was error setting up the signal.

void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, bool inputPolarity, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode)

Allows the user to count the source clock cycles until a capture event arrives.

The count is stored in the capture register.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• capturePin – Pin through which we receive the input signal to trigger the capture

• inputPolarity – true: invert polarity of the input signal, false: no inversion

• reloadOnCapture – true: reload the counter when an input capture occurs, false: no reload

• captureMode – Specifies which edge of the input signal triggers a capture

TMR_CSCTRL_OFLAG_MASK

TMR_CSCTRL_OFLAG_SHIFT

struct _qtmr_config

#include <fsl_qtmr.h>

Quad Timer config structure.

This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

qtmr_primary_count_source_t primarySource

Specify the primary count source

qtmr_input_source_t secondarySource

Specify the secondary count source

bool enableMasterMode

true: Broadcast compare function output to other counters; false no broadcast

bool enableExternalForce

true: Compare from another counter force state of OFLAG signal false: OFLAG controlled by local counter

uint8_t faultFilterCount

Fault filter count

uint8_t faultFilterPeriod

Fault filter period;value of 0 will bypass the filter

qtmr_debug_action_t debugMode

Operation in Debug mode

RDC: Resource Domain Controller

enum _rdc_interrupts

RDC interrupts.

Values:

enumerator kRDC_RestoreCompleteInterrupt

Interrupt generated when the RDC has completed restoring state to a recently re-powered memory regions.

enum _rdc_flags

RDC status.

Values:

enumerator kRDC_PowerDownDomainOn

Power down domain is ON.

enum _rdc_access_policy

Access permission policy.

Values:

enumerator kRDC_NoAccess

Could not read or write.

enumerator kRDC_WriteOnly

Write only.

enumerator kRDC_ReadOnly

Read only.

enumerator kRDC_ReadWrite

Read and write.

typedef struct _rdc_hardware_config rdc_hardware_config_t

RDC hardware configuration.

typedef struct _rdc_domain_assignment rdc_domain_assignment_t

Master domain assignment.

typedef struct _rdc_periph_access_config rdc_periph_access_config_t

Peripheral domain access permission configuration.

typedef struct _rdc_mem_access_config rdc_mem_access_config_t

Memory region domain access control configuration.

Note that when setting the rdc_mem_access_config_t::baseAddress and rdc_mem_access_config_t::endAddress, should be aligned to the region resolution, see rdc_mem_t definitions.

typedef struct _rdc_mem_status rdc_mem_status_t

Memory region access violation status.

void RDC_Init(RDC_Type *base)

Initializes the RDC module.

This function enables the RDC clock.

Parameters:

• base – RDC peripheral base address.

void RDC_Deinit(RDC_Type *base)

De-initializes the RDC module.

This function disables the RDC clock.

Parameters:

• base – RDC peripheral base address.

void RDC_GetHardwareConfig(RDC_Type *base, rdc_hardware_config_t *config)

Gets the RDC hardware configuration.

This function gets the RDC hardware configurations, including number of bus masters, number of domains, number of memory regions and number of peripherals.

Parameters:

• base – RDC peripheral base address.

• config – Pointer to the structure to get the configuration.

static inline void RDC_EnableInterrupts(RDC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – RDC peripheral base address.

• mask – Interrupts to enable, it is OR’ed value of enum _rdc_interrupts.

static inline void RDC_DisableInterrupts(RDC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – RDC peripheral base address.

• mask – Interrupts to disable, it is OR’ed value of enum _rdc_interrupts.

static inline uint32_t RDC_GetInterruptStatus(RDC_Type *base)

Get the interrupt pending status.

Parameters:

• base – RDC peripheral base address.

Returns:

Interrupts pending status, it is OR’ed value of enum _rdc_interrupts.

static inline void RDC_ClearInterruptStatus(RDC_Type *base, uint32_t mask)

Clear interrupt pending status.

Parameters:

• base – RDC peripheral base address.

• mask – Status to clear, it is OR’ed value of enum _rdc_interrupts.

static inline uint32_t RDC_GetStatus(RDC_Type *base)

Get RDC status.

Parameters:

• base – RDC peripheral base address.

Returns:

mask RDC status, it is OR’ed value of enum _rdc_flags.

static inline void RDC_ClearStatus(RDC_Type *base, uint32_t mask)

Clear RDC status.

Parameters:

• base – RDC peripheral base address.

• mask – RDC status to clear, it is OR’ed value of enum _rdc_flags.

void RDC_SetMasterDomainAssignment(RDC_Type *base, rdc_master_t master, const rdc_domain_assignment_t *domainAssignment)

Set master domain assignment.

Parameters:

• base – RDC peripheral base address.

• master – Which master to set.

• domainAssignment – Pointer to the assignment.

void RDC_GetDefaultMasterDomainAssignment(rdc_domain_assignment_t *domainAssignment)

Get default master domain assignment.

The default configuration is:

assignment->domainId = 0U;
assignment->lock = 0U;

Parameters:

• domainAssignment – Pointer to the assignment.

static inline void RDC_LockMasterDomainAssignment(RDC_Type *base, rdc_master_t master)

Lock master domain assignment.

Once locked, it could not be unlocked until next reset.

Parameters:

• base – RDC peripheral base address.

• master – Which master to lock.

void RDC_SetPeriphAccessConfig(RDC_Type *base, const rdc_periph_access_config_t *config)

Set peripheral access policy.

Parameters:

• base – RDC peripheral base address.

• config – Pointer to the policy configuration.

void RDC_GetDefaultPeriphAccessConfig(rdc_periph_access_config_t *config)

Get default peripheral access policy.

The default configuration is:

config->lock = false;
config->enableSema = false;
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(3, kRDC_ReadWrite);

Parameters:

• config – Pointer to the policy configuration.

static inline void RDC_LockPeriphAccessConfig(RDC_Type *base, rdc_periph_t periph)

Lock peripheral access policy configuration.

Once locked, it could not be unlocked until reset.

Parameters:

• base – RDC peripheral base address.

• periph – Which peripheral to lock.

static inline uint8_t RDC_GetPeriphAccessPolicy(RDC_Type *base, rdc_periph_t periph, uint8_t domainId)

Get the peripheral access policy for specific domain.

Parameters:

• base – RDC peripheral base address.

• periph – Which peripheral to get.

• domainId – Get policy for which domain.

Returns:

Access policy, see _rdc_access_policy.

void RDC_SetMemAccessConfig(RDC_Type *base, const rdc_mem_access_config_t *config)

Set memory region access policy.

Note that when setting the baseAddress and endAddress in config, should be aligned to the region resolution, see rdc_mem_t definitions.

Parameters:

• base – RDC peripheral base address.

• config – Pointer to the policy configuration.

void RDC_GetDefaultMemAccessConfig(rdc_mem_access_config_t *config)

Get default memory region access policy.

The default configuration is:

config->lock = false;
config->baseAddress = 0;
config->endAddress = 0;
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(3, kRDC_ReadWrite);

Parameters:

• config – Pointer to the policy configuration.

static inline void RDC_LockMemAccessConfig(RDC_Type *base, rdc_mem_t mem)

Lock memory access policy configuration.

Once locked, it could not be unlocked until reset. After locked, you can only call RDC_SetMemAccessValid to enable the configuration, but can not disable it or change other settings.

Parameters:

• base – RDC peripheral base address.

• mem – Which memory region to lock.

static inline void RDC_SetMemAccessValid(RDC_Type *base, rdc_mem_t mem, bool valid)

Enable or disable memory access policy configuration.

Parameters:

• base – RDC peripheral base address.

• mem – Which memory region to operate.

• valid – Pass in true to valid, false to invalid.

void RDC_GetMemViolationStatus(RDC_Type *base, rdc_mem_t mem, rdc_mem_status_t *status)

Get the memory region violation status.

The first access violation is captured. Subsequent violations are ignored until the status register is cleared. Contents are cleared upon reading the register. Clearing of contents occurs only when the status is read by the memory region’s associated domain ID(s).

Parameters:

• base – RDC peripheral base address.

• mem – Which memory region to get.

• status – The returned status.

static inline void RDC_ClearMemViolationFlag(RDC_Type *base, rdc_mem_t mem)

Clear the memory region violation flag.

Parameters:

• base – RDC peripheral base address.

• mem – Which memory region to clear.

static inline uint8_t RDC_GetMemAccessPolicy(RDC_Type *base, rdc_mem_t mem, uint8_t domainId)

Get the memory region access policy for specific domain.

Parameters:

• base – RDC peripheral base address.

• mem – Which memory region to get.

• domainId – Get policy for which domain.

Returns:

Access policy, see _rdc_access_policy.

static inline uint8_t RDC_GetCurrentMasterDomainId(RDC_Type *base)

Gets the domain ID of the current bus master.

This function returns the domain ID of the current bus master.

Parameters:

• base – RDC peripheral base address.

Returns:

Domain ID of current bus master.

FSL_RDC_DRIVER_VERSION

RDC_ACCESS_POLICY(domainID, policy)

struct _rdc_hardware_config

#include <fsl_rdc.h>

RDC hardware configuration.

Public Members

uint32_t domainNumber

Number of domains.

uint32_t masterNumber

Number of bus masters.

uint32_t periphNumber

Number of peripherals.

uint32_t memNumber

Number of memory regions.

struct _rdc_domain_assignment

#include <fsl_rdc.h>

Master domain assignment.

Public Members

uint32_t domainId

Domain ID.

uint32_t __pad0__

Reserved.

uint32_t lock

Lock the domain assignment.

struct _rdc_periph_access_config

#include <fsl_rdc.h>

Peripheral domain access permission configuration.

Public Members

rdc_periph_t periph

Peripheral name.

bool lock

Lock the permission until reset.

bool enableSema

Enable semaphore or not, when enabled, master should call RDC_SEMA42_Lock to lock the semaphore gate accordingly before access the peripheral.

uint16_t policy

Access policy.

struct _rdc_mem_access_config

#include <fsl_rdc.h>

Memory region domain access control configuration.

Note that when setting the rdc_mem_access_config_t::baseAddress and rdc_mem_access_config_t::endAddress, should be aligned to the region resolution, see rdc_mem_t definitions.

Public Members

rdc_mem_t mem

Memory region descriptor name.

bool lock

Lock the configuration.

uint64_t baseAddress

Start address of the memory region.

uint64_t endAddress

End address of the memory region.

uint16_t policy

Access policy.

struct _rdc_mem_status

#include <fsl_rdc.h>

Memory region access violation status.

Public Members

bool hasViolation

Violating happens or not.

uint8_t domainID

Violating Domain ID.

uint64_t address

Violating Address.

RDC_SEMA42: Hardware Semaphores Driver

FSL_RDC_SEMA42_DRIVER_VERSION

RDC_SEMA42 driver version.

void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base)

Initializes the RDC_SEMA42 module.

This function initializes the RDC_SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or RDC_SEMA42_ResetAllGates function.

Parameters:

• base – RDC_SEMA42 peripheral base address.

void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base)

De-initializes the RDC_SEMA42 module.

This function de-initializes the RDC_SEMA42 module. It only disables the clock.

Parameters:

• base – RDC_SEMA42 peripheral base address.

status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)

Tries to lock the RDC_SEMA42 gate.

This function tries to lock the specific RDC_SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number to lock.

• masterIndex – Current processor master index.

• domainId – Current processor domain ID.

Return values:

• kStatus_Success – Lock the sema42 gate successfully.

• kStatus_Failed – Sema42 gate has been locked by another processor.

void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)

Locks the RDC_SEMA42 gate.

This function locks the specific RDC_SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number to lock.

• masterIndex – Current processor master index.

• domainId – Current processor domain ID.

static inline void RDC_SEMA42_Unlock(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Unlocks the RDC_SEMA42 gate.

This function unlocks the specific RDC_SEMA42 gate. It only writes unlock value to the RDC_SEMA42 gate register. However, it does not check whether the RDC_SEMA42 gate is locked by the current processor or not. As a result, if the RDC_SEMA42 gate is not locked by the current processor, this function has no effect.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number to unlock.

static inline int32_t RDC_SEMA42_GetLockMasterIndex(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Gets which master has currently locked the gate.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number.

Returns:

Return -1 if the gate is not locked by any master, otherwise return the master index.

int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Gets which domain has currently locked the gate.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number.

Returns:

Return -1 if the gate is not locked by any domain, otherwise return the domain ID.

status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Resets the RDC_SEMA42 gate to an unlocked status.

This function resets a RDC_SEMA42 gate to an unlocked status.

Parameters:

• base – RDC_SEMA42 peripheral base address.

• gateNum – Gate number.

Return values:

• kStatus_Success – RDC_SEMA42 gate is reset successfully.

• kStatus_Failed – Some other reset process is ongoing.

static inline status_t RDC_SEMA42_ResetAllGates(RDC_SEMAPHORE_Type *base)

Resets all RDC_SEMA42 gates to an unlocked status.

This function resets all RDC_SEMA42 gate to an unlocked status.

Parameters:

• base – RDC_SEMA42 peripheral base address.

Return values:

• kStatus_Success – RDC_SEMA42 is reset successfully.

• kStatus_RDC_SEMA42_Reseting – Some other reset process is ongoing.

RDC_SEMA42_GATE_NUM_RESET_ALL

The number to reset all RDC_SEMA42 gates.

RDC_SEMA42_GATEn(base, n)

RDC_SEMA42 gate n register address.

RDC_SEMA42_GATE_COUNT

RDC_SEMA42 gate count.

RDC_SEMAPHORE_GATE_GTFSM_MASK

Romapi

Flash Pad Definitions.

Values:

enumerator kSerialFlash_1Pad

1-wire communication

enumerator kSerialFlash_2Pads

2-wire communication

enumerator kSerialFlash_4Pads

4-wire communication

enumerator kSerialFlash_8Pads

8-wire communication

FLEXSPI clock configuration type.

Values:

enumerator kFLEXSPIClk_SDR

Clock configure for SDR mode

enumerator kFLEXSPIClk_DDR

Clock configure for DDR mode

enum _flexspi_read_sample_clk

FLEXSPI Read Sample Clock Source definition.

Values:

enumerator kFLEXSPIReadSampleClk_LoopbackInternally

FLEXSPI Read Sample Clock Source from the Internal loopback

enumerator kFLEXSPIReadSampleClk_LoopbackFromDqsPad

FLEXSPI Read Sample Clock Source from the Dqs Pad loopback

enumerator kFLEXSPIReadSampleClk_LoopbackFromSckPad

FLEXSPI Read Sample Clock Source from the Sck Pad loopback

enumerator kFLEXSPIReadSampleClk_ExternalInputFromDqsPad

FLEXSPI Read Sample Clock Source from the External Input by the Dqs Pad

Flash Type Definition.

Values:

enumerator kFLEXSPIDeviceType_SerialNOR

Flash device is Serial NOR

Flash Configuration Command Type.

Values:

enumerator kDeviceConfigCmdType_Generic

Generic command, for example: configure dummy cycles, drive strength, etc.

enumerator kDeviceConfigCmdType_QuadEnable

Quad Enable command

enumerator kDeviceConfigCmdType_Spi2Xpi

Switch from SPI to DPI/QPI/OPI mode

enumerator kDeviceConfigCmdType_Xpi2Spi

Switch from DPI/QPI/OPI to SPI mode

enumerator kDeviceConfigCmdType_Spi2NoCmd

Switch to 0-4-4/0-8-8 mode

enumerator kDeviceConfigCmdType_Reset

Reset device command

enum _flexspi_serial_clk_freq

Definitions for FLEXSPI Serial Clock Frequency.

Values:

enumerator kFLEXSPISerialClk_NoChange

FlexSPI serial clock no changed

enumerator kFLEXSPISerialClk_30MHz

FlexSPI serial clock 30MHz

enumerator kFLEXSPISerialClk_50MHz

FlexSPI serial clock 50MHz

enumerator kFLEXSPISerialClk_60MHz

FlexSPI serial clock 60MHz

enumerator kFLEXSPISerialClk_75MHz

FlexSPI serial clock 75MHz

enumerator kFLEXSPISerialClk_80MHz

FlexSPI serial clock 80MHz

enumerator kFLEXSPISerialClk_100MHz

FlexSPI serial clock 100MHz

enumerator kFLEXSPISerialClk_133MHz

FlexSPI serial clock 133MHz

enumerator kFLEXSPISerialClk_166MHz

FlexSPI serial clock 166MHz

Misc feature bit definitions.

Values:

enumerator kFLEXSPIMiscOffset_DiffClkEnable

Bit for Differential clock enable

enumerator kFLEXSPIMiscOffset_Ck2Enable

Bit for CK2 enable

enumerator kFLEXSPIMiscOffset_ParallelEnable

Bit for Parallel mode enable

enumerator kFLEXSPIMiscOffset_WordAddressableEnable

Bit for Word Addressable enable

enumerator kFLEXSPIMiscOffset_SafeConfigFreqEnable

Bit for Safe Configuration Frequency enable

enumerator kFLEXSPIMiscOffset_PadSettingOverrideEnable

Bit for Pad setting override enable

enumerator kFLEXSPIMiscOffset_DdrModeEnable

Bit for DDR clock configuration indication.

enumerator kFLEXSPIMiscOffset_UseValidTimeForAllFreq

Bit for DLLCR settings under all modes

Manufacturer ID.

Values:

enumerator kSerialFlash_ISSI_ManufacturerID

Manufacturer ID of the ISSI serial flash

enumerator kSerialFlash_Adesto_ManufacturerID

Manufacturer ID of the Adesto Technologies serial flash

enumerator kSerialFlash_Winbond_ManufacturerID

Manufacturer ID of the Winbond serial flash

enumerator kSerialFlash_Cypress_ManufacturerID

Manufacturer ID for Cypress

enum _flexspi_nor_status

ROM FLEXSPI NOR flash status.

Values:

enumerator kStatus_ROM_FLEXSPI_SequenceExecutionTimeout

Status for Sequence Execution timeout

enumerator kStatus_ROM_FLEXSPI_InvalidSequence

Status for Invalid Sequence

enumerator kStatus_ROM_FLEXSPI_DeviceTimeout

Status for Device timeout

enumerator kStatus_ROM_FLEXSPINOR_SFDP_NotFound

Status for SFDP read failure

enumerator kStatus_ROM_FLEXSPINOR_Flash_NotFound

Status for Flash detection failure

enumerator kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed

Status for DDR Read dummy probe failure

enum _flexspi_operation

FLEXSPI Operation Context.

Values:

enumerator kFLEXSPIOperation_Command

FLEXSPI operation: Only command, both TX and RX buffer are ignored.

enumerator kFLEXSPIOperation_Config

FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT.

enumerator kFLEXSPIOperation_Write

FLEXSPI operation: Write, only TX buffer is effective

enumerator kFLEXSPIOperation_Read

FLEXSPI operation: Read, only Rx Buffer is effective.

typedef struct _flexspi_lut_seq flexspi_lut_seq_t

FLEXSPI LUT Sequence structure.

typedef struct _flexspi_mem_config flexspi_mem_config_t

FLEXSPI Memory Configuration Block.

typedef struct _flexspi_nor_config flexspi_nor_config_t

Serial NOR configuration block.

typedef enum _flexspi_operation flexspi_operation_t

FLEXSPI Operation Context.

typedef struct _flexspi_xfer flexspi_xfer_t

FLEXSPI Transfer Context.

void ROM_API_Init(void)

ROM API init.

Get the bootloader api entry address.

kFLEXSPIOperation_End

MISRA_CAST(to_type, to_var, from_type, from_var)

convert the type for MISRA

typedef struct _serial_nor_config_option serial_nor_config_option_t

Serial NOR Configuration Option.

void ROM_RunBootloader(void *arg)

Enter Bootloader.

Parameters:

• arg – A pointer to the storage for the bootloader param. refer to System Boot Chapter in device reference manual for details.

status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option)

Get FLEXSPI NOR Configuration Block based on specified option.

Parameters:

• instance – storage the instance of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• option – A pointer to the storage Serial NOR Configuration Option Context.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)

Initialize Serial NOR devices via FLEXSPI.

This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.

Parameters:

• instance – storage the instance of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src)

Program data to Serial NOR via FLEXSPI.

This function programs the NOR flash memory with the dest address for a given flash area as determined by the dst address and the length.

Note

It is recommended that use page aligned access; If the dst_addr is not aligned to page, the driver automatically aligns address down with the page address.

Parameters:

• instance – storage the instance of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• dst_addr – A pointer to the desired flash memory to be programmed.

• src – A pointer to the source buffer of data that is to be programmed into the NOR flash.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_Read(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes)

Read data from Serial NOR via FLEXSPI.

This function read the NOR flash memory with the start address for a given flash area as determined by the dst address and the length.

Note

It is recommended that use page aligned access; If the dstAddr is not aligned to page, the driver automatically aligns address down with the page address.

Parameters:

• instance – storage the instance of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• dst – A pointer to the dest buffer of data that is to be read from the NOR flash.

• start – The start address of the desired NOR flash memory to be read.

• lengthInBytes – The length, given in bytes to be read.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)

Erase Flash Region specified by address and length.

This function erases the appropriate number of flash sectors based on the desired start address and length.

Note

It is recommended that use sector-aligned access nor device; If dstAddr is not aligned with the sector,the driver automatically aligns address down with the sector address.

Note

It is recommended that use sector-aligned access nor device; If length is not aligned with the sector,the driver automatically aligns up with the sector.

Parameters:

• instance – storage the index of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired NOR flash memory to be erased.

• length – The length, given in bytes to be erased.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)

Erase one sector specified by address.

This function erases one of NOR flash sectors based on the desired address.

Note

It is recommended that use sector-aligned access nor device; If dstAddr is not aligned with the sector, the driver automatically aligns address down with the sector address.

Parameters:

• instance – storage the index of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired NOR flash memory to be erased.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)

Erase one block specified by address.

This function erases one block of NOR flash based on the desired address.

Note

It is recommended that use block-aligned access nor device; If dstAddr is not aligned with the block, the driver automatically aligns address down with the block address.

Parameters:

• instance – storage the index of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired NOR flash memory to be erased.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config)

Erase all the Serial NOR devices connected on FLEXSPI.

Parameters:

• instance – storage the instance of FLEXSPI.

• config – A pointer to the storage for the driver runtime state.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout

status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)

FLEXSPI command.

This function is used to perform the command write sequence to the NOR device.

Parameters:

• instance – storage the index of FLEXSPI.

• xfer – A pointer to the storage FLEXSPI Transfer Context.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber)

Configure FLEXSPI Lookup table.

Parameters:

• instance – storage the index of FLEXSPI.

• seqIndex – storage the sequence Id.

• lutBase – A pointer to the look-up-table for command sequences.

• seqNumber – storage sequence number.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address)

Wait until device is idle.

Parameters:

• instance – Indicates the index of FLEXSPI.

• config – A pointer to the storage for the driver runtime state

• isParallelMode – Indicates whether NOR flash is in parallel mode.

• address – Indicates the operation(erase/program/read) address for serial NOR flash.

Return values:

• kStatus_Success – Api was executed successfully.

• kStatus_InvalidArgument – A invalid argument is provided.

• kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.

• kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.

• kStatus_ROM_FLEXSPI_DeviceTimeout – Device timeout.

void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)

Software reset for the FLEXSPI logic.

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

Parameters:

• instance – storage the index of FLEXSPI.

FSL_ROM_HAS_FLEXSPINOR_API

ROM has FLEXSPI NOR API.

FSL_ROM_HAS_RUNBOOTLOADER_API

ROM has run bootloader API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG

ROM has FLEXSPI NOR get config API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT

ROM has flash init API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE

ROM has erase API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR

ROM has erase sector API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK

ROM has erase block API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL

ROM has erase all API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ

ROM has read API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT

ROM has update lut API.

FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER

ROM has FLEXSPI command API.

kROM_StatusGroup_FLEXSPINOR

ROM FLEXSPI NOR status group number.

FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)

FSL_ROM_FLEXSPI_BITMASK(bit_offset)

Generate bit mask.

FLEXSPI_CFG_BLK_TAG

FLEXSPI memory config block related definitions.

ascii “FCFB” Big Endian

FLEXSPI_CFG_BLK_VERSION

V1.4.0

CMD_SDR

CMD_DDR

RADDR_SDR

RADDR_DDR

CADDR_SDR

CADDR_DDR

MODE1_SDR

MODE1_DDR

MODE2_SDR

MODE2_DDR

MODE4_SDR

MODE4_DDR

MODE8_SDR

MODE8_DDR

WRITE_SDR

WRITE_DDR

READ_SDR

READ_DDR

LEARN_SDR

LEARN_DDR

DATSZ_SDR

DATSZ_DDR

DUMMY_SDR

DUMMY_DDR

DUMMY_RWDS_SDR

DUMMY_RWDS_DDR

JMP_ON_CS

STOP

FLEXSPI_1PAD

FLEXSPI_2PAD

FLEXSPI_4PAD

FLEXSPI_8PAD

NOR_CMD_LUT_SEQ_IDX_READ

NOR LUT sequence index used for default LUT assignment.

Note

It will take effect if the lut sequences are not customized. READ LUT sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_READSTATUS

Read Status LUT sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI

Read status DPI/QPI/OPI sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_WRITEENABLE

Write Enable sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI

Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_ERASESECTOR

Erase Sector sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_READID

NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK

Erase Block sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM

Program sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_CHIPERASE

Chip Erase sequence in lookupTable id stored in config block

NOR_CMD_LUT_SEQ_IDX_READ_SFDP

Read SFDP sequence in lookupTable id stored in config block

NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD

Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block

NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD

Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block

uint32_t max_freq

Maximum supported Frequency

uint32_t misc_mode

miscellaneous mode

uint32_t quad_mode_setting

Quad mode setting

uint32_t cmd_pads

Command pads

uint32_t query_pads

SFDP read pads

uint32_t device_type

Device type

uint32_t option_size

Option size, in terms of uint32_t, size = (option_size + 1) * 4

uint32_t tag

Tag, must be 0x0E

struct _serial_nor_config_option B

uint32_t U

union _serial_nor_config_option option0

uint32_t dummy_cycles

Dummy cycles before read

uint32_t status_override

Override status register value during device mode configuration

uint32_t pinmux_group

The pinmux group selection

uint32_t dqs_pinmux_group

The DQS Pinmux Group Selection

uint32_t drive_strength

The Drive Strength of FlexSPI Pads

uint32_t flash_connection

Flash connection option: 0 - Single Flash connected to port A, 1 - Parallel mode, 2 - Single Flash connected to Port B

struct _serial_nor_config_option B

uint32_t U

union _serial_nor_config_option option1

uint8_t seqNum

Sequence Number, valid number: 1-16

uint8_t seqId

Sequence Index, valid number: 0-15

uint16_t reserved

uint8_t time_100ps

Data valid time, in terms of 100ps

uint8_t delay_cells

Data valid time, in terms of delay cells

uint32_t tag

[0x000-0x003] Tag, fixed value 0x42464346UL

uint32_t version

[0x004-0x007] Version,[31:24] -‘V’, [23:16] - Major, [15:8] - Minor, [7:0] - bugfix

uint32_t reserved0

[0x008-0x00b] Reserved for future use

uint8_t readSampleClkSrc

[0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3

uint8_t csHoldTime

[0x00d-0x00d] Data hold time, default value: 3

uint8_t csSetupTime

[0x00e-0x00e] Date setup time, default value: 3

uint8_t columnAddressWidth

[0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet

uint8_t deviceModeCfgEnable

[0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable

uint8_t deviceModeType

[0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.

uint16_t waitTimeCfgCommands

[0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command

flexspi_lut_seq_t deviceModeSeq

[0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved

uint32_t deviceModeArg

[0x018-0x01b] Argument/Parameter for device configuration

uint8_t configCmdEnable

[0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable

uint8_t configModeType[3]

[0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

flexspi_lut_seq_t configCmdSeqs[3]

[0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

uint32_t reserved1

[0x02c-0x02f] Reserved for future use

uint32_t configCmdArgs[3]

[0x030-0x03b] Arguments/Parameters for device Configuration commands

uint32_t reserved2

[0x03c-0x03f] Reserved for future use

uint32_t controllerMiscOption

[0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details

uint8_t deviceType

[0x044-0x044] Device Type: See Flash Type Definition for more details

uint8_t sflashPadType

[0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal

uint8_t serialClkFreq

[0x046-0x046] Serial Flash Frequency, device specific definitions. See System Boot Chapter for more details

uint8_t lutCustomSeqEnable

[0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH

uint32_t reserved3[2]

[0x048-0x04f] Reserved for future use

uint32_t sflashA1Size

[0x050-0x053] Size of Flash connected to A1

uint32_t sflashA2Size

[0x054-0x057] Size of Flash connected to A2

uint32_t sflashB1Size

[0x058-0x05b] Size of Flash connected to B1

uint32_t sflashB2Size

[0x05c-0x05f] Size of Flash connected to B2

uint32_t csPadSettingOverride

[0x060-0x063] CS pad setting override value

uint32_t sclkPadSettingOverride

[0x064-0x067] SCK pad setting override value

uint32_t dataPadSettingOverride

[0x068-0x06b] data pad setting override value

uint32_t dqsPadSettingOverride

[0x06c-0x06f] DQS pad setting override value

uint32_t timeoutInMs

[0x070-0x073] Timeout threshold for read status command

uint32_t commandInterval

[0x074-0x077] CS deselect interval between two commands

flexspi_dll_time_t dataValidTime[2]

[0x078-0x07b] CLK edge to data valid time for PORT A and PORT B

uint16_t busyOffset

[0x07c-0x07d] Busy offset, valid value: 0-31

uint16_t busyBitPolarity

[0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy

uint32_t lookupTable[64]

[0x080-0x17f] Lookup table holds Flash command sequences

flexspi_lut_seq_t lutCustomSeq[12]

[0x180-0x1af] Customizable LUT Sequences

uint32_t reserved4[4]

[0x1b0-0x1bf] Reserved for future use

flexspi_mem_config_t memConfig

Common memory configuration info via FLEXSPI

uint32_t pageSize

Page size of Serial NOR

uint32_t sectorSize

Sector size of Serial NOR

uint8_t ipcmdSerialClkFreq

Clock frequency for IP command

uint8_t isUniformBlockSize

Sector/Block size is the same

uint8_t isDataOrderSwapped

Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)

uint8_t reserved0[1]

Reserved for future use

uint8_t serialNorType

Serial NOR Flash type: 0/1/2/3

uint8_t needExitNoCmdMode

Need to exit NoCmd mode before other IP command

uint8_t halfClkForNonReadCmd

Half the Serial Clock for non-read command: true/false

uint8_t needRestoreNoCmdMode

Need to Restore NoCmd mode after IP command execution

uint32_t blockSize

Block size

uint32_t reserve2[11]

Reserved for future use

flexspi_operation_t operation

FLEXSPI operation

uint32_t baseAddress

FLEXSPI operation base address

uint32_t seqId

Sequence Id

uint32_t seqNum

Sequence Number

bool isParallelModeEnable

Is a parallel transfer

uint32_t *txBuffer

Tx buffer

uint32_t txSize

Tx size in bytes

uint32_t *rxBuffer

Rx buffer

uint32_t rxSize

Rx size in bytes

FSL_ROM_ROMAPI_VERSION

ROM API version 1.1.1.

FSL_ROM_FLEXSPINOR_DRIVER_VERSION

ROM FLEXSPI NOR driver version 1.7.0.

struct _serial_nor_config_option

#include <fsl_romapi.h>

Serial NOR Configuration Option.

struct _flexspi_lut_seq

#include <fsl_romapi.h>

FLEXSPI LUT Sequence structure.

struct flexspi_dll_time_t

#include <fsl_romapi.h>

FLEXSPI DLL time.

struct _flexspi_mem_config

#include <fsl_romapi.h>

FLEXSPI Memory Configuration Block.

struct _flexspi_nor_config

#include <fsl_romapi.h>

Serial NOR configuration block.

struct _flexspi_xfer

#include <fsl_romapi.h>

FLEXSPI Transfer Context.

union option0

Public Members

struct _serial_nor_config_option B

uint32_t U

struct B

Public Members

uint32_t max_freq

Maximum supported Frequency

uint32_t misc_mode

miscellaneous mode

uint32_t quad_mode_setting

Quad mode setting

uint32_t cmd_pads

Command pads

uint32_t query_pads

SFDP read pads

uint32_t device_type

Device type

uint32_t option_size

Option size, in terms of uint32_t, size = (option_size + 1) * 4

uint32_t tag

Tag, must be 0x0E

union option1

Public Members

struct _serial_nor_config_option B

uint32_t U

struct B

Public Members

uint32_t dummy_cycles

Dummy cycles before read

uint32_t status_override

Override status register value during device mode configuration

uint32_t pinmux_group

The pinmux group selection

uint32_t dqs_pinmux_group

The DQS Pinmux Group Selection

uint32_t drive_strength

The Drive Strength of FlexSPI Pads

uint32_t flash_connection

Flash connection option: 0 - Single Flash connected to port A, 1 - Parallel mode, 2 - Single Flash connected to Port B

RTWDOG: 32-bit Watchdog Timer

void RTWDOG_GetDefaultConfig(rtwdog_config_t *config)

Initializes the RTWDOG configuration structure.

This function initializes the RTWDOG configuration structure to default values. The default values are:

rtwdogConfig->enableRtwdog = true;
rtwdogConfig->clockSource = kRTWDOG_ClockSource1;
rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1;
rtwdogConfig->workMode.enableWait = true;
rtwdogConfig->workMode.enableStop = false;
rtwdogConfig->workMode.enableDebug = false;
rtwdogConfig->testMode = kRTWDOG_TestModeDisabled;
rtwdogConfig->enableUpdate = true;
rtwdogConfig->enableInterrupt = false;
rtwdogConfig->enableWindowMode = false;
rtwdogConfig->windowValue = 0U;
rtwdogConfig->timeoutValue = 0xFFFFU;

See also

rtwdog_config_t

Parameters:

• config – Pointer to the RTWDOG configuration structure.

AT_QUICKACCESS_SECTION_CODE (void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config))

Initializes the RTWDOG module.

This function initializes the RTWDOG. To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true in the configuration.

Example:

rtwdog_config_t config;
RTWDOG_GetDefaultConfig(&config);
config.timeoutValue = 0x7ffU;
config.enableUpdate = true;
RTWDOG_Init(wdog_base,&config);

Parameters:

• base – RTWDOG peripheral base address.

• config – The configuration of the RTWDOG.

void RTWDOG_Deinit(RTWDOG_Type *base)

De-initializes the RTWDOG module.

This function shuts down the RTWDOG. Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.

Parameters:

• base – RTWDOG peripheral base address.

static inline void RTWDOG_Enable(RTWDOG_Type *base)

Enables the RTWDOG module.

This function writes a value into the WDOG_CS register to enable the RTWDOG. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address.

static inline void RTWDOG_Disable(RTWDOG_Type *base)

Disables the RTWDOG module.

This function writes a value into the WDOG_CS register to disable the RTWDOG. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address

static inline void RTWDOG_EnableInterrupts(RTWDOG_Type *base, uint32_t mask)

Enables the RTWDOG interrupt.

This function writes a value into the WDOG_CS register to enable the RTWDOG interrupt. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address.

• mask – The interrupts to enable. The parameter can be a combination of the following source if defined:

  • kRTWDOG_InterruptEnable

static inline void RTWDOG_DisableInterrupts(RTWDOG_Type *base, uint32_t mask)

Disables the RTWDOG interrupt.

This function writes a value into the WDOG_CS register to disable the RTWDOG interrupt. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address.

• mask – The interrupts to disabled. The parameter can be a combination of the following source if defined:

  • kRTWDOG_InterruptEnable

static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base)

Gets the RTWDOG all status flags.

This function gets all status flags.

Example to get the running flag:

uint32_t status;
status = RTWDOG_GetStatusFlags(wdog_base) & kRTWDOG_RunningFlag;

See also

_rtwdog_status_flags_t

• true: related status flag has been set.

• false: related status flag is not set.

Parameters:

• base – RTWDOG peripheral base address

Returns:

State of the status flag: asserted (true) or not-asserted (false).

static inline void RTWDOG_EnableWindowMode(RTWDOG_Type *base, bool enable)

Enables/disables the window mode.

Parameters:

• base – RTWDOG peripheral base address.

• enable – Enables(true) or disables(false) the feature.

static inline uint32_t RTWDOG_CountToMesec(RTWDOG_Type *base, uint32_t count, uint32_t clockFreqInHz)

Converts raw count value to millisecond.

Note that if the clock frequency is too high the timeout period can be less than 1 ms. In this case this api will return 0 value.

Parameters:

• base – RTWDOG peripheral base address.

• count – Raw count value.

• clockFreqInHz – The frequency of the clock source RTWDOG uses.

Returns:

Return converted time. Will return 0 if result is larger than 0xFFFFFFFF.

void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask)

Clears the RTWDOG flag.

This function clears the RTWDOG status flag.

Example to clear an interrupt flag:

RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag);

Parameters:

• base – RTWDOG peripheral base address.

• mask – The status flags to clear. The parameter can be any combination of the following values:

  • kRTWDOG_InterruptFlag

static inline void RTWDOG_SetTimeoutValue(RTWDOG_Type *base, uint16_t timeoutCount)

Sets the RTWDOG timeout value.

This function writes a timeout value into the WDOG_TOVAL register. The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address

• timeoutCount – RTWDOG timeout value, count of RTWDOG clock ticks.

static inline void RTWDOG_SetWindowValue(RTWDOG_Type *base, uint16_t windowValue)

Sets the RTWDOG window value.

This function writes a window value into the WDOG_WIN register. The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

• base – RTWDOG peripheral base address.

• windowValue – RTWDOG window value.

__STATIC_FORCEINLINE void RTWDOG_Unlock (RTWDOG_Type *base)

Unlocks the RTWDOG register written.

This function unlocks the RTWDOG register written.

Before starting the unlock sequence and following the configuration, disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. After the configuration finishes, re-enable the global interrupts.

Parameters:

• base – RTWDOG peripheral base address

static inline void RTWDOG_Refresh(RTWDOG_Type *base)

Refreshes the RTWDOG timer.

This function feeds the RTWDOG. This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted.

Parameters:

• base – RTWDOG peripheral base address

static inline uint32_t RTWDOG_GetCounterValue(RTWDOG_Type *base)

Gets the RTWDOG counter value.

This function gets the RTWDOG counter value.

Parameters:

• base – RTWDOG peripheral base address.

Returns:

Current RTWDOG counter value.

WDOG_FIRST_WORD_OF_UNLOCK

First word of unlock sequence

WDOG_SECOND_WORD_OF_UNLOCK

Second word of unlock sequence

WDOG_FIRST_WORD_OF_REFRESH

First word of refresh sequence

WDOG_SECOND_WORD_OF_REFRESH

Second word of refresh sequence

FSL_RTWDOG_DRIVER_VERSION

RTWDOG driver version.

enum _rtwdog_clock_source

Describes RTWDOG clock source.

Values:

enumerator kRTWDOG_ClockSource0

Clock source 0

enumerator kRTWDOG_ClockSource1

Clock source 1

enumerator kRTWDOG_ClockSource2

Clock source 2

enumerator kRTWDOG_ClockSource3

Clock source 3

enum _rtwdog_clock_prescaler

Describes the selection of the clock prescaler.

Values:

enumerator kRTWDOG_ClockPrescalerDivide1

Divided by 1

enumerator kRTWDOG_ClockPrescalerDivide256

Divided by 256

enum _rtwdog_test_mode

Describes RTWDOG test mode.

Values:

enumerator kRTWDOG_TestModeDisabled

Test Mode disabled

enumerator kRTWDOG_UserModeEnabled

User Mode enabled

enumerator kRTWDOG_LowByteTest

Test Mode enabled, only low byte is used

enumerator kRTWDOG_HighByteTest

Test Mode enabled, only high byte is used

enum _rtwdog_interrupt_enable_t

RTWDOG interrupt configuration structure.

This structure contains the settings for all of the RTWDOG interrupt configurations.

Values:

enumerator kRTWDOG_InterruptEnable

Interrupt is generated before forcing a reset

enum _rtwdog_status_flags_t

RTWDOG status flags.

This structure contains the RTWDOG status flags for use in the RTWDOG functions.

Values:

enumerator kRTWDOG_RunningFlag

Running flag, set when RTWDOG is enabled

enumerator kRTWDOG_InterruptFlag

Interrupt flag, set when interrupt occurs

typedef enum _rtwdog_clock_source rtwdog_clock_source_t

Describes RTWDOG clock source.

typedef enum _rtwdog_clock_prescaler rtwdog_clock_prescaler_t

Describes the selection of the clock prescaler.

typedef struct _rtwdog_work_mode rtwdog_work_mode_t

Defines RTWDOG work mode.

typedef enum _rtwdog_test_mode rtwdog_test_mode_t

Describes RTWDOG test mode.

typedef struct _rtwdog_config rtwdog_config_t

Describes RTWDOG configuration structure.

struct _rtwdog_work_mode

#include <fsl_rtwdog.h>

Defines RTWDOG work mode.

Public Members

bool enableWait

Enables or disables RTWDOG in wait mode

bool enableStop

Enables or disables RTWDOG in stop mode

bool enableDebug

Enables or disables RTWDOG in debug mode

struct _rtwdog_config

#include <fsl_rtwdog.h>

Describes RTWDOG configuration structure.

Public Members

bool enableRtwdog

Enables or disables RTWDOG

rtwdog_clock_source_t clockSource

Clock source select

rtwdog_clock_prescaler_t prescaler

Clock prescaler value

rtwdog_work_mode_t workMode

Configures RTWDOG work mode in debug stop and wait mode

rtwdog_test_mode_t testMode

Configures RTWDOG test mode

bool enableUpdate

Update write-once register enable

bool enableInterrupt

Enables or disables RTWDOG interrupt

bool enableWindowMode

Enables or disables RTWDOG window mode

uint16_t windowValue

Window value

uint16_t timeoutValue

Timeout value

SAI: Serial Audio Interface

SAI Driver

void SAI_Init(I2S_Type *base)

Initializes the SAI peripheral.

This API gates the SAI clock. The SAI module can’t operate unless SAI_Init is called to enable the clock.

Parameters:

• base – SAI base pointer.

void SAI_Deinit(I2S_Type *base)

De-initializes the SAI peripheral.

This API gates the SAI clock. The SAI module can’t operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.

Parameters:

• base – SAI base pointer.

void SAI_TxReset(I2S_Type *base)

Resets the SAI Tx.

This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.

Parameters:

• base – SAI base pointer

void SAI_RxReset(I2S_Type *base)

Resets the SAI Rx.

This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.

Parameters:

• base – SAI base pointer

void SAI_TxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Tx.

Parameters:

• base – SAI base pointer.

• enable – True means enable SAI Tx, false means disable.

void SAI_RxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Rx.

Parameters:

• base – SAI base pointer.

• enable – True means enable SAI Rx, false means disable.

static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction.

Select bit clock direction, master or slave.

Parameters:

• base – SAI base pointer.

• masterSlave – reference sai_master_slave_t.

static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction.

Select bit clock direction, master or slave.

Parameters:

• base – SAI base pointer.

• masterSlave – reference sai_master_slave_t.

static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx frame sync direction.

Select frame sync direction, master or slave.

Parameters:

• base – SAI base pointer.

• masterSlave – reference sai_master_slave_t.

static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Tx frame sync direction.

Select frame sync direction, master or slave.

Parameters:

• base – SAI base pointer.

• masterSlave – reference sai_master_slave_t.

void SAI_TxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Transmitter bit clock rate configurations.

Parameters:

• base – SAI base pointer.

• sourceClockHz – Bit clock source frequency.

• sampleRate – Audio data sample rate.

• bitWidth – Audio data bitWidth.

• channelNumbers – Audio channel numbers.

void SAI_RxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Receiver bit clock rate configurations.

Parameters:

• base – SAI base pointer.

• sourceClockHz – Bit clock source frequency.

• sampleRate – Audio data sample rate.

• bitWidth – Audio data bitWidth.

• channelNumbers – Audio channel numbers.

void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Transmitter Bit clock configurations.

Parameters:

• base – SAI base pointer.

• masterSlave – master or slave.

• config – bit clock other configurations, can be NULL in slave mode.

void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Receiver Bit clock configurations.

Parameters:

• base – SAI base pointer.

• masterSlave – master or slave.

• config – bit clock other configurations, can be NULL in slave mode.

void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)

Master clock configurations.

Parameters:

• base – SAI base pointer.

• config – master clock configurations.

void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI transmitter fifo configurations.

Parameters:

• base – SAI base pointer.

• config – fifo configurations.

void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI receiver fifo configurations.

Parameters:

• base – SAI base pointer.

• config – fifo configurations.

void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI transmitter Frame sync configurations.

Parameters:

• base – SAI base pointer.

• masterSlave – master or slave.

• config – frame sync configurations, can be NULL in slave mode.

void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI receiver Frame sync configurations.

Parameters:

• base – SAI base pointer.

• masterSlave – master or slave.

• config – frame sync configurations, can be NULL in slave mode.

void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI transmitter Serial data configurations.

Parameters:

• base – SAI base pointer.

• config – serial data configurations.

void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI receiver Serial data configurations.

Parameters:

• base – SAI base pointer.

• config – serial data configurations.

void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI transmitter configurations.

Parameters:

• base – SAI base pointer.

• config – transmitter configurations.

void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI receiver configurations.

Parameters:

• base – SAI base pointer.

• config – receiver configurations.

void SAI_GetClassicI2SConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get classic I2S mode configurations.

Parameters:

• config – transceiver configurations.

• bitWidth – audio data bitWidth.

• mode – audio data channel.

• saiChannelMask – mask value of the channel to be enable.

void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get left justified mode configurations.

Parameters:

• config – transceiver configurations.

• bitWidth – audio data bitWidth.

• mode – audio data channel.

• saiChannelMask – mask value of the channel to be enable.

void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get right justified mode configurations.

Parameters:

• config – transceiver configurations.

• bitWidth – audio data bitWidth.

• mode – audio data channel.

• saiChannelMask – mask value of the channel to be enable.

void SAI_GetTDMConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)

Get TDM mode configurations.

Parameters:

• config – transceiver configurations.

• frameSyncWidth – length of frame sync.

• bitWidth – audio data word width.

• dataWordNum – word number in one frame.

• saiChannelMask – mask value of the channel to be enable.

void SAI_GetDSPConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get DSP mode configurations.

DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:

SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
SAI_TxSetConfig(base, config)

Note

DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:

SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
config->frameSync.frameSyncEarly    = true;
SAI_TxSetConfig(base, config)

Parameters:

• config – transceiver configurations.

• frameSyncWidth – length of frame sync.

• bitWidth – audio data bitWidth.

• mode – audio data channel.

• saiChannelMask – mask value of the channel to enable.

static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state.

Parameters:

• base – SAI base pointer

Returns:

SAI Tx status flag value. Use the Status Mask to get the status value needed.

static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Tx status flag state.

Parameters:

• base – SAI base pointer

• mask – State mask. It can be a combination of the following source if defined:

  • kSAI_WordStartFlag

  • kSAI_SyncErrorFlag

  • kSAI_FIFOErrorFlag

static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state.

Parameters:

• base – SAI base pointer

Returns:

SAI Rx status flag value. Use the Status Mask to get the status value needed.

static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Rx status flag state.

Parameters:

• base – SAI base pointer

• mask – State mask. It can be a combination of the following sources if defined.

  • kSAI_WordStartFlag

  • kSAI_SyncErrorFlag

  • kSAI_FIFOErrorFlag

void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset .

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

• base – SAI base pointer

• resetType – Reset type, FIFO reset or software reset

void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset .

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

• base – SAI base pointer

• resetType – Reset type, FIFO reset or software reset

void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Tx channel FIFO enable mask.

Parameters:

• base – SAI base pointer

• mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.

void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Rx channel FIFO enable mask.

Parameters:

• base – SAI base pointer

• mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.

void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Tx data order.

Parameters:

• base – SAI base pointer

• order – Data order MSB or LSB

void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Rx data order.

Parameters:

• base – SAI base pointer

• order – Data order MSB or LSB

void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order.

Parameters:

• base – SAI base pointer

• polarity –

void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order.

Parameters:

• base – SAI base pointer

• polarity –

void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order.

Parameters:

• base – SAI base pointer

• polarity –

void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order.

Parameters:

• base – SAI base pointer

• polarity –

void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Tx FIFO packing feature.

Parameters:

• base – SAI base pointer.

• pack – FIFO pack type. It is element of sai_fifo_packing_t.

void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Rx FIFO packing feature.

Parameters:

• base – SAI base pointer.

• pack – FIFO pack type. It is element of sai_fifo_packing_t.

static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Tx FIFO error continue.

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.

Parameters:

• base – SAI base pointer.

• isEnabled – Is FIFO error continue enabled, true means enable, false means disable.

static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Rx FIFO error continue.

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.

Parameters:

• base – SAI base pointer.

• isEnabled – Is FIFO error continue enabled, true means enable, false means disable.

static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Tx interrupt requests.

Parameters:

• base – SAI base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSAI_WordStartInterruptEnable

  • kSAI_SyncErrorInterruptEnable

  • kSAI_FIFOWarningInterruptEnable

  • kSAI_FIFORequestInterruptEnable

  • kSAI_FIFOErrorInterruptEnable

static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Rx interrupt requests.

Parameters:

• base – SAI base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSAI_WordStartInterruptEnable

  • kSAI_SyncErrorInterruptEnable

  • kSAI_FIFOWarningInterruptEnable

  • kSAI_FIFORequestInterruptEnable

  • kSAI_FIFOErrorInterruptEnable

static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Tx interrupt requests.

Parameters:

• base – SAI base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSAI_WordStartInterruptEnable

  • kSAI_SyncErrorInterruptEnable

  • kSAI_FIFOWarningInterruptEnable

  • kSAI_FIFORequestInterruptEnable

  • kSAI_FIFOErrorInterruptEnable

static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Rx interrupt requests.

Parameters:

• base – SAI base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSAI_WordStartInterruptEnable

  • kSAI_SyncErrorInterruptEnable

  • kSAI_FIFOWarningInterruptEnable

  • kSAI_FIFORequestInterruptEnable

  • kSAI_FIFOErrorInterruptEnable

static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Tx DMA requests.

Parameters:

• base – SAI base pointer

• mask – DMA source The parameter can be combination of the following sources if defined.

  • kSAI_FIFOWarningDMAEnable

  • kSAI_FIFORequestDMAEnable

• enable – True means enable DMA, false means disable DMA.

static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Rx DMA requests.

Parameters:

• base – SAI base pointer

• mask – DMA source The parameter can be a combination of the following sources if defined.

  • kSAI_FIFOWarningDMAEnable

  • kSAI_FIFORequestDMAEnable

• enable – True means enable DMA, false means disable DMA.

static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Tx data register address.

This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

• base – SAI base pointer.

• channel – Which data channel used.

Returns:

data register address.

static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Rx data register address.

This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

• base – SAI base pointer.

• channel – Which data channel used.

Returns:

data register address.

void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

• bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.

• buffer – Pointer to the data to be written.

• size – Bytes to be written.

void SAI_WriteMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data to multi channel using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

• channelMask – channel mask.

• bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.

• buffer – Pointer to the data to be written.

• size – Bytes to be written.

static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)

Writes data into SAI FIFO.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

• data – Data needs to be written.

void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

• bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.

• buffer – Pointer to the data to be read.

• size – Bytes to be read.

void SAI_ReadMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives multi channel data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

• channelMask – channel mask.

• bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.

• buffer – Pointer to the data to be read.

• size – Bytes to be read.

static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)

Reads data from the SAI FIFO.

Parameters:

• base – SAI base pointer.

• channel – Data channel used.

Returns:

Data in SAI FIFO.

void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Tx handle.

This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – SAI base pointer

• handle – SAI handle pointer.

• callback – Pointer to the user callback function.

• userData – User parameter passed to the callback function

void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Rx handle.

This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – SAI base pointer.

• handle – SAI handle pointer.

• callback – Pointer to the user callback function.

• userData – User parameter passed to the callback function.

void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI transmitter transfer configurations.

This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

• base – SAI base pointer.

• handle – SAI handle pointer.

• config – tranmitter configurations.

void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI receiver transfer configurations.

This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

• base – SAI base pointer.

• handle – SAI handle pointer.

• config – receiver configurations.

status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on SAI.

Note

This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

• xfer – Pointer to the sai_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_SAI_TxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on SAI.

Note

This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.

Parameters:

• base – SAI base pointer

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

• xfer – Pointer to the sai_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_SAI_RxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a set byte count.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

• count – Bytes count sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a received byte count.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

• count – Bytes count received.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)

Aborts the current send.

Note

This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)

Aborts the current IRQ receive.

Note

This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – SAI base pointer

• handle – Pointer to the sai_handle_t structure which stores the transfer state.

void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI send.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI receive.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure.

void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler.

Parameters:

• base – SAI base pointer.

• handle – Pointer to the sai_handle_t structure.

FSL_SAI_DRIVER_VERSION

Version 2.4.4

_sai_status_t, SAI return status.

Values:

enumerator kStatus_SAI_TxBusy

SAI Tx is busy.

enumerator kStatus_SAI_RxBusy

SAI Rx is busy.

enumerator kStatus_SAI_TxError

SAI Tx FIFO error.

enumerator kStatus_SAI_RxError

SAI Rx FIFO error.

enumerator kStatus_SAI_QueueFull

SAI transfer queue is full.

enumerator kStatus_SAI_TxIdle

SAI Tx is idle

enumerator kStatus_SAI_RxIdle

SAI Rx is idle

_sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific

Values:

enumerator kSAI_Channel0Mask

channel 0 mask value

enumerator kSAI_Channel1Mask

channel 1 mask value

enumerator kSAI_Channel2Mask

channel 2 mask value

enumerator kSAI_Channel3Mask

channel 3 mask value

enumerator kSAI_Channel4Mask

channel 4 mask value

enumerator kSAI_Channel5Mask

channel 5 mask value

enumerator kSAI_Channel6Mask

channel 6 mask value

enumerator kSAI_Channel7Mask

channel 7 mask value

enum _sai_protocol

Define the SAI bus type.

Values:

enumerator kSAI_BusLeftJustified

Uses left justified format.

enumerator kSAI_BusRightJustified

Uses right justified format.

enumerator kSAI_BusI2S

Uses I2S format.

enumerator kSAI_BusPCMA

Uses I2S PCM A format.

enumerator kSAI_BusPCMB

Uses I2S PCM B format.

enum _sai_master_slave

Master or slave mode.

Values:

enumerator kSAI_Master

Master mode include bclk and frame sync

enumerator kSAI_Slave

Slave mode include bclk and frame sync

enumerator kSAI_Bclk_Master_FrameSync_Slave

bclk in master mode, frame sync in slave mode

enumerator kSAI_Bclk_Slave_FrameSync_Master

bclk in slave mode, frame sync in master mode

enum _sai_mono_stereo

Mono or stereo audio format.

Values:

enumerator kSAI_Stereo

Stereo sound.

enumerator kSAI_MonoRight

Only Right channel have sound.

enumerator kSAI_MonoLeft

Only left channel have sound.

enum _sai_data_order

SAI data order, MSB or LSB.

Values:

enumerator kSAI_DataLSB

LSB bit transferred first

enumerator kSAI_DataMSB

MSB bit transferred first

enum _sai_clock_polarity

SAI clock polarity, active high or low.

Values:

enumerator kSAI_PolarityActiveHigh

Drive outputs on rising edge

enumerator kSAI_PolarityActiveLow

Drive outputs on falling edge

enumerator kSAI_SampleOnFallingEdge

Sample inputs on falling edge

enumerator kSAI_SampleOnRisingEdge

Sample inputs on rising edge

enum _sai_sync_mode

Synchronous or asynchronous mode.

Values:

enumerator kSAI_ModeAsync

Asynchronous mode

enumerator kSAI_ModeSync

Synchronous mode (with receiver or transmit)

enumerator kSAI_ModeSyncWithOtherTx

Synchronous with another SAI transmit

enumerator kSAI_ModeSyncWithOtherRx

Synchronous with another SAI receiver

enum _sai_bclk_source

Bit clock source.

Values:

enumerator kSAI_BclkSourceBusclk

Bit clock using bus clock

enumerator kSAI_BclkSourceMclkOption1

Bit clock MCLK option 1

enumerator kSAI_BclkSourceMclkOption2

Bit clock MCLK option2

enumerator kSAI_BclkSourceMclkOption3

Bit clock MCLK option3

enumerator kSAI_BclkSourceMclkDiv

Bit clock using master clock divider

enumerator kSAI_BclkSourceOtherSai0

Bit clock from other SAI device

enumerator kSAI_BclkSourceOtherSai1

Bit clock from other SAI device

_sai_interrupt_enable_t, The SAI interrupt enable flag

Values:

enumerator kSAI_WordStartInterruptEnable

Word start flag, means the first word in a frame detected

enumerator kSAI_SyncErrorInterruptEnable

Sync error flag, means the sync error is detected

enumerator kSAI_FIFOWarningInterruptEnable

FIFO warning flag, means the FIFO is empty

enumerator kSAI_FIFOErrorInterruptEnable

FIFO error flag

enumerator kSAI_FIFORequestInterruptEnable

FIFO request, means reached watermark

_sai_dma_enable_t, The DMA request sources

Values:

enumerator kSAI_FIFOWarningDMAEnable

FIFO warning caused by the DMA request

enumerator kSAI_FIFORequestDMAEnable

FIFO request caused by the DMA request

_sai_flags, The SAI status flag

Values:

enumerator kSAI_WordStartFlag

Word start flag, means the first word in a frame detected

enumerator kSAI_SyncErrorFlag

Sync error flag, means the sync error is detected

enumerator kSAI_FIFOErrorFlag

FIFO error flag

enumerator kSAI_FIFORequestFlag

FIFO request flag.

enumerator kSAI_FIFOWarningFlag

FIFO warning flag

enum _sai_reset_type

The reset type.

Values:

enumerator kSAI_ResetTypeSoftware

Software reset, reset the logic state

enumerator kSAI_ResetTypeFIFO

FIFO reset, reset the FIFO read and write pointer

enumerator kSAI_ResetAll

All reset.

enum _sai_fifo_packing

The SAI packing mode The mode includes 8 bit and 16 bit packing.

Values:

enumerator kSAI_FifoPackingDisabled

Packing disabled

enumerator kSAI_FifoPacking8bit

8 bit packing enabled

enumerator kSAI_FifoPacking16bit

16bit packing enabled

enum _sai_sample_rate

Audio sample rate.

Values:

enumerator kSAI_SampleRate8KHz

Sample rate 8000 Hz

enumerator kSAI_SampleRate11025Hz

Sample rate 11025 Hz

enumerator kSAI_SampleRate12KHz

Sample rate 12000 Hz

enumerator kSAI_SampleRate16KHz

Sample rate 16000 Hz

enumerator kSAI_SampleRate22050Hz

Sample rate 22050 Hz

enumerator kSAI_SampleRate24KHz

Sample rate 24000 Hz

enumerator kSAI_SampleRate32KHz

Sample rate 32000 Hz

enumerator kSAI_SampleRate44100Hz

Sample rate 44100 Hz

enumerator kSAI_SampleRate48KHz

Sample rate 48000 Hz

enumerator kSAI_SampleRate96KHz

Sample rate 96000 Hz

enumerator kSAI_SampleRate192KHz

Sample rate 192000 Hz

enumerator kSAI_SampleRate384KHz

Sample rate 384000 Hz

enum _sai_word_width

Audio word width.

Values:

enumerator kSAI_WordWidth8bits

Audio data width 8 bits

enumerator kSAI_WordWidth16bits

Audio data width 16 bits

enumerator kSAI_WordWidth24bits

Audio data width 24 bits

enumerator kSAI_WordWidth32bits

Audio data width 32 bits

enum _sai_data_pin_state

sai data pin state definition

Values:

enumerator kSAI_DataPinStateTriState

transmit data pins are tri-stated when slots are masked or channels are disabled

enumerator kSAI_DataPinStateOutputZero

transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled

enum _sai_fifo_combine

sai fifo combine mode definition

Values:

enumerator kSAI_FifoCombineDisabled

sai TX/RX fifo combine mode disabled

enumerator kSAI_FifoCombineModeEnabledOnRead

sai TX fifo combine mode enabled on FIFO reads

enumerator kSAI_FifoCombineModeEnabledOnWrite

sai TX fifo combine mode enabled on FIFO write

enumerator kSAI_RxFifoCombineModeEnabledOnWrite

sai RX fifo combine mode enabled on FIFO write

enumerator kSAI_RXFifoCombineModeEnabledOnRead

sai RX fifo combine mode enabled on FIFO reads

enumerator kSAI_FifoCombineModeEnabledOnReadWrite

sai TX/RX fifo combined mode enabled on FIFO read/writes

enum _sai_transceiver_type

sai transceiver type

Values:

enumerator kSAI_Transmitter

sai transmitter

enumerator kSAI_Receiver

sai receiver

enum _sai_frame_sync_len

sai frame sync len

Values:

enumerator kSAI_FrameSyncLenOneBitClk

1 bit clock frame sync len for DSP mode

enumerator kSAI_FrameSyncLenPerWordWidth

Frame sync length decided by word width

typedef enum _sai_protocol sai_protocol_t

Define the SAI bus type.

typedef enum _sai_master_slave sai_master_slave_t

Master or slave mode.

typedef enum _sai_mono_stereo sai_mono_stereo_t

Mono or stereo audio format.

typedef enum _sai_data_order sai_data_order_t

SAI data order, MSB or LSB.

typedef enum _sai_clock_polarity sai_clock_polarity_t

SAI clock polarity, active high or low.

typedef enum _sai_sync_mode sai_sync_mode_t

Synchronous or asynchronous mode.

typedef enum _sai_bclk_source sai_bclk_source_t

Bit clock source.

typedef enum _sai_reset_type sai_reset_type_t

The reset type.

typedef enum _sai_fifo_packing sai_fifo_packing_t

The SAI packing mode The mode includes 8 bit and 16 bit packing.

typedef struct _sai_config sai_config_t

SAI user configuration structure.

typedef enum _sai_sample_rate sai_sample_rate_t

Audio sample rate.

typedef enum _sai_word_width sai_word_width_t

Audio word width.

typedef enum _sai_data_pin_state sai_data_pin_state_t

sai data pin state definition

typedef enum _sai_fifo_combine sai_fifo_combine_t

sai fifo combine mode definition

typedef enum _sai_transceiver_type sai_transceiver_type_t

sai transceiver type

typedef enum _sai_frame_sync_len sai_frame_sync_len_t

sai frame sync len

typedef struct _sai_transfer_format sai_transfer_format_t

sai transfer format

typedef struct _sai_master_clock sai_master_clock_t

master clock configurations

typedef struct _sai_fifo sai_fifo_t

sai fifo configurations

typedef struct _sai_bit_clock sai_bit_clock_t

sai bit clock configurations

typedef struct _sai_frame_sync sai_frame_sync_t

sai frame sync configurations

typedef struct _sai_serial_data sai_serial_data_t

sai serial data configurations

typedef struct _sai_transceiver sai_transceiver_t

sai transceiver configurations

typedef struct _sai_transfer sai_transfer_t

SAI transfer structure.

typedef struct _sai_handle sai_handle_t

typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData)

SAI transfer callback prototype.

SAI_XFER_QUEUE_SIZE

SAI transfer queue size, user can refine it according to use case.

FSL_SAI_HAS_FIFO_EXTEND_FEATURE

sai fifo feature

struct _sai_config

#include <fsl_sai.h>

SAI user configuration structure.

Public Members

sai_protocol_t protocol

Audio bus protocol in SAI

sai_sync_mode_t syncMode

SAI sync mode, control Tx/Rx clock sync

bool mclkOutputEnable

Master clock output enable, true means master clock divider enabled

sai_bclk_source_t bclkSource

Bit Clock source

sai_master_slave_t masterSlave

Master or slave

struct _sai_transfer_format

#include <fsl_sai.h>

sai transfer format

Public Members

uint32_t sampleRate_Hz

Sample rate of audio data

uint32_t bitWidth

Data length of audio data, usually 8/16/24/32 bits

sai_mono_stereo_t stereo

Mono or stereo

uint32_t masterClockHz

Master clock frequency in Hz

uint8_t watermark

Watermark value

uint8_t channel

Transfer start channel

uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask

uint8_t endChannel

end channel number

uint8_t channelNums

Total enabled channel numbers

sai_protocol_t protocol

Which audio protocol used

bool isFrameSyncCompact

True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock.

struct _sai_master_clock

#include <fsl_sai.h>

master clock configurations

Public Members

bool mclkOutputEnable

master clock output enable

uint32_t mclkHz

target mclk frequency

uint32_t mclkSourceClkHz

mclk source frequency

struct _sai_fifo

#include <fsl_sai.h>

sai fifo configurations

Public Members

bool fifoContinueOneError

fifo continues when error occur

sai_fifo_combine_t fifoCombine

fifo combine mode

sai_fifo_packing_t fifoPacking

fifo packing mode

uint8_t fifoWatermark

fifo watermark

struct _sai_bit_clock

#include <fsl_sai.h>

sai bit clock configurations

Public Members

bool bclkSrcSwap

bit clock source swap

bool bclkInputDelay

bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time .

sai_clock_polarity_t bclkPolarity

bit clock polarity

sai_bclk_source_t bclkSource

bit Clock source

struct _sai_frame_sync

#include <fsl_sai.h>

sai frame sync configurations

Public Members

uint8_t frameSyncWidth

frame sync width in number of bit clocks

bool frameSyncEarly

TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame

bool frameSyncGenerateOnDemand

internal frame sync is generated when FIFO waring flag is clear

sai_clock_polarity_t frameSyncPolarity

frame sync polarity

struct _sai_serial_data

#include <fsl_sai.h>

sai serial data configurations

Public Members

sai_data_pin_state_t dataMode

sai data pin state when slots masked or channel disabled

sai_data_order_t dataOrder

configure whether the LSB or MSB is transmitted first

uint8_t dataWord0Length

configure the number of bits in the first word in each frame

uint8_t dataWordNLength

configure the number of bits in the each word in each frame, except the first word

uint8_t dataWordLength

used to record the data length for dma transfer

uint8_t dataFirstBitShifted

Configure the bit index for the first bit transmitted for each word in the frame

uint8_t dataWordNum

configure the number of words in each frame

uint32_t dataMaskedWord

configure whether the transmit word is masked

struct _sai_transceiver

#include <fsl_sai.h>

sai transceiver configurations

Public Members

sai_serial_data_t serialData

serial data configurations

sai_frame_sync_t frameSync

ws configurations

sai_bit_clock_t bitClock

bit clock configurations

sai_fifo_t fifo

fifo configurations

sai_master_slave_t masterSlave

transceiver is master or slave

sai_sync_mode_t syncMode

transceiver sync mode

uint8_t startChannel

Transfer start channel

uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask

uint8_t endChannel

end channel number

uint8_t channelNums

Total enabled channel numbers

struct _sai_transfer

#include <fsl_sai.h>

SAI transfer structure.

Public Members

uint8_t *data

Data start address to transfer.

size_t dataSize

Transfer size.

struct _sai_handle

#include <fsl_sai.h>

SAI handle structure.

Public Members

I2S_Type *base

base address

uint32_t state

Transfer status

sai_transfer_callback_t callback

Callback function called at transfer event

void *userData

Callback parameter passed to callback function

uint8_t bitWidth

Bit width for transfer, 8/16/24/32 bits

uint8_t channel

Transfer start channel

uint8_t channelMask

enabled channel mask value, refernece _sai_channel_mask

uint8_t endChannel

end channel number

uint8_t channelNums

Total enabled channel numbers

sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint8_t watermark

Watermark value

SAI EDMA Driver

void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle)

Initializes the SAI eDMA handle.

This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• callback – Pointer to user callback function.

• userData – User parameter passed to the callback function.

• txDmaHandle – eDMA handle pointer, this handle shall be static allocated by users.

void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle)

Initializes the SAI Rx eDMA handle.

This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• callback – Pointer to user callback function.

• userData – User parameter passed to the callback function.

• rxDmaHandle – eDMA handle pointer, this handle shall be static allocated by users.

void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType)

Initializes the SAI interleave type.

This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is kSAI_EDMAInterleavePerChannelSample always

Parameters:

• handle – SAI eDMA handle pointer.

• interleaveType – Multi channel interleave type.

void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Tx.

Note

SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step.

sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite;
SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config);

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• saiConfig – sai configurations.

void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Rx.

Note

SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step.

sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead;
SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config);

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• saiConfig – sai configurations.

status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI transfer using DMA.

This function support multi channel transfer,

1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers

2. for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.

Note

This interface returns immediately after the transfer initiates. Call SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure.

Return values:

• kStatus_Success – Start a SAI eDMA send successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_TxBusy – SAI is busy sending data.

status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI receive using eDMA.

This function support multi channel transfer,

1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers

2. for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.

Note

This interface returns immediately after the transfer initiates. Call the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.

Parameters:

• base – SAI base pointer

• handle – SAI eDMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a SAI eDMA receive successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_RxBusy – SAI is busy receiving data.

status_t SAI_TransferSendLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA.

Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer.

Note

This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount).

• loopTransferCount – the counts of xfer array.

Return values:

• kStatus_Success – Start a SAI eDMA send successfully.

• kStatus_InvalidArgument – The input argument is invalid.

status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA.

Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer.

Note

This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount).

• loopTransferCount – the counts of xfer array.

Return values:

• kStatus_Success – Start a SAI eDMA receive successfully.

• kStatus_InvalidArgument – The input argument is invalid.

void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI send.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSendEDMA.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI receive.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceiveEDMA.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI transfer using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI receive using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.

Parameters:

• base – SAI base pointer

• handle – SAI eDMA handle pointer.

status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count sent by SAI.

Parameters:

• base – SAI base pointer.

• handle – SAI eDMA handle pointer.

• count – Bytes count sent by SAI.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.

status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count received by SAI.

Parameters:

• base – SAI base pointer

• handle – SAI eDMA handle pointer.

• count – Bytes count received by SAI.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.

uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Gets valid transfer slot.

This function can be used to query the valid transfer request slot that the application can submit. It should be called in the critical section, that means the application could call it in the corresponding callback function or disable IRQ before calling it in the application, otherwise, the returned value may not correct.

Parameters:

• base – SAI base pointer

• handle – SAI eDMA handle pointer.

Return values:

valid – slot count that application submit.

FSL_SAI_EDMA_DRIVER_VERSION

Version 2.7.1

enum _sai_edma_interleave

sai interleave type

Values:

enumerator kSAI_EDMAInterleavePerChannelSample

enumerator kSAI_EDMAInterleavePerChannelBlock

typedef struct sai_edma_handle sai_edma_handle_t

typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)

SAI eDMA transfer callback function for finish and error.

typedef enum _sai_edma_interleave sai_edma_interleave_t

sai interleave type

struct sai_edma_handle

#include <fsl_sai_edma.h>

SAI DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle

DMA handler for SAI send

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint8_t bytesPerFrame

Bytes in a frame

uint8_t channelMask

Enabled channel mask value, reference _sai_channel_mask

uint8_t channelNums

total enabled channel nums

uint8_t channel

Which data channel

uint8_t count

The transfer data count in a DMA request

uint32_t state

Internal state for SAI eDMA transfer

sai_edma_callback_t callback

Callback for users while transfer finish or error occurs

void *userData

User callback parameter

uint8_t tcd[((4U) + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA transfer.

sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer.

size_t transferSize[(4U)]

Data bytes need to transfer

sai_edma_interleave_t interleaveType

Transfer interleave type

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

SEMA4: Hardware Semaphores Driver

FSL_SEMA4_DRIVER_VERSION

SEMA4 driver version.

void SEMA4_Init(SEMA4_Type *base)

Initializes the SEMA4 module.

This function initializes the SEMA4 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA4_ResetGate or SEMA4_ResetAllGates function.

Parameters:

• base – SEMA4 peripheral base address.

void SEMA4_Deinit(SEMA4_Type *base)

De-initializes the SEMA4 module.

This function de-initializes the SEMA4 module. It only disables the clock.

Parameters:

• base – SEMA4 peripheral base address.

status_t SEMA4_TryLock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)

Tries to lock the SEMA4 gate.

This function tries to lock the specific SEMA4 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number to lock.

• procNum – Current processor number.

Return values:

• kStatus_Success – Lock the sema4 gate successfully.

• kStatus_Fail – Sema4 gate has been locked by another processor.

void SEMA4_Lock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)

Locks the SEMA4 gate.

This function locks the specific SEMA4 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number to lock.

• procNum – Current processor number.

static inline void SEMA4_Unlock(SEMA4_Type *base, uint8_t gateNum)

Unlocks the SEMA4 gate.

This function unlocks the specific SEMA4 gate. It only writes unlock value to the SEMA4 gate register. However, it does not check whether the SEMA4 gate is locked by the current processor or not. As a result, if the SEMA4 gate is not locked by the current processor, this function has no effect.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number to unlock.

static inline int32_t SEMA4_GetLockProc(SEMA4_Type *base, uint8_t gateNum)

Gets the status of the SEMA4 gate.

This function checks the lock status of a specific SEMA4 gate.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number.

Returns:

Return -1 if the gate is unlocked, otherwise return the processor number which has locked the gate.

status_t SEMA4_ResetGate(SEMA4_Type *base, uint8_t gateNum)

Resets the SEMA4 gate to an unlocked status.

This function resets a SEMA4 gate to an unlocked status.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number.

Return values:

• kStatus_Success – SEMA4 gate is reset successfully.

• kStatus_Fail – Some other reset process is ongoing.

static inline status_t SEMA4_ResetAllGates(SEMA4_Type *base)

Resets all SEMA4 gates to an unlocked status.

This function resets all SEMA4 gate to an unlocked status.

Parameters:

• base – SEMA4 peripheral base address.

Return values:

• kStatus_Success – SEMA4 is reset successfully.

• kStatus_Fail – Some other reset process is ongoing.

static inline void SEMA4_EnableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint32_t mask)

Enable the gate notification interrupt.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

Parameters:

• base – SEMA4 peripheral base address.

• procNum – Current processor number.

• mask – OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.

static inline void SEMA4_DisableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint32_t mask)

Disable the gate notification interrupt.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

Parameters:

• base – SEMA4 peripheral base address.

• procNum – Current processor number.

• mask – OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.

static inline uint32_t SEMA4_GetGateNotifyStatus(SEMA4_Type *base, uint8_t procNum)

Get the gate notification flags.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle. The status flags are cleared automatically when the gate is locked by current core or locked again before the other core.

Parameters:

• base – SEMA4 peripheral base address.

• procNum – Current processor number.

Returns:

OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1 flags are pending.

status_t SEMA4_ResetGateNotify(SEMA4_Type *base, uint8_t gateNum)

Resets the SEMA4 gate IRQ notification.

This function resets a SEMA4 gate IRQ notification.

Parameters:

• base – SEMA4 peripheral base address.

• gateNum – Gate number.

Return values:

• kStatus_Success – Reset successfully.

• kStatus_Fail – Some other reset process is ongoing.

static inline status_t SEMA4_ResetAllGateNotify(SEMA4_Type *base)

Resets all SEMA4 gates IRQ notification.

This function resets all SEMA4 gate IRQ notifications.

Parameters:

• base – SEMA4 peripheral base address.

Return values:

• kStatus_Success – Reset successfully.

• kStatus_Fail – Some other reset process is ongoing.

SEMA4_GATE_NUM_RESET_ALL

The number to reset all SEMA4 gates.

SEMA4_GATEn(base, n)

SEMA4 gate n register address.

SEMC: Smart External DRAM Controller Driver

void SEMC_GetDefaultConfig(semc_config_t *config)

Gets the SEMC default basic configuration structure.

The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example:

semc_config_t config;
SEMC_GetDefaultConfig(&config);

Parameters:

• config – The SEMC configuration structure pointer.

void SEMC_Init(SEMC_Type *base, semc_config_t *configure)

Initializes SEMC. This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.

Parameters:

• base – SEMC peripheral base address.

• configure – The SEMC configuration structure pointer.

void SEMC_Deinit(SEMC_Type *base)

Deinitializes the SEMC module and gates the clock.

This function gates the SEMC clock. As a result, the SEMC module doesn’t work after calling this function, for some IDE, calling this API may cause the next downloading operation failed. so, please call this API cautiously. Additional, users can using “#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)” to disable the clock control operation in drivers.

Parameters:

• base – SEMC peripheral base address.

status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)

Configures SDRAM controller in SEMC.

Parameters:

• base – SEMC peripheral base address.

• cs – The chip selection.

• config – The sdram configuration.

• clkSrc_Hz – The SEMC clock frequency.

status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)

Configures NAND controller in SEMC.

Parameters:

• base – SEMC peripheral base address.

• config – The nand configuration.

• clkSrc_Hz – The SEMC clock frequency.

status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)

Configures NOR controller in SEMC.

Parameters:

• base – SEMC peripheral base address.

• config – The nor configuration.

• clkSrc_Hz – The SEMC clock frequency.

status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base, semc_sram_cs_t cs, semc_sram_config_t *config, uint32_t clkSrc_Hz)

Configures SRAM controller in SEMC.

Parameters:

• base – SEMC peripheral base address.

• cs – The chip selection.

• config – The sram configuration.

• clkSrc_Hz – The SEMC clock frequency.

status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)

Configures SRAM controller in SEMC.

Deprecated:

Do not use this function. It has been superceded by SEMC_ConfigureSRAMWithChipSelection.

Parameters:

• base – SEMC peripheral base address.

• config – The sram configuration.

• clkSrc_Hz – The SEMC clock frequency.

status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)

Configures DBI controller in SEMC.

Parameters:

• base – SEMC peripheral base address.

• config – The dbi configuration.

• clkSrc_Hz – The SEMC clock frequency.

static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)

Enables the SEMC interrupt.

This function enables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to enable the IP command done and error interrupt, do the following.

SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);

Parameters:

• base – SEMC peripheral base address.

• mask – SEMC interrupts to enable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.

static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)

Disables the SEMC interrupt.

This function disables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to disable the IP command done and error interrupt, do the following.

SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);

Parameters:

• base – SEMC peripheral base address.

• mask – SEMC interrupts to disable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.

static inline bool SEMC_GetStatusFlag(SEMC_Type *base)

Gets the SEMC status.

This function gets the SEMC interrupts event status. User can use the a logical OR of enumeration member as a mask. See semc_interrupt_enable_t.

Parameters:

• base – SEMC peripheral base address.

Returns:

status flag, use status flag in semc_interrupt_enable_t to get the related status.

static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)

Clears the SEMC status flag state.

The following status register flags can be cleared SEMC interrupt status.

Parameters:

• base – SEMC base pointer

• mask – The status flag mask, a logical OR of enumeration member semc_interrupt_enable_t.

static inline bool SEMC_IsInIdle(SEMC_Type *base)

Check if SEMC is in idle.

Parameters:

• base – SEMC peripheral base address.

Returns:

True SEMC is in idle, false is not in idle.

status_t SEMC_SendIPCommand(SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)

SEMC IP command access.

Parameters:

• base – SEMC peripheral base address.

• memType – SEMC memory type. refer to “semc_mem_type_t”

• address – SEMC device address.

• command – SEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to “semc_ipcmd_nor_dbi_t”. For SRAM device, take refer to “semc_ipcmd_sram_t”. For SDRAM device, take refer to “semc_ipcmd_sdram_t”.

• write – Data for write access.

• read – Data pointer for read data out.

static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, semc_ipcmd_nand_addrmode_t addrMode, semc_ipcmd_nand_cmdmode_t cmdMode)

Build SEMC IP command for NAND.

This function build SEMC NAND IP command. The command is build of user command code, SEMC address mode and SEMC command mode.

Parameters:

• userCommand – NAND device normal command.

• addrMode – NAND address mode. Refer to “semc_ipcmd_nand_addrmode_t”.

• cmdMode – NAND command mode. Refer to “semc_ipcmd_nand_cmdmode_t”.

static inline bool SEMC_IsNandReady(SEMC_Type *base)

Check if the NAND device is ready.

Parameters:

• base – SEMC peripheral base address.

Returns:

True NAND is ready, false NAND is not ready.

status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)

SEMC NAND device memory write through IP command.

Parameters:

• base – SEMC peripheral base address.

• address – SEMC NAND device address.

• data – Data for write access.

• size_bytes – Data length.

status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)

SEMC NAND device memory read through IP command.

Parameters:

• base – SEMC peripheral base address.

• address – SEMC NAND device address.

• data – Data pointer for data read out.

• size_bytes – Data length.

status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)

SEMC NOR device memory write through IP command.

Parameters:

• base – SEMC peripheral base address.

• address – SEMC NOR device address.

• data – Data for write access.

• size_bytes – Data length.

status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)

SEMC NOR device memory read through IP command.

Parameters:

• base – SEMC peripheral base address.

• address – SEMC NOR device address.

• data – Data pointer for data read out.

• size_bytes – Data length.

FSL_SEMC_DRIVER_VERSION

SEMC driver version.

SEMC status, _semc_status.

Values:

enumerator kStatus_SEMC_InvalidDeviceType

Invalid device type.

enumerator kStatus_SEMC_IpCommandExecutionError

IP command execution error.

enumerator kStatus_SEMC_AxiCommandExecutionError

AXI command execution error.

enumerator kStatus_SEMC_InvalidMemorySize

Invalid memory sie.

enumerator kStatus_SEMC_InvalidIpcmdDataSize

Invalid IP command data size.

enumerator kStatus_SEMC_InvalidAddressPortWidth

Invalid address port width.

enumerator kStatus_SEMC_InvalidDataPortWidth

Invalid data port width.

enumerator kStatus_SEMC_InvalidSwPinmuxSelection

Invalid SW pinmux selection.

enumerator kStatus_SEMC_InvalidBurstLength

Invalid burst length

enumerator kStatus_SEMC_InvalidColumnAddressBitWidth

Invalid column address bit width.

enumerator kStatus_SEMC_InvalidBaseAddress

Invalid base address.

enumerator kStatus_SEMC_InvalidTimerSetting

Invalid timer setting.

enum _semc_mem_type

SEMC memory device type.

Values:

enumerator kSEMC_MemType_SDRAM

SDRAM

enumerator kSEMC_MemType_SRAM

SRAM

enumerator kSEMC_MemType_NOR

NOR

enumerator kSEMC_MemType_NAND

NAND

enumerator kSEMC_MemType_8080

enum _semc_waitready_polarity

SEMC WAIT/RDY polarity.

Values:

enumerator kSEMC_LowActive

Low active.

enumerator kSEMC_HighActive

High active.

enum _semc_sdram_cs

SEMC SDRAM Chip selection .

Values:

enumerator kSEMC_SDRAM_CS0

SEMC SDRAM CS0.

enumerator kSEMC_SDRAM_CS1

SEMC SDRAM CS1.

enumerator kSEMC_SDRAM_CS2

SEMC SDRAM CS2.

enumerator kSEMC_SDRAM_CS3

SEMC SDRAM CS3.

enum _semc_sram_cs

SEMC SRAM Chip selection .

Values:

enumerator kSEMC_SRAM_CS0

SEMC SRAM CS0.

enum _semc_nand_access_type

SEMC NAND device type.

Values:

enumerator kSEMC_NAND_ACCESS_BY_AXI

Access to NAND flash by AXI bus.

enumerator kSEMC_NAND_ACCESS_BY_IPCMD

Access to NAND flash by IP bus.

enum _semc_interrupt_enable

SEMC interrupts .

Values:

enumerator kSEMC_IPCmdDoneInterrupt

Ip command done interrupt.

enumerator kSEMC_IPCmdErrInterrupt

Ip command error interrupt.

enumerator kSEMC_AXICmdErrInterrupt

AXI command error interrupt.

enumerator kSEMC_AXIBusErrInterrupt

AXI bus error interrupt.

enum _semc_ipcmd_datasize

SEMC IP command data size in bytes.

Values:

enumerator kSEMC_IPcmdDataSize_1bytes

The IP command data size 1 byte.

enumerator kSEMC_IPcmdDataSize_2bytes

The IP command data size 2 byte.

enumerator kSEMC_IPcmdDataSize_3bytes

The IP command data size 3 byte.

enumerator kSEMC_IPcmdDataSize_4bytes

The IP command data size 4 byte.

enum _semc_refresh_time

SEMC auto-refresh timing.

Values:

enumerator kSEMC_RefreshThreeClocks

The refresh timing with three bus clocks.

enumerator kSEMC_RefreshSixClocks

The refresh timing with six bus clocks.

enumerator kSEMC_RefreshNineClocks

The refresh timing with nine bus clocks.

enum _semc_caslatency

CAS latency.

Values:

enumerator kSEMC_LatencyOne

Latency 1.

enumerator kSEMC_LatencyTwo

Latency 2.

enumerator kSEMC_LatencyThree

Latency 3.

enum _semc_sdram_column_bit_num

SEMC sdram column address bit number.

Values:

enumerator kSEMC_SdramColunm_12bit

12 bit.

enumerator kSEMC_SdramColunm_11bit

11 bit.

enumerator kSEMC_SdramColunm_10bit

10 bit.

enumerator kSEMC_SdramColunm_9bit

9 bit.

enumerator kSEMC_SdramColunm_8bit

8 bit.

enum _semc_sdram_burst_len

SEMC sdram burst length.

Values:

enumerator kSEMC_Sdram_BurstLen1

According to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller’s burst length is greater than 1. Burst length 1

enum _semc_nand_column_bit_num

SEMC nand column address bit number.

Values:

enumerator kSEMC_NandColum_16bit

16 bit.

enumerator kSEMC_NandColum_15bit

15 bit.

enumerator kSEMC_NandColum_14bit

14 bit.

enumerator kSEMC_NandColum_13bit

13 bit.

enumerator kSEMC_NandColum_12bit

12 bit.

enumerator kSEMC_NandColum_11bit

11 bit.

enumerator kSEMC_NandColum_10bit

10 bit.

enumerator kSEMC_NandColum_9bit

9 bit.

enum _semc_nand_burst_len

SEMC nand burst length.

Values:

enumerator kSEMC_Nand_BurstLen1

Burst length 1

enumerator kSEMC_Nand_BurstLen2

Burst length 2

enumerator kSEMC_Nand_BurstLen4

Burst length 4

enumerator kSEMC_Nand_BurstLen8

Burst length 8

enumerator kSEMC_Nand_BurstLen16

Burst length 16

enumerator kSEMC_Nand_BurstLen32

Burst length 32

enumerator kSEMC_Nand_BurstLen64

Burst length 64

enum _semc_norsram_column_bit_num

SEMC nor/sram column address bit number.

Values:

enumerator kSEMC_NorColum_12bit

12 bit.

enumerator kSEMC_NorColum_11bit

11 bit.

enumerator kSEMC_NorColum_10bit

10 bit.

enumerator kSEMC_NorColum_9bit

9 bit.

enumerator kSEMC_NorColum_8bit

8 bit.

enumerator kSEMC_NorColum_7bit

7 bit.

enumerator kSEMC_NorColum_6bit

6 bit.

enumerator kSEMC_NorColum_5bit

5 bit.

enumerator kSEMC_NorColum_4bit

4 bit.

enumerator kSEMC_NorColum_3bit

3 bit.

enumerator kSEMC_NorColum_2bit

2 bit.

enum _semc_norsram_burst_len

SEMC nor/sram burst length.

Values:

enumerator kSEMC_Nor_BurstLen1

Burst length 1

enumerator kSEMC_Nor_BurstLen2

Burst length 2

enumerator kSEMC_Nor_BurstLen4

Burst length 4

enumerator kSEMC_Nor_BurstLen8

Burst length 8

enumerator kSEMC_Nor_BurstLen16

Burst length 16

enumerator kSEMC_Nor_BurstLen32

Burst length 32

enumerator kSEMC_Nor_BurstLen64

Burst length 64

enum _semc_dbi_column_bit_num

SEMC dbi column address bit number.

Values:

enumerator kSEMC_Dbi_Colum_12bit

12 bit.

enumerator kSEMC_Dbi_Colum_11bit

11 bit.

enumerator kSEMC_Dbi_Colum_10bit

10 bit.

enumerator kSEMC_Dbi_Colum_9bit

9 bit.

enumerator kSEMC_Dbi_Colum_8bit

8 bit.

enumerator kSEMC_Dbi_Colum_7bit

7 bit.

enumerator kSEMC_Dbi_Colum_6bit

6 bit.

enumerator kSEMC_Dbi_Colum_5bit

5 bit.

enumerator kSEMC_Dbi_Colum_4bit

4 bit.

enumerator kSEMC_Dbi_Colum_3bit

3 bit.

enumerator kSEMC_Dbi_Colum_2bit

2 bit.

enum _semc_dbi_burst_len

SEMC dbi burst length.

Values:

enumerator kSEMC_Dbi_BurstLen1

Burst length 1

enumerator kSEMC_Dbi_BurstLen2

Burst length 2

enumerator kSEMC_Dbi_Dbi_BurstLen4

Burst length 4

enumerator kSEMC_Dbi_BurstLen8

Burst length 8

enumerator kSEMC_Dbi_BurstLen16

Burst length 16

enumerator kSEMC_Dbi_BurstLen32

Burst length 32

enumerator kSEMC_Dbi_BurstLen64

Burst length 64

enum _semc_iomux_pin

SEMC IOMUXC.

Values:

enumerator kSEMC_MUXA8

MUX A8 pin.

enumerator kSEMC_MUXCSX0

MUX CSX0 pin

enumerator kSEMC_MUXCSX1

MUX CSX1 Pin.

enumerator kSEMC_MUXCSX2

MUX CSX2 Pin.

enumerator kSEMC_MUXCSX3

MUX CSX3 Pin.

enumerator kSEMC_MUXRDY

MUX RDY pin.

enum _semc_iomux_nora27_pin

SEMC NOR/PSRAM Address bit 27 A27.

Values:

enumerator kSEMC_MORA27_NONE

No NOR/SRAM A27 pin.

enumerator kSEMC_NORA27_MUXCSX3

MUX CSX3 Pin.

enumerator kSEMC_NORA27_MUXRDY

MUX RDY pin.

enum _semc_port_size

SEMC port size.

Values:

enumerator kSEMC_PortSize8Bit

8-Bit port size.

enumerator kSEMC_PortSize16Bit

16-Bit port size.

enum _semc_addr_mode

SEMC address mode.

Values:

enumerator kSEMC_AddrDataMux

SEMC address/data mux mode.

enumerator kSEMC_AdvAddrdataMux

Advanced address/data mux mode.

enumerator kSEMC_AddrDataNonMux

Address/data non-mux mode.

enum _semc_dqs_mode

SEMC DQS read strobe mode.

Values:

enumerator kSEMC_Loopbackinternal

Dummy read strobe loopbacked internally.

enumerator kSEMC_Loopbackdqspad

Dummy read strobe loopbacked from DQS pad.

enum _semc_adv_polarity

SEMC ADV signal active polarity.

Values:

enumerator kSEMC_AdvActiveLow

Adv active low.

enumerator kSEMC_AdvActiveHigh

Adv active high.

enum _semc_sync_mode

SEMC sync mode.

Values:

enumerator kSEMC_AsyncMode

Async mode.

enumerator kSEMC_SyncMode

Sync mode.

enum _semc_adv_level_control

SEMC ADV signal level control.

Values:

enumerator kSEMC_AdvHigh

Adv is high during address hold state.

enumerator kSEMC_AdvLow

Adv is low during address hold state.

enum _semc_rdy_polarity

SEMC RDY signal active polarity.

Values:

enumerator kSEMC_RdyActiveLow

Adv active low.

enumerator kSEMC_RdyActivehigh

Adv active low.

enum _semc_ipcmd_nand_addrmode

SEMC IP command for NAND: address mode.

Values:

enumerator kSEMC_NANDAM_ColumnRow

Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2).

enumerator kSEMC_NANDAM_ColumnCA0

Address mode: column address only(1 Byte-CA0).

enumerator kSEMC_NANDAM_ColumnCA0CA1

Address mode: column address only(2 Byte-CA0/CA1).

enumerator kSEMC_NANDAM_RawRA0

Address mode: row address only(1 Byte-RA0).

enumerator kSEMC_NANDAM_RawRA0RA1

Address mode: row address only(2 Byte-RA0/RA1).

enumerator kSEMC_NANDAM_RawRA0RA1RA2

Address mode: row address only(3 Byte-RA0).

enum _semc_ipcmd_nand_cmdmode

SEMC IP command for NAND： command mode.

Values:

enumerator kSEMC_NANDCM_Command

command.

enumerator kSEMC_NANDCM_CommandHold

Command hold.

enumerator kSEMC_NANDCM_CommandAddress

Command address.

enumerator kSEMC_NANDCM_CommandAddressHold

Command address hold.

enumerator kSEMC_NANDCM_CommandAddressRead

Command address read.

enumerator kSEMC_NANDCM_CommandAddressWrite

Command address write.

enumerator kSEMC_NANDCM_CommandRead

Command read.

enumerator kSEMC_NANDCM_CommandWrite

Command write.

enumerator kSEMC_NANDCM_Read

Read.

enumerator kSEMC_NANDCM_Write

Write.

enum _semc_nand_address_option

SEMC NAND address option.

Values:

enumerator kSEMC_NandAddrOption_5byte_CA2RA3

CA0+CA1+RA0+RA1+RA2

enumerator kSEMC_NandAddrOption_4byte_CA2RA2

CA0+CA1+RA0+RA1

enumerator kSEMC_NandAddrOption_3byte_CA2RA1

CA0+CA1+RA0

enumerator kSEMC_NandAddrOption_4byte_CA1RA3

CA0+RA0+RA1+RA2

enumerator kSEMC_NandAddrOption_3byte_CA1RA2

CA0+RA0+RA1

enumerator kSEMC_NandAddrOption_2byte_CA1RA1

CA0+RA0

enum _semc_ipcmd_nor_dbi

SEMC IP command for NOR.

Values:

enumerator kSEMC_NORDBICM_Read

NOR read.

enumerator kSEMC_NORDBICM_Write

NOR write.

enum _semc_ipcmd_sram

SEMC IP command for SRAM.

Values:

enumerator kSEMC_SRAMCM_ArrayRead

SRAM memory array read.

enumerator kSEMC_SRAMCM_ArrayWrite

SRAM memory array write.

enumerator kSEMC_SRAMCM_RegRead

SRAM memory register read.

enumerator kSEMC_SRAMCM_RegWrite

SRAM memory register write.

enum _semc_ipcmd_sdram

SEMC IP command for SDARM.

Values:

enumerator kSEMC_SDRAMCM_Read

SDRAM memory read.

enumerator kSEMC_SDRAMCM_Write

SDRAM memory write.

enumerator kSEMC_SDRAMCM_Modeset

SDRAM MODE SET.

enumerator kSEMC_SDRAMCM_Active

SDRAM active.

enumerator kSEMC_SDRAMCM_AutoRefresh

SDRAM auto-refresh.

enumerator kSEMC_SDRAMCM_SelfRefresh

SDRAM self-refresh.

enumerator kSEMC_SDRAMCM_Precharge

SDRAM precharge.

enumerator kSEMC_SDRAMCM_Prechargeall

SDRAM precharge all.

typedef enum _semc_mem_type semc_mem_type_t

SEMC memory device type.

typedef enum _semc_waitready_polarity semc_waitready_polarity_t

SEMC WAIT/RDY polarity.

typedef enum _semc_sdram_cs semc_sdram_cs_t

SEMC SDRAM Chip selection .

typedef enum _semc_sram_cs semc_sram_cs_t

SEMC SRAM Chip selection .

typedef enum _semc_nand_access_type semc_nand_access_type_t

SEMC NAND device type.

typedef enum _semc_interrupt_enable semc_interrupt_enable_t

SEMC interrupts .

typedef enum _semc_ipcmd_datasize semc_ipcmd_datasize_t

SEMC IP command data size in bytes.

typedef enum _semc_refresh_time semc_refresh_time_t

SEMC auto-refresh timing.

typedef enum _semc_caslatency semc_caslatency_t

CAS latency.

typedef enum _semc_sdram_column_bit_num semc_sdram_column_bit_num_t

SEMC sdram column address bit number.

typedef enum _semc_sdram_burst_len sem_sdram_burst_len_t

SEMC sdram burst length.

typedef enum _semc_nand_column_bit_num semc_nand_column_bit_num_t

SEMC nand column address bit number.

typedef enum _semc_nand_burst_len sem_nand_burst_len_t

SEMC nand burst length.

typedef enum _semc_norsram_column_bit_num semc_norsram_column_bit_num_t

SEMC nor/sram column address bit number.

typedef enum _semc_norsram_burst_len sem_norsram_burst_len_t

SEMC nor/sram burst length.

typedef enum _semc_dbi_column_bit_num semc_dbi_column_bit_num_t

SEMC dbi column address bit number.

typedef enum _semc_dbi_burst_len sem_dbi_burst_len_t

SEMC dbi burst length.

typedef enum _semc_iomux_pin semc_iomux_pin

SEMC IOMUXC.

typedef enum _semc_iomux_nora27_pin semc_iomux_nora27_pin

SEMC NOR/PSRAM Address bit 27 A27.

typedef enum _semc_port_size smec_port_size_t

SEMC port size.

typedef enum _semc_addr_mode semc_addr_mode_t

SEMC address mode.

typedef enum _semc_dqs_mode semc_dqs_mode_t

SEMC DQS read strobe mode.

typedef enum _semc_adv_polarity semc_adv_polarity_t

SEMC ADV signal active polarity.

typedef enum _semc_sync_mode semc_sync_mode_t

SEMC sync mode.

typedef enum _semc_adv_level_control semc_adv_level_control_t

SEMC ADV signal level control.

typedef enum _semc_rdy_polarity semc_rdy_polarity_t

SEMC RDY signal active polarity.

typedef enum _semc_ipcmd_nand_addrmode semc_ipcmd_nand_addrmode_t

SEMC IP command for NAND: address mode.

typedef enum _semc_ipcmd_nand_cmdmode semc_ipcmd_nand_cmdmode_t

SEMC IP command for NAND： command mode.

typedef enum _semc_nand_address_option semc_nand_address_option_t

SEMC NAND address option.

typedef enum _semc_ipcmd_nor_dbi semc_ipcmd_nor_dbi_t

SEMC IP command for NOR.

typedef enum _semc_ipcmd_sram semc_ipcmd_sram_t

SEMC IP command for SRAM.

typedef enum _semc_ipcmd_sdram semc_ipcmd_sdram_t

SEMC IP command for SDARM.

typedef struct _semc_sdram_config semc_sdram_config_t

SEMC SDRAM configuration structure.

1. The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.

2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

typedef struct _semc_nand_timing_config semc_nand_timing_config_t

SEMC NAND device timing configuration structure.

typedef struct _semc_nand_config semc_nand_config_t

SEMC NAND configuration structure.

typedef struct _semc_nor_config semc_nor_config_t

SEMC NOR configuration structure.

typedef struct _semc_sram_config semc_sram_config_t

SEMC SRAM configuration structure.

typedef struct _semc_dbi_config semc_dbi_config_t

SEMC DBI configuration structure.

typedef struct _semc_queuea_weight_struct semc_queuea_weight_struct_t

SEMC AXI queue a weight setting structure.

typedef union _semc_queuea_weight semc_queuea_weight_t

SEMC AXI queue a weight setting union.

typedef struct _semc_queueb_weight_struct semc_queueb_weight_struct_t

SEMC AXI queue b weight setting structure.

typedef union _semc_queueb_weight semc_queueb_weight_t

SEMC AXI queue b weight setting union.

typedef struct _semc_axi_queueweight semc_axi_queueweight_t

SEMC AXI queue weight setting.

typedef struct _semc_config_t semc_config_t

SEMC configuration structure.

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it’s similar to the busTimeoutCycles.

struct _semc_sdram_config

#include <fsl_semc.h>

SEMC SDRAM configuration structure.

1. The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.

2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

Public Members

semc_iomux_pin csxPinMux

CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting.

uint32_t address

The base address.

uint32_t memsize_kbytes

The memory size in unit of kbytes.

smec_port_size_t portSize

Port size.

sem_sdram_burst_len_t burstLen

Burst length.

semc_sdram_column_bit_num_t columnAddrBitNum

Column address bit number.

semc_caslatency_t casLatency

CAS latency.

uint8_t tPrecharge2Act_Ns

Precharge to active wait time in unit of nanosecond.

uint8_t tAct2ReadWrite_Ns

Act to read/write wait time in unit of nanosecond.

uint8_t tRefreshRecovery_Ns

Refresh recovery time in unit of nanosecond.

uint8_t tWriteRecovery_Ns

write recovery time in unit of nanosecond.

uint8_t tCkeOff_Ns

CKE off minimum time in unit of nanosecond.

uint8_t tAct2Prechage_Ns

Active to precharge in unit of nanosecond.

uint8_t tSelfRefRecovery_Ns

Self refresh recovery time in unit of nanosecond.

uint8_t tRefresh2Refresh_Ns

Refresh to refresh wait time in unit of nanosecond.

uint8_t tAct2Act_Ns

Active to active wait time in unit of nanosecond.

uint32_t tPrescalePeriod_Ns

Prescaler timer period should not be larger than 256 * 16 * clock cycle.

uint32_t tIdleTimeout_Ns

Idle timeout in unit of prescale time period.

uint32_t refreshPeriod_nsPerRow

Refresh timer period like 64ms * 1000000/8192 .

uint32_t refreshUrgThreshold

Refresh urgent threshold.

uint8_t refreshBurstLen

Refresh burst length.

uint8_t delayChain

Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.

uint8_t autofreshTimes

Auto Refresh cycles times.

struct _semc_nand_timing_config

#include <fsl_semc.h>

SEMC NAND device timing configuration structure.

Public Members

uint8_t tCeSetup_Ns

CE setup time: tCS.

uint8_t tCeHold_Ns

CE hold time: tCH.

uint8_t tCeInterval_Ns

CE interval time:tCEITV.

uint8_t tWeLow_Ns

WE low time: tWP.

uint8_t tWeHigh_Ns

WE high time: tWH.

uint8_t tReLow_Ns

RE low time: tRP.

uint8_t tReHigh_Ns

RE high time: tREH.

uint8_t tTurnAround_Ns

Turnaround time for async mode: tTA.

uint8_t tWehigh2Relow_Ns

WE# high to RE# wait time: tWHR.

uint8_t tRehigh2Welow_Ns

RE# high to WE# low wait time: tRHW.

uint8_t tAle2WriteStart_Ns

ALE to write start wait time: tADL.

uint8_t tReady2Relow_Ns

Ready to RE# low min wait time: tRR.

uint8_t tWehigh2Busy_Ns

WE# high to busy wait time: tWB.

struct _semc_nand_config

#include <fsl_semc.h>

SEMC NAND configuration structure.

Public Members

semc_iomux_pin cePinMux

The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting.

uint32_t axiAddress

The base address for AXI nand.

uint32_t axiMemsize_kbytes

The memory size in unit of kbytes for AXI nand.

uint32_t ipgAddress

The base address for IPG nand .

uint32_t ipgMemsize_kbytes

The memory size in unit of kbytes for IPG nand.

semc_rdy_polarity_t rdyactivePolarity

Wait ready polarity.

bool edoModeEnabled

EDO mode enabled.

semc_nand_column_bit_num_t columnAddrBitNum

Column address bit number.

semc_nand_address_option_t arrayAddrOption

Address option.

sem_nand_burst_len_t burstLen

Burst length.

smec_port_size_t portSize

Port size.

semc_nand_timing_config_t *timingConfig

SEMC nand timing configuration.

struct _semc_nor_config

#include <fsl_semc.h>

SEMC NOR configuration structure.

Public Members

semc_iomux_pin cePinMux

The CE# pin mux setting.

semc_iomux_nora27_pin addr27

The Addr bit 27 pin mux setting.

uint32_t address

The base address.

uint32_t memsize_kbytes

The memory size in unit of kbytes.

uint8_t addrPortWidth

The address port width.

semc_rdy_polarity_t rdyactivePolarity

Wait ready polarity.

semc_adv_polarity_t advActivePolarity

ADV# polarity.

semc_norsram_column_bit_num_t columnAddrBitNum

Column address bit number.

semc_addr_mode_t addrMode

Address mode.

sem_norsram_burst_len_t burstLen

Burst length.

smec_port_size_t portSize

Port size.

uint8_t tCeSetup_Ns

The CE setup time.

uint8_t tCeHold_Ns

The CE hold time.

uint8_t tCeInterval_Ns

CE interval minimum time.

uint8_t tAddrSetup_Ns

The address setup time.

uint8_t tAddrHold_Ns

The address hold time.

uint8_t tWeLow_Ns

WE low time for async mode.

uint8_t tWeHigh_Ns

WE high time for async mode.

uint8_t tReLow_Ns

RE low time for async mode.

uint8_t tReHigh_Ns

RE high time for async mode.

uint8_t tTurnAround_Ns

Turnaround time for async mode.

uint8_t tAddr2WriteHold_Ns

Address to write data hold time for async mode.

uint8_t tWriteSetup_Ns

Write data setup time for sync mode.

uint8_t tWriteHold_Ns

Write hold time for sync mode.

uint8_t latencyCount

Latency count for sync mode.

uint8_t readCycle

Read cycle time for sync mode.

uint8_t delayChain

Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.

struct _semc_sram_config

#include <fsl_semc.h>

SEMC SRAM configuration structure.

Public Members

semc_iomux_pin cePinMux

The CE# pin mux setting.

semc_iomux_nora27_pin addr27

The Addr bit 27 pin mux setting.

uint32_t address

The base address.

uint32_t memsize_kbytes

The memory size in unit of kbytes.

uint8_t addrPortWidth

The address port width.

semc_adv_polarity_t advActivePolarity

ADV# polarity 1: active high, 0: active low.

semc_addr_mode_t addrMode

Address mode.

sem_norsram_burst_len_t burstLen

Burst length.

smec_port_size_t portSize

Port size.

semc_sync_mode_t syncMode

Sync mode.

bool waitEnable

Wait enable.

uint8_t waitSample

Wait sample.

semc_adv_level_control_t advLevelCtrl

ADV# level control during address hold state, 1: low, 0: high.

uint8_t tCeSetup_Ns

The CE setup time.

uint8_t tCeHold_Ns

The CE hold time.

uint8_t tCeInterval_Ns

CE interval minimum time.

uint8_t readHoldTime_Ns

read hold time.

uint8_t tAddrSetup_Ns

The address setup time.

uint8_t tAddrHold_Ns

The address hold time.

uint8_t tWeLow_Ns

WE low time for async mode.

uint8_t tWeHigh_Ns

WE high time for async mode.

uint8_t tReLow_Ns

RE low time for async mode.

uint8_t tReHigh_Ns

RE high time for async mode.

uint8_t tTurnAround_Ns

Turnaround time for async mode.

uint8_t tAddr2WriteHold_Ns

Address to write data hold time for async mode.

uint8_t tWriteSetup_Ns

Write data setup time for sync mode.

uint8_t tWriteHold_Ns

Write hold time for sync mode.

uint8_t latencyCount

Latency count for sync mode.

uint8_t readCycle

Read cycle time for sync mode.

uint8_t delayChain

Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.

struct _semc_dbi_config

#include <fsl_semc.h>

SEMC DBI configuration structure.

Public Members

semc_iomux_pin csxPinMux

The CE# pin mux.

uint32_t address

The base address.

uint32_t memsize_kbytes

The memory size in unit of 4kbytes.

semc_dbi_column_bit_num_t columnAddrBitNum

Column address bit number.

sem_dbi_burst_len_t burstLen

Burst length.

smec_port_size_t portSize

Port size.

uint8_t tCsxSetup_Ns

The CSX setup time.

uint8_t tCsxHold_Ns

The CSX hold time.

uint8_t tWexLow_Ns

WEX low time.

uint8_t tWexHigh_Ns

WEX high time.

uint8_t tRdxLow_Ns

RDX low time.

uint8_t tRdxHigh_Ns

RDX high time.

uint8_t tCsxInterval_Ns

Write data setup time.

struct _semc_queuea_weight_struct

#include <fsl_semc.h>

SEMC AXI queue a weight setting structure.

Public Members

uint32_t qos

weight of qos for queue 0 .

uint32_t aging

weight of aging for queue 0.

uint32_t slaveHitNoswitch

weight of read/write no switch for queue 0 .

uint32_t slaveHitSwitch

weight of read/write switch for queue 0.

union _semc_queuea_weight

#include <fsl_semc.h>

SEMC AXI queue a weight setting union.

Public Members

semc_queuea_weight_struct_t queueaConfig

Structure configuration for queueA.

uint32_t queueaValue

Configuration value for queueA which could directly write to the reg.

struct _semc_queueb_weight_struct

#include <fsl_semc.h>

SEMC AXI queue b weight setting structure.

Public Members

uint32_t qos

weight of qos for queue 1.

uint32_t aging

weight of aging for queue 1.

uint32_t weightPagehit

weight of page hit for queue 1 only .

uint32_t slaveHitNoswitch

weight of read/write no switch for queue 1.

uint32_t bankRotation

weight of bank rotation for queue 1 only .

union _semc_queueb_weight

#include <fsl_semc.h>

SEMC AXI queue b weight setting union.

Public Members

semc_queueb_weight_struct_t queuebConfig

Structure configuration for queueB.

uint32_t queuebValue

Configuration value for queueB which could directly write to the reg.

struct _semc_axi_queueweight

#include <fsl_semc.h>

SEMC AXI queue weight setting.

Public Members

bool queueaEnable

Enable queue a.

semc_queuea_weight_t queueaWeight

Weight settings for queue a.

bool queuebEnable

Enable queue b.

semc_queueb_weight_t queuebWeight

Weight settings for queue b.

struct _semc_config_t

#include <fsl_semc.h>

SEMC configuration structure.

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it’s similar to the busTimeoutCycles.

Public Members

semc_dqs_mode_t dqsMode

Dummy read strobe mode: use enum in “semc_dqs_mode_t”.

uint8_t cmdTimeoutCycles

Command execution timeout cycles.

uint8_t busTimeoutCycles

Bus timeout cycles.

semc_axi_queueweight_t queueWeight

AXI queue weight.

Smartcard

FSL_SMARTCARD_DRIVER_VERSION

Smart card driver version 2.3.0.

Smart card Error codes.

Values:

enumerator kStatus_SMARTCARD_Success

Transfer ends successfully

enumerator kStatus_SMARTCARD_TxBusy

Transmit in progress

enumerator kStatus_SMARTCARD_RxBusy

Receiving in progress

enumerator kStatus_SMARTCARD_NoTransferInProgress

No transfer in progress

enumerator kStatus_SMARTCARD_Timeout

Transfer ends with time-out

enumerator kStatus_SMARTCARD_Initialized

Smart card driver is already initialized

enumerator kStatus_SMARTCARD_PhyInitialized

Smart card PHY drive is already initialized

enumerator kStatus_SMARTCARD_CardNotActivated

Smart card is not activated

enumerator kStatus_SMARTCARD_InvalidInput

Function called with invalid input arguments

enumerator kStatus_SMARTCARD_OtherError

Some other error occur

enum _smartcard_control

Control codes for the Smart card protocol timers and misc.

Values:

enumerator kSMARTCARD_EnableADT

enumerator kSMARTCARD_DisableADT

enumerator kSMARTCARD_EnableGTV

enumerator kSMARTCARD_DisableGTV

enumerator kSMARTCARD_ResetWWT

enumerator kSMARTCARD_EnableWWT

enumerator kSMARTCARD_DisableWWT

enumerator kSMARTCARD_ResetCWT

enumerator kSMARTCARD_EnableCWT

enumerator kSMARTCARD_DisableCWT

enumerator kSMARTCARD_ResetBWT

enumerator kSMARTCARD_EnableBWT

enumerator kSMARTCARD_DisableBWT

enumerator kSMARTCARD_EnableInitDetect

enumerator kSMARTCARD_EnableAnack

enumerator kSMARTCARD_DisableAnack

enumerator kSMARTCARD_ConfigureBaudrate

enumerator kSMARTCARD_SetupATRMode

enumerator kSMARTCARD_SetupT0Mode

enumerator kSMARTCARD_SetupT1Mode

enumerator kSMARTCARD_EnableReceiverMode

enumerator kSMARTCARD_DisableReceiverMode

enumerator kSMARTCARD_EnableTransmitterMode

enumerator kSMARTCARD_DisableTransmitterMode

enumerator kSMARTCARD_ResetWaitTimeMultiplier

enum _smartcard_card_voltage_class

Defines Smart card interface voltage class values.

Values:

enumerator kSMARTCARD_VoltageClassUnknown

enumerator kSMARTCARD_VoltageClassA5_0V

enumerator kSMARTCARD_VoltageClassB3_3V

enumerator kSMARTCARD_VoltageClassC1_8V

enum _smartcard_transfer_state

Defines Smart card I/O transfer states.

Values:

enumerator kSMARTCARD_IdleState

enumerator kSMARTCARD_WaitingForTSState

enumerator kSMARTCARD_InvalidTSDetecetedState

enumerator kSMARTCARD_ReceivingState

enumerator kSMARTCARD_TransmittingState

enum _smartcard_reset_type

Defines Smart card reset types.

Values:

enumerator kSMARTCARD_ColdReset

enumerator kSMARTCARD_WarmReset

enumerator kSMARTCARD_NoColdReset

enumerator kSMARTCARD_NoWarmReset

enum _smartcard_transport_type

Defines Smart card transport protocol types.

Values:

enumerator kSMARTCARD_T0Transport

enumerator kSMARTCARD_T1Transport

enum _smartcard_parity_type

Defines Smart card data parity types.

Values:

enumerator kSMARTCARD_EvenParity

enumerator kSMARTCARD_OddParity

enum _smartcard_card_convention

Defines data Convention format.

Values:

enumerator kSMARTCARD_DirectConvention

enumerator kSMARTCARD_InverseConvention

enum _smartcard_interface_control

Defines Smart card interface IC control types.

Values:

enumerator kSMARTCARD_InterfaceSetVcc

enumerator kSMARTCARD_InterfaceSetClockToResetDelay

enumerator kSMARTCARD_InterfaceReadStatus

enum _smartcard_direction

Defines transfer direction.

Values:

enumerator kSMARTCARD_Receive

enumerator kSMARTCARD_Transmit

typedef enum _smartcard_control smartcard_control_t

Control codes for the Smart card protocol timers and misc.

typedef enum _smartcard_card_voltage_class smartcard_card_voltage_class_t

Defines Smart card interface voltage class values.

typedef enum _smartcard_transfer_state smartcard_transfer_state_t

Defines Smart card I/O transfer states.

typedef enum _smartcard_reset_type smartcard_reset_type_t

Defines Smart card reset types.

typedef enum _smartcard_transport_type smartcard_transport_type_t

Defines Smart card transport protocol types.

typedef enum _smartcard_parity_type smartcard_parity_type_t

Defines Smart card data parity types.

typedef enum _smartcard_card_convention smartcard_card_convention_t

Defines data Convention format.

typedef enum _smartcard_interface_control smartcard_interface_control_t

Defines Smart card interface IC control types.

typedef enum _smartcard_direction smartcard_direction_t

Defines transfer direction.

typedef void (*smartcard_interface_callback_t)(void *smartcardContext, void *param)

Smart card interface interrupt callback function type.

typedef void (*smartcard_transfer_callback_t)(void *smartcardContext, void *param)

Smart card transfer interrupt callback function type.

typedef void (*smartcard_time_delay_t)(uint32_t us)

Time Delay function used to passive waiting using RTOS [us].

typedef struct _smartcard_card_params smartcard_card_params_t

Defines card-specific parameters for Smart card driver.

typedef struct _smartcard_timers_state smartcard_timers_state_t

Smart card defines the state of the EMV timers in the Smart card driver.

typedef struct _smartcard_interface_config smartcard_interface_config_t

Defines user specified configuration of Smart card interface.

typedef struct _smartcard_xfer smartcard_xfer_t

Defines user transfer structure used to initialize transfer.

typedef struct _smartcard_context smartcard_context_t

Runtime state of the Smart card driver.

SMARTCARD_INIT_DELAY_CLOCK_CYCLES

Smart card global define which specify number of clock cycles until initial ‘TS’ character has to be received.

SMARTCARD_EMV_ATR_DURATION_ETU

Smart card global define which specify number of clock cycles during which ATR string has to be received.

SMARTCARD_TS_DIRECT_CONVENTION

Smart card specification initial TS character definition of direct convention.

SMARTCARD_TS_INVERSE_CONVENTION

Smart card specification initial TS character definition of inverse convention.

struct _smartcard_card_params

#include <fsl_smartcard.h>

Defines card-specific parameters for Smart card driver.

Public Members

uint16_t Fi

4 bits Fi - clock rate conversion integer

uint8_t fMax

Maximum Smart card frequency in MHz

uint8_t WI

8 bits WI - work wait time integer

uint8_t Di

4 bits DI - baud rate divisor

uint8_t BWI

4 bits BWI - block wait time integer

uint8_t CWI

4 bits CWI - character wait time integer

uint8_t BGI

4 bits BGI - block guard time integer

uint8_t GTN

8 bits GTN - extended guard time integer

uint8_t IFSC

Indicates IFSC value of the card

uint8_t modeNegotiable

Indicates if the card acts in negotiable or a specific mode.

uint8_t currentD

4 bits DI - current baud rate divisor

uint8_t status

Indicates smart card status

bool t0Indicated

Indicates ff T=0 indicated in TD1 byte

bool t1Indicated

Indicates if T=1 indicated in TD2 byte

bool atrComplete

Indicates whether the ATR received from the card was complete or not

bool atrValid

Indicates whether the ATR received from the card was valid or not

bool present

Indicates if a smart card is present

bool active

Indicates if the smart card is activated

bool faulty

Indicates whether smart card/interface is faulty

smartcard_card_convention_t convention

Card convention, kSMARTCARD_DirectConvention for direct convention, kSMARTCARD_InverseConvention for inverse convention

struct _smartcard_timers_state

#include <fsl_smartcard.h>

Smart card defines the state of the EMV timers in the Smart card driver.

Public Members

volatile bool adtExpired

Indicates whether ADT timer expired

volatile bool wwtExpired

Indicates whether WWT timer expired

volatile bool cwtExpired

Indicates whether CWT timer expired

volatile bool bwtExpired

Indicates whether BWT timer expired

volatile bool initCharTimerExpired

Indicates whether reception timer for initialization character (TS) after the RST has expired

struct _smartcard_interface_config

#include <fsl_smartcard.h>

Defines user specified configuration of Smart card interface.

Public Members

uint32_t smartCardClock

Smart card interface clock [Hz]

uint32_t clockToResetDelay

Indicates clock to RST apply delay [smart card clock cycles]

uint8_t clockModule

Smart card clock module number

uint8_t clockModuleChannel

Smart card clock module channel number

uint8_t clockModuleSourceClock

Smart card clock module source clock [e.g., BusClk]

smartcard_card_voltage_class_t vcc

Smart card voltage class

uint8_t controlPort

Smart card PHY control port instance

uint8_t controlPin

Smart card PHY control pin instance

uint8_t irqPort

Smart card PHY Interrupt port instance

uint8_t irqPin

Smart card PHY Interrupt pin instance

uint8_t resetPort

Smart card reset port instance

uint8_t resetPin

Smart card reset pin instance

uint8_t vsel0Port

Smart card PHY Vsel0 control port instance

uint8_t vsel0Pin

Smart card PHY Vsel0 control pin instance

uint8_t vsel1Port

Smart card PHY Vsel1 control port instance

uint8_t vsel1Pin

Smart card PHY Vsel1 control pin instance

uint8_t dataPort

Smart card PHY data port instance

uint8_t dataPin

Smart card PHY data pin instance

uint8_t dataPinMux

Smart card PHY data pin mux option

uint8_t tsTimerId

Numerical identifier of the External HW timer for Initial character detection

struct _smartcard_xfer

#include <fsl_smartcard.h>

Defines user transfer structure used to initialize transfer.

Public Members

smartcard_direction_t direction

Direction of communication. (RX/TX)

uint8_t *buff

The buffer of data.

size_t size

The number of transferred units.

struct _smartcard_context

#include <fsl_smartcard.h>

Runtime state of the Smart card driver.

Public Members

void *base

Smart card module base address

smartcard_direction_t direction

Direction of communication. (RX/TX)

uint8_t *xBuff

The buffer of data being transferred.

volatile size_t xSize

The number of bytes to be transferred.

volatile bool xIsBusy

True if there is an active transfer.

uint8_t txFifoEntryCount

Number of data word entries in transmit FIFO.

uint8_t rxFifoThreshold

The max value of the receiver FIFO threshold.

smartcard_interface_callback_t interfaceCallback

Callback to invoke after interface IC raised interrupt.

smartcard_transfer_callback_t transferCallback

Callback to invoke after transfer event occur.

void *interfaceCallbackParam

Interface callback parameter pointer.

void *transferCallbackParam

Transfer callback parameter pointer.

smartcard_time_delay_t timeDelay

Function which handles time delay defined by user or RTOS.

smartcard_reset_type_t resetType

Indicates whether a Cold reset or Warm reset was requested.

smartcard_transport_type_t tType

Indicates current transfer protocol (T0 or T1)

volatile smartcard_transfer_state_t transferState

Indicates the current transfer state

smartcard_timers_state_t timersState

Indicates the state of different protocol timers used in driver

smartcard_card_params_t cardParams

Smart card parameters(ATR and current) and interface slots states(ATR and current)

uint8_t IFSD

Indicates the terminal IFSD

smartcard_parity_type_t parity

Indicates current parity even/odd

volatile bool rxtCrossed

Indicates whether RXT thresholds has been crossed

volatile bool txtCrossed

Indicates whether TXT thresholds has been crossed

volatile bool wtxRequested

Indicates whether WTX has been requested or not

volatile bool parityError

Indicates whether a parity error has been detected

uint8_t statusBytes[2]

Used to store Status bytes SW1, SW2 of the last executed card command response

smartcard_interface_config_t interfaceConfig

Smart card interface configuration structure

bool abortTransfer

Used to abort transfer.

Smart Card EMVSIM Driver

void SMARTCARD_EMVSIM_GetDefaultConfig(smartcard_card_params_t *cardParams)

Fills in the smartcard_card_params structure with default values according to the EMV 4.3 specification.

Parameters:

• cardParams – The configuration structure of type smartcard_interface_config_t. Function fill in members: Fi = 372; Di = 1; currentD = 1; WI = 0x0A; GTN = 0x00; with default values.

status_t SMARTCARD_EMVSIM_Init(EMVSIM_Type *base, smartcard_context_t *context, uint32_t srcClock_Hz)

Initializes an EMVSIM peripheral for the Smart card/ISO-7816 operation.

This function un-gates the EMVSIM clock, initializes the module to EMV default settings, configures the IRQ, enables the module-level interrupt to the core and, initializes the driver context.

Parameters:

• base – The EMVSIM peripheral base address.

• context – A pointer to the smart card driver context structure.

• srcClock_Hz – Smart card clock generation module source clock.

Returns:

An error code or kStatus_SMARTCARD_Success.

void SMARTCARD_EMVSIM_Deinit(EMVSIM_Type *base)

This function disables the EMVSIM interrupts, disables the transmitter and receiver, flushes the FIFOs, and gates EMVSIM clock in SIM.

Parameters:

• base – The EMVSIM module base address.

int32_t SMARTCARD_EMVSIM_GetTransferRemainingBytes(EMVSIM_Type *base, smartcard_context_t *context)

Returns whether the previous EMVSIM transfer has finished.

When performing an async transfer, call this function to ascertain the context of the current transfer: in progress (or busy) or complete (success). If the transfer is still in progress, the user can obtain the number of words that have not been transferred.

Parameters:

• base – The EMVSIM module base address.

• context – A pointer to a smart card driver context structure.

Returns:

The number of bytes not transferred.

status_t SMARTCARD_EMVSIM_AbortTransfer(EMVSIM_Type *base, smartcard_context_t *context)

Terminates an asynchronous EMVSIM transfer early.

During an async EMVSIM transfer, the user can terminate the transfer early if the transfer is still in progress.

Parameters:

• base – The EMVSIM peripheral address.

• context – A pointer to a smart card driver context structure.

Return values:

• kStatus_SMARTCARD_Success – The transmit abort was successful.

• kStatus_SMARTCARD_NoTransmitInProgress – No transmission is currently in progress.

status_t SMARTCARD_EMVSIM_TransferNonBlocking(EMVSIM_Type *base, smartcard_context_t *context, smartcard_xfer_t *xfer)

Transfer data using interrupts.

A non-blocking (also known as asynchronous) function means that the function returns immediately after initiating the transfer function. The application has to get the transfer status to see when the transfer is complete. In other words, after calling the non-blocking (asynchronous) transfer function, the application must get the transfer status to check if the transmit is completed or not.

Parameters:

• base – The EMVSIM peripheral base address.

• context – A pointer to a smart card driver context structure.

• xfer – A pointer to the smart card transfer structure where the linked buffers and sizes are stored.

Returns:

An error code or kStatus_SMARTCARD_Success.

status_t SMARTCARD_EMVSIM_Control(EMVSIM_Type *base, smartcard_context_t *context, smartcard_control_t control, uint32_t param)

Controls the EMVSIM module per different user request.

return kStatus_SMARTCARD_Success in success. return kStatus_SMARTCARD_OtherError in case of error.

Parameters:

• base – The EMVSIM peripheral base address.

• context – A pointer to a smart card driver context structure.

• control – Control type.

• param – Integer value of specific to control command.

void SMARTCARD_EMVSIM_IRQHandler(EMVSIM_Type *base, smartcard_context_t *context)

Handles EMVSIM module interrupts.

Parameters:

• base – The EMVSIM peripheral base address.

• context – A pointer to a smart card driver context structure.

enum _emvsim_gpc_clock_select

General Purpose Counter clock selections.

Values:

enumerator kEMVSIM_GPCClockDisable

Disabled

enumerator kEMVSIM_GPCCardClock

Card clock

enumerator kEMVSIM_GPCRxClock

Receive clock

enumerator kEMVSIM_GPCTxClock

Transmit ETU clock

enum _presence_detect_edge

EMVSIM card presence detection edge control.

Values:

enumerator kEMVSIM_DetectOnFallingEdge

Presence detected on the falling edge

enumerator kEMVSIM_DetectOnRisingEdge

Presence detected on the rising edge

enum _presence_detect_status

EMVSIM card presence detection status.

Values:

enumerator kEMVSIM_DetectPinIsLow

Presence detected pin is logic low

enumerator kEMVSIM_DetectPinIsHigh

Presence detected pin is logic high

typedef enum _emvsim_gpc_clock_select emvsim_gpc_clock_select_t

General Purpose Counter clock selections.

typedef enum _presence_detect_edge emvsim_presence_detect_edge_t

EMVSIM card presence detection edge control.

typedef enum _presence_detect_status emvsim_presence_detect_status_t

EMVSIM card presence detection status.

SMARTCARD_EMV_RX_NACK_THRESHOLD

EMV RX NACK interrupt generation threshold.

SMARTCARD_EMV_TX_NACK_THRESHOLD

EMV TX NACK interrupt generation threshold.

SMARTCARD_WWT_ADJUSTMENT

Smart card Word Wait Timer adjustment value.

SMARTCARD_CWT_ADJUSTMENT

Smart card Character Wait Timer adjustment value.

Smart Card PHY Driver

void SMARTCARD_PHY_GetDefaultConfig(smartcard_interface_config_t *config)

Fills in the configuration structure with default values.

Parameters:

• config – The Smart card user configuration structure which contains configuration structure of type smartcard_interface_config_t. Function fill in members: clockToResetDelay = 42000, vcc = kSmartcardVoltageClassB3_3V, with default values.

status_t SMARTCARD_PHY_Init(void *base, smartcard_interface_config_t const *config, uint32_t srcClock_Hz)

Initializes a Smart card interface instance.

Parameters:

• base – The Smart card peripheral base address.

• config – The user configuration structure of type smartcard_interface_config_t. Call the function SMARTCARD_PHY_GetDefaultConfig() to fill the configuration structure.

• srcClock_Hz – Smart card clock generation module source clock.

Return values:

kStatus_SMARTCARD_Success – or kStatus_SMARTCARD_OtherError in case of error.

void SMARTCARD_PHY_Deinit(void *base, smartcard_interface_config_t const *config)

De-initializes a Smart card interface, stops the Smart card clock, and disables the VCC.

Parameters:

• base – The Smart card peripheral module base address.

• config – The user configuration structure of type smartcard_interface_config_t.

status_t SMARTCARD_PHY_Activate(void *base, smartcard_context_t *context, smartcard_reset_type_t resetType)

Activates the Smart card IC.

Parameters:

• base – The Smart card peripheral module base address.

• context – A pointer to a Smart card driver context structure.

• resetType – type of reset to be performed, possible values = kSmartcardColdReset, kSmartcardWarmReset

Return values:

kStatus_SMARTCARD_Success – or kStatus_SMARTCARD_OtherError in case of error.

status_t SMARTCARD_PHY_Deactivate(void *base, smartcard_context_t *context)

De-activates the Smart card IC.

Parameters:

• base – The Smart card peripheral module base address.

• context – A pointer to a Smart card driver context structure.

Return values:

kStatus_SMARTCARD_Success – or kStatus_SMARTCARD_OtherError in case of error.

status_t SMARTCARD_PHY_Control(void *base, smartcard_context_t *context, smartcard_interface_control_t control, uint32_t param)

Controls the Smart card interface IC.

Parameters:

• base – The Smart card peripheral module base address.

• context – A pointer to a Smart card driver context structure.

• control – A interface command type.

• param – Integer value specific to control type

Return values:

kStatus_SMARTCARD_Success – or kStatus_SMARTCARD_OtherError in case of error.

SMARTCARD_ATR_DURATION_ADJUSTMENT

Smart card definition which specifies the adjustment number of clock cycles during which an ATR string has to be received.

SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT

Smart card definition which specifies the adjustment number of clock cycles until an initial ‘TS’ character has to be received.

Smart Card PHY EMVSIM Driver

SNVS: Secure Non-Volatile Storage

Secure Non-Volatile Storage High-Power

void SNVS_HP_Init(SNVS_Type *base)

Initialize the SNVS.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

• base – SNVS peripheral base address

void SNVS_HP_Deinit(SNVS_Type *base)

Deinitialize the SNVS.

Parameters:

• base – SNVS peripheral base address

void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

• base – SNVS peripheral base address

• config – Pointer to the user’s SNVS configuration structure.

void SNVS_HP_RTC_Deinit(SNVS_Type *base)

Stops the RTC and SRTC timers.

Parameters:

• base – SNVS peripheral base address

void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config)

Fills in the SNVS config struct with the default settings.

The default values are as follows.

config->rtccalenable = false;
config->rtccalvalue = 0U;
config->PIFreq = 0U;

Parameters:

• config – Pointer to the user’s SNVS configuration structure.

status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime)

Sets the SNVS RTC date and time according to the given time structure.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the date and time details are stored.

Returns:

kStatus_Success: Success in setting the time and starting the SNVS RTC kStatus_InvalidArgument: Error because the datetime format is incorrect

void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)

Gets the SNVS RTC time and stores it in the given time structure.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the date and time details are stored.

status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime)

Sets the SNVS RTC alarm time.

The function sets the RTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error.

Parameters:

• base – SNVS peripheral base address

• alarmTime – Pointer to the structure where the alarm time is stored.

Returns:

kStatus_Success: success in setting the SNVS RTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed

void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)

Returns the SNVS RTC alarm time.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the alarm date and time details are stored.

void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base)

The function synchronizes RTC counter value with SRTC.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask)

Enables the selected SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_hp_interrupts_t

static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask)

Disables the selected SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

• mask – The interrupts to disable. This is a logical OR of members of the enumeration :: _snvs_hp_interrupts_t

uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base)

Gets the enabled SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration :: _snvs_hp_interrupts_t

uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base)

Gets the SNVS status flags.

Parameters:

• base – SNVS peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration :: _snvs_hp_status_flags_t

static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clears the SNVS status flags.

Parameters:

• base – SNVS peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration :: _snvs_hp_status_flags_t

static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base)

Starts the SNVS RTC time counter.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base)

Stops the SNVS RTC time counter.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_EnableHighAssuranceCounter(SNVS_Type *base, bool enable)

Enable or disable the High Assurance Counter (HAC)

Parameters:

• base – SNVS peripheral base address

• enable – Pass true to enable, false to disable.

static inline void SNVS_HP_StartHighAssuranceCounter(SNVS_Type *base, bool start)

Start or stop the High Assurance Counter (HAC)

Parameters:

• base – SNVS peripheral base address

• start – Pass true to start, false to stop.

static inline void SNVS_HP_SetHighAssuranceCounterInitialValue(SNVS_Type *base, uint32_t value)

Set the High Assurance Counter (HAC) initialize value.

Parameters:

• base – SNVS peripheral base address

• value – The initial value to set.

static inline void SNVS_HP_LoadHighAssuranceCounter(SNVS_Type *base)

Load the High Assurance Counter (HAC)

This function loads the HAC initialize value to counter register.

Parameters:

• base – SNVS peripheral base address

static inline uint32_t SNVS_HP_GetHighAssuranceCounter(SNVS_Type *base)

Get the current High Assurance Counter (HAC) value.

Parameters:

• base – SNVS peripheral base address

Returns:

HAC currnet value.

static inline void SNVS_HP_ClearHighAssuranceCounter(SNVS_Type *base)

Clear the High Assurance Counter (HAC)

This function can be called in a functional or soft fail state. When the HAC is enabled:

• If the HAC is cleared in the soft fail state, the SSM transitions to the hard fail state immediately;

• If the HAC is cleared in functional state, the SSM will transition to hard fail immediately after transitioning to soft fail.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_LockHighAssuranceCounter(SNVS_Type *base)

Lock the High Assurance Counter (HAC)

Once locked, the HAC initialize value could not be changed, the HAC enable status could not be changed. This could only be unlocked by system reset.

Parameters:

• base – SNVS peripheral base address

FSL_SNVS_HP_DRIVER_VERSION

Version 2.3.2

enum _snvs_hp_interrupts

List of SNVS interrupts.

Values:

enumerator kSNVS_RTC_AlarmInterrupt

RTC time alarm

enumerator kSNVS_RTC_PeriodicInterrupt

RTC periodic interrupt

enum _snvs_hp_status_flags

List of SNVS flags.

Values:

enumerator kSNVS_RTC_AlarmInterruptFlag

RTC time alarm flag

enumerator kSNVS_RTC_PeriodicInterruptFlag

RTC periodic interrupt flag

enumerator kSNVS_ZMK_ZeroFlag

The ZMK is zero

enumerator kSNVS_OTPMK_ZeroFlag

The OTPMK is zero

enum _snvs_hp_sv_status_flags

List of SNVS security violation flags.

Values:

enumerator kSNVS_LP_ViolationFlag

Low Power section Security Violation

enumerator kSNVS_ZMK_EccFailFlag

Zeroizable Master Key Error Correcting Code Check Failure

enumerator kSNVS_LP_SoftwareViolationFlag

LP Software Security Violation

enumerator kSNVS_FatalSoftwareViolationFlag

Software Fatal Security Violation

enumerator kSNVS_SoftwareViolationFlag

Software Security Violation

enumerator kSNVS_Violation0Flag

Security Violation 0

enumerator kSNVS_Violation1Flag

Security Violation 1

enumerator kSNVS_Violation2Flag

Security Violation 2

enumerator kSNVS_Violation4Flag

Security Violation 4

enumerator kSNVS_Violation5Flag

Security Violation 5

enum _snvs_hp_ssm_state

List of SNVS Security State Machine State.

Values:

enumerator kSNVS_SSMInit

Init

enumerator kSNVS_SSMHardFail

Hard Fail

enumerator kSNVS_SSMSoftFail

Soft Fail

enumerator kSNVS_SSMInitInter

Init Intermediate (transition state between Init and Check)

enumerator kSNVS_SSMCheck

Check

enumerator kSNVS_SSMNonSecure

Non-Secure

enumerator kSNVS_SSMTrusted

Trusted

enumerator kSNVS_SSMSecure

Secure

typedef enum _snvs_hp_interrupts snvs_hp_interrupts_t

List of SNVS interrupts.

typedef enum _snvs_hp_status_flags snvs_hp_status_flags_t

List of SNVS flags.

typedef enum _snvs_hp_sv_status_flags snvs_hp_sv_status_flags_t

List of SNVS security violation flags.

typedef struct _snvs_hp_rtc_datetime snvs_hp_rtc_datetime_t

Structure is used to hold the date and time.

typedef struct _snvs_hp_rtc_config snvs_hp_rtc_config_t

SNVS config structure.

This structure holds the configuration settings for the SNVS peripheral. To initialize this structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef enum _snvs_hp_ssm_state snvs_hp_ssm_state_t

List of SNVS Security State Machine State.

static inline void SNVS_HP_EnableMasterKeySelection(SNVS_Type *base, bool enable)

Enable or disable master key selection.

Parameters:

• base – SNVS peripheral base address

• enable – Pass true to enable, false to disable.

static inline void SNVS_HP_ProgramZeroizableMasterKey(SNVS_Type *base)

Trigger to program Zeroizable Master Key.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_ChangeSSMState(SNVS_Type *base)

Trigger SSM State Transition.

Trigger state transition of the system security monitor (SSM). It results only the following transitions of the SSM:

• Check State -> Non-Secure (when Non-Secure Boot and not in Fab Configuration)

• Check State –> Trusted (when Secure Boot or in Fab Configuration )

• Trusted State –> Secure

• Secure State –> Trusted

• Soft Fail –> Non-Secure

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_SetSoftwareFatalSecurityViolation(SNVS_Type *base)

Trigger Software Fatal Security Violation.

The result SSM state transition is:

• Check State -> Soft Fail

• Non-Secure State -> Soft Fail

• Trusted State -> Soft Fail

• Secure State -> Soft Fail

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_HP_SetSoftwareSecurityViolation(SNVS_Type *base)

Trigger Software Security Violation.

The result SSM state transition is:

• Check -> Non-Secure

• Trusted -> Soft Fail

• Secure -> Soft Fail

Parameters:

• base – SNVS peripheral base address

static inline snvs_hp_ssm_state_t SNVS_HP_GetSSMState(SNVS_Type *base)

Get current SSM State.

Parameters:

• base – SNVS peripheral base address

Returns:

Current SSM state

static inline void SNVS_HP_ResetLP(SNVS_Type *base)

Reset the SNVS LP section.

Reset the LP section except SRTC and Time alarm.

Parameters:

• base – SNVS peripheral base address

static inline uint32_t SNVS_HP_GetStatusFlags(SNVS_Type *base)

Get the SNVS HP status flags.

The flags are returned as the OR’ed value f the enumeration :: _snvs_hp_status_flags_t.

Parameters:

• base – SNVS peripheral base address

Returns:

The OR’ed value of status flags.

static inline void SNVS_HP_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clear the SNVS HP status flags.

The flags to clear are passed in as the OR’ed value of the enumeration :: _snvs_hp_status_flags_t. Only these flags could be cleared using this API.

• kSNVS_RTC_PeriodicInterruptFlag

• kSNVS_RTC_AlarmInterruptFlag

Parameters:

• base – SNVS peripheral base address

• mask – OR’ed value of the flags to clear.

static inline uint32_t SNVS_HP_GetSecurityViolationStatusFlags(SNVS_Type *base)

Get the SNVS HP security violation status flags.

The flags are returned as the OR’ed value of the enumeration :: _snvs_hp_sv_status_flags_t.

Parameters:

• base – SNVS peripheral base address

Returns:

The OR’ed value of security violation status flags.

static inline void SNVS_HP_ClearSecurityViolationStatusFlags(SNVS_Type *base, uint32_t mask)

Clear the SNVS HP security violation status flags.

The flags to clear are passed in as the OR’ed value of the enumeration :: _snvs_hp_sv_status_flags_t. Only these flags could be cleared using this API.

• kSNVS_ZMK_EccFailFlag

• kSNVS_Violation0Flag

• kSNVS_Violation1Flag

• kSNVS_Violation2Flag

• kSNVS_Violation3Flag

• kSNVS_Violation4Flag

• kSNVS_Violation5Flag

Parameters:

• base – SNVS peripheral base address

• mask – OR’ed value of the flags to clear.

SNVS_HPSVSR_SV0_MASK

SNVS_HPSVSR_SV1_MASK

SNVS_HPSVSR_SV2_MASK

SNVS_HPSVSR_SV4_MASK

SNVS_HPSVSR_SV5_MASK

SNVS_MAKE_HP_SV_FLAG(x)

Macro to make security violation flag.

Macro help to make security violation flag kSNVS_Violation0Flag to kSNVS_Violation5Flag, For example, SNVS_MAKE_HP_SV_FLAG(0) is kSNVS_Violation0Flag.

struct _snvs_hp_rtc_datetime

#include <fsl_snvs_hp.h>

Structure is used to hold the date and time.

Public Members

uint16_t year

Range from 1970 to 2099.

uint8_t month

Range from 1 to 12.

uint8_t day

Range from 1 to 31 (depending on month).

uint8_t hour

Range from 0 to 23.

uint8_t minute

Range from 0 to 59.

uint8_t second

Range from 0 to 59.

struct _snvs_hp_rtc_config

#include <fsl_snvs_hp.h>

SNVS config structure.

This structure holds the configuration settings for the SNVS peripheral. To initialize this structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

bool rtcCalEnable

true: RTC calibration mechanism is enabled; false:No calibration is used

uint32_t rtcCalValue

Defines signed calibration value for nonsecure RTC; This is a 5-bit 2’s complement value, range from -16 to +15

uint32_t periodicInterruptFreq

Defines frequency of the periodic interrupt; Range from 0 to 15

Secure Non-Volatile Storage Low-Power

void SNVS_LP_Init(SNVS_Type *base)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

• base – SNVS peripheral base address

void SNVS_LP_Deinit(SNVS_Type *base)

Deinit the SNVS LP section.

Parameters:

• base – SNVS peripheral base address

status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime)

Sets the SNVS SRTC date and time according to the given time structure.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the date and time details are stored.

Returns:

kStatus_Success: Success in setting the time and starting the SNVS SRTC kStatus_InvalidArgument: Error because the datetime format is incorrect

void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)

Gets the SNVS SRTC time and stores it in the given time structure.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the date and time details are stored.

status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime)

Sets the SNVS SRTC alarm time.

The function sets the SRTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error. Please note, that SRTC alarm has limited resolution because only 32 most significant bits of SRTC counter are compared to SRTC Alarm register. If the alarm time is beyond SRTC resolution, the function does not set the alarm and returns an error.

Parameters:

• base – SNVS peripheral base address

• alarmTime – Pointer to the structure where the alarm time is stored.

Returns:

kStatus_Success: success in setting the SNVS SRTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed or is beyond resolution

void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)

Returns the SNVS SRTC alarm time.

Parameters:

• base – SNVS peripheral base address

• datetime – Pointer to the structure where the alarm date and time details are stored.

static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask)

Enables the selected SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask)

Disables the selected SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base)

Gets the enabled SNVS interrupts.

Parameters:

• base – SNVS peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base)

Gets the SNVS status flags.

Parameters:

• base – SNVS peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration :: _snvs_lp_srtc_status_flags

static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clears the SNVS status flags.

Parameters:

• base – SNVS peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_status_flags

static inline void SNVS_LP_SRTC_StartTimer(SNVS_Type *base)

Starts the SNVS SRTC time counter.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_LP_SRTC_StopTimer(SNVS_Type *base)

Stops the SNVS SRTC time counter.

Parameters:

• base – SNVS peripheral base address

void SNVS_LP_EnablePassiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin, snvs_lp_passive_tamper_t config)

Enables the specified SNVS external tamper.

Parameters:

• base – SNVS peripheral base address

• pin – SNVS external tamper pin

• config – Configuration structure of external passive tamper

status_t SNVS_LP_EnableTxActiveTamper(SNVS_Type *base, snvs_lp_active_tx_tamper_t pin, tamper_active_tx_config_t config)

Enable active tamper tx external pad.

Parameters:

• base – SNVS peripheral base address

• pin – SNVS active tamper pin

• config – Configuration structure of external active tamper

status_t SNVS_LP_EnableRxActiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t rx, tamper_active_rx_config_t config)

Enable active tamper rx external pad.

Parameters:

• base – SNVS peripheral base address

• rx – SNVS external RX tamper pin

• config – SNVS RX tamper config structure

status_t SNVS_LP_SetVoltageTamper(SNVS_Type *base, bool enable)

Sets voltage tamper detect.

Parameters:

• base – SNVS peripheral base address

• enable – True if enable false if disable

status_t SNVS_LP_SetTemperatureTamper(SNVS_Type *base, bool enable)

Sets temperature tamper detect.

Parameters:

• base – SNVS peripheral base address

• enable – True if enable false if disable

status_t SNVS_LP_SetClockTamper(SNVS_Type *base, bool enable)

Sets clock tamper detect.

Parameters:

• base – SNVS peripheral base address

• enable – True if enable false if disable

snvs_lp_external_tamper_status_t SNVS_LP_CheckVoltageTamper(SNVS_Type *base)

brief Check voltage tamper

param base SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_CheckTemperatureTamper(SNVS_Type *base)

Check temperature tamper.

Parameters:

• base – SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_CheckClockTamper(SNVS_Type *base)

brief Check clock tamper

param base SNVS peripheral base address

void SNVS_LP_TamperPinTx_GetDefaultConfig(tamper_active_tx_config_t *config)

Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->clock = kSNVS_ActiveTamper16HZ; config->seed = 0U; config->polynomial = 0U; endcode

Parameters:

• config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_TamperPinRx_GetDefaultConfig(tamper_active_rx_config_t *config)

brief Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->filterenable = 0U; config->filter = 0U; config->tx = kSNVS_ActiveTamper1; endcode param config Pointer to the user’s SNVS configuration structure.

void SNVS_LP_PassiveTamperPin_GetDefaultConfig(snvs_lp_passive_tamper_t *config)

Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->polarity = 0U; config->filterenable = 0U; if available on SoC config->filter = 0U; if available on SoC endcode

Parameters:

• config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Disables the specified SNVS external tamper.

Parameters:

• base – SNVS peripheral base address

• pin – SNVS external tamper pin

void SNVS_LP_DisableAllExternalTamper(SNVS_Type *base)

Disable all external tamper.

Parameters:

• base – SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Returns status of the specified external tamper.

Parameters:

• base – SNVS peripheral base address

• pin – SNVS external tamper pin

Returns:

The status flag. This is the enumeration :: _snvs_lp_external_tamper_status

void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Clears status of the specified external tamper.

Parameters:

• base – SNVS peripheral base address

• pin – SNVS external tamper pin

void SNVS_LP_ClearAllExternalTamperStatus(SNVS_Type *base)

Clears status of the all external tamper.

Parameters:

• base – SNVS peripheral base address

static inline void SNVS_LP_EnableMonotonicCounter(SNVS_Type *base, bool enable)

Enable or disable the Monotonic Counter.

Parameters:

• base – SNVS peripheral base address

• enable – Pass true to enable, false to disable.

uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base)

Get the current Monotonic Counter.

Parameters:

• base – SNVS peripheral base address

Returns:

Current Monotonic Counter value.

static inline void SNVS_LP_IncreaseMonotonicCounter(SNVS_Type *base)

Increase the Monotonic Counter.

Increase the Monotonic Counter by 1.

Parameters:

• base – SNVS peripheral base address

void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[8U])

Write Zeroizable Master Key (ZMK) to the SNVS registers.

Parameters:

• base – SNVS peripheral base address

• ZMKey – The ZMK write to the SNVS register.

static inline void SNVS_LP_SetZeroizableMasterKeyValid(SNVS_Type *base, bool valid)

Set Zeroizable Master Key valid.

This API could only be called when using software programming mode. After writing ZMK using SNVS_LP_WriteZeroizableMasterKey, call this API to make the ZMK valid.

Parameters:

• base – SNVS peripheral base address

• valid – Pass true to set valid, false to set invalid.

static inline bool SNVS_LP_GetZeroizableMasterKeyValid(SNVS_Type *base)

Get Zeroizable Master Key valid status.

In hardware programming mode, call this API to check whether the ZMK is valid.

Parameters:

• base – SNVS peripheral base address

Returns:

true if valid, false if invalid.

static inline void SNVS_LP_SetZeroizableMasterKeyProgramMode(SNVS_Type *base, snvs_lp_zmk_program_mode_t mode)

Set Zeroizable Master Key programming mode.

Parameters:

• base – SNVS peripheral base address

• mode – ZMK programming mode.

static inline void SNVS_LP_EnableZeroizableMasterKeyECC(SNVS_Type *base, bool enable)

Enable or disable Zeroizable Master Key ECC.

Parameters:

• base – SNVS peripheral base address

• enable – Pass true to enable, false to disable.

static inline void SNVS_LP_SetMasterKeyMode(SNVS_Type *base, snvs_lp_master_key_mode_t mode)

Set SNVS Master Key mode.

Note

When kSNVS_ZMK or kSNVS_CMK used, the SNVS_HP must be configured to enable the master key selection.

Parameters:

• base – SNVS peripheral base address

• mode – Master Key mode.

FSL_SNVS_LP_DRIVER_VERSION

Version 2.4.6

enum _snvs_lp_srtc_interrupts

List of SNVS_LP interrupts.

Values:

enumerator kSNVS_SRTC_AlarmInterrupt

SRTC time alarm.

enum _snvs_lp_srtc_status_flags

List of SNVS_LP flags.

Values:

enumerator kSNVS_SRTC_AlarmInterruptFlag

SRTC time alarm flag

enum _snvs_lp_external_tamper

List of SNVS_LP external tampers.

Values:

enumerator kSNVS_ExternalTamper1

enum _snvs_lp_active_tamper

List of SNVS_LP active tampers.

Values:

enumerator kSNVS_ActiveTamper1

enumerator kSNVS_ActiveTamper2

enumerator kSNVS_ActiveTamper3

enumerator kSNVS_ActiveTamper4

enumerator kSNVS_ActiveTamper5

enum _snvs_lp_active_clock

List of SNVS_LP external tampers.

Values:

enumerator kSNVS_ActiveTamper16HZ

enumerator kSNVS_ActiveTamper8HZ

enumerator kSNVS_ActiveTamper4HZ

enumerator kSNVS_ActiveTamper2HZ

enum _snvs_lp_external_tamper_status

List of SNVS_LP external tampers status.

Values:

enumerator kSNVS_TamperNotDetected

enumerator kSNVS_TamperDetected

enum _snvs_lp_external_tamper_polarity

SNVS_LP external tamper polarity.

Values:

enumerator kSNVS_ExternalTamperActiveLow

enumerator kSNVS_ExternalTamperActiveHigh

enum _snvs_lp_zmk_program_mode

SNVS_LP Zeroizable Master Key programming mode.

Values:

enumerator kSNVS_ZMKSoftwareProgram

Software programming mode.

enumerator kSNVS_ZMKHardwareProgram

Hardware programming mode.

enum _snvs_lp_master_key_mode

SNVS_LP Master Key mode.

Values:

enumerator kSNVS_OTPMK

One Time Programmable Master Key.

enumerator kSNVS_ZMK

Zeroizable Master Key.

enumerator kSNVS_CMK

Combined Master Key, it is XOR of OPTMK and ZMK.

typedef enum _snvs_lp_srtc_interrupts snvs_lp_srtc_interrupts_t

List of SNVS_LP interrupts.

typedef enum _snvs_lp_srtc_status_flags snvs_lp_srtc_status_flags_t

List of SNVS_LP flags.

typedef enum _snvs_lp_external_tamper snvs_lp_external_tamper_t

List of SNVS_LP external tampers.

typedef enum _snvs_lp_active_tamper snvs_lp_active_tx_tamper_t

List of SNVS_LP active tampers.

typedef enum _snvs_lp_active_clock snvs_lp_active_clock_t

List of SNVS_LP external tampers.

typedef enum _snvs_lp_external_tamper_status snvs_lp_external_tamper_status_t

List of SNVS_LP external tampers status.

typedef enum _snvs_lp_external_tamper_polarity snvs_lp_external_tamper_polarity_t

SNVS_LP external tamper polarity.

typedef struct _snvs_lp_srtc_datetime snvs_lp_srtc_datetime_t

Structure is used to hold the date and time.

typedef struct _snvs_lp_srtc_config snvs_lp_srtc_config_t

SNVS_LP config structure.

This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef enum _snvs_lp_zmk_program_mode snvs_lp_zmk_program_mode_t

SNVS_LP Zeroizable Master Key programming mode.

typedef enum _snvs_lp_master_key_mode snvs_lp_master_key_mode_t

SNVS_LP Master Key mode.

void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

• base – SNVS peripheral base address

• config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_SRTC_Deinit(SNVS_Type *base)

Stops the SRTC timer.

Parameters:

• base – SNVS peripheral base address

void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config)

Fills in the SNVS_LP config struct with the default settings.

The default values are as follows.

config->srtccalenable = false;
config->srtccalvalue = 0U;

Parameters:

• config – Pointer to the user’s SNVS configuration structure.

SNVS_ZMK_REG_COUNT

Define of SNVS_LP Zeroizable Master Key registers.

SNVS_LP_MAX_TAMPER

Define of SNVS_LP Max possible tamper.

struct tamper_active_tx_config_t

#include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP active TX tamper pins.

struct tamper_active_rx_config_t

#include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP active RX tamper pins.

struct snvs_lp_passive_tamper_t

#include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP passive tamper pins.

struct _snvs_lp_srtc_datetime

#include <fsl_snvs_lp.h>

Structure is used to hold the date and time.

Public Members

uint16_t year

Range from 1970 to 2099.

uint8_t month

Range from 1 to 12.

uint8_t day

Range from 1 to 31 (depending on month).

uint8_t hour

Range from 0 to 23.

uint8_t minute

Range from 0 to 59.

uint8_t second

Range from 0 to 59.

struct _snvs_lp_srtc_config

#include <fsl_snvs_lp.h>

SNVS_LP config structure.

This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

bool srtcCalEnable

true: SRTC calibration mechanism is enabled; false: No calibration is used

uint32_t srtcCalValue

Defines signed calibration value for SRTC; This is a 5-bit 2’s complement value, range from -16 to +15

Soc_mipi_csi2rx

void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset)

Assert or deassert CSI2RX reset in system level.

Note

Don’t call this function directly.

Parameters:

• base – The CSI2RX peripheral base address.

• reset – Pass in true to set to reset state, false to release reset.

void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk)

Initialize the CSI2RX interface.

Note

Don’t call this function directly.

Parameters:

• base – The CSI2RX peripheral base address.

• tHsSettle_EscClk – t-HS_SETTLE in esc clock period.

void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base)

Deinitialize the CSI2RX interface.

Note

Don’t call this function directly.

Parameters:

• base – The CSI2RX peripheral base address.

FSL_SOC_MIPI_CSI2RX_DRIVER_VERSION

Driver version.

Soc_mipi_dsi

FSL_SOC_MIPI_DSI_DRIVER_VERSION

Driver version 2.0.0.

DSI_DPHY_PLL_VCO_MAX

DSI_DPHY_PLL_VCO_MIN

FSL_COMPONENT_ID

Soc_src

enum _src_core_name

System core.

Values:

enumerator kSRC_CM7Core

System Core CM4.

enumerator kSRC_CM4Core

System Core CM7.

enum _src_boot_fuse_selection

The enumeration of the boot fuse selection.

Values:

enumerator kSRC_SerialDownloaderBootFlow

The Boot flow jumps directly to the serial downloader.

enumerator kSRC_NormalBootFlow

The Boot flow follows the Normal Boot flow.

enum _src_global_system_reset_source

The enumeration of global system reset sources.

Values:

enumerator kSRC_WdogReset

WDOG triggers the global system reset.

enumerator kSRC_Wdog3Reset

WDOG3 triggers the global system reset.

enumerator kSRC_Wdog4Reset

WODG4 triggers the global system reset.

enumerator kSRC_M4LockUpReset

M4 core lockup triggers the global system reset.

enumerator kSRC_M7LockUpReset

M7 core lockup triggers the global system reset.

enumerator kSRC_M4RequestReset

M4 core request triggers the global system reset.

enumerator kSRC_M7RequestReset

M7 core request triggers the global system reset.

enumerator kSRC_TempsenseReset

Tempsense trigggers the global system reset.

enumerator kSRC_CSUReset

CSU triggers the global system reset.

enumerator kSRC_JageSoftwareReset

JATG software triggers the global system reset.

enumerator kSRC_OverVoltageReset

Over voltage triggers the global system reset.

enum _src_global_system_reset_status_flags

The enumeration of reset status flags.

Values:

enumerator kSRC_M7CoreIppResetFlag

The M7 Core reset is the result of ipp_reset_b pin.

enumerator kSRC_M7CoreM7RequestResetFlag

The M7 Core reset is the result of M7 core reset request.

enumerator kSRC_M7CoreM7LockUpResetFlag

The M7 Core reset is the result of M7 core lock up.

enumerator kSRC_M7CoreCSUResetFlag

The M7 Core reset is the result of csu_reset_b input.

enumerator kSRC_M7CoreIppUserResetFlag

The M7 Core reset is the result of ipp_user_reset_b qualified reset.

enumerator kSRC_M7CoreWdogResetFlag

The M7 Core reset is the result of the watchdog time-out event.

enumerator kSRC_M7CoreJtagResetFlag

The M7 Core reset is the result of HIGH-Z reset from JTAG.

enumerator kSRC_M7CoreJtagSWResetFlag

The M7 Core reset is the result of software reset from JTAG.

enumerator kSRC_M7CoreWdog3ResetFlag

The M7 Core reset is the result of watchdog3 time-out event.

enumerator kSRC_M7CoreWdog4ResetFlag

The M7 Core reset is the result of watchdog4 time-out event.

enumerator kSRC_M7CoreTempsenseResetFlag

The M7 Core reset is the result of on-chip temperature sensor.

enumerator kSRC_M7CoreM4RequestResetFlag

The M7 Core reset is the result of M4 CPU reset request.

enumerator kSRC_M7CoreM4LockUpResetFlag

The M7 Core reset is the result of M4 CPU lock up.

enumerator kSRC_M7CoreOverVoltageResetFlag

The M7 Core reset is the result of over voltage.

enumerator kSRC_M7CoreCdogResetFlag

The M7 Core reset is the result of Cdog.

enumerator kSRC_M4CoreIppResetFlag

The M4 Core reset is the result of ipp_reset_b pin.

enumerator kSRC_M4CoreM4RequestResetFlag

The M4 Core reset is the result of M4 core reset request.

enumerator kSRC_M4CoreM4LockUpResetFlag

The M4 Core reset is the result of M4 core lock up.

enumerator kSRC_M4CoreCSUResetFlag

The M4 Core reset is the result of csu_reset_b input.

enumerator kSRC_M4CoreIppUserResetFlag

The M4 Core reset is the result of ipp_user_reset_b qualified reset.

enumerator kSRC_M4CoreWdogResetFlag

The M4 Core reset is the result of the watchdog time-out event.

enumerator kSRC_M4CoreJtagResetFlag

The M4 Core reset is the result of HIGH-Z reset from JTAG.

enumerator kSRC_M4CoreJtagSWResetFlag

The M4 Core reset is the result of software reset from JTAG.

enumerator kSRC_M4CoreWdog3ResetFlag

The M4 Core reset is the result of watchdog3 time-out event.

enumerator kSRC_M4CoreWdog4ResetFlag

The M4 Core reset is the result of watchdog4 time-out event.

enumerator kSRC_M4CoreTempsenseResetFlag

The M4 Core reset is the result of on-chip temperature sensor.

enumerator kSRC_M4CoreM7RequestResetFlag

The M4 Core reset is the result of M7 CPU reset request.

enumerator kSRC_M4CoreM7LockUpResetFlag

The M4 Core reset is the result of M7 CPU lock up.

enumerator kSRC_M4CoreOverVoltageResetFlag

The M4 Core reset is the result of over voltage.

enumerator kSRC_M4CoreCdogResetFlag

The M4 Core reset is the result of Cdog.

enum _src_global_system_reset_mode

The enumeration of global system reset mode.

Values:

enumerator kSRC_ResetSystem

Generate the global system reset.

enumerator kSRC_DoNotResetSystem

Do not generate the global system reset.

enum _src_reset_slice_name

The enumeration of the slice name.

Values:

enumerator kSRC_MegaSlice

Megamix reset slice.

enumerator kSRC_DisplaySlice

Displaymix reset slice.

enumerator kSRC_WakeUpSlice

Wakeupmix reset slice.

enumerator kSRC_LpsrSlice

Lpsrmix reset slice.

enumerator kSRC_M4CoreSlice

M4 core reset slice.

enumerator kSRC_M7CoreSlice

M7 core reset slice.

enumerator kSRC_M4DebugSlice

M4 debug reset slice.

enumerator kSRC_M7DebugSlice

M7 debug reset slice.

enumerator kSRC_Usbphy1Slice

USBPHY1 reset slice.

enumerator kSRC_Usbphy2Slice

USBPHY2 reset slice.

enum _src_domain_mode_selection

The enumeration of the domain mode.

Values:

enumerator kSRC_Cpu0RunModeAssertReset

CPU0 in run mode will assert slice reset.

enumerator kSRC_Cpu0WaitModeAssertReset

CPU0 in wait mode will assert reset.

enumerator kSRC_Cpu0StopModeAssertReset

CPU0 in stop mode will assert reset.

enumerator kSRC_Cpu0SuspendModeAssertReset

CPU0 in suspend mode will assert reset.

enumerator kSRC_Cpu1RunModeAssertReset

CPU1 in run mode will assert slice reset.

enumerator kSRC_Cpu1WaitModeAssertReset

CPU1 in wait mode will assert reset.

enumerator kSRC_Cpu1StopModeAssertReset

CPU1 in stop mode will assert reset.

enumerator kSRC_Cpu1SuspendModeAssertReset

CPU1 in suspend mode will assert reset.

enum _src_setpoint_selection

The enumeration of setpoint.

Values:

enumerator kSRC_SetPoint0AssertReset

In setpoint0 will assert slice reset.

enumerator kSRC_SetPoint1AssertReset

In setpoint1 will assert slice reset.

enumerator kSRC_SetPoint2AssertReset

In setpoint2 will assert slice reset.

enumerator kSRC_SetPoint3AssertReset

In setpoint3 will assert slice reset.

enumerator kSRC_SetPoint4AssertReset

In setpoint4 will assert slice reset.

enumerator kSRC_SetPoint5AssertReset

In setpoint5 will assert slice reset.

enumerator kSRC_SetPoint6AssertReset

In setpoint6 will assert slice reset.

enumerator kSRC_SetPoint7AssertReset

In setpoint7 will assert slice reset.

enumerator kSRC_SetPoint8AssertReset

In setpoint8 will assert slice reset.

enumerator kSRC_SetPoint9AssertReset

In setpoint9 will assert slice reset.

enumerator kSRC_SetPoint10AssertReset

In setpoint10 will assert slice reset.

enumerator kSRC_SetPoint11AssertReset

In setpoint11 will assert slice reset.

enumerator kSRC_SetPoint12AssertReset

In setpoint12 will assert slice reset.

enumerator kSRC_SetPoint13AssertReset

In setpoint13 will assert slice reset.

enumerator kSRC_SetPoint14AssertReset

In setpoint14 will assert slice reset.

enumerator kSRC_SetPoint15AssertReset

In setpoint15 will assert slice reset.

enum _src_general_purpose_register_index

The index of each general purpose register.

Values:

enumerator kSRC_GeneralPurposeRegister1

The index of General Purpose Register1.

enumerator kSRC_GeneralPurposeRegister2

The index of General Purpose Register2.

enumerator kSRC_GeneralPurposeRegister3

The index of General Purpose Register3.

enumerator kSRC_GeneralPurposeRegister4

The index of General Purpose Register4.

enumerator kSRC_GeneralPurposeRegister5

The index of General Purpose Register5.

enumerator kSRC_GeneralPurposeRegister6

The index of General Purpose Register6.

enumerator kSRC_GeneralPurposeRegister7

The index of General Purpose Register7.

enumerator kSRC_GeneralPurposeRegister8

The index of General Purpose Register8.

enumerator kSRC_GeneralPurposeRegister9

The index of General Purpose Register9.

enumerator kSRC_GeneralPurposeRegister10

The index of General Purpose Register10.

enumerator kSRC_GeneralPurposeRegister11

The index of General Purpose Register11.

enumerator kSRC_GeneralPurposeRegister12

The index of General Purpose Register12.

enumerator kSRC_GeneralPurposeRegister13

The index of General Purpose Register13.

enumerator kSRC_GeneralPurposeRegister14

The index of General Purpose Register14.

enumerator kSRC_GeneralPurposeRegister15

The index of General Purpose Register15.

enumerator kSRC_GeneralPurposeRegister16

The index of General Purpose Register16.

enumerator kSRC_GeneralPurposeRegister17

The index of General Purpose Register17.

enumerator kSRC_GeneralPurposeRegister18

The index of General Purpose Register18.

enumerator kSRC_GeneralPurposeRegister19

The index of General Purpose Register19.

enumerator kSRC_GeneralPurposeRegister20

The index of General Purpose Register20.

enum _src_slice_reset_source

The enumeration of the reset source of each slice.

Values:

enumerator kSRC_SoftwareReset

Reset is caused by software setting.

enumerator kSRC_PowerModeTransferReset

Reset is caused by the power mode transfer.

enum _src_slice_reset_state

The enumeration of the reset state of each slice.

Values:

enumerator kSRC_SliceResetFinished

The reset is finished.

enumerator kSRC_SliceResetInProcess

The reset is in process.

typedef enum _src_core_name src_core_name_t

System core.

typedef enum _src_boot_fuse_selection src_boot_fuse_selection_t

The enumeration of the boot fuse selection.

typedef enum _src_global_system_reset_source src_global_system_reset_source_t

The enumeration of global system reset sources.

typedef enum _src_global_system_reset_mode src_global_system_reset_mode_t

The enumeration of global system reset mode.

typedef enum _src_reset_slice_name src_reset_slice_name_t

The enumeration of the slice name.

typedef enum _src_general_purpose_register_index src_general_purpose_register_index_t

The index of each general purpose register.

typedef struct _src_setpoint_authentication src_setpoint_authentication_t

The structure of setpoint authentication.

typedef struct _src_domain_mode_authentication src_domain_mode_authentication_t

The stucture of domain mode authentication.

typedef enum _src_slice_reset_state src_slice_reset_state_t

The enumeration of the reset state of each slice.

FSL_SRC_DRIVER_VERSION

SRC driver version 2.1.1.

SRC_SLICE_ADDRESS_OFFSET

SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET

SRC_SLICE_CONTROL_REGISTER_OFFSET

SRC_SLICE_SETPOINT_CONFIG_REGISTER_OFFSET

SRC_SLICE_DOMAIN_CONFIG_REGISTER_OFFSET

SRC_SLICE_STATUS_REGISTER_OFFSET

SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, registerOffset)

SRC_SLICE_STAT_UNDER_RST_MASK

SRC_SLICE_STAT_RST_BY_HW_MASK

SRC_SLICE_STAT_RST_BY_SW_MASK

SRC_WHITE_LIST_VALUE(coreName)

SRC_ASSIGN_LIST_VALUE(coreName)

SRC_SLICE_AUTHEN_DOMAIN_MODE_MASK

SRC_SLICE_AUTHEN_SETPOINT_MODE_MASK

SRC_SLICE_AUTHEN_LOCK_MODE_MASK

SRC_SLICE_AUTHEN_LOCK_MODE_SHIFT

SRC_SLICE_AUTHEN_LOCK_MODE(x)

SRC_SLICE_AUTHEN_ASSIGN_LIST_MASK

SRC_SLICE_AUTHEN_ASSIGN_LIST_SHIFT

SRC_SLICE_AUTHEN_ASSIGN_LIST(x)

SRC_SLICE_AUTHEN_LOCK_ASSIGN_MASK

SRC_SLICE_AUTHEN_LOCK_ASSIGN_SHIFT

SRC_SLICE_AUTHEN_LOCK_ASSIGN(x)

SRC_SLICE_AUTHEN_WHITE_LIST_MASK

SRC_SLICE_AUTHEN_WHITE_LIST_SHIFT

SRC_SLICE_AUTHEN_WHITE_LIST(x)

SRC_SLICE_AUTHEN_LOCK_LIST_MASK

SRC_SLICE_AUTHEN_LOCK_LIST_SHIFT

SRC_SLICE_AUTHEN_LOCK_LIST(x)

SRC_SLICE_AUTHEN_USER_MASK

SRC_SLICE_AUTHEN_USER_SHIFT

SRC_SLICE_AUTHEN_USER(x)

SRC_SLICE_AUTHEN_NONSECURE_MASK

SRC_SLICE_AUTHEN_NONSECURE_SHIFT

SRC_SLICE_AUTHEN_NONSECURE(x)

SRC_SLICE_AUTHEN_LOCK_SETTING_MASK

SRC_SLICE_AUTHEN_LOCK_SETTING_SHIFT

SRC_SLICE_AUTHEN_LOCK_SETTING(x)

void SRC_ReleaseCoreReset(SRC_Type *base, src_core_name_t coreName)

Releases related core reset operation.

The core reset will be held until the boot core to release it.

Parameters:

• base – SRC peripheral base address.

• coreName – The name of the reset core to be released.

static inline uint32_t SRC_GetBootConfig(SRC_Type *base)

Gets Boot configuration.

Parameters:

• base – SRC peripheral base address.

Returns:

Boot configuration. Please refer to fusemap.

static inline uint8_t SRC_GetBootMode(SRC_Type *base)

Gets the latched state of the BOOT_MODE1 and BOOT_MODE0 signals.

Parameters:

• base – SRC peripheral base address.

Returns:

Boot mode. Please refer to the Boot mode pin setting section of System Boot.

static inline src_boot_fuse_selection_t SRC_GetBootFuseSelection(SRC_Type *base)

Gets the state of the BT_FUSE_SEL fuse.

Parameters:

• base – SRC peripheral base address.

Returns:

The state of the BT_FUSE_SEL fuse, please refer to fusemap for more information.

static inline uint8_t SRC_GetSECConfigFuseState(SRC_Type *base)

Gets the state of the SECCONFIG[1] fuse.

Parameters:

• base – SRC peripheral base address.

Returns:

The state of the SECCONFIG[1] fuse. Please refer to fusemap for more information.

void SRC_SetGlobalSystemResetMode(SRC_Type *base, src_global_system_reset_source_t resetSource, src_global_system_reset_mode_t resetMode)

Sets the reset mode of global system reset source.

This function sets the selected mode of the input global system reset sources.

Parameters:

• base – SRC peripheral base address.

• resetSource – The global system reset source. See src_global_system_reset_source_t for more details.

• resetMode – The reset mode of each reset source. See src_global_system_reset_mode_t for more details.

static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base)

Gets global system reset status flags.

Parameters:

• base – SRC peripheral base address.

Returns:

The status of global system reset status. See _src_global_system_reset_status_flags for more details.

static inline void SRC_ClearGlobalSystemResetStatus(SRC_Type *base, uint32_t mask)

Clears the status of global reset.

Parameters:

• base – SRC peripheral base address.

• mask – The reset status flag to be cleared. See _src_global_system_reset_status_flags for more details.

void SRC_AssertSliceSoftwareReset(SRC_Type *base, src_reset_slice_name_t sliceName)

Asserts software reset for the selected slice.

Note

This function will return as soon as the resset is finished.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice to be reset. See src_reset_slice_name_t for more details.

static inline void SRC_AllowUserModeAccess(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable)

Allows/disallows user mode access.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• enable – Used to control user mode access.

  • true Allow user mode access.

  • false Disallow user mode access.

static inline void SRC_AllowNonSecureModeAccess(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable)

Allows/disallows non secure mode access.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• enable – Used to control non secure mode access.

  • true Allow non secure mode access.

  • false Disallow non secure mode access.

static inline void SRC_LockAccessSetting(SRC_Type *base, src_reset_slice_name_t sliceName)

Locks the setting of user mode access and non secure mode access.

Note

Once locked only reset can unlock related settings.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

static inline void SRC_SetDomainIdWhiteList(SRC_Type *base, src_reset_slice_name_t sliceName, uint8_t domainId)

Sets the domain ID white list for the selected slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• domainId – The core to access registers, should be the OR’ed value of src_core_name_t.

static inline void SRC_LockDomainIdWhiteList(SRC_Type *base, src_reset_slice_name_t sliceName)

Locks the value of white list.

Note

Once locked only reset can unlock related settings.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

static inline void SRC_SetAssignList(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t assignList)

Sets the value of assign list.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• assignList – Cores that subject to corresponding core status transition, should be the OR’ed value of src_core_name_t.

static inline void SRC_LockAssignList(SRC_Type *base, src_reset_slice_name_t sliceName)

Locks the value of assign list.

Note

Once locked only reset can unlock related settings.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

static inline void SRC_EnableSetPointTransferReset(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable)

Enable/disable setpoint transfer reset.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• enable – User to control setpoint transfer reset.

  • true Enable setpoint transfer reset.

  • false Disable setpoint transfer reset.

static inline void SRC_EnableDomainModeTransferReset(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable)

Enable/disable domain mode transfer reset.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice name to set, please refer to src_reset_slice_name_t for details.

• enable – User to control domain mode reset.

  • true Enable domain mode reset.

  • false Disable domain mode reset.

void SRC_SetSliceSetPointConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t setpointConfig)

Sets setpoint configuration for the selected reset slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The selected reset slice. See src_reset_slice_name_t for more details.

• setpointConfig – The logic OR’ed value of _src_setpoint_selection enumeration, when the system in the selected setpoint slice reset will be asserted.

void SRC_SetSliceDomainModeConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t domainConfig)

Sets domain mode configuration for the selected reset slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The selected reset slice. See src_reset_slice_name_t for more details.

• domainConfig – The logic OR’ed value of _src_domain_mode_selection enumerations.

void SRC_LockSliceMode(SRC_Type *base, src_reset_slice_name_t sliceName)

Locks the value of SETPOINT_MODE and DOMAIN_MODE for the selected reset slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The selected reset slice. See src_reset_slice_name_t for more details.

static inline uint32_t SRC_GetSliceResetStatusFlags(SRC_Type *base, src_reset_slice_name_t sliceName)

Gets the reset status flags of the selected slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The slice to be reset. See src_reset_slice_name_t for more details.

Returns:

The reset status flags for the selected slice. Please refer to _src_slice_reset_source for details.

static inline void SRC_ClearSliceResetStatusFlags(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t mask)

Clears the reset status flags of the selected slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The selected slice. See src_reset_slice_name_t for more details.

• mask – The reset status flags to be cleared. Please refer to _src_slice_reset_source for more details.

src_slice_reset_state_t SRC_GetSliceResetState(SRC_Type *base, src_reset_slice_name_t sliceName)

Gets the reset state of the selected slice.

Parameters:

• base – SRC peripheral base address.

• sliceName – The selected slice. See src_reset_slice_name_t for more details.

Return values:

• kSRC_SliceResetInProcess – The reset is in process.

• kSRC_SliceResetFinished – The reset is finished.

static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, src_general_purpose_register_index_t index, uint32_t value)

Sets value to general purpose registers.

Parameters:

• base – SRC peripheral base address.

• index – The index of GPRx register array. Please refer to src_general_purpose_register_index_t.

• value – Setting value for GPRx register.

static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, src_general_purpose_register_index_t index)

Gets the value from general purpose registers.

Parameters:

• base – SRC peripheral base address.

• index – The index of GPRx register array. Please refer to src_general_purpose_register_index_t.

Returns:

The setting value for GPRx register.

struct _src_setpoint_authentication

#include <fsl_soc_src.h>

The structure of setpoint authentication.

Public Members

bool enableSetpointTranferReset

Control whether reset slice is in setpoint mode.

• true Slice hardware reset will be triggered by set point transition.

• false Slice hardware reset will not be trigged by set point transition.

uint32_t whiteList

Select the core to access set point control register. The logic OR’ed value of src_core_name_t enumeration.

bool lockWhiteList

Control whether lock the value in white list

bool lockSetting

Control whether lock the setpoint access setting.

bool allowNonSecureModeAccess

Allow both secure and non-secure modes to config setpoint.

bool allowUserModeAccess

Allow both privilege and user modes to config setpoint.

struct _src_domain_mode_authentication

#include <fsl_soc_src.h>

The stucture of domain mode authentication.

Public Members

bool enableDomainModeTransferReset

Control whether reset slice is in domaim mode.

• true Slice hardware reset will be triggered by cpu power mode transition.

• false Slice hardware reset will not be trigged by cpu power mode transition.

uint32_t assignList

Select the core that reset of slice would be subject to the selected core status transition. The logic OR’ed value of src_core_name_t enumeration.

bool lockAssignList

Control whether lock the value in Assign list.

SPDIF: Sony/Philips Digital Interface

void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config)

Initializes the SPDIF peripheral.

Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. The configuration structure can be custom filled or set with default values by SPDIF_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault because the clock is not enabled.

Parameters:

• base – SPDIF base pointer

• config – SPDIF configuration structure.

void SPDIF_GetDefaultConfig(spdif_config_t *config)

Sets the SPDIF configuration structure to default values.

This API initializes the configuration structure for use in SPDIF_Init. The initialized structure can remain unchanged in SPDIF_Init, or it can be modified before calling SPDIF_Init. This is an example.

spdif_config_t config;
SPDIF_GetDefaultConfig(&config);

Parameters:

• config – pointer to master configuration structure

void SPDIF_Deinit(SPDIF_Type *base)

De-initializes the SPDIF peripheral.

This API gates the SPDIF clock. The SPDIF module can’t operate unless SPDIF_Init is called to enable the clock.

Parameters:

• base – SPDIF base pointer

uint32_t SPDIF_GetInstance(SPDIF_Type *base)

Get the instance number for SPDIF.

Parameters:

• base – SPDIF base pointer.

static inline void SPDIF_TxFIFOReset(SPDIF_Type *base)

Resets the SPDIF Tx.

This function makes Tx FIFO in reset mode.

Parameters:

• base – SPDIF base pointer

static inline void SPDIF_RxFIFOReset(SPDIF_Type *base)

Resets the SPDIF Rx.

This function enables the software reset and FIFO reset of SPDIF Rx. After reset, clear the reset bit.

Parameters:

• base – SPDIF base pointer

void SPDIF_TxEnable(SPDIF_Type *base, bool enable)

Enables/disables the SPDIF Tx.

Parameters:

• base – SPDIF base pointer

• enable – True means enable SPDIF Tx, false means disable.

static inline void SPDIF_RxEnable(SPDIF_Type *base, bool enable)

Enables/disables the SPDIF Rx.

Parameters:

• base – SPDIF base pointer

• enable – True means enable SPDIF Rx, false means disable.

static inline uint32_t SPDIF_GetStatusFlag(SPDIF_Type *base)

Gets the SPDIF status flag state.

Parameters:

• base – SPDIF base pointer

Returns:

SPDIF status flag value. Use the _spdif_interrupt_enable_t to get the status value needed.

static inline void SPDIF_ClearStatusFlags(SPDIF_Type *base, uint32_t mask)

Clears the SPDIF status flag state.

Parameters:

• base – SPDIF base pointer

• mask – State mask. It can be a combination of the _spdif_interrupt_enable_t member. Notice these members cannot be included, as these flags cannot be cleared by writing 1 to these bits:

  • kSPDIF_UChannelReceiveRegisterFull

  • kSPDIF_QChannelReceiveRegisterFull

  • kSPDIF_TxFIFOEmpty

  • kSPDIF_RxFIFOFull

static inline void SPDIF_EnableInterrupts(SPDIF_Type *base, uint32_t mask)

Enables the SPDIF Tx interrupt requests.

Parameters:

• base – SPDIF base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSPDIF_WordStartInterruptEnable

  • kSPDIF_SyncErrorInterruptEnable

  • kSPDIF_FIFOWarningInterruptEnable

  • kSPDIF_FIFORequestInterruptEnable

  • kSPDIF_FIFOErrorInterruptEnable

static inline void SPDIF_DisableInterrupts(SPDIF_Type *base, uint32_t mask)

Disables the SPDIF Tx interrupt requests.

Parameters:

• base – SPDIF base pointer

• mask – interrupt source The parameter can be a combination of the following sources if defined.

  • kSPDIF_WordStartInterruptEnable

  • kSPDIF_SyncErrorInterruptEnable

  • kSPDIF_FIFOWarningInterruptEnable

  • kSPDIF_FIFORequestInterruptEnable

  • kSPDIF_FIFOErrorInterruptEnable

static inline void SPDIF_EnableDMA(SPDIF_Type *base, uint32_t mask, bool enable)

Enables/disables the SPDIF DMA requests.

Parameters:

• base – SPDIF base pointer

• mask – SPDIF DMA enable mask, The parameter can be a combination of the following sources if defined

  • kSPDIF_RxDMAEnable

  • kSPDIF_TxDMAEnable

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t SPDIF_TxGetLeftDataRegisterAddress(SPDIF_Type *base)

Gets the SPDIF Tx left data register address.

This API is used to provide a transfer address for the SPDIF DMA transfer configuration.

Parameters:

• base – SPDIF base pointer.

Returns:

data register address.

static inline uint32_t SPDIF_TxGetRightDataRegisterAddress(SPDIF_Type *base)

Gets the SPDIF Tx right data register address.

This API is used to provide a transfer address for the SPDIF DMA transfer configuration.

Parameters:

• base – SPDIF base pointer.

Returns:

data register address.

static inline uint32_t SPDIF_RxGetLeftDataRegisterAddress(SPDIF_Type *base)

Gets the SPDIF Rx left data register address.

This API is used to provide a transfer address for the SPDIF DMA transfer configuration.

Parameters:

• base – SPDIF base pointer.

Returns:

data register address.

static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base)

Gets the SPDIF Rx right data register address.

This API is used to provide a transfer address for the SPDIF DMA transfer configuration.

Parameters:

• base – SPDIF base pointer.

Returns:

data register address.

void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz)

Configures the SPDIF Tx sample rate.

The audio format can be changed at run-time. This function configures the sample rate.

Parameters:

• base – SPDIF base pointer.

• sampleRate_Hz – SPDIF sample rate frequency in Hz.

• sourceClockFreq_Hz – SPDIF tx clock source frequency in Hz.

uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz)

Configures the SPDIF Rx audio format.

The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – SPDIF base pointer.

• clockSourceFreq_Hz – SPDIF system clock frequency in hz.

void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)

Sends data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SPDIF base pointer.

• buffer – Pointer to the data to be written.

• size – Bytes to be written.

static inline void SPDIF_WriteLeftData(SPDIF_Type *base, uint32_t data)

Writes data into SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

• data – Data needs to be written.

static inline void SPDIF_WriteRightData(SPDIF_Type *base, uint32_t data)

Writes data into SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

• data – Data needs to be written.

static inline void SPDIF_WriteChannelStatusHigh(SPDIF_Type *base, uint32_t data)

Writes data into SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

• data – Data needs to be written.

static inline void SPDIF_WriteChannelStatusLow(SPDIF_Type *base, uint32_t data)

Writes data into SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

• data – Data needs to be written.

void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)

Receives data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

• base – SPDIF base pointer.

• buffer – Pointer to the data to be read.

• size – Bytes to be read.

static inline uint32_t SPDIF_ReadLeftData(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

static inline uint32_t SPDIF_ReadRightData(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

static inline uint32_t SPDIF_ReadChannelStatusHigh(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

static inline uint32_t SPDIF_ReadChannelStatusLow(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

static inline uint32_t SPDIF_ReadQChannel(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

static inline uint32_t SPDIF_ReadUChannel(SPDIF_Type *base)

Reads data from the SPDIF FIFO.

Parameters:

• base – SPDIF base pointer.

Returns:

Data in SPDIF FIFO.

void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, void *userData)

Initializes the SPDIF Tx handle.

This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – SPDIF base pointer

• handle – SPDIF handle pointer.

• callback – Pointer to the user callback function.

• userData – User parameter passed to the callback function

void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, void *userData)

Initializes the SPDIF Rx handle.

This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF handle pointer.

• callback – Pointer to the user callback function.

• userData – User parameter passed to the callback function.

status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on SPDIF.

Note

This API returns immediately after the transfer initiates. Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer is finished.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

• xfer – Pointer to the spdif_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_SPDIF_TxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on SPDIF.

Note

This API returns immediately after the transfer initiates. Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer is finished.

Parameters:

• base – SPDIF base pointer

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

• xfer – Pointer to the spdif_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_SPDIF_RxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)

Gets a set byte count.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

• count – Bytes count sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)

Gets a received byte count.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

• count – Bytes count received.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle)

Aborts the current send.

Note

This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle)

Aborts the current IRQ receive.

Note

This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – SPDIF base pointer

• handle – Pointer to the spdif_handle_t structure which stores the transfer state.

void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)

Tx interrupt handler.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure.

void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)

Tx interrupt handler.

Parameters:

• base – SPDIF base pointer.

• handle – Pointer to the spdif_handle_t structure.

FSL_SPDIF_DRIVER_VERSION

Version 2.0.7

SPDIF return status.

Values:

enumerator kStatus_SPDIF_RxDPLLLocked

SPDIF Rx PLL locked.

enumerator kStatus_SPDIF_TxFIFOError

SPDIF Tx FIFO error.

enumerator kStatus_SPDIF_TxFIFOResync

SPDIF Tx left and right FIFO resync.

enumerator kStatus_SPDIF_RxCnew

SPDIF Rx status channel value updated.

enumerator kStatus_SPDIF_ValidatyNoGood

SPDIF validaty flag not good.

enumerator kStatus_SPDIF_RxIllegalSymbol

SPDIF Rx receive illegal symbol.

enumerator kStatus_SPDIF_RxParityBitError

SPDIF Rx parity bit error.

enumerator kStatus_SPDIF_UChannelOverrun

SPDIF receive U channel overrun.

enumerator kStatus_SPDIF_QChannelOverrun

SPDIF receive Q channel overrun.

enumerator kStatus_SPDIF_UQChannelSync

SPDIF U/Q channel sync found.

enumerator kStatus_SPDIF_UQChannelFrameError

SPDIF U/Q channel frame error.

enumerator kStatus_SPDIF_RxFIFOError

SPDIF Rx FIFO error.

enumerator kStatus_SPDIF_RxFIFOResync

SPDIF Rx left and right FIFO resync.

enumerator kStatus_SPDIF_LockLoss

SPDIF Rx PLL clock lock loss.

enumerator kStatus_SPDIF_TxIdle

SPDIF Tx is idle

enumerator kStatus_SPDIF_RxIdle

SPDIF Rx is idle

enumerator kStatus_SPDIF_QueueFull

SPDIF queue full

enum _spdif_rxfull_select

SPDIF Rx FIFO full falg select, it decides when assert the rx full flag.

Values:

enumerator kSPDIF_RxFull1Sample

Rx full at least 1 sample in left and right FIFO

enumerator kSPDIF_RxFull4Samples

Rx full at least 4 sample in left and right FIFO

enumerator kSPDIF_RxFull8Samples

Rx full at least 8 sample in left and right FIFO

enumerator kSPDIF_RxFull16Samples

Rx full at least 16 sample in left and right FIFO

enum _spdif_txempty_select

SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag.

Values:

enumerator kSPDIF_TxEmpty0Sample

Tx empty at most 0 sample in left and right FIFO

enumerator kSPDIF_TxEmpty4Samples

Tx empty at most 4 sample in left and right FIFO

enumerator kSPDIF_TxEmpty8Samples

Tx empty at most 8 sample in left and right FIFO

enumerator kSPDIF_TxEmpty12Samples

Tx empty at most 12 sample in left and right FIFO

enum _spdif_uchannel_source

SPDIF U channel source.

Values:

enumerator kSPDIF_NoUChannel

No embedded U channel

enumerator kSPDIF_UChannelFromRx

U channel from receiver, it is CD mode

enumerator kSPDIF_UChannelFromTx

U channel from on chip tx

enum _spdif_gain_select

SPDIF clock gain.

Values:

enumerator kSPDIF_GAIN_24

Gain select is 24

enumerator kSPDIF_GAIN_16

Gain select is 16

enumerator kSPDIF_GAIN_12

Gain select is 12

enumerator kSPDIF_GAIN_8

Gain select is 8

enumerator kSPDIF_GAIN_6

Gain select is 6

enumerator kSPDIF_GAIN_4

Gain select is 4

enumerator kSPDIF_GAIN_3

Gain select is 3

enum _spdif_tx_source

SPDIF tx data source.

Values:

enumerator kSPDIF_txFromReceiver

Tx data directly through SPDIF receiver

enumerator kSPDIF_txNormal

Normal operation, data from processor

enum _spdif_validity_config

SPDIF tx data source.

Values:

enumerator kSPDIF_validityFlagAlwaysSet

Outgoing validity flags always set

enumerator kSPDIF_validityFlagAlwaysClear

Outgoing validity flags always clear

The SPDIF interrupt enable flag.

Values:

enumerator kSPDIF_RxDPLLLocked

SPDIF DPLL locked

enumerator kSPDIF_TxFIFOError

Tx FIFO underrun or overrun

enumerator kSPDIF_TxFIFOResync

Tx FIFO left and right channel resync

enumerator kSPDIF_RxControlChannelChange

SPDIF Rx control channel value changed

enumerator kSPDIF_ValidityFlagNoGood

SPDIF validity flag no good

enumerator kSPDIF_RxIllegalSymbol

SPDIF receiver found illegal symbol

enumerator kSPDIF_RxParityBitError

SPDIF receiver found parity bit error

enumerator kSPDIF_UChannelReceiveRegisterFull

SPDIF U channel revceive register full

enumerator kSPDIF_UChannelReceiveRegisterOverrun

SPDIF U channel receive register overrun

enumerator kSPDIF_QChannelReceiveRegisterFull

SPDIF Q channel receive reigster full

enumerator kSPDIF_QChannelReceiveRegisterOverrun

SPDIF Q channel receive register overrun

enumerator kSPDIF_UQChannelSync

SPDIF U/Q channel sync found

enumerator kSPDIF_UQChannelFrameError

SPDIF U/Q channel frame error

enumerator kSPDIF_RxFIFOError

SPDIF Rx FIFO underrun/overrun

enumerator kSPDIF_RxFIFOResync

SPDIF Rx left and right FIFO resync

enumerator kSPDIF_LockLoss

SPDIF receiver loss of lock

enumerator kSPDIF_TxFIFOEmpty

SPDIF Tx FIFO empty

enumerator kSPDIF_RxFIFOFull

SPDIF Rx FIFO full

enumerator kSPDIF_AllInterrupt

all interrupt

The DMA request sources.

Values:

enumerator kSPDIF_RxDMAEnable

Rx FIFO full

enumerator kSPDIF_TxDMAEnable

Tx FIFO empty

typedef enum _spdif_rxfull_select spdif_rxfull_select_t

SPDIF Rx FIFO full falg select, it decides when assert the rx full flag.

typedef enum _spdif_txempty_select spdif_txempty_select_t

SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag.

typedef enum _spdif_uchannel_source spdif_uchannel_source_t

SPDIF U channel source.

typedef enum _spdif_gain_select spdif_gain_select_t

SPDIF clock gain.

typedef enum _spdif_tx_source spdif_tx_source_t

SPDIF tx data source.

typedef enum _spdif_validity_config spdif_validity_config_t

SPDIF tx data source.

typedef struct _spdif_config spdif_config_t

SPDIF user configuration structure.

typedef struct _spdif_transfer spdif_transfer_t

SPDIF transfer structure.

typedef struct _spdif_handle spdif_handle_t

typedef void (*spdif_transfer_callback_t)(SPDIF_Type *base, spdif_handle_t *handle, status_t status, void *userData)

SPDIF transfer callback prototype.

SPDIF_XFER_QUEUE_SIZE

SPDIF transfer queue size, user can refine it according to use case.

struct _spdif_config

#include <fsl_spdif.h>

SPDIF user configuration structure.

Public Members

bool isTxAutoSync

If auto sync mechanism open

bool isRxAutoSync

If auto sync mechanism open

uint8_t DPLLClkSource

SPDIF DPLL clock source, range from 0~15, meaning is chip-specific

uint8_t txClkSource

SPDIF tx clock source, range from 0~7, meaning is chip-specific

spdif_rxfull_select_t rxFullSelect

SPDIF rx buffer full select

spdif_txempty_select_t txFullSelect

SPDIF tx buffer empty select

spdif_uchannel_source_t uChannelSrc

U channel source

spdif_tx_source_t txSource

SPDIF tx data source

spdif_validity_config_t validityConfig

Validity flag config

spdif_gain_select_t gain

Rx receive clock measure gain parameter.

struct _spdif_transfer

#include <fsl_spdif.h>

SPDIF transfer structure.

Public Members

uint8_t *data

Data start address to transfer.

uint8_t *qdata

Data buffer for Q channel

uint8_t *udata

Data buffer for C channel

size_t dataSize

Transfer size.

struct _spdif_handle

#include <fsl_spdif.h>

SPDIF handle structure.

Public Members

uint32_t state

Transfer status

spdif_transfer_callback_t callback

Callback function called at transfer event

void *userData

Callback parameter passed to callback function

spdif_transfer_t spdifQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint8_t watermark

Watermark value

SPDIF eDMA Driver

void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, void *userData, edma_handle_t *dmaLeftHandle, edma_handle_t *dmaRightHandle)

Initializes the SPDIF eDMA handle.

This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. Usually, for a specified SPDIF instance, call this API once to get the initialized handle.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF eDMA handle pointer.

• callback – Pointer to user callback function.

• userData – User parameter passed to the callback function.

• dmaLeftHandle – eDMA handle pointer for left channel, this handle shall be static allocated by users.

• dmaRightHandle – eDMA handle pointer for right channel, this handle shall be static allocated by users.

void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, void *userData, edma_handle_t *dmaLeftHandle, edma_handle_t *dmaRightHandle)

Initializes the SPDIF Rx eDMA handle.

This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. Usually, for a specified SPDIF instance, call this API once to get the initialized handle.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF eDMA handle pointer.

• callback – Pointer to user callback function.

• userData – User parameter passed to the callback function.

• dmaLeftHandle – eDMA handle pointer for left channel, this handle shall be static allocated by users.

• dmaRightHandle – eDMA handle pointer for right channel, this handle shall be static allocated by users.

status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)

Performs a non-blocking SPDIF transfer using DMA.

Note

This interface returns immediately after the transfer initiates. Call SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure.

Return values:

• kStatus_Success – Start a SPDIF eDMA send successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_TxBusy – SPDIF is busy sending data.

status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)

Performs a non-blocking SPDIF receive using eDMA.

Note

This interface returns immediately after the transfer initiates. Call the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished.

Parameters:

• base – SPDIF base pointer

• handle – SPDIF eDMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a SPDIF eDMA receive successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_RxBusy – SPDIF is busy receiving data.

void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)

Aborts a SPDIF transfer using eDMA.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF eDMA handle pointer.

void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)

Aborts a SPDIF receive using eDMA.

Parameters:

• base – SPDIF base pointer

• handle – SPDIF eDMA handle pointer.

status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)

Gets byte count sent by SPDIF.

Parameters:

• base – SPDIF base pointer.

• handle – SPDIF eDMA handle pointer.

• count – Bytes count sent by SPDIF.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.

status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)

Gets byte count received by SPDIF.

Parameters:

• base – SPDIF base pointer

• handle – SPDIF eDMA handle pointer.

• count – Bytes count received by SPDIF.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.

FSL_SPDIF_EDMA_DRIVER_VERSION

Version 2.0.8

typedef struct _spdif_edma_handle spdif_edma_handle_t

typedef void (*spdif_edma_callback_t)(SPDIF_Type *base, spdif_edma_handle_t *handle, status_t status, void *userData)

SPDIF eDMA transfer callback function for finish and error.

typedef struct _spdif_edma_transfer spdif_edma_transfer_t

SPDIF transfer structure.

struct _spdif_edma_transfer

#include <fsl_spdif_edma.h>

SPDIF transfer structure.

Public Members

uint8_t *leftData

Data start address to transfer.

uint8_t *rightData

Data start address to transfer.

size_t dataSize

Transfer size.

struct _spdif_edma_handle

#include <fsl_spdif_edma.h>

SPDIF DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaLeftHandle

DMA handler for SPDIF left channel

edma_handle_t *dmaRightHandle

DMA handler for SPDIF right channel

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint8_t count

The transfer data count in a DMA request

uint32_t state

Internal state for SPDIF eDMA transfer

spdif_edma_callback_t callback

Callback for users while transfer finish or error occurs

void *userData

User callback parameter

edma_tcd_t leftTcd[(4U) + 1U]

TCD pool for eDMA transfer.

edma_tcd_t rightTcd[(4U) + 1U]

TCD pool for eDMA transfer.

spdif_edma_transfer_t spdifQueue[(4U)]

Transfer queue storing queued transfer.

size_t transferSize[(4U)]

Data bytes need to transfer, left and right are the same, so use one

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

SSARC: State Save and Restore Controller

static inline uint32_t SSARC_GetDescriptorRegisterAddress(SSARC_HP_Type *base, uint32_t index)

Gets the address of the register to be saved/restored.

Parameters:

• base – SSARC_HP peripheral base address.

• index – The index of descriptor. Range from 0 to 1023.

Returns:

The address of the register.

static inline uint32_t SSARC_GetDescriptorRegisterData(SSARC_HP_Type *base, uint32_t index)

Gets the value of the register to be saved/restored.

Parameters:

• base – SSARC_HP peripheral base address.

• index – The index of descriptor. Range from 0 to 1023.

Returns:

The value of the register.

void SSARC_SetDescriptorConfig(SSARC_HP_Type *base, uint32_t index, const ssarc_descriptor_config_t *config)

Sets the configuration of the descriptor.

Parameters:

• base – SSARC_HP peripheral base address.

• index – The index of descriptor. Range from 0 to 1023.

• config – Pointer to the structure ssarc_descriptor_config_t. Please refer to ssarc_descriptor_config_t for details.

void SSARC_GroupInit(SSARC_LP_Type *base, uint8_t groupID, const ssarc_group_config_t *config)

Inits the selected group.

Note

For the groups with the same save priority or restore priority, the save/restore operation runs in the group order.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

• config – Pointer to the structure ssarc_group_config_t. Please refer to ssarc_group_config_t for details.

static inline void SSARC_GroupDeinit(SSARC_LP_Type *base, uint8_t groupID)

De-inits the selected group.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

static inline void SSARC_LockGroupDomain(SSARC_LP_Type *base, uint8_t groupID)

Locks the configuration of the domain.

This function locks the configuration of the domain. Once locked, only the access from the same domain is allowed, access from other domains will be blocked. Once locked, it can only be unlocked by a hardware reset.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

static inline void SSARC_LockGroupWrite(SSARC_LP_Type *base, uint8_t groupID)

Locks the write access to the control registers and descriptors for the selected group.

This function Locks the write access to the control registers and descriptors for the selected group. All writes are blocked. Once locked, it can only be unlocked by a hardware reset.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

static inline void SSARC_LockGroupRead(SSARC_LP_Type *base, uint8_t groupID)

Locks the read access to the control registers and descriptors for the selected group.

This function Locks the read access to the control registers and descriptors for the selected group. All reads are blocked. Once locked, it can only be unlocked by a hardware reset.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

void SSARC_TriggerSoftwareRequest(SSARC_LP_Type *base, uint8_t groupID, ssarc_software_trigger_mode_t mode)

Triggers software request.

Note

Each group allows software to trigger the save/restore operation without getting the request from basic power controller.

Parameters:

• base – SSARC_LP peripheral base address.

• groupID – The index of the group. Range from 0 to 15.

• mode – Software trigger mode. Please refer to ssarc_software_trigger_mode_t for details.

static inline void SSARC_ResetWholeBlock(SSARC_LP_Type *base)

Resets the whole SSARC block by software.

Note

Only reset the SSARC registers, not include the DESC in SRAM.

Parameters:

• base – SSARC_LP peripheral base address.

static inline void SSARC_EnableHardwareRequest(SSARC_LP_Type *base, bool enable)

Enables/Disables save/restore request from the PGMC module.

Parameters:

• base – SSARC_LP peripheral base address.

• enable – Used to enable/disable save/restore hardware request.

  • true Enable GPC save/restore requests.

  • false Disable GPC save/restore requests.

static inline uint32_t SSARC_GetStatusFlags(SSARC_LP_Type *base)

Gets status flags.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The value of status flags. See _ssarc_interrupt_status_flags for details.

static inline void SSARC_ClearStatusFlags(SSARC_LP_Type *base, uint32_t mask)

Clears status flags.

Note

Only kSSARC_AddressErrorFlag, kSSARC_AHBErrorFlag, kSSARC_TimeoutFlag and kSSARC_GroupConflictFlag can be cleared.

Parameters:

• base – SSARC_LP peripheral base address.

• mask – The mask value for flags to be cleared. See _ssarc_interrupt_status_flags for details.

static inline uint32_t SSARC_GetErrorIndex(SSARC_LP_Type *base)

Gets the error index that indicates which descriptor will trigger the AHB_ERR or ADDR_ERR interrupt.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The error index.

static inline void SSARC_SetTimeoutValue(SSARC_LP_Type *base, uint32_t value)

Sets timeout value for the entire group to complete.

This function sets timeout value for the entire group to complete. Setting timeout value to 0 will disable this feature.

Parameters:

• base – SSARC_LP peripheral base address.

• value – The timeout value, 0 means disable time out feature.

static inline uint32_t SSARC_GetTimeoutValue(SSARC_LP_Type *base)

Gets timeout value for AHB clock.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The timeout value.

static inline uint16_t SSARC_GetHardwareRequestRestorePendingGroup(SSARC_LP_Type *base)

Gets the value that indicates which groups are pending for restore from hardware request.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The value of the pending groups.

static inline uint16_t SSARC_GetHardwareRequestSavePendingGroup(SSARC_LP_Type *base)

Gets the value that indicates which groups are pending for save from hardware request.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The value of the pending groups.

static inline uint16_t SSARC_GetSoftwareRequestRestorePendingGroup(SSARC_LP_Type *base)

Gets the value that indicates which groups are pending for restore from software request.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The value of the pending groups.

static inline uint16_t SSARC_GetSoftwareRequestSavePendingGroup(SSARC_LP_Type *base)

Gets the value that indicates which groups are pending for save from software request.

Parameters:

• base – SSARC_LP peripheral base address.

Returns:

The value of the pending groups.

FSL_SSARC_DRIVER_VERSION

SSARC driver version 2.1.0.

enum _ssarc_interrupt_status_flags

The enumeration of ssarc status flags.

Values:

enumerator kSSARC_AddressErrorFlag

If the descriptor is not in the range, assert address error.

enumerator kSSARC_AHBErrorFlag

If any AHB master access receives none-OKAY, assert AHB error.

enumerator kSSARC_SoftwareRequestDoneFlag

If a software triggered save or restore process is completed, assert sofware request done .

enumerator kSSARC_TimeoutFlag

If processing of a group has exceeded the timeout value, assert timeout.

enumerator kSSARC_GroupConflictFlag

Group conflict.

enum _ssarc_descriptor_register_size

The size of the register to be saved/restored.

Values:

enumerator kSSARC_DescriptorRegister8bitWidth

The register to be saved/restored is 8 bit width.

enumerator kSSARC_DescriptorRegister16bitWidth

The register to be saved/restored is 16 bit width.

enumerator kSSARC_DescriptorRegister32bitWidth

The register to be saved/restored is 32 bit width.

enum _ssarc_descriptor_operation

The operation of the descriptor.

Values:

enumerator kSSARC_SaveDisableRestoreDisable

Disable Save operation, disable restore operation.

enumerator kSSARC_SaveEnableRestoreDisable

Enable Save operation, disable restore operation.

enumerator kSSARC_SaveDisableRestoreEnable

Disable Save operation, enable restore operation.

enumerator kSSARC_SaveEnableRestoreEnable

Enable Save operation, enable restore operation.

enum _ssarc_descriptor_type

The type of operation.

Values:

enumerator kSSARC_ReadValueWriteBack

Read the register value on save operation and write it back on restore operation

enumerator kSSARC_WriteFixedValue

Always write a fixed value from DATA[31:0]

enumerator kSSARC_RMWOr

Read register, OR with the DATA[31:0], and write it back

enumerator kSSARC_RMWAnd

Read register, AND with the DATA[31:0], and write it back

enumerator kSSARC_DelayCycles

Delay for number of cycles based on the DATA[31:0]

enumerator kSSARC_Polling0

Read the register until read_data[31:0] & DATA[31:0] == 0

enumerator kSSARC_Polling1

Read the register until read_data[31:0] & DATA[31:0] != 0

enum _ssarc_save_restore_order

The order of the restore/save operation.

Values:

enumerator kSSARC_ProcessFromStartToEnd

Descriptors within the group are processed from start to end.

enumerator kSSARC_ProcessFromEndToStart

Descriptors within the group are processed from end to start.

enum _ssarc_software_trigger_mode

Software trigger mode.

Values:

enumerator kSSARC_TriggerSaveRequest

Don’t trigger restore operation, trigger the save operation by software.

enumerator kSSARC_TriggerRestoreRequest

Trigger the restore operation, don’t trigger the save operation.

typedef enum _ssarc_descriptor_register_size ssarc_descriptor_register_size_t

The size of the register to be saved/restored.

typedef enum _ssarc_descriptor_operation ssarc_descriptor_operation_t

The operation of the descriptor.

typedef enum _ssarc_descriptor_type ssarc_descriptor_type_t

The type of operation.

typedef enum _ssarc_save_restore_order ssarc_save_restore_order_t

The order of the restore/save operation.

typedef enum _ssarc_software_trigger_mode ssarc_software_trigger_mode_t

Software trigger mode.

typedef struct _ssarc_descriptor_config ssarc_descriptor_config_t

The configuration of descriptor.

typedef struct _ssarc_group_config ssarc_group_config_t

The configuration of the group.

SSARC_INT_STATUS_ALL

struct _ssarc_descriptor_config

#include <fsl_ssarc.h>

The configuration of descriptor.

Public Members

uint32_t address

The address of the register/memory to be saved/restored.

uint32_t data

The value of the register/memory to be saved/restored, please note that if the type is selected as kSSARC_ReadValueWriteBack, this data field is useless.

ssarc_descriptor_register_size_t size

The size of register to be saved/restored.

ssarc_descriptor_operation_t operation

The operation mode of descriptor.

ssarc_descriptor_type_t type

The type of operation.

struct _ssarc_group_config

#include <fsl_ssarc.h>

The configuration of the group.

Public Members

ssarc_cpu_domain_name_t cpuDomain

CPU domain, define the ownership of this group.

uint32_t startIndex

The index of the first descriptor of the group.

uint32_t endIndex

The index of the last descriptor of the group.

ssarc_save_restore_order_t restoreOrder

The restore order.

ssarc_save_restore_order_t saveOrder

The save order.

uint8_t restorePriority

Restore priority of current group. 0 is the highest priority, 15 is the lowest priority

uint8_t savePriority

Save priority of current group. 0 is the highest priority, 15 is the lowest priority.

ssarc_power_domain_name_t powerDomain

Power domain.

uint32_t highestAddress

Highest address that can be accessed for the descriptors in the group.

uint32_t lowestAddress

Lowest address that can be accessed for the descriptors in the group.

TEMPSENSOR: Temperature Sensor Module

FSL_TMPSNS_DRIVER_VERSION

TMPSNS interrupt status enable type, tmpsns_interrupt_status_enable_t.

Values:

enumerator kTEMPSENSOR_HighTempInterruptStatusEnable

High temperature interrupt status enable.

enumerator kTEMPSENSOR_LowTempInterruptStatusEnable

Low temperature interrupt status enable.

enumerator kTEMPSENSOR_PanicTempInterruptStatusEnable

Panic temperature interrupt status enable.

enumerator kTEMPSENSOR_FinishInterruptStatusEnable

Finish interrupt enable.

TMPSNS interrupt status type, tmpsns_interrupt_status_t.

Values:

enumerator kTEMPSENSOR_HighTempInterruptStatus

High temperature interrupt status.

enumerator kTEMPSENSOR_LowTempInterruptStatus

Low temperature interrupt status.

enumerator kTEMPSENSOR_PanicTempInterruptStatus

Panic temperature interrupt status.

enum tmpsns_measure_mode_t

TMPSNS measure mode, tempsensor_measure_mode.

Values:

enumerator kTEMPSENSOR_SingleMode

Single measurement mode.

enumerator kTEMPSENSOR_ContinuousMode

Continuous measurement mode.

enum _tmpsns_alarm_mode

TMPSNS alarm mode.

Values:

enumerator kTEMPMON_HighAlarmMode

The high alarm temperature interrupt mode.

enumerator kTEMPMON_PanicAlarmMode

The panic alarm temperature interrupt mode.

enumerator kTEMPMON_LowAlarmMode

The low alarm temperature interrupt mode.

typedef struct _tmpsns_config tmpsns_config_t

TMPSNS temperature structure.

typedef enum _tmpsns_alarm_mode tmpsns_alarm_mode_t

TMPSNS alarm mode.

void TMPSNS_Init(TMPSNS_Type *base, const tmpsns_config_t *config)

Initializes the TMPSNS module.

Parameters:

• base – TMPSNS base pointer

• config – Pointer to configuration structure.

void TMPSNS_Deinit(TMPSNS_Type *base)

Deinitializes the TMPSNS module.

Parameters:

• base – TMPSNS base pointer

void TMPSNS_GetDefaultConfig(tmpsns_config_t *config)

Gets the default configuration structure.

This function initializes the TMPSNS configuration structure to a default value. The default values are: tempmonConfig->frequency = 0x02U; tempmonConfig->highAlarmTemp = 44U; tempmonConfig->panicAlarmTemp = 90U; tempmonConfig->lowAlarmTemp = 39U;

Parameters:

• config – Pointer to a configuration structure.

void TMPSNS_StartMeasure(TMPSNS_Type *base)

start the temperature measurement process.

Parameters:

• base – TMPSNS base pointer.

void TMPSNS_StopMeasure(TMPSNS_Type *base)

stop the measurement process.

Parameters:

• base – TMPSNS base pointer

float TMPSNS_GetCurrentTemperature(TMPSNS_Type *base)

Get current temperature with the fused temperature calibration data.

Parameters:

• base – TMPSNS base pointer

Returns:

current temperature with degrees Celsius.

void TMPSNS_SetTempAlarm(TMPSNS_Type *base, int32_t tempVal, tmpsns_alarm_mode_t alarmMode)

Set the temperature count (raw sensor output) that will generate an alarm interrupt.

Parameters:

• base – TMPSNS base pointer

• tempVal – The alarm temperature with degrees Celsius

• alarmMode – The alarm mode.

void TMPSNS_EnableInterrupt(TMPSNS_Type *base, uint32_t mask)

Enable interrupt status.

Parameters:

• base – TMPSNS base pointer

• mask – The interrupts to enable from tmpsns_interrupt_status_enable_t.

void TMPSNS_DisableInterrupt(TMPSNS_Type *base, uint32_t mask)

Disable interrupt status.

Parameters:

• base – TMPSNS base pointer

• mask – The interrupts to disable from tmpsns_interrupt_status_enable_t.

static inline uint32_t TMPSNS_GetInterruptFlags(TMPSNS_Type *base)

Get interrupt status flag.

Parameters:

• base – TMPSNS base pointer

static inline void TMPSNS_ClearInterruptFlags(TMPSNS_Type *base, uint32_t mask)

Clear interrupt status flag.

Parameters:

• base – TMPSNS base pointer

• mask – The interrupts to disable from tmpsns_interrupt_status_t.

struct _tmpsns_config

#include <fsl_tempsensor.h>

TMPSNS temperature structure.

Public Members

tmpsns_measure_mode_t measureMode

The temperature measure mode.

uint16_t frequency

The temperature measure frequency.

int32_t highAlarmTemp

The high alarm temperature.

int32_t panicAlarmTemp

The panic alarm temperature.

int32_t lowAlarmTemp

The low alarm temperature.

USDHC: Ultra Secured Digital Host Controller Driver

void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)

USDHC module initialization function.

Configures the USDHC according to the user configuration.

Example:

usdhc_config_t config;
config.cardDetectDat3 = false;
config.endianMode = kUSDHC_EndianModeLittle;
config.dmaMode = kUSDHC_DmaModeAdma2;
config.readWatermarkLevel = 128U;
config.writeWatermarkLevel = 128U;
USDHC_Init(USDHC, &config);

Parameters:

• base – USDHC peripheral base address.

• config – USDHC configuration information.

Return values:

kStatus_Success – Operate successfully.

void USDHC_Deinit(USDHC_Type *base)

Deinitializes the USDHC.

Parameters:

• base – USDHC peripheral base address.

bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout)

Resets the USDHC.

Parameters:

• base – USDHC peripheral base address.

• mask – The reset type mask(_usdhc_reset).

• timeout – Timeout for reset.

Return values:

• true – Reset successfully.

• false – Reset failed.

status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_data_t *dataConfig, uint32_t flags)

Sets the DMA descriptor table configuration. A high level DMA descriptor configuration function.

Parameters:

• base – USDHC peripheral base address.

• dmaConfig – ADMA configuration

• dataConfig – Data descriptor

• flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.

Return values:

• kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.

• kStatus_Success – Operate successfully.

status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, const uint32_t *dataAddr, bool enAutoCmd23)

Internal DMA configuration. This function is used to config the USDHC DMA related registers.

Parameters:

• base – USDHC peripheral base address.

• dmaConfig – ADMA configuration.

• dataAddr – Transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.

• enAutoCmd23 – Flag to indicate Auto CMD23 is enable or not, a simple DMA parameter, if ADMA is used, leave it to false.

Return values:

• kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.

• kStatus_Success – Operate successfully.

status_t USDHC_SetADMA2Descriptor(uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)

Sets the ADMA2 descriptor table configuration.

Parameters:

• admaTable – ADMA table address.

• admaTableWords – ADMA table length.

• dataBufferAddr – Data buffer address.

• dataBytes – Data Data length.

• flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.

Return values:

• kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.

• kStatus_Success – Operate successfully.

status_t USDHC_SetADMA1Descriptor(uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)

Sets the ADMA1 descriptor table configuration.

Parameters:

• admaTable – ADMA table address.

• admaTableWords – ADMA table length.

• dataBufferAddr – Data buffer address.

• dataBytes – Data length.

• flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.

Return values:

• kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.

• kStatus_Success – Operate successfully.

static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable)

Enables internal DMA.

Parameters:

• base – USDHC peripheral base address.

• enable – enable or disable flag

static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask)

Enables the interrupt status.

Parameters:

• base – USDHC peripheral base address.

• mask – Interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask)

Disables the interrupt status.

Parameters:

• base – USDHC peripheral base address.

• mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask)

Enables the interrupt signal corresponding to the interrupt status flag.

Parameters:

• base – USDHC peripheral base address.

• mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask)

Disables the interrupt signal corresponding to the interrupt status flag.

Parameters:

• base – USDHC peripheral base address.

• mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base)

Gets the enabled interrupt status.

Parameters:

• base – USDHC peripheral base address.

Returns:

Current interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base)

Gets the current interrupt status.

Parameters:

• base – USDHC peripheral base address.

Returns:

Current interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask)

Clears a specified interrupt status. write 1 clears.

Parameters:

• base – USDHC peripheral base address.

• mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).

static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base)

Gets the status of auto command 12 error.

Parameters:

• base – USDHC peripheral base address.

Returns:

Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag).

static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base)

Gets the status of the ADMA error.

Parameters:

• base – USDHC peripheral base address.

Returns:

ADMA error status flags mask(_usdhc_adma_error_status_flag).

static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base)

Gets a present status.

This function gets the present USDHC’s status except for an interrupt status and an error status.

Parameters:

• base – USDHC peripheral base address.

Returns:

Present USDHC’s status flags mask(_usdhc_present_status_flag).

void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability)

Gets the capability information.

Parameters:

• base – USDHC peripheral base address.

• capability – Structure to save capability information.

static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable)

Forces the card clock on.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz)

Sets the SD bus clock frequency.

Parameters:

• base – USDHC peripheral base address.

• srcClock_Hz – USDHC source clock frequency united in Hz.

• busClock_Hz – SD bus clock frequency united in Hz.

Returns:

The nearest frequency of busClock_Hz configured for SD bus.

bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout)

Sends 80 clocks to the card to set it to the active state.

This function must be called each time the card is inserted to ensure that the card can receive the command correctly.

Parameters:

• base – USDHC peripheral base address.

• timeout – Timeout to initialize card.

Return values:

• true – Set card active successfully.

• false – Set card active failed.

static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high)

Triggers a hardware reset.

Parameters:

• base – USDHC peripheral base address.

• high – 1 or 0 level

static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width)

Sets the data transfer width.

Parameters:

• base – USDHC peripheral base address.

• width – Data transfer width.

static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data)

Fills the data port.

This function is used to implement the data transfer by Data Port instead of DMA.

Parameters:

• base – USDHC peripheral base address.

• data – The data about to be sent.

static inline uint32_t USDHC_ReadData(USDHC_Type *base)

Retrieves the data from the data port.

This function is used to implement the data transfer by Data Port instead of DMA.

Parameters:

• base – USDHC peripheral base address.

Returns:

The data has been read.

void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command)

Sends command function.

Parameters:

• base – USDHC peripheral base address.

• command – configuration

static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable)

Enables or disables a wakeup event in low-power mode.

Parameters:

• base – USDHC peripheral base address.

• mask – Wakeup events mask(_usdhc_wakeup_event).

• enable – True to enable, false to disable.

static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable)

Detects card insert status.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

static inline bool USDHC_DetectCardInsert(USDHC_Type *base)

Detects card insert status.

Parameters:

• base – USDHC peripheral base address.

static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable)

Enables or disables the SDIO card control.

Parameters:

• base – USDHC peripheral base address.

• mask – SDIO card control flags mask(_usdhc_sdio_control_flag).

• enable – True to enable, false to disable.

static inline void USDHC_SetContinueRequest(USDHC_Type *base)

Restarts a transaction which has stopped at the block GAP for the SDIO card.

Parameters:

• base – USDHC peripheral base address.

static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable)

Request stop at block gap function.

Parameters:

• base – USDHC peripheral base address.

• enable – True to stop at block gap, false to normal transfer.

void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config)

Configures the MMC boot feature.

Example:

usdhc_boot_config_t config;
config.ackTimeoutCount = 4;
config.bootMode = kUSDHC_BootModeNormal;
config.blockCount = 5;
config.enableBootAck = true;
config.enableBoot = true;
config.enableAutoStopAtBlockGap = true;
USDHC_SetMmcBootConfig(USDHC, &config);

Parameters:

• base – USDHC peripheral base address.

• config – The MMC boot configuration information.

static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable)

Enables or disables the mmc boot mode.

Parameters:

• base – USDHC peripheral base address.

• enable – True to enable, false to disable.

static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask)

Forces generating events according to the given mask.

Parameters:

• base – USDHC peripheral base address.

• mask – The force events bit posistion (_usdhc_force_event).

static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base)

Checks the SDR50 mode request tuning bit. When this bit set, application shall perform tuning for SDR50 mode.

Parameters:

• base – USDHC peripheral base address.

static inline bool USDHC_RequestReTuning(USDHC_Type *base)

Checks the request re-tuning bit. When this bit is set, user should do manual tuning or standard tuning function.

Parameters:

• base – USDHC peripheral base address.

static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable)

The SDR104 mode auto tuning enable and disable. This function should be called after tuning function execute pass, auto tuning will handle by hardware.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base)

The auto tuning enbale for CMD/DATA line.

Parameters:

• base – USDHC peripheral base address.

void USDHC_EnableManualTuning(USDHC_Type *base, bool enable)

Manual tuning trigger or abort. User should handle the tuning cmd and find the boundary of the delay then calucate a average value which will be configured to the CLK_TUNE_CTRL_STATUS This function should be called before function USDHC_AdjustDelayForManualTuning.

Parameters:

• base – USDHC peripheral base address.

• enable – tuning enable flag

static inline uint32_t USDHC_GetTuningDelayStatus(USDHC_Type *base)

Get the tuning delay cell setting.

Parameters:

• base – USDHC peripheral base address.

Return values:

CLK – Tuning Control and Status register value.

status_t USDHC_SetTuningDelay(USDHC_Type *base, uint32_t preDelay, uint32_t outDelay, uint32_t postDelay)

The tuning delay cell setting.

Parameters:

• base – USDHC peripheral base address.

• preDelay – Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE.

• outDelay – Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT.

• postDelay – Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST.

Return values:

• kStatus_Fail – config the delay setting fail

• kStatus_Success – config the delay setting success

status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay)

Adjusts delay for mannual tuning.

Deprecated:

Do not use this function. It has been superceded by USDHC_SetTuingDelay

Parameters:

• base – USDHC peripheral base address.

• delay – setting configuration

Return values:

• kStatus_Fail – config the delay setting fail

• kStatus_Success – config the delay setting success

static inline void USDHC_SetStandardTuningCounter(USDHC_Type *base, uint8_t counter)

set tuning counter tuning.

Parameters:

• base – USDHC peripheral base address.

• counter – tuning counter

Return values:

• kStatus_Fail – config the delay setting fail

• kStatus_Success – config the delay setting success

void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable)

The enable standard tuning function. The standard tuning window and tuning counter using the default config tuning cmd is sent by the software, user need to check whether the tuning result can be used for SDR50, SDR104, and HS200 mode tuning.

Parameters:

• base – USDHC peripheral base address.

• tuningStartTap – start tap

• step – tuning step

• enable – enable/disable flag

static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base)

Gets execute STD tuning status.

Parameters:

• base – USDHC peripheral base address.

static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base)

Checks STD tuning result.

Parameters:

• base – USDHC peripheral base address.

static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base)

Checks tuning error.

Parameters:

• base – USDHC peripheral base address.

void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos)

The enable/disable DDR mode.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

• nibblePos – nibble position

static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable)

The enable/disable HS400 mode.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

static inline void USDHC_ResetStrobeDLL(USDHC_Type *base)

Resets the strobe DLL.

Parameters:

• base – USDHC peripheral base address.

static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable)

Enables/disables the strobe DLL.

Parameters:

• base – USDHC peripheral base address.

• enable – enable/disable flag

void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval)

Configs the strobe DLL delay target and update interval.

Parameters:

• base – USDHC peripheral base address.

• delayTarget – delay target

• updateInterval – update interval

static inline void USDHC_SetStrobeDllOverride(USDHC_Type *base, uint32_t delayTaps)

Enables manual override for slave delay chain using STROBE_SLV_OVERRIDE_VAL.

Parameters:

• base – USDHC peripheral base address.

• delayTaps – Valid delay taps range from 1 - 128 taps. A value of 0 selects tap 1, and a value of 0x7F selects tap 128.

static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base)

Gets the strobe DLL status.

Parameters:

• base – USDHC peripheral base address.

void USDHC_SetDataConfig(USDHC_Type *base, usdhc_transfer_direction_t dataDirection, uint32_t blockCount, uint32_t blockSize)

USDHC data configuration.

Parameters:

• base – USDHC peripheral base address.

• dataDirection – Data direction, tx or rx.

• blockCount – Data block count.

• blockSize – Data block size.

void USDHC_TransferCreateHandle(USDHC_Type *base, usdhc_handle_t *handle, const usdhc_transfer_callback_t *callback, void *userData)

Creates the USDHC handle.

Parameters:

• base – USDHC peripheral base address.

• handle – USDHC handle pointer.

• callback – Structure pointer to contain all callback functions.

• userData – Callback function parameter.

status_t USDHC_TransferNonBlocking(USDHC_Type *base, usdhc_handle_t *handle, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer)

Transfers the command/data using an interrupt and an asynchronous method.

This function sends a command and data and returns immediately. It doesn’t wait for the transfer to complete or to encounter an error. The application must not call this API in multiple threads at the same time. Because of that this API doesn’t support the re-entry mechanism.

Note

Call API USDHC_TransferCreateHandle when calling this API.

Parameters:

• base – USDHC peripheral base address.

• handle – USDHC handle.

• dmaConfig – ADMA configuration.

• transfer – Transfer content.

Return values:

• kStatus_InvalidArgument – Argument is invalid.

• kStatus_USDHC_BusyTransferring – Busy transferring.

• kStatus_USDHC_PrepareAdmaDescriptorFailed – Prepare ADMA descriptor failed.

• kStatus_Success – Operate successfully.

status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer)

Transfers the command/data using a blocking method.

This function waits until the command response/data is received or the USDHC encounters an error by polling the status flag.

The application must not call this API in multiple threads at the same time. Because this API doesn’t support the re-entry mechanism.

Note

There is no need to call API USDHC_TransferCreateHandle when calling this API.

Parameters:

• base – USDHC peripheral base address.

• dmaConfig – adma configuration

• transfer – Transfer content.

Return values:

• kStatus_InvalidArgument – Argument is invalid.

• kStatus_USDHC_PrepareAdmaDescriptorFailed – Prepare ADMA descriptor failed.

• kStatus_USDHC_SendCommandFailed – Send command failed.

• kStatus_USDHC_TransferDataFailed – Transfer data failed.

• kStatus_Success – Operate successfully.

void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle)

IRQ handler for the USDHC.

This function deals with the IRQs on the given host controller.

Parameters:

• base – USDHC peripheral base address.

• handle – USDHC handle.

FSL_USDHC_DRIVER_VERSION

Driver version 2.8.4.

Enum _usdhc_status. USDHC status.

Values:

enumerator kStatus_USDHC_BusyTransferring

Transfer is on-going.

enumerator kStatus_USDHC_PrepareAdmaDescriptorFailed

Set DMA descriptor failed.

enumerator kStatus_USDHC_SendCommandFailed

Send command failed.

enumerator kStatus_USDHC_TransferDataFailed

Transfer data failed.

enumerator kStatus_USDHC_DMADataAddrNotAlign

Data address not aligned.

enumerator kStatus_USDHC_ReTuningRequest

Re-tuning request.

enumerator kStatus_USDHC_TuningError

Tuning error.

enumerator kStatus_USDHC_NotSupport

Not support.

enumerator kStatus_USDHC_TransferDataComplete

Transfer data complete.

enumerator kStatus_USDHC_SendCommandSuccess

Transfer command complete.

enumerator kStatus_USDHC_TransferDMAComplete

Transfer DMA complete.

Enum _usdhc_capability_flag. Host controller capabilities flag mask. .

Values:

enumerator kUSDHC_SupportAdmaFlag

Support ADMA.

enumerator kUSDHC_SupportHighSpeedFlag

Support high-speed.

enumerator kUSDHC_SupportDmaFlag

Support DMA.

enumerator kUSDHC_SupportSuspendResumeFlag

Support suspend/resume.

enumerator kUSDHC_SupportV330Flag

Support voltage 3.3V.

enumerator kUSDHC_SupportV300Flag

Support voltage 3.0V.

enumerator kUSDHC_Support4BitFlag

Flag in HTCAPBLT_MBL’s position, supporting 4-bit mode.

enumerator kUSDHC_Support8BitFlag

Flag in HTCAPBLT_MBL’s position, supporting 8-bit mode.

enumerator kUSDHC_SupportDDR50Flag

SD version 3.0 new feature, supporting DDR50 mode.

enumerator kUSDHC_SupportSDR104Flag

Support SDR104 mode.

enumerator kUSDHC_SupportSDR50Flag

Support SDR50 mode.

Enum _usdhc_wakeup_event. Wakeup event mask. .

Values:

enumerator kUSDHC_WakeupEventOnCardInt

Wakeup on card interrupt.

enumerator kUSDHC_WakeupEventOnCardInsert

Wakeup on card insertion.

enumerator kUSDHC_WakeupEventOnCardRemove

Wakeup on card removal.

enumerator kUSDHC_WakeupEventsAll

All wakeup events

Enum _usdhc_reset. Reset type mask. .

Values:

enumerator kUSDHC_ResetAll

Reset all except card detection.

enumerator kUSDHC_ResetCommand

Reset command line.

enumerator kUSDHC_ResetData

Reset data line.

enumerator kUSDHC_ResetTuning

Reset tuning circuit.

enumerator kUSDHC_ResetsAll

All reset types

Enum _usdhc_transfer_flag. Transfer flag mask.

Values:

enumerator kUSDHC_EnableDmaFlag

Enable DMA.

enumerator kUSDHC_CommandTypeSuspendFlag

Suspend command.

enumerator kUSDHC_CommandTypeResumeFlag

Resume command.

enumerator kUSDHC_CommandTypeAbortFlag

Abort command.

enumerator kUSDHC_EnableBlockCountFlag

Enable block count.

enumerator kUSDHC_EnableAutoCommand12Flag

Enable auto CMD12.

enumerator kUSDHC_DataReadFlag

Enable data read.

enumerator kUSDHC_MultipleBlockFlag

Multiple block data read/write.

enumerator kUSDHC_EnableAutoCommand23Flag

Enable auto CMD23.

enumerator kUSDHC_ResponseLength136Flag

136-bit response length.

enumerator kUSDHC_ResponseLength48Flag

48-bit response length.

enumerator kUSDHC_ResponseLength48BusyFlag

48-bit response length with busy status.

enumerator kUSDHC_EnableCrcCheckFlag

Enable CRC check.

enumerator kUSDHC_EnableIndexCheckFlag

Enable index check.

enumerator kUSDHC_DataPresentFlag

Data present flag.

Enum _usdhc_present_status_flag. Present status flag mask. .

Values:

enumerator kUSDHC_CommandInhibitFlag

Command inhibit.

enumerator kUSDHC_DataInhibitFlag

Data inhibit.

enumerator kUSDHC_DataLineActiveFlag

Data line active.

enumerator kUSDHC_SdClockStableFlag

SD bus clock stable.

enumerator kUSDHC_WriteTransferActiveFlag

Write transfer active.

enumerator kUSDHC_ReadTransferActiveFlag

Read transfer active.

enumerator kUSDHC_BufferWriteEnableFlag

Buffer write enable.

enumerator kUSDHC_BufferReadEnableFlag

Buffer read enable.

enumerator kUSDHC_ReTuningRequestFlag

Re-tuning request flag, only used for SDR104 mode.

enumerator kUSDHC_DelaySettingFinishedFlag

Delay setting finished flag.

enumerator kUSDHC_CardInsertedFlag

Card inserted.

enumerator kUSDHC_CommandLineLevelFlag

Command line signal level.

enumerator kUSDHC_Data0LineLevelFlag

Data0 line signal level.

enumerator kUSDHC_Data1LineLevelFlag

Data1 line signal level.

enumerator kUSDHC_Data2LineLevelFlag

Data2 line signal level.

enumerator kUSDHC_Data3LineLevelFlag

Data3 line signal level.

enumerator kUSDHC_Data4LineLevelFlag

Data4 line signal level.

enumerator kUSDHC_Data5LineLevelFlag

Data5 line signal level.

enumerator kUSDHC_Data6LineLevelFlag

Data6 line signal level.

enumerator kUSDHC_Data7LineLevelFlag

Data7 line signal level.

Enum _usdhc_interrupt_status_flag. Interrupt status flag mask. .

Values:

enumerator kUSDHC_CommandCompleteFlag

Command complete.

enumerator kUSDHC_DataCompleteFlag

Data complete.

enumerator kUSDHC_BlockGapEventFlag

Block gap event.

enumerator kUSDHC_DmaCompleteFlag

DMA interrupt.

enumerator kUSDHC_BufferWriteReadyFlag

Buffer write ready.

enumerator kUSDHC_BufferReadReadyFlag

Buffer read ready.

enumerator kUSDHC_CardInsertionFlag

Card inserted.

enumerator kUSDHC_CardRemovalFlag

Card removed.

enumerator kUSDHC_CardInterruptFlag

Card interrupt.

enumerator kUSDHC_ReTuningEventFlag

Re-Tuning event, only for SD3.0 SDR104 mode.

enumerator kUSDHC_TuningPassFlag

SDR104 mode tuning pass flag.

enumerator kUSDHC_TuningErrorFlag

SDR104 tuning error flag.

enumerator kUSDHC_CommandTimeoutFlag

Command timeout error.

enumerator kUSDHC_CommandCrcErrorFlag

Command CRC error.

enumerator kUSDHC_CommandEndBitErrorFlag

Command end bit error.

enumerator kUSDHC_CommandIndexErrorFlag

Command index error.

enumerator kUSDHC_DataTimeoutFlag

Data timeout error.

enumerator kUSDHC_DataCrcErrorFlag

Data CRC error.

enumerator kUSDHC_DataEndBitErrorFlag

Data end bit error.

enumerator kUSDHC_AutoCommand12ErrorFlag

Auto CMD12 error.

enumerator kUSDHC_DmaErrorFlag

DMA error.

enumerator kUSDHC_CommandErrorFlag

Command error

enumerator kUSDHC_DataErrorFlag

Data error

enumerator kUSDHC_ErrorFlag

All error

enumerator kUSDHC_DataFlag

Data interrupts

enumerator kUSDHC_DataDMAFlag

Data interrupts

enumerator kUSDHC_CommandFlag

Command interrupts

enumerator kUSDHC_CardDetectFlag

Card detection interrupts

enumerator kUSDHC_SDR104TuningFlag

SDR104 tuning flag.

enumerator kUSDHC_AllInterruptFlags

All flags mask

Enum _usdhc_auto_command12_error_status_flag. Auto CMD12 error status flag mask. .

Values:

enumerator kUSDHC_AutoCommand12NotExecutedFlag

Not executed error.

enumerator kUSDHC_AutoCommand12TimeoutFlag

Timeout error.

enumerator kUSDHC_AutoCommand12EndBitErrorFlag

End bit error.

enumerator kUSDHC_AutoCommand12CrcErrorFlag

CRC error.

enumerator kUSDHC_AutoCommand12IndexErrorFlag

Index error.

enumerator kUSDHC_AutoCommand12NotIssuedFlag

Not issued error.

Enum _usdhc_standard_tuning. Standard tuning flag.

Values:

enumerator kUSDHC_ExecuteTuning

Used to start tuning procedure.

enumerator kUSDHC_TuningSampleClockSel

When std_tuning_en bit is set, this bit is used to select sampleing clock.

Enum _usdhc_adma_error_status_flag. ADMA error status flag mask. .

Values:

enumerator kUSDHC_AdmaLenghMismatchFlag

Length mismatch error.

enumerator kUSDHC_AdmaDescriptorErrorFlag

Descriptor error.

Enum _usdhc_adma_error_state. ADMA error state.

This state is the detail state when ADMA error has occurred.

Values:

enumerator kUSDHC_AdmaErrorStateStopDma

Stop DMA, previous location set in the ADMA system address is errored address.

enumerator kUSDHC_AdmaErrorStateFetchDescriptor

Fetch descriptor, current location set in the ADMA system address is errored address.

enumerator kUSDHC_AdmaErrorStateChangeAddress

Change address, no DMA error has occurred.

enumerator kUSDHC_AdmaErrorStateTransferData

Transfer data, previous location set in the ADMA system address is errored address.

enumerator kUSDHC_AdmaErrorStateInvalidLength

Invalid length in ADMA descriptor.

enumerator kUSDHC_AdmaErrorStateInvalidDescriptor

Invalid descriptor fetched by ADMA.

enumerator kUSDHC_AdmaErrorState

ADMA error state

Enum _usdhc_force_event. Force event bit position. .

Values:

enumerator kUSDHC_ForceEventAutoCommand12NotExecuted

Auto CMD12 not executed error.

enumerator kUSDHC_ForceEventAutoCommand12Timeout

Auto CMD12 timeout error.

enumerator kUSDHC_ForceEventAutoCommand12CrcError

Auto CMD12 CRC error.

enumerator kUSDHC_ForceEventEndBitError

Auto CMD12 end bit error.

enumerator kUSDHC_ForceEventAutoCommand12IndexError

Auto CMD12 index error.

enumerator kUSDHC_ForceEventAutoCommand12NotIssued

Auto CMD12 not issued error.

enumerator kUSDHC_ForceEventCommandTimeout

Command timeout error.

enumerator kUSDHC_ForceEventCommandCrcError

Command CRC error.

enumerator kUSDHC_ForceEventCommandEndBitError

Command end bit error.

enumerator kUSDHC_ForceEventCommandIndexError

Command index error.

enumerator kUSDHC_ForceEventDataTimeout

Data timeout error.

enumerator kUSDHC_ForceEventDataCrcError

Data CRC error.

enumerator kUSDHC_ForceEventDataEndBitError

Data end bit error.

enumerator kUSDHC_ForceEventAutoCommand12Error

Auto CMD12 error.

enumerator kUSDHC_ForceEventCardInt

Card interrupt.

enumerator kUSDHC_ForceEventDmaError

Dma error.

enumerator kUSDHC_ForceEventTuningError

Tuning error.

enumerator kUSDHC_ForceEventsAll

All force event flags mask.

enum _usdhc_transfer_direction

Data transfer direction.

Values:

enumerator kUSDHC_TransferDirectionReceive

USDHC transfer direction receive.

enumerator kUSDHC_TransferDirectionSend

USDHC transfer direction send.

enum _usdhc_data_bus_width

Data transfer width.

Values:

enumerator kUSDHC_DataBusWidth1Bit

1-bit mode

enumerator kUSDHC_DataBusWidth4Bit

4-bit mode

enumerator kUSDHC_DataBusWidth8Bit

8-bit mode

enum _usdhc_endian_mode

Endian mode.

Values:

enumerator kUSDHC_EndianModeBig

Big endian mode.

enumerator kUSDHC_EndianModeHalfWordBig

Half word big endian mode.

enumerator kUSDHC_EndianModeLittle

Little endian mode.

enum _usdhc_dma_mode

DMA mode.

Values:

enumerator kUSDHC_DmaModeSimple

External DMA.

enumerator kUSDHC_DmaModeAdma1

ADMA1 is selected.

enumerator kUSDHC_DmaModeAdma2

ADMA2 is selected.

enumerator kUSDHC_ExternalDMA

External DMA mode selected.

Enum _usdhc_sdio_control_flag. SDIO control flag mask. .

Values:

enumerator kUSDHC_StopAtBlockGapFlag

Stop at block gap.

enumerator kUSDHC_ReadWaitControlFlag

Read wait control.

enumerator kUSDHC_InterruptAtBlockGapFlag

Interrupt at block gap.

enumerator kUSDHC_ReadDoneNo8CLK

Read done without 8 clk for block gap.

enumerator kUSDHC_ExactBlockNumberReadFlag

Exact block number read.

enum _usdhc_boot_mode

MMC card boot mode.

Values:

enumerator kUSDHC_BootModeNormal

Normal boot

enumerator kUSDHC_BootModeAlternative

Alternative boot

enum _usdhc_card_command_type

The command type.

Values:

enumerator kCARD_CommandTypeNormal

Normal command

enumerator kCARD_CommandTypeSuspend

Suspend command

enumerator kCARD_CommandTypeResume

Resume command

enumerator kCARD_CommandTypeAbort

Abort command

enumerator kCARD_CommandTypeEmpty

Empty command

enum _usdhc_card_response_type

The command response type.

Defines the command response type from card to host controller.

Values:

enumerator kCARD_ResponseTypeNone

Response type: none

enumerator kCARD_ResponseTypeR1

Response type: R1

enumerator kCARD_ResponseTypeR1b

Response type: R1b

enumerator kCARD_ResponseTypeR2

Response type: R2

enumerator kCARD_ResponseTypeR3

Response type: R3

enumerator kCARD_ResponseTypeR4

Response type: R4

enumerator kCARD_ResponseTypeR5

Response type: R5

enumerator kCARD_ResponseTypeR5b

Response type: R5b

enumerator kCARD_ResponseTypeR6

Response type: R6

enumerator kCARD_ResponseTypeR7

Response type: R7

Enum _usdhc_adma1_descriptor_flag. The mask for the control/status field in ADMA1 descriptor.

Values:

enumerator kUSDHC_Adma1DescriptorValidFlag

Valid flag.

enumerator kUSDHC_Adma1DescriptorEndFlag

End flag.

enumerator kUSDHC_Adma1DescriptorInterrupFlag

Interrupt flag.

enumerator kUSDHC_Adma1DescriptorActivity1Flag

Activity 1 flag.

enumerator kUSDHC_Adma1DescriptorActivity2Flag

Activity 2 flag.

enumerator kUSDHC_Adma1DescriptorTypeNop

No operation.

enumerator kUSDHC_Adma1DescriptorTypeTransfer

Transfer data.

enumerator kUSDHC_Adma1DescriptorTypeLink

Link descriptor.

enumerator kUSDHC_Adma1DescriptorTypeSetLength

Set data length.

Enum _usdhc_adma2_descriptor_flag. ADMA1 descriptor control and status mask.

Values:

enumerator kUSDHC_Adma2DescriptorValidFlag

Valid flag.

enumerator kUSDHC_Adma2DescriptorEndFlag

End flag.

enumerator kUSDHC_Adma2DescriptorInterruptFlag

Interrupt flag.

enumerator kUSDHC_Adma2DescriptorActivity1Flag

Activity 1 mask.

enumerator kUSDHC_Adma2DescriptorActivity2Flag

Activity 2 mask.

enumerator kUSDHC_Adma2DescriptorTypeNop

No operation.

enumerator kUSDHC_Adma2DescriptorTypeReserved

Reserved.

enumerator kUSDHC_Adma2DescriptorTypeTransfer

Transfer type.

enumerator kUSDHC_Adma2DescriptorTypeLink

Link type.

Enum _usdhc_adma_flag. ADMA descriptor configuration flag. .

Values:

enumerator kUSDHC_AdmaDescriptorSingleFlag

Try to finish the transfer in a single ADMA descriptor. If transfer size is bigger than one ADMA descriptor’s ability, new another descriptor for data transfer.

enumerator kUSDHC_AdmaDescriptorMultipleFlag

Create multiple ADMA descriptors within the ADMA table, this is used for mmc boot mode specifically, which need to modify the ADMA descriptor on the fly, so the flag should be used combining with stop at block gap feature.

enum _usdhc_burst_len

DMA transfer burst len config.

Values:

enumerator kUSDHC_EnBurstLenForINCR

Enable burst len for INCR.

enumerator kUSDHC_EnBurstLenForINCR4816

Enable burst len for INCR4/INCR8/INCR16.

enumerator kUSDHC_EnBurstLenForINCR4816WRAP

Enable burst len for INCR4/8/16 WRAP.

Enum _usdhc_transfer_data_type. Tansfer data type definition.

Values:

enumerator kUSDHC_TransferDataNormal

Transfer normal read/write data.

enumerator kUSDHC_TransferDataTuning

Transfer tuning data.

enumerator kUSDHC_TransferDataBoot

Transfer boot data.

enumerator kUSDHC_TransferDataBootcontinous

Transfer boot data continuously.

typedef enum _usdhc_transfer_direction usdhc_transfer_direction_t

Data transfer direction.

typedef enum _usdhc_data_bus_width usdhc_data_bus_width_t

Data transfer width.

typedef enum _usdhc_endian_mode usdhc_endian_mode_t

Endian mode.

typedef enum _usdhc_dma_mode usdhc_dma_mode_t

DMA mode.

typedef enum _usdhc_boot_mode usdhc_boot_mode_t

MMC card boot mode.

typedef enum _usdhc_card_command_type usdhc_card_command_type_t

The command type.

typedef enum _usdhc_card_response_type usdhc_card_response_type_t

The command response type.

Defines the command response type from card to host controller.

typedef enum _usdhc_burst_len usdhc_burst_len_t

DMA transfer burst len config.

typedef uint32_t usdhc_adma1_descriptor_t

Defines the ADMA1 descriptor structure.

typedef struct _usdhc_adma2_descriptor usdhc_adma2_descriptor_t

Defines the ADMA2 descriptor structure.

typedef struct _usdhc_capability usdhc_capability_t

USDHC capability information.

Defines a structure to save the capability information of USDHC.

typedef struct _usdhc_boot_config usdhc_boot_config_t

Data structure to configure the MMC boot feature.

typedef struct _usdhc_config usdhc_config_t

Data structure to initialize the USDHC.

typedef struct _usdhc_command usdhc_command_t

Card command descriptor.

Defines card command-related attribute.

typedef struct _usdhc_adma_config usdhc_adma_config_t

ADMA configuration.

typedef struct _usdhc_scatter_gather_data_list usdhc_scatter_gather_data_list_t

Card scatter gather data list.

Allow application register uncontinuous data buffer for data transfer.

typedef struct _usdhc_scatter_gather_data usdhc_scatter_gather_data_t

Card scatter gather data descriptor.

Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.

typedef struct _usdhc_scatter_gather_transfer usdhc_scatter_gather_transfer_t

usdhc scatter gather transfer.

typedef struct _usdhc_data usdhc_data_t

Card data descriptor.

Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.

typedef struct _usdhc_transfer usdhc_transfer_t

Transfer state.

typedef struct _usdhc_handle usdhc_handle_t

USDHC handle typedef.

typedef struct _usdhc_transfer_callback usdhc_transfer_callback_t

USDHC callback functions.

typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content)

USDHC transfer function.

typedef struct _usdhc_host usdhc_host_t

USDHC host descriptor.

USDHC_MAX_BLOCK_COUNT

Maximum block count can be set one time.

FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER

USDHC scatter gather feature control macro.

USDHC_ADMA1_ADDRESS_ALIGN

The alignment size for ADDRESS filed in ADMA1’s descriptor.

USDHC_ADMA1_LENGTH_ALIGN

The alignment size for LENGTH field in ADMA1’s descriptor.

USDHC_ADMA2_ADDRESS_ALIGN

The alignment size for ADDRESS field in ADMA2’s descriptor.

USDHC_ADMA2_LENGTH_ALIGN

The alignment size for LENGTH filed in ADMA2’s descriptor.

USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT

The bit shift for ADDRESS filed in ADMA1’s descriptor.

Address/page field	Reserved	Attribute
31 12	11 6	05	04	03	02	01	00
address or data length	000000	Act2	Act1	0	Int	End	Valid

Act2	Act1	Comment	31-28	27-12
0	0	No op	Don’t care
0	1	Set data length	0000	Data Length
1	0	Transfer data	Data address
1	1	Link descriptor	Descriptor address

USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK

The bit mask for ADDRESS field in ADMA1’s descriptor.

USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT

The bit shift for LENGTH filed in ADMA1’s descriptor.

USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK

The mask for LENGTH field in ADMA1’s descriptor.

USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY

The maximum value of LENGTH filed in ADMA1’s descriptor. Since the max transfer size ADMA1 support is 65535 which is indivisible by 4096, so to make sure a large data load transfer (>64KB) continuously (require the data address be always align with 4096), software will set the maximum data length for ADMA1 to (64 - 4)KB.

USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT

The bit shift for LENGTH field in ADMA2’s descriptor.

Address field	Length	Reserved	Attribute
63 32	31 16	15 06	05	04	03	02	01	00
32-bit address	16-bit length	0000000000	Act2	Act1	0	Int	End	Valid

Act2	Act1	Comment	Operation
0	0	No op	Don’t care
0	1	Reserved	Read this line and go to next one
1	0	Transfer data	Transfer data with address and length set in this descriptor line
1	1	Link descriptor	Link to another descriptor

USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK

The bit mask for LENGTH field in ADMA2’s descriptor.

USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY

The maximum value of LENGTH field in ADMA2’s descriptor.

struct _usdhc_adma2_descriptor

#include <fsl_usdhc.h>

Defines the ADMA2 descriptor structure.

Public Members

uint32_t attribute

The control and status field.

const uint32_t *address

The address field.

struct _usdhc_capability

#include <fsl_usdhc.h>

USDHC capability information.

Defines a structure to save the capability information of USDHC.

Public Members

uint32_t sdVersion

Support SD card/sdio version.

uint32_t mmcVersion

Support EMMC card version.

uint32_t maxBlockLength

Maximum block length united as byte.

uint32_t maxBlockCount

Maximum block count can be set one time.

uint32_t flags

Capability flags to indicate the support information(_usdhc_capability_flag).

struct _usdhc_boot_config

#include <fsl_usdhc.h>

Data structure to configure the MMC boot feature.

Public Members

uint32_t ackTimeoutCount

Timeout value for the boot ACK. The available range is 0 ~ 15.

usdhc_boot_mode_t bootMode

Boot mode selection.

uint32_t blockCount

Stop at block gap value of automatic mode. Available range is 0 ~ 65535.

size_t blockSize

Block size.

bool enableBootAck

Enable or disable boot ACK.

bool enableAutoStopAtBlockGap

Enable or disable auto stop at block gap function in boot period.

struct _usdhc_config

#include <fsl_usdhc.h>

Data structure to initialize the USDHC.

Public Members

uint32_t dataTimeout

Data timeout value.

usdhc_endian_mode_t endianMode

Endian mode.

uint8_t readWatermarkLevel

Watermark level for DMA read operation. Available range is 1 ~ 128.

uint8_t writeWatermarkLevel

Watermark level for DMA write operation. Available range is 1 ~ 128.

struct _usdhc_command

#include <fsl_usdhc.h>

Card command descriptor.

Defines card command-related attribute.

Public Members

uint32_t index

Command index.

uint32_t argument

Command argument.

usdhc_card_command_type_t type

Command type.

usdhc_card_response_type_t responseType

Command response type.

uint32_t response[4U]

Response for this command.

uint32_t responseErrorFlags

Response error flag, which need to check the command reponse.

uint32_t flags

Cmd flags.

struct _usdhc_adma_config

#include <fsl_usdhc.h>

ADMA configuration.

Public Members

usdhc_dma_mode_t dmaMode

DMA mode.

uint32_t *admaTable

ADMA table address, can’t be null if transfer way is ADMA1/ADMA2.

uint32_t admaTableWords

ADMA table length united as words, can’t be 0 if transfer way is ADMA1/ADMA2.

struct _usdhc_scatter_gather_data_list

#include <fsl_usdhc.h>

Card scatter gather data list.

Allow application register uncontinuous data buffer for data transfer.

struct _usdhc_scatter_gather_data

#include <fsl_usdhc.h>

Card scatter gather data descriptor.

Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.

Public Members

bool enableAutoCommand12

Enable auto CMD12.

bool enableAutoCommand23

Enable auto CMD23.

bool enableIgnoreError

Enable to ignore error event to read/write all the data.

usdhc_transfer_direction_t dataDirection

data direction

uint8_t dataType

this is used to distinguish the normal/tuning/boot data.

size_t blockSize

Block size.

usdhc_scatter_gather_data_list_t sgData

scatter gather data

struct _usdhc_scatter_gather_transfer

#include <fsl_usdhc.h>

usdhc scatter gather transfer.

Public Members

usdhc_scatter_gather_data_t *data

Data to transfer.

usdhc_command_t *command

Command to send.

struct _usdhc_data

#include <fsl_usdhc.h>

Card data descriptor.

Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.

Public Members

bool enableAutoCommand12

Enable auto CMD12.

bool enableAutoCommand23

Enable auto CMD23.

bool enableIgnoreError

Enable to ignore error event to read/write all the data.

uint8_t dataType

this is used to distinguish the normal/tuning/boot data.

size_t blockSize

Block size.

uint32_t blockCount

Block count.

uint32_t *rxData

Buffer to save data read.

const uint32_t *txData

Data buffer to write.

struct _usdhc_transfer

#include <fsl_usdhc.h>

Transfer state.

Public Members

usdhc_data_t *data

Data to transfer.

usdhc_command_t *command

Command to send.

struct _usdhc_transfer_callback

#include <fsl_usdhc.h>

USDHC callback functions.

Public Members

void (*CardInserted)(USDHC_Type *base, void *userData)

Card inserted occurs when DAT3/CD pin is for card detect

void (*CardRemoved)(USDHC_Type *base, void *userData)

Card removed occurs

void (*SdioInterrupt)(USDHC_Type *base, void *userData)

SDIO card interrupt occurs

void (*BlockGap)(USDHC_Type *base, void *userData)

stopped at block gap event

void (*TransferComplete)(USDHC_Type *base, usdhc_handle_t *handle, status_t status, void *userData)

Transfer complete callback.

void (*ReTuning)(USDHC_Type *base, void *userData)

Handle the re-tuning.

struct _usdhc_handle

#include <fsl_usdhc.h>

USDHC handle.

Defines the structure to save the USDHC state information and callback function.

Note

All the fields except interruptFlags and transferredWords must be allocated by the user.

Public Members

usdhc_data_t *volatile data

Transfer parameter. Data to transfer.

usdhc_command_t *volatile command

Transfer parameter. Command to send.

volatile uint32_t transferredWords

Transfer status. Words transferred by DATAPORT way.

usdhc_transfer_callback_t callback

Callback function.

void *userData

Parameter for transfer complete callback.

struct _usdhc_host

#include <fsl_usdhc.h>

USDHC host descriptor.

Public Members

USDHC_Type *base

USDHC peripheral base address.

uint32_t sourceClock_Hz

USDHC source clock frequency united in Hz.

usdhc_config_t config

USDHC configuration.

usdhc_capability_t capability

USDHC capability information.

usdhc_transfer_function_t transfer

USDHC transfer function.

WDOG: Watchdog Timer Driver

void WDOG_GetDefaultConfig(wdog_config_t *config)

Initializes the WDOG configuration structure.

This function initializes the WDOG configuration structure to default values. The default values are as follows.

wdogConfig->enableWdog = true;
wdogConfig->workMode.enableWait = true;
wdogConfig->workMode.enableStop = true;
wdogConfig->workMode.enableDebug = true;
wdogConfig->enableInterrupt = false;
wdogConfig->enablePowerdown = false;
wdogConfig->resetExtension = flase;
wdogConfig->timeoutValue = 0xFFU;
wdogConfig->interruptTimeValue = 0x04u;

See also

wdog_config_t

Parameters:

• config – Pointer to the WDOG configuration structure.

void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)

Initializes the WDOG.

This function initializes the WDOG. When called, the WDOG runs according to the configuration.

This is an example.

wdog_config_t config;
WDOG_GetDefaultConfig(&config);
config.timeoutValue = 0xffU;
config->interruptTimeValue = 0x04u;
WDOG_Init(wdog_base,&config);

Parameters:

• base – WDOG peripheral base address

• config – The configuration of WDOG

void WDOG_Deinit(WDOG_Type *base)

Shuts down the WDOG.

This function shuts down the WDOG. Watchdog Enable bit is a write one once only bit. It is not possible to clear this bit by a software write, once the bit is set. This bit(WDE) can be set/reset only in debug mode(exception).

static inline void WDOG_Enable(WDOG_Type *base)

Enables the WDOG module.

This function writes a value into the WDOG_WCR register to enable the WDOG. This is a write one once only bit. It is not possible to clear this bit by a software write, once the bit is set. only debug mode exception.

Parameters:

• base – WDOG peripheral base address

static inline void WDOG_Disable(WDOG_Type *base)

Disables the WDOG module.

This function writes a value into the WDOG_WCR register to disable the WDOG. This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. only debug mode exception

Parameters:

• base – WDOG peripheral base address

static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base)

Trigger the system software reset.

This function will write to the WCR[SRS] bit to trigger a software system reset. This bit will automatically resets to “1” after it has been asserted to “0”. Note: Calling this API will reset the system right now, please using it with more attention.

Parameters:

• base – WDOG peripheral base address

static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base)

Trigger an output assertion.

This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion. The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to assertion along with WDOG_B signal. Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please take more attention while calling it.

Parameters:

• base – WDOG peripheral base address

static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask)

Enables the WDOG interrupt.

This bit is a write once only bit. Once the software does a write access to this bit, it will get locked and cannot be reprogrammed until the next system reset assertion

Parameters:

• base – WDOG peripheral base address

• mask – The interrupts to enable The parameter can be combination of the following source if defined.

  • kWDOG_InterruptEnable

uint16_t WDOG_GetStatusFlags(WDOG_Type *base)

Gets the WDOG all reset status flags.

This function gets all reset status flags.

uint16_t status;
status = WDOG_GetStatusFlags (wdog_base);

See also

_wdog_status_flags

• true: a related status flag has been set.

• false: a related status flag is not set.

Parameters:

• base – WDOG peripheral base address

Returns:

State of the status flag: asserted (true) or not-asserted (false).

void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)

Clears the WDOG flag.

This function clears the WDOG status flag.

This is an example for clearing the interrupt flag.

WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);

Parameters:

• base – WDOG peripheral base address

• mask – The status flags to clear. The parameter could be any combination of the following values. kWDOG_TimeoutFlag

static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)

Sets the WDOG timeout value.

This function sets the timeout value. This function writes a value into WCR registers. The time-out value can be written at any point of time but it is loaded to the counter at the time when WDOG is enabled or after the service routine has been performed.

Parameters:

• base – WDOG peripheral base address

• timeoutCount – WDOG timeout value; count of WDOG clock tick.

static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)

Sets the WDOG interrupt count timeout value.

This function sets the interrupt count timeout value. This function writes a value into WIC registers which are wirte-once. This field is write once only. Once the software does a write access to this field, it will get locked and cannot be reprogrammed until the next system reset assertion.

Parameters:

• base – WDOG peripheral base address

• timeoutCount – WDOG timeout value; count of WDOG clock tick.

static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base)

Disable the WDOG power down enable bit.

This function disable the WDOG power down enable(PDE). This function writes a value into WMCR registers which are wirte-once. This field is write once only. Once software sets this bit it cannot be reset until the next system reset.

Parameters:

• base – WDOG peripheral base address

void WDOG_Refresh(WDOG_Type *base)

Refreshes the WDOG timer.

This function feeds the WDOG. This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.

Parameters:

• base – WDOG peripheral base address

FSL_WDOG_DRIVER_VERSION

Defines WDOG driver version.

WDOG_REFRESH_KEY

enum _wdog_interrupt_enable

WDOG interrupt configuration structure, default settings all disabled.

This structure contains the settings for all of the WDOG interrupt configurations.

Values:

enumerator kWDOG_InterruptEnable

WDOG timeout generates an interrupt before reset

enum _wdog_status_flags

WDOG status flags.

This structure contains the WDOG status flags for use in the WDOG functions.

Values:

enumerator kWDOG_RunningFlag

Running flag, set when WDOG is enabled

enumerator kWDOG_PowerOnResetFlag

Power On flag, set when reset is the result of a powerOnReset

enumerator kWDOG_TimeoutResetFlag

Timeout flag, set when reset is the result of a timeout

enumerator kWDOG_SoftwareResetFlag

Software flag, set when reset is the result of a software

enumerator kWDOG_InterruptFlag

interrupt flag,whether interrupt has occurred or not

typedef struct _wdog_work_mode wdog_work_mode_t

Defines WDOG work mode.

typedef struct _wdog_config wdog_config_t

Describes WDOG configuration structure.

struct _wdog_work_mode

#include <fsl_wdog.h>

Defines WDOG work mode.

Public Members

bool enableWait

If set to true, WDOG continues in wait mode

bool enableStop

If set to true, WDOG continues in stop mode

bool enableDebug

If set to true, WDOG continues in debug mode

struct _wdog_config

#include <fsl_wdog.h>

Describes WDOG configuration structure.

Public Members

bool enableWdog

Enables or disables WDOG

wdog_work_mode_t workMode

Configures WDOG work mode in debug stop and wait mode

bool enableInterrupt

Enables or disables WDOG interrupt

uint16_t timeoutValue

Timeout value

uint16_t interruptTimeValue

Interrupt count timeout value

bool softwareResetExtension

software reset extension

bool enablePowerDown

power down enable bit

bool enableTimeOutAssert

Enable WDOG_B timeout assertion.

XBARA: Inter-Peripheral Crossbar Switch

void XBARA_Init(XBARA_Type *base)

Initializes the XBARA module.

This function un-gates the XBARA clock.

Parameters:

• base – XBARA peripheral address.

void XBARA_Deinit(XBARA_Type *base)

Shuts down the XBARA module.

This function disables XBARA clock.

Parameters:

• base – XBARA peripheral address.

void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)

Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal.

This function connects the XBARA input to the selected XBARA output. If more than one XBARA module is available, only the inputs and outputs from the same module can be connected.

Example:

XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18);

Parameters:

• base – XBARA peripheral address.

• input – XBARA input signal.

• output – XBARA output signal.

uint32_t XBARA_GetStatusFlags(XBARA_Type *base)

Gets the active edge detection status.

This function gets the active edge detect status of all XBARA_OUTs. If the active edge occurs, the return value is asserted. When the interrupt or the DMA functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt or DMA request is asserted and 0 when the interrupt or DMA request has been cleared.

Parameters:

• base – XBARA peripheral address.

Returns:

the mask of these status flag bits.

void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)

Clears the edge detection status flags of relative mask.

Parameters:

• base – XBARA peripheral address.

• mask – the status flags to clear.

void XBARA_SetOutputSignalConfig(XBARA_Type *base, xbar_output_signal_t output, const xbara_control_config_t *controlConfig)

Configures the XBARA control register.

This function configures an XBARA control register. The active edge detection and the DMA/IRQ function on the corresponding XBARA output can be set.

Example:

xbara_control_config_t userConfig;
userConfig.activeEdge = kXBARA_EdgeRising;
userConfig.requestType = kXBARA_RequestInterruptEnalbe;
XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig);

Parameters:

• base – XBARA peripheral address.

• output – XBARA output number.

• controlConfig – Pointer to structure that keeps configuration of control register.

enum _xbara_active_edge

XBARA active edge for detection.

Values:

enumerator kXBARA_EdgeNone

Edge detection status bit never asserts.

enumerator kXBARA_EdgeRising

Edge detection status bit asserts on rising edges.

enumerator kXBARA_EdgeFalling

Edge detection status bit asserts on falling edges.

enumerator kXBARA_EdgeRisingAndFalling

Edge detection status bit asserts on rising and falling edges.

enum _xbar_request

Defines the XBARA DMA and interrupt configurations.

Values:

enumerator kXBARA_RequestDisable

Interrupt and DMA are disabled.

enumerator kXBARA_RequestDMAEnable

DMA enabled, interrupt disabled.

enumerator kXBARA_RequestInterruptEnable

Interrupt enabled, DMA disabled.

enum _xbara_status_flag_t

XBARA status flags.

This provides constants for the XBARA status flags for use in the XBARA functions.

Values:

enumerator kXBARA_EdgeDetectionOut0

XBAR_OUT0 active edge interrupt flag, sets when active edge detected.

enumerator kXBARA_EdgeDetectionOut1

XBAR_OUT1 active edge interrupt flag, sets when active edge detected.

enumerator kXBARA_EdgeDetectionOut2

XBAR_OUT2 active edge interrupt flag, sets when active edge detected.

enumerator kXBARA_EdgeDetectionOut3

XBAR_OUT3 active edge interrupt flag, sets when active edge detected.

typedef enum _xbara_active_edge xbara_active_edge_t

XBARA active edge for detection.

typedef enum _xbar_request xbara_request_t

Defines the XBARA DMA and interrupt configurations.

typedef enum _xbara_status_flag_t xbara_status_flag_t

XBARA status flags.

This provides constants for the XBARA status flags for use in the XBARA functions.

typedef struct XBARAControlConfig xbara_control_config_t

Defines the configuration structure of the XBARA control register.

This structure keeps the configuration of XBARA control register for one output. Control registers are available only for a few outputs. Not every XBARA module has control registers.

FSL_XBARA_DRIVER_VERSION

XBARA_SELx(base, output)

XBARA_WR_SELx_SELx(base, input, output)

kXBARA_RequestInterruptEnalbe

struct XBARAControlConfig

#include <fsl_xbara.h>

Defines the configuration structure of the XBARA control register.

This structure keeps the configuration of XBARA control register for one output. Control registers are available only for a few outputs. Not every XBARA module has control registers.

Public Members

xbara_active_edge_t activeEdge

Active edge to be detected.

xbara_request_t requestType

Selects DMA/Interrupt request.

XBARB: Inter-Peripheral Crossbar Switch

void XBARB_Init(XBARB_Type *base)

Initializes the XBARB module.

This function un-gates the XBARB clock.

Parameters:

• base – XBARB peripheral address.

void XBARB_Deinit(XBARB_Type *base)

Shuts down the XBARB module.

This function disables XBARB clock.

Parameters:

• base – XBARB peripheral address.

void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)

Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal.

This function configures which XBARB input is connected to the selected XBARB output. If more than one XBARB module is available, only the inputs and outputs from the same module can be connected.

Parameters:

• base – XBARB peripheral address.

• input – XBARB input signal.

• output – XBARB output signal.

FSL_XBARB_DRIVER_VERSION

XBARB_SELx(base, output)

XBARB_WR_SELx_SELx(base, input, output)

XECC: external error correction code controller

void XECC_Init(XECC_Type *base, const xecc_config_t *config)

XECC module initialization function.

Parameters:

• base – XECC base address.

• config – pointer to the XECC configuration structure.

void XECC_Deinit(XECC_Type *base)

Deinitializes the XECC.

Parameters:

• base – XECC base address.

void XECC_GetDefaultConfig(xecc_config_t *config)

Sets the XECC configuration structure to default values.

Parameters:

• config – pointer to the XECC configuration structure.

static inline uint32_t XECC_GetStatusFlags(XECC_Type *base)

Gets XECC status flags.

Parameters:

• base – XECC peripheral base address.

Returns:

XECC status flags.

static inline void XECC_ClearStatusFlags(XECC_Type *base, uint32_t mask)

XECC module clear interrupt status.

Parameters:

• base – XECC base address.

• mask – status to clear from xecc_interrupt_status_t.

static inline void XECC_EnableInterruptStatus(XECC_Type *base, uint32_t mask)

XECC module enable interrupt status.

Parameters:

• base – XECC base address.

• mask – status to enable from xecc_interrupt_status_enable_t.

static inline void XECC_DisableInterruptStatus(XECC_Type *base, uint32_t mask)

XECC module disable interrupt status.

Parameters:

• base – XECC base address.

• mask – status to disable from xecc_interrupt_status_enable_t.

static inline void XECC_EnableInterrupts(XECC_Type *base, uint32_t mask)

XECC module enable interrupt.

Parameters:

• base – XECC base address.

• mask – The interrupts to enable from xecc_interrupt_enable_t.

static inline void XECC_DisableInterrupts(XECC_Type *base, uint32_t mask)

XECC module disable interrupt.

Parameters:

• base – XECC base address.

• mask – The interrupts to disable from xecc_interrupt_enable_t.

static inline void XECC_WriteECCEnable(XECC_Type *base, bool enable)

XECC module write ECC function enable.

Parameters:

• base – XECC base address.

• enable – enable or disable.

static inline void XECC_ReadECCEnable(XECC_Type *base, bool enable)

XECC module read ECC function enable.

Parameters:

• base – XECC base address.

• enable – enable or disable.

static inline void XECC_SwapECCEnable(XECC_Type *base, bool enable)

XECC module swap data enable.

Parameters:

• base – XECC base address.

• enable – enable or disable.

status_t XECC_ErrorInjection(XECC_Type *base, uint32_t errordata, uint8_t erroreccdata)

XECC module error injection.

Parameters:

• base – XECC base address.

• errordata – error data.

• erroreccdata – ecc code.

Return values:

kStatus_Success. –

void XECC_GetSingleErrorInfo(XECC_Type *base, xecc_single_error_info_t *info)

XECC module get single error information.

Parameters:

• base – XECC base address.

• info – single error information.

void XECC_GetMultiErrorInfo(XECC_Type *base, xecc_multi_error_info_t *info)

XECC module get multiple error information.

Parameters:

• base – XECC base address.

• info – multiple error information.

FSL_XECC_DRIVER_VERSION

Driver version 2.0.0.

XECC interrupt configuration structure, , xecc_interrupt_enable_t.

This structure contains the settings for all of the XECC interrupt configurations.

Values:

enumerator kXECC_SingleErrorInterruptEnable

Single bit error interrupt enable

enumerator kXECC_MultiErrorInterruptEnable

Multiple bit error interrupt enable

enumerator kXECC_AllInterruptsEnable

all interrupts enable

XECC interrupt status configuration structure, xecc_interrupt_status_enable_t.

This structure contains the settings for all of the XECC interrupt status configurations.

Values:

enumerator kXECC_SingleErrorInterruptStatusEnable

Single bit error interrupt status enable

enumerator kXECC_MultiErrorInterruptStatusEnable

Multiple bits error interrupt status enable

enumerator kXECC_AllInterruptsStatusEnable

all interrupts enable

XECC status flags, xecc_interrupt_status_t.

This provides constants for the XECC status flags for use in the XECC functions.

Values:

enumerator kXECC_SingleErrorInterruptFlag

Single bit error interrupt happens on read data

enumerator kXECC_MultiErrorInterruptFlag

Multiple bits error interrupt happens on read data

enumerator kXECC_AllInterruptsFlag

all interrupts happens on read data

typedef struct _xecc_config xecc_config_t

XECC user configuration.

typedef struct _xecc_single_error_info xecc_single_error_info_t

XECC single error information, including single error address, ECC code, error data, error bit position and error bit field.

typedef struct _xecc_multi_error_info xecc_multi_error_info_t

XECC multiple error information, including multiple error address, ECC code, error data and error bit field.

struct _xecc_config

#include <fsl_xecc.h>

XECC user configuration.

Public Members

bool enableXECC

Enable the XECC function.

bool enableWriteECC

Enable write ECC function.

bool enableReadECC

Enable read ECC function.

bool enableSwap

Enable swap function. The minimum ECC region range is 4k, so the lower 12 bits of this register must be 0.

uint32_t Region0BaseAddress

ECC region 0 base address.

uint32_t Region0EndAddress

ECC region 0 end address.

uint32_t Region1BaseAddress

ECC region 1 base address.

uint32_t Region1EndAddress

ECC region 1 end address.

uint32_t Region2BaseAddress

ECC region 2 base address.

uint32_t Region2EndAddress

ECC region 2 end address.

uint32_t Region3BaseAddress

ECC region 3 base address.

uint32_t Region3EndAddress

ECC region 3 end address.

struct _xecc_single_error_info

#include <fsl_xecc.h>

XECC single error information, including single error address, ECC code, error data, error bit position and error bit field.

Public Members

uint32_t singleErrorAddress

Single error address

uint32_t singleErrorData

Single error read data

uint32_t singleErrorEccCode

Single error ECC code

uint32_t singleErrorBitPos

Single error bit postion

uint32_t singleErrorBitField

Single error bit field

struct _xecc_multi_error_info

#include <fsl_xecc.h>

XECC multiple error information, including multiple error address, ECC code, error data and error bit field.

Public Members

uint32_t multiErrorAddress

Multiple error address

uint32_t multiErrorData

Multiple error read data

uint32_t multiErrorEccCode

Multiple error ECC code

uint32_t multiErrorBitField

Single error bit field

XRDC2: Extended Resource Domain Controller 2

void XRDC2_SetGlobalValid(XRDC2_Type *base, bool valid)

Sets the XRDC2 global valid.

This function sets the XRDC2 global valid or invalid. When the XRDC2 is global invalid, all accesses from all bus masters to all slaves are allowed.

Parameters:

• base – XRDC2 peripheral base address.

• valid – True to valid XRDC2.

static inline uint8_t XRDC2_GetCurrentMasterDomainId(XRDC2_Type *base)

Gets the domain ID of the current bus master.

This function returns the domain ID of the current bus master.

Parameters:

• base – XRDC2 peripheral base address.

Returns:

Domain ID of current bus master.

static inline void XRDC2_SetGlobalConfigLock(XRDC2_Type *base, xrdc2_global_config_lock_t mode)

Set the global configuration lock mode.

Once change the lock mode, it could not be changed until next reset.

Parameters:

• base – XRDC2 peripheral base address.

• mode – The lock mode.

static inline uint8_t XRDC2_GetCurrentGlobalConfigLockOwnerDomainId(XRDC2_Type *base)

Gets the domain ID of global configuration lock owner.

Parameters:

• base – XRDC2 peripheral base address.

Returns:

Domain ID of the global configuration lock owner.

void XRDC2_GetDefaultMasterDomainAssignment(xrdc2_master_domain_assignment_t *assignment)

Gets the default master domain assignment.

This function sets the assignment as follows:

config->lock = false;
config->privilegeAttr = kXRDC2_MasterPrivilege;
config->secureAttr = kXRDC2_MasterSecure;
config->domainId = 0U;
config->mask = 0U;
config->match = 0U;

Parameters:

• assignment – Pointer to the assignment structure.

void XRDC2_SetMasterDomainAssignment(XRDC2_Type *base, xrdc2_master_t master, uint8_t assignIndex, const xrdc2_master_domain_assignment_t *assignment)

Sets the processor bus master domain assignment.

Parameters:

• base – XRDC2 peripheral base address.

• master – Which master to configure.

• assignIndex – Which assignment register to set.

• assignment – Pointer to the assignment structure.

static inline void XRDC2_LockMasterDomainAssignment(XRDC2_Type *base, xrdc2_master_t master, uint8_t assignIndex)

Locks the bus master domain assignment register.

This function locks the master domain assignment. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to lock. After it is locked, the register can’t be changed until next reset.

Parameters:

• base – XRDC2 peripheral base address.

• master – Which master to configure.

• assignIndex – Which assignment register to lock.

static inline void XRDC2_SetMasterDomainAssignmentValid(XRDC2_Type *base, xrdc2_master_t master, uint8_t assignIndex, bool valid)

Sets the master domain assignment as valid or invalid.

This function sets the master domain assignment as valid or invalid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to configure.

Parameters:

• base – XRDC2 peripheral base address.

• master – Which master to configure.

• assignIndex – Index for the domain assignment register.

• valid – True to set valid, false to set invalid.

void XRDC2_GetMemSlotAccessDefaultConfig(xrdc2_mem_slot_access_config_t *config)

Gets the default memory slot access configuration.

This function sets the assignment as follows:

config->lockMode = kXRDC2_AccessConfigLockDisabled;
config->policy[0] = kXRDC2_AccessPolicyNone;
config->policy[1] = kXRDC2_AccessPolicyNone;
...

Parameters:

• config – Pointer to the configuration.

void XRDC2_SetMemSlotAccessConfig(XRDC2_Type *base, xrdc2_mem_slot_t memSlot, const xrdc2_mem_slot_access_config_t *config)

Sets the memory slot access policy.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – Which memory slot descriptor to set.

• config – Pointer to the access policy configuration structure.

void XRDC2_SetMemSlotAccessValid(XRDC2_Type *base, xrdc2_mem_slot_t memSlot, bool valid)

Sets the memory slot descriptor as valid or invalid.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – Which memory slot descriptor to set.

• valid – True to set valid, false to set invalid.

void XRDC2_SetMemSlotAccessLockMode(XRDC2_Type *base, xrdc2_mem_slot_t memSlot, xrdc2_access_config_lock_t lockMode)

Sets the memory slot descriptor lock mode.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – Which memory slot descriptor to set.

• lockMode – The lock mode to set.

void XRDC2_SetMemSlotDomainAccessPolicy(XRDC2_Type *base, xrdc2_mem_slot_t memSlot, uint8_t domainId, xrdc2_access_policy_t policy)

Sets the memory slot access policy for specific domain.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

• domainId – The ID of the domain whose policy will be changed.

• policy – The access policy to set.

void XRDC2_EnableMemSlotExclAccessLock(XRDC2_Type *base, xrdc2_mem_slot_t memSlot, bool enable)

Enable or disable the memory slot exclusive access lock.

The lock must be enabled first before use. Once disabled, it could not be enabled until reset.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

• enable – True to enable, false to disable.

uint8_t XRDC2_GetMemSlotExclAccessLockDomainOwner(XRDC2_Type *base, xrdc2_mem_slot_t memSlot)

Get current memory slot exclusive access lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

Returns:

The domain ID of the lock owner.

status_t XRDC2_TryLockMemSlotExclAccess(XRDC2_Type *base, xrdc2_mem_slot_t memSlot)

Try to lock the memory slot exclusive access.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

Return values:

• kStatus_Fail – Failed to lock.

• kStatus_Success – Locked succussfully.

void XRDC2_LockMemSlotExclAccess(XRDC2_Type *base, xrdc2_mem_slot_t memSlot)

Lock the memory slot exclusive access using blocking method.

Note

This function must be called when the lock is not disabled.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

static inline void XRDC2_UnlockMemSlotExclAccess(XRDC2_Type *base, xrdc2_mem_slot_t memSlot)

Unlock the memory slot exclusive access.

Note

This function must be called by the lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

static inline void XRDC2_ForceMemSlotExclAccessLockRelease(XRDC2_Type *base, xrdc2_mem_slot_t memSlot)

Force the memory slot exclusive access lock release.

The master does not own the lock could call this function to force release the lock.

Parameters:

• base – XRDC2 peripheral base address.

• memSlot – The memory slot to operate.

void XRDC2_GetMemAccessDefaultConfig(xrdc2_mem_access_config_t *config)

Gets the default memory access configuration.

This function sets the assignment as follows:

config->startAddr = 0U;
config->endAddr = 0xFFFFFFFFU;
config->lockMode = kXRDC2_AccessConfigLockDisabled;
config->policy[0] = kXRDC2_AccessPolicyNone;
config->policy[1] = kXRDC2_AccessPolicyNone;
...

Parameters:

• config – Pointer to the configuration.

void XRDC2_SetMemAccessConfig(XRDC2_Type *base, xrdc2_mem_t mem, const xrdc2_mem_access_config_t *config)

Sets the memory region access policy.

Parameters:

• base – XRDC2 peripheral base address.

• mem – Which memory region descriptor to set.

• config – Pointer to the access policy configuration structure.

void XRDC2_SetMemAccessValid(XRDC2_Type *base, xrdc2_mem_t mem, bool valid)

Sets the memory region descriptor as valid or invalid.

Parameters:

• base – XRDC2 peripheral base address.

• mem – Which memory region descriptor to set.

• valid – True to set valid, false to set invalid.

void XRDC2_SetMemAccessLockMode(XRDC2_Type *base, xrdc2_mem_t mem, xrdc2_access_config_lock_t lockMode)

Sets the memory descriptor lock mode.

Parameters:

• base – XRDC2 peripheral base address.

• mem – Which memory descriptor to set.

• lockMode – The lock mode to set.

void XRDC2_SetMemDomainAccessPolicy(XRDC2_Type *base, xrdc2_mem_t mem, uint8_t domainId, xrdc2_access_policy_t policy)

Sets the memory region access policy for specific domain.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

• domainId – The ID of the domain whose policy will be changed.

• policy – The access policy to set.

void XRDC2_EnableMemExclAccessLock(XRDC2_Type *base, xrdc2_mem_t mem, bool enable)

Enable or disable the memory region exclusive access lock.

Once disabled, it could not be enabled until reset.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

• enable – True to enable, false to disable.

uint8_t XRDC2_GetMemExclAccessLockDomainOwner(XRDC2_Type *base, xrdc2_mem_t mem)

Get current memory region exclusive access lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

Returns:

The domain ID of the lock owner.

status_t XRDC2_TryLockMemExclAccess(XRDC2_Type *base, xrdc2_mem_t mem)

Try to lock the memory region exclusive access.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

Return values:

• kStatus_Fail – Failed to lock.

• kStatus_Success – Locked succussfully.

void XRDC2_LockMemExclAccess(XRDC2_Type *base, xrdc2_mem_t mem)

Lock the memory region exclusive access using blocking method.

Note

This function must be called when the lock is not disabled.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

void XRDC2_UnlockMemExclAccess(XRDC2_Type *base, xrdc2_mem_t mem)

Unlock the memory region exclusive access.

Note

This function must be called by the lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

void XRDC2_ForceMemExclAccessLockRelease(XRDC2_Type *base, xrdc2_mem_t mem)

Force the memory region exclusive access lock release.

The master does not own the lock could call this function to force release the lock.

Parameters:

• base – XRDC2 peripheral base address.

• mem – The memory region to operate.

void XRDC2_GetPeriphAccessDefaultConfig(xrdc2_periph_access_config_t *config)

Gets the default peripheral access configuration.

The default configuration is set as follows:

config->lockMode          = kXRDC2_AccessConfigLockWritable;
config->policy[0]         = kXRDC2_AccessPolicyNone;
config->policy[1]         = kXRDC2_AccessPolicyNone;
...
config->policy[15]        = kXRDC2_AccessPolicyNone;

Parameters:

• config – Pointer to the configuration structure.

void XRDC2_SetPeriphAccessConfig(XRDC2_Type *base, xrdc2_periph_t periph, const xrdc2_periph_access_config_t *config)

Sets the peripheral access policy.

Parameters:

• base – XRDC2 peripheral base address.

• periph – Which peripheral descriptor to set.

• config – Pointer to the access policy configuration structure.

void XRDC2_SetPeriphAccessValid(XRDC2_Type *base, xrdc2_periph_t periph, bool valid)

Sets the peripheral descriptor as valid or invalid.

Parameters:

• base – XRDC2 peripheral base address.

• periph – Which peripheral descriptor to set.

• valid – True to set valid, false to set invalid.

void XRDC2_SetPeriphAccessLockMode(XRDC2_Type *base, xrdc2_periph_t periph, xrdc2_access_config_lock_t lockMode)

Sets the peripheral descriptor lock mode.

Parameters:

• base – XRDC2 peripheral base address.

• periph – Which peripheral descriptor to set.

• lockMode – The lock mode to set.

void XRDC2_SetPeriphDomainAccessPolicy(XRDC2_Type *base, xrdc2_periph_t periph, uint8_t domainId, xrdc2_access_policy_t policy)

Sets the peripheral access policy for specific domain.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

• domainId – The ID of the domain whose policy will be changed.

• policy – The access policy to set.

void XRDC2_EnablePeriphExclAccessLock(XRDC2_Type *base, xrdc2_periph_t periph, bool enable)

Disable the peripheral exclusive access lock.

Once disabled, it could not be enabled until reset.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

• enable – True to enable, false to disable.

uint8_t XRDC2_GetPeriphExclAccessLockDomainOwner(XRDC2_Type *base, xrdc2_periph_t periph)

Get current peripheral exclusive access lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

Returns:

The domain ID of the lock owner.

status_t XRDC2_TryLockPeriphExclAccess(XRDC2_Type *base, xrdc2_periph_t periph)

Try to lock the peripheral exclusive access.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

Return values:

• kStatus_Fail – Failed to lock.

• kStatus_Success – Locked succussfully.

void XRDC2_LockPeriphExclAccess(XRDC2_Type *base, xrdc2_periph_t periph)

Lock the peripheral exclusive access using blocking method.

Note

This function must be called when the lock is not disabled.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

void XRDC2_UnlockPeriphExclAccess(XRDC2_Type *base, xrdc2_periph_t periph)

Unlock the peripheral exclusive access.

Note

This function must be called by the lock owner.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

void XRDC2_ForcePeriphExclAccessLockRelease(XRDC2_Type *base, xrdc2_periph_t periph)

Force the peripheral exclusive access lock release.

The master does not own the lock could call this function to force release the lock.

Parameters:

• base – XRDC2 peripheral base address.

• periph – The peripheral to operate.

enum _xrdc2_global_config_lock

Global configuration lock.

Values:

enumerator kXRDC2_GlobalConfigLockDisabled

Lock disabled, registers can be written by any domain.

enumerator kXRDC2_GlobalConfigLockDisabledUntilReset

Lock disabled until the next reset.

enumerator kXRDC2_GlobalConfigLockOwnerOnly

Lock enabled, only the lock owner can write.

enumerator kXRDC2_GlobalConfigLockEnabledUntilReset

Lock enabled, all registers are read only until the next reset.

enum _xrdc2_secure_attr

XRDC2 secure attribute, the register bit MDACi_MDAj_W0[SA], secure/nonsecure attribute output on a hit.

Values:

enumerator kXRDC2_MasterSecure

Use the bus master’s secure/nonsecure attribute directly.

enumerator kXRDC2_ForceSecure

Force the bus attribute for this master to secure.

enumerator kXRDC2_ForceNonSecure

Force the bus attribute for this master to non-secure.

enum _xrdc2_privilege_attr

XRDC2 privileged attribute, the register bit MDACi_MDAj_W0[PA], defines the privileged/user attribute on a hit.

Values:

enumerator kXRDC2_MasterPrivilege

Use the bus master’s attribute directly.

enumerator kXRDC2_ForceUser

Force the bus attribute for this master to user.

enumerator kXRDC2_ForcePrivilege

Force the bus attribute for this master to privileged.

enum _xrdc2_access_policy

XRDC2 domain access control policy.

Values:

enumerator kXRDC2_AccessPolicyNone

enumerator kXRDC2_AccessPolicyAlt1

enumerator kXRDC2_AccessPolicyAlt2

enumerator kXRDC2_AccessPolicyAlt3

enumerator kXRDC2_AccessPolicyAlt4

enumerator kXRDC2_AccessPolicyAlt5

enumerator kXRDC2_AccessPolicyAlt6

enumerator kXRDC2_AccessPolicyAll

enum _xrdc2_access_config_lock

Access configuration lock mode, the register field PDAC and MRGD LK2.

Values:

enumerator kXRDC2_AccessConfigLockDisabled

Entire PDACn/MRGDn/MSC can be written.

enumerator kXRDC2_AccessConfigLockDisabledUntilReset

Entire PDACn/MRGDn/MSC can be written until next reset.

enumerator kXRDC2_AccessConfigLockDomainXOnly

Domain x only write the DxACP field.

enumerator kXRDC2_AccessConfigLockEnabledUntilReset

PDACn/MRGDn/MSC is read-only until the next reset.

typedef enum _xrdc2_global_config_lock xrdc2_global_config_lock_t

Global configuration lock.

typedef enum _xrdc2_secure_attr xrdc2_secure_attr_t

XRDC2 secure attribute, the register bit MDACi_MDAj_W0[SA], secure/nonsecure attribute output on a hit.

typedef enum _xrdc2_privilege_attr xrdc2_privilege_attr_t

XRDC2 privileged attribute, the register bit MDACi_MDAj_W0[PA], defines the privileged/user attribute on a hit.

typedef struct _xrdc2_master_domain_assignment xrdc2_master_domain_assignment_t

Domain assignment for the bus master.

XRDC2 compares the bus master match input with the parameter xrdc2_master_domain_assignment_t::mask and xrdc2_master_domain_assignment_t::match in this structure. If hit, the domain ID, privilege attribute, and secure attribute are used for the access.

typedef enum _xrdc2_access_policy xrdc2_access_policy_t

XRDC2 domain access control policy.

typedef enum _xrdc2_access_config_lock xrdc2_access_config_lock_t

Access configuration lock mode, the register field PDAC and MRGD LK2.

typedef struct _xrdc2_periph_access_config xrdc2_periph_access_config_t

XRDC2 peripheral domain access control configuration.

typedef struct _xrdc2_mem_access_config xrdc2_mem_access_config_t

XRDC2 memory region domain access control configuration.

typedef struct _xrdc2_mem_slot_access_config xrdc2_mem_slot_access_config_t

XRDC2 memory slot domain access control configuration.

void XRDC2_Init(XRDC2_Type *base)

Initializes the XRDC2 module.

Parameters:

• base – XRDC2 peripheral base address.

void XRDC2_Deinit(XRDC2_Type *base)

De-initializes the XRDC2 module.

Parameters:

• base – XRDC2 peripheral base address.

FSL_XRDC2_DRIVER_VERSION

Driver version.

XRDC2_EAL_FORCE_RELEASE_MAGIC_0

XRDC2_EAL_FORCE_RELEASE_MAGIC_1

XRDC2_EAL_DISABLE

XRDC2_EAL_DISABLE_UNTIL_RESET

XRDC2_EAL_UNLOCKED

XRDC2_EAL_LOCKED

XRDC2_EAL_MASK

struct _xrdc2_master_domain_assignment

#include <fsl_xrdc2.h>

Domain assignment for the bus master.

XRDC2 compares the bus master match input with the parameter xrdc2_master_domain_assignment_t::mask and xrdc2_master_domain_assignment_t::match in this structure. If hit, the domain ID, privilege attribute, and secure attribute are used for the access.

Public Members

bool lock

Set true to lock the descriptor.

xrdc2_privilege_attr_t privilegeAttr

Privilege attribute.

xrdc2_secure_attr_t secureAttr

Secure attribute.

uint8_t domainId

Domain ID used when this descriptor hit.

uint16_t mask

Mask used for descriptor hit.

uint16_t match

Match used for descriptor hit.

struct _xrdc2_periph_access_config

#include <fsl_xrdc2.h>

XRDC2 peripheral domain access control configuration.

Public Members

xrdc2_access_config_lock_t lockMode

PDACn lock configuration.

xrdc2_access_policy_t policy[1]

Access policy for each domain.

struct _xrdc2_mem_access_config

#include <fsl_xrdc2.h>

XRDC2 memory region domain access control configuration.

Public Members

uint32_t startAddr

Memory region start address, should be 4k aligned.

uint32_t endAddr

Memory region end address, (endAddr + 1) should be 4k aligned.

xrdc2_access_config_lock_t lockMode

MRGDn lock configuration.

xrdc2_access_policy_t policy[1]

Access policy for each domain.

struct _xrdc2_mem_slot_access_config

#include <fsl_xrdc2.h>

XRDC2 memory slot domain access control configuration.

Public Members

xrdc2_access_config_lock_t lockMode

Descriptor lock configuration.

xrdc2_access_policy_t policy[1]

Access policy for each domain.