MIMXRT1189
ACMP: Analog Comparator Driver
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void ACMP_Init(CMP_Type *base, const acmp_config_t *config)
Initializes the ACMP.
The default configuration can be got by calling ACMP_GetDefaultConfig().
- Parameters:
base – ACMP peripheral base address.
config – Pointer to ACMP configuration structure.
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void ACMP_Deinit(CMP_Type *base)
Deinitializes the ACMP.
- Parameters:
base – ACMP peripheral base address.
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void ACMP_GetDefaultConfig(acmp_config_t *config)
Gets the default configuration for ACMP.
This function initializes the user configuration structure to default value. The default value are:
Example:
config->enableHighSpeed = false; config->enableInvertOutput = false; config->useUnfilteredOutput = false; config->enablePinOut = false; config->enableHysteresisBothDirections = false; config->hysteresisMode = kACMP_hysteresisMode0;
- Parameters:
config – Pointer to ACMP configuration structure.
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void ACMP_Enable(CMP_Type *base, bool enable)
Enables or disables the ACMP.
- Parameters:
base – ACMP peripheral base address.
enable – True to enable the ACMP.
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void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable)
Enables the link from CMP to DAC enable.
When this bit is set, the DAC enable/disable is controlled by the bit CMP_C0[EN] instead of CMP_C1[DACEN].
- Parameters:
base – ACMP peripheral base address.
enable – Enable the feature or not.
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void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config)
Sets the channel configuration.
Note that the plus/minus mux’s setting is only valid when the positive/negative port’s input isn’t from DAC but from channel mux.
Example:
acmp_channel_config_t configStruct = {0}; configStruct.positivePortInput = kACMP_PortInputFromDAC; configStruct.negativePortInput = kACMP_PortInputFromMux; configStruct.minusMuxInput = 1U; ACMP_SetChannelConfig(CMP0, &configStruct);
- Parameters:
base – ACMP peripheral base address.
config – Pointer to channel configuration structure.
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void ACMP_EnableDMA(CMP_Type *base, bool enable)
Enables or disables DMA.
- Parameters:
base – ACMP peripheral base address.
enable – True to enable DMA.
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void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config)
Configures the filter.
The filter can be enabled when the filter count is bigger than 1, the filter period is greater than 0 and the sample clock is from divided bus clock or the filter is bigger than 1 and the sample clock is from external clock. Detailed usage can be got from the reference manual.
Example:
acmp_filter_config_t configStruct = {0}; configStruct.filterCount = 5U; configStruct.filterPeriod = 200U; configStruct.enableSample = false; ACMP_SetFilterConfig(CMP0, &configStruct);
- Parameters:
base – ACMP peripheral base address.
config – Pointer to filter configuration structure.
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void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config)
Configures the internal DAC.
Example:
acmp_dac_config_t configStruct = {0}; configStruct.referenceVoltageSource = kACMP_VrefSourceVin1; configStruct.DACValue = 20U; configStruct.enableOutput = false; configStruct.workMode = kACMP_DACWorkLowSpeedMode; ACMP_SetDACConfig(CMP0, &configStruct);
- Parameters:
base – ACMP peripheral base address.
config – Pointer to DAC configuration structure. “NULL” is for disabling the feature.
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void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
Enables interrupts.
- Parameters:
base – ACMP peripheral base address.
mask – Interrupts mask. See “_acmp_interrupt_enable”.
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void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
Disables interrupts.
- Parameters:
base – ACMP peripheral base address.
mask – Interrupts mask. See “_acmp_interrupt_enable”.
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uint32_t ACMP_GetStatusFlags(CMP_Type *base)
Gets status flags.
- Parameters:
base – ACMP peripheral base address.
- Returns:
Status flags asserted mask. See “_acmp_status_flags”.
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void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
Clears status flags.
- Parameters:
base – ACMP peripheral base address.
mask – Status flags mask. See “_acmp_status_flags”.
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void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config)
Configure the discrete mode.
Configure the discrete mode when supporting 3V domain with 1.8V core.
- Parameters:
base – ACMP peripheral base address.
config – Pointer to configuration structure. See “acmp_discrete_mode_config_t”.
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void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config)
Get the default configuration for discrete mode setting.
- Parameters:
config – Pointer to configuration structure to be restored with the setting values.
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FSL_ACMP_DRIVER_VERSION
ACMP driver version 2.3.0.
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enum _acmp_interrupt_enable
Interrupt enable/disable mask.
Values:
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enumerator kACMP_OutputRisingInterruptEnable
Enable the interrupt when comparator outputs rising.
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enumerator kACMP_OutputFallingInterruptEnable
Enable the interrupt when comparator outputs falling.
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enumerator kACMP_OutputRisingInterruptEnable
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enum _acmp_status_flags
Status flag mask.
Values:
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enumerator kACMP_OutputRisingEventFlag
Rising-edge on compare output has occurred.
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enumerator kACMP_OutputFallingEventFlag
Falling-edge on compare output has occurred.
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enumerator kACMP_OutputAssertEventFlag
Return the current value of the analog comparator output.
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enumerator kACMP_OutputRisingEventFlag
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enum _acmp_offset_mode
Comparator hard block offset control.
If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.
Values:
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enumerator kACMP_OffsetLevel0
The comparator hard block output has level 0 offset internally.
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enumerator kACMP_OffsetLevel1
The comparator hard block output has level 1 offset internally.
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enumerator kACMP_OffsetLevel0
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enum _acmp_hysteresis_mode
Comparator hard block hysteresis control.
See chip data sheet to get the actual hysteresis value with each level.
Values:
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enumerator kACMP_HysteresisLevel0
Offset is level 0 and Hysteresis is level 0.
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enumerator kACMP_HysteresisLevel1
Offset is level 0 and Hysteresis is level 1.
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enumerator kACMP_HysteresisLevel2
Offset is level 0 and Hysteresis is level 2.
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enumerator kACMP_HysteresisLevel3
Offset is level 0 and Hysteresis is level 3.
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enumerator kACMP_HysteresisLevel0
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enum _acmp_reference_voltage_source
CMP Voltage Reference source.
Values:
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enumerator kACMP_VrefSourceVin1
Vin1 is selected as resistor ladder network supply reference Vin.
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enumerator kACMP_VrefSourceVin2
Vin2 is selected as resistor ladder network supply reference Vin.
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enumerator kACMP_VrefSourceVin1
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enum _acmp_port_input
Port input source.
Values:
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enumerator kACMP_PortInputFromDAC
Port input from the 8-bit DAC output.
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enumerator kACMP_PortInputFromMux
Port input from the analog 8-1 mux.
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enumerator kACMP_PortInputFromDAC
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enum _acmp_dac_work_mode
Internal DAC’s work mode.
Values:
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enumerator kACMP_DACWorkLowSpeedMode
DAC is selected to work in low speed and low power mode.
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enumerator kACMP_DACWorkHighSpeedMode
DAC is selected to work in high speed high power mode.
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enumerator kACMP_DACWorkLowSpeedMode
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typedef enum _acmp_offset_mode acmp_offset_mode_t
Comparator hard block offset control.
If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.
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typedef enum _acmp_hysteresis_mode acmp_hysteresis_mode_t
Comparator hard block hysteresis control.
See chip data sheet to get the actual hysteresis value with each level.
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typedef enum _acmp_reference_voltage_source acmp_reference_voltage_source_t
CMP Voltage Reference source.
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typedef enum _acmp_port_input acmp_port_input_t
Port input source.
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typedef enum _acmp_dac_work_mode acmp_dac_work_mode_t
Internal DAC’s work mode.
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typedef struct _acmp_config acmp_config_t
Configuration for ACMP.
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typedef struct _acmp_channel_config acmp_channel_config_t
Configuration for channel.
The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.
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typedef struct _acmp_filter_config acmp_filter_config_t
Configuration for filter.
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typedef struct _acmp_dac_config acmp_dac_config_t
Configuration for DAC.
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typedef struct _acmp_discrete_mode_config acmp_discrete_mode_config_t
Configuration for discrete mode.
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CMP_C0_CFx_MASK
The mask of status flags cleared by writing 1.
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struct _acmp_config
- #include <fsl_acmp.h>
Configuration for ACMP.
Public Members
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acmp_offset_mode_t offsetMode
Offset mode.
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acmp_hysteresis_mode_t hysteresisMode
Hysteresis mode.
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bool enableHighSpeed
Enable High Speed (HS) comparison mode.
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bool enableInvertOutput
Enable inverted comparator output.
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bool useUnfilteredOutput
Set compare output(COUT) to equal COUTA(true) or COUT(false).
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bool enablePinOut
The comparator output is available on the associated pin.
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acmp_offset_mode_t offsetMode
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struct _acmp_channel_config
- #include <fsl_acmp.h>
Configuration for channel.
The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.
Public Members
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acmp_port_input_t positivePortInput
Input source of the comparator’s positive port.
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uint32_t plusMuxInput
Plus mux input channel(0~7).
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acmp_port_input_t negativePortInput
Input source of the comparator’s negative port.
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uint32_t minusMuxInput
Minus mux input channel(0~7).
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acmp_port_input_t positivePortInput
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struct _acmp_filter_config
- #include <fsl_acmp.h>
Configuration for filter.
Public Members
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uint32_t filterCount
Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.
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uint32_t filterPeriod
Filter Sample Period. The divider to bus clock. Available range is 0-255.
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uint32_t filterCount
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struct _acmp_dac_config
- #include <fsl_acmp.h>
Configuration for DAC.
Public Members
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acmp_reference_voltage_source_t referenceVoltageSource
Supply voltage reference source.
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uint32_t DACValue
Value for DAC Output Voltage. Available range is 0-255.
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bool enableOutput
Enable the DAC output.
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acmp_reference_voltage_source_t referenceVoltageSource
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struct _acmp_discrete_mode_config
- #include <fsl_acmp.h>
Configuration for discrete mode.
Public Members
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bool enablePositiveChannelDiscreteMode
Positive Channel Continuous Mode Enable. By default, the continuous mode is used.
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bool enableNegativeChannelDiscreteMode
Negative Channel Continuous Mode Enable. By default, the continuous mode is used.
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bool enablePositiveChannelDiscreteMode
AOI: Crossbar AND/OR/INVERT Driver
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void AOI_Init(AOI_Type *base)
Initializes an AOI instance for operation.
This function un-gates the AOI clock.
- Parameters:
base – AOI peripheral address.
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void AOI_Deinit(AOI_Type *base)
Deinitializes an AOI instance for operation.
This function shutdowns AOI module.
- Parameters:
base – AOI peripheral address.
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void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
Gets the Boolean evaluation associated.
This function returns the Boolean evaluation associated.
Example:
aoi_event_config_t demoEventLogicStruct; AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
- Parameters:
base – AOI peripheral address.
event – Index of the event which will be set of type aoi_event_t.
config – Selected input configuration .
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void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
Configures an AOI event.
This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.
Example:
aoi_event_config_t demoEventLogicStruct; demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; demoEventLogicStruct.PT0BC = kAOI_InputSignal; demoEventLogicStruct.PT0CC = kAOI_LogicOne; demoEventLogicStruct.PT0DC = kAOI_LogicOne; demoEventLogicStruct.PT1AC = kAOI_LogicZero; demoEventLogicStruct.PT1BC = kAOI_LogicOne; demoEventLogicStruct.PT1CC = kAOI_LogicOne; demoEventLogicStruct.PT1DC = kAOI_LogicOne; demoEventLogicStruct.PT2AC = kAOI_LogicZero; demoEventLogicStruct.PT2BC = kAOI_LogicOne; demoEventLogicStruct.PT2CC = kAOI_LogicOne; demoEventLogicStruct.PT2DC = kAOI_LogicOne; demoEventLogicStruct.PT3AC = kAOI_LogicZero; demoEventLogicStruct.PT3BC = kAOI_LogicOne; demoEventLogicStruct.PT3CC = kAOI_LogicOne; demoEventLogicStruct.PT3DC = kAOI_LogicOne; AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
- Parameters:
base – AOI peripheral address.
event – Event which will be configured of type aoi_event_t.
eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.
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FSL_AOI_DRIVER_VERSION
Version 2.0.2.
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enum _aoi_input_config
AOI input configurations.
The selection item represents the Boolean evaluations.
Values:
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enumerator kAOI_LogicZero
Forces the input to logical zero.
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enumerator kAOI_InputSignal
Passes the input signal.
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enumerator kAOI_InvInputSignal
Inverts the input signal.
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enumerator kAOI_LogicOne
Forces the input to logical one.
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enumerator kAOI_LogicZero
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enum _aoi_event
AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
Values:
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enumerator kAOI_Event0
Event 0 index
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enumerator kAOI_Event1
Event 1 index
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enumerator kAOI_Event2
Event 2 index
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enumerator kAOI_Event3
Event 3 index
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enumerator kAOI_Event0
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typedef enum _aoi_input_config aoi_input_config_t
AOI input configurations.
The selection item represents the Boolean evaluations.
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typedef enum _aoi_event aoi_event_t
AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
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typedef struct _aoi_event_config aoi_event_config_t
AOI event configuration structure.
Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.
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AOI
AOI peripheral address
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struct _aoi_event_config
- #include <fsl_aoi.h>
AOI event configuration structure.
Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.
Public Members
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aoi_input_config_t PT0AC
Product term 0 input A
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aoi_input_config_t PT0BC
Product term 0 input B
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aoi_input_config_t PT0CC
Product term 0 input C
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aoi_input_config_t PT0DC
Product term 0 input D
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aoi_input_config_t PT1AC
Product term 1 input A
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aoi_input_config_t PT1BC
Product term 1 input B
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aoi_input_config_t PT1CC
Product term 1 input C
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aoi_input_config_t PT1DC
Product term 1 input D
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aoi_input_config_t PT2AC
Product term 2 input A
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aoi_input_config_t PT2BC
Product term 2 input B
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aoi_input_config_t PT2CC
Product term 2 input C
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aoi_input_config_t PT2DC
Product term 2 input D
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aoi_input_config_t PT3AC
Product term 3 input A
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aoi_input_config_t PT3BC
Product term 3 input B
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aoi_input_config_t PT3CC
Product term 3 input C
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aoi_input_config_t PT3DC
Product term 3 input D
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aoi_input_config_t PT0AC
ASRC: Asynchronous sample rate converter
ASRC Driver
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uint32_t ASRC_GetInstance(ASRC_Type *base)
Get instance number of the ASRC peripheral.
- Parameters:
base – ASRC base pointer.
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void ASRC_Init(ASRC_Type *base, uint32_t asrcPeripheralClock_Hz)
brief Initializes the asrc peripheral.
This API gates the asrc clock. The asrc module can’t operate unless ASRC_Init is called to enable the clock.
param base asrc base pointer. param asrcPeripheralClock_Hz peripheral clock of ASRC.
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void ASRC_Deinit(ASRC_Type *base)
De-initializes the ASRC peripheral.
This API gates the ASRC clock and disable ASRC module. The ASRC module can’t operate unless ASRC_Init
- Parameters:
base – ASRC base pointer.
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void ASRC_SoftwareReset(ASRC_Type *base)
Do software reset .
This software reset bit is self-clear bit, it will generate a software reset signal inside ASRC. After 9 cycles of the ASRC processing clock, this reset process will stop and this bit will cleared automatically.
- Parameters:
base – ASRC base pointer
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status_t ASRC_SetChannelPairConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)
ASRC configure channel pair.
- Parameters:
base – ASRC base pointer.
channelPair – index of channel pair, reference _asrc_channel_pair.
config – ASRC channel pair configuration pointer.
inputSampleRate – input audio data sample rate.
outputSampleRate – output audio data sample rate.
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uint32_t ASRC_GetOutSamplesSize(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)
Get output sample buffer size.
Note
This API is depends on the ASRC output configuration, should be called after the ASRC_SetChannelPairConfig.
- Parameters:
base – asrc base pointer.
channelPair – ASRC channel pair number.
inSampleRate – input sample rate.
outSampleRate – output sample rate.
inSamplesize – input sampleS size.
- Return values:
output – buffer size in byte.
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uint32_t ASRC_MapSamplesWidth(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *inWidth, uint32_t *outWidth)
Map register sample width to real sample width.
Note
This API is depends on the ASRC configuration, should be called after the ASRC_SetChannelPairConfig.
- Parameters:
base – asrc base pointer.
channelPair – asrc channel pair index.
inWidth – ASRC channel pair number.
outWidth – input sample rate.
- Return values:
input – sample mask value.
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uint32_t ASRC_GetRemainFifoSamples(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *buffer, uint32_t outSampleWidth, uint32_t remainSamples)
Get left samples in fifo.
- Parameters:
base – asrc base pointer.
channelPair – ASRC channel pair number.
buffer – input sample numbers.
outSampleWidth – output sample width.
remainSamples – output sample rate.
- Return values:
remain – samples number.
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static inline void ASRC_ModuleEnable(ASRC_Type *base, bool enable)
ASRC module enable.
- Parameters:
base – ASRC base pointer.
enable – true is enable, false is disable
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static inline void ASRC_ChannelPairEnable(ASRC_Type *base, asrc_channel_pair_t channelPair, bool enable)
ASRC enable channel pair.
- Parameters:
base – ASRC base pointer.
channelPair – channel pair mask value, reference _asrc_channel_pair_mask.
enable – true is enable, false is disable.
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static inline void ASRC_EnableInterrupt(ASRC_Type *base, uint32_t mask)
ASRC interrupt enable This function enable the ASRC interrupt with the provided mask.
- Parameters:
base – ASRC peripheral base address.
mask – The interrupts to enable. Logical OR of _asrc_interrupt_mask.
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static inline void ASRC_DisableInterrupt(ASRC_Type *base, uint32_t mask)
ASRC interrupt disable This function disable the ASRC interrupt with the provided mask.
- Parameters:
base – ASRC peripheral base address.
mask – The interrupts to disable. Logical OR of _asrc_interrupt_mask.
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static inline uint32_t ASRC_GetStatus(ASRC_Type *base)
Gets the ASRC status flag state.
- Parameters:
base – ASRC base pointer
- Returns:
ASRC Tx status flag value. Use the Status Mask to get the status value needed.
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static inline bool ASRC_GetChannelPairInitialStatus(ASRC_Type *base, asrc_channel_pair_t channel)
Gets the ASRC channel pair initialization state.
- Parameters:
base – ASRC base pointer
channel – ASRC channel pair.
- Returns:
ASRC Tx status flag value. Use the Status Mask to get the status value needed.
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static inline uint32_t ASRC_GetChannelPairFifoStatus(ASRC_Type *base, asrc_channel_pair_t channelPair)
Gets the ASRC channel A fifo a status flag state.
- Parameters:
base – ASRC base pointer
channelPair – ASRC channel pair.
- Returns:
ASRC channel pair a fifo status flag value. Use the Status Mask to get the status value needed.
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static inline void ASRC_ChannelPairWriteData(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t data)
Writes data into ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair.
data – Data needs to be written.
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static inline uint32_t ASRC_ChannelPairReadData(ASRC_Type *base, asrc_channel_pair_t channelPair)
Read data from ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair.
- Return values:
value – read from fifo.
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static inline uint32_t ASRC_GetInputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)
Get input data fifo address. Note: ASRC fifo width is 24bit.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair.
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static inline uint32_t ASRC_GetOutputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)
Get output data fifo address. Note: ASRC fifo width is 24bit.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair.
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status_t ASRC_SetIdealRatioConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inputSampleRate, uint32_t outputSampleRate)
ASRC configure ideal ratio. The ideal ratio should be used when input clock source is not avalible.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair.
inputSampleRate – input audio data sample rate.
outputSampleRate – output audio data sample rate.
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status_t ASRC_TransferSetChannelPairConfig(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)
ASRC configure channel pair.
- Parameters:
base – ASRC base pointer.
handle – ASRC transactional handle pointer.
config – ASRC channel pair configuration pointer.
inputSampleRate – input audio data sample rate.
outputSampleRate – output audio data sample rate.
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void ASRC_TransferCreateHandle(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_t channelPair, asrc_transfer_callback_t inCallback, asrc_transfer_callback_t outCallback, void *userData)
Initializes the ASRC handle.
This function initializes the handle for the ASRC transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – ASRC base pointer
handle – ASRC handle pointer.
channelPair – ASRC channel pair.
inCallback – Pointer to the user callback function.
outCallback – Pointer to the user callback function.
userData – User parameter passed to the callback function
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status_t ASRC_TransferNonBlocking(ASRC_Type *base, asrc_handle_t *handle, asrc_transfer_t *xfer)
Performs an interrupt non-blocking convert on asrc.
Note
This API returns immediately after the transfer initiates, application should check the wait and check the callback status.
- Parameters:
base – asrc base pointer.
handle – Pointer to the asrc_handle_t structure which stores the transfer state.
xfer – Pointer to the ASRC_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_ASRCBusy – Previous receive still not finished.
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status_t ASRC_TransferBlocking(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_transfer_t *xfer)
Performs an blocking convert on asrc.
Note
This API returns immediately after the convert finished.
- Parameters:
base – asrc base pointer.
channelPair – channel pair index.
xfer – Pointer to the ASRC_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
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status_t ASRC_TransferGetConvertedCount(ASRC_Type *base, asrc_handle_t *handle, size_t *count)
Get converted byte count.
- Parameters:
base – ASRC base pointer.
handle – Pointer to the asrc_handle_t structure which stores the transfer state.
count – Bytes count sent.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_ASRCIdle – There is not a non-blocking transaction currently in progress.
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void ASRC_TransferAbortConvert(ASRC_Type *base, asrc_handle_t *handle)
Aborts the current convert.
Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – ASRC base pointer.
handle – Pointer to the asrc_handle_t structure which stores the transfer state.
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void ASRC_TransferTerminateConvert(ASRC_Type *base, asrc_handle_t *handle)
Terminate all ASRC convert.
This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortConvert.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
-
void ASRC_TransferHandleIRQ(ASRC_Type *base, asrc_handle_t *handle)
ASRC convert interrupt handler.
- Parameters:
base – ASRC base pointer.
handle – Pointer to the asrc_handle_t structure.
-
FSL_ASRC_DRIVER_VERSION
Version 2.1.3
ASRC return status .
Values:
-
enumerator kStatus_ASRCIdle
ASRC is idle.
-
enumerator kStatus_ASRCInIdle
ASRC in is idle.
-
enumerator kStatus_ASRCOutIdle
ASRC out is idle.
-
enumerator kStatus_ASRCBusy
ASRC is busy.
-
enumerator kStatus_ASRCInvalidArgument
ASRC invalid argument.
-
enumerator kStatus_ASRCClockConfigureFailed
ASRC clock configure failed
-
enumerator kStatus_ASRCChannelPairConfigureFailed
ASRC clock configure failed
-
enumerator kStatus_ASRCConvertError
ASRC clock configure failed
-
enumerator kStatus_ASRCNotSupport
ASRC not support
-
enumerator kStatus_ASRCQueueFull
ASRC queue is full
-
enumerator kStatus_ASRCOutQueueIdle
ASRC out queue is idle
-
enumerator kStatus_ASRCInQueueIdle
ASRC in queue is idle
-
enumerator kStatus_ASRCIdle
-
enum _asrc_channel_pair
ASRC channel pair mask.
Values:
-
enumerator kASRC_ChannelPairA
channel pair A value
-
enumerator kASRC_ChannelPairB
channel pair B value
-
enumerator kASRC_ChannelPairC
channel pair C value
-
enumerator kASRC_ChannelPairA
ASRC support sample rate .
Values:
-
enumerator kASRC_SampleRate_8000HZ
asrc sample rate 8KHZ
-
enumerator kASRC_SampleRate_11025HZ
asrc sample rate 11.025KHZ
-
enumerator kASRC_SampleRate_12000HZ
asrc sample rate 12KHZ
-
enumerator kASRC_SampleRate_16000HZ
asrc sample rate 16KHZ
-
enumerator kASRC_SampleRate_22050HZ
asrc sample rate 22.05KHZ
-
enumerator kASRC_SampleRate_24000HZ
asrc sample rate 24KHZ
-
enumerator kASRC_SampleRate_30000HZ
asrc sample rate 30KHZ
-
enumerator kASRC_SampleRate_32000HZ
asrc sample rate 32KHZ
-
enumerator kASRC_SampleRate_44100HZ
asrc sample rate 44.1KHZ
-
enumerator kASRC_SampleRate_48000HZ
asrc sample rate 48KHZ
-
enumerator kASRC_SampleRate_64000HZ
asrc sample rate 64KHZ
-
enumerator kASRC_SampleRate_88200HZ
asrc sample rate 88.2KHZ
-
enumerator kASRC_SampleRate_96000HZ
asrc sample rate 96KHZ
-
enumerator kASRC_SampleRate_128000HZ
asrc sample rate 128KHZ
-
enumerator kASRC_SampleRate_176400HZ
asrc sample rate 176.4KHZ
-
enumerator kASRC_SampleRate_192000HZ
asrc sample rate 192KHZ
-
enumerator kASRC_SampleRate_8000HZ
The ASRC interrupt enable flag .
Values:
-
enumerator kASRC_FPInWaitStateInterruptEnable
FP in wait state mask
-
enumerator kASRC_OverLoadInterruptMask
overload interrupt mask
-
enumerator kASRC_DataOutputCInterruptMask
data output c interrupt mask
-
enumerator kASRC_DataOutputBInterruptMask
data output b interrupt mask
-
enumerator kASRC_DataOutputAInterruptMask
data output a interrupt mask
-
enumerator kASRC_DataInputCInterruptMask
data input c interrupt mask
-
enumerator kASRC_DataInputBInterruptMask
data input b interrupt mask
-
enumerator kASRC_DataInputAInterruptMask
data input a interrupt mask
-
enumerator kASRC_FPInWaitStateInterruptEnable
The ASRC interrupt status .
Values:
-
enumerator kASRC_StatusDSLCounterReady
DSL counter
-
enumerator kASRC_StatusTaskQueueOverLoad
task queue overload
-
enumerator kASRC_StatusPairCOutputOverLoad
pair c output overload
-
enumerator kASRC_StatusPairBOutputOverLoad
pair b output overload
-
enumerator kASRC_StatusPairAOutputOverLoad
pair a output overload
-
enumerator kASRC_StatusPairCInputOverLoad
pair c input overload
-
enumerator kASRC_StatusPairBInputOverLoad
pair b input overload
-
enumerator kASRC_StatusPairAInputOverLoad
pair a input overload
-
enumerator kASRC_StatusPairCOutputOverflow
pair c output overflow
-
enumerator kASRC_StatusPairBOutputOverflow
pair b output overflow
-
enumerator kASRC_StatusPairAOutputOverflow
pair a output overflow
-
enumerator kASRC_StatusPairCInputUnderflow
pair c input underflow
-
enumerator kASRC_StatusPairBInputUnderflow
pair b input under flow
-
enumerator kASRC_StatusPairAInputUnderflow
pair a input underflow
-
enumerator kASRC_StatusFPInWaitState
FP in wait state
-
enumerator kASRC_StatusOverloadError
overload error
-
enumerator kASRC_StatusInputError
input error status
-
enumerator kASRC_StatusOutputError
output error status
-
enumerator kASRC_StatusPairCOutputReady
pair c output ready
-
enumerator kASRC_StatusPairBOutputReady
pair b output ready
-
enumerator kASRC_StatusPairAOutputReady
pair a output ready
-
enumerator kASRC_StatusPairCInputReady
pair c input ready
-
enumerator kASRC_StatusPairBInputReady
pair b input ready
-
enumerator kASRC_StatusPairAInputReady
pair a input ready
-
enumerator kASRC_StatusPairAInterrupt
pair A interrupt
-
enumerator kASRC_StatusPairBInterrupt
pair B interrupt
-
enumerator kASRC_StatusPairCInterrupt
pair C interrupt
-
enumerator kASRC_StatusDSLCounterReady
ASRC channel pair status .
Values:
-
enumerator kASRC_OutputFifoNearFull
channel pair output fifo near full
-
enumerator kASRC_InputFifoNearEmpty
channel pair input fifo near empty
-
enumerator kASRC_OutputFifoNearFull
-
enum _asrc_ratio
ASRC ideal ratio.
Values:
-
enumerator kASRC_RatioNotUsed
ideal ratio not used
-
enumerator kASRC_RatioUseInternalMeasured
ideal ratio use internal measure ratio, can be used for real time streaming audio
-
enumerator kASRC_RatioUseIdealRatio
ideal ratio use manual configure ratio, can be used for the non-real time streaming audio
-
enumerator kASRC_RatioNotUsed
-
enum _asrc_audio_channel
Number of channels in audio data.
Values:
-
enumerator kASRC_ChannelsNumber1
channel number is 1
-
enumerator kASRC_ChannelsNumber2
channel number is 2
-
enumerator kASRC_ChannelsNumber3
channel number is 3
-
enumerator kASRC_ChannelsNumber4
channel number is 4
-
enumerator kASRC_ChannelsNumber5
channel number is 5
-
enumerator kASRC_ChannelsNumber6
channel number is 6
-
enumerator kASRC_ChannelsNumber7
channel number is 7
-
enumerator kASRC_ChannelsNumber8
channel number is 8
-
enumerator kASRC_ChannelsNumber9
channel number is 9
-
enumerator kASRC_ChannelsNumber10
channel number is 10
-
enumerator kASRC_ChannelsNumber1
-
enum _asrc_data_width
data width
Values:
-
enumerator kASRC_DataWidth24Bit
data width 24bit
-
enumerator kASRC_DataWidth16Bit
data width 16bit
-
enumerator kASRC_DataWidth8Bit
data width 8bit
-
enumerator kASRC_DataWidth24Bit
-
enum _asrc_data_align
data alignment
Values:
-
enumerator kASRC_DataAlignMSB
data alignment MSB
-
enumerator kASRC_DataAlignLSB
data alignment LSB
-
enumerator kASRC_DataAlignMSB
-
enum _asrc_sign_extension
sign extension
Values:
-
enumerator kASRC_NoSignExtension
no sign extension
-
enumerator kASRC_SignExtension
sign extension
-
enumerator kASRC_NoSignExtension
-
typedef enum _asrc_channel_pair asrc_channel_pair_t
ASRC channel pair mask.
-
typedef enum _asrc_ratio asrc_ratio_t
ASRC ideal ratio.
-
typedef enum _asrc_audio_channel asrc_audio_channel_t
Number of channels in audio data.
-
typedef enum _asrc_data_width asrc_data_width_t
data width
-
typedef enum _asrc_data_align asrc_data_align_t
data alignment
-
typedef enum _asrc_sign_extension asrc_sign_extension_t
sign extension
-
typedef struct _asrc_channel_pair_config asrc_channel_pair_config_t
asrc channel pair configuation
-
typedef struct _asrc_transfer asrc_transfer_t
SAI transfer structure.
-
typedef struct _asrc_handle asrc_handle_t
asrc handler
-
typedef void (*asrc_transfer_callback_t)(ASRC_Type *base, asrc_handle_t *handle, status_t status, void *userData)
ASRC transfer callback prototype.
-
typedef struct _asrc_in_handle asrc_in_handle_t
asrc in handler
-
typedef struct _asrc_out_handle asrc_out_handle_t
output handler
-
ASRC_XFER_QUEUE_SIZE
ASRC transfer queue size, user can refine it according to use case.
-
FSL_ASRC_CHANNEL_PAIR_COUNT
ASRC channel pair count.
-
FSL_ASRC_CHANNEL_PAIR_FIFO_DEPTH
ASRC FIFO depth.
-
ASRC_ASRCTR_AT_MASK(index)
ASRC register access macro.
-
ASRC_ASRCTR_RATIO_MASK(index)
-
ASRC_ASRCTR_RATIO(ratio, index)
-
ASRC_ASRIER_INPUT_INTERRUPT_MASK(index)
-
ASRC_ASRIER_OUTPUTPUT_INTERRUPT_MASK(index)
-
ASRC_ASRCNCR_CHANNEL_COUNTER_MASK(index)
-
ASRC_ASRCNCR_CHANNEL_COUNTER(counter, index)
-
ASRC_ASRCFG_PRE_MODE_MASK(index)
-
ASRC_ASRCFG_PRE_MODE(mode, index)
-
ASRC_ASRCFG_POST_MODE_MASK(index)
-
ASRC_ASRCFG_POST_MODE(mode, index)
-
ASRC_ASRCFG_INIT_DONE_MASK(index)
-
ASRC_ASRCSR_INPUT_CLOCK_SOURCE_MASK(index)
-
ASRC_ASRCSR_INPUT_CLOCK_SOURCE(source, index)
-
ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE_MASK(index)
-
ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE(source, index)
-
ASRC_ASRCDR_INPUT_PRESCALER_MASK(index)
-
ASRC_ASRCDR_INPUT_PRESCALER(prescaler, index)
-
ASRC_ASRCDR_INPUT_DIVIDER_MASK(index)
-
ASRC_ASRCDR_INPUT_DIVIDER(divider, index)
-
ASRC_ASRCDR_OUTPUT_PRESCALER_MASK(index)
-
ASRC_ASRCDR_OUTPUT_PRESCALER(prescaler, index)
-
ASRC_ASRCDR_OUTPUT_DIVIDER_MASK(index)
-
ASRC_ASRCDR_OUTPUT_DIVIDER(divider, index)
-
ASCR_ASRCDR_OUTPUT_CLOCK_DIVIDER_PRESCALER(value, index)
-
ASCR_ASRCDR_INPUT_CLOCK_DIVIDER_PRESCALER(value, index)
-
ASRC_IDEAL_RATIO_HIGH(base, index)
-
ASRC_IDEAL_RATIO_LOW(base, index)
-
ASRC_ASRMCR(base, index)
-
ASRC_ASRMCR1(base, index)
-
ASRC_ASRDI(base, index)
-
ASRC_ASRDO(base, index)
-
ASRC_ASRDI_ADDR(base, index)
-
ASRC_ASRDO_ADDR(base, index)
-
ASRC_ASRFST_ADDR(base, index)
-
ASRC_GET_CHANNEL_COUNTER(base, index)
-
struct _asrc_channel_pair_config
- #include <fsl_asrc.h>
asrc channel pair configuation
Public Members
-
asrc_audio_channel_t audioDataChannels
audio data channel numbers
-
asrc_clock_source_t inClockSource
input clock source, reference the clock source definition in SOC header file
-
uint32_t inSourceClock_Hz
input source clock frequency
-
asrc_clock_source_t outClockSource
output clock source, reference the clock source definition in SOC header file
-
uint32_t outSourceClock_Hz
output source clock frequency
-
asrc_ratio_t sampleRateRatio
sample rate ratio type
-
asrc_data_width_t inDataWidth
input data width
-
asrc_data_align_t inDataAlign
input data alignment
-
asrc_data_width_t outDataWidth
output data width
-
asrc_data_align_t outDataAlign
output data alignment
-
asrc_sign_extension_t outSignExtension
output extension
-
uint8_t outFifoThreshold
output fifo threshold
-
uint8_t inFifoThreshold
input fifo threshold
-
bool bufStallWhenFifoEmptyFull
stall Pair A conversion in case of Buffer near empty full condition
-
asrc_audio_channel_t audioDataChannels
-
struct _asrc_transfer
- #include <fsl_asrc.h>
SAI transfer structure.
Public Members
-
void *inData
Data address to convert.
-
size_t inDataSize
input data size.
-
void *outData
Data address to store converted data
-
size_t outDataSize
output data size.
-
void *inData
-
struct _asrc_in_handle
- #include <fsl_asrc.h>
asrc in handler
Public Members
-
asrc_transfer_callback_t callback
Callback function called at convert complete
-
uint32_t sampleWidth
data width
-
uint32_t sampleMask
data mask
-
uint32_t fifoThreshold
fifo threshold
-
uint8_t *asrcQueue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSamples[(4U)]
Data bytes need to convert
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
asrc_transfer_callback_t callback
-
struct _asrc_out_handle
- #include <fsl_asrc.h>
output handler
Public Members
-
asrc_transfer_callback_t callback
Callback function called at convert complete
-
uint32_t sampleWidth
data width
-
uint32_t fifoThreshold
fifo threshold
-
uint8_t *asrcQueue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSamples[(4U)]
Data bytes need to convert
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
asrc_transfer_callback_t callback
-
struct _asrc_handle
- #include <fsl_asrc.h>
ASRC handle structure.
Public Members
-
ASRC_Type *base
base address
-
uint32_t state
Transfer status
-
void *userData
Callback parameter passed to callback function
-
asrc_audio_channel_t audioDataChannels
audio channel number
-
asrc_channel_pair_t channelPair
channel pair mask
-
asrc_in_handle_t in
asrc input handler
-
asrc_out_handle_t out
asrc output handler
-
ASRC_Type *base
ASRC EDMA Driver
-
void ASRC_TransferInCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *inDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)
Initializes the ASRC IN eDMA handle.
This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair
handle – ASRC eDMA handle pointer.
callback – Pointer to user callback function.
inDmaHandle – DMA handler for ASRC in.
periphConfig – peripheral configuration.
userData – User parameter passed to the callback function.
-
void ASRC_TransferOutCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *outDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)
Initializes the ASRC OUT eDMA handle.
This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.
- Parameters:
base – ASRC base pointer.
channelPair – ASRC channel pair
handle – ASRC eDMA handle pointer.
callback – Pointer to user callback function.
outDmaHandle – DMA handler for ASRC out.
periphConfig – peripheral configuration.
userData – User parameter passed to the callback function.
-
status_t ASRC_TransferSetChannelPairConfigEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_config_t *asrcConfig, uint32_t inSampleRate, uint32_t outSampleRate)
Configures the ASRC P2P channel pair.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
asrcConfig – asrc configurations.
inSampleRate – ASRC input sample rate.
outSampleRate – ASRC output sample rate.
-
uint32_t ASRC_GetOutSamplesSizeEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)
Get output sample buffer size can be transferred by edma.
Note
This API is depends on the ASRC output configuration, should be called after the ASRC_TransferSetChannelPairConfigEDMA.
- Parameters:
base – asrc base pointer.
handle – ASRC channel pair edma handle.
inSampleRate – input sample rate.
outSampleRate – output sample rate.
inSamplesize – input sampleS size.
- Return values:
output – buffer size in byte.
-
status_t ASRC_TransferEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_transfer_t *xfer)
Performs a non-blocking ASRC m2m convert using EDMA.
Note
This interface returns immediately after the transfer initiates.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
xfer – Pointer to the DMA transfer structure.
- Return values:
kStatus_Success – Start a ASRC eDMA send successfully.
kStatus_InvalidArgument – The input argument is invalid.
kStatus_ASRCQueueFull – ASRC EDMA driver queue is full.
-
void ASRC_TransferInAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
Aborts a ASRC IN transfer using eDMA.
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
-
void ASRC_TransferOutAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
Aborts a ASRC OUT transfer using eDMA.
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
-
void ASRC_TransferInTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
Terminate In ASRC Convert.
This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
-
void ASRC_TransferOutTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
Terminate Out ASRC Convert.
This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.
- Parameters:
base – ASRC base pointer.
handle – ASRC eDMA handle pointer.
-
FSL_ASRC_EDMA_DRIVER_VERSION
Version 2.2.0
-
typedef struct _asrc_edma_handle asrc_edma_handle_t
-
typedef void (*asrc_edma_callback_t)(ASRC_Type *base, asrc_edma_handle_t *handle, status_t status, void *userData)
ASRC eDMA transfer callback function for finish and error.
-
typedef void (*asrc_start_peripheral_t)(bool start)
ASRC trigger peripheral function pointer.
-
typedef struct _asrc_p2p_edma_config asrc_p2p_edma_config_t
destination peripheral configuration
-
typedef struct _asrc_in_edma_handle asrc_in_edma_handle_t
@ brief asrc in edma handler
-
typedef struct _asrc_out_edma_handle asrc_out_edma_handle_t
@ brief asrc out edma handler
-
ASRC_XFER_IN_QUEUE_SIZE
ASRC IN edma QUEUE size.
<
-
ASRC_XFER_OUT_QUEUE_SIZE
-
struct _asrc_p2p_edma_config
- #include <fsl_asrc_edma.h>
destination peripheral configuration
Public Members
-
asrc_start_peripheral_t startPeripheral
trigger peripheral start
-
asrc_start_peripheral_t startPeripheral
-
struct _asrc_in_edma_handle
- #include <fsl_asrc_edma.h>
@ brief asrc in edma handler
Public Members
-
edma_handle_t *inDmaHandle
DMA handler for ASRC in
-
uint8_t tcd[(4U + 1U) * sizeof(edma_tcd_t)]
TCD pool for eDMA send.
-
uint32_t sampleWidth
input data width
-
uint32_t fifoThreshold
ASRC input fifo threshold
-
uint32_t *asrcQueue[4U]
Transfer queue storing queued transfer.
-
size_t transferSize[4U]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer.
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint32_t state
Internal state for ASRC eDMA transfer
-
const asrc_p2p_edma_config_t *peripheralConfig
peripheral configuration pointer
-
edma_handle_t *inDmaHandle
-
struct _asrc_out_edma_handle
- #include <fsl_asrc_edma.h>
@ brief asrc out edma handler
Public Members
-
edma_handle_t *outDmaHandle
DMA handler for ASRC out
-
uint8_t tcd[(((4U) * 2U) + 1U) * sizeof(edma_tcd_t)]
TCD pool for eDMA send.
-
uint32_t sampleWidth
output data width
-
uint32_t fifoThreshold
ASRC output fifo threshold
-
uint32_t *asrcQueue[((4U) * 2U)]
Transfer queue storing queued transfer.
-
size_t transferSize[((4U) * 2U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer.
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint32_t state
Internal state for ASRC eDMA transfer
-
const asrc_p2p_edma_config_t *peripheralConfig
peripheral configuration pointer
-
edma_handle_t *outDmaHandle
-
struct _asrc_edma_handle
- #include <fsl_asrc_edma.h>
ASRC DMA transfer handle.
Public Members
-
asrc_in_edma_handle_t in
asrc in handler
-
asrc_out_edma_handle_t out
asrc out handler
-
asrc_channel_pair_t channelPair
channel pair
-
void *userData
User callback parameter
-
asrc_edma_callback_t callback
Callback for users while transfer finish or error occurs
-
asrc_in_edma_handle_t in
Battery-Backed Non-Secure Module
-
void BBNSM_Init(BBNSM_Type *base)
Init the BBNSM section.
- Parameters:
base – BBNSM peripheral base address
-
void BBNSM_Deinit(BBNSM_Type *base)
Deinit the BBNSM section.
- Parameters:
base – BBNSM peripheral base address
-
FSL_BBNSM_DRIVER_VERSION
Version 2.0.0
-
enum _bbnsm_interrupts
List of BBNSM interrupts.
Values:
-
enumerator kBBNSM_RTC_AlarmInterrupt
RTC time alarm interrupt
-
enumerator kBBNSM_RTC_RolloverInterrupt
RTC rollover interrupt
-
enumerator kBBNSM_RTC_AlarmInterrupt
-
enum _bbnsm_status_flags
List of BBNSM flags.
Values:
-
enumerator kBBNSM_RTC_AlarmInterruptFlag
RTC time alarm interrupt flag
-
enumerator kBBNSM_RTC_RolloverInterruptFlag
RTC rollover interrupt flag
-
enumerator kBBNSM_PWR_ON_InterruptFlag
power on interrupt flag
-
enumerator kBBNSM_PWR_OFF_InterruptFlag
power off interrupt flag
-
enumerator kBBNSM_EMG_OFF_InterruptFlag
emergency power off interrupt flag
-
enumerator kBBNSM_RTC_AlarmInterruptFlag
-
typedef enum _bbnsm_interrupts bbnsm_interrupts_t
List of BBNSM interrupts.
-
typedef enum _bbnsm_status_flags bbnsm_status_flags_t
List of BBNSM flags.
-
typedef struct _bbnsm_rtc_config bbnsm_rtc_config_t
BBNSM config structure.
This structure holds the configuration settings for the BBNSM peripheral. To initialize this structure to reasonable defaults, call the BBNSM_RTC_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
-
void BBNSM_RTC_Init(BBNSM_Type *base, const bbnsm_rtc_config_t *config)
Ungates the BBNSM clock and configures the peripheral for basic operation.
Note
This API should be called at the beginning of the application using the BBNSM driver.
- Parameters:
base – BBNSM peripheral base address
config – Pointer to the user’s BBNSM rtc configuration structure.
-
void BBNSM_RTC_Deinit(BBNSM_Type *base)
Stops the RTC timer.
- Parameters:
base – BBNSM peripheral base address
-
void BBNSM_RTC_GetDefaultConfig(bbnsm_rtc_config_t *config)
Fills in the BBNSM RTC config struct with the default settings.
The default values are as follows.
config->rtccalenable = false; config->rtccalvalue = 0U;
- Parameters:
config – Pointer to the user’s BBNSM configuration structure.
-
status_t BBNSM_RTC_SetAlarm(BBNSM_Type *base, uint32_t alarmSeconds)
Sets the BBNSM RTC alarm time.
The function sets the RTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error. Please note, that RTC alarm has limited resolution because only 32 most significant bits of RTC counter are compared to RTC Alarm register. If the alarm time is beyond RTC resolution, the function does not set the alarm and returns an error.
- Parameters:
base – BBNSM peripheral base address
alarmSeconds –
- Returns:
kStatus_Success: success in setting the BBNSM RTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed or is beyond resolution
-
uint32_t BBNSM_RTC_GetAlarm(BBNSM_Type *base)
Returns the BBNSM RTC alarm time.
- Parameters:
base – BBNSM peripheral base address
-
struct _bbnsm_rtc_config
- #include <fsl_bbnsm.h>
BBNSM config structure.
This structure holds the configuration settings for the BBNSM peripheral. To initialize this structure to reasonable defaults, call the BBNSM_RTC_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
Public Members
-
bool rtcCalEnable
true: RTC calibration mechanism is enabled; false: No calibration is used
-
uint32_t rtcCalValue
Defines signed calibration value for RTC; This is a 5-bit 2’s complement value, range from -16 to +15
-
bool rtcCalEnable
CACHE: ARMV7-M7 CACHE Memory Controller
-
static inline void L1CACHE_EnableICache(void)
Enables cortex-m7 L1 instruction cache.
-
static inline void L1CACHE_DisableICache(void)
Disables cortex-m7 L1 instruction cache.
-
static inline void L1CACHE_InvalidateICache(void)
Invalidate cortex-m7 L1 instruction cache.
-
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
Invalidate cortex-m7 L1 instruction cache by range.
Note
The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The start address of the memory to be invalidated.
size_byte – The memory size.
-
static inline void L1CACHE_EnableDCache(void)
Enables cortex-m7 L1 data cache.
-
static inline void L1CACHE_DisableDCache(void)
Disables cortex-m7 L1 data cache.
-
static inline void L1CACHE_InvalidateDCache(void)
Invalidates cortex-m7 L1 data cache.
-
static inline void L1CACHE_CleanDCache(void)
Cleans cortex-m7 L1 data cache.
-
static inline void L1CACHE_CleanInvalidateDCache(void)
Cleans and Invalidates cortex-m7 L1 data cache.
-
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
Invalidates cortex-m7 L1 data cache by range.
Note
The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The start address of the memory to be invalidated.
size_byte – The memory size.
-
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
Cleans cortex-m7 L1 data cache by range.
Note
The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The start address of the memory to be cleaned.
size_byte – The memory size.
-
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
Cleans and Invalidates cortex-m7 L1 data cache by range.
Note
The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The start address of the memory to be clean and invalidated.
size_byte – The memory size.
-
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all instruction caches by range.
Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
Note
address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be invalidated.
-
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates all data caches by range.
Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
Note
address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be invalidated.
-
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
Cleans all data caches by range.
Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
Note
address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be cleaned.
-
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
Cleans and Invalidates all data caches by range.
Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
Note
address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be cleaned and invalidated.
-
FSL_CACHE_DRIVER_VERSION
cache driver version 2.0.4.
Clock Driver
-
enum _clock_lpcg
Clock LPCG index.
Values:
-
enumerator kCLOCK_M7
Clock LPCG M7
-
enumerator kCLOCK_M33
Clock LPCG M33
-
enumerator kCLOCK_Edgelock
Clock LPCG Edgelock
-
enumerator kCLOCK_Sim_Aon
Clock LPCG Sim_Aon
-
enumerator kCLOCK_Sim_Wakeup
Clock LPCG Sim_Wakeup
-
enumerator kCLOCK_Sim_Mega
Clock LPCG Sim_Mega
-
enumerator kCLOCK_Sim_R
Clock LPCG Sim_R
-
enumerator kCLOCK_Anadig
Clock LPCG Anadig
-
enumerator kCLOCK_Dcdc
Clock LPCG Dcdc
-
enumerator kCLOCK_Src
Clock LPCG Src
-
enumerator kCLOCK_Ccm
Clock LPCG Ccm
-
enumerator kCLOCK_Gpc
Clock LPCG Gpc
-
enumerator kCLOCK_Adc1
Clock LPCG Adc1
-
enumerator kCLOCK_Adc2
Clock LPCG Adc2
-
enumerator kCLOCK_Dac
Clock LPCG Dac
-
enumerator kCLOCK_Acmp1
Clock LPCG Acmp1
-
enumerator kCLOCK_Acmp2
Clock LPCG Acmp2
-
enumerator kCLOCK_Acmp3
Clock LPCG Acmp3
-
enumerator kCLOCK_Acmp4
Clock LPCG Acmp4
-
enumerator kCLOCK_Wdog1
Clock LPCG Wdog1
-
enumerator kCLOCK_Wdog2
Clock LPCG Wdog2
-
enumerator kCLOCK_Wdog3
Clock LPCG Wdog3
-
enumerator kCLOCK_Wdog4
Clock LPCG Wdog4
-
enumerator kCLOCK_Wdog5
Clock LPCG Wdog5
-
enumerator kCLOCK_Ewm0
Clock LPCG Ewm0
-
enumerator kCLOCK_Sema1
Clock LPCG Sema1
-
enumerator kCLOCK_Sema2
Clock LPCG Sema2
-
enumerator kCLOCK_Mu_A
Clock LPCG Mu_A
-
enumerator kCLOCK_Mu_B
Clock LPCG Mu_B
-
enumerator kCLOCK_Edma3
Clock LPCG Edma3
-
enumerator kCLOCK_Edma4
Clock LPCG Edma4
-
enumerator kCLOCK_Romcp
Clock LPCG Romcp
-
enumerator kCLOCK_Ocram1
Clock LPCG Ocram1
-
enumerator kCLOCK_Ocram2
Clock LPCG Ocram2
-
enumerator kCLOCK_Flexspi1
Clock LPCG Flexspi1
-
enumerator kCLOCK_Flexspi2
Clock LPCG Flexspi2
-
enumerator kCLOCK_Flexspi_Slv
Clock LPCG Flexspi_Slv
-
enumerator kCLOCK_Trdc
Clock LPCG Trdc
-
enumerator kCLOCK_Ocotp
Clock LPCG Ocotp
-
enumerator kCLOCK_Semc
Clock LPCG Semc
-
enumerator kCLOCK_Iee
Clock LPCG Iee
-
enumerator kCLOCK_Cstrace
Clock LPCG Cstrace
-
enumerator kCLOCK_Csswo
Clock LPCG Csswo
-
enumerator kCLOCK_Iomuxc1
Clock LPCG Iomuxc1
-
enumerator kCLOCK_Iomuxc2
Clock LPCG Iomuxc2
-
enumerator kCLOCK_Gpio1
Clock LPCG Gpio1
-
enumerator kCLOCK_Gpio2
Clock LPCG Gpio2
-
enumerator kCLOCK_Gpio3
Clock LPCG Gpio3
-
enumerator kCLOCK_Gpio4
Clock LPCG Gpio4
-
enumerator kCLOCK_Gpio5
Clock LPCG Gpio5
-
enumerator kCLOCK_Gpio6
Clock LPCG Gpio6
-
enumerator kCLOCK_Flexio1
Clock LPCG Flexio1
-
enumerator kCLOCK_Flexio2
Clock LPCG Flexio2
-
enumerator kCLOCK_Lpit1
Clock LPCG Lpit1
-
enumerator kCLOCK_Lpit2
Clock LPCG Lpit2
-
enumerator kCLOCK_Lpit3
Clock LPCG Lpit3
-
enumerator kCLOCK_Lptmr1
Clock LPCG Lptmr1
-
enumerator kCLOCK_Lptmr2
Clock LPCG Lptmr2
-
enumerator kCLOCK_Lptmr3
Clock LPCG Lptmr3
-
enumerator kCLOCK_Tpm1
Clock LPCG Tpm1
-
enumerator kCLOCK_Tpm2
Clock LPCG Tpm2
-
enumerator kCLOCK_Tpm3
Clock LPCG Tpm3
-
enumerator kCLOCK_Tpm4
Clock LPCG Tpm4
-
enumerator kCLOCK_Tpm5
Clock LPCG Tpm5
-
enumerator kCLOCK_Tpm6
Clock LPCG Tpm6
-
enumerator kCLOCK_Qtimer1
Clock LPCG Qtimer1
-
enumerator kCLOCK_Qtimer2
Clock LPCG Qtimer2
-
enumerator kCLOCK_Qtimer3
Clock LPCG Qtimer3
-
enumerator kCLOCK_Qtimer4
Clock LPCG Qtimer4
-
enumerator kCLOCK_Qtimer5
Clock LPCG Qtimer5
-
enumerator kCLOCK_Qtimer6
Clock LPCG Qtimer6
-
enumerator kCLOCK_Qtimer7
Clock LPCG Qtimer7
-
enumerator kCLOCK_Qtimer8
Clock LPCG Qtimer8
-
enumerator kCLOCK_Gpt1
Clock LPCG Gpt1
-
enumerator kCLOCK_Gpt2
Clock LPCG Gpt2
-
enumerator kCLOCK_Syscount
Clock LPCG Syscount
-
enumerator kCLOCK_Can1
Clock LPCG Can1
-
enumerator kCLOCK_Can2
Clock LPCG Can2
-
enumerator kCLOCK_Can3
Clock LPCG Can3
-
enumerator kCLOCK_Lpuart1
Clock LPCG Lpuart1
-
enumerator kCLOCK_Lpuart2
Clock LPCG Lpuart2
-
enumerator kCLOCK_Lpuart3
Clock LPCG Lpuart3
-
enumerator kCLOCK_Lpuart4
Clock LPCG Lpuart4
-
enumerator kCLOCK_Lpuart5
Clock LPCG Lpuart5
-
enumerator kCLOCK_Lpuart6
Clock LPCG Lpuart6
-
enumerator kCLOCK_Lpuart7
Clock LPCG Lpuart7
-
enumerator kCLOCK_Lpuart8
Clock LPCG Lpuart8
-
enumerator kCLOCK_Lpuart9
Clock LPCG Lpuart9
-
enumerator kCLOCK_Lpuart10
Clock LPCG Lpuart10
-
enumerator kCLOCK_Lpuart11
Clock LPCG Lpuart11
-
enumerator kCLOCK_Lpuart12
Clock LPCG Lpuart12
-
enumerator kCLOCK_Lpi2c1
Clock LPCG Lpi2c1
-
enumerator kCLOCK_Lpi2c2
Clock LPCG Lpi2c2
-
enumerator kCLOCK_Lpi2c3
Clock LPCG Lpi2c3
-
enumerator kCLOCK_Lpi2c4
Clock LPCG Lpi2c4
-
enumerator kCLOCK_Lpi2c5
Clock LPCG Lpi2c5
-
enumerator kCLOCK_Lpi2c6
Clock LPCG Lpi2c6
-
enumerator kCLOCK_Lpspi1
Clock LPCG Lpspi1
-
enumerator kCLOCK_Lpspi2
Clock LPCG Lpspi2
-
enumerator kCLOCK_Lpspi3
Clock LPCG Lpspi3
-
enumerator kCLOCK_Lpspi4
Clock LPCG Lpspi4
-
enumerator kCLOCK_Lpspi5
Clock LPCG Lpspi5
-
enumerator kCLOCK_Lpspi6
Clock LPCG Lpspi6
-
enumerator kCLOCK_I3c1
Clock LPCG I3c1
-
enumerator kCLOCK_I3c2
Clock LPCG I3c2
-
enumerator kCLOCK_Usdhc1
Clock LPCG Usdhc1
-
enumerator kCLOCK_Usdhc2
Clock LPCG Usdhc2
-
enumerator kCLOCK_Usb
Clock LPCG Usb
-
enumerator kCLOCK_Sinc1
Clock LPCG Sinc1
-
enumerator kCLOCK_Sinc2
Clock LPCG Sinc2
-
enumerator kCLOCK_Sinc3
Clock LPCG Sinc3
-
enumerator kCLOCK_Xbar1
Clock LPCG Xbar1
-
enumerator kCLOCK_Xbar2
Clock LPCG Xbar2
-
enumerator kCLOCK_Xbar3
Clock LPCG Xbar3
-
enumerator kCLOCK_Aoi1
Clock LPCG Aoi1
-
enumerator kCLOCK_Aoi2
Clock LPCG Aoi2
-
enumerator kCLOCK_Aoi3
Clock LPCG Aoi3
-
enumerator kCLOCK_Aoi4
Clock LPCG Aoi4
-
enumerator kCLOCK_Enc1
Clock LPCG Enc1
-
enumerator kCLOCK_Enc2
Clock LPCG Enc2
-
enumerator kCLOCK_Enc3
Clock LPCG Enc3
-
enumerator kCLOCK_Enc4
Clock LPCG Enc4
-
enumerator kCLOCK_Kpp
Clock LPCG Kpp
-
enumerator kCLOCK_Pwm1
Clock LPCG Pwm1
-
enumerator kCLOCK_Pwm2
Clock LPCG Pwm2
-
enumerator kCLOCK_Pwm3
Clock LPCG Pwm3
-
enumerator kCLOCK_Pwm4
Clock LPCG Pwm4
-
enumerator kCLOCK_Ecat
Clock LPCG Ecat
-
enumerator kCLOCK_Netc
Clock LPCG Netc
-
enumerator kCLOCK_Serdes1
Clock LPCG Serdes1
-
enumerator kCLOCK_Serdes2
Clock LPCG Serdes2
-
enumerator kCLOCK_Serdes3
Clock LPCG Serdes3
-
enumerator kCLOCK_Xcelbusx
Clock LPCG Xcelbusx
-
enumerator kCLOCK_Xriocu4
Clock LPCG Xriocu4
-
enumerator kCLOCK_Sptp
Clock LPCG Sptp
-
enumerator kCLOCK_Mctrl
Clock LPCG Mctrl
-
enumerator kCLOCK_Sai1
Clock LPCG Sai1
-
enumerator kCLOCK_Sai2
Clock LPCG Sai2
-
enumerator kCLOCK_Sai3
Clock LPCG Sai3
-
enumerator kCLOCK_Sai4
Clock LPCG Sai4
-
enumerator kCLOCK_Spdif
Clock LPCG Spdif
-
enumerator kCLOCK_Asrc
Clock LPCG Asrc
-
enumerator kCLOCK_Pdm
Clock LPCG Mic
-
enumerator kCLOCK_Vref
Clock LPCG Vref
-
enumerator kCLOCK_Bist
Clock LPCG Bist
-
enumerator kCLOCK_Ssi_W2M7
Clock LPCG Ssi_W2M7
-
enumerator kCLOCK_Ssi_M72W
Clock LPCG Ssi_M72W
-
enumerator kCLOCK_Ssi_W2Ao
Clock LPCG Ssi_W2Ao
-
enumerator kCLOCK_Ssi_Ao2W
Clock LPCG Ssi_Ao2W
-
enumerator kCLOCK_IpInvalid
Invalid value.
-
enumerator kCLOCK_M7
-
enum _clock_name
Clock name.
Values:
-
enumerator kCLOCK_OscRc24M
24MHz RC Oscillator.
-
enumerator kCLOCK_OscRc400M
400MHz RC Oscillator.
-
enumerator kCLOCK_Osc24M
24MHz Oscillator.
-
enumerator kCLOCK_Osc24MOut
24MHz Oscillator Out.
-
enumerator kCLOCK_ArmPll
ARM PLL.
-
enumerator kCLOCK_ArmPllOut
ARM PLL Out.
-
enumerator kCLOCK_SysPll2
SYS PLL2.
-
enumerator kCLOCK_SysPll2Out
SYS PLL2 OUT.
-
enumerator kCLOCK_SysPll2Pfd0
SYS PLL2 PFD0.
-
enumerator kCLOCK_SysPll2Pfd1
SYS PLL2 PFD1.
-
enumerator kCLOCK_SysPll2Pfd2
SYS PLL2 PFD2.
-
enumerator kCLOCK_SysPll2Pfd3
SYS PLL2 PFD3.
-
enumerator kCLOCK_SysPll3
SYS PLL3.
-
enumerator kCLOCK_SysPll3Out
SYS PLL3 OUT.
-
enumerator kCLOCK_SysPll3Div2
SYS PLL3 DIV2
-
enumerator kCLOCK_SysPll3Pfd0
SYS PLL3 PFD0.
-
enumerator kCLOCK_SysPll3Pfd1
SYS PLL3 PFD1
-
enumerator kCLOCK_SysPll3Pfd2
SYS PLL3 PFD2
-
enumerator kCLOCK_SysPll3Pfd3
SYS PLL3 PFD3
-
enumerator kCLOCK_SysPll1
SYS PLL1.
-
enumerator kCLOCK_SysPll1Out
SYS PLL1 OUT.
-
enumerator kCLOCK_SysPll1Div2
SYS PLL1 DIV2.
-
enumerator kCLOCK_SysPll1Div5
SYS PLL1 DIV5.
-
enumerator kCLOCK_AudioPll
SYS AUDIO PLL.
-
enumerator kCLOCK_AudioPllOut
SYS AUDIO PLL OUT.
-
enumerator kCLOCK_CpuClk
SYS CPU CLK.
-
enumerator kCLOCK_CoreSysClk
SYS CORE SYS CLK.
-
enumerator kCLOCK_OscRc24M
-
enum _clock_root
Root clock index.
Values:
-
enumerator kCLOCK_Root_M7
CLOCK Root M7
-
enumerator kCLOCK_Root_M33
CLOCK Root M33
-
enumerator kCLOCK_Root_Edgelock
CLOCK Root Edgelock
-
enumerator kCLOCK_Root_Bus_Aon
CLOCK Root Bus_Aon
-
enumerator kCLOCK_Root_Bus_Wakeup
CLOCK Root Bus_Wakeup
-
enumerator kCLOCK_Root_Wakeup_Axi
CLOCK Root Wakeup_Axi
-
enumerator kCLOCK_Root_Swo_Trace
CLOCK Root Swo_Trace
-
enumerator kCLOCK_Root_M33_Systick
CLOCK Root M33_Systick
-
enumerator kCLOCK_Root_M7_Systick
CLOCK Root M7_Systick
-
enumerator kCLOCK_Root_Flexio1
CLOCK Root Flexio1
-
enumerator kCLOCK_Root_Flexio2
CLOCK Root Flexio2
-
enumerator kCLOCK_Root_Lpit3
CLOCK Root Lpit3
-
enumerator kCLOCK_Root_Lptimer1
CLOCK Root Lptimer1
-
enumerator kCLOCK_Root_Lptimer2
CLOCK Root Lptimer2
-
enumerator kCLOCK_Root_Lptimer3
CLOCK Root Lptimer3
-
enumerator kCLOCK_Root_Tpm2
CLOCK Root Tpm2
-
enumerator kCLOCK_Root_Tpm4
CLOCK Root Tpm4
-
enumerator kCLOCK_Root_Tpm5
CLOCK Root Tpm5
-
enumerator kCLOCK_Root_Tpm6
CLOCK Root Tpm6
-
enumerator kCLOCK_Root_Gpt1
CLOCK Root Gpt1
-
enumerator kCLOCK_Root_Gpt2
CLOCK Root Gpt2
-
enumerator kCLOCK_Root_Flexspi1
CLOCK Root Flexspi1
-
enumerator kCLOCK_Root_Flexspi2
CLOCK Root Flexspi2
-
enumerator kCLOCK_Root_Flexspi_Slv
CLOCK Root Flexspi_Slv
-
enumerator kCLOCK_Root_Can1
CLOCK Root Can1
-
enumerator kCLOCK_Root_Can2
CLOCK Root Can2
-
enumerator kCLOCK_Root_Can3
CLOCK Root Can3
-
enumerator kCLOCK_Root_Lpuart0102
CLOCK Root Lpuart0102
-
enumerator kCLOCK_Root_Lpuart0304
CLOCK Root Lpuart0304
-
enumerator kCLOCK_Root_Lpuart0506
CLOCK Root Lpuart0506
-
enumerator kCLOCK_Root_Lpuart0708
CLOCK Root Lpuart0708
-
enumerator kCLOCK_Root_Lpuart0910
CLOCK Root Lpuart0910
-
enumerator kCLOCK_Root_Lpuart1112
CLOCK Root Lpuart1112
-
enumerator kCLOCK_Root_Lpi2c0102
CLOCK Root Lpi2c0102
-
enumerator kCLOCK_Root_Lpi2c0304
CLOCK Root Lpi2c0304
-
enumerator kCLOCK_Root_Lpi2c0506
CLOCK Root Lpi2c0506
-
enumerator kCLOCK_Root_Lpspi0102
CLOCK Root Lpspi0102
-
enumerator kCLOCK_Root_Lpspi0304
CLOCK Root Lpspi0304
-
enumerator kCLOCK_Root_Lpspi0506
CLOCK Root Lpspi0506
-
enumerator kCLOCK_Root_I3c1
CLOCK Root I3c1
-
enumerator kCLOCK_Root_I3c2
CLOCK Root I3c2
-
enumerator kCLOCK_Root_Usdhc1
CLOCK Root Usdhc1
-
enumerator kCLOCK_Root_Usdhc2
CLOCK Root Usdhc2
-
enumerator kCLOCK_Root_Semc
CLOCK Root Semc
-
enumerator kCLOCK_Root_Adc1
CLOCK Root Adc1
-
enumerator kCLOCK_Root_Adc2
CLOCK Root Adc2
-
enumerator kCLOCK_Root_Acmp
CLOCK Root Acmp
-
enumerator kCLOCK_Root_Ecat
CLOCK Root Ecat
-
enumerator kCLOCK_Root_Enet
CLOCK Root Enet
-
enumerator kCLOCK_Root_Tmr_1588
CLOCK Root Tmr_1588
-
enumerator kCLOCK_Root_Netc
CLOCK Root Netc
-
enumerator kCLOCK_Root_Mac0
CLOCK Root Mac0
-
enumerator kCLOCK_Root_Mac1
CLOCK Root Mac1
-
enumerator kCLOCK_Root_Mac2
CLOCK Root Mac2
-
enumerator kCLOCK_Root_Mac3
CLOCK Root Mac3
-
enumerator kCLOCK_Root_Mac4
CLOCK Root Mac4
-
enumerator kCLOCK_Root_Serdes0
CLOCK Root Serdes0
-
enumerator kCLOCK_Root_Serdes1
CLOCK Root Serdes1
-
enumerator kCLOCK_Root_Serdes2
CLOCK Root Serdes2
-
enumerator kCLOCK_Root_Serdes0_1G
CLOCK Root Serdes0_1G
-
enumerator kCLOCK_Root_Serdes1_1G
CLOCK Root Serdes1_1G
-
enumerator kCLOCK_Root_Serdes2_1G
CLOCK Root Serdes2_1G
-
enumerator kCLOCK_Root_Xcelbusx
CLOCK Root Xcelbusx
-
enumerator kCLOCK_Root_Xriocu4
CLOCK Root Xriocu4
-
enumerator kCLOCK_Root_Mctrl
CLOCK Root Mctrl
-
enumerator kCLOCK_Root_Sai1
CLOCK Root Sai1
-
enumerator kCLOCK_Root_Sai2
CLOCK Root Sai2
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enumerator kCLOCK_Root_Sai3
CLOCK Root Sai3
-
enumerator kCLOCK_Root_Sai4
CLOCK Root Sai4
-
enumerator kCLOCK_Root_Spdif
CLOCK Root Spdif
-
enumerator kCLOCK_Root_Asrc
CLOCK Root Asrc
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enumerator kCLOCK_Root_Mic
CLOCK Root Mic
-
enumerator kCLOCK_Root_Cko1
CLOCK Root Cko1
-
enumerator kCLOCK_Root_Cko2
CLOCK Root Cko2
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enumerator kCLOCK_Root_M7
-
enum _clock_root_mux_source
The enumerator of clock roots’ clock source mux value.
Values:
-
enumerator kCLOCK_M7_ClockRoot_MuxOscRc24M
M7 mux from OscRc24M.
-
enumerator kCLOCK_M7_ClockRoot_MuxOscRc400M
M7 mux from OscRc400M.
-
enumerator kCLOCK_M7_ClockRoot_MuxArmPllOut
M7 mux from ArmPllOut.
-
enumerator kCLOCK_M7_ClockRoot_MuxSysPll3Out
M7 mux from SysPll3Out.
-
enumerator kCLOCK_M33_ClockRoot_MuxOscRc24M
M33 mux from OscRc24M.
-
enumerator kCLOCK_M33_ClockRoot_MuxOscRc400M
M33 mux from OscRc400M.
-
enumerator kCLOCK_M33_ClockRoot_MuxSysPll3Out
M33 mux from SysPll3Out.
-
enumerator kCLOCK_M33_ClockRoot_MuxArmPllOut
M33 mux from ArmPllOut.
-
enumerator kCLOCK_EDGELOCK_ClockRoot_MuxOscRc24M
EDGELOCK mux from OscRc24M.
-
enumerator kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M
EDGELOCK mux from OscRc400M.
-
enumerator kCLOCK_EDGELOCK_ClockRoot_MuxSysPll1Out
EDGELOCK mux from SysPll1Out.
-
enumerator kCLOCK_EDGELOCK_ClockRoot_MuxSysPll2Pfd1
EDGELOCK mux from SysPll2Pfd1.
-
enumerator kCLOCK_BUS_AON_ClockRoot_MuxOscRc24M
BUS_AON mux from OscRc24M.
-
enumerator kCLOCK_BUS_AON_ClockRoot_MuxOscRc400M
BUS_AON mux from OscRc400M.
-
enumerator kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out
BUS_AON mux from SysPll2Out.
-
enumerator kCLOCK_BUS_AON_ClockRoot_MuxSysPll3Pfd2
BUS_AON mux from SysPll3Pfd2.
-
enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc24M
BUS_WAKEUP mux from OscRc24M.
-
enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc400M
BUS_WAKEUP mux from OscRc400M.
-
enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out
BUS_WAKEUP mux from SysPll2Out.
-
enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll3Pfd1
BUS_WAKEUP mux from SysPll3Pfd1.
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enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc24M
WAKEUP_AXI mux from OscRc24M.
-
enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc400M
WAKEUP_AXI mux from OscRc400M.
-
enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out
WAKEUP_AXI mux from SysPll3Out.
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enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll2Pfd1
WAKEUP_AXI mux from SysPll2Pfd1.
-
enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc24M
SWO_TRACE mux from OscRc24M.
-
enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc400M
SWO_TRACE mux from OscRc400M.
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enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2
SWO_TRACE mux from SysPll3Div2.
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enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll1Div5
SWO_TRACE mux from SysPll1Div5.
-
enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc24M
M33_SYSTICK mux from OscRc24M.
-
enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc400M
M33_SYSTICK mux from OscRc400M.
-
enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut
M33_SYSTICK mux from Osc24MOut.
-
enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxSysPll3Div2
M33_SYSTICK mux from SysPll3Div2.
-
enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M
M7_SYSTICK mux from OscRc24M.
-
enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M
M7_SYSTICK mux from OscRc400M.
-
enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut
M7_SYSTICK mux from Osc24MOut.
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enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2
M7_SYSTICK mux from SysPll3Div2.
-
enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc24M
FLEXIO1 mux from OscRc24M.
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enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M
FLEXIO1 mux from OscRc400M.
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enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2
FLEXIO1 mux from SysPll3Div2.
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enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5
FLEXIO1 mux from SysPll1Div5.
-
enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc24M
FLEXIO2 mux from OscRc24M.
-
enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M
FLEXIO2 mux from OscRc400M.
-
enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2
FLEXIO2 mux from SysPll3Div2.
-
enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5
FLEXIO2 mux from SysPll1Div5.
-
enumerator kCLOCK_LPIT3_ClockRoot_MuxOscRc24M
LPIT3 mux from OscRc24M.
-
enumerator kCLOCK_LPIT3_ClockRoot_MuxOscRc400M
LPIT3 mux from OscRc400M.
-
enumerator kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2
LPIT3 mux from SysPll3Div2.
-
enumerator kCLOCK_LPIT3_ClockRoot_MuxSysPll2Pfd3
LPIT3 mux from SysPll2Pfd3.
-
enumerator kCLOCK_LPTIMER1_ClockRoot_MuxOscRc24M
LPTIMER1 mux from OscRc24M.
-
enumerator kCLOCK_LPTIMER1_ClockRoot_MuxOscRc400M
LPTIMER1 mux from OscRc400M.
-
enumerator kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2
LPTIMER1 mux from SysPll3Div2.
-
enumerator kCLOCK_LPTIMER1_ClockRoot_MuxSysPll2Pfd3
LPTIMER1 mux from SysPll2Pfd3.
-
enumerator kCLOCK_LPTIMER2_ClockRoot_MuxOscRc24M
LPTIMER2 mux from OscRc24M.
-
enumerator kCLOCK_LPTIMER2_ClockRoot_MuxOscRc400M
LPTIMER2 mux from OscRc400M.
-
enumerator kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2
LPTIMER2 mux from SysPll3Div2.
-
enumerator kCLOCK_LPTIMER2_ClockRoot_MuxSysPll2Pfd3
LPTIMER2 mux from SysPll2Pfd3.
-
enumerator kCLOCK_LPTIMER3_ClockRoot_MuxOscRc24M
LPTIMER3 mux from OscRc24M.
-
enumerator kCLOCK_LPTIMER3_ClockRoot_MuxOscRc400M
LPTIMER3 mux from OscRc400M.
-
enumerator kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2
LPTIMER3 mux from SysPll3Div2.
-
enumerator kCLOCK_LPTIMER3_ClockRoot_MuxSysPll2Pfd3
LPTIMER3 mux from SysPll2Pfd3.
-
enumerator kCLOCK_TPM2_ClockRoot_MuxOscRc24M
TPM2 mux from OscRc24M.
-
enumerator kCLOCK_TPM2_ClockRoot_MuxOscRc400M
TPM2 mux from OscRc400M.
-
enumerator kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2
TPM2 mux from SysPll3Div2.
-
enumerator kCLOCK_TPM2_ClockRoot_MuxSysPll2Pfd3
TPM2 mux from SysPll2Pfd3.
-
enumerator kCLOCK_TPM4_ClockRoot_MuxOscRc24M
TPM4 mux from OscRc24M.
-
enumerator kCLOCK_TPM4_ClockRoot_MuxOscRc400M
TPM4 mux from OscRc400M.
-
enumerator kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2
TPM4 mux from SysPll3Div2.
-
enumerator kCLOCK_TPM4_ClockRoot_MuxSysPll2Pfd3
TPM4 mux from SysPll2Pfd3.
-
enumerator kCLOCK_TPM5_ClockRoot_MuxOscRc24M
TPM5 mux from OscRc24M.
-
enumerator kCLOCK_TPM5_ClockRoot_MuxOscRc400M
TPM5 mux from OscRc400M.
-
enumerator kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2
TPM5 mux from SysPll3Div2.
-
enumerator kCLOCK_TPM5_ClockRoot_MuxSysPll2Pfd3
TPM5 mux from SysPll2Pfd3.
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enumerator kCLOCK_TPM6_ClockRoot_MuxOscRc24M
TPM6 mux from OscRc24M.
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enumerator kCLOCK_TPM6_ClockRoot_MuxOscRc400M
TPM6 mux from OscRc400M.
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enumerator kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2
TPM6 mux from SysPll3Div2.
-
enumerator kCLOCK_TPM6_ClockRoot_MuxSysPll2Pfd3
TPM6 mux from SysPll2Pfd3.
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enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc24M
GPT1 mux from OscRc24M.
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enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc400M
GPT1 mux from OscRc400M.
-
enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2
GPT1 mux from SysPll3Div2.
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enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll2Pfd3
GPT1 mux from SysPll2Pfd3.
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enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc24M
GPT2 mux from OscRc24M.
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enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc400M
GPT2 mux from OscRc400M.
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enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2
GPT2 mux from SysPll3Div2.
-
enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll2Pfd3
GPT2 mux from SysPll2Pfd3.
-
enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M
FLEXSPI1 mux from OscRc24M.
-
enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M
FLEXSPI1 mux from OscRc400M.
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enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0
FLEXSPI1 mux from SysPll3Pfd0.
-
enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd0
FLEXSPI1 mux from SysPll2Pfd0.
-
enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc24M
FLEXSPI2 mux from OscRc24M.
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enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M
FLEXSPI2 mux from OscRc400M.
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enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2
FLEXSPI2 mux from SysPll3Pfd2.
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enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd1
FLEXSPI2 mux from SysPll2Pfd1.
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enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc24M
FLEXSPI_SLV mux from OscRc24M.
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enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc400M
FLEXSPI_SLV mux from OscRc400M.
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enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out
FLEXSPI_SLV mux from SysPll2Out.
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enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll1Out
FLEXSPI_SLV mux from SysPll1Out.
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enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc24M
CAN1 mux from OscRc24M.
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enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc400M
CAN1 mux from OscRc400M.
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enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll3Out
CAN1 mux from SysPll3Out.
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enumerator kCLOCK_CAN1_ClockRoot_MuxOsc24MOut
CAN1 mux from Osc24MOut.
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enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc24M
CAN2 mux from OscRc24M.
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enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc400M
CAN2 mux from OscRc400M.
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enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll3Out
CAN2 mux from SysPll3Out.
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enumerator kCLOCK_CAN2_ClockRoot_MuxOsc24MOut
CAN2 mux from Osc24MOut.
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enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc24M
CAN3 mux from OscRc24M.
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enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc400M
CAN3 mux from OscRc400M.
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enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll3Out
CAN3 mux from SysPll3Out.
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enumerator kCLOCK_CAN3_ClockRoot_MuxOsc24MOut
CAN3 mux from Osc24MOut.
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enumerator kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M
LPUART0102 mux from OscRc24M.
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enumerator kCLOCK_LPUART0102_ClockRoot_MuxOscRc400M
LPUART0102 mux from OscRc400M.
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enumerator kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2
LPUART0102 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART0102_ClockRoot_MuxSysPll2Pfd3
LPUART0102 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M
LPUART0304 mux from OscRc24M.
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enumerator kCLOCK_LPUART0304_ClockRoot_MuxOscRc400M
LPUART0304 mux from OscRc400M.
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enumerator kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2
LPUART0304 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART0304_ClockRoot_MuxSysPll2Pfd3
LPUART0304 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M
LPUART0506 mux from OscRc24M.
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enumerator kCLOCK_LPUART0506_ClockRoot_MuxOscRc400M
LPUART0506 mux from OscRc400M.
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enumerator kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2
LPUART0506 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART0506_ClockRoot_MuxSysPll2Pfd3
LPUART0506 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M
LPUART0708 mux from OscRc24M.
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enumerator kCLOCK_LPUART0708_ClockRoot_MuxOscRc400M
LPUART0708 mux from OscRc400M.
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enumerator kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2
LPUART0708 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART0708_ClockRoot_MuxSysPll2Pfd3
LPUART0708 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M
LPUART0910 mux from OscRc24M.
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enumerator kCLOCK_LPUART0910_ClockRoot_MuxOscRc400M
LPUART0910 mux from OscRc400M.
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enumerator kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2
LPUART0910 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART0910_ClockRoot_MuxSysPll2Pfd3
LPUART0910 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M
LPUART1112 mux from OscRc24M.
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enumerator kCLOCK_LPUART1112_ClockRoot_MuxOscRc400M
LPUART1112 mux from OscRc400M.
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enumerator kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2
LPUART1112 mux from SysPll3Div2.
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enumerator kCLOCK_LPUART1112_ClockRoot_MuxSysPll2Pfd3
LPUART1112 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPI2C0102_ClockRoot_MuxOscRc24M
LPI2C0102 mux from OscRc24M.
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enumerator kCLOCK_LPI2C0102_ClockRoot_MuxOscRc400M
LPI2C0102 mux from OscRc400M.
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enumerator kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2
LPI2C0102 mux from SysPll3Div2.
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enumerator kCLOCK_LPI2C0102_ClockRoot_MuxSysPll2Pfd3
LPI2C0102 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPI2C0304_ClockRoot_MuxOscRc24M
LPI2C0304 mux from OscRc24M.
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enumerator kCLOCK_LPI2C0304_ClockRoot_MuxOscRc400M
LPI2C0304 mux from OscRc400M.
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enumerator kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2
LPI2C0304 mux from SysPll3Div2.
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enumerator kCLOCK_LPI2C0304_ClockRoot_MuxSysPll2Pfd3
LPI2C0304 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPI2C0506_ClockRoot_MuxOscRc24M
LPI2C0506 mux from OscRc24M.
-
enumerator kCLOCK_LPI2C0506_ClockRoot_MuxOscRc400M
LPI2C0506 mux from OscRc400M.
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enumerator kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2
LPI2C0506 mux from SysPll3Div2.
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enumerator kCLOCK_LPI2C0506_ClockRoot_MuxSysPll2Pfd3
LPI2C0506 mux from SysPll2Pfd3.
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enumerator kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M
LPSPI0102 mux from OscRc24M.
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enumerator kCLOCK_LPSPI0102_ClockRoot_MuxOscRc400M
LPSPI0102 mux from OscRc400M.
-
enumerator kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1
LPSPI0102 mux from SysPll3Pfd1.
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enumerator kCLOCK_LPSPI0102_ClockRoot_MuxSysPll2Out
LPSPI0102 mux from SysPll2Out.
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enumerator kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M
LPSPI0304 mux from OscRc24M.
-
enumerator kCLOCK_LPSPI0304_ClockRoot_MuxOscRc400M
LPSPI0304 mux from OscRc400M.
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enumerator kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1
LPSPI0304 mux from SysPll3Pfd1.
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enumerator kCLOCK_LPSPI0304_ClockRoot_MuxSysPll2Out
LPSPI0304 mux from SysPll2Out.
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enumerator kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M
LPSPI0506 mux from OscRc24M.
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enumerator kCLOCK_LPSPI0506_ClockRoot_MuxOscRc400M
LPSPI0506 mux from OscRc400M.
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enumerator kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1
LPSPI0506 mux from SysPll3Pfd1.
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enumerator kCLOCK_LPSPI0506_ClockRoot_MuxSysPll2Out
LPSPI0506 mux from SysPll2Out.
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enumerator kCLOCK_I3C1_ClockRoot_MuxOscRc24M
I3C1 mux from OscRc24M.
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enumerator kCLOCK_I3C1_ClockRoot_MuxOscRc400M
I3C1 mux from OscRc400M.
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enumerator kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2
I3C1 mux from SysPll3Div2.
-
enumerator kCLOCK_I3C1_ClockRoot_MuxSysPll2Pfd3
I3C1 mux from SysPll2Pfd3.
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enumerator kCLOCK_I3C2_ClockRoot_MuxOscRc24M
I3C2 mux from OscRc24M.
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enumerator kCLOCK_I3C2_ClockRoot_MuxOscRc400M
I3C2 mux from OscRc400M.
-
enumerator kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2
I3C2 mux from SysPll3Div2.
-
enumerator kCLOCK_I3C2_ClockRoot_MuxSysPll2Pfd3
I3C2 mux from SysPll2Pfd3.
-
enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc24M
USDHC1 mux from OscRc24M.
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enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc400M
USDHC1 mux from OscRc400M.
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enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2
USDHC1 mux from SysPll2Pfd2.
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enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5
USDHC1 mux from SysPll1Div5.
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enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc24M
USDHC2 mux from OscRc24M.
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enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc400M
USDHC2 mux from OscRc400M.
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enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2
USDHC2 mux from SysPll2Pfd2.
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enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5
USDHC2 mux from SysPll1Div5.
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enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc24M
SEMC mux from OscRc24M.
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enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc400M
SEMC mux from OscRc400M.
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enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll1Out
SEMC mux from SysPll1Out.
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enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd0
SEMC mux from SysPll2Pfd0.
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enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc24M
ADC1 mux from OscRc24M.
-
enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc400M
ADC1 mux from OscRc400M.
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enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2
ADC1 mux from SysPll3Div2.
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enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3
ADC1 mux from SysPll2Pfd3.
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enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc24M
ADC2 mux from OscRc24M.
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enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc400M
ADC2 mux from OscRc400M.
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enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2
ADC2 mux from SysPll3Div2.
-
enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3
ADC2 mux from SysPll2Pfd3.
-
enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc24M
ACMP mux from OscRc24M.
-
enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc400M
ACMP mux from OscRc400M.
-
enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll3Out
ACMP mux from SysPll3Out.
-
enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3
ACMP mux from SysPll2Pfd3.
-
enumerator kCLOCK_ECAT_ClockRoot_MuxOscRc24M
ECAT mux from OscRc24M.
-
enumerator kCLOCK_ECAT_ClockRoot_MuxOscRc400M
ECAT mux from OscRc400M.
-
enumerator kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2
ECAT mux from SysPll1Div2.
-
enumerator kCLOCK_ECAT_ClockRoot_MuxSysPll1Div5
ECAT mux from SysPll1Div5.
-
enumerator kCLOCK_ENET_ClockRoot_MuxOscRc24M
ENET mux from OscRc24M.
-
enumerator kCLOCK_ENET_ClockRoot_MuxOscRc400M
ENET mux from OscRc400M.
-
enumerator kCLOCK_ENET_ClockRoot_MuxSysPll1Div2
ENET mux from SysPll1Div2.
-
enumerator kCLOCK_ENET_ClockRoot_MuxSysPll1Div5
ENET mux from SysPll1Div5.
-
enumerator kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M
TMR_1588 mux from OscRc24M.
-
enumerator kCLOCK_TMR_1588_ClockRoot_MuxOscRc400M
TMR_1588 mux from OscRc400M.
-
enumerator kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out
TMR_1588 mux from SysPll3Out.
-
enumerator kCLOCK_TMR_1588_ClockRoot_MuxSysPll2Pfd3
TMR_1588 mux from SysPll2Pfd3.
-
enumerator kCLOCK_NETC_ClockRoot_MuxOscRc24M
NETC mux from OscRc24M.
-
enumerator kCLOCK_NETC_ClockRoot_MuxOscRc400M
NETC mux from OscRc400M.
-
enumerator kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3
NETC mux from SysPll3Pfd3.
-
enumerator kCLOCK_NETC_ClockRoot_MuxSysPll2Pfd1
NETC mux from SysPll2Pfd1.
-
enumerator kCLOCK_MAC0_ClockRoot_MuxOscRc24M
MAC0 mux from OscRc24M.
-
enumerator kCLOCK_MAC0_ClockRoot_MuxOscRc400M
MAC0 mux from OscRc400M.
-
enumerator kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2
MAC0 mux from SysPll1Div2.
-
enumerator kCLOCK_MAC0_ClockRoot_MuxSysPll1Div5
MAC0 mux from SysPll1Div5.
-
enumerator kCLOCK_MAC1_ClockRoot_MuxOscRc24M
MAC1 mux from OscRc24M.
-
enumerator kCLOCK_MAC1_ClockRoot_MuxOscRc400M
MAC1 mux from OscRc400M.
-
enumerator kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2
MAC1 mux from SysPll1Div2.
-
enumerator kCLOCK_MAC1_ClockRoot_MuxSysPll1Div5
MAC1 mux from SysPll1Div5.
-
enumerator kCLOCK_MAC2_ClockRoot_MuxOscRc24M
MAC2 mux from OscRc24M.
-
enumerator kCLOCK_MAC2_ClockRoot_MuxOscRc400M
MAC2 mux from OscRc400M.
-
enumerator kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2
MAC2 mux from SysPll1Div2.
-
enumerator kCLOCK_MAC2_ClockRoot_MuxSysPll1Div5
MAC2 mux from SysPll1Div5.
-
enumerator kCLOCK_MAC3_ClockRoot_MuxOscRc24M
MAC3 mux from OscRc24M.
-
enumerator kCLOCK_MAC3_ClockRoot_MuxOscRc400M
MAC3 mux from OscRc400M.
-
enumerator kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2
MAC3 mux from SysPll1Div2.
-
enumerator kCLOCK_MAC3_ClockRoot_MuxSysPll1Div5
MAC3 mux from SysPll1Div5.
-
enumerator kCLOCK_MAC4_ClockRoot_MuxOscRc24M
MAC4 mux from OscRc24M.
-
enumerator kCLOCK_MAC4_ClockRoot_MuxOscRc400M
MAC4 mux from OscRc400M.
-
enumerator kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2
MAC4 mux from SysPll1Div2.
-
enumerator kCLOCK_MAC4_ClockRoot_MuxSysPll1Div5
MAC4 mux from SysPll1Div5.
-
enumerator kCLOCK_SERDES0_ClockRoot_MuxOscRc24M
SERDES0 mux from OscRc24M.
-
enumerator kCLOCK_SERDES0_ClockRoot_MuxOscRc400M
SERDES0 mux from OscRc400M.
-
enumerator kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div2
SERDES0 mux from SysPll1Div2.
-
enumerator kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div5
SERDES0 mux from SysPll1Div5.
-
enumerator kCLOCK_SERDES1_ClockRoot_MuxOscRc24M
SERDES1 mux from OscRc24M.
-
enumerator kCLOCK_SERDES1_ClockRoot_MuxOscRc400M
SERDES1 mux from OscRc400M.
-
enumerator kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div2
SERDES1 mux from SysPll1Div2.
-
enumerator kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div5
SERDES1 mux from SysPll1Div5.
-
enumerator kCLOCK_SERDES2_ClockRoot_MuxOscRc24M
SERDES2 mux from OscRc24M.
-
enumerator kCLOCK_SERDES2_ClockRoot_MuxOscRc400M
SERDES2 mux from OscRc400M.
-
enumerator kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div2
SERDES2 mux from SysPll1Div2.
-
enumerator kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div5
SERDES2 mux from SysPll1Div5.
-
enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc24M
SERDES0_1G mux from OscRc24M.
-
enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc400M
SERDES0_1G mux from OscRc400M.
-
enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxSysPll1Out
SERDES0_1G mux from SysPll1Out.
-
enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxAudioPllOut
SERDES0_1G mux from AudioPllOut.
-
enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc24M
SERDES1_1G mux from OscRc24M.
-
enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc400M
SERDES1_1G mux from OscRc400M.
-
enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxSysPll1Out
SERDES1_1G mux from SysPll1Out.
-
enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxAudioPllOut
SERDES1_1G mux from AudioPllOut.
-
enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc24M
SERDES2_1G mux from OscRc24M.
-
enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc400M
SERDES2_1G mux from OscRc400M.
-
enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxSysPll1Out
SERDES2_1G mux from SysPll1Out.
-
enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxAudioPllOut
SERDES2_1G mux from AudioPllOut.
-
enumerator kCLOCK_XCELBUSX_ClockRoot_MuxOscRc24M
XCELBUSX mux from OscRc24M.
-
enumerator kCLOCK_XCELBUSX_ClockRoot_MuxOscRc400M
XCELBUSX mux from OscRc400M.
-
enumerator kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Out
XCELBUSX mux from SysPll3Out.
-
enumerator kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Pfd1
XCELBUSX mux from SysPll3Pfd1.
-
enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOscRc24M
XRIOCU4 mux from OscRc24M.
-
enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOscRc400M
XRIOCU4 mux from OscRc400M.
-
enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOsc24MOut
XRIOCU4 mux from Osc24MOut.
-
enumerator kCLOCK_XRIOCU4_ClockRoot_MuxSysPll3Div2
XRIOCU4 mux from SysPll3Div2.
-
enumerator kCLOCK_MCTRL_ClockRoot_MuxOscRc24M
MCTRL mux from OscRc24M.
-
enumerator kCLOCK_MCTRL_ClockRoot_MuxOscRc400M
MCTRL mux from OscRc400M.
-
enumerator kCLOCK_MCTRL_ClockRoot_MuxSysPll1Div5
MCTRL mux from SysPll1Div5.
-
enumerator kCLOCK_MCTRL_ClockRoot_MuxAudioPllOut
MCTRL mux from AudioPllOut.
-
enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc24M
SAI1 mux from OscRc24M.
-
enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc400M
SAI1 mux from OscRc400M.
-
enumerator kCLOCK_SAI1_ClockRoot_MuxAudioPllOut
SAI1 mux from AudioPllOut.
-
enumerator kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2
SAI1 mux from SysPll3Pfd2.
-
enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc24M
SAI2 mux from OscRc24M.
-
enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc400M
SAI2 mux from OscRc400M.
-
enumerator kCLOCK_SAI2_ClockRoot_MuxAudioPllOut
SAI2 mux from AudioPllOut.
-
enumerator kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2
SAI2 mux from SysPll3Pfd2.
-
enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc24M
SAI3 mux from OscRc24M.
-
enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc400M
SAI3 mux from OscRc400M.
-
enumerator kCLOCK_SAI3_ClockRoot_MuxAudioPllOut
SAI3 mux from AudioPllOut.
-
enumerator kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2
SAI3 mux from SysPll3Pfd2.
-
enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc24M
SAI4 mux from OscRc24M.
-
enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc400M
SAI4 mux from OscRc400M.
-
enumerator kCLOCK_SAI4_ClockRoot_MuxAudioPllOut
SAI4 mux from AudioPllOut.
-
enumerator kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd2
SAI4 mux from SysPll3Pfd2.
-
enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc24M
SPDIF mux from OscRc24M.
-
enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc400M
SPDIF mux from OscRc400M.
-
enumerator kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut
SPDIF mux from AudioPllOut.
-
enumerator kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2
SPDIF mux from SysPll3Pfd2.
-
enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc24M
ASRC mux from OscRc24M.
-
enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc400M
ASRC mux from OscRc400M.
-
enumerator kCLOCK_ASRC_ClockRoot_MuxSysPll3Out
ASRC mux from SysPll3Out.
-
enumerator kCLOCK_ASRC_ClockRoot_MuxAudioPllOut
ASRC mux from AudioPllOut.
-
enumerator kCLOCK_MIC_ClockRoot_MuxOscRc24M
MIC mux from OscRc24M.
-
enumerator kCLOCK_MIC_ClockRoot_MuxOscRc400M
MIC mux from OscRc400M.
-
enumerator kCLOCK_MIC_ClockRoot_MuxSysPll3Div2
MIC mux from SysPll3Div2.
-
enumerator kCLOCK_MIC_ClockRoot_MuxAudioPllOut
MIC mux from AudioPllOut.
-
enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc24M
CKO1 mux from OscRc24M.
-
enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc400M
CKO1 mux from OscRc400M.
-
enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2
CKO1 mux from SysPll3Div2.
-
enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll1Div2
CKO1 mux from SysPll1Div2.
-
enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc24M
CKO2 mux from OscRc24M.
-
enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc400M
CKO2 mux from OscRc400M.
-
enumerator kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5
CKO2 mux from SysPll1Div5.
-
enumerator kCLOCK_CKO2_ClockRoot_MuxArmPllOut
CKO2 mux from ArmPllOut.
-
enumerator kCLOCK_M7_ClockRoot_MuxOscRc24M
-
enum _clock_osc
OSC 24M sorce select.
Values:
-
enumerator kCLOCK_RcOsc
On chip OSC.
-
enumerator kCLOCK_XtalOsc
24M Xtal OSC
-
enumerator kCLOCK_RcOsc
-
enum _clock_gate_value
Clock gate value.
Values:
-
enumerator kCLOCK_Off
Clock is off.
-
enumerator kCLOCK_On
Clock is on
-
enumerator kCLOCK_Off
-
enum _clock_mode_t
System clock mode.
Values:
-
enumerator kCLOCK_ModeRun
Remain in run mode.
-
enumerator kCLOCK_ModeWait
Transfer to wait mode.
-
enumerator kCLOCK_ModeStop
Transfer to stop mode.
-
enumerator kCLOCK_ModeRun
-
enum _clock_usb_src
USB clock source definition.
Values:
-
enumerator kCLOCK_Usb480M
Use 480M.
-
enumerator kCLOCK_UsbSrcUnused
Used when the function does not care the clock source.
-
enumerator kCLOCK_Usb480M
-
enum _clock_usb_phy_src
Source of the USB HS PHY.
Values:
-
enumerator kCLOCK_Usbphy480M
Use 480M.
-
enumerator kCLOCK_Usbphy480M
-
enum _clock_pll_clk_src
PLL clock source, bypass cloco source also.
Values:
-
enumerator kCLOCK_PllClkSrc24M
Pll clock source 24M
-
enumerator kCLOCK_PllSrcClkPN
Pll clock source CLK1_P and CLK1_N
-
enumerator kCLOCK_PllClkSrc24M
-
enum _clock_pll_post_div
PLL post divider enumeration.
Values:
-
enumerator kCLOCK_PllPostDiv2
Divide by 2.
-
enumerator kCLOCK_PllPostDiv4
Divide by 4.
-
enumerator kCLOCK_PllPostDiv8
Divide by 8.
-
enumerator kCLOCK_PllPostDiv1
Divide by 1.
-
enumerator kCLOCK_PllPostDiv2
-
enum _clock_pll
PLL name.
Values:
-
enumerator kCLOCK_PllArm
ARM PLL.
-
enumerator kCLOCK_PllSys1
SYS1 PLL, it has a dedicated frequency of 1GHz.
-
enumerator kCLOCK_PllSys2
SYS2 PLL, it has a dedicated frequency of 528MHz.
-
enumerator kCLOCK_PllSys3
SYS3 PLL, it has a dedicated frequency of 480MHz.
-
enumerator kCLOCK_PllAudio
Audio PLL.
-
enumerator kCLOCK_PllInvalid
Invalid value.
-
enumerator kCLOCK_PllArm
-
enum _clock_pfd
PLL PFD name.
Values:
-
enumerator kCLOCK_Pfd0
PLL PFD0
-
enumerator kCLOCK_Pfd1
PLL PFD1
-
enumerator kCLOCK_Pfd2
PLL PFD2
-
enumerator kCLOCK_Pfd3
PLL PFD3
-
enumerator kCLOCK_Pfd0
-
enum _clock_control_mode
The enumeration of control mode.
Values:
-
enumerator kCLOCK_SoftwareMode
Software control mode.
-
enumerator kCLOCK_GpcMode
GPC control mode.
-
enumerator kCLOCK_SoftwareMode
-
enum _clock_24MOsc_mode
The enumeration of 24MHz crystal oscillator mode.
Values:
-
enumerator kCLOCK_24MOscHighGainMode
24MHz crystal oscillator work as high gain mode.
-
enumerator kCLOCK_24MOscBypassMode
24MHz crystal oscillator work as bypass mode.
-
enumerator kCLOCK_24MOscLowPowerMode
24MHz crystal oscillator work as low power mode.
-
enumerator kCLOCK_24MOscHighGainMode
-
enum _clock_1MHzOut_behavior
The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
Values:
-
enumerator kCLOCK_1MHzOutDisable
Disable 1MHz output clock.
-
enumerator kCLOCK_1MHzOutEnableLocked1Mhz
Enable 1MHz output clock, and select locked 1MHz to output.
-
enumerator kCLOCK_1MHzOutEnableFreeRunning1Mhz
Enable 1MHZ output clock, and select free-running 1MHz to output.
-
enumerator kCLOCK_1MHzOutDisable
-
enum _clock_level
The clock dependence level.
Values:
-
enumerator kCLOCK_Level0
Not needed in any mode.
-
enumerator kCLOCK_Level1
Needed in RUN mode.
-
enumerator kCLOCK_Level2
Needed in RUN and WAIT mode.
-
enumerator kCLOCK_Level3
Needed in RUN, WAIT and STOP mode.
-
enumerator kCLOCK_Level4
Always on in any mode.
-
enumerator kCLOCK_Level0
-
typedef enum _clock_lpcg clock_lpcg_t
Clock LPCG index.
-
typedef enum _clock_name clock_name_t
Clock name.
-
typedef enum _clock_root clock_root_t
Root clock index.
-
typedef enum _clock_root_mux_source clock_root_mux_source_t
The enumerator of clock roots’ clock source mux value.
-
typedef enum _clock_osc clock_osc_t
OSC 24M sorce select.
-
typedef enum _clock_gate_value clock_gate_value_t
Clock gate value.
-
typedef enum _clock_mode_t clock_mode_t
System clock mode.
-
typedef enum _clock_usb_src clock_usb_src_t
USB clock source definition.
-
typedef enum _clock_usb_phy_src clock_usb_phy_src_t
Source of the USB HS PHY.
-
typedef enum _clock_pll_post_div clock_pll_post_div_t
PLL post divider enumeration.
-
typedef struct _clock_arm_pll_config clock_arm_pll_config_t
PLL configuration for ARM.
The output clock frequency is:
Fout=Fin*loopDivider /(2 * postDivider).
Fin is always 24MHz.
-
typedef struct _clock_usb_pll_config clock_usb_pll_config_t
PLL configuration for USB.
-
typedef struct _clock_pll_ss_config clock_pll_ss_config_t
Spread specturm configure Pll.
-
typedef struct _clock_sys_pll2_config clock_sys_pll2_config_t
PLL configure for Sys Pll2.
-
typedef struct _clock_sys_pll1_config clock_sys_pll1_config_t
PLL configure for Sys Pll1.
-
typedef struct _clock_audio_pll_config clock_audio_pll_config_t
PLL configuration for AUDIO.
-
typedef struct _clock_root_config_t clock_root_config_t
Clock root configuration.
-
typedef enum _clock_pll clock_pll_t
PLL name.
-
typedef enum _clock_pfd clock_pfd_t
PLL PFD name.
-
typedef enum _clock_control_mode clock_control_mode_t
The enumeration of control mode.
-
typedef enum _clock_24MOsc_mode clock_24MOsc_mode_t
The enumeration of 24MHz crystal oscillator mode.
-
typedef enum _clock_1MHzOut_behavior clock_1MHzOut_behavior_t
The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
-
typedef enum _clock_level clock_level_t
The clock dependence level.
-
const clock_name_t s_clockSourceName[][4]
-
static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)
Set CCM Root Clock MUX node to certain value.
- Parameters:
root – Which root clock node to set, see clock_root_t.
src – Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.
-
static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)
Get CCM Root Clock MUX value.
- Parameters:
root – Which root clock node to get, see clock_root_t.
- Returns:
Clock mux value.
-
static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)
Get CCM Root Clock Source.
- Parameters:
root – Which root clock node to get, see clock_root_t.
src – Clock mux value to get, see clock_root_mux_source_t.
- Returns:
Clock source
-
static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div)
Set CCM Root Clock DIV certain value.
- Parameters:
root – Which root clock to set, see clock_root_t.
div – Clock div value to set, different divider has different value range.
-
static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)
Get CCM DIV node value.
- Parameters:
root – Which root clock node to get, see clock_root_t.
- Returns:
divider set for this root
-
static inline void CLOCK_PowerOffRootClock(clock_root_t root)
Power Off Root Clock.
- Parameters:
root – Which root clock node to set, see clock_root_t.
-
static inline void CLOCK_PowerOnRootClock(clock_root_t root)
Power On Root Clock.
- Parameters:
root – Which root clock node to set, see clock_root_t.
-
static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)
Configure Root Clock.
- Parameters:
root – Which root clock node to set, see clock_root_t.
config – root clock config, see clock_root_config_t
-
static inline void CLOCK_ControlGate(clock_lpcg_t name, clock_gate_value_t value)
Control the clock gate for specific IP.
Note
This API will not have any effect when this clock is in CPULPM or SetPoint Mode
- Parameters:
name – Which clock to enable, see clock_lpcg_t.
value – Clock gate value to set, see clock_gate_value_t.
-
static inline void CLOCK_EnableClock(clock_lpcg_t name)
Enable the clock for specific IP.
- Parameters:
name – Which clock to enable, see clock_lpcg_t.
-
static inline void CLOCK_DisableClock(clock_lpcg_t name)
Disable the clock for specific IP.
- Parameters:
name – Which clock to disable, see clock_lpcg_t.
-
uint32_t CLOCK_GetFreq(clock_name_t name)
Gets the clock frequency for a specific clock name.
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.
- Parameters:
name – Clock names defined in clock_name_t
- Returns:
Clock frequency value in hertz
-
static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)
Gets the clock frequency for a specific root clock name.
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.
- Parameters:
root – Clock names defined in clock_root_t
- Returns:
Clock frequency value in hertz
-
uint32_t CLOCK_GetM7Freq(void)
Get the CCM CPU/core/system frequency.
- Returns:
Clock frequency; If the clock is invalid, returns 0.
-
uint32_t CLOCK_GetM33Freq(void)
Get the CCM CPU/core/system frequency.
- Returns:
Clock frequency; If the clock is invalid, returns 0.
-
static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)
Check if PLL is bypassed.
- Parameters:
pll – PLL control name (see clock_pll_t enumeration)
- Returns:
PLL bypass status.
true: The PLL is bypassed.
false: The PLL is not bypassed.
-
static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)
Check if PLL is enabled.
- Parameters:
pll – PLL control name (see clock_pll_t enumeration)
- Returns:
PLL bypass status.
true: The PLL is enabled.
false: The PLL is not enabled.
-
FSL_CLOCK_DRIVER_VERSION
CLOCK driver version.
-
SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
-
CCSR_OFFSET
CCM registers offset.
-
CBCDR_OFFSET
-
CBCMR_OFFSET
-
CSCMR1_OFFSET
-
CSCMR2_OFFSET
-
CSCDR1_OFFSET
-
CDCDR_OFFSET
-
CSCDR2_OFFSET
-
CSCDR3_OFFSET
-
CACRR_OFFSET
-
CS1CDR_OFFSET
-
CS2CDR_OFFSET
-
ARM_PLL_OFFSET
CCM Analog registers offset.
-
PLL_SYS_OFFSET
-
PLL_USB1_OFFSET
-
PLL_AUDIO_OFFSET
-
PLL_VIDEO_OFFSET
-
PLL_ENET_OFFSET
-
PLL_USB2_OFFSET
-
CCM_TUPLE(reg, shift, mask, busyShift)
-
CCM_TUPLE_REG(base, tuple)
-
CCM_TUPLE_SHIFT(tuple)
-
CCM_TUPLE_MASK(tuple)
-
CCM_TUPLE_BUSY_SHIFT(tuple)
-
CCM_BUSY_WAIT
-
CCM_ANALOG_TUPLE(reg, shift)
CCM ANALOG tuple macros to map corresponding registers and bit fields.
-
CCM_ANALOG_TUPLE_SHIFT(tuple)
-
CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)
-
CCM_ANALOG_TUPLE_REG(base, tuple)
-
PLL_SYS1_1G_FREQ
SYS_PLL_FREQ frequency in Hz.
-
PLL_SYS2_528_MFI
-
PLL_SYS2_528_FREQ
-
PLL_SYS3_480_MFI
-
PLL_SYS3_480_FREQ
-
XTAL_FREQ
-
VREF_CLOCKS
Clock gate name array for VREF.
-
LPADC_CLOCKS
Clock gate name array for LPADC.
-
AOI_CLOCKS
Clock gate name array for AOI.
-
ASRC_CLOCKS
Clock ip name array for ASRC.
-
CMP_CLOCKS
Clock ip name array for CMP.
-
DAC_CLOCKS
Clock ip name array for DAC.
-
DCDC_CLOCKS
Clock gate name array for DCDC.
-
ECAT_CLOCKS
Clock ip name array for ECAT.
-
EDMA_CLOCKS
Clock gate name array for EDMA.
-
ENC_CLOCKS
Clock ip name array for ENC.
-
EWM_CLOCKS
Clock gate name array for EWM.
-
FLEXCAN_CLOCKS
Clock ip name array for FLEXCAN.
-
FLEXIO_CLOCKS
Clock ip name array for FLEXIO.
-
FLEXSPI_CLOCKS
Clock gate name array for FLEXSPI.
-
FLEXSPI_SLV_CLOCKS
Clock gate name array for FLEXSPI_SLV.
-
GPC_CLOCKS
Clock gate name array for GPC.
-
GPIO_CLOCKS
Clock ip name array for GPIO.
-
GPT_CLOCKS
Clock ip name array for GPT.
-
I3C_CLOCKS
Clock ip name array for I3C.
-
IEE_CLOCKS
Clock ip name array for IEE.
-
KPP_CLOCKS
Clock ip name array for KPP.
-
LPI2C_CLOCKS
Clock ip name array for LPI2C.
-
LPIT_CLOCKS
Clock ip name array for LPIT.
-
LPSPI_CLOCKS
Clock ip name array for LPSPI.
-
LPTMR_CLOCKS
Clock ip name array for LPTMR.
-
LPUART_CLOCKS
Clock ip name array for LPUART.
-
PDM_CLOCKS
Clock ip name array for MIC.
-
MU_CLOCKS
Clock gate name array for MU.
-
NETC_CLOCKS
Clock ip name array for NETC.
-
OCOTP_CLOCKS
Clock ip name array for OCOTP.
-
PWM_CLOCKS
Clock ip name array for PWM.
-
SAI_CLOCKS
Clock ip name array for SAI.
-
SEMA42_CLOCKS
Clock gate name array for Sema.
-
SEMC_CLOCKS
Clock ip name array for SEMC.
-
SERDES_CLOCKS
Clock ip name array for SERDES.
-
SINC_CLOCKS
Clock ip name array for SINC.
-
SPDIF_CLOCKS
Clock ip name array for SPDIF.
-
SRC_CLOCKS
Clock gate name array for SRC.
-
TMR_CLOCKS
Clock ip name array for QTIMER.
-
TPM_CLOCKS
Clock ip name array for TPM.
-
USB_CLOCKS
Clock ip name array for USB.
-
USDHC_CLOCKS
Clock ip name array for USDHC.
-
WDOG_CLOCKS
Clock gate name array for WDOG.
-
XBAR_CLOCKS
Clock ip name array for XBAR.
-
CCM_OBS_OSC_RC_24M
-
CCM_OBS_OSC_RC_400M
-
CCM_OBS_OSC_24M_OUT
-
CCM_OBS_PLL_ARM_OUT
-
CCM_OBS_PLL_528_OUT
-
CCM_OBS_PLL_528_PFD0
-
CCM_OBS_PLL_528_PFD1
-
CCM_OBS_PLL_528_PFD2
-
CCM_OBS_PLL_528_PFD3
-
CCM_OBS_PLL_480_OUT
-
CCM_OBS_PLL_480_DIV2
-
CCM_OBS_PLL_480_PFD0
-
CCM_OBS_PLL_480_PFD1
-
CCM_OBS_PLL_480_PFD2
-
CCM_OBS_PLL_480_PFD3
-
CCM_OBS_PLL_1G_OUT
-
CCM_OBS_PLL_1G_DIV2
-
CCM_OBS_PLL_1G_DIV5
-
CCM_OBS_PLL_AUDIO_OUT
-
CCM_OBS_M7_CLK_ROOT
-
CCM_OBS_M33_CLK_ROOT
-
CCM_OBS_EDGELOCK_CLK_ROOT
-
CCM_OBS_BUS_AON_CLK_ROOT
-
CCM_OBS_BUS_WAKEUP_CLK_ROOT
-
CCM_OBS_WAKEUP_AXI_CLK_ROOT
-
CCM_OBS_SWO_TRACE_CLK_ROOT
-
CCM_OBS_M33_SYSTICK_CLK_ROOT
-
CCM_OBS_M7_SYSTICK_CLK_ROOT
-
CCM_OBS_FLEXIO1_CLK_ROOT
-
CCM_OBS_FLEXIO2_CLK_ROOT
-
CCM_OBS_LPIT3_CLK_ROOT
-
CCM_OBS_LPTMR1_CLK_ROOT
-
CCM_OBS_LPTMR2_CLK_ROOT
-
CCM_OBS_LPTMR3_CLK_ROOT
-
CCM_OBS_TPM2_CLK_ROOT
-
CCM_OBS_TPM4_CLK_ROOT
-
CCM_OBS_TPM5_CLK_ROOT
-
CCM_OBS_TPM6_CLK_ROOT
-
CCM_OBS_GPT1_CLK_ROOT
-
CCM_OBS_GPT2_CLK_ROOT
-
CCM_OBS_FLEXSPI1_CLK_ROOT
-
CCM_OBS_FLEXSPI2_CLK_ROOT
-
CCM_OBS_FLEXSPI_SLV_CLK_ROOT
-
CCM_OBS_CAN1_CLK_ROOT
-
CCM_OBS_CAN2_CLK_ROOT
-
CCM_OBS_CAN3_CLK_ROOT
-
CCM_OBS_LPUART0102_CLK_ROOT
-
CCM_OBS_LPUART0304_CLK_ROOT
-
CCM_OBS_LPUART0506_CLK_ROOT
-
CCM_OBS_LPUART0708_CLK_ROOT
-
CCM_OBS_LPUART0910_CLK_ROOT
-
CCM_OBS_LPUART1112_CLK_ROOT
-
CCM_OBS_LPI2C0102_CLK_ROOT
-
CCM_OBS_LPI2C0304_CLK_ROOT
-
CCM_OBS_LPI2C0506_CLK_ROOT
-
CCM_OBS_LPSPI0102_CLK_ROOT
-
CCM_OBS_LPSPI0304_CLK_ROOT
-
CCM_OBS_LPSPI0506_CLK_ROOT
-
CCM_OBS_I3C1_CLK_ROOT
-
CCM_OBS_I3C2_CLK_ROOT
-
CCM_OBS_USDHC1_CLK_ROOT
-
CCM_OBS_USDHC2_CLK_ROOT
-
CCM_OBS_SEMC_CLK_ROOT
-
CCM_OBS_ADC1_CLK_ROOT
-
CCM_OBS_ADC2_CLK_ROOT
-
CCM_OBS_ACMP_CLK_ROOT
-
CCM_OBS_ECAT_CLK_ROOT
-
CCM_OBS_ENET_REFCLK_ROOT
-
CCM_OBS_TMR_1588_CLK_ROOT
-
CCM_OBS_NETC_CLK_ROOT
-
CCM_OBS_MAC0_CLK_ROOT
-
CCM_OBS_MAC1_CLK_ROOT
-
CCM_OBS_MAC2_CLK_ROOT
-
CCM_OBS_MAC3_CLK_ROOT
-
CCM_OBS_MAC4_CLK_ROOT
-
CCM_OBS_SERDES0_CLK_ROOT
-
CCM_OBS_SERDES1_CLK_ROOT
-
CCM_OBS_SERDES2_CLK_ROOT
-
CCM_OBS_SERDES0_1G_CLK_ROOT
-
CCM_OBS_SERDES1_1G_CLK_ROOT
-
CCM_OBS_SERDES2_1G_CLK_ROOT
-
CCM_OBS_XCELBUSX_CLK_ROOT
-
CCM_OBS_XRIOCU4_CLK_ROOT
-
CCM_OBS_MOTORCTRL_CLK_ROOT
-
CCM_OBS_SAI1_CLK_ROOT
-
CCM_OBS_SAI2_CLK_ROOT
-
CCM_OBS_SAI3_CLK_ROOT
-
CCM_OBS_SAI4_CLK_ROOT
-
CCM_OBS_SPDIF_CLK_ROOT
-
CCM_OBS_ASRC_CLK_ROOT
-
CCM_OBS_MIC_CLK_ROOT
-
CCM_OBS_CCM_CKO1_CLK_ROOT
-
CCM_OBS_CCM_CKO2_CLK_ROOT
-
CCM_OBS_DIV
-
clock_ip_name_t
-
CLOCK_GetCpuClkFreq
-
CLOCK_GetCoreSysClkFreq
For compatible with other platforms without CCM.
-
PLL_PFD_COUNT
-
static inline uint32_t CLOCK_GetRtcFreq(void)
Gets the RTC clock frequency.
- Returns:
Clock frequency; If the clock is invalid, returns 0.
-
void CLOCK_SetClockSourceControlMode(clock_name_t name, clock_control_mode_t controlMode)
Set the control mode of a specifed clock.
- Parameters:
name – Clock names defined in clock_name_t
controlMode – The control mode to be set, please refer to clock_control_mode_t.
-
static inline void CLOCK_OSC_EnableOscRc24M(bool enable)
Enable/disable 24MHz RC oscillator.
- Parameters:
enable – Used to enable or disable the 24MHz RC oscillator.
true Enable the 24MHz RC oscillator.
false Dissable the 24MHz RC oscillator.
-
void CLOCK_OSC_EnableOsc24M(void)
Enable OSC 24Mhz.
This function enables OSC 24Mhz.
-
static inline void CLOCK_OSC_GateOsc24M(bool enableGate)
Gate/ungate the 24MHz crystal oscillator output.
Note
Gating the 24MHz crystal oscillator can save power.
- Parameters:
enableGate – Used to gate/ungate the 24MHz crystal oscillator.
true Gate the 24MHz crystal oscillator to save power.
false Ungate the 24MHz crystal oscillator.
-
void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode)
Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.
- Parameters:
workMode – The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.
-
void CLOCK_OSC_EnableOscRc400M(void)
Enable OSC RC 400Mhz.
This function enables OSC RC 400Mhz.
-
static inline void CLOCK_OSC_GateOscRc400M(bool enableGate)
Gate/ungate 400MHz RC oscillator.
- Parameters:
enableGate – Used to gate/ungate 400MHz RC oscillator.
true Gate the 400MHz RC oscillator.
false Ungate the 400MHz RC oscillator.
-
void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim)
Trims OSC RC 400MHz.
- Parameters:
enable – Used to enable trim function.
bypass – Bypass the trim function.
trim – Trim value.
-
void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue)
Set the divide value for ref_clk to generate slow clock.
Note
slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.
- Parameters:
divValue – The divide value to be set, the available range is 0~63.
-
void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount)
Set the target count for the fast clock.
- Parameters:
targetCount – The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.
-
void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis)
Set the negative and positive hysteresis value for the tuned clock.
Note
The hysteresis value should be set after the clock is tuned.
- Parameters:
negHysteresis – The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
posHysteresis – The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
-
void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass)
Bypass/un-bypass the tune logic.
- Parameters:
enableBypass – Used to control whether to bypass the turn logic.
true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
false Use the output of tune logic to run the oscillator.
-
void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable)
Start/Stop the tune logic.
- Parameters:
enable – Used to start or stop the tune logic.
true Start tuning
false Stop tuning and reset the tuning logic.
-
void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze)
Freeze/Unfreeze the tuning value.
- Parameters:
enableFreeze – Used to control whether to freeze the tune value.
true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
false Unfreezes and continues the tune operation.
-
void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue)
Set the 400MHz RC oscillator tune value when the tune logic is disabled.
- Parameters:
tuneValue – The tune value to determine the frequency of Oscillator.
-
void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior)
Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.
Note
The 1MHz clock is divided from 400M RC Oscillator.
- Parameters:
behavior – The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.
-
void CLOCK_OSC_SetLocked1MHzCount(uint16_t count)
Set the count for the locked 1MHz clock out.
- Parameters:
count – Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.
-
bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void)
Check the error flag for locked 1MHz clock out.
- Returns:
The error flag for locked 1MHz clock out.
true The count value has been reached within one diviced ref clock period
false No effect.
-
void CLOCK_OSC_ClearLocked1MHzErrorFlag(void)
Clear the error flag for locked 1MHz clock out.
-
uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void)
Get current count for the fast clock during the tune process.
- Returns:
The current count for the fast clock.
-
uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void)
Get current tune value used by oscillator during tune process.
- Returns:
The current tune value.
-
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
Initialize the ARM PLL.
This function initialize the ARM PLL with specific settings
- Parameters:
config – configuration to set to PLL.
-
status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz)
Calculate corresponding config values per given frequency.
This function calculates config valudes per given frequency for Arm PLL
- Parameters:
config – pll config structure
freqInMhz – target frequency
-
status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz)
Initializes the Arm PLL with Specific Frequency (in Mhz).
This function initializes the Arm PLL with specific frequency
- Parameters:
freqInMhz – target frequency
-
void CLOCK_DeinitArmPll(void)
De-initialize the ARM PLL.
-
void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
Calculate spread spectrum step and stop.
This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/syspll1), the factor is denominator.
- Parameters:
factor – factor to calculate step/stop
range – spread spectrum range
mod – spread spectrum modulation frequency
ss – calculated spread spectrum values
-
void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config)
Initialize the System PLL1.
This function initializes the System PLL1 with specific settings
- Parameters:
config – Configuration to set to PLL1.
-
void CLOCK_DeinitSysPll1(void)
De-initialize the System PLL1.
-
void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config)
Initialize the System PLL2.
This function initializes the System PLL2 with specific settings
- Parameters:
config – Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum
-
void CLOCK_DeinitSysPll2(void)
De-initialize the System PLL2.
-
bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd)
Check if Sys PLL2 PFD is enabled.
Note
Only useful in software control mode.
- Parameters:
pfd – PFD control name
- Returns:
PFD bypass status.
true: power on.
false: power off.
-
void CLOCK_InitSysPll3(void)
Initialize the System PLL3.
This function initializes the System PLL3 with specific settings
-
void CLOCK_DeinitSysPll3(void)
De-initialize the System PLL3.
-
bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd)
Check if Sys PLL3 PFD is enabled.
Note
Only useful in software control mode.
- Parameters:
pfd – PFD control name
- Returns:
PFD bypass status.
true: power on.
false: power off.
-
void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass)
PLL bypass setting.
- Parameters:
pll – PLL control name (see clock_pll_t enumeration)
bypass – Bypass the PLL.
true: Bypass the PLL.
false:Not bypass the PLL.
-
status_t CLOCK_CalcAudioPllFreq(clock_audio_pll_config_t *config, uint32_t freqInMhz)
Calculate corresponding config values per given frequency.
This function calculates config valudes per given frequency for Audio PLL.
- Parameters:
config – pll config structure
freqInMhz – target frequency
-
status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
Initializes the Audio PLL with Specific Frequency (in Mhz).
This function initializes the Audio PLL with specific frequency
- Parameters:
freqInMhz – target frequency
ssEnable – enable spread spectrum or not
ssRange – range spread spectrum range
ssMod – spread spectrum modulation frequency
-
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
Initializes the Audio PLL.
This function initializes the Audio PLL with specific settings
- Parameters:
config – Configuration to set to PLL.
-
void CLOCK_DeinitAudioPll(void)
De-initialize the Audio PLL.
-
uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
Get current PLL output frequency.
This function get current output frequency of specific PLL
- Parameters:
pll – pll name to get frequency.
- Returns:
The PLL output frequency in hertz.
-
void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
Initialize PLL PFD.
This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.
Note
It is recommended that PFD settings are kept between 13-35.
- Parameters:
pll – Which PLL of targeting PFD to be operated.
pfd – Which PFD clock to enable.
frac – The PFD FRAC value.
-
void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)
De-initialize selected PLL PFD.
- Parameters:
pll – Which PLL of targeting PFD to be operated.
pfd – Which PFD clock to enable.
-
uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd)
Get current PFD output frequency.
This function get current output frequency of specific System PLL PFD
- Parameters:
pll – Which PLL of targeting PFD to be operated.
pfd – pfd name to get frequency.
- Returns:
The PFD output frequency in hertz.
-
uint32_t CLOCK_GetFreqFromObs(uint8_t obsIndex, uint32_t obsSigIndex)
-
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.
- Parameters:
src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq – USB HS does not care about the clock source, so this parameter is ignored.
- Return values:
true – The clock is set successfully.
false – The clock source is invalid to get proper USB HS clock.
-
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
Enable USB HS clock.
This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.
- Parameters:
src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq – USB HS does not care about the clock source, so this parameter is ignored.
- Return values:
true – The clock is set successfully.
false – The clock source is invalid to get proper USB HS clock.
-
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
This function enables the internal 480MHz USB PHY PLL clock.
- Parameters:
src – USB HS PHY PLL clock source.
freq – The frequency specified by src.
- Return values:
true – The clock is set successfully.
false – The clock source is invalid to get proper USB HS clock.
-
void CLOCK_DisableUsbhs0PhyPllClock(void)
Disable USB HS PHY PLL clock.
This function disables USB HS PHY PLL clock.
-
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
Enable USB HS PHY PLL clock.
This function enables the internal 480MHz USB PHY PLL clock.
- Parameters:
src – USB HS PHY PLL clock source.
freq – The frequency specified by src.
- Return values:
true – The clock is set successfully.
false – The clock source is invalid to get proper USB HS clock.
-
void CLOCK_DisableUsbhs1PhyPllClock(void)
Disable USB HS PHY PLL clock.
This function disables USB HS PHY PLL clock.
-
static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)
Lock the value of Domain ID white list for this clock.
Note
Once locked, this bit and domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock source name, see clock_name_t.
-
static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)
Set domain ID that can change this clock.
Note
If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock source name, see clock_name_t.
domainId – Domains that on the whitelist can change this clock.
-
void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, uint32_t domainMap, clock_level_t level)
Set this clock works in CPU Low Power Mode.
Note
When LOCK_MODE bit is set, control mode can not be changed until next system reset.
- Parameters:
name – Clock source name, see clock_name_t.
domainMap – Domains that on the whitelist can change this clock.
level – Depend level of this clock.
-
static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)
Lock the value of Domain ID white list for this clock.
Note
Once locked, this bit and domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock root name, see clock_root_t.
-
static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)
Set domain ID that can change this clock.
Note
If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock root name, see clock_root_t.
domainId – Domains that on the whitelist can change this clock.
-
static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)
Lock the value of Domain ID white list for this clock.
Note
Once locked, this bit and domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock gate name, see clock_lpcg_t.
-
static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)
Set domain ID that can change this clock.
Note
If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
- Parameters:
name – Clock gate name, see clock_lpcg_t.
domainId – Domains that on the whitelist can change this clock.
-
void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, uint32_t domainMap, clock_level_t level)
Set this clock works in CPU Low Power Mode.
Note
When LOCK_MODE bit is set, control mode can not be changed until next system reset.
- Parameters:
name – Clock gate name, see clock_lpcg_t.
domainMap – Domains that on the whitelist can change this clock.
level – Depend level of this clock.
-
clock_pll_post_div_t postDivider
Post divider.
-
uint32_t loopDivider
PLL loop divider. Valid range: 104-208.
-
uint8_t loopDivider
PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22
-
uint8_t src
Pll clock source, reference _clock_pll_clk_src
-
uint16_t stop
Spread spectrum stop value to get frequency change.
-
uint16_t step
Spread spectrum step value to get frequency change step.
-
uint32_t mfd
Denominator of spread spectrum
-
clock_pll_ss_config_t *ss
Spread spectrum parameter, it can be NULL, if ssEnable is set to false
-
bool ssEnable
Enable spread spectrum flag
-
bool pllDiv2En
Enable Sys Pll1 divide-by-2 clock or not.
-
bool pllDiv5En
Enable Sys Pll1 divide-by-5 clock or not.
-
clock_pll_ss_config_t *ss
Spread spectrum parameter, it can be NULL, if ssEnable is set to false
-
bool ssEnable
Enable spread spectrum flag
-
uint8_t loopDivider
PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
-
uint8_t postDivider
Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.
-
uint32_t numerator
30 bit numerator of fractional loop divider.
-
uint32_t denominator
30 bit denominator of fractional loop divider
-
clock_pll_ss_config_t *ss
Spread spectrum parameter, it can be NULL, if ssEnable is set to false
-
bool ssEnable
Enable spread spectrum flag
-
bool clockOff
-
uint8_t mux
See clock_root_mux_source_t for details.
-
uint8_t div
it’s the actual divider
-
FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
Configure whether driver controls clock.
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.
Note
All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
-
struct _clock_arm_pll_config
- #include <fsl_clock.h>
PLL configuration for ARM.
The output clock frequency is:
Fout=Fin*loopDivider /(2 * postDivider).
Fin is always 24MHz.
-
struct _clock_usb_pll_config
- #include <fsl_clock.h>
PLL configuration for USB.
-
struct _clock_pll_ss_config
- #include <fsl_clock.h>
Spread specturm configure Pll.
-
struct _clock_sys_pll2_config
- #include <fsl_clock.h>
PLL configure for Sys Pll2.
-
struct _clock_sys_pll1_config
- #include <fsl_clock.h>
PLL configure for Sys Pll1.
-
struct _clock_audio_pll_config
- #include <fsl_clock.h>
PLL configuration for AUDIO.
-
struct _clock_root_config_t
- #include <fsl_clock.h>
Clock root configuration.
DAC12: 12-bit Digital-to-Analog Converter Driver
-
void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info)
Get hardware information about this module.
- Parameters:
base – DAC12 peripheral base address.
info – Pointer to info structure, see to dac12_hardware_info_t.
-
void DAC12_Init(DAC_Type *base, const dac12_config_t *config)
Initialize the DAC12 module.
- Parameters:
base – DAC12 peripheral base address.
config – Pointer to configuration structure, see to dac12_config_t.
-
void DAC12_GetDefaultConfig(dac12_config_t *config)
Initializes the DAC12 user configuration structure.
This function initializes the user configuration structure to a default value. The default values are:
config->fifoWatermarkLevel = 0U; config->fifoWorkMode = kDAC12_FIFODisabled; config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1; config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode; config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0; config->speedMode = kDAC12_SpeedLowMode; config->speedMode = false; config->currentReferenceInternalTrimValue = 0x4;
- Parameters:
config – Pointer to the configuration structure. See “dac12_config_t”.
-
void DAC12_Deinit(DAC_Type *base)
De-initialize the DAC12 module.
- Parameters:
base – DAC12 peripheral base address.
-
static inline void DAC12_Enable(DAC_Type *base, bool enable)
Enable the DAC12’s converter or not.
- Parameters:
base – DAC12 peripheral base address.
enable – Enable the DAC12’s converter or not.
-
static inline void DAC12_ResetConfig(DAC_Type *base)
Reset all internal logic and registers.
- Parameters:
base – DAC12 peripheral base address.
-
static inline void DAC12_ResetFIFO(DAC_Type *base)
Reset the FIFO pointers.
FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers to the same address to reset the FIFO as empty.
- Parameters:
base – DAC12 peripheral base address.
-
static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base)
Get status flags.
- Parameters:
base – DAC12 peripheral base address.
- Returns:
Mask of current status flags. See to _dac12_status_flags.
-
static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags)
Clear status flags.
Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to target chip’s reference manual document.
- Parameters:
base – DAC12 peripheral base address.
flags – Mask of status flags to be cleared. See to _dac12_status_flags.
-
static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask)
Enable interrupts.
- Parameters:
base – DAC12 peripheral base address.
mask – Mask value of interrupts to be enabled. See to _dac12_interrupt_enable.
-
static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask)
Disable interrupts.
- Parameters:
base – DAC12 peripheral base address.
mask – Mask value of interrupts to be disabled. See to _dac12_interrupt_enable.
-
static inline void DAC12_EnableDMA(DAC_Type *base, bool enable)
Enable DMA or not.
When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
-
static inline void DAC12_SetData(DAC_Type *base, uint32_t value)
Set data into the entry of FIFO buffer.
When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion without trigger support. When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored into the FIFO buffer.
- Parameters:
base – DAC12 peripheral base address.
value – Setting value into FIFO buffer.
-
static inline void DAC12_DoSoftwareTrigger(DAC_Type *base)
Do trigger the FIFO by software.
When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the data in the entry pointed by read pointer would be converted as new output.
- Parameters:
base – DAC12 peripheral base address.
-
static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base)
Get the current read pointer of FIFO.
- Parameters:
base – DAC12 peripheral base address.
- Returns:
Read pointer index of FIFO buffer.
-
static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base)
Get the current write pointer of FIFO.
- Parameters:
base – DAC12 peripheral base address.
- Returns:
Write pointer index of FIFO buffer
-
FSL_DAC12_DRIVER_VERSION
DAC12 driver version 2.1.1.
-
enum _dac12_status_flags
DAC12 flags.
Values:
-
enumerator kDAC12_OverflowFlag
FIFO overflow status flag, which indicates that more data has been written into FIFO than it can hold.
-
enumerator kDAC12_UnderflowFlag
FIFO underflow status flag, which means that there is a new trigger after the FIFO is nearly empty.
-
enumerator kDAC12_WatermarkFlag
FIFO wartermark status flag, which indicates the remaining FIFO data is less than the watermark setting.
-
enumerator kDAC12_NearlyEmptyFlag
FIFO nearly empty flag, which means there is only one data remaining in FIFO.
-
enumerator kDAC12_FullFlag
FIFO full status flag, which means that the FIFO read pointer equals the write pointer, as the write pointer increase.
-
enumerator kDAC12_OverflowFlag
-
enum _dac12_interrupt_enable
DAC12 interrupts.
Values:
-
enumerator kDAC12_UnderOrOverflowInterruptEnable
Underflow and overflow interrupt enable.
-
enumerator kDAC12_WatermarkInterruptEnable
Watermark interrupt enable.
-
enumerator kDAC12_NearlyEmptyInterruptEnable
Nearly empty interrupt enable.
-
enumerator kDAC12_FullInterruptEnable
Full interrupt enable.
-
enumerator kDAC12_UnderOrOverflowInterruptEnable
-
enum _dac12_fifo_size_info
DAC12 FIFO size information provided by hardware.
Values:
-
enumerator kDAC12_FIFOSize2
FIFO depth is 2.
-
enumerator kDAC12_FIFOSize4
FIFO depth is 4.
-
enumerator kDAC12_FIFOSize8
FIFO depth is 8.
-
enumerator kDAC12_FIFOSize16
FIFO depth is 16.
-
enumerator kDAC12_FIFOSize32
FIFO depth is 32.
-
enumerator kDAC12_FIFOSize64
FIFO depth is 64.
-
enumerator kDAC12_FIFOSize128
FIFO depth is 128.
-
enumerator kDAC12_FIFOSize256
FIFO depth is 256.
-
enumerator kDAC12_FIFOSize2
-
enum _dac12_fifo_work_mode
DAC12 FIFO work mode.
Values:
-
enumerator kDAC12_FIFODisabled
FIFO disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
-
enumerator kDAC12_FIFOWorkAsNormalMode
Data will first read from FIFO to buffer then go to conversion.
-
enumerator kDAC12_FIFOWorkAsSwingMode
In Swing mode, the FIFO must be set up to be full. In Swing back mode, a trigger changes the read pointer to make it swing between the FIFO Full and Nearly Empty state. That is, the trigger increases the read pointer till FIFO is nearly empty and decreases the read pointer till the FIFO is full.
-
enumerator kDAC12_FIFODisabled
-
enum _dac12_reference_voltage_source
DAC12 reference voltage source.
Values:
-
enumerator kDAC12_ReferenceVoltageSourceAlt1
The DAC selects DACREF_1 as the reference voltage.
-
enumerator kDAC12_ReferenceVoltageSourceAlt2
The DAC selects DACREF_2 as the reference voltage.
-
enumerator kDAC12_ReferenceVoltageSourceAlt1
-
enum _dac12_fifo_trigger_mode
DAC12 FIFO trigger mode.
Values:
-
enumerator kDAC12_FIFOTriggerByHardwareMode
Buffer would be triggered by hardware.
-
enumerator kDAC12_FIFOTriggerBySoftwareMode
Buffer would be triggered by software.
-
enumerator kDAC12_FIFOTriggerByHardwareMode
-
enum _dac12_reference_current_source
DAC internal reference current source.
Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.
Values:
-
enumerator kDAC12_ReferenceCurrentSourceDisabled
None of reference current source is enabled.
-
enumerator kDAC12_ReferenceCurrentSourceAlt0
Use the internal reference current generated by the module itself.
-
enumerator kDAC12_ReferenceCurrentSourceAlt1
Use the ZTC(Zero Temperature Coefficient) reference current generated by on-chip power management module.
-
enumerator kDAC12_ReferenceCurrentSourceAlt2
Use the PTAT(Proportional To Absolution Temperature) reference current generated by power management module.
-
enumerator kDAC12_ReferenceCurrentSourceDisabled
-
enum _dac12_speed_mode
DAC analog buffer speed mode for conversion.
Values:
-
enumerator kDAC12_SpeedLowMode
Low speed mode.
-
enumerator kDAC12_SpeedMiddleMode
Middle speed mode.
-
enumerator kDAC12_SpeedHighMode
High speed mode.
-
enumerator kDAC12_SpeedLowMode
-
typedef enum _dac12_fifo_size_info dac12_fifo_size_info_t
DAC12 FIFO size information provided by hardware.
-
typedef enum _dac12_fifo_work_mode dac12_fifo_work_mode_t
DAC12 FIFO work mode.
-
typedef enum _dac12_reference_voltage_source dac12_reference_voltage_source_t
DAC12 reference voltage source.
-
typedef enum _dac12_fifo_trigger_mode dac12_fifo_trigger_mode_t
DAC12 FIFO trigger mode.
-
typedef enum _dac12_reference_current_source dac12_reference_current_source_t
DAC internal reference current source.
Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.
-
typedef enum _dac12_speed_mode dac12_speed_mode_t
DAC analog buffer speed mode for conversion.
-
typedef struct _dac12_hardware_info dac12_hardware_info_t
DAC12 hardware information.
-
DAC12_CR_W1C_FLAGS_MASK
Define “write 1 to clear” flags.
-
DAC12_CR_ALL_FLAGS_MASK
Define all the flag bits in DACx_CR register.
-
struct _dac12_hardware_info
- #include <fsl_dac12.h>
DAC12 hardware information.
Public Members
-
dac12_fifo_size_info_t fifoSizeInfo
The number of words in this device’s DAC buffer.
-
dac12_fifo_size_info_t fifoSizeInfo
-
struct dac12_config_t
- #include <fsl_dac12.h>
DAC12 module configuration.
Actually, the most fields are for FIFO buffer.
Public Members
-
uint32_t fifoWatermarkLevel
FIFO’s watermark, the max value can be the hardware FIFO size.
-
dac12_fifo_work_mode_t fifoWorkMode
FIFI’s work mode about pointers.
-
dac12_reference_voltage_source_t referenceVoltageSource
Select the reference voltage source.
-
dac12_reference_current_source_t referenceCurrentSource
Select the trigger mode for FIFO. Select the reference current source.
-
dac12_speed_mode_t speedMode
Select the speed mode for conversion.
-
bool enableAnalogBuffer
Enable analog buffer for high drive.
-
uint32_t fifoWatermarkLevel
Dcdc_soc
-
void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
Initializes the basic resource of DCDC module, such as control mode, etc.
- Parameters:
base – DCDC peripheral base address.
config – Pointer to the dcdc_config_t structure.
-
void DCDC_Deinit(DCDC_Type *base)
De-initializes the DCDC module.
- Parameters:
base – DCDC peripheral base address.
-
void DCDC_GetDefaultConfig(dcdc_config_t *config)
Gets the default setting for DCDC, such as control mode, etc.
This function initializes the user configuration structure to a default value. The default values are:
config->controlMode = kDCDC_StaticControl; config->trimInputMode = kDCDC_SampleTrimInput; config->enableDcdcTimeout = false; config->enableSwitchingConverterOutput = false;
- Parameters:
config – Pointer to configuration structure. See to dcdc_config_t.
-
static inline void DCDC_SetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)
-
static inline uint16_t DCDC_GetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base)
Gets the target value of VDD1P0 in low power mode, the result takes “mV” as the unit.
- Parameters:
base – DCDC peripheral base address.
- Returns:
The VDD1P0’s voltage value in low power mode and the unit is “mV”.
-
static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enable)
-
static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)
Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step.
- Parameters:
base – DCDC peripheral base address.
core – Core for DCDC to control.
targetVoltage – The target value of VDD1P0 in buck mode, see dcdc_1P0_target_vol_t.
-
static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
Gets the target value of VDD1P0 in buck mode, the result takes “mV” as the unit.
- Parameters:
base – DCDC peripheral base address.
- Returns:
The VDD1P0’s voltage value in buck mode and the unit is “mV”.
-
static inline void DCDC_GPC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)
-
static inline void DCDC_GPC_SetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)
Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in low power mode, 25mV each step.
- Parameters:
base – DCDC peripheral base address.
core – Core for DCDC to control.
targetVoltage – The target value of VDD1P0 in low power mode, see dcdc_1P0_target_vol_t.
-
static inline void DCDC_GPC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enable)
Enable VDD1P0 in low power mode.
- Parameters:
base – DCDC peripheral base address.
core – Core for DCDC to control.
enable – Enable the output or not.
-
static inline void DCDC_SetVDD1P8TargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P8_target_vol_t targetVoltage)
Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8, 25mV each step.
- Parameters:
base – DCDC peripheral base address.
core – Core for DCDC to control.
targetVoltage – The target value of VDD1P8, see dcdc_1P8_target_vol_t.
-
static inline uint16_t DCDC_GetVDD1P8TargetVoltage(DCDC_Type *base)
Gets the target value of VDD1P8, the result takes “mV” as the unit.
- Parameters:
base – DCDC peripheral base address.
- Returns:
The VDD1P8’s voltage value and the unit is “mV”.
-
static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)
Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be disabled.
- Parameters:
base – DCDC peripheral base address.
enable – Used to control the behavior.
true Enables stepping for VDD1P0.
false Disables stepping for VDD1P0.
-
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
Gets the default setting for detection configuration.
The default configuration are set according to responding registers’ setting when powered on. They are:
config->enableXtalokDetection = false; config->powerDownOverVoltageVdd1P8Detection = true; config->powerDownOverVoltageVdd1P0Detection = true; config->powerDownLowVoltageDetection = false; config->powerDownOverCurrentDetection = true; config->powerDownPeakCurrentDetection = true; config->powerDownZeroCrossDetection = true; config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
- Parameters:
config – Pointer to configuration structure. See to dcdc_detection_config_t.
-
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
Configures the DCDC detection.
- Parameters:
base – DCDC peripheral base address.
config – Pointer to configuration structure. See to dcdc_detection_config_t.
-
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
Configures the DCDC clock source.
- Parameters:
base – DCDC peripheral base address.
clockSource – Clock source for DCDC. See to dcdc_clock_source_t.
-
static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
Sets the bangap trim value(0~31) to trim bandgap voltage.
- Parameters:
base – DCDC peripheral base address.
trimValue – The bangap trim value. Available range is 0U-31U.
-
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
Gets the default setting for loop control configuration.
The default configuration are set according to responding registers’ setting when powered on. They are:
config->enableCommonHysteresis = false; config->enableCommonThresholdDetection = false; config->enableInvertHysteresisSign = false; config->enableRCThresholdDetection = false; config->enableRCScaleCircuit = 0U; config->complementFeedForwardStep = 0U; config->controlParameterMagnitude = 2U; config->integralProportionalRatio = 2U;
- Parameters:
config – Pointer to configuration structure. See to dcdc_loop_control_config_t.
-
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
Configures the DCDC loop control.
- Parameters:
base – DCDC peripheral base address.
config – Pointer to configuration structure. See to dcdc_loop_control_config_t.
-
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
Configures the DCDC internal regulator.
- Parameters:
base – DCDC peripheral base address.
config – Pointer to configuration structure. See to dcdc_internal_regulator_config_t.
-
static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
Adjusts delay to reduce ground noise.
- Parameters:
base – DCDC peripheral base address.
enable – Enable the feature or not.
-
static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)
Get DCDC status flags.
- Parameters:
base – peripheral base address.
- Returns:
Mask of asserted status flags. See to _dcdc_status_flags.
-
void DCDC_BootIntoCCM(DCDC_Type *base)
Boots DCDC into CCM(continous conduction mode).
pwd_zcd=0x1; pwd_cmp_offset=0x0; dcdc_loopctrl_en_rcscale=0x3;
- Parameters:
base – DCDC peripheral base address.
-
enum _dcdc_status_flags
The enumeration of DCDC status flags.
Values:
-
enumerator kDCDC_AlreadySettledStatusFlag
Indicate DCDC status. 1’b1: DCDC already settled 1’b0: DCDC is settling.
-
enumerator kDCDC_AlreadySettledStatusFlag
-
enum _dcdc_core_slice
CORE slice.
Values:
-
enumerator kDCDC_CORE0
CORE slice 0.
-
enumerator kDCDC_CORE1
CORE slice 1.
-
enumerator kDCDC_CORE0
-
enum _dcdc_control_mode
DCDC control mode, including software control mode and GPC control mode.
Values:
-
enumerator kDCDC_SoftwareControl
Controlled by software.
-
enumerator kDCDC_GPCControl
Controlled by GPC.
-
enumerator kDCDC_SoftwareControl
-
enum _dcdc_trim_input_mode
DCDC trim input mode, including sample trim input and hold trim input.
Values:
-
enumerator kDCDC_SampleTrimInput
Sample trim input.
-
enumerator kDCDC_HoldTrimInput
Hold trim input.
-
enumerator kDCDC_SampleTrimInput
-
enum _dcdc_1P0_target_vol
The enumeration VDD1P0’s target voltage value.
Values:
-
enumerator kDCDC_1P0Target0P6V
The target voltage value of VDD1P0 is 0.6V.
-
enumerator kDCDC_1P0Target0P625V
The target voltage value of VDD1P0 is 0.625V.
-
enumerator kDCDC_1P0Target0P65V
The target voltage value of VDD1P0 is 0.65V.
-
enumerator kDCDC_1P0Target0P675V
The target voltage value of VDD1P0 is 0.675V.
-
enumerator kDCDC_1P0Target0P7V
The target voltage value of VDD1P0 is 0.7V.
-
enumerator kDCDC_1P0Target0P725V
The target voltage value of VDD1P0 is 0.725V.
-
enumerator kDCDC_1P0Target0P75V
The target voltage value of VDD1P0 is 0.75V.
-
enumerator kDCDC_1P0Target0P775V
The target voltage value of VDD1P0 is 0.775V.
-
enumerator kDCDC_1P0Target0P8V
The target voltage value of VDD1P0 is 0.8V.
-
enumerator kDCDC_1P0Target0P825V
The target voltage value of VDD1P0 is 0.825V.
-
enumerator kDCDC_1P0Target0P85V
The target voltage value of VDD1P0 is 0.85V.
-
enumerator kDCDC_1P0Target0P875V
The target voltage value of VDD1P0 is 0.875V.
-
enumerator kDCDC_1P0Target0P9V
The target voltage value of VDD1P0 is 0.9V.
-
enumerator kDCDC_1P0Target0P925V
The target voltage value of VDD1P0 is 0.925V.
-
enumerator kDCDC_1P0Target0P95V
The target voltage value of VDD1P0 is 0.95V.
-
enumerator kDCDC_1P0Target0P975V
The target voltage value of VDD1P0 is 0.975V.
-
enumerator kDCDC_1P0Target1P0V
The target voltage value of VDD1P0 is 1.0V.
-
enumerator kDCDC_1P0Target1P025V
The target voltage value of VDD1P0 is 1.025V.
-
enumerator kDCDC_1P0Target1P05V
The target voltage value of VDD1P0 is 1.05V.
-
enumerator kDCDC_1P0Target1P075V
The target voltage value of VDD1P0 is 1.075V.
-
enumerator kDCDC_1P0Target1P1V
The target voltage value of VDD1P0 is 1.1V.
-
enumerator kDCDC_1P0Target1P125V
The target voltage value of VDD1P0 is 1.125V.
-
enumerator kDCDC_1P0Target1P15V
The target voltage value of VDD1P0 is 1.15V.
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enumerator kDCDC_1P0Target1P175V
The target voltage value of VDD1P0 is 1.175V.
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enumerator kDCDC_1P0Target1P2V
The target voltage value of VDD1P0 is 1.2V.
-
enumerator kDCDC_1P0Target1P225V
The target voltage value of VDD1P0 is 1.225V.
-
enumerator kDCDC_1P0Target1P25V
The target voltage value of VDD1P0 is 1.25V.
-
enumerator kDCDC_1P0Target1P275V
The target voltage value of VDD1P0 is 1.275V.
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enumerator kDCDC_1P0Target1P3V
The target voltage value of VDD1P0 is 1.3V.
-
enumerator kDCDC_1P0Target1P325V
The target voltage value of VDD1P0 is 1.325V.
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enumerator kDCDC_1P0Target1P35V
The target voltage value of VDD1P0 is 1.35V.
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enumerator kDCDC_1P0Target1P375V
The target voltage value of VDD1P0 is 1.375V.
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enumerator kDCDC_1P0Target0P6V
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enum _dcdc_1P8_target_vol
The enumeration VDD1P8’s target voltage value.
Values:
-
enumerator kDCDC_1P8Target1P5V
The target voltage value of VDD1P8 is 1.5V.
-
enumerator kDCDC_1P8Target1P525V
The target voltage value of VDD1P8 is 1.525V.
-
enumerator kDCDC_1P8Target1P55V
The target voltage value of VDD1P8 is 1.55V.
-
enumerator kDCDC_1P8Target1P575V
The target voltage value of VDD1P8 is 1.575V.
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enumerator kDCDC_1P8Target1P6V
The target voltage value of VDD1P8 is 1.6V.
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enumerator kDCDC_1P8Target1P625V
The target voltage value of VDD1P8 is 1.625V.
-
enumerator kDCDC_1P8Target1P65V
The target voltage value of VDD1P8 is 1.65V.
-
enumerator kDCDC_1P8Target1P675V
The target voltage value of VDD1P8 is 1.675V.
-
enumerator kDCDC_1P8Target1P7V
The target voltage value of VDD1P8 is 1.7V.
-
enumerator kDCDC_1P8Target1P725V
The target voltage value of VDD1P8 is 1.725V.
-
enumerator kDCDC_1P8Target1P75V
The target voltage value of VDD1P8 is 1.75V.
-
enumerator kDCDC_1P8Target1P775V
The target voltage value of VDD1P8 is 1.775V.
-
enumerator kDCDC_1P8Target1P8V
The target voltage value of VDD1P8 is 1.8V.
-
enumerator kDCDC_1P8Target1P825V
The target voltage value of VDD1P8 is 1.825V.
-
enumerator kDCDC_1P8Target1P85V
The target voltage value of VDD1P8 is 1.85V.
-
enumerator kDCDC_1P8Target1P875V
The target voltage value of VDD1P8 is 1.875V.
-
enumerator kDCDC_1P8Target1P9V
The target voltage value of VDD1P8 is 1.9V.
-
enumerator kDCDC_1P8Target1P925V
The target voltage value of VDD1P8 is 1.925V.
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enumerator kDCDC_1P8Target1P95V
The target voltage value of VDD1P8 is 1.95V.
-
enumerator kDCDC_1P8Target1P975V
The target voltage value of VDD1P8 is 1.975V.
-
enumerator kDCDC_1P8Target2P0V
The target voltage value of VDD1P8 is 2.0V.
-
enumerator kDCDC_1P8Target2P025V
The target voltage value of VDD1P8 is 2.025V.
-
enumerator kDCDC_1P8Target2P05V
The target voltage value of VDD1P8 is 2.05V.
-
enumerator kDCDC_1P8Target2P075V
The target voltage value of VDD1P8 is 2.075V.
-
enumerator kDCDC_1P8Target2P1V
The target voltage value of VDD1P8 is 2.1V.
-
enumerator kDCDC_1P8Target2P125V
The target voltage value of VDD1P8 is 2.125V.
-
enumerator kDCDC_1P8Target2P15V
The target voltage value of VDD1P8 is 2.15V.
-
enumerator kDCDC_1P8Target2P175V
The target voltage value of VDD1P8 is 2.175V.
-
enumerator kDCDC_1P8Target2P2V
The target voltage value of VDD1P8 is 2.2V.
-
enumerator kDCDC_1P8Target2P225V
The target voltage value of VDD1P8 is 2.225V.
-
enumerator kDCDC_1P8Target2P25V
The target voltage value of VDD1P8 is 2.25V.
-
enumerator kDCDC_1P8Target2P275V
The target voltage value of VDD1P8 is 2.275V.
-
enumerator kDCDC_1P8Target1P5V
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enum _dcdc_comparator_current_bias
The current bias of low power comparator.
Values:
-
enumerator kDCDC_ComparatorCurrentBias50nA
The current bias of low power comparator is 50nA.
-
enumerator kDCDC_ComparatorCurrentBias100nA
The current bias of low power comparator is 100nA.
-
enumerator kDCDC_ComparatorCurrentBias200nA
The current bias of low power comparator is 200nA.
-
enumerator kDCDC_ComparatorCurrentBias400nA
The current bias of low power comparator is 400nA.
-
enumerator kDCDC_ComparatorCurrentBias50nA
-
enum _dcdc_peak_current_threshold
The threshold if peak current detection.
Values:
-
enumerator kDCDC_PeakCurrentRunMode250mALPMode1P5A
Over peak current threshold in low power mode is 250mA, in run mode is 1.5A
-
enumerator kDCDC_PeakCurrentRunMode200mALPMode1P5A
Over peak current threshold in low power mode is 200mA, in run mode is 1.5A
-
enumerator kDCDC_PeakCurrentRunMode250mALPMode2A
Over peak current threshold in low power mode is 250mA, in run mode is 2A
-
enumerator kDCDC_PeakCurrentRunMode200mALPMode2A
Over peak current threshold in low power mode is 200mA, in run mode is 2A
-
enumerator kDCDC_PeakCurrentRunMode250mALPMode1P5A
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enum _dcdc_clock_source
Oscillator clock option.
Values:
-
enumerator kDCDC_ClockAutoSwitch
Automatic clock switch from internal oscillator to external clock.
-
enumerator kDCDC_ClockInternalOsc
Use internal oscillator.
-
enumerator kDCDC_ClockExternalOsc
Use external 24M crystal oscillator.
-
enumerator kDCDC_ClockAutoSwitch
-
enum _dcdc_voltage_output_sel
Voltage output option.
Values:
-
enumerator kDCDC_VoltageOutput1P8
1.8V output.
-
enumerator kDCDC_VoltageOutput1P0
1.0V output.
-
enumerator kDCDC_VoltageOutput1P8
-
typedef enum _dcdc_core_slice dcdc_core_slice_t
CORE slice.
-
typedef enum _dcdc_control_mode dcdc_control_mode_t
DCDC control mode, including software control mode and GPC control mode.
-
typedef enum _dcdc_trim_input_mode dcdc_trim_input_mode_t
DCDC trim input mode, including sample trim input and hold trim input.
-
typedef enum _dcdc_1P0_target_vol dcdc_1P0_target_vol_t
The enumeration VDD1P0’s target voltage value.
-
typedef enum _dcdc_1P8_target_vol dcdc_1P8_target_vol_t
The enumeration VDD1P8’s target voltage value.
-
typedef enum _dcdc_comparator_current_bias dcdc_comparator_current_bias_t
The current bias of low power comparator.
-
typedef enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t
The threshold if peak current detection.
-
typedef enum _dcdc_clock_source dcdc_clock_source_t
Oscillator clock option.
-
typedef enum _dcdc_voltage_output_sel dcdc_voltage_output_sel_t
Voltage output option.
-
typedef struct _dcdc_config dcdc_config_t
Configuration for DCDC.
-
typedef struct _dcdc_min_power_config dcdc_min_power_config_t
Configuration for min power setting.
-
typedef struct _dcdc_detection_config dcdc_detection_config_t
Configuration for DCDC detection.
-
typedef struct _dcdc_loop_control_config dcdc_loop_control_config_t
Configuration for the loop control.
-
typedef struct _dcdc_internal_regulator_config dcdc_internal_regulator_config_t
Configuration for DCDC internal regulator.
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FSL_DCDC_DRIVER_VERSION
DCDC driver version.
Version 2.0.1.
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VDD1P0_TARGET_VOLTAGE
The array of VDD1P0 target voltage.
-
VDD1P8_TARGET_VOLTAGE
The array of VDD1P8 target voltage.
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struct _dcdc_config
- #include <fsl_dcdc.h>
Configuration for DCDC.
Public Members
-
dcdc_control_mode_t controlMode
DCDC control mode.
-
dcdc_trim_input_mode_t trimInputMode
Hold trim input.
-
dcdc_control_mode_t controlMode
-
struct _dcdc_min_power_config
- #include <fsl_dcdc.h>
Configuration for min power setting.
Public Members
-
bool enableUseHalfFreqForContinuous
Set DCDC clock to half frequency for the continuous mode.
-
bool enableUseHalfFreqForContinuous
-
struct _dcdc_detection_config
- #include <fsl_dcdc.h>
Configuration for DCDC detection.
Public Members
-
bool enableXtalokDetection
Enable xtalok detection circuit.
-
bool powerDownOverVoltageVdd1P8Detection
Power down over-voltage detection comparator for VDD1P8.
-
bool powerDownOverVoltageVdd1P0Detection
Power down over-voltage detection comparator for VDD1P0.
-
bool powerDownLowVoltageDetection
Power down low-voltage detection comparator.
-
bool powerDownOverCurrentDetection
Power down over-current detection.
-
bool enableXtalokDetection
-
struct _dcdc_loop_control_config
- #include <fsl_dcdc.h>
Configuration for the loop control.
Public Members
-
bool enableCommonHysteresis
Enable hysteresis in switching converter common mode analog comparators. This feature will improve transient supply ripple and efficiency.
-
bool enableCommonThresholdDetection
Increase the threshold detection for common mode analog comparator.
-
bool enableDifferentialHysteresis
Enable hysteresis in switching converter differential mode analog comparators. This feature will improve transient supply ripple and efficiency.
-
bool enableDifferentialThresholdDetection
Increase the threshold detection for differential mode analog comparators.
-
bool enableInvertHysteresisSign
Invert the sign of the hysteresis in DC-DC analog comparators.
-
bool enableRCThresholdDetection
Increase the threshold detection for RC scale circuit.
-
uint32_t enableRCScaleCircuit
Available range is 0~7. Enable analog circuit of DC-DC converter to respond faster under transient load conditions.
-
uint32_t complementFeedForwardStep
Available range is 0~7. Two’s complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional to the change. This can be used to force a certain control loop behavior, such as improving response under known heavy load transients.
-
uint32_t controlParameterMagnitude
Available range is 0~15. Magnitude of proportional control parameter in the switching DC-DC converter control loop.
-
uint32_t integralProportionalRatio
Available range is 0~3.Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response.
-
bool enableCommonHysteresis
-
struct _dcdc_internal_regulator_config
- #include <fsl_dcdc.h>
Configuration for DCDC internal regulator.
Public Members
-
uint32_t feedbackPoint
Available range is 0~3. Select the feedback point of the internal regulator.
-
uint32_t feedbackPoint
eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver
-
void EDMA_Init(EDMA_Type *base, const edma_config_t *config)
Initializes the eDMA peripheral.
This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.
Note
This function enables the minor loop map feature.
- Parameters:
base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.
-
void EDMA_Deinit(EDMA_Type *base)
Deinitializes the eDMA peripheral.
This function gates the eDMA clock.
- Parameters:
base – eDMA peripheral base address.
-
void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
Push content of TCD structure into hardware TCD register.
- Parameters:
base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.
-
void EDMA_GetDefaultConfig(edma_config_t *config)
Gets the eDMA default configuration structure.
This function sets the configuration structure to default values. The default configuration is set to the following values.
config.enableContinuousLinkMode = false; config.enableHaltOnError = true; config.enableRoundRobinArbitration = false; config.enableDebugMode = false;
- Parameters:
config – A pointer to the eDMA configuration structure.
-
void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)
EDMA Channel initialization.
- Parameters:
base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.
-
static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)
Set channel memory attribute.
- Parameters:
base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.
-
static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)
Set channel sign extension.
- Parameters:
base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.
-
static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)
Set channel swap size.
- Parameters:
base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.
-
static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)
Set channel access type.
- Parameters:
base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.
-
static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)
Set channel request source.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.
-
static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)
Gets the channel identification and attribute information on the system bus interface.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
- Returns:
The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.
-
static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)
Set channel master ID replication.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.
-
static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)
Set channel security level.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.
-
void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)
Sets all TCD registers to default values.
This function sets TCD registers for this channel to default values.
Note
This function must not be called while the channel transfer is ongoing or it causes unpredictable results.
Note
This function enables the auto stop request feature.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
-
void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Configures the eDMA transfer attribute.
This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:
edma_transfer_t config; edma_tcd_t tcd; config.srcAddr = ..; config.destAddr = ..; ... EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
Note
If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.
-
void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
Configures the eDMA minor offset feature.
The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.
-
void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)
Configures the eDMA channel preemption feature.
This function configures the channel preemption attribute and the priority of the channel.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.
-
void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
Sets the channel link for the eDMA transfer.
This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
Note
Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
kEDMA_LinkNone
kEDMA_MinorLink
kEDMA_MajorLink
linkedChannel – The linked channel number.
-
void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
Sets the bandwidth for the eDMA transfer.
Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
kEDMABandwidthStallNone
kEDMABandwidthStall4Cycle
kEDMABandwidthStall8Cycle
-
void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
Sets the source modulo and the destination modulo for the eDMA transfer.
This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.
-
static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)
Enables an async request for the eDMA transfer.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).
-
static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)
Enables an auto stop request for the eDMA transfer.
If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).
-
void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)
Enables the interrupt source for the eDMA transfer.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.
-
void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)
Disables the interrupt source for the eDMA transfer.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.
-
void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)
Configures the eDMA channel TCD major offset feature.
Adjustment value added to the source address at the completion of the major iteration count
- Parameters:
base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.
-
void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)
Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt
Application should be careful about the TCD pool buffer storage class,
For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.
Note
This function enables the auto stop request feature.
- Parameters:
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.
-
void EDMA_TcdReset(edma_tcd_t *tcd)
Sets all fields to default values for the TCD structure.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt
This function sets all fields for this TCD structure to default value.
Note
This function enables the auto stop request feature.
- Parameters:
tcd – Pointer to the TCD structure.
-
void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Configures the eDMA TCD transfer attribute.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt
The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:
edma_transfer_t config = { ... } edma_tcd_t tcd __aligned(32); edma_tcd_t nextTcd __aligned(32); EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
Note
TCD address should be 32 bytes aligned or it causes an eDMA error.
Note
If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.
- Parameters:
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.
-
void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
Configures the eDMA TCD minor offset feature.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt
A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.
- Parameters:
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.
-
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
Sets the channel link for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt
This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
Note
Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
- Parameters:
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
kEDMA_LinkNone
kEDMA_MinorLink
kEDMA_MajorLink
linkedChannel – The linked channel number.
-
static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
Sets the bandwidth for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt
Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.
- Parameters:
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
kEDMABandwidthStallNone
kEDMABandwidthStall4Cycle
kEDMABandwidthStall8Cycle
-
void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
Sets the source modulo and the destination modulo for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt
This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.
- Parameters:
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.
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static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
Sets the auto stop request for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt
If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
- Parameters:
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).
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void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
Enables the interrupt source for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt
- Parameters:
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.
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void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
Disables the interrupt source for the eDMA TCD.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt
- Parameters:
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.
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void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)
Configures the eDMA TCD major offset feature.
@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt
Adjustment value added to the source address at the completion of the major iteration count
- Parameters:
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.
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void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)
Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.
Application should be careful about the TCD pool buffer storage class,
For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.
Note
This function enables the auto stop request feature.
- Parameters:
base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.
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void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)
Sets all fields to default values for the TCD structure.
This function sets all fields for this TCD structure to default value.
Note
This function enables the auto stop request feature.
- Parameters:
base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
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void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Configures the eDMA TCD transfer attribute.
The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:
edma_transfer_t config = { ... } edma_tcd_t tcd __aligned(32); edma_tcd_t nextTcd __aligned(32); EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
Note
TCD address should be 32 bytes aligned or it causes an eDMA error.
Note
If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.
- Parameters:
base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.
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void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
Configures the eDMA TCD minor offset feature.
A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.
- Parameters:
base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.
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void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
Sets the channel link for the eDMA TCD.
This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
Note
Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
- Parameters:
base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
kEDMA_LinkNone
kEDMA_MinorLink
kEDMA_MajorLink
linkedChannel – The linked channel number.
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static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
Sets the bandwidth for the eDMA TCD.
Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.
- Parameters:
base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
kEDMABandwidthStallNone
kEDMABandwidthStall4Cycle
kEDMABandwidthStall8Cycle
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void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
Sets the source modulo and the destination modulo for the eDMA TCD.
This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.
- Parameters:
base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.
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static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)
Sets the auto stop request for the eDMA TCD.
If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
- Parameters:
base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).
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void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)
Enables the interrupt source for the eDMA TCD.
- Parameters:
base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.
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void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)
Disables the interrupt source for the eDMA TCD.
- Parameters:
base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.
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void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)
Configures the eDMA TCD major offset feature.
Adjustment value added to the source address at the completion of the major iteration count
- Parameters:
base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.
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static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)
Enables the eDMA hardware channel request.
This function enables the hardware channel request.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
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static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)
Disables the eDMA hardware channel request.
This function disables the hardware channel request.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
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static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)
Starts the eDMA transfer by using the software trigger.
This function starts a minor loop transfer.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
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uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)
Gets the remaining major loop count from the eDMA current channel TCD.
This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.
Note
1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.
The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
- Returns:
Major loop count which has not been transferred yet for the current TCD.
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static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)
Gets the eDMA channel error status flags.
- Parameters:
base – eDMA peripheral base address.
- Returns:
The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.
-
uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)
Gets the eDMA channel status flags.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
- Returns:
The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.
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void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)
Clears the eDMA channel status flags.
- Parameters:
base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.
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void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)
Creates the eDMA handle.
This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.
- Parameters:
handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.
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void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
Installs the TCDs memory pool into the eDMA handle.
This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
- Parameters:
handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.
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void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
Installs a callback function for the eDMA transfer.
This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.
- Parameters:
handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.
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void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)
Prepares the eDMA transfer structure configurations.
This function prepares the transfer configuration structure according to the user input.
Note
The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.
- Parameters:
config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
-
void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)
Prepares the eDMA transfer structure.
This function prepares the transfer configuration structure according to the user input.
Note
The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).
- Parameters:
config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.
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void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)
Prepares the eDMA transfer content descriptor.
This function prepares the transfer content descriptor structure according to the user input.
Note
The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).
- Parameters:
handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.
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status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)
Submits the eDMA transfer content descriptor.
This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.
Typical user case:
submit single transfer
edma_tcd_t tcd; EDMA_PrepareTransferTCD(handle, tcd, ....) EDMA_SubmitTransferTCD(handle, tcd) EDMA_StartTransfer(handle)
submit static link transfer,
edma_tcd_t tcd[2]; EDMA_PrepareTransferTCD(handle, &tcd[0], ....) EDMA_PrepareTransferTCD(handle, &tcd[1], ....) EDMA_SubmitTransferTCD(handle, &tcd[0]) EDMA_StartTransfer(handle)
submit dynamic link transfer
edma_tcd_t tcdpool[2]; EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); edma_tcd_t tcd; EDMA_PrepareTransferTCD(handle, tcd, ....) EDMA_SubmitTransferTCD(handle, tcd) EDMA_PrepareTransferTCD(handle, tcd, ....) EDMA_SubmitTransferTCD(handle, tcd) EDMA_StartTransfer(handle)
submit loop transfer
edma_tcd_t tcd[2]; EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) EDMA_SubmitTransferTCD(handle, &tcd[0]) EDMA_StartTransfer(handle)
- Parameters:
handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
- Return values:
kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.
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status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
Submits the eDMA transfer request.
This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.
- Parameters:
handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.
- Return values:
kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.
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status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)
Submits the eDMA scatter gather transfer configurations.
The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A
To use the ring transfer feature, the application should allocate several transfer object, such as
Then eDMA driver will link transfer[0] and transfer[1] to each otheredma_channel_transfer_config_t transfer[2]; EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);
Note
Application should check the return value of this function to avoid transfer request submit failed
- Parameters:
handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.
- Return values:
kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument
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void EDMA_StartTransfer(edma_handle_t *handle)
eDMA starts transfer.
This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.
- Parameters:
handle – eDMA handle pointer.
-
void EDMA_StopTransfer(edma_handle_t *handle)
eDMA stops transfer.
This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.
- Parameters:
handle – eDMA handle pointer.
-
void EDMA_AbortTransfer(edma_handle_t *handle)
eDMA aborts transfer.
This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.
- Parameters:
handle – DMA handle pointer.
-
static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)
Get unused TCD slot number.
This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.
- Parameters:
handle – DMA handle pointer.
- Returns:
The unused tcd slot number.
-
static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)
Get the next tcd address.
This function gets the next tcd address. If this is last TCD, return 0.
- Parameters:
handle – DMA handle pointer.
- Returns:
The next TCD address.
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void EDMA_HandleIRQ(edma_handle_t *handle)
eDMA IRQ handler for the current major loop transfer completion.
This function clears the channel major interrupt flag and calls the callback function if it is not NULL.
Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).
For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.
See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.
- Parameters:
handle – eDMA handle pointer.
-
FSL_EDMA_DRIVER_VERSION
eDMA driver version
Version 2.10.4.
_edma_transfer_status eDMA transfer status
Values:
-
enumerator kStatus_EDMA_QueueFull
TCD queue is full.
-
enumerator kStatus_EDMA_Busy
Channel is busy and can’t handle the transfer request.
-
enumerator kStatus_EDMA_QueueFull
-
enum _edma_transfer_size
eDMA transfer configuration
Values:
-
enumerator kEDMA_TransferSize1Bytes
Source/Destination data transfer size is 1 byte every time
-
enumerator kEDMA_TransferSize2Bytes
Source/Destination data transfer size is 2 bytes every time
-
enumerator kEDMA_TransferSize4Bytes
Source/Destination data transfer size is 4 bytes every time
-
enumerator kEDMA_TransferSize8Bytes
Source/Destination data transfer size is 8 bytes every time
-
enumerator kEDMA_TransferSize16Bytes
Source/Destination data transfer size is 16 bytes every time
-
enumerator kEDMA_TransferSize32Bytes
Source/Destination data transfer size is 32 bytes every time
-
enumerator kEDMA_TransferSize64Bytes
Source/Destination data transfer size is 64 bytes every time
-
enumerator kEDMA_TransferSize128Bytes
Source/Destination data transfer size is 128 bytes every time
-
enumerator kEDMA_TransferSize1Bytes
-
enum _edma_modulo
eDMA modulo configuration
Values:
-
enumerator kEDMA_ModuloDisable
Disable modulo
-
enumerator kEDMA_Modulo2bytes
Circular buffer size is 2 bytes.
-
enumerator kEDMA_Modulo4bytes
Circular buffer size is 4 bytes.
-
enumerator kEDMA_Modulo8bytes
Circular buffer size is 8 bytes.
-
enumerator kEDMA_Modulo16bytes
Circular buffer size is 16 bytes.
-
enumerator kEDMA_Modulo32bytes
Circular buffer size is 32 bytes.
-
enumerator kEDMA_Modulo64bytes
Circular buffer size is 64 bytes.
-
enumerator kEDMA_Modulo128bytes
Circular buffer size is 128 bytes.
-
enumerator kEDMA_Modulo256bytes
Circular buffer size is 256 bytes.
-
enumerator kEDMA_Modulo512bytes
Circular buffer size is 512 bytes.
-
enumerator kEDMA_Modulo1Kbytes
Circular buffer size is 1 K bytes.
-
enumerator kEDMA_Modulo2Kbytes
Circular buffer size is 2 K bytes.
-
enumerator kEDMA_Modulo4Kbytes
Circular buffer size is 4 K bytes.
-
enumerator kEDMA_Modulo8Kbytes
Circular buffer size is 8 K bytes.
-
enumerator kEDMA_Modulo16Kbytes
Circular buffer size is 16 K bytes.
-
enumerator kEDMA_Modulo32Kbytes
Circular buffer size is 32 K bytes.
-
enumerator kEDMA_Modulo64Kbytes
Circular buffer size is 64 K bytes.
-
enumerator kEDMA_Modulo128Kbytes
Circular buffer size is 128 K bytes.
-
enumerator kEDMA_Modulo256Kbytes
Circular buffer size is 256 K bytes.
-
enumerator kEDMA_Modulo512Kbytes
Circular buffer size is 512 K bytes.
-
enumerator kEDMA_Modulo1Mbytes
Circular buffer size is 1 M bytes.
-
enumerator kEDMA_Modulo2Mbytes
Circular buffer size is 2 M bytes.
-
enumerator kEDMA_Modulo4Mbytes
Circular buffer size is 4 M bytes.
-
enumerator kEDMA_Modulo8Mbytes
Circular buffer size is 8 M bytes.
-
enumerator kEDMA_Modulo16Mbytes
Circular buffer size is 16 M bytes.
-
enumerator kEDMA_Modulo32Mbytes
Circular buffer size is 32 M bytes.
-
enumerator kEDMA_Modulo64Mbytes
Circular buffer size is 64 M bytes.
-
enumerator kEDMA_Modulo128Mbytes
Circular buffer size is 128 M bytes.
-
enumerator kEDMA_Modulo256Mbytes
Circular buffer size is 256 M bytes.
-
enumerator kEDMA_Modulo512Mbytes
Circular buffer size is 512 M bytes.
-
enumerator kEDMA_Modulo1Gbytes
Circular buffer size is 1 G bytes.
-
enumerator kEDMA_Modulo2Gbytes
Circular buffer size is 2 G bytes.
-
enumerator kEDMA_ModuloDisable
-
enum _edma_bandwidth
Bandwidth control.
Values:
-
enumerator kEDMA_BandwidthStallNone
No eDMA engine stalls.
-
enumerator kEDMA_BandwidthStall4Cycle
eDMA engine stalls for 4 cycles after each read/write.
-
enumerator kEDMA_BandwidthStall8Cycle
eDMA engine stalls for 8 cycles after each read/write.
-
enumerator kEDMA_BandwidthStallNone
-
enum _edma_channel_link_type
Channel link type.
Values:
-
enumerator kEDMA_LinkNone
No channel link
-
enumerator kEDMA_MinorLink
Channel link after each minor loop
-
enumerator kEDMA_MajorLink
Channel link while major loop count exhausted
-
enumerator kEDMA_LinkNone
_edma_channel_status_flags eDMA channel status flags.
Values:
-
enumerator kEDMA_DoneFlag
DONE flag, set while transfer finished, CITER value exhausted
-
enumerator kEDMA_ErrorFlag
eDMA error flag, an error occurred in a transfer
-
enumerator kEDMA_InterruptFlag
eDMA interrupt flag, set while an interrupt occurred of this channel
-
enumerator kEDMA_DoneFlag
_edma_error_status_flags eDMA channel error status flags.
Values:
-
enumerator kEDMA_DestinationBusErrorFlag
Bus error on destination address
-
enumerator kEDMA_SourceBusErrorFlag
Bus error on the source address
-
enumerator kEDMA_ScatterGatherErrorFlag
Error on the Scatter/Gather address, not 32byte aligned.
-
enumerator kEDMA_NbytesErrorFlag
NBYTES/CITER configuration error
-
enumerator kEDMA_DestinationOffsetErrorFlag
Destination offset not aligned with destination size
-
enumerator kEDMA_DestinationAddressErrorFlag
Destination address not aligned with destination size
-
enumerator kEDMA_SourceOffsetErrorFlag
Source offset not aligned with source size
-
enumerator kEDMA_SourceAddressErrorFlag
Source address not aligned with source size
-
enumerator kEDMA_ErrorChannelFlag
Error channel number of the cancelled channel number
-
enumerator kEDMA_TransferCanceledFlag
Transfer cancelled
-
enumerator kEDMA_ValidFlag
No error occurred, this bit is 0. Otherwise, it is 1.
-
enumerator kEDMA_DestinationBusErrorFlag
_edma_interrupt_enable eDMA interrupt source
Values:
-
enumerator kEDMA_ErrorInterruptEnable
Enable interrupt while channel error occurs.
-
enumerator kEDMA_MajorInterruptEnable
Enable interrupt while major count exhausted.
-
enumerator kEDMA_HalfInterruptEnable
Enable interrupt while major count to half value.
-
enumerator kEDMA_ErrorInterruptEnable
-
enum _edma_transfer_type
eDMA transfer type
Values:
-
enumerator kEDMA_MemoryToMemory
Transfer from memory to memory
-
enumerator kEDMA_PeripheralToMemory
Transfer from peripheral to memory
-
enumerator kEDMA_MemoryToPeripheral
Transfer from memory to peripheral
-
enumerator kEDMA_PeripheralToPeripheral
Transfer from Peripheral to peripheral
-
enumerator kEDMA_MemoryToMemory
-
enum edma_channel_memory_attribute
eDMA channel memory attribute
Values:
-
enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer
No write allocate, no read allocate, non-cacheable, non-bufferable.
-
enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable
No write allocate, no read allocate, non-cacheable, bufferable.
-
enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer
No write allocate, no read allocate, cacheable, non-bufferable.
-
enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable
No write allocate, no read allocate, cacheable, bufferable.
-
enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer
No write allocate, read allocate, non-cacheable, non-bufferable.
-
enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable
No write allocate, read allocate, non-cacheable, bufferable.
-
enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer
No write allocate, read allocate, cacheable, non-bufferable.
-
enumerator kEDMA_ChannelNoWriteReadCacheableBufferable
No write allocate, read allocate, cacheable, bufferable.
-
enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer
write allocate, no read allocate, non-cacheable, non-bufferable.
-
enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable
write allocate, no read allocate, non-cacheable, bufferable.
-
enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer
write allocate, no read allocate, cacheable, non-bufferable.
-
enumerator kEDMA_ChannelWriteNoReadCacheableBufferable
write allocate, no read allocate, cacheable, bufferable.
-
enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer
write allocate, read allocate, non-cacheable, non-bufferable.
-
enumerator kEDMA_ChannelWriteReadNoCacheBufferable
write allocate, read allocate, non-cacheable, bufferable.
-
enumerator kEDMA_ChannelWriteReadCacheableNoBuffer
write allocate, read allocate, cacheable, non-bufferable.
-
enumerator kEDMA_ChannelWriteReadCacheableBufferable
write allocate, read allocate, cacheable, bufferable.
-
enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer
-
enum _edma_channel_swap_size
eDMA4 channel swap size
Values:
-
enumerator kEDMA_ChannelSwapDisabled
Swap is disabled.
-
enumerator kEDMA_ChannelReadWith8bitSwap
Swap occurs with respect to the read 8bit.
-
enumerator kEDMA_ChannelReadWith16bitSwap
Swap occurs with respect to the read 16bit.
-
enumerator kEDMA_ChannelReadWith32bitSwap
Swap occurs with respect to the read 32bit.
-
enumerator kEDMA_ChannelWriteWith8bitSwap
Swap occurs with respect to the write 8bit.
-
enumerator kEDMA_ChannelWriteWith16bitSwap
Swap occurs with respect to the write 16bit.
-
enumerator kEDMA_ChannelWriteWith32bitSwap
Swap occurs with respect to the write 32bit.
-
enumerator kEDMA_ChannelSwapDisabled
eDMA channel system bus information, _edma_channel_sys_bus_info
Values:
-
enumerator kEDMA_PrivilegedAccessLevel
Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.
-
enumerator kEDMA_MasterId
DMA’s master ID when channel is active and master ID replication is enabled.
-
enumerator kEDMA_PrivilegedAccessLevel
-
enum _edma_channel_access_type
eDMA4 channel access type
Values:
-
enumerator kEDMA_ChannelDataAccess
Data access for eDMA4 transfers.
-
enumerator kEDMA_ChannelInstructionAccess
Instruction access for eDMA4 transfers.
-
enumerator kEDMA_ChannelDataAccess
-
enum _edma_channel_protection_level
eDMA4 channel protection level
Values:
-
enumerator kEDMA_ChannelProtectionLevelUser
user protection level for eDMA transfers.
-
enumerator kEDMA_ChannelProtectionLevelPrivileged
Privileged protection level eDMA transfers.
-
enumerator kEDMA_ChannelProtectionLevelUser
-
typedef enum _edma_transfer_size edma_transfer_size_t
eDMA transfer configuration
-
typedef enum _edma_modulo edma_modulo_t
eDMA modulo configuration
-
typedef enum _edma_bandwidth edma_bandwidth_t
Bandwidth control.
-
typedef enum _edma_channel_link_type edma_channel_link_type_t
Channel link type.
-
typedef enum _edma_transfer_type edma_transfer_type_t
eDMA transfer type
-
typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t
eDMA channel priority configuration
-
typedef struct _edma_minor_offset_config edma_minor_offset_config_t
eDMA minor offset configuration
-
typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t
eDMA channel memory attribute
-
typedef enum _edma_channel_swap_size edma_channel_swap_size_t
eDMA4 channel swap size
-
typedef enum _edma_channel_access_type edma_channel_access_type_t
eDMA4 channel access type
-
typedef enum _edma_channel_protection_level edma_channel_protection_level_t
eDMA4 channel protection level
-
typedef struct _edma_channel_config edma_channel_config_t
eDMA4 channel configuration
-
typedef edma_core_tcd_t edma_tcd_t
eDMA TCD.
This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.
-
typedef struct _edma_transfer_config edma_transfer_config_t
edma4 channel transfer configuration
The transfer configuration structure support full feature configuration of the transfer control descriptor.
1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission
2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature
Note
User should pay attention to the transfer size alignment limitation
the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.
-
typedef struct _edma_config edma_config_t
eDMA global configuration structure.
-
typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)
Define callback function for eDMA.
This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
- Param handle:
EDMA handle pointer, users shall not touch the values inside.
- Param userData:
The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
- Param transferDone:
If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
- Param tcds:
How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.
-
typedef struct _edma_handle edma_handle_t
eDMA transfer handle structure
-
FSL_EDMA_DRIVER_EDMA4
eDMA driver name
-
EDMA_ALLOCATE_TCD(name, number)
Macro used for allocate edma TCD.
-
DMA_DCHPRI_INDEX(channel)
Compute the offset unit from DCHPRI3.
-
struct _edma_channel_Preemption_config
- #include <fsl_edma.h>
eDMA channel priority configuration
Public Members
-
bool enableChannelPreemption
If true: a channel can be suspended by other channel with higher priority
-
bool enablePreemptAbility
If true: a channel can suspend other channel with low priority
-
uint8_t channelPriority
Channel priority
-
bool enableChannelPreemption
-
struct _edma_minor_offset_config
- #include <fsl_edma.h>
eDMA minor offset configuration
Public Members
-
bool enableSrcMinorOffset
Enable(true) or Disable(false) source minor loop offset.
-
bool enableDestMinorOffset
Enable(true) or Disable(false) destination minor loop offset.
-
uint32_t minorOffset
Offset for a minor loop mapping.
-
bool enableSrcMinorOffset
-
struct _edma_channel_config
- #include <fsl_edma.h>
eDMA4 channel configuration
Public Members
-
edma_channel_Preemption_config_t channelPreemptionConfig
channel preemption configuration
-
edma_channel_memory_attribute_t channelReadMemoryAttribute
channel memory read attribute configuration
-
edma_channel_memory_attribute_t channelWriteMemoryAttribute
channel memory write attribute configuration
-
edma_channel_swap_size_t channelSwapSize
channel swap size configuration
-
edma_channel_access_type_t channelAccessType
channel access type configuration
-
uint8_t channelDataSignExtensionBitPosition
channel data sign extension bit psition configuration
-
uint32_t channelRequestSource
hardware service request source for the channel
-
bool enableMasterIDReplication
enable master ID replication
-
edma_channel_protection_level_t protectionLevel
protection level
-
edma_channel_Preemption_config_t channelPreemptionConfig
-
struct _edma_transfer_config
- #include <fsl_edma.h>
edma4 channel transfer configuration
The transfer configuration structure support full feature configuration of the transfer control descriptor.
1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission
2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature
Note
User should pay attention to the transfer size alignment limitation
the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.
Public Members
-
uint32_t srcAddr
Source data address.
-
uint32_t destAddr
Destination data address.
-
edma_transfer_size_t srcTransferSize
Source data transfer size.
-
edma_transfer_size_t destTransferSize
Destination data transfer size.
-
int16_t srcOffset
Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed
-
int16_t destOffset
Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.
-
uint32_t minorLoopBytes
bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled
-
uint32_t majorLoopCounts
minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop
-
uint16_t enabledInterruptMask
channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable
-
edma_modulo_t srcAddrModulo
source circular data queue range
-
int32_t srcMajorLoopOffset
source major loop offset
-
edma_modulo_t dstAddrModulo
destination circular data queue range
-
int32_t dstMajorLoopOffset
destination major loop offset
-
bool enableSrcMinorLoopOffset
enable source minor loop offset
-
bool enableDstMinorLoopOffset
enable dest minor loop offset
-
int32_t minorLoopOffset
burst offset, the offset will be applied after minor loop update
-
bool enableChannelMajorLoopLink
channel link when major loop complete
-
uint32_t majorLoopLinkChannel
major loop link channel number
-
bool enableChannelMinorLoopLink
channel link when minor loop complete
-
uint32_t minorLoopLinkChannel
minor loop link channel number
-
edma_tcd_t *linkTCD
pointer to the link transfer control descriptor
-
struct _edma_config
- #include <fsl_edma.h>
eDMA global configuration structure.
Public Members
-
bool enableContinuousLinkMode
Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.
-
bool enableMasterIdReplication
Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.
-
bool enableGlobalChannelLink
Enable(true) channel linking is available and controlled by each channel’s link settings.
-
bool enableHaltOnError
Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
-
bool enableDebugMode
Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.
-
bool enableRoundRobinArbitration
Enable(true) channel linking is available and controlled by each channel’s link settings.
-
edma_channel_config_t *channelConfig[1]
channel preemption configuration
-
bool enableContinuousLinkMode
-
struct _edma_handle
- #include <fsl_edma.h>
eDMA transfer handle structure
Public Members
-
edma_callback callback
Callback function for major count exhausted.
-
void *userData
Callback function parameter.
-
EDMA_ChannelType *channelBase
eDMA peripheral channel base address.
-
EDMA_Type *base
eDMA peripheral base address
-
EDMA_TCDType *tcdBase
eDMA peripheral tcd base address.
-
edma_tcd_t *tcdPool
Pointer to memory stored TCDs.
-
uint32_t channel
eDMA channel number.
-
volatile int8_t header
The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.
-
volatile int8_t tail
The last TCD index. Should point to the next TCD to be stored into the memory pool.
-
volatile int8_t tcdUsed
The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.
-
volatile int8_t tcdSize
The total number of TCD slots in the queue.
-
edma_callback callback
eDMA core Driver
-
enum _edma_tcd_type
eDMA tcd flag type
Values:
-
enumerator kEDMA_EDMA4Flag
Data access for eDMA4 transfers.
-
enumerator kEDMA_EDMA5Flag
Instruction access for eDMA4 transfers.
-
enumerator kEDMA_EDMA4Flag
-
typedef struct _edma_core_mp edma_core_mp_t
edma core channel struture definition
-
typedef struct _edma_core_channel edma_core_channel_t
edma core channel struture definition
-
typedef enum _edma_tcd_type edma_tcd_type_t
eDMA tcd flag type
-
typedef struct _edma5_core_tcd edma5_core_tcd_t
edma5 core TCD struture definition
-
typedef struct _edma4_core_tcd edma4_core_tcd_t
edma4 core TCD struture definition
-
typedef struct _edma_core_tcd edma_core_tcd_t
edma core TCD struture definition
-
typedef edma_core_channel_t EDMA_ChannelType
EDMA typedef.
-
typedef edma_core_tcd_t EDMA_TCDType
-
typedef void EDMA_Type
-
DMA_CORE_MP_CSR_EDBG_MASK
-
DMA_CORE_MP_CSR_ERCA_MASK
-
DMA_CORE_MP_CSR_HAE_MASK
-
DMA_CORE_MP_CSR_HALT_MASK
-
DMA_CORE_MP_CSR_GCLC_MASK
-
DMA_CORE_MP_CSR_GMRC_MASK
-
DMA_CORE_MP_CSR_EDBG(x)
-
DMA_CORE_MP_CSR_ERCA(x)
-
DMA_CORE_MP_CSR_HAE(x)
-
DMA_CORE_MP_CSR_HALT(x)
-
DMA_CORE_MP_CSR_GCLC(x)
-
DMA_CORE_MP_CSR_GMRC(x)
-
DMA_CSR_INTMAJOR_MASK
-
DMA_CSR_INTHALF_MASK
-
DMA_CSR_DREQ_MASK
-
DMA_CSR_ESG_MASK
-
DMA_CSR_BWC_MASK
-
DMA_CSR_BWC(x)
-
DMA_CSR_START_MASK
-
DMA_CITER_ELINKNO_CITER_MASK
-
DMA_BITER_ELINKNO_BITER_MASK
-
DMA_CITER_ELINKNO_CITER_SHIFT
-
DMA_CITER_ELINKYES_CITER_MASK
-
DMA_CITER_ELINKYES_CITER_SHIFT
-
DMA_ATTR_SMOD_MASK
-
DMA_ATTR_DMOD_MASK
-
DMA_CITER_ELINKNO_ELINK_MASK
-
DMA_CSR_MAJORELINK_MASK
-
DMA_BITER_ELINKYES_ELINK_MASK
-
DMA_CITER_ELINKYES_ELINK_MASK
-
DMA_CSR_MAJORLINKCH_MASK
-
DMA_BITER_ELINKYES_LINKCH_MASK
-
DMA_CITER_ELINKYES_LINKCH_MASK
-
DMA_NBYTES_MLOFFYES_MLOFF_MASK
-
DMA_NBYTES_MLOFFYES_DMLOE_MASK
-
DMA_NBYTES_MLOFFYES_SMLOE_MASK
-
DMA_NBYTES_MLOFFNO_NBYTES_MASK
-
DMA_ATTR_DMOD(x)
-
DMA_ATTR_SMOD(x)
-
DMA_BITER_ELINKYES_LINKCH(x)
-
DMA_CITER_ELINKYES_LINKCH(x)
-
DMA_NBYTES_MLOFFYES_MLOFF(x)
-
DMA_NBYTES_MLOFFYES_DMLOE(x)
-
DMA_NBYTES_MLOFFYES_SMLOE(x)
-
DMA_NBYTES_MLOFFNO_NBYTES(x)
-
DMA_NBYTES_MLOFFYES_NBYTES(x)
-
DMA_ATTR_DSIZE(x)
-
DMA_ATTR_SSIZE(x)
-
DMA_CSR_DREQ(x)
-
DMA_CSR_MAJORLINKCH(x)
-
DMA_CH_MATTR_WCACHE(x)
-
DMA_CH_MATTR_RCACHE(x)
-
DMA_CH_CSR_SIGNEXT_MASK
-
DMA_CH_CSR_SIGNEXT_SHIFT
-
DMA_CH_CSR_SWAP_MASK
-
DMA_CH_CSR_SWAP_SHIFT
-
DMA_CH_SBR_INSTR_MASK
-
DMA_CH_SBR_INSTR_SHIFT
-
DMA_CH_MUX_SOURCE(x)
-
DMA_ERR_DBE_FLAG
DMA error flag.
-
DMA_ERR_SBE_FLAG
-
DMA_ERR_SGE_FLAG
-
DMA_ERR_NCE_FLAG
-
DMA_ERR_DOE_FLAG
-
DMA_ERR_DAE_FLAG
-
DMA_ERR_SOE_FLAG
-
DMA_ERR_SAE_FLAG
-
DMA_ERR_ERRCHAN_FLAG
-
DMA_ERR_ECX_FLAG
-
DMA_ERR_FLAG
-
DMA_CLEAR_DONE_STATUS(base, channel)
get/clear DONE bit
-
DMA_GET_DONE_STATUS(base, channel)
-
DMA_ENABLE_ERROR_INT(base, channel)
enable/disable error interupt
-
DMA_DISABLE_ERROR_INT(base, channel)
-
DMA_CLEAR_ERROR_STATUS(base, channel)
get/clear error status
-
DMA_GET_ERROR_STATUS(base, channel)
-
DMA_CLEAR_INT_STATUS(base, channel)
get/clear INT status
-
DMA_GET_INT_STATUS(base, channel)
-
DMA_ENABLE_MAJOR_INT(base, channel)
enable/dsiable MAJOR/HALF INT
-
DMA_ENABLE_HALF_INT(base, channel)
-
DMA_DISABLE_MAJOR_INT(base, channel)
-
DMA_DISABLE_HALF_INT(base, channel)
-
EDMA_TCD_ALIGN_SIZE
EDMA tcd align size.
-
EDMA_CORE_BASE(base)
EDMA base address convert macro.
-
EDMA_MP_BASE(base)
-
EDMA_CHANNEL_BASE(base, channel)
-
EDMA_TCD_BASE(base, channel)
-
EDMA_TCD_TYPE(x)
EDMA TCD type macro.
-
EDMA_TCD_SADDR(tcd, flag)
EDMA TCD address convert macro.
-
EDMA_TCD_SOFF(tcd, flag)
-
EDMA_TCD_ATTR(tcd, flag)
-
EDMA_TCD_NBYTES(tcd, flag)
-
EDMA_TCD_SLAST(tcd, flag)
-
EDMA_TCD_DADDR(tcd, flag)
-
EDMA_TCD_DOFF(tcd, flag)
-
EDMA_TCD_CITER(tcd, flag)
-
EDMA_TCD_DLAST_SGA(tcd, flag)
-
EDMA_TCD_CSR(tcd, flag)
-
EDMA_TCD_BITER(tcd, flag)
-
struct _edma_core_mp
- #include <fsl_edma_core.h>
edma core channel struture definition
Public Members
- __IO uint32_t MP_CSR
Channel Control and Status, array offset: 0x10000, array step: 0x10000
- __IO uint32_t MP_ES
Channel Error Status, array offset: 0x10004, array step: 0x10000
-
struct _edma_core_channel
- #include <fsl_edma_core.h>
edma core channel struture definition
Public Members
- __IO uint32_t CH_CSR
Channel Control and Status, array offset: 0x10000, array step: 0x10000
- __IO uint32_t CH_ES
Channel Error Status, array offset: 0x10004, array step: 0x10000
- __IO uint32_t CH_INT
Channel Interrupt Status, array offset: 0x10008, array step: 0x10000
- __IO uint32_t CH_SBR
Channel System Bus, array offset: 0x1000C, array step: 0x10000
- __IO uint32_t CH_PRI
Channel Priority, array offset: 0x10010, array step: 0x10000
-
struct _edma5_core_tcd
- #include <fsl_edma_core.h>
edma5 core TCD struture definition
Public Members
- __IO uint32_t SADDR
SADDR register, used to save source address
- __IO uint32_t SADDR_HIGH
SADDR HIGH register, used to save source address
- __IO uint16_t SOFF
SOFF register, save offset bytes every transfer
- __IO uint16_t ATTR
ATTR register, source/destination transfer size and modulo
- __IO uint32_t NBYTES
Nbytes register, minor loop length in bytes
- __IO uint32_t SLAST
SLAST register
- __IO uint32_t SLAST_SDA_HIGH
SLAST SDA HIGH register
- __IO uint32_t DADDR
DADDR register, used for destination address
- __IO uint32_t DADDR_HIGH
DADDR HIGH register, used for destination address
- __IO uint32_t DLAST_SGA
DLASTSGA register, next tcd address used in scatter-gather mode
- __IO uint32_t DLAST_SGA_HIGH
DLASTSGA HIGH register, next tcd address used in scatter-gather mode
- __IO uint16_t DOFF
DOFF register, used for destination offset
- __IO uint16_t CITER
CITER register, current minor loop numbers, for unfinished minor loop.
- __IO uint16_t CSR
CSR register, for TCD control status
- __IO uint16_t BITER
BITER register, begin minor loop count.
-
uint8_t RESERVED[16]
Aligned 64 bytes
-
struct _edma4_core_tcd
- #include <fsl_edma_core.h>
edma4 core TCD struture definition
Public Members
- __IO uint32_t SADDR
SADDR register, used to save source address
- __IO uint16_t SOFF
SOFF register, save offset bytes every transfer
- __IO uint16_t ATTR
ATTR register, source/destination transfer size and modulo
- __IO uint32_t NBYTES
Nbytes register, minor loop length in bytes
- __IO uint32_t SLAST
SLAST register
- __IO uint32_t DADDR
DADDR register, used for destination address
- __IO uint16_t DOFF
DOFF register, used for destination offset
- __IO uint16_t CITER
CITER register, current minor loop numbers, for unfinished minor loop.
- __IO uint32_t DLAST_SGA
DLASTSGA register, next tcd address used in scatter-gather mode
- __IO uint16_t CSR
CSR register, for TCD control status
- __IO uint16_t BITER
BITER register, begin minor loop count.
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struct _edma_core_tcd
- #include <fsl_edma_core.h>
edma core TCD struture definition
-
union MP_REGS
Public Members
-
struct _edma_core_mp EDMA5_REG
-
struct _edma_core_mp EDMA5_REG
-
struct EDMA5_REG
Public Members
- __IO uint32_t MP_INT_LOW
Channel Control and Status, array offset: 0x10008, array step: 0x10000
- __I uint32_t MP_INT_HIGH
Channel Control and Status, array offset: 0x1000C, array step: 0x10000
- __I uint32_t MP_HRS_LOW
Channel Control and Status, array offset: 0x10010, array step: 0x10000
- __I uint32_t MP_HRS_HIGH
Channel Control and Status, array offset: 0x10014, array step: 0x10000
- __IO uint32_t MP_STOPCH
Channel Control and Status, array offset: 0x10020, array step: 0x10000
- __I uint32_t MP_SSR_LOW
Channel Control and Status, array offset: 0x10030, array step: 0x10000
- __I uint32_t MP_SSR_HIGH
Channel Control and Status, array offset: 0x10034, array step: 0x10000
- __IO uint32_t CH_GRPRI [64]
Channel Control and Status, array offset: 0x10100, array step: 0x10000
- __IO uint32_t CH_MUX [64]
Channel Control and Status, array offset: 0x10200, array step: 0x10000
- __IO uint32_t CH_PROT [64]
Channel Control and Status, array offset: 0x10400, array step: 0x10000
-
union CH_REGS
-
struct EDMA5_REG
Public Members
- __IO uint32_t CH_MATTR
Memory Attributes Register, array offset: 0x10018, array step: 0x8000
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struct EDMA4_REG
Public Members
- __IO uint32_t CH_MUX
Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000
- __IO uint16_t CH_MATTR
Memory Attributes Register, array offset: 0x10018, array step: 0x8000
-
union TCD_REGS
Public Members
-
edma4_core_tcd_t edma4_tcd
-
edma4_core_tcd_t edma4_tcd
eDMA soc Driver
-
FSL_EDMA_SOC_DRIVER_VERSION
Driver version 2.1.0.
-
FSL_EDMA_SOC_IP_DMA3
DMA IP version.
-
FSL_EDMA_SOC_IP_DMA4
-
EDMA_BASE_PTRS
DMA base table.
-
EDMA_CHN_IRQS
Verify dma base and request source
-
EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source)
-
EDMA_CHANNEL_OFFSET
EDMA base address convert macro.
-
EDMA_CHANNEL_ARRAY_STEP(base)
Ele_base_api
-
status_t ELE_BaseAPI_Ping(S3MU_Type *mu)
Ping ELE.
This function Ping EdgeLock Enclave, can be sent at any time to verify ELE is alive. Additionally, this command reloads the fuse shadow registers and kick the Sentinel active bit. This active bit must be kicked at least once every day (24 hours).
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_GetFwVersion(S3MU_Type *mu, uint32_t *EleFwVersion)
Get ELE FW Version.
This function is used to retrieve the Sentinel FW version.
- Parameters:
mu – MU peripheral base address
EleFwVersion – Pointer where ElE firmware version will be stored
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_GetFwStatus(S3MU_Type *mu, uint32_t *EleFwStatus)
Get ELE FW Status.
This function is used to retrieve the Sentinel FW status.
- Parameters:
mu – MU peripheral base address
EleFwStatus – Pointer where ElE firmware status will be stored
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_EnableAPC(S3MU_Type *mu)
Enable APC (Application core)
This function is used by RTC (real time core) to release APC (Application core) when needed.
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
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status_t ELE_BaseAPI_ForwardLifecycle(S3MU_Type *mu, uint32_t Lifecycle)
Forward Lifecycle update.
This function is to change chip lifecycle 0x01U for NXP provisoned 0x02U for OEM Open 0x08U for OEM Closed 0x80U for OEM Locked
- Parameters:
mu – MU peripheral base address
Lifecycle – to switch
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
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status_t ELE_BaseAPI_ReleaseRDC(S3MU_Type *mu, uint32_t RdcID, uint32_t CoreID)
Release RDC.
This function is used to release specifed RDC to the core identified in this function. The RDC will be released only if the FW of the core to which is the RDC ownership is going to be transferred has been properly authenticated and verified.
- Parameters:
mu – MU peripheral base address
RdcID – Resource Domain Control identifier
CoreID – Core identifier
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_StartRng(S3MU_Type *mu)
Start the initialization of the RNG context.
The RNG must be started before using some of the ELE services.
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
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status_t ELE_BaseAPI_EnableOtfad(S3MU_Type *mu, uint8_t OtfadID)
Enable an instance of OTFAD.
- Parameters:
mu – MU peripheral base address
OtfadID – ID of the OTFAD instance to enable - used only if there are multiple instances on the SoC
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_ClockChangeStart(S3MU_Type *mu)
Start the clock change process.
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_ClockChangeFinish(S3MU_Type *mu, uint8_t NewClockRateELE, uint8_t NewClockRateCM33)
Change ELE and/or CM33 clock.
It is valid to pass both parameters at the same time if the SoC supports both.
- Parameters:
mu – MU peripheral base address
NewClockRateELE – the new clock rate for ELE
NewClockRateCM33 – the new clock rate for the CM33 core
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
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status_t ELE_BaseAPI_VoltageChangeStart(S3MU_Type *mu)
Start the voltage change process.
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t ELE_BaseAPI_VoltageChangeFinish(S3MU_Type *mu)
Finish the voltage change process.
- Parameters:
mu – MU peripheral base address
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
FSL_ELE_BASE_API_DRIVER_VERSION
Defines ELE Base API version 1.0.0.
Change log:
Version 1.0.0
initial version
-
RESPONSE_SUCCESS
-
SHIFT_16
-
SHIFT_8
-
MSG_RESPONSE_MAX
-
MSG_TAG_CMD
-
MSG_TAG_RESP
-
PING
-
PING_SIZE
-
PING_RESPONSE_HDR
-
GET_FW_VERSION
-
GET_FW_VERSION_SIZE
-
GET_FW_VERSION_RESPONSE_HDR
-
CLOCK_CHANGE_START
-
CLOCK_CHANGE_START_SIZE
-
CLOCK_CHANGE_START_RESPONSE_HDR
-
CLOCK_CHANGE_FINISH
-
CLOCK_CHANGE_FINISH_SIZE
-
CLOCK_CHANGE_FINISH_RESPONSE_HDR
-
VOLTAGE_CHANGE_START
-
VOLTAGE_CHANGE_START_SIZE
-
VOLTAGE_CHANGE_START_RESPONSE_HDR
-
VOLTAGE_CHANGE_FINISH
-
VOLTAGE_CHANGE_FINISH_SIZE
-
VOLTAGE_CHANGE_FINISH_RESPONSE_HDR
-
GET_FW_STATUS
-
GET_FW_STATUS_SIZE
-
GET_FW_STATUS_RESPONSE_HDR
-
ENABLE_APC
-
ENABLE_APC_SIZE
-
ENABLE_APC_RESPONSE_HDR
-
START_RNG
-
START_RNG_SIZE
-
START_RNG_RESPONSE_HDR
-
FORWARD_LIFECYCLE
-
FORWARD_LIFECYCLE_SIZE
-
FORWARD_LIFECYCLE_RESPONSE_HDR
-
ENABLE_OTFAD
-
ENABLE_OTFAD_SIZE
-
ENABLE_OTFAD_RESPONSE_HDR
-
RELEASE_RDC
-
RELEASE_RDC_SIZE
-
RELEASE_RDC_RESPONSE_HDR
EQDC: Enhanced Quadrature Encoder/Decoder
-
void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
Initializes the EQDC module.
This function initializes the EQDC by enabling the IP bus clock (optional).
- Parameters:
base – EQDC peripheral base address.
psConfig – Pointer to configuration structure.
-
void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)
Gets an available pre-defined configuration.
The default value are:
psConfig->enableReverseDirection = false; psConfig->countOnce = false; psConfig->operateMode = kEQDC_QuadratureDecodeOperationMode; psConfig->countMode = kEQDC_QuadratureX4; psConfig->homeEnableInitPosCounterMode = kEQDC_HomeInitPosCounterDisabled; psConfig->indexPresetInitPosCounterMode = kEQDC_IndexInitPosCounterDisabled; psConfig->enableIndexInitPositionCounter = false; psConfig->enableDma = false; psConfig->bufferedRegisterLoadMode = false; psConfig->enableTriggerInitPositionCounter = false; psConfig->enableTriggerClearPositionRegisters = false; psConfig->enableTriggerHoldPositionRegisters = false; psConfig->enableWatchdog = false; psConfig->watchdogTimeoutValue = 0xFFFFU; psConfig->filterPhaseA = 0U; psConfig->filterPhaseB = 0U; psConfig->filterIndPre = 0U; psConfig->filterHomEna = 0U; psConfig->filterClockSourceselection = false; psConfig->filterSampleCount = kEQDC_Filter3Samples; psConfig->filterSamplePeriod = 0U; psConfig->outputPulseMode = kEQDC_OutputPulseOnCounterEqualCompare; psConfig->positionCompareValue[0] = 0xFFFFFFFFU; psConfig->positionCompareValue[1] = 0xFFFFFFFFU; psConfig->positionCompareValue[2] = 0xFFFFFFFFU; psConfig->positionCompareValue[3] = 0xFFFFFFFFU; psConfig->revolutionCountCondition = kEQDC_RevolutionCountOnIndexPulse; psConfig->positionModulusValue = 0U; psConfig->positionInitialValue = 0U; psConfig->positionCounterValue = 0U; psConfig->enablePeriodMeasurement = false; psConfig->prescaler = kEQDC_Prescaler1; psConfig->enabledInterruptsMask = 0U;
- Parameters:
psConfig – Pointer to configuration structure.
-
void EQDC_Deinit(EQDC_Type *base)
De-initializes the EQDC module.
This function deinitializes the EQDC by disabling the IP bus clock (optional).
- Parameters:
base – EQDC peripheral base address.
-
void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)
Initializes the mode of operation.
This function initializes mode of operation by enabling the IP bus clock (optional).
- Parameters:
base – EQDC peripheral base address.
operateMode – Select operation mode.
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static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode)
Initializes the mode of count.
These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved
- Parameters:
base – EQDC peripheral base address.
countMode – Select count mode.
-
static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable)
Enable watchdog for EQDC module.
- Parameters:
base – EQDC peripheral base address
bEnable – Enables or disables the watchdog
-
static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout)
Set watchdog timeout value.
- Parameters:
base – EQDC peripheral base address
u16Timeout – Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out
-
static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable)
Enable DMA for EQDC module.
- Parameters:
base – EQDC peripheral base address
bEnable – Enables or disables the DMA
-
static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base)
Set Buffered Register Load (Update) Mode.
This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
-
static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base)
Clear Buffered Register Load (Update) Mode.
Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
-
static inline void EQDC_SetEqdcLdok(EQDC_Type *base)
Set load okay.
Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.
- Parameters:
base – EQDC peripheral base address.
-
static inline uint8_t EQDC_GetEqdcLdok(EQDC_Type *base)
Get load okay.
- Parameters:
base – EQDC peripheral base address.
-
static inline void EQDC_ClearEqdcLdok(EQDC_Type *base)
Clear load okay.
- Parameters:
base – EQDC peripheral base address.
-
static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base)
Get the status flags.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Logical OR’ed value of the status flags, _eqdc_status_flags.
-
static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags)
Clear the status flags.
- Parameters:
base – EQDC peripheral base address.
u32Flags – Logical OR’ed value of the flags to clear, _eqdc_status_flags.
-
static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base)
Get the signals’ real-time status.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Logical OR’ed value of the real-time signal status, _eqdc_signal_status.
-
static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base)
Get the direction of the last count.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Direction of the last count.
-
static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)
Enable the interrupts.
- Parameters:
base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.
-
static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)
Disable the interrupts.
- Parameters:
base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.
-
static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base)
Load the initial position value to position counter.
Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.
- Parameters:
base – EQDC peripheral base address.
-
static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue)
Set initial position value for EQDC module.
Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
u32PositionInitValue – Position initial value
-
static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue)
Set position counter value.
Set the position counter value (POS or UPOS, LPOS).
- Parameters:
base – EQDC peripheral base address
positionCounterValue – Position counter value
-
static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue)
Set position counter modulus value.
Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
positionModulusValue – Position modulus value
-
static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value)
Set position counter compare 0 value.
Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
u32PositionComp0Value – Position modulus value
-
static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value)
Set position counter compare 1 value.
Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
u32PositionComp1Value – Position modulus value
-
static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value)
Set position counter compare 2 value.
Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
u32PositionComp2Value – Position modulus value
-
static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value)
Set position counter compare 3 value.
Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:
If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.
- Parameters:
base – EQDC peripheral base address
u32PositionComp3Value – Position modulus value
-
static inline uint32_t EQDC_GetPosition(EQDC_Type *base)
Get the current position counter’s value.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Current position counter’s value.
-
static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base)
Get the hold position counter’s value.
The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:
Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position counter’s value.
-
static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base)
Get the hold position counter1’s value.
The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position counter1’s value.
-
static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base)
Get the hold position counter2’s value.
The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position counter2’s value.
-
static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base)
Get the hold position counter3’s value.
The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position counter3’s value.
-
static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base)
Get the position difference counter’s value.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The position difference counter’s value.
-
static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base)
Get the hold position difference counter’s value.
The position difference (POSD) value is loaded to hold position difference (POSDH) when:
Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.
TRIGGER happens and TRIGGER is enabled to update the hold registers.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position difference counter’s value.
-
static inline uint16_t EQDC_GetRevolution(EQDC_Type *base)
Get the revolution counter’s value.
Get the revolution counter (REV) value.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The revolution counter’s value.
-
static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base)
Get the hold revolution counter’s value.
The revolution counter (REV) value is loaded to hold revolution (REVH) when:
Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold position revolution counter’s value.
-
static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base)
Get the last edge time.
Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The last edge time.
-
static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base)
Get the hold last edge time.
The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.
- Parameters:
base – EQDC peripheral base address.
- Returns:
Hold of last edge time.
-
static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base)
Get the Position Difference Period counter value.
The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The position difference period counter value.
-
static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base)
Get buffered Position Difference Period counter value.
The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The buffered position difference period counter value.
-
static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)
Get Hold Position Difference Period counter value.
The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.
- Parameters:
base – EQDC peripheral base address.
- Returns:
The hold position difference period counter value.
-
enum _eqdc_status_flags
EQDC status flags, these flags indicate the counter’s events. .
Values:
-
enumerator kEQDC_HomeEnableTransitionFlag
HOME/ENABLE signal transition occured.
-
enumerator kEQDC_IndexPresetPulseFlag
INDEX/PRESET pulse occured.
-
enumerator kEQDC_WatchdogTimeoutFlag
Watchdog timeout occured.
-
enumerator kEQDC_SimultPhaseChangeFlag
Simultaneous change of PHASEA and PHASEB occured.
-
enumerator kEQDC_CountDirectionChangeFlag
Count direction change interrupt enable.
-
enumerator kEQDC_PositionRollOverFlag
Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.
-
enumerator kEQDC_PositionRollUnderFlag
Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.
-
enumerator kEQDC_PositionCompare0Flag
Position counter match the COMP0 value.
-
enumerator kEQDC_PositionCompare1Flag
Position counter match the COMP1 value.
-
enumerator kEQDC_PositionCompare2Flag
Position counter match the COMP2 value.
-
enumerator kEQDC_PositionCompare3Flag
Position counter match the COMP3 value.
-
enumerator kEQDC_StatusAllFlags
-
enumerator kEQDC_HomeEnableTransitionFlag
-
enum _eqdc_signal_status
Signal status, these flags indicate the raw and filtered input signal status. .
Values:
-
enumerator kEQDC_SignalStatusRawHomeEnable
Raw HOME/ENABLE input.
-
enumerator kEQDC_SignalStatusRawIndexPreset
Raw INDEX/PRESET input.
-
enumerator kEQDC_SignalStatusRawPhaseB
Raw PHASEB input.
-
enumerator kEQDC_SignalStatusRawPhaseA
Raw PHASEA input.
-
enumerator kEQDC_SignalStatusFilteredHomeEnable
The filtered HOME/ENABLE input.
-
enumerator kEQDC_SignalStatusFilteredIndexPreset
The filtered INDEX/PRESET input.
-
enumerator kEQDC_SignalStatusFilteredPhaseB
The filtered PHASEB input.
-
enumerator kEQDC_SignalStatusFilteredPhaseA
The filtered PHASEA input.
-
enumerator kEQDC_SignalStatusPositionCompare0Flag
Position Compare 0 Flag Output.
-
enumerator kEQDC_SignalStatusPositionCompare1Flag
Position Compare 1 Flag Output.
-
enumerator kEQDC_SignalStatusPositionCompare2Flag
Position Compare 2 Flag Output.
-
enumerator kEQDC_SignalStatusPositionCompare3Flag
Position Compare 3 Flag Output.
-
enumerator kEQDC_SignalStatusCountDirectionFlagHold
Count Direction Flag Hold.
-
enumerator kEQDC_SignalStatusCountDirectionFlag
Count Direction Flag Output.
-
enumerator kEQDC_SignalStatusAllFlags
-
enumerator kEQDC_SignalStatusRawHomeEnable
-
enum _eqdc_interrupt_enable
Interrupt enable/disable mask. .
Values:
-
enumerator kEQDC_HomeEnableTransitionInterruptEnable
HOME/ENABLE signal transition interrupt enable.
-
enumerator kEQDC_IndexPresetPulseInterruptEnable
INDEX/PRESET pulse interrupt enable.
-
enumerator kEQDC_WatchdogTimeoutInterruptEnable
Watchdog timeout interrupt enable.
-
enumerator kEQDC_SimultPhaseChangeInterruptEnable
Simultaneous PHASEA and PHASEB change interrupt enable.
-
enumerator kEQDC_CountDirectionChangeInterruptEnable
Count direction change interrupt enable.
-
enumerator kEQDC_PositionRollOverInterruptEnable
Roll-over interrupt enable.
-
enumerator kEQDC_PositionRollUnderInterruptEnable
Roll-under interrupt enable.
-
enumerator kEQDC_AllInterruptEnable
-
enumerator kEQDC_HomeEnableTransitionInterruptEnable
-
enum _eqdc_home_enable_init_pos_counter_mode
Define HOME/ENABLE signal’s trigger mode.
Values:
-
enumerator kEQDC_HomeInitPosCounterDisabled
Don’t use HOME/ENABLE signal to initialize the position counter.
-
enumerator kEQDC_HomeInitPosCounterOnRisingEdge
Use positive going edge to trigger initialization of position counters.
-
enumerator kEQDC_HomeInitPosCounterOnFallingEdge
Use negative going edge to trigger initialization of position counters.
-
enumerator kEQDC_HomeInitPosCounterDisabled
-
enum _eqdc_index_preset_init_pos_counter_mode
Define INDEX/PRESET signal’s trigger mode.
Values:
-
enumerator kEQDC_IndexInitPosCounterDisabled
INDEX/PRESET pulse does not initialize the position counter.
-
enumerator kEQDC_IndexInitPosCounterOnRisingEdge
Use INDEX/PRESET pulse rising edge to initialize position counter.
-
enumerator kEQDC_IndexInitPosCounterOnFallingEdge
Use INDEX/PRESET pulse falling edge to initialize position counter.
-
enumerator kEQDC_IndexInitPosCounterDisabled
-
enum _eqdc_operate_mode
Define type for decoder opertion mode.
The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.
Values:
-
enumerator kEQDC_QuadratureDecodeOperationMode
Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.
-
enumerator kEQDC_QuadratureCountOperationMode
Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.
-
enumerator kEQDC_SinglePhaseDecodeOperationMode
Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.
-
enumerator kEQDC_SinglePhaseCountOperationMode
Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.
-
enumerator kEQDC_QuadratureDecodeOperationMode
-
enum _eqdc_count_mode
Define type for decoder count mode.
In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.
If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.
Values:
-
enumerator kEQDC_QuadratureX4
Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
-
enumerator kEQDC_QuadratureX2
Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
-
enumerator kEQDC_QuadratureX1
Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.
-
enumerator kEQDC_UpDownPulseCount
Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.
-
enumerator kEQDC_SignedCountDoubleEdge
Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.
-
enumerator kEQDC_SignedCountSingleEdge
Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.
-
enum _eqdc_output_pulse_mode
Define type for the condition of POSMATCH pulses.
Values:
-
enumerator kEQDC_OutputPulseOnCounterEqualCompare
POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).
-
enumerator kEQDC_OutputPulseOnReadingPositionCounter
POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).
-
enumerator kEQDC_OutputPulseOnCounterEqualCompare
-
enum _eqdc_revolution_count_condition
Define type for determining how the revolution counter (REV) is incremented/decremented.
Values:
-
enumerator kEQDC_RevolutionCountOnIndexPulse
Use INDEX pulse to increment/decrement revolution counter.
-
enumerator kEQDC_RevolutionCountOnRollOverModulus
Use modulus counting roll-over/under to increment/decrement revolution counter.
-
enumerator kEQDC_RevolutionCountOnIndexPulse
-
enum _eqdc_filter_sample_count
Input Filter Sample Count.
The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition
Values:
-
enumerator kEQDC_Filter3Samples
3 samples.
-
enumerator kEQDC_Filter4Samples
4 samples.
-
enumerator kEQDC_Filter5Samples
5 samples.
-
enumerator kEQDC_Filter6Samples
6 samples.
-
enumerator kEQDC_Filter7Samples
7 samples.
-
enumerator kEQDC_Filter8Samples
8 samples.
-
enumerator kEQDC_Filter9Samples
9 samples.
-
enumerator kEQDC_Filter10Samples
10 samples.
-
enumerator kEQDC_Filter3Samples
-
enum _eqdc_count_direction_flag
Count direction.
Values:
-
enumerator kEQDC_CountDirectionDown
Last count was in down direction.
-
enumerator kEQDC_CountDirectionUp
Last count was in up direction.
-
enumerator kEQDC_CountDirectionDown
-
enum _eqdc_prescaler
Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).
Values:
-
enumerator kEQDC_Prescaler1
Prescaler value 1.
-
enumerator kEQDC_Prescaler2
Prescaler value 2.
-
enumerator kEQDC_Prescaler4
Prescaler value 4.
-
enumerator kEQDC_Prescaler8
Prescaler value 8.
-
enumerator kEQDC_Prescaler16
Prescaler value 16.
-
enumerator kEQDC_Prescaler32
Prescaler value 32.
-
enumerator kEQDC_Prescaler64
Prescaler value 64.
-
enumerator kEQDC_Prescaler128
Prescaler value 128.
-
enumerator kEQDC_Prescaler256
Prescaler value 256.
-
enumerator kEQDC_Prescaler512
Prescaler value 512.
-
enumerator kEQDC_Prescaler1024
Prescaler value 1024.
-
enumerator kEQDC_Prescaler2048
Prescaler value 2048.
-
enumerator kEQDC_Prescaler4096
Prescaler value 4096.
-
enumerator kEQDC_Prescaler8192
Prescaler value 8192.
-
enumerator kEQDC_Prescaler16384
Prescaler value 16384.
-
enumerator kEQDC_Prescaler32768
Prescaler value 32768.
-
enumerator kEQDC_Prescaler1
-
typedef enum _eqdc_home_enable_init_pos_counter_mode eqdc_home_enable_init_pos_counter_mode_t
Define HOME/ENABLE signal’s trigger mode.
-
typedef enum _eqdc_index_preset_init_pos_counter_mode eqdc_index_preset_init_pos_counter_mode_t
Define INDEX/PRESET signal’s trigger mode.
-
typedef enum _eqdc_operate_mode eqdc_operate_mode_t
Define type for decoder opertion mode.
The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.
-
typedef enum _eqdc_count_mode eqdc_count_mode_t
Define type for decoder count mode.
In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.
If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.
-
typedef enum _eqdc_output_pulse_mode eqdc_output_pulse_mode_t
Define type for the condition of POSMATCH pulses.
-
typedef enum _eqdc_revolution_count_condition eqdc_revolution_count_condition_t
Define type for determining how the revolution counter (REV) is incremented/decremented.
-
typedef enum _eqdc_filter_sample_count eqdc_filter_sample_count_t
Input Filter Sample Count.
The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition
-
typedef enum _eqdc_count_direction_flag eqdc_count_direction_flag_t
Count direction.
-
typedef enum _eqdc_prescaler eqdc_prescaler_t
Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).
-
typedef struct _eqdc_config eqdc_config_t
Define user configuration structure for EQDC module.
-
FSL_EQDC_DRIVER_VERSION
-
EQDC_CTRL_W1C_FLAGS
W1C bits in EQDC CTRL registers.
-
EQDC_INTCTRL_W1C_FLAGS
W1C bits in EQDC INTCTRL registers.
-
EQDC_CTRL_INT_EN
Interrupt enable bits in EQDC CTRL registers.
-
EQDC_INTCTRL_INT_EN
Interrupt enable bits in EQDC INTCTRL registers.
-
EQDC_CTRL_INT_FLAGS
Interrupt flag bits in EQDC CTRL registers.
-
EQDC_INTCTRL_INT_FLAGS
Interrupt flag bits in EQDC INTCTRL registers.
-
struct _eqdc_config
- #include <fsl_eqdc.h>
Define user configuration structure for EQDC module.
Public Members
-
bool enableReverseDirection
Enable reverse direction counting.
-
bool countOnce
Selects modulo loop or one shot counting mode.
-
bool enableDma
Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)
-
bool bufferedRegisterLoadMode
selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD).
-
bool enableTriggerInitPositionCounter
Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER’s rising edge.
-
bool enableIndexInitPositionCounter
Enables the feature that the position counter to be initialized by Index Event Edge Mark.
This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:
When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.
When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.
-
bool enableTriggerClearPositionRegisters
Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER’s rising edge.
-
bool enableTriggerHoldPositionRegisters
Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER’s rising edge.
-
bool filterPhaseA
Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed.
-
bool filterPhaseB
Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed.
-
bool filterIndPre
Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed.
-
bool filterHomEna
Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed.
-
bool enableWatchdog
Enable the watchdog to detect if the target is moving or not.
-
uint16_t watchdogTimeoutValue
Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer.
-
eqdc_prescaler_t prescaler
Prescaler.
-
bool filterClockSourceselection
Filter Clock Source selection.
-
eqdc_filter_sample_count_t filterSampleCount
Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.
-
uint8_t filterSamplePeriod
Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.
-
eqdc_operate_mode_t operateMode
Selects operation mode.
-
eqdc_count_mode_t countMode
Selects count mode.
-
eqdc_home_enable_init_pos_counter_mode_t homeEnableInitPosCounterMode
Select how HOME/Enable signal used to initialize position counters.
-
eqdc_index_preset_init_pos_counter_mode_t indexPresetInitPosCounterMode
Select how INDEX/Preset signal used to initialize position counters.
-
eqdc_output_pulse_mode_t outputPulseMode
The condition of POSMATCH pulses.
-
uint32_t positionCompareValue[4]
Position compare 0 ~ 3 value. The available value is a 32-bit number.
-
eqdc_revolution_count_condition_t revolutionCountCondition
Revolution Counter Modulus Enable.
-
uint32_t positionModulusValue
Position modulus value. The available value is a 32-bit number.
-
uint32_t positionInitialValue
Position initial value. The available value is a 32-bit number.
-
uint32_t positionCounterValue
Position counter value. When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.
-
bool enablePeriodMeasurement
Enable period measurement. When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.
-
uint16_t enabledInterruptsMask
Mask of interrupts to be enabled, should be OR’ed value of _eqdc_interrupt_enable.
-
bool enableReverseDirection
EWM: External Watchdog Monitor Driver
-
void EWM_Init(EWM_Type *base, const ewm_config_t *config)
Initializes the EWM peripheral.
This function is used to initialize the EWM. After calling, the EWM runs immediately according to the configuration. Note that, except for the interrupt enable control bit, other control bits and registers are write once after a CPU reset. Modifying them more than once generates a bus transfer error.
This is an example.
ewm_config_t config; EWM_GetDefaultConfig(&config); config.compareHighValue = 0xAAU; EWM_Init(ewm_base,&config);
- Parameters:
base – EWM peripheral base address
config – The configuration of the EWM
-
void EWM_Deinit(EWM_Type *base)
Deinitializes the EWM peripheral.
This function is used to shut down the EWM.
- Parameters:
base – EWM peripheral base address
-
void EWM_GetDefaultConfig(ewm_config_t *config)
Initializes the EWM configuration structure.
This function initializes the EWM configuration structure to default values. The default values are as follows.
ewmConfig->enableEwm = true; ewmConfig->enableEwmInput = false; ewmConfig->setInputAssertLogic = false; ewmConfig->enableInterrupt = false; ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; ewmConfig->prescaler = 0; ewmConfig->compareLowValue = 0; ewmConfig->compareHighValue = 0xFEU;
See also
ewm_config_t
- Parameters:
config – Pointer to the EWM configuration structure.
-
static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)
Enables the EWM interrupt.
This function enables the EWM interrupt.
- Parameters:
base – EWM peripheral base address
mask – The interrupts to enable The parameter can be combination of the following source if defined
kEWM_InterruptEnable
-
static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)
Disables the EWM interrupt.
This function enables the EWM interrupt.
- Parameters:
base – EWM peripheral base address
mask – The interrupts to disable The parameter can be combination of the following source if defined
kEWM_InterruptEnable
-
static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
Gets all status flags.
This function gets all status flags.
This is an example for getting the running flag.
uint32_t status; status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;
See also
_ewm_status_flags_t
True: a related status flag has been set.
False: a related status flag is not set.
- Parameters:
base – EWM peripheral base address
- Returns:
State of the status flag: asserted (true) or not-asserted (false).
-
void EWM_Refresh(EWM_Type *base)
Services the EWM.
This function resets the EWM counter to zero.
- Parameters:
base – EWM peripheral base address
-
FSL_EWM_DRIVER_VERSION
EWM driver version 2.0.3.
-
enum _ewm_lpo_clock_source
Describes EWM clock source.
Values:
-
enumerator kEWM_LpoClockSource0
EWM clock sourced from lpo_clk[0]
-
enumerator kEWM_LpoClockSource1
EWM clock sourced from lpo_clk[1]
-
enumerator kEWM_LpoClockSource2
EWM clock sourced from lpo_clk[2]
-
enumerator kEWM_LpoClockSource3
EWM clock sourced from lpo_clk[3]
-
enumerator kEWM_LpoClockSource0
-
enum _ewm_interrupt_enable_t
EWM interrupt configuration structure with default settings all disabled.
This structure contains the settings for all of EWM interrupt configurations.
Values:
-
enumerator kEWM_InterruptEnable
Enable the EWM to generate an interrupt
-
enumerator kEWM_InterruptEnable
-
enum _ewm_status_flags_t
EWM status flags.
This structure contains the constants for the EWM status flags for use in the EWM functions.
Values:
-
enumerator kEWM_RunningFlag
Running flag, set when EWM is enabled
-
enumerator kEWM_RunningFlag
-
typedef enum _ewm_lpo_clock_source ewm_lpo_clock_source_t
Describes EWM clock source.
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typedef struct _ewm_config ewm_config_t
Data structure for EWM configuration.
This structure is used to configure the EWM.
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struct _ewm_config
- #include <fsl_ewm.h>
Data structure for EWM configuration.
This structure is used to configure the EWM.
Public Members
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bool enableEwm
Enable EWM module
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bool enableEwmInput
Enable EWM_in input
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bool setInputAssertLogic
EWM_in signal assertion state
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bool enableInterrupt
Enable EWM interrupt
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ewm_lpo_clock_source_t clockSource
Clock source select
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uint8_t prescaler
Clock prescaler value
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uint8_t compareLowValue
Compare low-register value
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uint8_t compareHighValue
Compare high-register value
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bool enableEwm
FGPIO Driver
FlexCAN: Flex Controller Area Network Driver
FlexCAN Driver
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bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)
Determine whether the FlexCAN instance support CAN FD mode at run time.
Note
Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.
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void FLEXCAN_EnterFreezeMode(CAN_Type *base)
Enter FlexCAN Freeze Mode.
This function makes the FlexCAN work under Freeze Mode.
- Parameters:
base – FlexCAN peripheral base address.
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void FLEXCAN_ExitFreezeMode(CAN_Type *base)
Exit FlexCAN Freeze Mode.
This function makes the FlexCAN leave Freeze Mode.
- Parameters:
base – FlexCAN peripheral base address.
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uint32_t FLEXCAN_GetInstance(CAN_Type *base)
Get the FlexCAN instance from peripheral base address.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
FlexCAN instance.
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bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)
Calculates the improved timing values by specific bit Rates for classical CAN.
This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.
- Parameters:
base – FlexCAN peripheral base address.
bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.
- Returns:
TRUE if timing configuration found, FALSE if failed to find configuration.
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void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)
Initializes a FlexCAN instance.
This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.
flexcan_config_t flexcanConfig; flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig.bitRate = 1000000U; flexcanConfig.maxMbNum = 16; flexcanConfig.enableLoopBack = false; flexcanConfig.enableSelfWakeup = false; flexcanConfig.enableIndividMask = false; flexcanConfig.enableDoze = false; flexcanConfig.disableSelfReception = false; flexcanConfig.enableListenOnlyMode = false; flexcanConfig.timingConfig = timingConfig; FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.
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bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)
Calculates the improved timing values by specific bit rates for CANFD.
This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.
- Parameters:
base – FlexCAN peripheral base address.
bitRate – The CANFD bus control speed in bps defined by user.
bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.
- Returns:
TRUE if timing configuration found, FALSE if failed to find configuration
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void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)
Initializes a FlexCAN instance.
This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.
flexcan_config_t flexcanConfig; flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig.bitRate = 1000000U; flexcanConfig.bitRateFD = 2000000U; flexcanConfig.maxMbNum = 16; flexcanConfig.enableLoopBack = false; flexcanConfig.enableSelfWakeup = false; flexcanConfig.enableIndividMask = false; flexcanConfig.disableSelfReception = false; flexcanConfig.enableListenOnlyMode = false; flexcanConfig.enableDoze = false; flexcanConfig.timingConfig = timingConfig; FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.
dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.
brs – True if bit rate switch is enabled in FD mode.
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void FLEXCAN_Deinit(CAN_Type *base)
De-initializes a FlexCAN instance.
This function disables the FlexCAN module clock and sets all register values to the reset value.
- Parameters:
base – FlexCAN peripheral base address.
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void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)
Gets the default configuration structure.
This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;
- Parameters:
pConfig – Pointer to the FlexCAN configuration structure.
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void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)
Sets the FlexCAN classical CAN protocol timing characteristic.
This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.
Note
Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.
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status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)
Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.
This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.
Note
Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().
- Parameters:
base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRate_Bps – Bit rate in Bps.
- Returns:
kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.
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void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)
Sets the FlexCAN CANFD data phase timing characteristic.
This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.
Note
Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.
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status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)
Set bit rate of FlexCAN FD frame.
This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.
- Parameters:
base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRateN_Bps – Nominal bit Rate in Bps.
bitRateD_Bps – Data bit Rate in Bps.
- Returns:
kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.
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void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
Sets the FlexCAN receive message buffer global mask.
This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
- Parameters:
base – FlexCAN peripheral base address.
mask – Rx Message Buffer Global Mask value.
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void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
Sets the FlexCAN receive FIFO global mask.
This function sets the global mask for FlexCAN FIFO in a matching process.
- Parameters:
base – FlexCAN peripheral base address.
mask – Rx Fifo Global Mask value.
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void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
Sets the FlexCAN receive individual mask.
This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.
- Parameters:
base – FlexCAN peripheral base address.
maskIdx – The Index of individual Mask.
mask – Rx Individual Mask value.
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void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
Configures a FlexCAN transmit message buffer.
This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
true: Enable Tx Message Buffer.
false: Disable Tx Message Buffer.
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void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)
Configures a FlexCAN Receive Message Buffer.
This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
true: Enable Rx Message Buffer.
false: Disable Rx Message Buffer.
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void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
Configures a FlexCAN transmit message buffer.
This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
true: Enable Tx Message Buffer.
false: Disable Tx Message Buffer.
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void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)
Configures a FlexCAN Receive Message Buffer.
This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
true: Enable Rx Message Buffer.
false: Disable Rx Message Buffer.
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void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)
Configures a FlexCAN Remote Response Message Buffer.
User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pFrame – Pointer to CAN message frame structure for response.
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void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)
Configures the FlexCAN Legacy Rx FIFO.
This function configures the FlexCAN Rx FIFO with given configuration.
Note
Legacy Rx FIFO only can receive classic CAN message.
- Parameters:
base – FlexCAN peripheral base address.
pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Legacy Rx FIFO.
true: Enable Legacy Rx FIFO.
false: Disable Legacy Rx FIFO.
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void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable)
Configures the FlexCAN Enhanced Rx FIFO.
This function configures the Enhanced Rx FIFO with given configuration.
Note
Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time.
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Enhanced Rx FIFO.
true: Enable Enhanced Rx FIFO.
false: Disable Enhanced Rx FIFO.
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void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)
Configures the FlexCAN Pretended Networking mode.
This function configures the FlexCAN Pretended Networking mode with given configuration.
- Parameters:
base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.
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static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)
Gets the FlexCAN module interrupt flags.
This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.
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static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)
Clears status flags with the provided mask.
This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.
- Parameters:
base – FlexCAN peripheral base address.
mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.
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static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
Gets the FlexCAN Bus Error Counter value.
This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.
- Parameters:
base – FlexCAN peripheral base address.
txErrBuf – Buffer to store Tx Error Counter value.
rxErrBuf – Buffer to store Rx Error Counter value.
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static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)
Gets the FlexCAN Message Buffer interrupt flags.
This function gets the interrupt flags of a given Message Buffers.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
- Returns:
The status of given Message Buffers.
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static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
Gets the FlexCAN High 64 Message Buffer interrupt flags.
Valid only if the number of available MBs exceeds 64.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
- Returns:
The status of given Message Buffers.
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static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)
Clears the FlexCAN Message Buffer interrupt flags.
This function clears the interrupt flags of a given Message Buffers.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
Clears the FlexCAN High 64 Message Buffer interrupt flags.
Valid only if the number of available MBs exceeds 64.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)
Gets the FlexCAN Memory Error Report registers status.
This function gets the FlexCAN Memory Error Report registers status.
- Parameters:
base – FlexCAN peripheral base address.
errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.
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static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)
Gets the FlexCAN Number of Matches when in Pretended Networking.
This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
The number of received wake up msessages.
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static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
Gets the number of FlexCAN Enhanced Rx FIFO available frames.
This function gets the number of CAN messages stored in the Enhanced Rx FIFO.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
The number of available CAN messages stored in the Enhanced Rx FIFO.
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static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
Enables FlexCAN interrupts according to the provided mask.
This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.
- Parameters:
base – FlexCAN peripheral base address.
mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.
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static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
Disables FlexCAN interrupts according to the provided mask.
This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.
- Parameters:
base – FlexCAN peripheral base address.
mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.
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static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
Enables FlexCAN Message Buffer interrupts.
This function enables the interrupts of given Message Buffers.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
Enables FlexCAN high 64 Message Buffer interrupts.
Valid only if the number of available MBs exceeds 64.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
Disables FlexCAN Message Buffer interrupts.
This function disables the interrupts of given Message Buffers.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
Disables FlexCAN high 64 Message Buffer interrupts.
Valid only if the number of available MBs exceeds 64.
- Parameters:
base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.
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void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
Enables or disables the FlexCAN Rx FIFO DMA request.
This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.
- Parameters:
base – FlexCAN peripheral base address.
enable – true to enable, false to disable.
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static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
Gets the Rx FIFO Head address.
This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.
- Parameters:
base – FlexCAN peripheral base address.
- Returns:
FlexCAN Rx FIFO Head address.
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static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
Enables or disables the FlexCAN module operation.
This function enables or disables the FlexCAN module.
- Parameters:
base – FlexCAN base pointer.
enable – true to enable, false to disable.
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status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)
Writes a FlexCAN Message to the Transmit Message Buffer.
This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.
- Return values:
kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
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status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)
Reads a FlexCAN Message from Receive Message Buffer.
This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.
- Return values:
kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
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status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)
Writes a FlexCAN FD Message to the Transmit Message Buffer.
This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.
- Return values:
kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
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status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)
Reads a FlexCAN FD Message from Receive Message Buffer.
This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.
- Parameters:
base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.
- Return values:
kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
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status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)
Reads a FlexCAN Message from Legacy Rx FIFO.
This function reads a CAN message from the FlexCAN Legacy Rx FIFO.
- Parameters:
base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.
- Return values:
kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
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status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)
Reads a FlexCAN Message from Enhanced Rx FIFO.
This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.
- Parameters:
base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN FD message frame structure for reception.
- Return values:
kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
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status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)
Reads a FlexCAN Message from Wake Up MB.
This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.
- Parameters:
base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.
mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.
- Return values:
kStatus_Success – - Read Message from Wake up Message Buffer successfully.
kStatus_Fail – - Wake up Message Buffer has no valid content.
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status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)
Performs a polling send transaction on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.
- Return values:
kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
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status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)
Performs a polling receive transaction on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.
- Return values:
kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
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status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)
Sends a message using IRQ.
This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.
- Return values:
kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.
-
status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)
Receives a message using IRQ.
This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.
- Return values:
kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.
-
void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
Aborts the interrupt driven message send process.
This function aborts the interrupt driven message send process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.
-
void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
Aborts the interrupt driven message receive process.
This function aborts the interrupt driven message receive process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.
-
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)
Performs a polling send transaction on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.
- Return values:
kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
-
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)
Performs a polling receive transaction on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.
- Return values:
kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
-
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)
Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN message frame structure for reception.
- Return values:
kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
-
status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)
Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.
Note
A transfer handle does not need to be created before calling this API.
- Parameters:
base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN FD message frame structure for reception.
- Return values:
kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
-
void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)
Initializes the FlexCAN handle.
This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
callback – The callback function.
userData – The parameter of the callback function.
-
status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)
Sends a message using IRQ.
This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.
- Return values:
kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.
-
status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)
Receives a message using IRQ.
This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.
- Return values:
kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.
-
status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)
Receives a message from Rx FIFO using IRQ.
This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.
- Return values:
kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.
-
status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)
Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
-
status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)
Receives a message from Enhanced Rx FIFO using IRQ.
This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@
- Return values:
kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.
-
static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)
Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
-
uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)
Gets the detail index of Mailbox’s Timestamp by handle.
Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking
- Parameters:
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.
- Return values:
the – index of mailbox ‘s timestamp stored in the handle.
-
void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
Aborts the interrupt driven message send process.
This function aborts the interrupt driven message send process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.
-
void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
Aborts the interrupt driven message receive process.
This function aborts the interrupt driven message receive process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.
-
void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)
Aborts the interrupt driven message receive from Rx FIFO process.
This function aborts the interrupt driven message receive from Rx FIFO process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
-
void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle)
Aborts the interrupt driven message receive from Enhanced Rx FIFO process.
This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
-
void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
FlexCAN IRQ handle function.
This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
-
FSL_FLEXCAN_DRIVER_VERSION
FlexCAN driver version.
FlexCAN transfer status.
Values:
-
enumerator kStatus_FLEXCAN_TxBusy
Tx Message Buffer is Busy.
-
enumerator kStatus_FLEXCAN_TxIdle
Tx Message Buffer is Idle.
-
enumerator kStatus_FLEXCAN_TxSwitchToRx
Remote Message is send out and Message buffer changed to Receive one.
-
enumerator kStatus_FLEXCAN_RxBusy
Rx Message Buffer is Busy.
-
enumerator kStatus_FLEXCAN_RxIdle
Rx Message Buffer is Idle.
-
enumerator kStatus_FLEXCAN_RxOverflow
Rx Message Buffer is Overflowed.
-
enumerator kStatus_FLEXCAN_RxFifoBusy
Rx Message FIFO is Busy.
-
enumerator kStatus_FLEXCAN_RxFifoIdle
Rx Message FIFO is Idle.
-
enumerator kStatus_FLEXCAN_RxFifoOverflow
Rx Message FIFO is overflowed.
-
enumerator kStatus_FLEXCAN_RxFifoWarning
Rx Message FIFO is almost overflowed.
-
enumerator kStatus_FLEXCAN_RxFifoDisabled
Rx Message FIFO is disabled during reading.
-
enumerator kStatus_FLEXCAN_ErrorStatus
FlexCAN Module Error and Status.
-
enumerator kStatus_FLEXCAN_WakeUp
FlexCAN is waken up from STOP mode.
-
enumerator kStatus_FLEXCAN_UnHandled
UnHadled Interrupt asserted.
-
enumerator kStatus_FLEXCAN_RxRemote
Rx Remote Message Received in Mail box.
-
enumerator kStatus_FLEXCAN_RxFifoUnderflow
Enhanced Rx Message FIFO is underflow.
-
enumerator kStatus_FLEXCAN_TxBusy
-
enum _flexcan_frame_format
FlexCAN frame format.
Values:
-
enumerator kFLEXCAN_FrameFormatStandard
Standard frame format attribute.
-
enumerator kFLEXCAN_FrameFormatExtend
Extend frame format attribute.
-
enumerator kFLEXCAN_FrameFormatStandard
-
enum _flexcan_frame_type
FlexCAN frame type.
Values:
-
enumerator kFLEXCAN_FrameTypeData
Data frame type attribute.
-
enumerator kFLEXCAN_FrameTypeRemote
Remote frame type attribute.
-
enumerator kFLEXCAN_FrameTypeData
-
enum _flexcan_clock_source
FlexCAN clock source.
- Deprecated:
Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0
Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1
Values:
-
enumerator kFLEXCAN_ClkSrcOsc
FlexCAN Protocol Engine clock from Oscillator.
-
enumerator kFLEXCAN_ClkSrcPeri
FlexCAN Protocol Engine clock from Peripheral Clock.
-
enumerator kFLEXCAN_ClkSrc0
FlexCAN Protocol Engine clock selected by user as SRC == 0.
-
enumerator kFLEXCAN_ClkSrc1
FlexCAN Protocol Engine clock selected by user as SRC == 1.
-
enum _flexcan_wake_up_source
FlexCAN wake up source.
Values:
-
enumerator kFLEXCAN_WakeupSrcUnfiltered
FlexCAN uses unfiltered Rx input to detect edge.
-
enumerator kFLEXCAN_WakeupSrcFiltered
FlexCAN uses filtered Rx input to detect edge.
-
enumerator kFLEXCAN_WakeupSrcUnfiltered
-
enum _flexcan_rx_fifo_filter_type
FlexCAN Rx Fifo Filter type.
Values:
-
enumerator kFLEXCAN_RxFifoFilterTypeA
One full ID (standard and extended) per ID Filter element.
-
enumerator kFLEXCAN_RxFifoFilterTypeB
Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.
-
enumerator kFLEXCAN_RxFifoFilterTypeC
Four partial 8-bit Standard or extended ID slices per ID Filter Table element.
-
enumerator kFLEXCAN_RxFifoFilterTypeD
All frames rejected.
-
enumerator kFLEXCAN_RxFifoFilterTypeA
-
enum _flexcan_mb_size
FlexCAN Message Buffer Payload size.
Values:
-
enumerator kFLEXCAN_8BperMB
Selects 8 bytes per Message Buffer.
-
enumerator kFLEXCAN_16BperMB
Selects 16 bytes per Message Buffer.
-
enumerator kFLEXCAN_32BperMB
Selects 32 bytes per Message Buffer.
-
enumerator kFLEXCAN_64BperMB
Selects 64 bytes per Message Buffer.
-
enumerator kFLEXCAN_8BperMB
-
enum _flexcan_fd_frame_length
FlexCAN CAN FD frame supporting data length (available DLC values).
For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.
Values:
-
enumerator kFLEXCAN_0BperFrame
Frame contains 0 valid data bytes.
-
enumerator kFLEXCAN_1BperFrame
Frame contains 1 valid data bytes.
-
enumerator kFLEXCAN_2BperFrame
Frame contains 2 valid data bytes.
-
enumerator kFLEXCAN_3BperFrame
Frame contains 3 valid data bytes.
-
enumerator kFLEXCAN_4BperFrame
Frame contains 4 valid data bytes.
-
enumerator kFLEXCAN_5BperFrame
Frame contains 5 valid data bytes.
-
enumerator kFLEXCAN_6BperFrame
Frame contains 6 valid data bytes.
-
enumerator kFLEXCAN_7BperFrame
Frame contains 7 valid data bytes.
-
enumerator kFLEXCAN_8BperFrame
Frame contains 8 valid data bytes.
-
enumerator kFLEXCAN_12BperFrame
Frame contains 12 valid data bytes.
-
enumerator kFLEXCAN_16BperFrame
Frame contains 16 valid data bytes.
-
enumerator kFLEXCAN_20BperFrame
Frame contains 20 valid data bytes.
-
enumerator kFLEXCAN_24BperFrame
Frame contains 24 valid data bytes.
-
enumerator kFLEXCAN_32BperFrame
Frame contains 32 valid data bytes.
-
enumerator kFLEXCAN_48BperFrame
Frame contains 48 valid data bytes.
-
enumerator kFLEXCAN_64BperFrame
Frame contains 64 valid data bytes.
-
enumerator kFLEXCAN_0BperFrame
-
enum _flexcan_efifo_dma_per_read_length
FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.
Values:
-
enumerator kFLEXCAN_1WordPerRead
Transfer 1 32-bit words (CS).
-
enumerator kFLEXCAN_2WordPerRead
Transfer 2 32-bit words (CS + ID).
-
enumerator kFLEXCAN_3WordPerRead
Transfer 3 32-bit words (CS + ID + 1~4 bytes data).
-
enumerator kFLEXCAN_4WordPerRead
Transfer 4 32-bit words (CS + ID + 5~8 bytes data).
-
enumerator kFLEXCAN_5WordPerRead
Transfer 5 32-bit words (CS + ID + 9~12 bytes data).
-
enumerator kFLEXCAN_6WordPerRead
Transfer 6 32-bit words (CS + ID + 13~16 bytes data).
-
enumerator kFLEXCAN_7WordPerRead
Transfer 7 32-bit words (CS + ID + 17~20 bytes data).
-
enumerator kFLEXCAN_8WordPerRead
Transfer 8 32-bit words (CS + ID + 21~24 bytes data).
-
enumerator kFLEXCAN_9WordPerRead
Transfer 9 32-bit words (CS + ID + 25~28 bytes data).
-
enumerator kFLEXCAN_10WordPerRead
Transfer 10 32-bit words (CS + ID + 29~32 bytes data).
-
enumerator kFLEXCAN_11WordPerRead
Transfer 11 32-bit words (CS + ID + 33~36 bytes data).
-
enumerator kFLEXCAN_12WordPerRead
Transfer 12 32-bit words (CS + ID + 37~40 bytes data).
-
enumerator kFLEXCAN_13WordPerRead
Transfer 13 32-bit words (CS + ID + 41~44 bytes data).
-
enumerator kFLEXCAN_14WordPerRead
Transfer 14 32-bit words (CS + ID + 45~48 bytes data).
-
enumerator kFLEXCAN_15WordPerRead
Transfer 15 32-bit words (CS + ID + 49~52 bytes data).
-
enumerator kFLEXCAN_16WordPerRead
Transfer 16 32-bit words (CS + ID + 53~56 bytes data).
-
enumerator kFLEXCAN_17WordPerRead
Transfer 17 32-bit words (CS + ID + 57~60 bytes data).
-
enumerator kFLEXCAN_18WordPerRead
Transfer 18 32-bit words (CS + ID + 61~64 bytes data).
-
enumerator kFLEXCAN_19WordPerRead
Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).
-
enumerator kFLEXCAN_1WordPerRead
-
enum _flexcan_rx_fifo_priority
FlexCAN Enhanced/Legacy Rx FIFO priority.
The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.
Values:
-
enumerator kFLEXCAN_RxFifoPrioLow
Matching process start from Rx Message Buffer first.
-
enumerator kFLEXCAN_RxFifoPrioHigh
Matching process start from Enhanced/Legacy Rx FIFO first.
-
enumerator kFLEXCAN_RxFifoPrioLow
-
enum _flexcan_interrupt_enable
FlexCAN interrupt enable enumerations.
This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.
Note
FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.
Values:
-
enumerator kFLEXCAN_BusOffInterruptEnable
Bus Off interrupt, use bit 15.
-
enumerator kFLEXCAN_ErrorInterruptEnable
CAN Error interrupt, use bit 14.
-
enumerator kFLEXCAN_TxWarningInterruptEnable
Tx Warning interrupt, use bit 11.
-
enumerator kFLEXCAN_RxWarningInterruptEnable
Rx Warning interrupt, use bit 10.
-
enumerator kFLEXCAN_WakeUpInterruptEnable
Self Wake Up interrupt, use bit 26.
-
enumerator kFLEXCAN_FDErrorInterruptEnable
CAN FD Error interrupt, use bit 31.
-
enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable
PN Match Wake Up interrupt, use high word bit 17.
-
enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable
PN Timeout Wake Up interrupt, use high word bit 16. Enhanced Rx FIFO Underflow interrupt, use high word bit 31.
-
enumerator kFLEXCAN_ERxFifoUnderflowInterruptEnable
Enhanced Rx FIFO Overflow interrupt, use high word bit 30.
-
enumerator kFLEXCAN_ERxFifoOverflowInterruptEnable
Enhanced Rx FIFO Watermark interrupt, use high word bit 29.
-
enumerator kFLEXCAN_ERxFifoWatermarkInterruptEnable
Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28.
-
enumerator kFLEXCAN_ERxFifoDataAvlInterruptEnable
-
enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable
Host Access With Non-Correctable Errors interrupt, use high word bit 0.
-
enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable
FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.
-
enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable
Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.
-
enumerator kFLEXCAN_BusOffInterruptEnable
-
enum _flexcan_flags
FlexCAN status flags.
This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
Note
The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.
Values:
-
enumerator kFLEXCAN_ErrorOverrunFlag
Error Overrun Status.
-
enumerator kFLEXCAN_FDErrorIntFlag
CAN FD Error Interrupt Flag.
-
enumerator kFLEXCAN_BusoffDoneIntFlag
Bus Off process completed Interrupt Flag.
-
enumerator kFLEXCAN_SynchFlag
CAN Synchronization Status.
-
enumerator kFLEXCAN_TxWarningIntFlag
Tx Warning Interrupt Flag.
-
enumerator kFLEXCAN_RxWarningIntFlag
Rx Warning Interrupt Flag.
-
enumerator kFLEXCAN_IdleFlag
FlexCAN In IDLE Status.
-
enumerator kFLEXCAN_FaultConfinementFlag
FlexCAN Fault Confinement State.
-
enumerator kFLEXCAN_TransmittingFlag
FlexCAN In Transmission Status.
-
enumerator kFLEXCAN_ReceivingFlag
FlexCAN In Reception Status.
-
enumerator kFLEXCAN_BusOffIntFlag
Bus Off Interrupt Flag.
-
enumerator kFLEXCAN_ErrorIntFlag
CAN Error Interrupt Flag.
-
enumerator kFLEXCAN_WakeUpIntFlag
Self Wake-Up Interrupt Flag.
-
enumerator kFLEXCAN_ErrorFlag
-
enumerator kFLEXCAN_PNMatchIntFlag
PN Matching Event Interrupt Flag.
-
enumerator kFLEXCAN_PNTimeoutIntFlag
PN Timeout Event Interrupt Flag.
-
enumerator kFLEXCAN_ERxFifoUnderflowIntFlag
Enhanced Rx FIFO underflow Interrupt Flag.
-
enumerator kFLEXCAN_ERxFifoOverflowIntFlag
Enhanced Rx FIFO overflow Interrupt Flag.
-
enumerator kFLEXCAN_ERxFifoWatermarkIntFlag
Enhanced Rx FIFO watermark Interrupt Flag.
-
enumerator kFLEXCAN_ERxFifoDataAvlIntFlag
Enhanced Rx FIFO data available Interrupt Flag.
-
enumerator kFLEXCAN_ERxFifoEmptyFlag
Enhanced Rx FIFO empty status.
-
enumerator kFLEXCAN_ERxFifoFullFlag
Enhanced Rx FIFO full status.
-
enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag
Host Access With Non-Correctable Error Interrupt Flag.
-
enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag
FlexCAN Access With Non-Correctable Error Interrupt Flag.
-
enumerator kFLEXCAN_CorrectableErrorIntFlag
Correctable Error Interrupt Flag.
-
enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag
Host Access With Non-Correctable Error Interrupt Overrun Flag.
-
enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag
FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.
-
enumerator kFLEXCAN_CorrectableErrorOverrunFlag
Correctable Error Interrupt Overrun Flag.
-
enumerator kFLEXCAN_AllMemoryErrorFlag
All Memory Error Flags.
-
enumerator kFLEXCAN_ErrorOverrunFlag
-
enum _flexcan_error_flags
FlexCAN error status flags.
The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.
Values:
-
enumerator kFLEXCAN_FDStuffingError
Stuffing Error.
-
enumerator kFLEXCAN_FDFormError
Form Error.
-
enumerator kFLEXCAN_FDCrcError
Cyclic Redundancy Check Error.
-
enumerator kFLEXCAN_FDBit0Error
Unable to send dominant bit.
-
enumerator kFLEXCAN_FDBit1Error
Unable to send recessive bit.
-
enumerator kFLEXCAN_TxErrorWarningFlag
Tx Error Warning Status.
-
enumerator kFLEXCAN_RxErrorWarningFlag
Rx Error Warning Status.
-
enumerator kFLEXCAN_StuffingError
Stuffing Error.
-
enumerator kFLEXCAN_FormError
Form Error.
-
enumerator kFLEXCAN_CrcError
Cyclic Redundancy Check Error.
-
enumerator kFLEXCAN_AckError
Received no ACK on transmission.
-
enumerator kFLEXCAN_Bit0Error
Unable to send dominant bit.
-
enumerator kFLEXCAN_Bit1Error
Unable to send recessive bit.
-
enumerator kFLEXCAN_FDStuffingError
FlexCAN Legacy Rx FIFO status flags.
The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.
Values:
-
enumerator kFLEXCAN_RxFifoOverflowFlag
Rx FIFO overflow flag.
-
enumerator kFLEXCAN_RxFifoWarningFlag
Rx FIFO almost full flag.
-
enumerator kFLEXCAN_RxFifoFrameAvlFlag
Frames available in Rx FIFO flag.
-
enumerator kFLEXCAN_RxFifoOverflowFlag
-
enum _flexcan_memory_error_type
FlexCAN Memory Error Type.
Values:
-
enumerator kFLEXCAN_CorrectableError
The memory error is correctable which means on bit error.
-
enumerator kFLEXCAN_NonCorrectableError
The memory error is non-correctable which means two bit errors.
-
enumerator kFLEXCAN_CorrectableError
-
enum _flexcan_memory_access_type
FlexCAN Memory Access Type.
Values:
-
enumerator kFLEXCAN_MoveOutFlexCanAccess
The memory error was detected during move-out FlexCAN access.
-
enumerator kFLEXCAN_MoveInAccess
The memory error was detected during move-in FlexCAN access.
-
enumerator kFLEXCAN_TxArbitrationAccess
The memory error was detected during Tx Arbitration FlexCAN access.
-
enumerator kFLEXCAN_RxMatchingAccess
The memory error was detected during Rx Matching FlexCAN access.
-
enumerator kFLEXCAN_MoveOutHostAccess
The memory error was detected during Rx Matching Host (CPU) access.
-
enumerator kFLEXCAN_MoveOutFlexCanAccess
-
enum _flexcan_byte_error_syndrome
FlexCAN Memory Error Byte Syndrome.
Values:
-
enumerator kFLEXCAN_NoError
No bit error in this byte.
-
enumerator kFLEXCAN_ParityBits0Error
Parity bit 0 error in this byte.
-
enumerator kFLEXCAN_ParityBits1Error
Parity bit 1 error in this byte.
-
enumerator kFLEXCAN_ParityBits2Error
Parity bit 2 error in this byte.
-
enumerator kFLEXCAN_ParityBits3Error
Parity bit 3 error in this byte.
-
enumerator kFLEXCAN_ParityBits4Error
Parity bit 4 error in this byte.
-
enumerator kFLEXCAN_DataBits0Error
Data bit 0 error in this byte.
-
enumerator kFLEXCAN_DataBits1Error
Data bit 1 error in this byte.
-
enumerator kFLEXCAN_DataBits2Error
Data bit 2 error in this byte.
-
enumerator kFLEXCAN_DataBits3Error
Data bit 3 error in this byte.
-
enumerator kFLEXCAN_DataBits4Error
Data bit 4 error in this byte.
-
enumerator kFLEXCAN_DataBits5Error
Data bit 5 error in this byte.
-
enumerator kFLEXCAN_DataBits6Error
Data bit 6 error in this byte.
-
enumerator kFLEXCAN_DataBits7Error
Data bit 7 error in this byte.
-
enumerator kFLEXCAN_AllZeroError
All-zeros non-correctable error in this byte.
-
enumerator kFLEXCAN_AllOneError
All-ones non-correctable error in this byte.
-
enumerator kFLEXCAN_NonCorrectableErrors
Non-correctable error in this byte.
-
enumerator kFLEXCAN_NoError
-
enum _flexcan_pn_match_source
FlexCAN Pretended Networking match source selection.
Values:
-
enumerator kFLEXCAN_PNMatSrcID
Message match with ID filtering.
-
enumerator kFLEXCAN_PNMatSrcIDAndData
Message match with ID filtering and payload filtering.
-
enumerator kFLEXCAN_PNMatSrcID
-
enum _flexcan_pn_match_mode
FlexCAN Pretended Networking mode match type.
Values:
-
enumerator kFLEXCAN_PNMatModeEqual
Match upon ID/Payload contents against an exact target value.
-
enumerator kFLEXCAN_PNMatModeGreater
Match upon an ID/Payload value greater than or equal to a specified target value.
-
enumerator kFLEXCAN_PNMatModeSmaller
Match upon an ID/Payload value smaller than or equal to a specified target value.
-
enumerator kFLEXCAN_PNMatModeRange
Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit
-
enumerator kFLEXCAN_PNMatModeEqual
-
typedef enum _flexcan_frame_format flexcan_frame_format_t
FlexCAN frame format.
-
typedef enum _flexcan_frame_type flexcan_frame_type_t
FlexCAN frame type.
-
typedef enum _flexcan_clock_source flexcan_clock_source_t
FlexCAN clock source.
- Deprecated:
Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0
Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1
-
typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t
FlexCAN wake up source.
-
typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t
FlexCAN Rx Fifo Filter type.
-
typedef enum _flexcan_mb_size flexcan_mb_size_t
FlexCAN Message Buffer Payload size.
-
typedef enum _flexcan_efifo_dma_per_read_length flexcan_efifo_dma_per_read_length_t
FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.
-
typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t
FlexCAN Enhanced/Legacy Rx FIFO priority.
The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.
-
typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t
FlexCAN Memory Error Type.
-
typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t
FlexCAN Memory Access Type.
-
typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t
FlexCAN Memory Error Byte Syndrome.
-
typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t
FlexCAN memory error register status structure.
This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.
-
typedef struct _flexcan_frame flexcan_frame_t
FlexCAN message frame structure.
-
typedef struct _flexcan_fd_frame flexcan_fd_frame_t
CAN FD message frame structure.
The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.
-
typedef struct _flexcan_timing_config flexcan_timing_config_t
FlexCAN protocol timing characteristic configuration structure.
-
typedef struct _flexcan_config flexcan_config_t
FlexCAN module configuration structure.
- Deprecated:
Do not use the baudRate. It has been superceded bitRate
Do not use the baudRateFD. It has been superceded bitRateFD
-
typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t
FlexCAN Receive Message Buffer configuration structure.
This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.
-
typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t
FlexCAN Pretended Networking match source selection.
-
typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t
FlexCAN Pretended Networking mode match type.
-
typedef struct _flexcan_pn_config flexcan_pn_config_t
FlexCAN Pretended Networking configuration structure.
This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.
-
typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t
FlexCAN Legacy Rx FIFO configuration structure.
-
typedef struct _flexcan_enhanced_rx_fifo_std_id_filter flexcan_enhanced_rx_fifo_std_id_filter_t
FlexCAN Enhanced Rx FIFO Standard ID filter element structure.
-
typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter flexcan_enhanced_rx_fifo_ext_id_filter_t
FlexCAN Enhanced Rx FIFO Extended ID filter element structure.
-
typedef struct _flexcan_enhanced_rx_fifo_config flexcan_enhanced_rx_fifo_config_t
FlexCAN Enhanced Rx FIFO configuration structure.
-
typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t
FlexCAN Message Buffer transfer.
-
typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t
FlexCAN Rx FIFO transfer.
-
typedef struct _flexcan_handle flexcan_handle_t
FlexCAN handle structure definition.
-
typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)
-
FLEXCAN_WAIT_TIMEOUT
-
DLC_LENGTH_DECODE(dlc)
FlexCAN frame length helper macro.
-
FLEXCAN_ID_STD(id)
FlexCAN Frame ID helper macro.
Standard Frame ID helper macro.
-
FLEXCAN_ID_EXT(id)
Extend Frame ID helper macro.
-
FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)
FlexCAN Rx Message Buffer Mask helper macro.
Standard Rx Message Buffer Mask helper macro.
-
FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide)
Extend Rx Message Buffer Mask helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)
FlexCAN Legacy Rx FIFO Mask helper macro.
Standard Rx FIFO Mask helper macro Type A helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)
Standard Rx FIFO Mask helper macro Type B upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)
Standard Rx FIFO Mask helper macro Type B lower part helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id)
Standard Rx FIFO Mask helper macro Type C upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)
Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id)
Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.
-
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id)
Standard Rx FIFO Mask helper macro Type C lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)
Extend Rx FIFO Mask helper macro Type A helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)
Extend Rx FIFO Mask helper macro Type B upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)
Extend Rx FIFO Mask helper macro Type B lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id)
Extend Rx FIFO Mask helper macro Type C upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id)
Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id)
Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id)
Extend Rx FIFO Mask helper macro Type C lower part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)
FlexCAN Rx FIFO Filter helper macro.
Standard Rx FIFO Filter helper macro Type A helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide)
Standard Rx FIFO Filter helper macro Type B upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide)
Standard Rx FIFO Filter helper macro Type B lower part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id)
Standard Rx FIFO Filter helper macro Type C upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id)
Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id)
Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.
-
FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)
Standard Rx FIFO Filter helper macro Type C lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide)
Extend Rx FIFO Filter helper macro Type A helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide)
Extend Rx FIFO Filter helper macro Type B upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide)
Extend Rx FIFO Filter helper macro Type B lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)
Extend Rx FIFO Filter helper macro Type C upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id)
Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id)
Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.
-
FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id)
Extend Rx FIFO Filter helper macro Type C lower part helper macro.
-
ENHANCED_RX_FIFO_FSCH(x)
FlexCAN Enhanced Rx FIFO Filter and Mask helper macro.
-
RTR_STD_HIGH(x)
-
RTR_STD_LOW(x)
-
RTR_EXT(x)
-
ID_STD_LOW(id)
-
ID_STD_HIGH(id)
-
ID_EXT(id)
-
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask)
Standard ID filter element with filter + mask scheme.
-
FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask)
Standard ID filter element with filter range.
-
FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2)
Standard ID filter element with two filters without masks.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr)
Extended ID filter element with filter + mask scheme low word.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask)
Extended ID filter element with filter + mask scheme high word.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr)
Extended ID filter element with range scheme low word.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask)
Extended ID filter element with range scheme high word.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2)
Extended ID filter element with two filters without masks low word.
-
FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1)
Extended ID filter element with two filters without masks high word.
-
FLEXCAN_PN_STD_MASK(id, rtr)
FlexCAN Pretended Networking ID Mask helper macro.
Standard Rx Message Buffer Mask helper macro.
-
FLEXCAN_PN_EXT_MASK(id, rtr)
Extend Rx Message Buffer Mask helper macro.
-
FLEXCAN_PN_INT_MASK(x)
FlexCAN interrupt/status flag helper macro.
-
FLEXCAN_PN_INT_UNMASK(x)
-
FLEXCAN_PN_STATUS_MASK(x)
-
FLEXCAN_PN_STATUS_UNMASK(x)
-
FLEXCAN_EFIFO_INT_MASK(x)
-
FLEXCAN_EFIFO_INT_UNMASK(x)
-
FLEXCAN_EFIFO_STATUS_MASK(x)
-
FLEXCAN_EFIFO_STATUS_UNMASK(x)
-
FLEXCAN_MECR_INT_MASK(x)
-
FLEXCAN_MECR_INT_UNMASK(x)
-
FLEXCAN_MECR_STATUS_MASK(x)
-
FLEXCAN_MECR_STATUS_UNMASK(x)
-
FLEXCAN_ERROR_AND_STATUS_INIT_FLAG
-
FLEXCAN_WAKE_UP_FLAG
-
FLEXCAN_MEMORY_ERROR_INIT_FLAG
-
FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG
-
E_RX_FIFO(base)
FlexCAN Enhanced Rx FIFO base address helper macro.
-
FLEXCAN_CALLBACK(x)
FlexCAN transfer callback function.
The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.
-
struct _flexcan_memory_error_report_status
- #include <fsl_flexcan.h>
FlexCAN memory error register status structure.
This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.
Public Members
-
flexcan_memory_error_type_t errorType
The type of memory error that giving rise to the report.
-
flexcan_memory_access_type_t accessType
The type of memory access that giving rise to the memory error.
-
uint16_t accessAddress
The address where memory error detected.
-
uint32_t errorData
The raw data word read from memory with error.
-
flexcan_memory_error_type_t errorType
-
struct _flexcan_frame
- #include <fsl_flexcan.h>
FlexCAN message frame structure.
-
struct _flexcan_fd_frame
- #include <fsl_flexcan.h>
CAN FD message frame structure.
The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.
Public Members
-
uint32_t idhit
Note
ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is correct. CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive mode).
-
uint32_t idhit
-
struct _flexcan_timing_config
- #include <fsl_flexcan.h>
FlexCAN protocol timing characteristic configuration structure.
Public Members
-
uint16_t preDivider
Classic CAN or CAN FD nominal phase bit rate prescaler.
-
uint8_t rJumpwidth
Classic CAN or CAN FD nominal phase Re-sync Jump Width.
-
uint8_t phaseSeg1
Classic CAN or CAN FD nominal phase Segment 1.
-
uint8_t phaseSeg2
Classic CAN or CAN FD nominal phase Segment 2.
-
uint8_t propSeg
Classic CAN or CAN FD nominal phase Propagation Segment.
-
uint16_t fpreDivider
CAN FD data phase bit rate prescaler.
-
uint8_t frJumpwidth
CAN FD data phase Re-sync Jump Width.
-
uint8_t fphaseSeg1
CAN FD data phase Phase Segment 1.
-
uint8_t fphaseSeg2
CAN FD data phase Phase Segment 2.
-
uint8_t fpropSeg
CAN FD data phase Propagation Segment.
-
uint16_t preDivider
-
struct _flexcan_config
- #include <fsl_flexcan.h>
FlexCAN module configuration structure.
- Deprecated:
Do not use the baudRate. It has been superceded bitRate
Do not use the baudRateFD. It has been superceded bitRateFD
Public Members
-
flexcan_clock_source_t clkSrc
Clock source for FlexCAN Protocol Engine.
-
flexcan_wake_up_source_t wakeupSrc
Wake up source selection.
-
uint8_t maxMbNum
The maximum number of Message Buffers used by user.
-
bool enableLoopBack
Enable or Disable Loop Back Self Test Mode.
-
bool enableTimerSync
Enable or Disable Timer Synchronization.
-
bool enableSelfWakeup
Enable or Disable Self Wakeup Mode.
-
bool enableIndividMask
Enable or Disable Rx Individual Mask and Queue feature.
-
bool disableSelfReception
Enable or Disable Self Reflection.
-
bool enableListenOnlyMode
Enable or Disable Listen Only Mode.
-
bool enableDoze
Enable or Disable Doze Mode.
-
bool enablePretendedeNetworking
Enable or Disable the Pretended Networking mode.
-
bool enableMemoryErrorControl
Enable or Disable the memory errors detection and correction mechanism.
-
bool enableNonCorrectableErrorEnterFreeze
Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.
-
bool enableTransceiverDelayMeasure
Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.
-
bool enableRemoteRequestFrameStored
true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.
-
struct _flexcan_rx_mb_config
- #include <fsl_flexcan.h>
FlexCAN Receive Message Buffer configuration structure.
This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.
Public Members
-
uint32_t id
CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.
-
flexcan_frame_format_t format
CAN Frame Identifier format(Standard of Extend).
-
flexcan_frame_type_t type
CAN Frame Type(Data or Remote).
-
uint32_t id
-
struct _flexcan_pn_config
- #include <fsl_flexcan.h>
FlexCAN Pretended Networking configuration structure.
This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.
Public Members
-
bool enableTimeout
Enable or Disable timeout event trigger wakeup.
-
uint16_t timeoutValue
The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.
-
bool enableMatch
Enable or Disable match event trigger wakeup.
-
flexcan_pn_match_source_t matchSrc
Selects the match source (ID and/or data match) to trigger wakeup.
-
uint8_t matchNum
The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.
-
flexcan_pn_match_mode_t idMatchMode
The ID match type.
-
flexcan_pn_match_mode_t dataMatchMode
The data match type.
-
uint32_t idLower
The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.
-
uint32_t idUpper
The ID target values 2 which used only as the upper limit value in ID match “range
detection” or used to store the ID mask in “equal to”.
-
uint8_t lengthLower
The lower limit for length of data bytes which used only in data match “range
detection”. Range in 0x0 ~ 0x8.
-
uint8_t lengthUpper
The upper limit for length of data bytes which used only in data match “range
detection”. Range in 0x0 ~ 0x8.
-
bool enableTimeout
-
struct _flexcan_rx_fifo_config
- #include <fsl_flexcan.h>
FlexCAN Legacy Rx FIFO configuration structure.
Public Members
-
uint32_t *idFilterTable
Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.
-
uint8_t idFilterNum
The FlexCAN Legacy Rx FIFO Filter elements quantity.
-
flexcan_rx_fifo_filter_type_t idFilterType
The FlexCAN Legacy Rx FIFO Filter type.
-
flexcan_rx_fifo_priority_t priority
The FlexCAN Legacy Rx FIFO receive priority.
-
uint32_t *idFilterTable
-
struct _flexcan_enhanced_rx_fifo_std_id_filter
- #include <fsl_flexcan.h>
FlexCAN Enhanced Rx FIFO Standard ID filter element structure.
Public Members
-
uint32_t filterType
FlexCAN internal Free-Running Counter Time Stamp.
-
uint32_t rtr1
CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.
-
uint32_t std1
CAN Frame Type(DATA or REMOTE).
-
uint32_t rtr2
CAN Frame Identifier(STD or EXT format).
-
uint32_t std2
Substitute Remote request.
-
uint32_t filterType
-
struct _flexcan_enhanced_rx_fifo_ext_id_filter
- #include <fsl_flexcan.h>
FlexCAN Enhanced Rx FIFO Extended ID filter element structure.
Public Members
-
uint32_t filterType
FlexCAN internal Free-Running Counter Time Stamp.
-
uint32_t rtr1
CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.
-
uint32_t std1
CAN Frame Type(DATA or REMOTE).
-
uint32_t rtr2
CAN Frame Identifier(STD or EXT format).
-
uint32_t std2
Substitute Remote request.
-
uint32_t filterType
-
struct _flexcan_enhanced_rx_fifo_config
- #include <fsl_flexcan.h>
FlexCAN Enhanced Rx FIFO configuration structure.
Public Members
-
uint32_t *idFilterTable
Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member occupies 32 bit word, table size should be equal to idFilterNum. There are two types of Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table members), the extended-ID filter element needs to be placed in front of the table.
-
uint8_t idFilterPairNum
idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two standard ID filter elements.
-
uint8_t extendIdFilterNum
The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO identifier filter table, each extended-ID filter element occupies 2 words, extendIdFilterNum need less than or equal to idFilterPairNum.
-
uint8_t fifoWatermark
(fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO which can trigger FIFO watermark interrupt or a DMA request.
-
flexcan_efifo_dma_per_read_length_t dmaPerReadLength
Define the length of each read of the Enhanced RX FIFO element by the DAM, see _flexcan_fd_frame_length.
-
flexcan_rx_fifo_priority_t priority
The FlexCAN Enhanced Rx FIFO receive priority.
-
uint32_t *idFilterTable
-
struct _flexcan_mb_transfer
- #include <fsl_flexcan.h>
FlexCAN Message Buffer transfer.
Public Members
-
flexcan_frame_t *frame
The buffer of CAN Message to be transfer.
-
uint8_t mbIdx
The index of Message buffer used to transfer Message.
-
flexcan_frame_t *frame
-
struct _flexcan_fifo_transfer
- #include <fsl_flexcan.h>
FlexCAN Rx FIFO transfer.
Public Members
-
flexcan_fd_frame_t *framefd
The buffer of CAN Message to be received from Enhanced Rx FIFO.
-
flexcan_frame_t *frame
The buffer of CAN Message to be received from Legacy Rx FIFO.
-
size_t frameNum
Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO.
-
flexcan_fd_frame_t *framefd
-
struct _flexcan_handle
- #include <fsl_flexcan.h>
FlexCAN handle structure.
Public Members
-
flexcan_transfer_callback_t callback
Callback function.
-
void *userData
FlexCAN callback function parameter.
-
flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]
The buffer for received CAN data from Message Buffers.
-
flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]
The buffer for received CAN FD data from Message Buffers.
-
flexcan_frame_t *volatile rxFifoFrameBuf
The buffer for received CAN data from Legacy Rx FIFO.
-
flexcan_fd_frame_t *volatile rxFifoFDFrameBuf
The buffer for received CAN FD data from Ehanced Rx FIFO.
-
size_t rxFifoFrameNum
The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO.
-
size_t rxFifoTransferTotalNum
Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO.
-
volatile uint8_t mbState[CAN_WORD1_COUNT]
Message Buffer transfer state.
-
volatile uint8_t rxFifoState
Rx FIFO transfer state.
-
volatile uint32_t timestamp[CAN_WORD1_COUNT]
Mailbox transfer timestamp.
-
flexcan_transfer_callback_t callback
-
struct byteStatus
Public Members
-
bool byteIsRead
The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.
-
bool byteIsRead
-
struct __unnamed34__
Public Members
-
uint32_t timestamp
FlexCAN internal Free-Running Counter Time Stamp.
-
uint32_t length
CAN frame data length in bytes (Range: 0~8).
-
uint32_t type
CAN Frame Type(DATA or REMOTE).
-
uint32_t format
CAN Frame Identifier(STD or EXT format).
-
uint32_t __pad0__
Reserved.
-
uint32_t idhit
CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).
-
uint32_t timestamp
-
struct __unnamed36__
Public Members
-
uint32_t id
CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.
-
uint32_t __pad0__
Reserved.
-
uint32_t id
-
union __unnamed38__
Public Members
- struct _flexcan_frame
- struct _flexcan_frame
-
struct __unnamed40__
Public Members
-
uint32_t dataWord0
CAN Frame payload word0.
-
uint32_t dataWord1
CAN Frame payload word1.
-
uint32_t dataWord0
-
struct __unnamed42__
Public Members
-
uint8_t dataByte3
CAN Frame payload byte3.
-
uint8_t dataByte2
CAN Frame payload byte2.
-
uint8_t dataByte1
CAN Frame payload byte1.
-
uint8_t dataByte0
CAN Frame payload byte0.
-
uint8_t dataByte7
CAN Frame payload byte7.
-
uint8_t dataByte6
CAN Frame payload byte6.
-
uint8_t dataByte5
CAN Frame payload byte5.
-
uint8_t dataByte4
CAN Frame payload byte4.
-
uint8_t dataByte3
-
struct __unnamed44__
Public Members
-
uint32_t timestamp
FlexCAN internal Free-Running Counter Time Stamp.
-
uint32_t length
CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.
-
uint32_t type
CAN Frame Type(DATA or REMOTE).
-
uint32_t format
CAN Frame Identifier(STD or EXT format).
-
uint32_t srr
Substitute Remote request.
-
uint32_t esi
Error State Indicator.
-
uint32_t brs
Bit Rate Switch.
-
uint32_t edl
Extended Data Length.
-
uint32_t timestamp
-
struct __unnamed46__
Public Members
-
uint32_t id
CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.
-
uint32_t __pad0__
Reserved.
-
uint32_t id
-
union __unnamed48__
Public Members
- struct _flexcan_fd_frame
- struct _flexcan_fd_frame
-
struct __unnamed50__
Public Members
-
uint32_t dataWord[16]
CAN FD Frame payload, 16 double word maximum.
-
uint32_t dataWord[16]
-
struct __unnamed52__
Public Members
-
uint8_t dataByte3
CAN Frame payload byte3.
-
uint8_t dataByte2
CAN Frame payload byte2.
-
uint8_t dataByte1
CAN Frame payload byte1.
-
uint8_t dataByte0
CAN Frame payload byte0.
-
uint8_t dataByte7
CAN Frame payload byte7.
-
uint8_t dataByte6
CAN Frame payload byte6.
-
uint8_t dataByte5
CAN Frame payload byte5.
-
uint8_t dataByte4
CAN Frame payload byte4.
-
uint8_t dataByte3
-
union __unnamed54__
Public Members
- struct _flexcan_config
- struct _flexcan_config
-
struct __unnamed56__
Public Members
-
uint32_t baudRate
FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.
-
uint32_t baudRateFD
FlexCAN FD bit rate in bps, for CANFD data phase.
-
uint32_t baudRate
-
struct __unnamed58__
Public Members
-
uint32_t bitRate
FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.
-
uint32_t bitRateFD
FlexCAN FD bit rate in bps, for CANFD data phase.
-
uint32_t bitRate
-
union __unnamed60__
Public Members
- struct _flexcan_pn_config
< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range
detection”.
- struct _flexcan_pn_config
-
struct __unnamed64__
< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range
detection”.
Public Members
-
uint32_t lowerWord0
CAN Frame payload word0.
-
uint32_t lowerWord1
CAN Frame payload word1.
-
uint32_t lowerWord0
-
struct __unnamed66__
Public Members
-
uint8_t lowerByte3
CAN Frame payload byte3.
-
uint8_t lowerByte2
CAN Frame payload byte2.
-
uint8_t lowerByte1
CAN Frame payload byte1.
-
uint8_t lowerByte0
CAN Frame payload byte0.
-
uint8_t lowerByte7
CAN Frame payload byte7.
-
uint8_t lowerByte6
CAN Frame payload byte6.
-
uint8_t lowerByte5
CAN Frame payload byte5.
-
uint8_t lowerByte4
CAN Frame payload byte4.
-
uint8_t lowerByte3
-
union __unnamed62__
Public Members
- struct _flexcan_pn_config
< The data target values 2 which used only as the upper limit value in data match “range
detection” or used to store the data mask in “equal to”.
- struct _flexcan_pn_config
-
struct __unnamed68__
< The data target values 2 which used only as the upper limit value in data match “range
detection” or used to store the data mask in “equal to”.
Public Members
-
uint32_t upperWord0
CAN Frame payload word0.
-
uint32_t upperWord1
CAN Frame payload word1.
-
uint32_t upperWord0
-
struct __unnamed70__
Public Members
-
uint8_t upperByte3
CAN Frame payload byte3.
-
uint8_t upperByte2
CAN Frame payload byte2.
-
uint8_t upperByte1
CAN Frame payload byte1.
-
uint8_t upperByte0
CAN Frame payload byte0.
-
uint8_t upperByte7
CAN Frame payload byte7.
-
uint8_t upperByte6
CAN Frame payload byte6.
-
uint8_t upperByte5
CAN Frame payload byte5.
-
uint8_t upperByte4
CAN Frame payload byte4.
-
uint8_t upperByte3
FlexCAN eDMA Driver
-
void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)
Initializes the FlexCAN handle, which is used in transactional functions.
- Parameters:
base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.
-
void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)
Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
- Parameters:
base – FlexCAN peripheral base address.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
pEdmaConfig – The user configuration structure of type edma_transfer_t.
-
status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)
Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
This function to Update edma transfer confiugration and Start eDMA transfer
- Parameters:
base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pEdmaConfig – The user configuration structure of type edma_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.
-
status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)
Receives the CAN Message from the Legacy Rx FIFO using eDMA.
This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.
-
status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)
Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
-
void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)
Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
- Parameters:
base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
-
status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)
Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.
- Parameters:
base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.
-
static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)
Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
- Parameters:
base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
-
FSL_FLEXCAN_EDMA_DRIVER_VERSION
FlexCAN EDMA driver version.
-
typedef struct _flexcan_edma_handle flexcan_edma_handle_t
-
typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData)
FlexCAN transfer callback function.
-
struct _flexcan_edma_handle
- #include <fsl_flexcan_edma.h>
FlexCAN eDMA handle.
Public Members
-
flexcan_edma_transfer_callback_t callback
Callback function.
-
void *userData
FlexCAN callback function parameter.
-
edma_handle_t *rxFifoEdmaHandle
The EDMA handler for Rx FIFO.
-
volatile uint8_t rxFifoState
Rx FIFO transfer state.
-
size_t frameNum
The number of messages that need to be received.
-
flexcan_fd_frame_t *framefd
Point to the buffer of CAN Message to be received from Enhanced Rx FIFO.
-
flexcan_edma_transfer_callback_t callback
FlexIO: FlexIO Driver
FlexIO Driver
-
void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().
Example:
flexio_config_t config; FLEXIO_GetDefaultConfig(&config);
- Parameters:
userConfig – pointer to flexio_config_t structure
-
void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
Example
flexio_config_t config = { .enableFlexio = true, .enableInDoze = false, .enableInDebug = true, .enableFastAccess = false }; FLEXIO_Configure(base, &config);
- Parameters:
base – FlexIO peripheral base address
userConfig – pointer to flexio_config_t structure
-
void FLEXIO_Deinit(FLEXIO_Type *base)
Gates the FlexIO clock. Call this API to stop the FlexIO clock.
Note
After calling this API, call the FLEXO_Init to use the FlexIO module.
- Parameters:
base – FlexIO peripheral base address
-
uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
Get instance number for FLEXIO module.
- Parameters:
base – FLEXIO peripheral base address.
-
void FLEXIO_Reset(FLEXIO_Type *base)
Resets the FlexIO module.
- Parameters:
base – FlexIO peripheral base address
-
static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
Enables the FlexIO module operation.
- Parameters:
base – FlexIO peripheral base address
enable – true to enable, false to disable.
-
static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
Reads the input data on each of the FlexIO pins.
- Parameters:
base – FlexIO peripheral base address
- Returns:
FlexIO pin input data
-
static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)
Gets the current state pointer for state mode use.
- Parameters:
base – FlexIO peripheral base address
- Returns:
current State pointer
-
void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.
Example
flexio_shifter_config_t config = { .timerSelect = 0, .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, .pinPolarity = kFLEXIO_PinActiveLow, .shifterMode = kFLEXIO_ShifterModeTransmit, .inputSource = kFLEXIO_ShifterInputFromPin, .shifterStop = kFLEXIO_ShifterStopBitHigh, .shifterStart = kFLEXIO_ShifterStartBitLow }; FLEXIO_SetShifterConfig(base, &config);
- Parameters:
base – FlexIO peripheral base address
index – Shifter index
shifterConfig – Pointer to flexio_shifter_config_t structure
-
void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.
Example
flexio_timer_config_t config = { .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, .triggerSource = kFLEXIO_TimerTriggerSourceInternal, .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, .pinSelect = 0, .pinPolarity = kFLEXIO_PinActiveHigh, .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, .timerStart = kFLEXIO_TimerStartBitEnabled }; FLEXIO_SetTimerConfig(base, &config);
- Parameters:
base – FlexIO peripheral base address
index – Timer index
timerConfig – Pointer to the flexio_timer_config_t structure
-
static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)
This function set the value of the prescaler on flexio channels.
- Parameters:
base – Pointer to the FlexIO simulated peripheral type.
index – Timer index
clocksource – Set clock value
-
static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.
Note
For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
-
static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.
Note
For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
-
static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.
Note
For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)
-
static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.
Note
For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)
-
static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.
Note
For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))
- Parameters:
base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)
-
static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.
Note
For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))
- Parameters:
base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)
-
static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
Gets the shifter status flags.
- Parameters:
base – FlexIO peripheral base address
- Returns:
Shifter status flags
-
static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)
Clears the shifter status flags.
Note
For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
-
static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
Gets the shifter error flags.
- Parameters:
base – FlexIO peripheral base address
- Returns:
Shifter error flags
-
static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)
Clears the shifter error flags.
Note
For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)
-
static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
Gets the timer status flags.
- Parameters:
base – FlexIO peripheral base address
- Returns:
Timer status flags
-
static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)
Clears the timer status flags.
Note
For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))
- Parameters:
base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)
-
static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)
Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.
Note
For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))
- Parameters:
base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
enable – True to enable, false to disable.
-
uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
Gets the shifter buffer address for the DMA transfer usage.
- Parameters:
base – FlexIO peripheral base address
type – Shifter type of flexio_shifter_buffer_type_t
index – Shifter index
- Returns:
Corresponding shifter buffer index
-
status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
- Parameters:
base – Pointer to the FlexIO simulated peripheral type.
handle – Pointer to the handler for FlexIO simulated peripheral.
isr – FlexIO simulated peripheral interrupt handler.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.
-
status_t FLEXIO_UnregisterHandleIRQ(void *base)
Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
- Parameters:
base – Pointer to the FlexIO simulated peripheral type.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.
-
static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)
Sets the output level of the multiple FLEXIO pins to the logic 0.
- Parameters:
base – FlexIO peripheral base address
mask – FLEXIO pin number mask
-
static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)
Sets the output level of the multiple FLEXIO pins to the logic 1.
- Parameters:
base – FlexIO peripheral base address
mask – FLEXIO pin number mask
-
static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)
Reverses the current output logic of the multiple FLEXIO pins.
- Parameters:
base – FlexIO peripheral base address
mask – FLEXIO pin number mask
-
static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)
Sets the output level of the FLEXIO pins to the logic 1 or 0.
- Parameters:
base – FlexIO peripheral base address
pin – FLEXIO pin number.
output – FLEXIO pin output logic level.
0: corresponding pin output low-logic level.
1: corresponding pin output high-logic level.
-
static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)
Enables the FLEXIO output pin function.
- Parameters:
base – FlexIO peripheral base address
pin – FLEXIO pin number.
-
static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)
Reads the current input value of the FLEXIO pin.
- Parameters:
base – FlexIO peripheral base address
pin – FLEXIO pin number.
- Return values:
FLEXIO – port input value
0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.
-
static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)
Gets the FLEXIO input pin status.
- Parameters:
base – FlexIO peripheral base address
pin – FLEXIO pin number.
- Return values:
FLEXIO – port input status
0: corresponding pin input capture no status.
1: corresponding pin input capture rising or falling edge.
-
static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)
Clears the multiple FLEXIO input pins status.
- Parameters:
base – FlexIO peripheral base address
mask – FLEXIO pin number mask
-
FSL_FLEXIO_DRIVER_VERSION
FlexIO driver version.
-
enum _flexio_timer_trigger_polarity
Define time of timer trigger polarity.
Values:
-
enumerator kFLEXIO_TimerTriggerPolarityActiveHigh
Active high.
-
enumerator kFLEXIO_TimerTriggerPolarityActiveLow
Active low.
-
enumerator kFLEXIO_TimerTriggerPolarityActiveHigh
-
enum _flexio_timer_trigger_source
Define type of timer trigger source.
Values:
-
enumerator kFLEXIO_TimerTriggerSourceExternal
External trigger selected.
-
enumerator kFLEXIO_TimerTriggerSourceInternal
Internal trigger selected.
-
enumerator kFLEXIO_TimerTriggerSourceExternal
-
enum _flexio_pin_config
Define type of timer/shifter pin configuration.
Values:
-
enumerator kFLEXIO_PinConfigOutputDisabled
Pin output disabled.
-
enumerator kFLEXIO_PinConfigOpenDrainOrBidirection
Pin open drain or bidirectional output enable.
-
enumerator kFLEXIO_PinConfigBidirectionOutputData
Pin bidirectional output data.
-
enumerator kFLEXIO_PinConfigOutput
Pin output.
-
enumerator kFLEXIO_PinConfigOutputDisabled
-
enum _flexio_pin_polarity
Definition of pin polarity.
Values:
-
enumerator kFLEXIO_PinActiveHigh
Active high.
-
enumerator kFLEXIO_PinActiveLow
Active low.
-
enumerator kFLEXIO_PinActiveHigh
-
enum _flexio_timer_mode
Define type of timer work mode.
Values:
-
enumerator kFLEXIO_TimerModeDisabled
Timer Disabled.
-
enumerator kFLEXIO_TimerModeDual8BitBaudBit
Dual 8-bit counters baud/bit mode.
-
enumerator kFLEXIO_TimerModeDual8BitPWM
Dual 8-bit counters PWM mode.
-
enumerator kFLEXIO_TimerModeSingle16Bit
Single 16-bit counter mode.
-
enumerator kFLEXIO_TimerModeDisabled
-
enum _flexio_timer_output
Define type of timer initial output or timer reset condition.
Values:
-
enumerator kFLEXIO_TimerOutputOneNotAffectedByReset
Logic one when enabled and is not affected by timer reset.
-
enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset
Logic zero when enabled and is not affected by timer reset.
-
enumerator kFLEXIO_TimerOutputOneAffectedByReset
Logic one when enabled and on timer reset.
-
enumerator kFLEXIO_TimerOutputZeroAffectedByReset
Logic zero when enabled and on timer reset.
-
enumerator kFLEXIO_TimerOutputOneNotAffectedByReset
-
enum _flexio_timer_decrement_source
Define type of timer decrement.
Values:
-
enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput
Decrement counter on FlexIO clock, Shift clock equals Timer output.
-
enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
-
enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
-
enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
-
enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput
-
enum _flexio_timer_reset_condition
Define type of timer reset condition.
Values:
-
enumerator kFLEXIO_TimerResetNever
Timer never reset.
-
enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput
Timer reset on Timer Pin equal to Timer Output.
-
enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput
Timer reset on Timer Trigger equal to Timer Output.
-
enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge
Timer reset on Timer Pin rising edge.
-
enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge
Timer reset on Trigger rising edge.
-
enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge
Timer reset on Trigger rising or falling edge.
-
enumerator kFLEXIO_TimerResetNever
-
enum _flexio_timer_disable_condition
Define type of timer disable condition.
Values:
-
enumerator kFLEXIO_TimerDisableNever
Timer never disabled.
-
enumerator kFLEXIO_TimerDisableOnPreTimerDisable
Timer disabled on Timer N-1 disable.
-
enumerator kFLEXIO_TimerDisableOnTimerCompare
Timer disabled on Timer compare.
-
enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow
Timer disabled on Timer compare and Trigger Low.
-
enumerator kFLEXIO_TimerDisableOnPinBothEdge
Timer disabled on Pin rising or falling edge.
-
enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh
Timer disabled on Pin rising or falling edge provided Trigger is high.
-
enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge
Timer disabled on Trigger falling edge.
-
enumerator kFLEXIO_TimerDisableNever
-
enum _flexio_timer_enable_condition
Define type of timer enable condition.
Values:
-
enumerator kFLEXIO_TimerEnabledAlways
Timer always enabled.
-
enumerator kFLEXIO_TimerEnableOnPrevTimerEnable
Timer enabled on Timer N-1 enable.
-
enumerator kFLEXIO_TimerEnableOnTriggerHigh
Timer enabled on Trigger high.
-
enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh
Timer enabled on Trigger high and Pin high.
-
enumerator kFLEXIO_TimerEnableOnPinRisingEdge
Timer enabled on Pin rising edge.
-
enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh
Timer enabled on Pin rising edge and Trigger high.
-
enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge
Timer enabled on Trigger rising edge.
-
enumerator kFLEXIO_TimerEnableOnTriggerBothEdge
Timer enabled on Trigger rising or falling edge.
-
enumerator kFLEXIO_TimerEnabledAlways
-
enum _flexio_timer_stop_bit_condition
Define type of timer stop bit generate condition.
Values:
-
enumerator kFLEXIO_TimerStopBitDisabled
Stop bit disabled.
-
enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare
Stop bit is enabled on timer compare.
-
enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable
Stop bit is enabled on timer disable.
-
enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable
Stop bit is enabled on timer compare and timer disable.
-
enumerator kFLEXIO_TimerStopBitDisabled
-
enum _flexio_timer_start_bit_condition
Define type of timer start bit generate condition.
Values:
-
enumerator kFLEXIO_TimerStartBitDisabled
Start bit disabled.
-
enumerator kFLEXIO_TimerStartBitEnabled
Start bit enabled.
-
enumerator kFLEXIO_TimerStartBitDisabled
-
enum _flexio_timer_output_state
FlexIO as PWM channel output state.
Values:
-
enumerator kFLEXIO_PwmLow
The output state of PWM channel is low
-
enumerator kFLEXIO_PwmHigh
The output state of PWM channel is high
-
enumerator kFLEXIO_PwmLow
-
enum _flexio_shifter_timer_polarity
Define type of timer polarity for shifter control.
Values:
-
enumerator kFLEXIO_ShifterTimerPolarityOnPositive
Shift on positive edge of shift clock.
-
enumerator kFLEXIO_ShifterTimerPolarityOnNegitive
Shift on negative edge of shift clock.
-
enumerator kFLEXIO_ShifterTimerPolarityOnPositive
-
enum _flexio_shifter_mode
Define type of shifter working mode.
Values:
-
enumerator kFLEXIO_ShifterDisabled
Shifter is disabled.
-
enumerator kFLEXIO_ShifterModeReceive
Receive mode.
-
enumerator kFLEXIO_ShifterModeTransmit
Transmit mode.
-
enumerator kFLEXIO_ShifterModeMatchStore
Match store mode.
-
enumerator kFLEXIO_ShifterModeMatchContinuous
Match continuous mode.
-
enumerator kFLEXIO_ShifterModeState
SHIFTBUF contents are used for storing programmable state attributes.
-
enumerator kFLEXIO_ShifterModeLogic
SHIFTBUF contents are used for implementing programmable logic look up table.
-
enumerator kFLEXIO_ShifterDisabled
-
enum _flexio_shifter_input_source
Define type of shifter input source.
Values:
-
enumerator kFLEXIO_ShifterInputFromPin
Shifter input from pin.
-
enumerator kFLEXIO_ShifterInputFromNextShifterOutput
Shifter input from Shifter N+1.
-
enumerator kFLEXIO_ShifterInputFromPin
-
enum _flexio_shifter_stop_bit
Define of STOP bit configuration.
Values:
-
enumerator kFLEXIO_ShifterStopBitDisable
Disable shifter stop bit.
-
enumerator kFLEXIO_ShifterStopBitLow
Set shifter stop bit to logic low level.
-
enumerator kFLEXIO_ShifterStopBitHigh
Set shifter stop bit to logic high level.
-
enumerator kFLEXIO_ShifterStopBitDisable
-
enum _flexio_shifter_start_bit
Define type of START bit configuration.
Values:
-
enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable
Disable shifter start bit, transmitter loads data on enable.
-
enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift
Disable shifter start bit, transmitter loads data on first shift.
-
enumerator kFLEXIO_ShifterStartBitLow
Set shifter start bit to logic low level.
-
enumerator kFLEXIO_ShifterStartBitHigh
Set shifter start bit to logic high level.
-
enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable
-
enum _flexio_shifter_buffer_type
Define FlexIO shifter buffer type.
Values:
-
enumerator kFLEXIO_ShifterBuffer
Shifter Buffer N Register.
-
enumerator kFLEXIO_ShifterBufferBitSwapped
Shifter Buffer N Bit Byte Swapped Register.
-
enumerator kFLEXIO_ShifterBufferByteSwapped
Shifter Buffer N Byte Swapped Register.
-
enumerator kFLEXIO_ShifterBufferBitByteSwapped
Shifter Buffer N Bit Swapped Register.
-
enumerator kFLEXIO_ShifterBufferNibbleByteSwapped
Shifter Buffer N Nibble Byte Swapped Register.
-
enumerator kFLEXIO_ShifterBufferHalfWordSwapped
Shifter Buffer N Half Word Swapped Register.
-
enumerator kFLEXIO_ShifterBufferNibbleSwapped
Shifter Buffer N Nibble Swapped Register.
-
enumerator kFLEXIO_ShifterBuffer
-
enum _flexio_gpio_direction
FLEXIO gpio direction definition.
Values:
-
enumerator kFLEXIO_DigitalInput
Set current pin as digital input
-
enumerator kFLEXIO_DigitalOutput
Set current pin as digital output
-
enumerator kFLEXIO_DigitalInput
-
enum _flexio_pin_input_config
FLEXIO gpio input config.
Values:
-
enumerator kFLEXIO_InputInterruptDisabled
Interrupt request is disabled.
-
enumerator kFLEXIO_InputInterruptEnable
Interrupt request is enable.
-
enumerator kFLEXIO_FlagRisingEdgeEnable
Input pin flag on rising edge.
-
enumerator kFLEXIO_FlagFallingEdgeEnable
Input pin flag on falling edge.
-
enumerator kFLEXIO_InputInterruptDisabled
-
typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t
Define time of timer trigger polarity.
-
typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t
Define type of timer trigger source.
-
typedef enum _flexio_pin_config flexio_pin_config_t
Define type of timer/shifter pin configuration.
-
typedef enum _flexio_pin_polarity flexio_pin_polarity_t
Definition of pin polarity.
-
typedef enum _flexio_timer_mode flexio_timer_mode_t
Define type of timer work mode.
-
typedef enum _flexio_timer_output flexio_timer_output_t
Define type of timer initial output or timer reset condition.
-
typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t
Define type of timer decrement.
-
typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t
Define type of timer reset condition.
-
typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t
Define type of timer disable condition.
-
typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t
Define type of timer enable condition.
-
typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t
Define type of timer stop bit generate condition.
-
typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t
Define type of timer start bit generate condition.
-
typedef enum _flexio_timer_output_state flexio_timer_output_state_t
FlexIO as PWM channel output state.
-
typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t
Define type of timer polarity for shifter control.
-
typedef enum _flexio_shifter_mode flexio_shifter_mode_t
Define type of shifter working mode.
-
typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t
Define type of shifter input source.
-
typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t
Define of STOP bit configuration.
-
typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t
Define type of START bit configuration.
-
typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t
Define FlexIO shifter buffer type.
-
typedef struct _flexio_config_ flexio_config_t
Define FlexIO user configuration structure.
-
typedef struct _flexio_timer_config flexio_timer_config_t
Define FlexIO timer configuration structure.
-
typedef struct _flexio_shifter_config flexio_shifter_config_t
Define FlexIO shifter configuration structure.
-
typedef enum _flexio_gpio_direction flexio_gpio_direction_t
FLEXIO gpio direction definition.
-
typedef enum _flexio_pin_input_config flexio_pin_input_config_t
FLEXIO gpio input config.
-
typedef struct _flexio_gpio_config flexio_gpio_config_t
The FLEXIO pin configuration structure.
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.
-
typedef void (*flexio_isr_t)(void *base, void *handle)
typedef for FlexIO simulated driver interrupt handler.
-
FLEXIO_Type *const s_flexioBases[]
Pointers to flexio bases for each instance.
-
const clock_ip_name_t s_flexioClocks[]
Pointers to flexio clocks for each instance.
-
void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)
Configure a FLEXIO pin used by the board.
To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.
This is an example to define an input pin or an output pin configuration.
Define a digital input pin configuration, flexio_gpio_config_t config = { kFLEXIO_DigitalInput, 0U, kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, } Define a digital output pin configuration, flexio_gpio_config_t config = { kFLEXIO_DigitalOutput, 0U, 0U }
- Parameters:
base – FlexIO peripheral base address
pin – FLEXIO pin number.
config – FLEXIO pin configuration pointer.
-
FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)
Calculate FlexIO timer trigger.
-
FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)
-
FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)
-
struct _flexio_config_
- #include <fsl_flexio.h>
Define FlexIO user configuration structure.
Public Members
-
bool enableFlexio
Enable/disable FlexIO module
-
bool enableInDoze
Enable/disable FlexIO operation in doze mode
-
bool enableInDebug
Enable/disable FlexIO operation in debug mode
-
bool enableFastAccess
Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.
-
bool enableFlexio
-
struct _flexio_timer_config
- #include <fsl_flexio.h>
Define FlexIO timer configuration structure.
Public Members
-
uint32_t triggerSelect
The internal trigger selection number using MACROs.
-
flexio_timer_trigger_polarity_t triggerPolarity
Trigger Polarity.
-
flexio_timer_trigger_source_t triggerSource
Trigger Source, internal (see ‘trgsel’) or external.
-
flexio_pin_config_t pinConfig
Timer Pin Configuration.
-
uint32_t pinSelect
Timer Pin number Select.
-
flexio_pin_polarity_t pinPolarity
Timer Pin Polarity.
-
flexio_timer_mode_t timerMode
Timer work Mode.
-
flexio_timer_output_t timerOutput
Configures the initial state of the Timer Output and whether it is affected by the Timer reset.
-
flexio_timer_decrement_source_t timerDecrement
Configures the source of the Timer decrement and the source of the Shift clock.
-
flexio_timer_reset_condition_t timerReset
Configures the condition that causes the timer counter (and optionally the timer output) to be reset.
-
flexio_timer_disable_condition_t timerDisable
Configures the condition that causes the Timer to be disabled and stop decrementing.
-
flexio_timer_enable_condition_t timerEnable
Configures the condition that causes the Timer to be enabled and start decrementing.
-
flexio_timer_stop_bit_condition_t timerStop
Timer STOP Bit generation.
-
flexio_timer_start_bit_condition_t timerStart
Timer STRAT Bit generation.
-
uint32_t timerCompare
Value for Timer Compare N Register.
-
uint32_t triggerSelect
-
struct _flexio_shifter_config
- #include <fsl_flexio.h>
Define FlexIO shifter configuration structure.
Public Members
-
uint32_t timerSelect
Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.
-
flexio_shifter_timer_polarity_t timerPolarity
Timer Polarity.
-
flexio_pin_config_t pinConfig
Shifter Pin Configuration.
-
uint32_t pinSelect
Shifter Pin number Select.
-
flexio_pin_polarity_t pinPolarity
Shifter Pin Polarity.
-
flexio_shifter_mode_t shifterMode
Configures the mode of the Shifter.
-
uint32_t parallelWidth
Configures the parallel width when using parallel mode.
-
flexio_shifter_input_source_t inputSource
Selects the input source for the shifter.
-
flexio_shifter_stop_bit_t shifterStop
Shifter STOP bit.
-
flexio_shifter_start_bit_t shifterStart
Shifter START bit.
-
uint32_t timerSelect
-
struct _flexio_gpio_config
- #include <fsl_flexio.h>
The FLEXIO pin configuration structure.
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.
Public Members
-
flexio_gpio_direction_t pinDirection
FLEXIO pin direction, input or output
-
uint8_t outputLogic
Set a default output logic, which has no use in input
-
uint8_t inputConfig
Set an input config
-
flexio_gpio_direction_t pinDirection
FlexIO eDMA I2S Driver
-
void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)
Initializes the FlexIO I2S eDMA handle.
This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
-
void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)
Initializes the FlexIO I2S Rx eDMA handle.
This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
-
void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
Configures the FlexIO I2S Tx audio format.
Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
-
status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)
Performs a non-blocking FlexIO I2S transfer using DMA.
Note
This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.
- Return values:
kStatus_Success – Start a FlexIO I2S eDMA send successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_TxBusy – FlexIO I2S is busy sending data.
-
status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)
Performs a non-blocking FlexIO I2S receive using eDMA.
Note
This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.
- Return values:
kStatus_Success – Start a FlexIO I2S eDMA receive successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_RxBusy – FlexIO I2S is busy receiving data.
-
void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
Aborts a FlexIO I2S transfer using eDMA.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
-
void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
Aborts a FlexIO I2S receive using eDMA.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
-
status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
Gets the remaining bytes to be sent.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes sent.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
Get the remaining bytes to be received.
- Parameters:
base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes received.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION
FlexIO I2S EDMA driver version 2.1.8.
-
typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t
-
typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData)
FlexIO I2S eDMA transfer callback function for finish and error.
-
struct _flexio_i2s_edma_handle
- #include <fsl_flexio_i2s_edma.h>
FlexIO I2S DMA transfer handle, users should not touch the content of the handle.
Public Members
-
edma_handle_t *dmaHandle
DMA handler for FlexIO I2S send
-
uint8_t bytesPerFrame
Bytes in a frame
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
uint32_t state
Internal state for FlexIO I2S eDMA transfer
-
flexio_i2s_edma_callback_t callback
Callback for users while transfer finish or error occurred
-
void *userData
User callback parameter
-
edma_tcd_t tcd[(4U) + 1U]
TCD pool for eDMA transfer.
-
flexio_i2s_transfer_t queue[(4U)]
Transfer queue storing queued transfer.
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer.
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
edma_handle_t *dmaHandle
FlexIO eDMA SPI Driver
-
status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)
Initializes the FlexIO SPI master eDMA handle.
This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.
-
status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)
Performs a non-blocking FlexIO SPI transfer using eDMA.
Note
This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.
- Return values:
kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.
-
void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
Aborts a FlexIO SPI transfer using eDMA.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
-
status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)
Gets the number of bytes transferred so far using FlexIO SPI master eDMA.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.
-
static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)
Initializes the FlexIO SPI slave eDMA handle.
This function initializes the FlexIO SPI slave eDMA handle.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.
-
status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)
Performs a non-blocking FlexIO SPI transfer using eDMA.
Note
This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.
- Return values:
kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.
-
static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)
Aborts a FlexIO SPI transfer using eDMA.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
-
static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)
Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.
- Parameters:
base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.
-
FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION
FlexIO SPI EDMA driver version.
-
typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t
typedef for flexio_spi_master_edma_handle_t in advance.
-
typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t
Slave handle is the same with master handle.
-
typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData)
FlexIO SPI master callback for finished transmit.
-
typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData)
FlexIO SPI slave callback for finished transmit.
-
struct _flexio_spi_master_edma_handle
- #include <fsl_flexio_spi_edma.h>
FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.
Public Members
-
size_t transferSize
Total bytes to be transferred.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
bool txInProgress
Send transfer in progress
-
bool rxInProgress
Receive transfer in progress
-
edma_handle_t *txHandle
DMA handler for SPI send
-
edma_handle_t *rxHandle
DMA handler for SPI receive
-
flexio_spi_master_edma_transfer_callback_t callback
Callback for SPI DMA transfer
-
void *userData
User Data for SPI DMA callback
-
size_t transferSize
FlexIO eDMA UART Driver
-
status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)
Initializes the UART handle which is used in transactional functions.
- Parameters:
base – Pointer to FLEXIO_UART_Type.
handle – Pointer to flexio_uart_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.
txEdmaHandle – User requested DMA handle for TX DMA transfer.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.
-
status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)
Sends data using eDMA.
This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – UART handle pointer.
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.
-
status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)
Receives data using eDMA.
This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_UART_RxBusy – Previous transfer on going.
-
void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
Aborts the sent data which using eDMA.
This function aborts sent data which using eDMA.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
-
void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
Aborts the receive data which using eDMA.
This function aborts the receive data which using eDMA.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
-
status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
Gets the number of bytes sent out.
This function gets the number of bytes sent out.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes sent so far by the non-blocking transaction.
- Return values:
kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.
-
status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
Gets the number of bytes received.
This function gets the number of bytes received.
- Parameters:
base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes received so far by the non-blocking transaction.
- Return values:
kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.
-
FSL_FLEXIO_UART_EDMA_DRIVER_VERSION
FlexIO UART EDMA driver version.
-
typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t
-
typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData)
UART transfer callback function.
-
struct _flexio_uart_edma_handle
- #include <fsl_flexio_uart_edma.h>
UART eDMA handle.
Public Members
-
flexio_uart_edma_transfer_callback_t callback
Callback function.
-
void *userData
UART callback function parameter.
-
size_t txDataSizeAll
Total bytes to be sent.
-
size_t rxDataSizeAll
Total bytes to be received.
-
edma_handle_t *txEdmaHandle
The eDMA TX channel used.
-
edma_handle_t *rxEdmaHandle
The eDMA RX channel used.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
volatile uint8_t txState
TX transfer state.
-
volatile uint8_t rxState
RX transfer state
-
flexio_uart_edma_transfer_callback_t callback
FlexIO I2C Master Driver
-
status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)
Make sure the bus isn’t already pulled down.
Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure..
- Return values:
kStatus_Success –
kStatus_FLEXIO_I2C_Busy –
-
status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.
Example
FLEXIO_I2C_Type base = { .flexioBase = FLEXIO, .SDAPinIndex = 0, .SCLPinIndex = 1, .shifterIndex = {0,1}, .timerIndex = {0,1} }; flexio_i2c_master_config_t config = { .enableInDoze = false, .enableInDebug = true, .enableFastAccess = false, .baudRate_Bps = 100000 }; FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
masterConfig – Pointer to flexio_i2c_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.
- Return values:
kStatus_Success – Initialization successful
kStatus_InvalidArgument – The source clock exceed upper range limitation
-
void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.
- Parameters:
base – pointer to FLEXIO_I2C_Type structure.
-
void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().
Example:
flexio_i2c_master_config_t config; FLEXIO_I2C_MasterGetDefaultConfig(&config);
- Parameters:
masterConfig – Pointer to flexio_i2c_master_config_t structure.
-
static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
Enables/disables the FlexIO module operation.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
enable – Pass true to enable module, false does not have any effect.
-
uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
Gets the FlexIO I2C master status flags.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure
- Returns:
Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.
-
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
Clears the FlexIO I2C master status flags.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
kFLEXIO_I2C_RxFullFlag
kFLEXIO_I2C_ReceiveNakFlag
-
void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
Enables the FlexIO i2c master interrupt requests.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source. Currently only one interrupt request source:
kFLEXIO_I2C_TransferCompleteInterruptEnable
-
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
Disables the FlexIO I2C master interrupt requests.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source.
-
void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
Sets the FlexIO I2C master transfer baudrate.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure
baudRate_Bps – the baud rate value in HZ
srcClock_Hz – source clock in HZ
-
void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
Sends START + 7-bit address to the bus.
Note
This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
address – 7-bit address.
direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:
kFLEXIO_I2C_Write: Transmit
kFLEXIO_I2C_Read: Receive
-
void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
Sends the stop signal on the bus.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
-
void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
Sends the repeated start signal on the bus.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
-
void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
Sends the stop signal when transfer is still on-going.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
-
void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
Configures the sent ACK/NAK for the following byte.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
enable – True to configure send ACK, false configure to send NAK.
-
status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)
Sets the number of bytes to be transferred from a start signal to a stop signal.
Note
Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
count – Number of bytes need to be transferred from a start signal to a re-start/stop signal
- Return values:
kStatus_Success – Successfully configured the count.
kStatus_InvalidArgument – Input argument is invalid.
-
static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)
Writes one byte of data to the I2C bus.
Note
This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
data – a byte of data.
-
static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)
Reads one byte of data from the I2C bus.
Note
This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
- Returns:
data byte read.
-
status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
Sends a buffer of data in bytes.
Note
This function blocks via polling until all bytes have been sent.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
txBuff – The data bytes to send.
txSize – The number of data bytes to send.
- Return values:
kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.
-
status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
Receives a buffer of bytes.
Note
This function blocks via polling until all bytes have been received.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
rxBuff – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.
- Return values:
kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.
-
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
Performs a master polling transfer on the I2C bus.
Note
The API does not return until the transfer succeeds or fails due to receiving NAK.
- Parameters:
base – pointer to FLEXIO_I2C_Type structure.
xfer – pointer to flexio_i2c_master_transfer_t structure.
- Returns:
status of status_t.
-
status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)
Initializes the I2C handle which is used in transactional functions.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
callback – Pointer to user callback function.
userData – User param passed to the callback function.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.
-
status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)
Performs a master interrupt non-blocking transfer on the I2C bus.
Note
The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
xfer – pointer to flexio_i2c_master_transfer_t structure
- Return values:
kStatus_Success – Successfully start a transfer.
kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.
-
status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
Gets the master transfer status during a interrupt non-blocking transfer.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
kStatus_Success – Successfully return the count.
-
void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
Aborts an interrupt non-blocking transfer early.
Note
This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
-
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
Master interrupt handler.
- Parameters:
i2cType – Pointer to FLEXIO_I2C_Type structure
i2cHandle – Pointer to flexio_i2c_master_transfer_t structure
-
FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION
FlexIO I2C transfer status.
Values:
-
enumerator kStatus_FLEXIO_I2C_Busy
I2C is busy doing transfer.
-
enumerator kStatus_FLEXIO_I2C_Idle
I2C is busy doing transfer.
-
enumerator kStatus_FLEXIO_I2C_Nak
NAK received during transfer.
-
enumerator kStatus_FLEXIO_I2C_Timeout
Timeout polling status flags.
-
enumerator kStatus_FLEXIO_I2C_Busy
-
enum _flexio_i2c_master_interrupt
Define FlexIO I2C master interrupt mask.
Values:
-
enumerator kFLEXIO_I2C_TxEmptyInterruptEnable
Tx buffer empty interrupt enable.
-
enumerator kFLEXIO_I2C_RxFullInterruptEnable
Rx buffer full interrupt enable.
-
enumerator kFLEXIO_I2C_TxEmptyInterruptEnable
-
enum _flexio_i2c_master_status_flags
Define FlexIO I2C master status mask.
Values:
-
enumerator kFLEXIO_I2C_TxEmptyFlag
Tx shifter empty flag.
-
enumerator kFLEXIO_I2C_RxFullFlag
Rx shifter full/Transfer complete flag.
-
enumerator kFLEXIO_I2C_ReceiveNakFlag
Receive NAK flag.
-
enumerator kFLEXIO_I2C_TxEmptyFlag
-
enum _flexio_i2c_direction
Direction of master transfer.
Values:
-
enumerator kFLEXIO_I2C_Write
Master send to slave.
-
enumerator kFLEXIO_I2C_Read
Master receive from slave.
-
enumerator kFLEXIO_I2C_Write
-
typedef enum _flexio_i2c_direction flexio_i2c_direction_t
Direction of master transfer.
-
typedef struct _flexio_i2c_type FLEXIO_I2C_Type
Define FlexIO I2C master access structure typedef.
-
typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t
Define FlexIO I2C master user configuration structure.
-
typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t
Define FlexIO I2C master transfer structure.
-
typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t
FlexIO I2C master handle typedef.
-
typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData)
FlexIO I2C master transfer callback typedef.
-
I2C_RETRY_TIMES
Retry times for waiting flag.
-
struct _flexio_i2c_type
- #include <fsl_flexio_i2c_master.h>
Define FlexIO I2C master access structure typedef.
Public Members
-
FLEXIO_Type *flexioBase
FlexIO base pointer.
-
uint8_t SDAPinIndex
Pin select for I2C SDA.
-
uint8_t SCLPinIndex
Pin select for I2C SCL.
-
uint8_t shifterIndex[2]
Shifter index used in FlexIO I2C.
-
uint8_t timerIndex[3]
Timer index used in FlexIO I2C.
-
uint32_t baudrate
Master transfer baudrate, used to calculate delay time.
-
FLEXIO_Type *flexioBase
-
struct _flexio_i2c_master_config
- #include <fsl_flexio_i2c_master.h>
Define FlexIO I2C master user configuration structure.
Public Members
-
bool enableMaster
Enables the FlexIO I2C peripheral at initialization time.
-
bool enableInDoze
Enable/disable FlexIO operation in doze mode.
-
bool enableInDebug
Enable/disable FlexIO operation in debug mode.
-
bool enableFastAccess
Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.
-
uint32_t baudRate_Bps
Baud rate in Bps.
-
bool enableMaster
-
struct _flexio_i2c_master_transfer
- #include <fsl_flexio_i2c_master.h>
Define FlexIO I2C master transfer structure.
Public Members
-
uint32_t flags
Transfer flag which controls the transfer, reserved for FlexIO I2C.
-
uint8_t slaveAddress
7-bit slave address.
-
flexio_i2c_direction_t direction
Transfer direction, read or write.
-
uint32_t subaddress
Sub address. Transferred MSB first.
-
uint8_t subaddressSize
Size of command buffer.
-
uint8_t volatile *data
Transfer buffer.
-
volatile size_t dataSize
Transfer size.
-
uint32_t flags
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struct _flexio_i2c_master_handle
- #include <fsl_flexio_i2c_master.h>
Define FlexIO I2C master handle structure.
Public Members
-
flexio_i2c_master_transfer_t transfer
FlexIO I2C master transfer copy.
-
size_t transferSize
Total bytes to be transferred.
-
uint8_t state
Transfer state maintained during transfer.
-
flexio_i2c_master_transfer_callback_t completionCallback
Callback function called at transfer event. Callback function called at transfer event.
-
void *userData
Callback parameter passed to callback function.
-
bool needRestart
Whether master needs to send re-start signal.
-
flexio_i2c_master_transfer_t transfer
FlexIO I2S Driver
-
void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
Initializes the FlexIO I2S.
This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().
Note
This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.
- Parameters:
base – FlexIO I2S base pointer
config – FlexIO I2S configure structure.
-
void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
Sets the FlexIO I2S configuration structure to default values.
The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().
- Parameters:
config – pointer to master configuration structure
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void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
De-initializes the FlexIO I2S.
Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.
- Parameters:
base – FlexIO I2S base pointer
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static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
Enables/disables the FlexIO I2S module operation.
- Parameters:
base – Pointer to FLEXIO_I2S_Type
enable – True to enable, false dose not have any effect.
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uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
Gets the FlexIO I2S status flags.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
- Returns:
Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
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void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
Enables the FlexIO I2S interrupt.
This function enables the FlexIO UART interrupt.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
mask – interrupt source
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void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
Disables the FlexIO I2S interrupt.
This function enables the FlexIO UART interrupt.
- Parameters:
base – pointer to FLEXIO_I2S_Type structure
mask – interrupt source
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static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
Enables/disables the FlexIO I2S Tx DMA requests.
- Parameters:
base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.
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static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
Enables/disables the FlexIO I2S Rx DMA requests.
- Parameters:
base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.
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static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
Gets the FlexIO I2S send data register address.
This function returns the I2S data register address, mainly used by DMA/eDMA.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
- Returns:
FlexIO i2s send data register address.
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static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
Gets the FlexIO I2S receive data register address.
This function returns the I2S data register address, mainly used by DMA/eDMA.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
- Returns:
FlexIO i2s receive data register address.
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void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
Configures the FlexIO I2S audio format in master mode.
Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – I2S master clock source frequency in Hz.
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void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
Configures the FlexIO I2S audio format in slave mode.
Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.
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status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
Sends data using a blocking method.
Note
This function blocks via polling until data is ready to be sent.
- Parameters:
base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
txData – Pointer to the data to be written.
size – Bytes to be written.
- Return values:
kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.
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static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)
Writes data into a data register.
- Parameters:
base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
data – Data to be written.
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status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
Receives a piece of data using a blocking method.
Note
This function blocks via polling until data is ready to be sent.
- Parameters:
base – FlexIO I2S base pointer
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
rxData – Pointer to the data to be read.
size – Bytes to be read.
- Return values:
kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.
-
static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)
Reads a data from the data register.
- Parameters:
base – FlexIO I2S base pointer
- Returns:
Data read from data register.
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void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)
Initializes the FlexIO I2S handle.
This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.
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void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
Configures the FlexIO I2S audio format.
Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – FlexIO I2S handle pointer.
format – Pointer to audio data format structure.
srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
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void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)
Initializes the FlexIO I2S receive handle.
This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.
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status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)
Performs an interrupt non-blocking send transfer on FlexIO I2S.
Note
The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure
- Return values:
kStatus_Success – Successfully start the data transmission.
kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.
kStatus_InvalidArgument – The input parameter is invalid.
-
status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)
Performs an interrupt non-blocking receive transfer on FlexIO I2S.
Note
The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure
- Return values:
kStatus_Success – Successfully start the data receive.
kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.
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void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
Aborts the current send.
Note
This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
-
void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
Aborts the current receive.
Note
This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
-
status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
Gets the remaining bytes to be sent.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes sent.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
Gets the remaining bytes to be received.
- Parameters:
base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes recieved.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
- Returns:
count Bytes received.
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void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
Tx interrupt handler.
- Parameters:
i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure
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void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
Rx interrupt handler.
- Parameters:
i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure.
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FSL_FLEXIO_I2S_DRIVER_VERSION
FlexIO I2S driver version 2.2.0.
FlexIO I2S transfer status.
Values:
-
enumerator kStatus_FLEXIO_I2S_Idle
FlexIO I2S is in idle state
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enumerator kStatus_FLEXIO_I2S_TxBusy
FlexIO I2S Tx is busy
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enumerator kStatus_FLEXIO_I2S_RxBusy
FlexIO I2S Tx is busy
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enumerator kStatus_FLEXIO_I2S_Error
FlexIO I2S error occurred
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enumerator kStatus_FLEXIO_I2S_QueueFull
FlexIO I2S transfer queue is full.
-
enumerator kStatus_FLEXIO_I2S_Timeout
FlexIO I2S timeout polling status flags.
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enumerator kStatus_FLEXIO_I2S_Idle
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enum _flexio_i2s_master_slave
Master or slave mode.
Values:
-
enumerator kFLEXIO_I2S_Master
Master mode
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enumerator kFLEXIO_I2S_Slave
Slave mode
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enumerator kFLEXIO_I2S_Master
_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.
Values:
-
enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable
Transmit buffer empty interrupt enable.
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enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable
Receive buffer full interrupt enable.
-
enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable
_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.
Values:
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enumerator kFLEXIO_I2S_TxDataRegEmptyFlag
Transmit buffer empty flag.
-
enumerator kFLEXIO_I2S_RxDataRegFullFlag
Receive buffer full flag.
-
enumerator kFLEXIO_I2S_TxDataRegEmptyFlag
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enum _flexio_i2s_sample_rate
Audio sample rate.
Values:
-
enumerator kFLEXIO_I2S_SampleRate8KHz
Sample rate 8000Hz
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enumerator kFLEXIO_I2S_SampleRate11025Hz
Sample rate 11025Hz
-
enumerator kFLEXIO_I2S_SampleRate12KHz
Sample rate 12000Hz
-
enumerator kFLEXIO_I2S_SampleRate16KHz
Sample rate 16000Hz
-
enumerator kFLEXIO_I2S_SampleRate22050Hz
Sample rate 22050Hz
-
enumerator kFLEXIO_I2S_SampleRate24KHz
Sample rate 24000Hz
-
enumerator kFLEXIO_I2S_SampleRate32KHz
Sample rate 32000Hz
-
enumerator kFLEXIO_I2S_SampleRate44100Hz
Sample rate 44100Hz
-
enumerator kFLEXIO_I2S_SampleRate48KHz
Sample rate 48000Hz
-
enumerator kFLEXIO_I2S_SampleRate96KHz
Sample rate 96000Hz
-
enumerator kFLEXIO_I2S_SampleRate8KHz
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enum _flexio_i2s_word_width
Audio word width.
Values:
-
enumerator kFLEXIO_I2S_WordWidth8bits
Audio data width 8 bits
-
enumerator kFLEXIO_I2S_WordWidth16bits
Audio data width 16 bits
-
enumerator kFLEXIO_I2S_WordWidth24bits
Audio data width 24 bits
-
enumerator kFLEXIO_I2S_WordWidth32bits
Audio data width 32 bits
-
enumerator kFLEXIO_I2S_WordWidth8bits
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typedef struct _flexio_i2s_type FLEXIO_I2S_Type
Define FlexIO I2S access structure typedef.
-
typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t
Master or slave mode.
-
typedef struct _flexio_i2s_config flexio_i2s_config_t
FlexIO I2S configure structure.
-
typedef struct _flexio_i2s_format flexio_i2s_format_t
FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.
-
typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t
Audio sample rate.
-
typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t
Audio word width.
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typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t
Define FlexIO I2S transfer structure.
-
typedef struct _flexio_i2s_handle flexio_i2s_handle_t
-
typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData)
FlexIO I2S xfer callback prototype.
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I2S_RETRY_TIMES
Retry times for waiting flag.
-
FLEXIO_I2S_XFER_QUEUE_SIZE
FlexIO I2S transfer queue size, user can refine it according to use case.
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struct _flexio_i2s_type
- #include <fsl_flexio_i2s.h>
Define FlexIO I2S access structure typedef.
Public Members
-
FLEXIO_Type *flexioBase
FlexIO base pointer
-
uint8_t txPinIndex
Tx data pin index in FlexIO pins
-
uint8_t rxPinIndex
Rx data pin index
-
uint8_t bclkPinIndex
Bit clock pin index
-
uint8_t fsPinIndex
Frame sync pin index
-
uint8_t txShifterIndex
Tx data shifter index
-
uint8_t rxShifterIndex
Rx data shifter index
-
uint8_t bclkTimerIndex
Bit clock timer index
-
uint8_t fsTimerIndex
Frame sync timer index
-
FLEXIO_Type *flexioBase
-
struct _flexio_i2s_config
- #include <fsl_flexio_i2s.h>
FlexIO I2S configure structure.
Public Members
-
bool enableI2S
Enable FlexIO I2S
-
flexio_i2s_master_slave_t masterSlave
Master or slave
-
flexio_pin_polarity_t txPinPolarity
Tx data pin polarity, active high or low
-
flexio_pin_polarity_t rxPinPolarity
Rx data pin polarity
-
flexio_pin_polarity_t bclkPinPolarity
Bit clock pin polarity
-
flexio_pin_polarity_t fsPinPolarity
Frame sync pin polarity
-
flexio_shifter_timer_polarity_t txTimerPolarity
Tx data valid on bclk rising or falling edge
-
flexio_shifter_timer_polarity_t rxTimerPolarity
Rx data valid on bclk rising or falling edge
-
bool enableI2S
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struct _flexio_i2s_format
- #include <fsl_flexio_i2s.h>
FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.
Public Members
-
uint8_t bitWidth
Bit width of audio data, always 8/16/24/32 bits
-
uint32_t sampleRate_Hz
Sample rate of the audio data
-
uint8_t bitWidth
-
struct _flexio_i2s_transfer
- #include <fsl_flexio_i2s.h>
Define FlexIO I2S transfer structure.
Public Members
-
uint8_t *data
Data buffer start pointer
-
size_t dataSize
Bytes to be transferred.
-
uint8_t *data
-
struct _flexio_i2s_handle
- #include <fsl_flexio_i2s.h>
Define FlexIO I2S handle structure.
Public Members
-
uint32_t state
Internal state
-
flexio_i2s_callback_t callback
Callback function called at transfer event
-
void *userData
Callback parameter passed to callback function
-
uint8_t bitWidth
Bit width for transfer, 8/16/24/32bits
-
flexio_i2s_transfer_t queue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint32_t state
FlexIO SPI Driver
-
void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().
Example
FLEXIO_SPI_Type spiDev = { .flexioBase = FLEXIO, .SDOPinIndex = 0, .SDIPinIndex = 1, .SCKPinIndex = 2, .CSnPinIndex = 3, .shifterIndex = {0,1}, .timerIndex = {0,1} }; flexio_spi_master_config_t config = { .enableMaster = true, .enableInDoze = false, .enableInDebug = true, .enableFastAccess = false, .baudRate_Bps = 500000, .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, .direction = kFLEXIO_SPI_MsbFirst, .dataMode = kFLEXIO_SPI_8BitMode }; FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
Note
1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
masterConfig – Pointer to the flexio_spi_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.
-
void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
Resets the FlexIO SPI timer and shifter config.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type.
-
void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:
flexio_spi_master_config_t masterConfig; FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
- Parameters:
masterConfig – Pointer to the flexio_spi_master_config_t structure.
-
void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().
Note
1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example
FLEXIO_SPI_Type spiDev = { .flexioBase = FLEXIO, .SDOPinIndex = 0, .SDIPinIndex = 1, .SCKPinIndex = 2, .CSnPinIndex = 3, .shifterIndex = {0,1}, .timerIndex = {0} }; flexio_spi_slave_config_t config = { .enableSlave = true, .enableInDoze = false, .enableInDebug = true, .enableFastAccess = false, .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, .direction = kFLEXIO_SPI_MsbFirst, .dataMode = kFLEXIO_SPI_8BitMode }; FLEXIO_SPI_SlaveInit(&spiDev, &config);
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
slaveConfig – Pointer to the flexio_spi_slave_config_t structure.
-
void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
Gates the FlexIO clock.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type.
-
void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:
flexio_spi_slave_config_t slaveConfig; FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
- Parameters:
slaveConfig – Pointer to the flexio_spi_slave_config_t structure.
-
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
Gets FlexIO SPI status flags.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
- Returns:
status flag; Use the status flag to AND the following flag mask and get the status.
kFLEXIO_SPI_TxEmptyFlag
kFLEXIO_SPI_RxEmptyFlag
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void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
Clears FlexIO SPI status flags.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
mask – status flag The parameter can be any combination of the following values:
kFLEXIO_SPI_TxEmptyFlag
kFLEXIO_SPI_RxEmptyFlag
-
void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
Enables the FlexIO SPI interrupt.
This function enables the FlexIO SPI interrupt.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source. The parameter can be any combination of the following values:
kFLEXIO_SPI_RxFullInterruptEnable
kFLEXIO_SPI_TxEmptyInterruptEnable
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void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
Disables the FlexIO SPI interrupt.
This function disables the FlexIO SPI interrupt.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source The parameter can be any combination of the following values:
kFLEXIO_SPI_RxFullInterruptEnable
kFLEXIO_SPI_TxEmptyInterruptEnable
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void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
mask – SPI DMA source.
enable – True means enable DMA, false means disable DMA.
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static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
Gets the FlexIO SPI transmit data register address for MSB first transfer.
This function returns the SPI data register address, which is mainly used by DMA/eDMA.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
- Returns:
FlexIO SPI transmit data register address.
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static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
Gets the FlexIO SPI receive data register address for the MSB first transfer.
This function returns the SPI data register address, which is mainly used by DMA/eDMA.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
- Returns:
FlexIO SPI receive data register address.
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static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
Enables/disables the FlexIO SPI module operation.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type.
enable – True to enable, false does not have any effect.
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void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
baudRate_Bps – Baud Rate needed in Hz.
srcClockHz – SPI source clock frequency in Hz.
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static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
Writes one byte of data, which is sent using the MSB method.
Note
This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
data – 8/16/32 bit data.
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static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
Reads 8 bit/16 bit data.
Note
This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
- Returns:
8 bit/16 bit data received.
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status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)
Sends a buffer of data bytes.
Note
This function blocks using the polling method until all bytes have been sent.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The data bytes to send.
size – The number of data bytes to send.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.
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status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)
Receives a buffer of bytes.
Note
This function blocks using the polling method until all bytes have been received.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The buffer to store the received bytes.
size – The number of data bytes to be received.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.
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status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
Receives a buffer of bytes.
Note
This function blocks via polling until all bytes have been received.
- Parameters:
base – pointer to FLEXIO_SPI_Type structure
xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.
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void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)
Flush tx/rx shifters.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
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status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)
Initializes the FlexIO SPI Master handle, which is used in transactional functions.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.
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status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)
Master transfer data using IRQ.
This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.
- Return values:
kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.
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void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
Aborts the master data transfer, which used IRQ.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
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status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
Gets the data transfer status which used IRQ.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
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void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
FlexIO SPI master IRQ handler function.
- Parameters:
spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
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status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)
Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.
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status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)
Slave transfer data using IRQ.
This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.
- Parameters:
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
base – Pointer to the FLEXIO_SPI_Type structure.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.
- Return values:
kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.
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static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
Aborts the slave data transfer which used IRQ, share same API with master.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
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static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)
Gets the data transfer status which used IRQ, share same API with master.
- Parameters:
base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
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void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
FlexIO SPI slave IRQ handler function.
- Parameters:
spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
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FSL_FLEXIO_SPI_DRIVER_VERSION
FlexIO SPI driver version.
Error codes for the FlexIO SPI driver.
Values:
-
enumerator kStatus_FLEXIO_SPI_Busy
FlexIO SPI is busy.
-
enumerator kStatus_FLEXIO_SPI_Idle
SPI is idle
-
enumerator kStatus_FLEXIO_SPI_Error
FlexIO SPI error.
-
enumerator kStatus_FLEXIO_SPI_Timeout
FlexIO SPI timeout polling status flags.
-
enumerator kStatus_FLEXIO_SPI_Busy
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enum _flexio_spi_clock_phase
FlexIO SPI clock phase configuration.
Values:
-
enumerator kFLEXIO_SPI_ClockPhaseFirstEdge
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
-
enumerator kFLEXIO_SPI_ClockPhaseSecondEdge
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
-
enumerator kFLEXIO_SPI_ClockPhaseFirstEdge
-
enum _flexio_spi_shift_direction
FlexIO SPI data shifter direction options.
Values:
-
enumerator kFLEXIO_SPI_MsbFirst
Data transfers start with most significant bit.
-
enumerator kFLEXIO_SPI_LsbFirst
Data transfers start with least significant bit.
-
enumerator kFLEXIO_SPI_MsbFirst
-
enum _flexio_spi_data_bitcount_mode
FlexIO SPI data length mode options.
Values:
-
enumerator kFLEXIO_SPI_8BitMode
8-bit data transmission mode.
-
enumerator kFLEXIO_SPI_16BitMode
16-bit data transmission mode.
-
enumerator kFLEXIO_SPI_32BitMode
32-bit data transmission mode.
-
enumerator kFLEXIO_SPI_8BitMode
-
enum _flexio_spi_interrupt_enable
Define FlexIO SPI interrupt mask.
Values:
-
enumerator kFLEXIO_SPI_TxEmptyInterruptEnable
Transmit buffer empty interrupt enable.
-
enumerator kFLEXIO_SPI_RxFullInterruptEnable
Receive buffer full interrupt enable.
-
enumerator kFLEXIO_SPI_TxEmptyInterruptEnable
-
enum _flexio_spi_status_flags
Define FlexIO SPI status mask.
Values:
-
enumerator kFLEXIO_SPI_TxBufferEmptyFlag
Transmit buffer empty flag.
-
enumerator kFLEXIO_SPI_RxBufferFullFlag
Receive buffer full flag.
-
enumerator kFLEXIO_SPI_TxBufferEmptyFlag
-
enum _flexio_spi_dma_enable
Define FlexIO SPI DMA mask.
Values:
-
enumerator kFLEXIO_SPI_TxDmaEnable
Tx DMA request source
-
enumerator kFLEXIO_SPI_RxDmaEnable
Rx DMA request source
-
enumerator kFLEXIO_SPI_DmaAllEnable
All DMA request source
-
enumerator kFLEXIO_SPI_TxDmaEnable
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enum _flexio_spi_transfer_flags
Define FlexIO SPI transfer flags.
Note
Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.
Values:
-
enumerator kFLEXIO_SPI_8bitMsb
FlexIO SPI 8-bit MSB first
-
enumerator kFLEXIO_SPI_8bitLsb
FlexIO SPI 8-bit LSB first
-
enumerator kFLEXIO_SPI_16bitMsb
FlexIO SPI 16-bit MSB first
-
enumerator kFLEXIO_SPI_16bitLsb
FlexIO SPI 16-bit LSB first
-
enumerator kFLEXIO_SPI_32bitMsb
FlexIO SPI 32-bit MSB first
-
enumerator kFLEXIO_SPI_32bitLsb
FlexIO SPI 32-bit LSB first
-
enumerator kFLEXIO_SPI_csContinuous
Enable the CS signal continuous mode
-
enumerator kFLEXIO_SPI_8bitMsb
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typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t
FlexIO SPI clock phase configuration.
-
typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t
FlexIO SPI data shifter direction options.
-
typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t
FlexIO SPI data length mode options.
-
typedef struct _flexio_spi_type FLEXIO_SPI_Type
Define FlexIO SPI access structure typedef.
-
typedef struct _flexio_spi_master_config flexio_spi_master_config_t
Define FlexIO SPI master configuration structure.
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typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t
Define FlexIO SPI slave configuration structure.
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typedef struct _flexio_spi_transfer flexio_spi_transfer_t
Define FlexIO SPI transfer structure.
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typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t
typedef for flexio_spi_master_handle_t in advance.
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typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t
Slave handle is the same with master handle.
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typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData)
FlexIO SPI master callback for finished transmit.
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typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData)
FlexIO SPI slave callback for finished transmit.
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FLEXIO_SPI_DUMMYDATA
FlexIO SPI dummy transfer data, the data is sent while txData is NULL.
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SPI_RETRY_TIMES
Retry times for waiting flag.
-
FLEXIO_SPI_XFER_DATA_FORMAT(flag)
Get the transfer data format of width and bit order.
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struct _flexio_spi_type
- #include <fsl_flexio_spi.h>
Define FlexIO SPI access structure typedef.
Public Members
-
FLEXIO_Type *flexioBase
FlexIO base pointer.
-
uint8_t SDOPinIndex
Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.
-
uint8_t SDIPinIndex
Pin select for data input.
-
uint8_t SCKPinIndex
Pin select for clock.
-
uint8_t CSnPinIndex
Pin select for enable.
-
uint8_t shifterIndex[2]
Shifter index used in FlexIO SPI.
-
uint8_t timerIndex[2]
Timer index used in FlexIO SPI.
-
FLEXIO_Type *flexioBase
-
struct _flexio_spi_master_config
- #include <fsl_flexio_spi.h>
Define FlexIO SPI master configuration structure.
Public Members
-
bool enableMaster
Enable/disable FlexIO SPI master after configuration.
-
bool enableInDoze
Enable/disable FlexIO operation in doze mode.
-
bool enableInDebug
Enable/disable FlexIO operation in debug mode.
-
bool enableFastAccess
Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.
-
uint32_t baudRate_Bps
Baud rate in Bps.
-
flexio_spi_clock_phase_t phase
Clock phase.
-
flexio_spi_data_bitcount_mode_t dataMode
8bit or 16bit mode.
-
bool enableMaster
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struct _flexio_spi_slave_config
- #include <fsl_flexio_spi.h>
Define FlexIO SPI slave configuration structure.
Public Members
-
bool enableSlave
Enable/disable FlexIO SPI slave after configuration.
-
bool enableInDoze
Enable/disable FlexIO operation in doze mode.
-
bool enableInDebug
Enable/disable FlexIO operation in debug mode.
-
bool enableFastAccess
Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.
-
flexio_spi_clock_phase_t phase
Clock phase.
-
flexio_spi_data_bitcount_mode_t dataMode
8bit or 16bit mode.
-
bool enableSlave
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struct _flexio_spi_transfer
- #include <fsl_flexio_spi.h>
Define FlexIO SPI transfer structure.
Public Members
-
const uint8_t *txData
Send buffer.
-
uint8_t *rxData
Receive buffer.
-
size_t dataSize
Transfer bytes.
-
uint8_t flags
FlexIO SPI control flag, MSB first or LSB first.
-
const uint8_t *txData
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struct _flexio_spi_master_handle
- #include <fsl_flexio_spi.h>
Define FlexIO SPI handle structure.
Public Members
-
const uint8_t *txData
Transfer buffer.
-
uint8_t *rxData
Receive buffer.
-
size_t transferSize
Total bytes to be transferred.
-
volatile size_t txRemainingBytes
Send data remaining in bytes.
-
volatile size_t rxRemainingBytes
Receive data remaining in bytes.
-
volatile uint32_t state
FlexIO SPI internal state.
-
uint8_t bytePerFrame
SPI mode, 2bytes or 1byte in a frame
-
flexio_spi_shift_direction_t direction
Shift direction.
-
flexio_spi_master_transfer_callback_t callback
FlexIO SPI callback.
-
void *userData
Callback parameter.
-
const uint8_t *txData
FlexIO UART Driver
-
status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().
Example
FLEXIO_UART_Type base = { .flexioBase = FLEXIO, .TxPinIndex = 0, .RxPinIndex = 1, .shifterIndex = {0,1}, .timerIndex = {0,1} }; flexio_uart_config_t config = { .enableInDoze = false, .enableInDebug = true, .enableFastAccess = false, .baudRate_Bps = 115200U, .bitCountPerChar = 8 }; FLEXIO_UART_Init(base, &config, srcClock_Hz);
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
userConfig – Pointer to the flexio_uart_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.
- Return values:
kStatus_Success – Configuration success.
kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.
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void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
Resets the FlexIO UART shifter and timer config.
Note
After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
- Parameters:
base – Pointer to FLEXIO_UART_Type structure
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void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:
flexio_uart_config_t config; FLEXIO_UART_GetDefaultConfig(&userConfig);
- Parameters:
userConfig – Pointer to the flexio_uart_config_t structure.
-
uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
Gets the FlexIO UART status flags.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
- Returns:
FlexIO UART status flags.
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void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
Gets the FlexIO UART status flags.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
kFLEXIO_UART_TxDataRegEmptyFlag
kFLEXIO_UART_RxEmptyFlag
kFLEXIO_UART_RxOverRunFlag
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void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
Enables the FlexIO UART interrupt.
This function enables the FlexIO UART interrupt.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.
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void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
Disables the FlexIO UART interrupt.
This function disables the FlexIO UART interrupt.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.
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static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)
Gets the FlexIO UARt transmit data register address.
This function returns the UART data register address, which is mainly used by DMA/eDMA.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
- Returns:
FlexIO UART transmit data register address.
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static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)
Gets the FlexIO UART receive data register address.
This function returns the UART data register address, which is mainly used by DMA/eDMA.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
- Returns:
FlexIO UART receive data register address.
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static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)
Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.
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static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.
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static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)
Enables/disables the FlexIO UART module operation.
- Parameters:
base – Pointer to the FLEXIO_UART_Type.
enable – True to enable, false does not have any effect.
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static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)
Writes one byte of data.
Note
This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
buffer – The data bytes to send.
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static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)
Reads one byte of data.
Note
This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
buffer – The buffer to store the received bytes.
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status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
Sends a buffer of data bytes.
Note
This function blocks using the polling method until all bytes have been sent.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.
- Return values:
kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.
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status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
Receives a buffer of bytes.
Note
This function blocks using the polling method until all bytes have been received.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.
- Return values:
kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.
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status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)
Initializes the UART handle.
This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.
The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as
ringBuffer
.- Parameters:
base – to FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.
- Return values:
kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.
-
void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
Sets up the RX ring buffer.
This function sets up the RX ring buffer to a specific UART handle.
When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.
Note
When using the RX ring buffer, one byte is reserved for internal use. In other words, if
ringBufferSize
is 32, only 31 bytes are used for saving data.- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.
-
void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
Aborts the background transfer and uninstalls the ring buffer.
This function aborts the background transfer and uninstalls the ring buffer.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
-
status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)
Transmits a buffer of data using the interrupt method.
This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.
Note
The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.
- Return values:
kStatus_Success – Successfully starts the data transmission.
kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.
-
void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
Aborts the interrupt-driven data transmit.
This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
-
status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
Gets the number of bytes sent.
This function gets the number of bytes sent driven by interrupt.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.
- Return values:
kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.
-
status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)
Receives a buffer of data using the interrupt method.
This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter
receivedBytes
shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameterreceivedBytes
set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – UART transfer structure. See flexio_uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.
- Return values:
kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.
-
void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
Aborts the receive data which was using IRQ.
This function aborts the receive data which was using IRQ.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
-
status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
Gets the number of bytes received.
This function gets the number of bytes received driven by interrupt.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.
- Return values:
kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.
-
void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
FlexIO UART IRQ handler function.
This function processes the FlexIO UART transmit and receives the IRQ request.
- Parameters:
uartType – Pointer to the FLEXIO_UART_Type structure.
uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
-
void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)
Flush tx/rx shifters.
- Parameters:
base – Pointer to the FLEXIO_UART_Type structure.
-
FSL_FLEXIO_UART_DRIVER_VERSION
FlexIO UART driver version.
Error codes for the UART driver.
Values:
-
enumerator kStatus_FLEXIO_UART_TxBusy
Transmitter is busy.
-
enumerator kStatus_FLEXIO_UART_RxBusy
Receiver is busy.
-
enumerator kStatus_FLEXIO_UART_TxIdle
UART transmitter is idle.
-
enumerator kStatus_FLEXIO_UART_RxIdle
UART receiver is idle.
-
enumerator kStatus_FLEXIO_UART_ERROR
ERROR happens on UART.
-
enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun
UART RX software ring buffer overrun.
-
enumerator kStatus_FLEXIO_UART_RxHardwareOverrun
UART RX receiver overrun.
-
enumerator kStatus_FLEXIO_UART_Timeout
UART times out.
-
enumerator kStatus_FLEXIO_UART_BaudrateNotSupport
Baudrate is not supported in current clock source
-
enumerator kStatus_FLEXIO_UART_TxBusy
-
enum _flexio_uart_bit_count_per_char
FlexIO UART bit count per char.
Values:
-
enumerator kFLEXIO_UART_7BitsPerChar
7-bit data characters
-
enumerator kFLEXIO_UART_8BitsPerChar
8-bit data characters
-
enumerator kFLEXIO_UART_9BitsPerChar
9-bit data characters
-
enumerator kFLEXIO_UART_7BitsPerChar
-
enum _flexio_uart_interrupt_enable
Define FlexIO UART interrupt mask.
Values:
-
enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable
Transmit buffer empty interrupt enable.
-
enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable
Receive buffer full interrupt enable.
-
enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable
-
enum _flexio_uart_status_flags
Define FlexIO UART status mask.
Values:
-
enumerator kFLEXIO_UART_TxDataRegEmptyFlag
Transmit buffer empty flag.
-
enumerator kFLEXIO_UART_RxDataRegFullFlag
Receive buffer full flag.
-
enumerator kFLEXIO_UART_RxOverRunFlag
Receive buffer over run flag.
-
enumerator kFLEXIO_UART_TxDataRegEmptyFlag
-
typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t
FlexIO UART bit count per char.
-
typedef struct _flexio_uart_type FLEXIO_UART_Type
Define FlexIO UART access structure typedef.
-
typedef struct _flexio_uart_config flexio_uart_config_t
Define FlexIO UART user configuration structure.
-
typedef struct _flexio_uart_transfer flexio_uart_transfer_t
Define FlexIO UART transfer structure.
-
typedef struct _flexio_uart_handle flexio_uart_handle_t
-
typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData)
FlexIO UART transfer callback function.
-
UART_RETRY_TIMES
Retry times for waiting flag.
-
struct _flexio_uart_type
- #include <fsl_flexio_uart.h>
Define FlexIO UART access structure typedef.
Public Members
-
FLEXIO_Type *flexioBase
FlexIO base pointer.
-
uint8_t TxPinIndex
Pin select for UART_Tx.
-
uint8_t RxPinIndex
Pin select for UART_Rx.
-
uint8_t shifterIndex[2]
Shifter index used in FlexIO UART.
-
uint8_t timerIndex[2]
Timer index used in FlexIO UART.
-
FLEXIO_Type *flexioBase
-
struct _flexio_uart_config
- #include <fsl_flexio_uart.h>
Define FlexIO UART user configuration structure.
Public Members
-
bool enableUart
Enable/disable FlexIO UART TX & RX.
-
bool enableInDoze
Enable/disable FlexIO operation in doze mode
-
bool enableInDebug
Enable/disable FlexIO operation in debug mode
-
bool enableFastAccess
Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.
-
uint32_t baudRate_Bps
Baud rate in Bps.
-
flexio_uart_bit_count_per_char_t bitCountPerChar
number of bits, 7/8/9 -bit
-
bool enableUart
-
struct _flexio_uart_transfer
- #include <fsl_flexio_uart.h>
Define FlexIO UART transfer structure.
Public Members
-
size_t dataSize
Transfer size
-
size_t dataSize
-
struct _flexio_uart_handle
- #include <fsl_flexio_uart.h>
Define FLEXIO UART handle structure.
Public Members
-
const uint8_t *volatile txData
Address of remaining data to send.
-
volatile size_t txDataSize
Size of the remaining data to send.
-
uint8_t *volatile rxData
Address of remaining data to receive.
-
volatile size_t rxDataSize
Size of the remaining data to receive.
-
size_t txDataSizeAll
Total bytes to be sent.
-
size_t rxDataSizeAll
Total bytes to be received.
-
uint8_t *rxRingBuffer
Start address of the receiver ring buffer.
-
size_t rxRingBufferSize
Size of the ring buffer.
-
volatile uint16_t rxRingBufferHead
Index for the driver to store received data into ring buffer.
-
volatile uint16_t rxRingBufferTail
Index for the user to get data from the ring buffer.
-
flexio_uart_transfer_callback_t callback
Callback function.
-
void *userData
UART callback function parameter.
-
volatile uint8_t txState
TX transfer state.
-
volatile uint8_t rxState
RX transfer state
-
const uint8_t *volatile txData
-
union __unnamed263__
Public Members
-
uint8_t *data
The buffer of data to be transfer.
-
uint8_t *rxData
The buffer to receive data.
-
const uint8_t *txData
The buffer of data to be sent.
-
uint8_t *data
FLEXSPI: Flexible Serial Peripheral Interface Driver
-
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
Get the instance number for FLEXSPI.
- Parameters:
base – FLEXSPI base pointer.
-
status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
Check and clear IP command execution errors.
- Parameters:
base – FLEXSPI base pointer.
status – interrupt status.
-
void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
Initializes the FLEXSPI module and internal state.
This function enables the clock for FLEXSPI and also configures the FLEXSPI with the input configure parameters. Users should call this function before any FLEXSPI operations.
- Parameters:
base – FLEXSPI peripheral base address.
config – FLEXSPI configure structure.
-
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
Gets default settings for FLEXSPI.
- Parameters:
config – FLEXSPI configuration structure.
-
void FLEXSPI_Deinit(FLEXSPI_Type *base)
Deinitializes the FLEXSPI module.
Clears the FLEXSPI state and FLEXSPI module registers.
- Parameters:
base – FLEXSPI peripheral base address.
-
void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
Update FLEXSPI DLL value depending on currently flexspi root clock.
- Parameters:
base – FLEXSPI peripheral base address.
config – Flash configuration parameters.
port – FLEXSPI Operation port.
-
void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
Configures the connected device parameter.
This function configures the connected device relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the connected device.
- Parameters:
base – FLEXSPI peripheral base address.
config – Flash configuration parameters.
port – FLEXSPI Operation port.
-
void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
Software reset for the FLEXSPI logic.
This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.
- Parameters:
base – FLEXSPI peripheral base address.
-
static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
Enables or disables the FLEXSPI module.
- Parameters:
base – FLEXSPI peripheral base address.
enable – True means enable FLEXSPI, false means disable.
-
static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
Enables the FLEXSPI interrupts.
- Parameters:
base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.
-
static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
Disable the FLEXSPI interrupts.
- Parameters:
base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.
-
static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
Enables or disables FLEXSPI IP Tx FIFO DMA requests.
- Parameters:
base – FLEXSPI peripheral base address.
enable – Enable flag for transmit DMA request. Pass true for enable, false for disable.
-
static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
Enables or disables FLEXSPI IP Rx FIFO DMA requests.
- Parameters:
base – FLEXSPI peripheral base address.
enable – Enable flag for receive DMA request. Pass true for enable, false for disable.
-
static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
Gets FLEXSPI IP tx fifo address for DMA transfer.
- Parameters:
base – FLEXSPI peripheral base address.
- Return values:
The – tx fifo address.
-
static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
Gets FLEXSPI IP rx fifo address for DMA transfer.
- Parameters:
base – FLEXSPI peripheral base address.
- Return values:
The – rx fifo address.
-
static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
Clears the FLEXSPI IP FIFO logic.
- Parameters:
base – FLEXSPI peripheral base address.
txFifo – Pass true to reset TX FIFO.
rxFifo – Pass true to reset RX FIFO.
-
static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
Gets the valid data entries in the FLEXSPI FIFOs.
- Parameters:
base – FLEXSPI peripheral base address.
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.
-
static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
Get the FLEXSPI interrupt status flags.
- Parameters:
base – FLEXSPI peripheral base address.
- Return values:
interrupt – status flag, use status flag to AND flexspi_flags_t could get the related status.
-
static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
Get the FLEXSPI interrupt status flags.
- Parameters:
base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.
-
static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
Gets the trigger source of current command sequence granted by arbitrator.
- Parameters:
base – FLEXSPI peripheral base address.
- Return values:
trigger – source of current command sequence.
-
static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
Gets the error code when IP command error detected.
- Parameters:
base – FLEXSPI peripheral base address.
index – Pointer to a uint8_t type variable to receive the sequence index when error detected.
- Return values:
error – code when IP command error detected.
-
static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
Gets the error code when AHB command error detected.
- Parameters:
base – FLEXSPI peripheral base address.
index – Pointer to a uint8_t type variable to receive the sequence index when error detected.
- Return values:
error – code when AHB command error detected.
-
static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
Returns whether the bus is idle.
- Parameters:
base – FLEXSPI peripheral base address.
- Return values:
true – Bus is idle.
false – Bus is busy.
-
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)
Update read sample clock source.
- Parameters:
base – FLEXSPI peripheral base address.
clockSource – clockSource of type flexspi_read_sample_clock_t
-
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
Updates the LUT table.
- Parameters:
base – FLEXSPI peripheral base address.
index – From which index start to update. It could be any index of the LUT table, which also allows user to update command content inside a command. Each command consists of up to 8 instructions and occupy 4*32-bit memory.
cmd – Command sequence array.
count – Number of sequences.
-
static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
Writes data into FIFO.
- Parameters:
base – FLEXSPI peripheral base address
data – The data bytes to send
fifoIndex – Destination fifo index.
-
static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
Receives data from data FIFO.
- Parameters:
base – FLEXSPI peripheral base address
fifoIndex – Source fifo index.
- Returns:
The data in the FIFO.
-
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
Sends a buffer of data bytes using blocking method.
Note
This function blocks via polling until all bytes have been sent.
- Parameters:
base – FLEXSPI peripheral base address
buffer – The data bytes to send
size – The number of data bytes to send
- Return values:
kStatus_Success – write success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected
-
status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
Receives a buffer of data bytes using a blocking method.
Note
This function blocks via polling until all bytes have been sent.
- Parameters:
base – FLEXSPI peripheral base address
buffer – The data bytes to send
size – The number of data bytes to receive
- Return values:
kStatus_Success – read success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequencen error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected
-
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
Execute command to transfer a buffer data bytes using a blocking method.
- Parameters:
base – FLEXSPI peripheral base address
xfer – pointer to the transfer structure.
- Return values:
kStatus_Success – command transfer success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected
-
void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData)
Initializes the FLEXSPI handle which is used in transactional functions.
- Parameters:
base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure to store the transfer state.
callback – pointer to user callback function.
userData – user parameter passed to the callback function.
-
status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
Performs a interrupt non-blocking transfer on the FLEXSPI bus.
Note
Calling the API returns immediately after transfer initiates. The user needs to call FLEXSPI_GetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or FLEXSPI could not read data properly.
- Parameters:
base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state.
xfer – pointer to flexspi_transfer_t structure.
- Return values:
kStatus_Success – Successfully start the data transmission.
kStatus_FLEXSPI_Busy – Previous transmission still not finished.
-
status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
Gets the master transfer status during a interrupt non-blocking transfer.
- Parameters:
base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.
-
void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
Aborts an interrupt non-blocking transfer early.
Note
This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state
-
void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
Master interrupt handler.
- Parameters:
base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure.
-
FSL_FLEXSPI_DRIVER_VERSION
FLEXSPI driver version.
Status structure of FLEXSPI.
Values:
-
enumerator kStatus_FLEXSPI_Busy
FLEXSPI is busy
-
enumerator kStatus_FLEXSPI_SequenceExecutionTimeout
Sequence execution timeout error occurred during FLEXSPI transfer.
-
enumerator kStatus_FLEXSPI_IpCommandSequenceError
IP command Sequence execution timeout error occurred during FLEXSPI transfer.
-
enumerator kStatus_FLEXSPI_IpCommandGrantTimeout
IP command grant timeout error occurred during FLEXSPI transfer.
-
enumerator kStatus_FLEXSPI_Busy
CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command.
Values:
-
enumerator kFLEXSPI_Command_STOP
Stop execution, deassert CS.
-
enumerator kFLEXSPI_Command_SDR
Transmit Command code to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_RADDR_SDR
Transmit Row Address to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_CADDR_SDR
Transmit Column Address to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_MODE1_SDR
Transmit 1-bit Mode bits to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_MODE2_SDR
Transmit 2-bit Mode bits to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_MODE4_SDR
Transmit 4-bit Mode bits to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_MODE8_SDR
Transmit 8-bit Mode bits to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_WRITE_SDR
Transmit Programming Data to Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_READ_SDR
Receive Read Data from Flash, using SDR mode.
-
enumerator kFLEXSPI_Command_LEARN_SDR
Receive Read Data or Preamble bit from Flash, SDR mode.
-
enumerator kFLEXSPI_Command_DATSZ_SDR
Transmit Read/Program Data size (byte) to Flash, SDR mode.
-
enumerator kFLEXSPI_Command_DUMMY_SDR
Leave data lines undriven by FlexSPI controller.
-
enumerator kFLEXSPI_Command_DUMMY_RWDS_SDR
Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.
-
enumerator kFLEXSPI_Command_DDR
Transmit Command code to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_RADDR_DDR
Transmit Row Address to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_CADDR_DDR
Transmit Column Address to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_MODE1_DDR
Transmit 1-bit Mode bits to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_MODE2_DDR
Transmit 2-bit Mode bits to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_MODE4_DDR
Transmit 4-bit Mode bits to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_MODE8_DDR
Transmit 8-bit Mode bits to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_WRITE_DDR
Transmit Programming Data to Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_READ_DDR
Receive Read Data from Flash, using DDR mode.
-
enumerator kFLEXSPI_Command_LEARN_DDR
Receive Read Data or Preamble bit from Flash, DDR mode.
-
enumerator kFLEXSPI_Command_DATSZ_DDR
Transmit Read/Program Data size (byte) to Flash, DDR mode.
-
enumerator kFLEXSPI_Command_DUMMY_DDR
Leave data lines undriven by FlexSPI controller.
-
enumerator kFLEXSPI_Command_DUMMY_RWDS_DDR
Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.
-
enumerator kFLEXSPI_Command_JUMP_ON_CS
Stop execution, deassert CS and save operand[7:0] as the instruction start pointer for next sequence
-
enumerator kFLEXSPI_Command_STOP
-
enum _flexspi_pad
pad definition of FLEXSPI, use to form LUT instruction.
Values:
-
enumerator kFLEXSPI_1PAD
Transmit command/address and transmit/receive data only through DATA0/DATA1.
-
enumerator kFLEXSPI_2PAD
Transmit command/address and transmit/receive data only through DATA[1:0].
-
enumerator kFLEXSPI_4PAD
Transmit command/address and transmit/receive data only through DATA[3:0].
-
enumerator kFLEXSPI_8PAD
Transmit command/address and transmit/receive data only through DATA[7:0].
-
enumerator kFLEXSPI_1PAD
-
enum _flexspi_flags
FLEXSPI interrupt status flags.
Values:
-
enumerator kFLEXSPI_SequenceExecutionTimeoutFlag
Sequence execution timeout.
-
enumerator kFLEXSPI_AhbBusErrorFlag
AHB Bus error flag.
-
enumerator kFLEXSPI_SckStoppedBecauseTxEmptyFlag
SCK is stopped during command sequence because Async TX FIFO empty.
-
enumerator kFLEXSPI_SckStoppedBecauseRxFullFlag
SCK is stopped during command sequence because Async RX FIFO full.
-
enumerator kFLEXSPI_IpTxFifoWatermarkEmptyFlag
IP TX FIFO WaterMark empty.
-
enumerator kFLEXSPI_IpRxFifoWatermarkAvailableFlag
IP RX FIFO WaterMark available.
-
enumerator kFLEXSPI_AhbCommandSequenceErrorFlag
AHB triggered Command Sequences Error.
-
enumerator kFLEXSPI_IpCommandSequenceErrorFlag
IP triggered Command Sequences Error.
-
enumerator kFLEXSPI_AhbCommandGrantTimeoutFlag
AHB triggered Command Sequences Grant Timeout.
-
enumerator kFLEXSPI_IpCommandGrantTimeoutFlag
IP triggered Command Sequences Grant Timeout.
-
enumerator kFLEXSPI_IpCommandExecutionDoneFlag
IP triggered Command Sequences Execution finished.
-
enumerator kFLEXSPI_AllInterruptFlags
All flags.
-
enumerator kFLEXSPI_SequenceExecutionTimeoutFlag
-
enum _flexspi_read_sample_clock
FLEXSPI sample clock source selection for Flash Reading.
Values:
-
enumerator kFLEXSPI_ReadSampleClkLoopbackInternally
Dummy Read strobe generated by FlexSPI Controller and loopback internally.
-
enumerator kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
-
enumerator kFLEXSPI_ReadSampleClkLoopbackFromSckPad
SCK output clock and loopback from SCK pad.
-
enumerator kFLEXSPI_ReadSampleClkExternalInputFromDqsPad
Flash provided Read strobe and input from DQS pad.
-
enumerator kFLEXSPI_ReadSampleClkLoopbackInternally
-
enum _flexspi_cs_interval_cycle_unit
FLEXSPI interval unit for flash device select.
Values:
-
enumerator kFLEXSPI_CsIntervalUnit1SckCycle
Chip selection interval: CSINTERVAL * 1 serial clock cycle.
-
enumerator kFLEXSPI_CsIntervalUnit256SckCycle
Chip selection interval: CSINTERVAL * 256 serial clock cycle.
-
enumerator kFLEXSPI_CsIntervalUnit1SckCycle
-
enum _flexspi_ahb_write_wait_unit
FLEXSPI AHB wait interval unit for writing.
Values:
-
enumerator kFLEXSPI_AhbWriteWaitUnit2AhbCycle
AWRWAIT unit is 2 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit8AhbCycle
AWRWAIT unit is 8 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit32AhbCycle
AWRWAIT unit is 32 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit128AhbCycle
AWRWAIT unit is 128 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit512AhbCycle
AWRWAIT unit is 512 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit2048AhbCycle
AWRWAIT unit is 2048 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit8192AhbCycle
AWRWAIT unit is 8192 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit32768AhbCycle
AWRWAIT unit is 32768 ahb clock cycle.
-
enumerator kFLEXSPI_AhbWriteWaitUnit2AhbCycle
-
enum _flexspi_ip_error_code
Error Code when IP command Error detected.
Values:
-
enumerator kFLEXSPI_IpCmdErrorNoError
No error.
-
enumerator kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd
IP command with JMP_ON_CS instruction used.
-
enumerator kFLEXSPI_IpCmdErrorUnknownOpCode
Unknown instruction opcode in the sequence.
-
enumerator kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence
Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
-
enumerator kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence
Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
-
enumerator kFLEXSPI_IpCmdErrorInvalidAddress
Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
-
enumerator kFLEXSPI_IpCmdErrorSequenceExecutionTimeout
Sequence execution timeout.
-
enumerator kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss
Flash boundary crossed.
-
enumerator kFLEXSPI_IpCmdErrorNoError
-
enum _flexspi_ahb_error_code
Error Code when AHB command Error detected.
Values:
-
enumerator kFLEXSPI_AhbCmdErrorNoError
No error.
-
enumerator kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd
AHB Write command with JMP_ON_CS instruction used in the sequence.
-
enumerator kFLEXSPI_AhbCmdErrorUnknownOpCode
Unknown instruction opcode in the sequence.
-
enumerator kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence
Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
-
enumerator kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence
Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
-
enumerator kFLEXSPI_AhbCmdSequenceExecutionTimeout
Sequence execution timeout.
-
enumerator kFLEXSPI_AhbCmdErrorNoError
-
enum _flexspi_port
FLEXSPI operation port select.
Values:
-
enumerator kFLEXSPI_PortA1
Access flash on A1 port.
-
enumerator kFLEXSPI_PortA2
Access flash on A2 port.
-
enumerator kFLEXSPI_PortB1
Access flash on B1 port.
-
enumerator kFLEXSPI_PortB2
Access flash on B2 port.
-
enumerator kFLEXSPI_PortCount
-
enumerator kFLEXSPI_PortA1
-
enum _flexspi_arb_command_source
Trigger source of current command sequence granted by arbitrator.
Values:
-
enumerator kFLEXSPI_AhbReadCommand
-
enumerator kFLEXSPI_AhbWriteCommand
-
enumerator kFLEXSPI_IpCommand
-
enumerator kFLEXSPI_SuspendedCommand
-
enumerator kFLEXSPI_AhbReadCommand
-
enum _flexspi_command_type
Command type.
Values:
-
enumerator kFLEXSPI_Command
FlexSPI operation: Only command, both TX and Rx buffer are ignored.
-
enumerator kFLEXSPI_Config
FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT.
-
enumerator kFLEXSPI_Read
-
enumerator kFLEXSPI_Write
-
enumerator kFLEXSPI_Command
-
typedef enum _flexspi_pad flexspi_pad_t
pad definition of FLEXSPI, use to form LUT instruction.
-
typedef enum _flexspi_flags flexspi_flags_t
FLEXSPI interrupt status flags.
-
typedef enum _flexspi_read_sample_clock flexspi_read_sample_clock_t
FLEXSPI sample clock source selection for Flash Reading.
-
typedef enum _flexspi_cs_interval_cycle_unit flexspi_cs_interval_cycle_unit_t
FLEXSPI interval unit for flash device select.
-
typedef enum _flexspi_ahb_write_wait_unit flexspi_ahb_write_wait_unit_t
FLEXSPI AHB wait interval unit for writing.
-
typedef enum _flexspi_ip_error_code flexspi_ip_error_code_t
Error Code when IP command Error detected.
-
typedef enum _flexspi_ahb_error_code flexspi_ahb_error_code_t
Error Code when AHB command Error detected.
-
typedef enum _flexspi_port flexspi_port_t
FLEXSPI operation port select.
-
typedef enum _flexspi_arb_command_source flexspi_arb_command_source_t
Trigger source of current command sequence granted by arbitrator.
-
typedef enum _flexspi_command_type flexspi_command_type_t
Command type.
-
typedef struct _flexspi_ahbBuffer_config flexspi_ahbBuffer_config_t
-
typedef struct _flexspi_config flexspi_config_t
FLEXSPI configuration structure.
-
typedef struct _flexspi_device_config flexspi_device_config_t
External device configuration items.
-
typedef struct _flexspi_transfer flexspi_transfer_t
Transfer structure for FLEXSPI.
-
typedef struct _flexspi_handle flexspi_handle_t
-
typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, flexspi_handle_t *handle, status_t status, void *userData)
FLEXSPI transfer callback function.
-
FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT
-
FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
Formula to form FLEXSPI instructions in LUT table.
-
struct _flexspi_ahbBuffer_config
- #include <fsl_flexspi.h>
Public Members
-
uint8_t priority
This priority for AHB Master Read which this AHB RX Buffer is assigned.
-
uint8_t masterIndex
AHB Master ID the AHB RX Buffer is assigned.
-
uint16_t bufferSize
AHB buffer size in byte.
-
bool enablePrefetch
AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows prefetch disable/enable separately for each master.
-
uint8_t priority
-
struct _flexspi_config
- #include <fsl_flexspi.h>
FLEXSPI configuration structure.
Public Members
-
flexspi_read_sample_clock_t rxSampleClock
Sample Clock source selection for Flash Reading.
-
bool enableSckFreeRunning
Enable/disable SCK output free-running.
-
bool enableDoze
Enable/disable doze mode support.
-
bool enableHalfSpeedAccess
Enable/disable divide by 2 of the clock for half speed commands.
-
bool enableSameConfigForAll
Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all.
-
uint16_t seqTimeoutCycle
Timeout wait cycle for command sequence execution, timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles.
-
uint8_t ipGrantTimeoutCycle
Timeout wait cycle for IP command grant, timeout after ipGrantTimeoutCycle*1024 AHB clock cycles.
-
uint8_t txWatermark
FLEXSPI IP transmit watermark value.
-
uint8_t rxWatermark
FLEXSPI receive watermark value.
-
flexspi_read_sample_clock_t rxSampleClock
-
struct _flexspi_device_config
- #include <fsl_flexspi.h>
External device configuration items.
Public Members
-
uint32_t flexspiRootClk
FLEXSPI serial root clock.
-
bool isSck2Enabled
FLEXSPI use SCK2.
-
uint32_t flashSize
Flash size in KByte.
-
bool addressShift
Address shift.
-
flexspi_cs_interval_cycle_unit_t CSIntervalUnit
CS interval unit, 1 or 256 cycle.
-
uint16_t CSInterval
CS line assert interval, multiply CS interval unit to get the CS line assert interval cycles.
-
uint8_t CSHoldTime
CS line hold time.
-
uint8_t CSSetupTime
CS line setup time.
-
uint8_t dataValidTime
Data valid time for external device.
-
uint8_t columnspace
Column space size.
-
bool enableWordAddress
If enable word address.
-
uint8_t AWRSeqIndex
Sequence ID for AHB write command.
-
uint8_t AWRSeqNumber
Sequence number for AHB write command.
-
uint8_t ARDSeqIndex
Sequence ID for AHB read command.
-
uint8_t ARDSeqNumber
Sequence number for AHB read command.
-
flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit
AHB write wait unit.
-
uint16_t AHBWriteWaitInterval
AHB write wait interval, multiply AHB write interval unit to get the AHB write wait cycles.
-
bool enableWriteMask
Enable/Disable FLEXSPI drive DQS pin as write mask when writing to external device.
-
uint32_t flexspiRootClk
-
struct _flexspi_transfer
- #include <fsl_flexspi.h>
Transfer structure for FLEXSPI.
Public Members
-
uint32_t deviceAddress
Operation device address.
-
flexspi_port_t port
Operation port.
-
flexspi_command_type_t cmdType
Execution command type.
-
uint8_t seqIndex
Sequence ID for command.
-
uint8_t SeqNumber
Sequence number for command.
-
uint32_t *data
Data buffer.
-
size_t dataSize
Data size in bytes.
-
uint32_t deviceAddress
-
struct _flexspi_handle
- #include <fsl_flexspi.h>
Transfer handle structure for FLEXSPI.
Public Members
-
uint32_t state
Internal state for FLEXSPI transfer
-
uint8_t *data
Data buffer.
-
size_t dataSize
Remaining Data size in bytes.
-
size_t transferTotalSize
Total Data size in bytes.
-
flexspi_transfer_callback_t completionCallback
Callback for users while transfer finish or error occurred
-
void *userData
FLEXSPI callback function parameter.
-
uint32_t state
-
struct ahbConfig
Public Members
-
uint8_t ahbGrantTimeoutCycle
Timeout wait cycle for AHB command grant, timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles.
-
uint16_t ahbBusTimeoutCycle
Timeout wait cycle for AHB read/write access, timeout after ahbBusTimeoutCycle*1024 AHB clock cycles.
-
uint8_t resumeWaitCycle
Wait cycle for idle state before suspended command sequence resume, timeout after ahbBusTimeoutCycle AHB clock cycles.
-
flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]
AHB buffer size.
-
bool enableClearAHBBufferOpt
Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK.
-
bool enableReadAddressOpt
Enable/disable remove AHB read burst start address alignment limitation. when enable, there is no AHB read burst start address alignment limitation.
-
bool enableAHBPrefetch
Enable/disable AHB read prefetch feature, when enabled, FLEXSPI will fetch more data than current AHB burst.
-
bool enableAHBBufferable
Enable/disable AHB bufferable write access support, when enabled, FLEXSPI return before waiting for command execution finished.
-
bool enableAHBCachable
Enable AHB bus cachable read access support.
-
uint8_t ahbGrantTimeoutCycle
FLEXSPI eDMA Driver
-
void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)
Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.
- Parameters:
base – FLEXSPI peripheral base address
handle – Pointer to flexspi_edma_handle_t structure
callback – FLEXSPI callback, NULL means no callback.
userData – User callback function data.
txDmaHandle – User requested DMA handle for TX DMA transfer.
rxDmaHandle – User requested DMA handle for RX DMA transfer.
-
void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_transfer_nsize_t nsize)
Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).
See also
flexspi_edma_transfer_nsize_t .
- Parameters:
base – FLEXSPI peripheral base address
handle – Pointer to flexspi_edma_handle_t structure
nsize – FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is kFLEXPSI_EDMAnSize1Bytes(one byte).
-
status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_transfer_t *xfer)
Transfers FLEXSPI data using an eDMA non-blocking method.
This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking.
- Parameters:
base – FLEXSPI peripheral base address.
handle – Pointer to flexspi_edma_handle_t structure
xfer – FLEXSPI transfer structure.
- Return values:
kStatus_FLEXSPI_Busy – FLEXSPI is busy transfer.
kStatus_InvalidArgument – The watermark configuration is invalid, the watermark should be power of 2 to do successfully EDMA transfer.
kStatus_Success – FLEXSPI successfully start edma transfer.
-
void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle)
Aborts the transfer data using eDMA.
This function aborts the transfer data using eDMA.
- Parameters:
base – FLEXSPI peripheral base address.
handle – Pointer to flexspi_edma_handle_t structure
-
status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count)
Gets the transferred counts of transfer.
- Parameters:
base – FLEXSPI peripheral base address.
handle – Pointer to flexspi_edma_handle_t structure.
count – Bytes transfer.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
FSL_FLEXSPI_EDMA_DRIVER_VERSION
FLEXSPI EDMA driver version.
FLEXSPI EDMA driver.
-
FSL_FLEXSPI_EDMA_DRIVER_VERSION
FLEXSPI EDMA driver.
-
enum _flexspi_edma_ntransfer_size
eDMA transfer configuration
Values:
-
enumerator kFLEXPSI_EDMAnSize1Bytes
Source/Destination data transfer size is 1 byte every time
-
enumerator kFLEXPSI_EDMAnSize2Bytes
Source/Destination data transfer size is 2 bytes every time
-
enumerator kFLEXPSI_EDMAnSize4Bytes
Source/Destination data transfer size is 4 bytes every time
-
enumerator kFLEXPSI_EDMAnSize8Bytes
Source/Destination data transfer size is 8 bytes every time
-
enumerator kFLEXPSI_EDMAnSize32Bytes
Source/Destination data transfer size is 32 bytes every time
-
enumerator kFLEXPSI_EDMAnSize1Bytes
-
enum _flexspi_edma_ntransfer_size
eDMA transfer configuration
Values:
-
enumerator kFLEXPSI_EDMAnSize1Bytes
Source/Destination data transfer size is 1 byte every time
-
enumerator kFLEXPSI_EDMAnSize2Bytes
Source/Destination data transfer size is 2 bytes every time
-
enumerator kFLEXPSI_EDMAnSize4Bytes
Source/Destination data transfer size is 4 bytes every time
-
enumerator kFLEXPSI_EDMAnSize8Bytes
Source/Destination data transfer size is 8 bytes every time
-
enumerator kFLEXPSI_EDMAnSize32Bytes
Source/Destination data transfer size is 32 bytes every time
-
enumerator kFLEXPSI_EDMAnSize1Bytes
-
typedef struct _flexspi_edma_handle flexspi_edma_handle_t
-
typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)
FLEXSPI eDMA transfer callback function for finish and error.
-
typedef enum _flexspi_edma_ntransfer_size flexspi_edma_transfer_nsize_t
eDMA transfer configuration
-
typedef struct _flexspi_edma_handle flexspi_edma_handle_t
-
typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)
FLEXSPI eDMA transfer callback function for finish and error.
-
typedef enum _flexspi_edma_ntransfer_size flexspi_edma_transfer_nsize_t
eDMA transfer configuration
-
struct _flexspi_edma_handle
- #include <fsl_flexspi_edma.h>
FLEXSPI DMA transfer handle, users should not touch the content of the handle.
Public Members
-
edma_handle_t *txDmaHandle
eDMA handler for FLEXSPI Tx.
-
edma_handle_t *rxDmaHandle
eDMA handler for FLEXSPI Rx.
-
size_t transferSize
Bytes need to transfer.
-
flexspi_edma_transfer_nsize_t nsize
eDMA SSIZE/DSIZE in each transfer.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
uint8_t count
The transfer data count in a DMA request.
-
uint32_t state
Internal state for FLEXSPI eDMA transfer.
-
flexspi_edma_callback_t completionCallback
A callback function called after the eDMA transfer is finished.
-
void *userData
User callback parameter
-
edma_handle_t *txDmaHandle
FLEXSPI_FLR: Flexible Serial Peripheral Interface Follower Driver
IO mode enumeration of FLEXSPI FOLLOWER.
Values:
-
enumerator kFLEXSPI_SLV_IOMODE_SDRx4
-
enumerator kFLEXSPI_SLV_IOMODE_SDRx8
-
enumerator kFLEXSPI_SLV_IOMODE_DDRx4
-
enumerator kFLEXSPI_SLV_IOMODE_DDRx8
-
enumerator kFLEXSPI_SLV_IOMODE_SDRx4
Clock frequency enumeration of FLEXSPI FOLLOWER.
Values:
-
enumerator RootClock_50M
-
enumerator RootClock_66M
-
enumerator RootClock_80M
-
enumerator RootClock_100M
-
enumerator RootClock_133M
-
enumerator RootClock_166M
-
enumerator RootClock_200M
-
enumerator RootClock_400M
-
enumerator RootClock_50M
The read fetch size enumeration of FLEXSPI FOLLOWER.
Values:
-
enumerator Read_Fetch_256Bytes
-
enumerator Read_Fetch_512Bytes
-
enumerator Read_Fetch_1KBytes
-
enumerator Read_Fetch_2KBytes
-
enumerator Read_Fetch_256Bytes
Clock frequency enumeration of FLEXSPI FOLLOWER.
Values:
-
enumerator Write_Watermark_32Bytes
-
enumerator Write_Watermark_64Bytes
-
enumerator Write_Watermark_128Bytes
-
enumerator Write_Watermark_256Bytes
-
enumerator Write_Watermark_32Bytes
Interrupt status flags of FLEXSPI FOLLOWER.
Values:
-
enumerator kFLEXSPI_SLV_Mail0InterruptFlag
Mailbox0 interrupt
-
enumerator kFLEXSPI_SLV_Mail1InterruptFlag
Mailbox1 interrupt
-
enumerator kFLEXSPI_SLV_Mail2InterruptFlag
Mailbox2 interrupt
-
enumerator kFLEXSPI_SLV_Mail3InterruptFlag
Mailbox3 interrupt
-
enumerator kFLEXSPI_SLV_Mail4InterruptFlag
Mailbox4 interrupt
-
enumerator kFLEXSPI_SLV_Mail5InterruptFlag
Mailbox5 interrupt
-
enumerator kFLEXSPI_SLV_Mail6InterruptFlag
Mailbox6 interrupt
-
enumerator kFLEXSPI_SLV_Mail7InterruptFlag
Mailbox7 interrupt
-
enumerator kFLEXSPI_SLV_Mail8InterruptFlag
Mailbox8 interrupt
-
enumerator kFLEXSPI_SLV_WriteOverflowFlag
An IO RX FIFO overflow occurred during command/address/write data phase
-
enumerator kFLEXSPI_SLV_ReadUnderflowFlag
IO TX FIFO underflow has occurred during a read command
-
enumerator kFLEXSPI_SLV_ErrorCommandFlag
An unknown command has been received from the SPI bus
-
enumerator kFLEXSPI_SLV_InvalidInterruptFlag
-
enumerator kFLEXSPI_SLV_Mail0InterruptFlag
-
typedef struct _flexspi_slv_config flexspi_slv_config_t
FLEXSPI FOLLOWER configuration structure.
-
typedef struct _flexspi_slv_handle flexspi_slv_handle_t
-
typedef void (*flexspi_slv_interrupt_callback_t)(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle)
FLEXSPI FOLLOWER interrupt callback function.
-
FSL_FLEXSPI_SLV_DRIVER_VERSION
FLEXSPI FOLLOWER driver version.
-
FSL_FEATURE_FLEXSPI_SLV_AXI_RX_BUFFER_SIZE
-
FSL_FEATURE_FLEXSPI_SLV_AXI_TX_BUFFER_SIZE
-
FLEXSPI_SLV_MAILBOX_CMD(x)
-
FLEXSPI_SLV_MAILBOX_CMD_INT(x)
-
FLEXSPI_SLV_CMD_DDR(x)
-
uint32_t FLEXSPI_SLV_GetInstance(FLEXSPI_SLV_Type *base)
Get the instance number for FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER base pointer.
-
uint32_t FLEXSPI_SLV_CheckAndClearInterrupt(FLEXSPI_SLV_Type *base)
Check and clear interrupt flags.
- Parameters:
base – FLEXSPI FOLLOWER base pointer.
- Returns:
Interrupt flag.
-
void FLEXSPI_SLV_Init(FLEXSPI_SLV_Type *base, const flexspi_slv_config_t *config)
Initializes the FLEXSPI FOLLOWER module and internal state.
This function enables the clock for FLEXSPI FOLLOWER and also configures the FLEXSPI FOLLOWER with the input configure parameters. Users should call this function before any FLEXSPI FOLLOWER operations.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
config – FLEXSPI FOLLOWER configure structure.
-
void FLEXSPI_SLV_GetDefaultConfig(flexspi_slv_config_t *config)
Gets default settings for FLEXSPI FOLLOWER.
- Parameters:
config – FLEXSPI FOLLOWER configuration structure.
-
void FLEXSPI_SLV_Deinit(FLEXSPI_SLV_Type *base)
Deinitializes the FLEXSPI FOLLOWER module.
Clears the FLEXSPI FOLLOWER state and FLEXSPI FOLLOWER module registers.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
-
static inline void FLEXSPI_SLV_SoftwareReset_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Software reset for the FLEXSPI FOLLOWER logic.
This function sets the software reset flags for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – 0(Finished) or 1(Initiate)
-
static inline void FLEXSPI_SLV_IOMode_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set IO mode for the FLEXSPI FOLLOWER module.
This function sets the IO mode flags for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – Set IO Mode for FLEXSPI FOLLOWER
-
static inline void FLEXSPI_SLV_Update_RWCMD_Base_Range(FLEXSPI_SLV_Type *base)
Update RW CMD base address and range value for the FLEXSPI FOLLOWER module.
This function updates RW CMD base address and range value for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
-
static inline void FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set RW command base address1 for the FLEXSPI FOLLOWER module.
This function sets the RW command base address1 for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – The high 16-bit base address of the RW command
-
static inline void FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set RW command base address2 for the FLEXSPI FOLLOWER module.
This function sets the RW command base address2 for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – The high 16-bit base address of the RW command
-
static inline void FLEXSPI_SLV_AddrRange_SetVal(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val)
Set address1/2 range for the FLEXSPI FOLLOWER module.
This function sets the address1/2 range for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
i – The index of RW command, 0 or 1.
val – The size of the memory range in 1KB units.
-
static inline void FLEXSPI_SLV_Read_WMEN_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Enable or disable read water mark for the FLEXSPI FOLLOWER module.
This function enables or disables read water mark for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – 0(Disable) or 1(Enable)
-
static inline void FLEXSPI_SLV_Read_RDWM_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set read water mark level for the FLEXSPI FOLLOWER module.
This function sets read water mark level for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – Read watermark level in bytes
-
static inline void FLEXSPI_SLV_Read_FetchSizeSet(FLEXSPI_SLV_Type *base, uint32_t val)
Sets the maximum read size triggered by a single read command.
This function sets the maximum read size for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – The maximum read size
-
static inline uint32_t FLEXSPI_SLV_Read_FetchSizeGet(FLEXSPI_SLV_Type *base)
Gets the maximum read size triggered by a single read command.
This function gets the maximum read size for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Returns:
The maximum read size
-
static inline void FLEXSPI_SLV_Write_WRWM_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set write water mark level for the FLEXSPI FOLLOWER module.
This function sets write water mark level for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – Write watermark level
-
static inline void FLEXSPI_SLV_CSMASK_SetVal(FLEXSPI_SLV_Type *base, uint32_t val)
Set CS mask value for the FLEXSPI FOLLOWER module.
This function sets CS mask value for the FLEXSPI FOLLOWER.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
val – 0(Not masked) or 1(Masked)
-
static inline void FLEXSPI_SLV_EnableInterrupts(FLEXSPI_SLV_Type *base, uint32_t mask)
Enables the FLEXSPI FOLLOWER interrupts.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
mask – FLEXSPI FOLLOWER interrupt source.
-
static inline void FLEXSPI_SLV_DisableInterrupts(FLEXSPI_SLV_Type *base, uint32_t mask)
Disable the FLEXSPI FOLLOWER interrupts.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
mask – FLEXSPI FOLLOWER interrupt source.
-
static inline uint32_t FLEXSPI_SLV_GetEnabledInterrupts(FLEXSPI_SLV_Type *base)
Get the FLEXSPI FOLLOWER enabled interrupts.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
-
static inline void FLEXSPI_SLV_EnableMailInterrupt(FLEXSPI_SLV_Type *base, bool enable)
Enable the FLEXSPI FOLLOWER mailbox interrupts.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
enable – Whether enable the mailbox interrupt.
-
static inline bool FLEXSPI_SLV_GetEnabledMailInterrupt(FLEXSPI_SLV_Type *base)
Return whether the FLEXSPI FOLLOWER enables the mailbox interrupt.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
-
static inline void FLEXSPI_SLV_GetOutOfRangeCounts(FLEXSPI_SLV_Type *base, size_t *rdCount, size_t *wrCount)
Gets the SPI leader read/write out-of-allowed-range count.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
rdCount – [out] Pointer through which the current number in the read out-of-allowed-range counter is returned. Pass NULL if this value is not required.
wrCount – [out] Pointer through which the current number in the write out-of-allowed-range counter is returned Pass NULL if this value is not required.
-
static inline uint32_t FLEXSPI_SLV_GetInterruptStatusFlags(FLEXSPI_SLV_Type *base)
Get the FLEXSPI FOLLOWER interrupt status flags.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
Interrupt – status flag, use status flag to AND the bit mask could get the related status.
-
static inline uint32_t FLEXSPI_SLV_GetMailInterruptIndex(FLEXSPI_SLV_Type *base)
Get the FLEXSPI FOLLOWER mailbox interrupt register.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Returns:
Return the index of the FLEXSPI FOLLOWER mail interrupt register
-
static inline uint32_t FLEXSPI_SLV_GetMailboxData(FLEXSPI_SLV_Type *base, uint32_t index)
Get the FLEXSPI FOLLOWER mailbox data.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
index – The index of the mail interrupt register
- Returns:
Return the FLEXSPI FOLLOWER mailbox data
-
static inline void FLEXSPI_SLV_ClearInterruptStatusFlags(FLEXSPI_SLV_Type *base, uint32_t mask)
Clear the FLEXSPI FOLLOWER interrupt status flags.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
mask – FLEXSPI FOLLOWER interrupt source.
-
static inline void FLEXSPI_SLV_ClearMailInterruptFlag(FLEXSPI_SLV_Type *base)
Clear the FLEXSPI FOLLOWER mailbox interrupt flag.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
-
static inline bool FLEXSPI_SLV_GetAXIWriteBusyStatus(FLEXSPI_SLV_Type *base)
Returns whether the current AXI write leader is busy with a write command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
true – The current AXI write leader is busy.
false – The current AXI write leader is not busy.
-
static inline bool FLEXSPI_SLV_GetAXIReadIdleStatus(FLEXSPI_SLV_Type *base)
Returns whether the AXI read leader is busy with a read request or else idle with no pending AXI read request.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
true – The current AXI read leader is idle.
false – The current AXI read leader is busy.
-
static inline bool FLEXSPI_SLV_GetRegReadWriteIdleStatus(FLEXSPI_SLV_Type *base)
Returns whether the SPI to read/write register queue is idle.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
true – The SPI to read/write register queue is idle.
false – The SPI to read/write register queue is busy.
-
static inline bool FLEXSPI_SLV_GetSEQIdleStatus(FLEXSPI_SLV_Type *base)
Returns whether the SEQ control logic is idle or else busy with an ongoing SPI request.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
true – The SEQ control logic is idle.
false – The SEQ control logic is busy.
-
static inline bool FLEXSPI_SLV_GetModuleBusyStatus(FLEXSPI_SLV_Type *base)
Returns whether the FLEXSPI FOLLOWER module is busy.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
- Return values:
true – The SEQ control logic is busy.
false – The SEQ control logic is idle.
-
static inline void FLEXSPI_SLV_Read_CommandSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val)
Sets the read memory command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
i – The read command setting register index
val – The read command value.
-
static inline uint32_t FLEXSPI_SLV_Read_CommandGet(FLEXSPI_SLV_Type *base, uint32_t i)
Gets the read memory command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
i – The read command setting register index
-
static inline void FLEXSPI_SLV_Read_Command_DummyCyclesSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val)
Sets the dummy cycle for the read memory command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
i – The read command dummy cycle setting register index
val – The dummy cycle value of the read command.
-
static inline uint32_t FLEXSPI_SLV_Read_Command_DummyCyclesGet(FLEXSPI_SLV_Type *base, uint32_t i)
Gets the dummy cycle for the read memory command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
i – The read command dummy cycle setting register index
-
static inline void FLEXSPI_SLV_Write_CommandSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val)
Sets the write memory command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
i – The write command setting register index
val – The write command value.
-
static inline void FLEXSPI_SLV_Read_Register_CommandSet(FLEXSPI_SLV_Type *base, uint32_t val)
Sets the read register command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
val – The read register command value.
-
static inline void FLEXSPI_SLV_Read_Register_Command_DummyCyclesSet(FLEXSPI_SLV_Type *base, uint32_t val)
Sets the dummy cycle for the read register command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
val – The dummy cycle value of the read register command.
-
static inline void FLEXSPI_SLV_Write_Register_CommandSet(FLEXSPI_SLV_Type *base, uint32_t val)
Sets the write register command.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address
val – The write register command value.
-
void FLEXSPI_SLV_InterruptCreateHandle(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle, flexspi_slv_interrupt_callback_t callback, void *userData)
Initializes the FLEXSPI FOLLOWER handle which is used in transactional functions.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
handle – Pointer to flexspi_slv_handle_t structure to store the interrupt state.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
-
void FLEXSPI_SLV_HandleIRQ(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle)
Master interrupt handler.
- Parameters:
base – FLEXSPI FOLLOWER peripheral base address.
handle – Pointer to flexspi_slv_handle_t structure.
-
int clock_freq
-
uint32_t baseAddr1
Read/Write CMD1 Base Address.
-
uint32_t baseAddr2
Read/Write CMD2 Base Address.
-
uint32_t addrRange1
Read/Write CMD1 Addr Range.
-
uint32_t addrRange2
Read/Write CMD2 Addr Range.
-
uint8_t io_mode
IO mode control - SDRx4, SDRx8, DDRx4, DDRx8
-
uint8_t rxFetch_size
Specifies the maximum read size triggered by a single read command.
-
uint8_t rxWatermark
Triggers a new AXI read to fetch more data through the IP AXI header.
-
uint8_t txWatermark
Specifies the watermark value. During the write command, if pending write data equals or exceeds the watermark level, it triggers a new AXI write.
-
uint32_t state
Interrupt state for FLEXSPI FOLLOWER
-
flexspi_slv_interrupt_callback_t callback
Callback for users while mailbox received or error occurred
-
void *userData
FLEXSPI FOLLOWER callback function parameter.
-
struct _flexspi_slv_config
- #include <fsl_flexspi_flr.h>
FLEXSPI FOLLOWER configuration structure.
-
struct _flexspi_slv_handle
- #include <fsl_flexspi_flr.h>
Interrupt handle structure for FLEXSPI FOLLOWER.
Gpc
-
void GPC_AssignCpuDomain(gpc_cpu_slice_t cpu, uint32_t domainMap)
-
static inline void GPC_CM_EnableCpuSleepHold(gpc_cpu_slice_t slice, bool enable)
-
static inline void GPC_CM_SetNextCpuMode(gpc_cpu_slice_t slice, gpc_cpu_mode_t mode)
Set the CPU mode on the next sleep event.
This function configures the CPU mode that the CPU core will transmit to on next sleep event.
Note
This API must be called each time before entering sleep.
- Parameters:
slice – GPC CPU slice number.
mode – The CPU mode that the core will transmit to, refer to “gpc_cpu_mode_t”.
-
static inline gpc_cpu_mode_t GPC_CM_GetCurrentCpuMode(gpc_cpu_slice_t slice)
Get current CPU mode.
- Parameters:
slice – GPC CPU slice number.
- Returns:
The current CPU mode, in type of gpc_cpu_mode_t.
-
static inline gpc_cpu_mode_t GPC_CM_GetPreviousCpuMode(gpc_cpu_slice_t slice)
Get previous CPU mode.
- Parameters:
slice – GPC CPU slice number.
- Returns:
The previous CPU mode, in type of gpc_cpu_mode_t.
-
void GPC_CM_EnableIrqWakeup(gpc_cpu_slice_t slice, uint32_t irqId, bool enable)
Enable IRQ wakeup request.
This function enables the IRQ request which can wakeup the CPU platform.
- Parameters:
slice – GPC CPU slice number.
irqId – ID of the IRQ, accessible range is 0-255.
enable – Enable the IRQ request or not.
-
static inline void GPC_CM_EnableNonIrqWakeup(gpc_cpu_slice_t slice, uint32_t mask, bool enable)
Enable Non-IRQ wakeup request.
This function enables the non-IRQ request which can wakeup the CPU platform.
- Parameters:
slice – GPC CPU slice number.
mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.
enable – Enable the Non-IRQ request or not.
-
bool GPC_CM_GetIrqWakeupStatus(gpc_cpu_slice_t slice, uint32_t irqId)
Get the status of the IRQ wakeup request.
- Parameters:
slice – GPC CPU slice number.
irqId – ID of the IRQ, accessible range is 0-255.
- Returns:
Indicate the IRQ request is asserted or not.
-
static inline bool GPC_CM_GetNonIrqWakeupStatus(gpc_cpu_slice_t slice, uint32_t mask)
Get the status of the Non-IRQ wakeup request.
- Parameters:
slice – GPC CPU slice number.
mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.
- Returns:
Indicate the Non-IRQ request is asserted or not.
-
void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable)
brief Config the cpu mode transition step.
param slice GPC CPU slice number. param step step type, refer to “gpc_cm_tran_step_t”. param enable Used to control the transition step.
true This step is enabled.
false This step is disabled, GPC will skip this step and not send any request.
-
void GPC_CM_RequestSystemSleepMode(gpc_cpu_slice_t slice, const gpc_cpu_mode_t mode)
Request the chip into system sleep mode.
- Parameters:
slice – GPC CPU slice number.
mode – CPU mode. Refer to “gpc_cpu_mode_t”.
-
void GPC_CM_ClearSystemSleepModeRequest(gpc_cpu_slice_t slice, const gpc_cpu_mode_t mode)
Clear the system sleep mode request.
- Parameters:
slice – GPC CPU slice number.
mode – CPU mode. Refer to “gpc_cpu_mode_t”.
-
static inline bool GPC_CM_GetSystemSleepModeStatus(gpc_cpu_slice_t slice, uint32_t mask)
Get the status of the CPU system sleep mode transition.
- Parameters:
slice – GPC CPU slice number.
mask – System sleep mode transition status mask, refer to “gpc_cm_system sleep_mode_status_t”.
- Returns:
Indicate the CPU’s system sleep transition status.
-
void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step, bool enable)
brief Config the system sleep transition step.
param base GPC system sleep controller base address. param step step type, refer to “gpc_ss_tran_step_t”. param enable Used to control the transition step.
true This step is enabled.
false This step is disabled, GPC will skip this step and not send any request.
-
static inline void GPC_SS_SoftwareTriggerPMICStandby(GPC_SYS_SLEEP_CTRL_Type *base, bool enable)
Trigger PMIC standby ON/OFF by software.
- Parameters:
base – PMIC module base address.
enable – Trigger on/off PMIC standby.
true Trigger PMIC standby ON.
false Trigger PMIC standby OFF.
-
static inline void GPC_SS_SystemSleepTriggerPMICStandby(GPC_SYS_SLEEP_CTRL_Type *base, bool enable)
brief Assert the PMIC standby request when system sleep.
- Parameters:
base – PMIC module base address.
enable – Assert PMIC standby request or not.
true Assert PMIC_STBY_REQ when system sleep is entered.
false Do not assert PMIC_STBY_REQ when system sleep is entered.
-
FSL_GPC_RIVER_VERSION
GPC driver version 2.1.0.
_gpc_cm_non_irq_wakeup_request GPC Non-IRQ wakeup request.
Values:
-
enumerator kGPC_CM_DebugWakeupRequest
Debug wakeup request.
-
enumerator kGPC_CM_DebugWakeupRequest
Values:
-
enumerator kGPC_Domain0
GPC domain 0.
-
enumerator kGPC_Domain1
GPC domain 1.
-
enumerator kGPC_Domain2
GPC domain 2.
-
enumerator kGPC_Domain3
GPC domain 3.
-
enumerator kGPC_Domain4
GPC domain 4.
-
enumerator kGPC_Domain5
GPC domain 5.
-
enumerator kGPC_Domain6
GPC domain 6.
-
enumerator kGPC_Domain7
GPC domain 7.
-
enumerator kGPC_Domain8
GPC domain 8.
-
enumerator kGPC_Domain9
GPC domain 9.
-
enumerator kGPC_Domain10
GPC domain 10.
-
enumerator kGPC_Domain11
GPC domain 11.
-
enumerator kGPC_Domain12
GPC domain 12.
-
enumerator kGPC_Domain13
GPC domain 13.
-
enumerator kGPC_Domain14
GPC domain 14.
-
enumerator kGPC_Domain15
GPC domain 15.
-
enumerator kGPC_Domain0
-
enum _gpc_cpu_slice
CPU slice.
Values:
-
enumerator kGPC_CPU0
CPU slice 0.
-
enumerator kGPC_CPU1
CPU slice 1.
-
enumerator kGPC_CPU0
-
enum _gpc_cm_tran_step
CPU mode transition step in sleep/wakeup sequence.
Values:
-
enumerator kGPC_CM_SleepSsar
SSAR (State Save And Restore) sleep step.
-
enumerator kGPC_CM_SleepLpcg
LPCG (Low Power Clock Gating) sleep step.
-
enumerator kGPC_CM_SleepPll
PLL sleep step.
-
enumerator kGPC_CM_SleepIso
ISO (Isolation) sleep step.
-
enumerator kGPC_CM_SleepReset
Reset sleep step.
-
enumerator kGPC_CM_SleepPower
Power sleep step.
-
enumerator kGPC_CM_SleepSYS
System sleep sleep step. Note that this step is controlled by system sleep controller.
-
enumerator kGPC_CM_WakeupSYS
System sleep wakeup step. Note that this step is controlled by system sleep controller.
-
enumerator kGPC_CM_WakeupPower
Power wakeup step.
-
enumerator kGPC_CM_WakeupReset
Reset wakeup step.
-
enumerator kGPC_CM_WakeupIso
ISO wakeup step.
-
enumerator kGPC_CM_WakeupPll
PLL wakeup step.
-
enumerator kGPC_CM_WakeupLpcg
LPCG wakeup step.
-
enumerator kGPC_CM_WakeupSsar
SSAR wakeup step.
-
enumerator kGPC_CM_SleepSsar
-
enum _gpc_cpu_mode
CPU mode.
Values:
-
enumerator kGPC_RunMode
Stay in RUN mode.
-
enumerator kGPC_WaitMode
Transit to WAIT mode.
-
enumerator kGPC_StopMode
Transit to STOP mode.
-
enumerator kGPC_SuspendMode
Transit to SUSPEND mode.
-
enumerator kGPC_RunMode
-
enum _gpc_ss_tran_step
GPC system sleep mode transition steps.
Values:
-
enumerator kGPC_SS_Step0In
Bias in step.
-
enumerator kGPC_SS_Step1In
PLDO in step.
-
enumerator kGPC_SS_Step2In
Bandgap in step.
-
enumerator kGPC_SS_Step3In
LDO in step.
-
enumerator kGPC_SS_DcdcIn
DCDC in step.
-
enumerator kGPC_SS_PmicIn
PMIC in step.
-
enumerator kGPC_SS_PmicOut
PMIC out step.
-
enumerator kGPC_SS_DcdcOut
DCDC out step.
-
enumerator kGPC_SS_Step3Out
LDO out step.
-
enumerator kGPC_SS_Step2Out
Bandgap out step.
-
enumerator kGPC_SS_Step1Out
PLDO out step.
-
enumerator kGPC_SS_Step0Out
Bias out step.
-
enumerator kGPC_SS_Step0In
-
typedef enum _gpc_cpu_slice gpc_cpu_slice_t
CPU slice.
-
typedef enum _gpc_cm_tran_step gpc_cm_tran_step_t
CPU mode transition step in sleep/wakeup sequence.
-
typedef enum _gpc_cpu_mode gpc_cpu_mode_t
CPU mode.
-
typedef enum _gpc_ss_tran_step gpc_ss_tran_step_t
GPC system sleep mode transition steps.
-
GPC_RESERVED_USE_MACRO
-
GPC_CM_SLEEP_SSAR_CTRL_OFFSET
-
GPC_CM_SLEEP_LPCG_CTRL_OFFSET
-
GPC_CM_SLEEP_PLL_CTRL_OFFSET
-
GPC_CM_SLEEP_ISO_CTRL_OFFSET
-
GPC_CM_SLEEP_RESET_CTRL_OFFSET
-
GPC_CM_SLEEP_POWER_CTRL_OFFSET
-
GPC_CM_WAKEUP_POWER_CTRL_OFFSET
-
GPC_CM_WAKEUP_RESET_CTRL_OFFSET
-
GPC_CM_WAKEUP_ISO_CTRL_OFFSET
-
GPC_CM_WAKEUP_PLL_CTRL_OFFSET
-
GPC_CM_WAKEUP_LPCG_CTRL_OFFSET
-
GPC_CM_WAKEUP_SSAR_CTRL_OFFSET
-
GPC_SS_STEP0_IN_CTRL_OFFSET
-
GPC_SS_STEP1_IN_CTRL_OFFSET
-
GPC_SS_STEP2_IN_CTRL_OFFSET
-
GPC_SS_STEP3_IN_CTRL_OFFSET
-
GPC_SS_DCDC_IN_CTRL_OFFSET
-
GPC_SS_PMIC_IN_CTRL_OFFSET
-
GPC_SS_PMIC_OUT_CTRL_OFFSET
-
GPC_SS_DCDC_OUT_CTRL_OFFSET
-
GPC_SS_STEP3_OUT_CTRL_OFFSET
-
GPC_SS_STEP2_OUT_CTRL_OFFSET
-
GPC_SS_STEP1_OUT_CTRL_OFFSET
-
GPC_SS_STEP0_OUT_CTRL_OFFSET
-
GPC_CM_STEP_REG_OFFSET
-
GPC_SS_STEP_REG_OFFSET
-
GPC_STAT(mask, shift)
GPT: General Purpose Timer
-
void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)
Initialize GPT to reset state and initialize running mode.
- Parameters:
base – GPT peripheral base address.
initConfig – GPT mode setting configuration.
-
void GPT_Deinit(GPT_Type *base)
Disables the module and gates the GPT clock.
- Parameters:
base – GPT peripheral base address.
-
void GPT_GetDefaultConfig(gpt_config_t *config)
Fills in the GPT configuration structure with default settings.
The default values are:
config->clockSource = kGPT_ClockSource_Periph; config->divider = 1U; config->enableRunInStop = true; config->enableRunInWait = true; config->enableRunInDoze = false; config->enableRunInDbg = false; config->enableFreeRun = false; config->enableMode = true;
- Parameters:
config – Pointer to the user configuration structure.
-
static inline void GPT_SoftwareReset(GPT_Type *base)
Software reset of GPT module.
- Parameters:
base – GPT peripheral base address.
-
static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)
Set clock source of GPT.
- Parameters:
base – GPT peripheral base address.
gptClkSource – Clock source (see gpt_clock_source_t typedef enumeration).
-
static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)
Get clock source of GPT.
- Parameters:
base – GPT peripheral base address.
- Returns:
clock source (see gpt_clock_source_t typedef enumeration).
-
static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)
Set pre scaler of GPT.
- Parameters:
base – GPT peripheral base address.
divider – Divider of GPT (1-4096).
-
static inline uint32_t GPT_GetClockDivider(GPT_Type *base)
Get clock divider in GPT module.
- Parameters:
base – GPT peripheral base address.
- Returns:
clock divider in GPT module (1-4096).
-
static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)
OSC 24M pre-scaler before selected by clock source.
- Parameters:
base – GPT peripheral base address.
divider – OSC Divider(1-16).
-
static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)
Get OSC 24M clock divider in GPT module.
- Parameters:
base – GPT peripheral base address.
- Returns:
OSC clock divider in GPT module (1-16).
-
static inline void GPT_StartTimer(GPT_Type *base)
Start GPT timer.
- Parameters:
base – GPT peripheral base address.
-
static inline void GPT_StopTimer(GPT_Type *base)
Stop GPT timer.
- Parameters:
base – GPT peripheral base address.
-
static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)
Reads the current GPT counting value.
- Parameters:
base – GPT peripheral base address.
- Returns:
Current GPT counter value.
-
static inline void GPT_SetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)
Set GPT operation mode of input capture channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
mode – GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).
-
static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)
Get GPT operation mode of input capture channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
- Returns:
GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).
-
static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)
Get GPT input capture value of certain channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
- Returns:
GPT input capture value.
-
static inline void GPT_SetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)
Set GPT operation mode of output compare channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
mode – GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).
-
static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel)
Get GPT operation mode of output compare channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
- Returns:
GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).
-
static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)
Set GPT output compare value of output compare channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
value – GPT output compare value.
-
static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)
Get GPT output compare value of output compare channel.
- Parameters:
base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
- Returns:
GPT output compare value.
-
static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)
Force GPT output action on output compare channel, ignoring comparator.
- Parameters:
base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
-
static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)
Enables the selected GPT interrupts.
- Parameters:
base – GPT peripheral base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t
-
static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)
Disables the selected GPT interrupts.
- Parameters:
base – GPT peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t
-
static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)
Gets the enabled GPT interrupts.
- Parameters:
base – GPT peripheral base address
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t
-
static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)
Get GPT status flags.
- Parameters:
base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).
- Returns:
GPT status, each bit represents one status flag.
-
static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)
Clears the GPT status flags.
- Parameters:
base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).
-
FSL_GPT_DRIVER_VERSION
-
enum _gpt_clock_source
List of clock sources.
Note
Actual number of clock sources is SoC dependent
Values:
-
enumerator kGPT_ClockSource_Off
GPT Clock Source Off.
-
enumerator kGPT_ClockSource_Periph
GPT Clock Source from Peripheral Clock.
-
enumerator kGPT_ClockSource_HighFreq
GPT Clock Source from High Frequency Reference Clock.
-
enumerator kGPT_ClockSource_Ext
GPT Clock Source from external pin.
-
enumerator kGPT_ClockSource_LowFreq
GPT Clock Source from Low Frequency Reference Clock.
-
enumerator kGPT_ClockSource_Osc
GPT Clock Source from Crystal oscillator.
-
enumerator kGPT_ClockSource_Off
-
enum _gpt_input_capture_channel
List of input capture channel number.
Values:
-
enumerator kGPT_InputCapture_Channel1
GPT Input Capture Channel1.
-
enumerator kGPT_InputCapture_Channel2
GPT Input Capture Channel2.
-
enumerator kGPT_InputCapture_Channel1
-
enum _gpt_input_operation_mode
List of input capture operation mode.
Values:
-
enumerator kGPT_InputOperation_Disabled
Don’t capture.
-
enumerator kGPT_InputOperation_RiseEdge
Capture on rising edge of input pin.
-
enumerator kGPT_InputOperation_FallEdge
Capture on falling edge of input pin.
-
enumerator kGPT_InputOperation_BothEdge
Capture on both edges of input pin.
-
enumerator kGPT_InputOperation_Disabled
-
enum _gpt_output_compare_channel
List of output compare channel number.
Values:
-
enumerator kGPT_OutputCompare_Channel1
Output Compare Channel1.
-
enumerator kGPT_OutputCompare_Channel2
Output Compare Channel2.
-
enumerator kGPT_OutputCompare_Channel3
Output Compare Channel3.
-
enumerator kGPT_OutputCompare_Channel1
-
enum _gpt_output_operation_mode
List of output compare operation mode.
Values:
-
enumerator kGPT_OutputOperation_Disconnected
Don’t change output pin.
-
enumerator kGPT_OutputOperation_Toggle
Toggle output pin.
-
enumerator kGPT_OutputOperation_Clear
Set output pin low.
-
enumerator kGPT_OutputOperation_Set
Set output pin high.
-
enumerator kGPT_OutputOperation_Activelow
Generate a active low pulse on output pin.
-
enumerator kGPT_OutputOperation_Disconnected
-
enum _gpt_interrupt_enable
List of GPT interrupts.
Values:
-
enumerator kGPT_OutputCompare1InterruptEnable
Output Compare Channel1 interrupt enable
-
enumerator kGPT_OutputCompare2InterruptEnable
Output Compare Channel2 interrupt enable
-
enumerator kGPT_OutputCompare3InterruptEnable
Output Compare Channel3 interrupt enable
-
enumerator kGPT_InputCapture1InterruptEnable
Input Capture Channel1 interrupt enable
-
enumerator kGPT_InputCapture2InterruptEnable
Input Capture Channel1 interrupt enable
-
enumerator kGPT_RollOverFlagInterruptEnable
Counter rolled over interrupt enable
-
enumerator kGPT_OutputCompare1InterruptEnable
-
enum _gpt_status_flag
Status flag.
Values:
-
enumerator kGPT_OutputCompare1Flag
Output compare channel 1 event.
-
enumerator kGPT_OutputCompare2Flag
Output compare channel 2 event.
-
enumerator kGPT_OutputCompare3Flag
Output compare channel 3 event.
-
enumerator kGPT_InputCapture1Flag
Input Capture channel 1 event.
-
enumerator kGPT_InputCapture2Flag
Input Capture channel 2 event.
-
enumerator kGPT_RollOverFlag
Counter reaches maximum value and rolled over to 0 event.
-
enumerator kGPT_OutputCompare1Flag
-
typedef enum _gpt_clock_source gpt_clock_source_t
List of clock sources.
Note
Actual number of clock sources is SoC dependent
-
typedef enum _gpt_input_capture_channel gpt_input_capture_channel_t
List of input capture channel number.
-
typedef enum _gpt_input_operation_mode gpt_input_operation_mode_t
List of input capture operation mode.
-
typedef enum _gpt_output_compare_channel gpt_output_compare_channel_t
List of output compare channel number.
-
typedef enum _gpt_output_operation_mode gpt_output_operation_mode_t
List of output compare operation mode.
-
typedef enum _gpt_interrupt_enable gpt_interrupt_enable_t
List of GPT interrupts.
-
typedef enum _gpt_status_flag gpt_status_flag_t
Status flag.
-
typedef struct _gpt_init_config gpt_config_t
Structure to configure the running mode.
-
struct _gpt_init_config
- #include <fsl_gpt.h>
Structure to configure the running mode.
Public Members
-
gpt_clock_source_t clockSource
clock source for GPT module.
-
uint32_t divider
clock divider (prescaler+1) from clock source to counter.
-
bool enableFreeRun
true: FreeRun mode, false: Restart mode.
-
bool enableRunInWait
GPT enabled in wait mode.
-
bool enableRunInStop
GPT enabled in stop mode.
-
bool enableRunInDoze
GPT enabled in doze mode.
-
bool enableRunInDbg
GPT enabled in debug mode.
-
bool enableMode
true: counter reset to 0 when enabled; false: counter retain its value when enabled.
-
gpt_clock_source_t clockSource
I3C: I3C Driver
-
FSL_I3C_DRIVER_VERSION
I3C driver version.
I3C status return codes.
Values:
-
enumerator kStatus_I3C_Busy
The master is already performing a transfer.
-
enumerator kStatus_I3C_Idle
The slave driver is idle.
-
enumerator kStatus_I3C_Nak
The slave device sent a NAK in response to an address.
-
enumerator kStatus_I3C_WriteAbort
The slave device sent a NAK in response to a write.
-
enumerator kStatus_I3C_Term
The master terminates slave read.
-
enumerator kStatus_I3C_HdrParityError
Parity error from DDR read.
-
enumerator kStatus_I3C_CrcError
CRC error from DDR read.
-
enumerator kStatus_I3C_ReadFifoError
Read from M/SRDATAB register when FIFO empty.
-
enumerator kStatus_I3C_WriteFifoError
Write to M/SWDATAB register when FIFO full.
-
enumerator kStatus_I3C_MsgError
Message SDR/DDR mismatch or read/write message in wrong state
-
enumerator kStatus_I3C_InvalidReq
Invalid use of request.
-
enumerator kStatus_I3C_Timeout
The module has stalled too long in a frame.
-
enumerator kStatus_I3C_SlaveCountExceed
The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
-
enumerator kStatus_I3C_IBIWon
The I3C slave event IBI or MR or HJ won the arbitration on a header address.
-
enumerator kStatus_I3C_OverrunError
Slave internal from-bus buffer/FIFO overrun.
-
enumerator kStatus_I3C_UnderrunError
Slave internal to-bus buffer/FIFO underrun
-
enumerator kStatus_I3C_UnderrunNak
Slave internal from-bus buffer/FIFO underrun and NACK error
-
enumerator kStatus_I3C_InvalidStart
Slave invalid start flag
-
enumerator kStatus_I3C_SdrParityError
SDR parity error
-
enumerator kStatus_I3C_S0S1Error
S0 or S1 error
-
enumerator kStatus_I3C_Busy
-
enum _i3c_hdr_mode
I3C HDR modes.
Values:
-
enumerator kI3C_HDRModeNone
-
enumerator kI3C_HDRModeDDR
-
enumerator kI3C_HDRModeTSP
-
enumerator kI3C_HDRModeTSL
-
enumerator kI3C_HDRModeNone
-
typedef enum _i3c_hdr_mode i3c_hdr_mode_t
I3C HDR modes.
-
typedef struct _i3c_device_info i3c_device_info_t
I3C device information.
-
I3C_RETRY_TIMES
Timeout times for waiting flag.
-
I3C_MAX_DEVCNT
-
I3C_IBI_BUFF_SIZE
-
struct _i3c_device_info
- #include <fsl_i3c.h>
I3C device information.
Public Members
-
uint8_t dynamicAddr
Device dynamic address.
-
uint8_t staticAddr
Static address.
-
uint8_t dcr
Device characteristics register information.
-
uint8_t bcr
Bus characteristics register information.
-
uint16_t vendorID
Device vendor ID(manufacture ID).
-
uint32_t partNumber
Device part number info
-
uint16_t maxReadLength
Maximum read length.
-
uint16_t maxWriteLength
Maximum write length.
-
uint8_t hdrMode
Support hdr mode, could be OR logic in i3c_hdr_mode.
-
uint8_t dynamicAddr
I3C Common Driver
-
typedef struct _i3c_config i3c_config_t
Structure with settings to initialize the I3C module, could both initialize master and slave functionality.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
-
uint32_t I3C_GetInstance(I3C_Type *base)
Get which instance current I3C is used.
- Parameters:
base – The I3C peripheral base address.
-
void I3C_GetDefaultConfig(i3c_config_t *config)
Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.
This function provides the following default configuration for I3C:
config->enableMaster = kI3C_MasterCapable; config->disableTimeout = false; config->hKeep = kI3C_MasterHighKeeperNone; config->enableOpenDrainStop = true; config->enableOpenDrainHigh = true; config->baudRate_Hz.i2cBaud = 400000U; config->baudRate_Hz.i3cPushPullBaud = 12500000U; config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; config->masterDynamicAddress = 0x0AU; config->slowClock_Hz = 1000000U; config->enableSlave = true; config->vendorID = 0x11BU; config->enableRandomPart = false; config->partNumber = 0; config->dcr = 0; config->bcr = 0; config->hdrMode = (uint8_t)kI3C_HDRModeDDR; config->nakAllRequest = false; config->ignoreS0S1Error = false; config->offline = false; config->matchSlaveStartStop = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().
- Parameters:
config – [out] User provided configuration structure for default values. Refer to i3c_config_t.
-
void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)
Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration.
- Parameters:
base – The I3C peripheral base address.
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.
-
struct _i3c_config
- #include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
Public Members
-
i3c_master_enable_t enableMaster
Enable master mode.
-
bool disableTimeout
Whether to disable timeout to prevent the ERRWARN.
-
i3c_master_hkeep_t hKeep
High keeper mode setting.
-
bool enableOpenDrainStop
Whether to emit open-drain speed STOP.
-
bool enableOpenDrainHigh
Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD.
-
i3c_baudrate_hz_t baudRate_Hz
Desired baud rate settings.
-
uint8_t masterDynamicAddress
Main master dynamic address configuration.
-
uint32_t maxWriteLength
Maximum write length.
-
uint32_t maxReadLength
Maximum read length.
-
bool enableSlave
Whether to enable slave.
-
uint8_t staticAddr
Static address.
-
uint16_t vendorID
Device vendor ID(manufacture ID).
-
uint32_t partNumber
Device part number info
-
uint8_t dcr
Device characteristics register information.
-
uint8_t bcr
Bus characteristics register information.
-
uint8_t hdrMode
Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t.
-
bool nakAllRequest
Whether to reply NAK to all requests except broadcast CCC.
-
bool ignoreS0S1Error
Whether to ignore S0/S1 error in SDR mode.
-
bool offline
Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely.
-
bool matchSlaveStartStop
Whether to assert start/stop status only the time slave is addressed.
-
i3c_master_enable_t enableMaster
I3C Master Driver
-
void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)
Provides a default configuration for the I3C master peripheral.
This function provides the following default configuration for the I3C master peripheral:
masterConfig->enableMaster = kI3C_MasterOn; masterConfig->disableTimeout = false; masterConfig->hKeep = kI3C_MasterHighKeeperNone; masterConfig->enableOpenDrainStop = true; masterConfig->enableOpenDrainHigh = true; masterConfig->baudRate_Hz = 100000U; masterConfig->busType = kI3C_TypeI2C;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I3C_MasterInit().
- Parameters:
masterConfig – [out] User provided configuration structure for default values. Refer to i3c_master_config_t.
-
void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
Initializes the I3C master peripheral.
This function enables the peripheral clock and initializes the I3C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.
- Parameters:
base – The I3C peripheral base address.
masterConfig – User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.
-
void I3C_MasterDeinit(I3C_Type *base)
Deinitializes the I3C master peripheral.
This function disables the I3C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.
- Parameters:
base – The I3C peripheral base address.
-
status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)
-
status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)
-
status_t I3C_CheckForBusyBus(I3C_Type *base)
-
static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)
Set I3C module master mode.
- Parameters:
base – The I3C peripheral base address.
enable – Enable master mode.
-
void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)
Provides a default configuration for the I3C slave peripheral.
This function provides the following default configuration for the I3C slave peripheral:
slaveConfig->enableslave = true;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().
- Parameters:
slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t.
-
void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)
Initializes the I3C slave peripheral.
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.
- Parameters:
base – The I3C peripheral base address.
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override.
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
-
void I3C_SlaveDeinit(I3C_Type *base)
Deinitializes the I3C slave peripheral.
This function disables the I3C slave peripheral and gates the clock.
- Parameters:
base – The I3C peripheral base address.
-
static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
Enable/Disable Slave.
- Parameters:
base – The I3C peripheral base address.
isEnable – Enable or disable.
-
static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)
Gets the I3C master status flags.
A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_master_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C master status flag state.
The following status register flags can be cleared:
kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag
Attempts to clear other flags has no effect.
See also
_i3c_master_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_master_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags().
-
static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)
Gets the I3C master error status flags.
A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_master_error_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the error status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C master error status flag state.
See also
_i3c_master_error_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_master_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags().
-
i3c_master_state_t I3C_MasterGetState(I3C_Type *base)
Gets the I3C master state.
- Parameters:
base – The I3C peripheral base address.
- Returns:
I3C master state.
-
static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)
Gets the I3C slave status flags.
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_slave_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C slave status flag state.
The following status register flags can be cleared:
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
Attempts to clear other flags has no effect.
See also
_i3c_slave_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags().
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static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)
Gets the I3C slave error status flags.
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_slave_error_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the error status flags:
1: related status flag is set.
0: related status flag is not set.
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static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C slave error status flag state.
See also
_i3c_slave_error_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags().
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i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)
Gets the I3C slave state.
- Parameters:
base – The I3C peripheral base address.
- Returns:
I3C slave activity state, refer i3c_slave_activity_state_t.
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status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)
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static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
Enables the I3C master interrupt requests.
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask.
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static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
Disables the I3C master interrupt requests.
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask.
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static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)
Returns the set of currently enabled I3C master interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.
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static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)
Returns the set of pending I3C master interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of pending interrupts.
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static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
Enables the I3C slave interrupt requests.
Only below flags can be enabled as interrupts.
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
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static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
Disables the I3C slave interrupt requests.
Only below flags can be disabled as interrupts.
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
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static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)
Returns the set of currently enabled I3C slave interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.
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static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
Returns the set of pending I3C slave interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts.
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static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
Enables or disables I3C master DMA requests.
- Parameters:
base – The I3C peripheral base address.
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.
width – DMA read/write unit in bytes.
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static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C master transmit data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Master Transmit Data Register address.
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static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C master receive data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Master Receive Data Register address.
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static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
Enables or disables I3C slave DMA requests.
- Parameters:
base – The I3C peripheral base address.
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.
width – DMA read/write unit in bytes.
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static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C slave transmit data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Slave Transmit Data Register address.
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static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C slave receive data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Slave Receive Data Register address.
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static inline void I3C_MasterSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
Sets the watermarks for I3C master FIFOs.
- Parameters:
base – The I3C peripheral base address.
txLvl – Transmit FIFO watermark level. The kI3C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.
rxLvl – Receive FIFO watermark level. The kI3C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
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static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
Gets the current number of bytes in the I3C master FIFOs.
- Parameters:
base – The I3C peripheral base address.
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.
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static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
Sets the watermarks for I3C slave FIFOs.
- Parameters:
base – The I3C peripheral base address.
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
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static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
Gets the current number of bytes in the I3C slave FIFOs.
- Parameters:
base – The I3C peripheral base address.
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.
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void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz)
Sets the I3C bus frequency for master transactions.
The I3C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.
- Parameters:
base – The I3C peripheral base address.
baudRate_Hz – Pointer to structure of requested bus frequency in Hertz.
sourceClock_Hz – I3C functional clock frequency in Hertz.
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static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)
Returns whether the bus is idle.
Requires the master mode to be enabled.
- Parameters:
base – The I3C peripheral base address.
- Return values:
true – Bus is busy.
false – Bus is idle.
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status_t I3C_MasterStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)
Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified in the call.
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the a address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.
- Parameters:
base – The I3C peripheral base address.
type – The bus type to use in this transaction.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes.
- Return values:
kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
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status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)
Sends a START signal and slave address on the I2C/I3C bus.
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.
- Parameters:
base – The I3C peripheral base address.
type – The bus type to use in this transaction.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
- Return values:
kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
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status_t I3C_MasterRepeatedStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)
Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified in the call.
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize configuration.
Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.
- Parameters:
base – The I3C peripheral base address.
type – The bus type to use in this transaction.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes.
- Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.
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static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)
Sends a repeated START signal and slave address on the I2C/I3C bus.
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address.
Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.
- Parameters:
base – The I3C peripheral base address.
type – The bus type to use in this transaction.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
- Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.
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status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)
Performs a polling send transfer on the I2C/I3C bus.
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_I3C_Nak.
- Parameters:
base – The I3C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options.
- Return values:
kStatus_Success – Data was sent successfully.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
kStatus_I3C_Timeout – The module has stalled too long in a frame.
kStatus_I3C_Nak – The slave device sent a NAK in response to an address.
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write.
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full.
kStatus_I3C_InvalidReq – Invalid use of request.
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status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
Performs a polling receive transfer on the I2C/I3C bus.
- Parameters:
base – The I3C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options.
- Return values:
kStatus_Success – Data was received successfully.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
kStatus_I3C_Timeout – The module has stalled too long in a frame.
kStatus_I3C_Term – The master terminates slave read.
kStatus_I3C_HdrParityError – Parity error from DDR read.
kStatus_I3C_CrcError – CRC error from DDR read.
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty.
kStatus_I3C_InvalidReq – Invalid use of request.
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status_t I3C_MasterStop(I3C_Type *base)
Sends a STOP signal on the I2C/I3C bus.
This function does not return until the STOP signal is seen on the bus, or an error occurs.
- Parameters:
base – The I3C peripheral base address.
- Return values:
kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
kStatus_I3C_Timeout – The module has stalled too long in a frame.
kStatus_I3C_InvalidReq – Invalid use of request.
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void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq)
I3C master emit request.
- Parameters:
base – The I3C peripheral base address.
masterReq – I3C master request of type i3c_bus_request_t
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static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)
I3C master emit request.
- Parameters:
base – The I3C peripheral base address.
ibiResponse – I3C master emit IBI response of type i3c_ibi_response_t
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void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)
I3C master register IBI rule.
- Parameters:
base – The I3C peripheral base address.
ibiRule – Pointer to ibi rule description of type i3c_register_ibi_addr_t
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void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)
I3C master get IBI rule.
- Parameters:
base – The I3C peripheral base address.
ibiRule – Pointer to store the read out ibi rule description.
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i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base)
I3C master get IBI Type.
- Parameters:
base – The I3C peripheral base address.
- Return values:
i3c_ibi_type_t – Type of i3c_ibi_type_t.
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static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)
I3C master get IBI Address.
- Parameters:
base – The I3C peripheral base address.
- Return values:
The – 8-bit IBI address.
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status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint8_t *addressList, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate)
Performs a DAA in the i3c bus with specified temporary baud rate.
- Parameters:
base – The I3C peripheral base address.
addressList – The pointer for address list which is used to do DAA.
count – The address count in the address list.
daaBaudRate – The temporary baud rate in DAA process, NULL for using initial setting. The initial setting is set back between the completion of the DAA and the return of this function.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
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static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)
Performs a DAA in the i3c bus.
- Parameters:
base – The I3C peripheral base address.
addressList – The pointer for address list which is used to do DAA.
count – The address count in the address list. The initial setting is set back between the completion of the DAA and the return of this function.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
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i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count)
Get device information list after DAA process is done.
- Parameters:
base – The I3C peripheral base address.
count – [out] The pointer to store the available device count.
- Returns:
Pointer to the i3c_device_info_t array.
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void I3C_MasterClearDeviceCount(I3C_Type *base)
Clear the global device count which represents current devices number on the bus. When user resets all dynamic addresses on the bus, should call this API.
- Parameters:
base – The I3C peripheral base address.
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status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer)
Performs a master polling transfer on the I2C/I3C bus.
Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.
- Parameters:
base – The I3C peripheral base address.
transfer – Pointer to the transfer structure.
- Return values:
kStatus_Success – Data was received successfully.
kStatus_I3C_Busy – Another master is currently utilizing the bus.
kStatus_I3C_IBIWon – The I3C slave event IBI or MR or HJ won the arbitration on a header address.
kStatus_I3C_Timeout – The module has stalled too long in a frame.
kStatus_I3C_Nak – The slave device sent a NAK in response to an address.
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write.
kStatus_I3C_Term – The master terminates slave read.
kStatus_I3C_HdrParityError – Parity error from DDR read.
kStatus_I3C_CrcError – CRC error from DDR read.
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty.
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full.
kStatus_I3C_InvalidReq – Invalid use of request.
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status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)
Performs a polling send transfer on the I3C bus.
- Parameters:
base – The I3C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
- Returns:
Error or success status returned by API.
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status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)
Performs a polling receive transfer on the I3C bus.
- Parameters:
base – The I3C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
- Returns:
Error or success status returned by API.
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void I3C_MasterTransferCreateHandle(I3C_Type *base, i3c_master_handle_t *handle, const i3c_master_transfer_callback_t *callback, void *userData)
Creates a new handle for the I3C master non-blocking APIs.
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbort() API shall be called.
Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.
- Parameters:
base – The I3C peripheral base address.
handle – [out] Pointer to the I3C master driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
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status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer)
Performs a non-blocking transaction on the I2C/I3C bus.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
transfer – The pointer to the transfer descriptor.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.
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status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count)
Returns number of bytes transferred so far.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
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void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)
Terminates a non-blocking I3C master transmission early.
Note
It is not safe to call this function from an IRQ handler that has a higher priority than the I3C peripheral’s IRQ priority.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
- Return values:
kStatus_Success – A transaction was successfully aborted.
kStatus_I3C_Idle – There is not a non-blocking transaction currently in progress.
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void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)
Reusable routine to handle master interrupts.
Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The I3C peripheral base address.
intHandle – Pointer to the I3C master driver handle.
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enum _i3c_master_flags
I3C master peripheral flags.
The following status register flags can be cleared:
kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.
Note
These enums are meant to be OR’d together to form a bit mask.
Values:
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enumerator kI3C_MasterBetweenFlag
Between messages/DAAs flag
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enumerator kI3C_MasterNackDetectFlag
NACK detected flag
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enumerator kI3C_MasterSlaveStartFlag
Slave request start flag
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enumerator kI3C_MasterControlDoneFlag
Master request complete flag
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enumerator kI3C_MasterCompleteFlag
Transfer complete flag
-
enumerator kI3C_MasterRxReadyFlag
Rx data ready in Rx buffer flag
-
enumerator kI3C_MasterTxReadyFlag
Tx buffer ready for Tx data flag
-
enumerator kI3C_MasterArbitrationWonFlag
Header address won arbitration flag
-
enumerator kI3C_MasterErrorFlag
Error occurred flag
-
enumerator kI3C_MasterSlave2MasterFlag
Switch from slave to master flag
-
enumerator kI3C_MasterClearFlags
-
enum _i3c_master_error_flags
I3C master error flags to indicate the causes.
Note
These enums are meant to be OR’d together to form a bit mask.
Values:
-
enumerator kI3C_MasterErrorNackFlag
Slave NACKed the last address
-
enumerator kI3C_MasterErrorWriteAbortFlag
Slave NACKed the write data
-
enumerator kI3C_MasterErrorParityFlag
Parity error from DDR read
-
enumerator kI3C_MasterErrorCrcFlag
CRC error from DDR read
-
enumerator kI3C_MasterErrorReadFlag
Read from MRDATAB register when FIFO empty
-
enumerator kI3C_MasterErrorWriteFlag
Write to MWDATAB register when FIFO full
-
enumerator kI3C_MasterErrorMsgFlag
Message SDR/DDR mismatch or read/write message in wrong state
-
enumerator kI3C_MasterErrorInvalidReqFlag
Invalid use of request
-
enumerator kI3C_MasterErrorTimeoutFlag
The module has stalled too long in a frame
-
enumerator kI3C_MasterAllErrorFlags
All error flags
-
enumerator kI3C_MasterErrorNackFlag
-
enum _i3c_master_state
I3C working master state.
Values:
-
enumerator kI3C_MasterStateIdle
Bus stopped.
-
enumerator kI3C_MasterStateSlvReq
Bus stopped but slave holding SDA low.
-
enumerator kI3C_MasterStateMsgSdr
In SDR Message mode from using MWMSG_SDR.
-
enumerator kI3C_MasterStateNormAct
In normal active SDR mode.
-
enumerator kI3C_MasterStateDdr
In DDR Message mode.
-
enumerator kI3C_MasterStateDaa
In ENTDAA mode.
-
enumerator kI3C_MasterStateIbiAck
Waiting on IBI ACK/NACK decision.
-
enumerator kI3C_MasterStateIbiRcv
Receiving IBI.
-
enumerator kI3C_MasterStateIdle
-
enum _i3c_master_enable
I3C master enable configuration.
Values:
-
enumerator kI3C_MasterOff
Master off.
-
enumerator kI3C_MasterOn
Master on.
-
enumerator kI3C_MasterCapable
Master capable.
-
enumerator kI3C_MasterOff
-
enum _i3c_master_hkeep
I3C high keeper configuration.
Values:
-
enumerator kI3C_MasterHighKeeperNone
Use PUR to hold SCL high.
-
enumerator kI3C_MasterHighKeeperWiredIn
Use pin_HK controls.
-
enumerator kI3C_MasterPassiveSDA
Hi-Z for Bus Free and hold SDA.
-
enumerator kI3C_MasterPassiveSDASCL
Hi-Z both for Bus Free, and can Hi-Z SDA for hold.
-
enumerator kI3C_MasterHighKeeperNone
-
enum _i3c_bus_request
Emits the requested operation when doing in pieces vs. by message.
Values:
-
enumerator kI3C_RequestNone
No request.
-
enumerator kI3C_RequestEmitStartAddr
Request to emit start and address on bus.
-
enumerator kI3C_RequestEmitStop
Request to emit stop on bus.
-
enumerator kI3C_RequestIbiAckNack
Manual IBI ACK or NACK.
-
enumerator kI3C_RequestProcessDAA
Process DAA.
-
enumerator kI3C_RequestForceExit
Request to force exit.
-
enumerator kI3C_RequestAutoIbi
Hold in stopped state, but Auto-emit START,7E.
-
enumerator kI3C_RequestNone
-
enum _i3c_bus_type
Bus type with EmitStartAddr.
Values:
-
enumerator kI3C_TypeI3CSdr
SDR mode of I3C.
-
enumerator kI3C_TypeI2C
Standard i2c protocol.
-
enumerator kI3C_TypeI3CDdr
HDR-DDR mode of I3C.
-
enumerator kI3C_TypeI3CSdr
-
enum _i3c_ibi_response
IBI response.
Values:
-
enumerator kI3C_IbiRespAck
ACK with no mandatory byte.
-
enumerator kI3C_IbiRespNack
NACK.
-
enumerator kI3C_IbiRespAckMandatory
ACK with mandatory byte.
-
enumerator kI3C_IbiRespManual
Reserved.
-
enumerator kI3C_IbiRespAck
-
enum _i3c_ibi_type
IBI type.
Values:
-
enumerator kI3C_IbiNormal
In-band interrupt.
-
enumerator kI3C_IbiHotJoin
slave hot join.
-
enumerator kI3C_IbiMasterRequest
slave master ship request.
-
enumerator kI3C_IbiNormal
-
enum _i3c_ibi_state
IBI state.
Values:
-
enumerator kI3C_IbiReady
In-band interrupt ready state, ready for user to handle.
-
enumerator kI3C_IbiDataBuffNeed
In-band interrupt need data buffer for data receive.
-
enumerator kI3C_IbiAckNackPending
In-band interrupt Ack/Nack pending for decision.
-
enumerator kI3C_IbiReady
-
enum _i3c_direction
Direction of master and slave transfers.
Values:
-
enumerator kI3C_Write
Master transmit.
-
enumerator kI3C_Read
Master receive.
-
enumerator kI3C_Write
-
enum _i3c_tx_trigger_level
Watermark of TX int/dma trigger level.
Values:
-
enumerator kI3C_TxTriggerOnEmpty
Trigger on empty.
-
enumerator kI3C_TxTriggerUntilOneQuarterOrLess
Trigger on 1/4 full or less.
-
enumerator kI3C_TxTriggerUntilOneHalfOrLess
Trigger on 1/2 full or less.
-
enumerator kI3C_TxTriggerUntilOneLessThanFull
Trigger on 1 less than full or less.
-
enumerator kI3C_TxTriggerOnEmpty
-
enum _i3c_rx_trigger_level
Watermark of RX int/dma trigger level.
Values:
-
enumerator kI3C_RxTriggerOnNotEmpty
Trigger on not empty.
-
enumerator kI3C_RxTriggerUntilOneQuarterOrMore
Trigger on 1/4 full or more.
-
enumerator kI3C_RxTriggerUntilOneHalfOrMore
Trigger on 1/2 full or more.
-
enumerator kI3C_RxTriggerUntilThreeQuarterOrMore
Trigger on 3/4 full or more.
-
enumerator kI3C_RxTriggerOnNotEmpty
-
enum _i3c_rx_term_ops
I3C master read termination operations.
Values:
-
enumerator kI3C_RxTermDisable
Master doesn’t terminate read, used for CCC transfer.
-
enumerator kI3C_RxAutoTerm
Master auto terminate read after receiving specified bytes(<=255).
-
enumerator kI3C_RxTermLastByte
Master terminates read at any time after START, no length limitation.
-
enumerator kI3C_RxTermDisable
-
enum _i3c_start_scl_delay
I3C start SCL delay options.
Values:
-
enumerator kI3C_NoDelay
No delay.
-
enumerator kI3C_IncreaseSclHalfPeriod
Increases SCL clock period by 1/2.
-
enumerator kI3C_IncreaseSclOnePeriod
Increases SCL clock period by 1.
-
enumerator kI3C_IncreaseSclOneAndHalfPeriod
Increases SCL clock period by 1 1/2
-
enumerator kI3C_NoDelay
-
enum _i3c_master_transfer_flags
Transfer option flags.
Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _i3c_master_transfer::flags field.
Values:
-
enumerator kI3C_TransferDefaultFlag
Transfer starts with a start signal, stops with a stop signal.
-
enumerator kI3C_TransferNoStartFlag
Don’t send a start condition, address, and sub address
-
enumerator kI3C_TransferRepeatedStartFlag
Send a repeated start condition
-
enumerator kI3C_TransferNoStopFlag
Don’t send a stop condition.
-
enumerator kI3C_TransferWordsFlag
Transfer in words, else transfer in bytes.
-
enumerator kI3C_TransferDisableRxTermFlag
Disable Rx termination. Note: It’s for I3C CCC transfer.
-
enumerator kI3C_TransferRxAutoTermFlag
Set Rx auto-termination. Note: It’s adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive.
-
enumerator kI3C_TransferStartWithBroadcastAddr
Start transfer with 0x7E, then read/write data with device address.
-
enumerator kI3C_TransferDefaultFlag
-
typedef enum _i3c_master_state i3c_master_state_t
I3C working master state.
-
typedef enum _i3c_master_enable i3c_master_enable_t
I3C master enable configuration.
-
typedef enum _i3c_master_hkeep i3c_master_hkeep_t
I3C high keeper configuration.
-
typedef enum _i3c_bus_request i3c_bus_request_t
Emits the requested operation when doing in pieces vs. by message.
-
typedef enum _i3c_bus_type i3c_bus_type_t
Bus type with EmitStartAddr.
-
typedef enum _i3c_ibi_response i3c_ibi_response_t
IBI response.
-
typedef enum _i3c_ibi_type i3c_ibi_type_t
IBI type.
-
typedef enum _i3c_ibi_state i3c_ibi_state_t
IBI state.
-
typedef enum _i3c_direction i3c_direction_t
Direction of master and slave transfers.
-
typedef enum _i3c_tx_trigger_level i3c_tx_trigger_level_t
Watermark of TX int/dma trigger level.
-
typedef enum _i3c_rx_trigger_level i3c_rx_trigger_level_t
Watermark of RX int/dma trigger level.
-
typedef enum _i3c_rx_term_ops i3c_rx_term_ops_t
I3C master read termination operations.
-
typedef enum _i3c_start_scl_delay i3c_start_scl_delay_t
I3C start SCL delay options.
-
typedef struct _i3c_register_ibi_addr i3c_register_ibi_addr_t
Structure with setting master IBI rules and slave registry.
-
typedef struct _i3c_baudrate i3c_baudrate_hz_t
Structure with I3C baudrate settings.
-
typedef struct _i3c_master_daa_baudrate i3c_master_daa_baudrate_t
I3C DAA baud rate configuration.
-
typedef struct _i3c_master_config i3c_master_config_t
Structure with settings to initialize the I3C master module.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
-
typedef struct _i3c_master_transfer i3c_master_transfer_t
-
typedef struct _i3c_master_handle i3c_master_handle_t
-
typedef struct _i3c_master_transfer_callback i3c_master_transfer_callback_t
i3c master callback functions.
-
typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle)
Typedef for master interrupt handler.
-
struct _i3c_register_ibi_addr
- #include <fsl_i3c.h>
Structure with setting master IBI rules and slave registry.
Public Members
-
uint8_t address[5]
Address array for registry.
-
bool ibiHasPayload
Whether the address array has mandatory IBI byte.
-
uint8_t address[5]
-
struct _i3c_baudrate
- #include <fsl_i3c.h>
Structure with I3C baudrate settings.
Public Members
-
uint32_t i2cBaud
Desired I2C baud rate in Hertz.
-
uint32_t i3cPushPullBaud
Desired I3C push-pull baud rate in Hertz.
-
uint32_t i3cOpenDrainBaud
Desired I3C open-drain baud rate in Hertz.
-
uint32_t i2cBaud
-
struct _i3c_master_daa_baudrate
- #include <fsl_i3c.h>
I3C DAA baud rate configuration.
Public Members
-
uint32_t sourceClock_Hz
FCLK, function clock in Hertz.
-
uint32_t i3cPushPullBaud
Desired I3C push-pull baud rate in Hertz.
-
uint32_t i3cOpenDrainBaud
Desired I3C open-drain baud rate in Hertz.
-
uint32_t sourceClock_Hz
-
struct _i3c_master_config
- #include <fsl_i3c.h>
Structure with settings to initialize the I3C master module.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
Public Members
-
i3c_master_enable_t enableMaster
Enable master mode.
-
bool disableTimeout
Whether to disable timeout to prevent the ERRWARN.
-
i3c_master_hkeep_t hKeep
High keeper mode setting.
-
bool enableOpenDrainStop
Whether to emit open-drain speed STOP.
-
bool enableOpenDrainHigh
Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD.
-
i3c_baudrate_hz_t baudRate_Hz
Desired baud rate settings.
-
i3c_master_enable_t enableMaster
-
struct _i3c_master_transfer_callback
- #include <fsl_i3c.h>
i3c master callback functions.
Public Members
-
void (*slave2Master)(I3C_Type *base, void *userData)
Transfer complete callback
-
void (*ibiCallback)(I3C_Type *base, i3c_master_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)
IBI event callback
-
void (*transferComplete)(I3C_Type *base, i3c_master_handle_t *handle, status_t completionStatus, void *userData)
Transfer complete callback
-
void (*slave2Master)(I3C_Type *base, void *userData)
-
struct _i3c_master_transfer
- #include <fsl_i3c.h>
Non-blocking transfer descriptor structure.
This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API.
Public Members
-
uint32_t flags
Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. Set to 0 or kI3C_TransferDefaultFlag for normal transfers.
-
uint8_t slaveAddress
The 7-bit slave address.
-
i3c_direction_t direction
Either kI3C_Read or kI3C_Write.
-
uint32_t subaddress
Sub address. Transferred MSB first.
-
size_t subaddressSize
Length of sub address to send in bytes. Maximum size is 4 bytes.
-
void *data
Pointer to data to transfer.
-
size_t dataSize
Number of bytes to transfer.
-
i3c_bus_type_t busType
bus type.
-
i3c_ibi_response_t ibiResponse
ibi response during transfer.
-
uint32_t flags
-
struct _i3c_master_handle
- #include <fsl_i3c.h>
Driver handle for master non-blocking APIs.
Note
The contents of this structure are private and subject to change.
Public Members
-
uint8_t state
Transfer state machine current state.
-
uint32_t remainingBytes
Remaining byte count in current state.
-
i3c_rx_term_ops_t rxTermOps
Read termination operation.
-
i3c_master_transfer_t transfer
Copy of the current transfer info.
-
uint8_t ibiAddress
Slave address which request IBI.
-
uint8_t *ibiBuff
Pointer to IBI buffer to keep ibi bytes.
-
size_t ibiPayloadSize
IBI payload size.
-
i3c_ibi_type_t ibiType
IBI type.
-
i3c_master_transfer_callback_t callback
Callback functions pointer.
-
void *userData
Application data passed to callback.
-
uint8_t state
I3C Master DMA Driver
-
void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, const i3c_master_edma_callback_t *callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)
Create a new handle for the I3C master DMA APIs.
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function.
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function.
-
status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)
Performs a non-blocking DMA-based transaction on the I3C bus.
The callback specified when the handle was created is invoked when the transaction has completed.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
transfer – The pointer to the transfer descriptor.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.
-
status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)
Returns number of bytes transferred so far.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.
-
void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)
Terminates a non-blocking I3C master transmission early.
Note
It is not safe to call this function from an IRQ handler that has a higher priority than the DMA peripheral’s IRQ priority.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C master driver handle.
-
void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)
Reusable routine to handle master interrupts.
Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The I3C peripheral base address.
i3cHandle – Pointer to the I3C master DMA driver handle.
-
typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t
-
typedef struct _i3c_master_edma_callback i3c_master_edma_callback_t
i3c master callback functions.
-
struct _i3c_master_edma_callback
- #include <fsl_i3c_edma.h>
i3c master callback functions.
Public Members
-
void (*slave2Master)(I3C_Type *base, void *userData)
Transfer complete callback
-
void (*ibiCallback)(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)
IBI event callback
-
void (*transferComplete)(I3C_Type *base, i3c_master_edma_handle_t *handle, status_t status, void *userData)
Transfer complete callback
-
void (*slave2Master)(I3C_Type *base, void *userData)
-
struct _i3c_master_edma_handle
- #include <fsl_i3c_edma.h>
Driver handle for master EDMA APIs.
Note
The contents of this structure are private and subject to change.
Public Members
-
I3C_Type *base
I3C base pointer.
-
uint8_t state
Transfer state machine current state.
-
uint32_t transferCount
Indicates progress of the transfer
-
uint8_t subaddressBuffer[4]
Saving subaddress command.
-
uint8_t subaddressCount
Saving command count.
-
i3c_master_transfer_t transfer
Copy of the current transfer info.
-
i3c_master_edma_callback_t callback
Callback function pointer.
-
void *userData
Application data passed to callback.
-
edma_handle_t *rxDmaHandle
Handle for receive DMA channel.
-
edma_handle_t *txDmaHandle
Handle for transmit DMA channel.
-
uint8_t ibiAddress
Slave address which request IBI.
-
uint8_t *ibiBuff
Pointer to IBI buffer to keep ibi bytes.
-
size_t ibiPayloadSize
IBI payload size.
-
i3c_ibi_type_t ibiType
IBI type.
-
I3C_Type *base
I3C Slave Driver
-
void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)
Provides a default configuration for the I3C slave peripheral.
This function provides the following default configuration for the I3C slave peripheral:
slaveConfig->enableslave = true;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().
- Parameters:
slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t.
-
void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)
Initializes the I3C slave peripheral.
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.
- Parameters:
base – The I3C peripheral base address.
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override.
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
-
void I3C_SlaveDeinit(I3C_Type *base)
Deinitializes the I3C slave peripheral.
This function disables the I3C slave peripheral and gates the clock.
- Parameters:
base – The I3C peripheral base address.
-
static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
Enable/Disable Slave.
- Parameters:
base – The I3C peripheral base address.
isEnable – Enable or disable.
-
static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)
Gets the I3C slave status flags.
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_slave_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C slave status flag state.
The following status register flags can be cleared:
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
Attempts to clear other flags has no effect.
See also
_i3c_slave_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags().
-
static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)
Gets the I3C slave error status flags.
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_i3c_slave_error_flags
- Parameters:
base – The I3C peripheral base address.
- Returns:
State of the error status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
Clears the I3C slave error status flag state.
See also
_i3c_slave_error_flags.
- Parameters:
base – The I3C peripheral base address.
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags().
-
i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)
Gets the I3C slave state.
- Parameters:
base – The I3C peripheral base address.
- Returns:
I3C slave activity state, refer i3c_slave_activity_state_t.
-
status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)
-
static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
Enables the I3C slave interrupt requests.
Only below flags can be enabled as interrupts.
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
Disables the I3C slave interrupt requests.
Only below flags can be disabled as interrupts.
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag
- Parameters:
base – The I3C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)
Returns the set of currently enabled I3C slave interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.
-
static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
Returns the set of pending I3C slave interrupt requests.
- Parameters:
base – The I3C peripheral base address.
- Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts.
-
static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
Enables or disables I3C slave DMA requests.
- Parameters:
base – The I3C peripheral base address.
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.
width – DMA read/write unit in bytes.
-
static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C slave transmit data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Slave Transmit Data Register address.
-
static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
Gets I3C slave receive data register address for DMA transfer.
- Parameters:
base – The I3C peripheral base address.
width – DMA read/write unit in bytes.
- Returns:
The I3C Slave Receive Data Register address.
-
static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
Sets the watermarks for I3C slave FIFOs.
- Parameters:
base – The I3C peripheral base address.
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
-
static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
Gets the current number of bytes in the I3C slave FIFOs.
- Parameters:
base – The I3C peripheral base address.
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.
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status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)
Performs a polling send transfer on the I3C bus.
- Parameters:
base – The I3C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
- Returns:
Error or success status returned by API.
-
status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)
Performs a polling receive transfer on the I3C bus.
- Parameters:
base – The I3C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
- Returns:
Error or success status returned by API.
-
void I3C_SlaveTransferCreateHandle(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_callback_t callback, void *userData)
Creates a new handle for the I3C slave non-blocking APIs.
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.
Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.
- Parameters:
base – The I3C peripheral base address.
handle – [out] Pointer to the I3C slave driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
-
status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask)
Starts accepting slave transfers.
Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i3c_slave_transfer_event_t enumerators for the events you wish to receive. The kI3C_SlaveTransmitEvent and kI3C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI3C_SlaveAllEvents constant is provided as a convenient way to enable all events.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI3C_SlaveAllEvents to enable all events.
- Return values:
kStatus_Success – Slave transfers were successfully started.
kStatus_I3C_Busy – Slave transfers have already been started on this handle.
-
status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count)
Gets the slave transfer status during a non-blocking transfer.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to i2c_slave_handle_t structure.
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress –
-
void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle)
Aborts the slave non-blocking transfers.
Note
This API could be called at any time to stop slave for handling the bus events.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
- Return values:
kStatus_Success –
kStatus_I3C_Idle –
-
void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)
Reusable routine to handle slave interrupts.
Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The I3C peripheral base address.
intHandle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
-
enum _i3c_slave_flags
I3C slave peripheral flags.
The following status register flags can be cleared:
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
Only below flags can be enabled as interrupts.
kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag
Note
These enums are meant to be OR’d together to form a bit mask.
Values:
-
enumerator kI3C_SlaveNotStopFlag
Slave status not stop flag
-
enumerator kI3C_SlaveMessageFlag
Slave status message, indicating slave is listening to the bus traffic or responding
-
enumerator kI3C_SlaveRequiredReadFlag
Slave status required, either is master doing SDR read from slave, or is IBI pushing out.
-
enumerator kI3C_SlaveRequiredWriteFlag
Slave status request write, master is doing SDR write to slave, except slave in ENTDAA mode
-
enumerator kI3C_SlaveBusDAAFlag
I3C bus is in ENTDAA mode
-
enumerator kI3C_SlaveBusHDRModeFlag
I3C bus is in HDR mode
-
enumerator kI3C_SlaveBusStartFlag
Start/Re-start event is seen since the bus was last cleared
-
enumerator kI3C_SlaveMatchedFlag
Slave address(dynamic/static) matched since last cleared
-
enumerator kI3C_SlaveBusStopFlag
Stop event is seen since the bus was last cleared
-
enumerator kI3C_SlaveRxReadyFlag
Rx data ready in rx buffer flag
-
enumerator kI3C_SlaveTxReadyFlag
Tx buffer ready for Tx data flag
-
enumerator kI3C_SlaveDynamicAddrChangedFlag
Slave dynamic address has been assigned, re-assigned, or lost
-
enumerator kI3C_SlaveReceivedCCCFlag
Slave received Common command code
-
enumerator kI3C_SlaveErrorFlag
Error occurred flag
-
enumerator kI3C_SlaveHDRCommandMatchFlag
High data rate command match
-
enumerator kI3C_SlaveCCCHandledFlag
Slave received Common command code is handled by I3C module
-
enumerator kI3C_SlaveEventSentFlag
Slave IBI/P2P/MR/HJ event has been sent
-
enumerator kI3C_SlaveIbiDisableFlag
Slave in band interrupt is disabled.
-
enumerator kI3C_SlaveMasterRequestDisabledFlag
Slave master request is disabled.
-
enumerator kI3C_SlaveHotJoinDisabledFlag
Slave Hot-Join is disabled.
-
enumerator kI3C_SlaveClearFlags
All flags which are cleared by the driver upon starting a transfer.
-
enumerator kI3C_SlaveAllIrqFlags
-
enum _i3c_slave_error_flags
I3C slave error flags to indicate the causes.
Note
These enums are meant to be OR’d together to form a bit mask.
Values:
-
enumerator kI3C_SlaveErrorOverrunFlag
Slave internal from-bus buffer/FIFO overrun.
-
enumerator kI3C_SlaveErrorUnderrunFlag
Slave internal to-bus buffer/FIFO underrun
-
enumerator kI3C_SlaveErrorUnderrunNakFlag
Slave internal from-bus buffer/FIFO underrun and NACK error
-
enumerator kI3C_SlaveErrorTermFlag
Terminate error from master
-
enumerator kI3C_SlaveErrorInvalidStartFlag
Slave invalid start flag
-
enumerator kI3C_SlaveErrorSdrParityFlag
SDR parity error
-
enumerator kI3C_SlaveErrorHdrParityFlag
HDR parity error
-
enumerator kI3C_SlaveErrorHdrCRCFlag
HDR-DDR CRC error
-
enumerator kI3C_SlaveErrorS0S1Flag
S0 or S1 error
-
enumerator kI3C_SlaveErrorOverreadFlag
Over-read error
-
enumerator kI3C_SlaveErrorOverwriteFlag
Over-write error
-
enumerator kI3C_SlaveErrorOverrunFlag
-
enum _i3c_slave_event
I3C slave.event.
Values:
-
enumerator kI3C_SlaveEventNormal
Normal mode.
-
enumerator kI3C_SlaveEventIBI
In band interrupt event.
-
enumerator kI3C_SlaveEventMasterReq
Master request event.
-
enumerator kI3C_SlaveEventHotJoinReq
Hot-join event.
-
enumerator kI3C_SlaveEventNormal
-
enum _i3c_slave_activity_state
I3C slave.activity state.
Values:
-
enumerator kI3C_SlaveNoLatency
Normal bus operation
-
enumerator kI3C_SlaveLatency1Ms
1ms of latency.
-
enumerator kI3C_SlaveLatency100Ms
100ms of latency.
-
enumerator kI3C_SlaveLatency10S
10s latency.
-
enumerator kI3C_SlaveNoLatency
-
enum _i3c_slave_transfer_event
Set of events sent to the callback for non blocking slave transfers.
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.
Note
These enumerations are meant to be OR’d together to form a bit mask of events.
Values:
-
enumerator kI3C_SlaveAddressMatchEvent
Received the slave address after a start or repeated start.
-
enumerator kI3C_SlaveTransmitEvent
Callback is requested to provide data to transmit (slave-transmitter role).
-
enumerator kI3C_SlaveReceiveEvent
Callback is requested to provide a buffer in which to place received data (slave-receiver role).
-
enumerator kI3C_SlaveRequiredTransmitEvent
Callback is requested to provide a buffer in which to place received data (slave-receiver role).
-
enumerator kI3C_SlaveStartEvent
A start/repeated start was detected.
-
enumerator kI3C_SlaveHDRCommandMatchEvent
Slave Match HDR Command.
-
enumerator kI3C_SlaveCompletionEvent
A stop was detected, completing the transfer.
-
enumerator kI3C_SlaveRequestSentEvent
Slave request event sent.
-
enumerator kI3C_SlaveReceivedCCCEvent
Slave received CCC event, need to handle by application.
-
enumerator kI3C_SlaveAllEvents
Bit mask of all available events.
-
enumerator kI3C_SlaveAddressMatchEvent
-
typedef enum _i3c_slave_event i3c_slave_event_t
I3C slave.event.
-
typedef enum _i3c_slave_activity_state i3c_slave_activity_state_t
I3C slave.activity state.
-
typedef struct _i3c_slave_config i3c_slave_config_t
Structure with settings to initialize the I3C slave module.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
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typedef enum _i3c_slave_transfer_event i3c_slave_transfer_event_t
Set of events sent to the callback for non blocking slave transfers.
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.
Note
These enumerations are meant to be OR’d together to form a bit mask of events.
-
typedef struct _i3c_slave_transfer i3c_slave_transfer_t
I3C slave transfer structure.
-
typedef struct _i3c_slave_handle i3c_slave_handle_t
-
typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData)
Slave event callback function pointer type.
This callback is used only for the slave non-blocking transfer API. To install a callback, use the I3C_SlaveSetCallback() function after you have created a handle.
- Param base:
Base address for the I3C instance on which the event occurred.
- Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback.
- Param userData:
Arbitrary pointer-sized value passed from the application.
-
typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle)
Typedef for slave interrupt handler.
-
struct _i3c_slave_config
- #include <fsl_i3c.h>
Structure with settings to initialize the I3C slave module.
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
Public Members
-
bool enableSlave
Whether to enable slave.
-
uint8_t staticAddr
Static address.
-
uint16_t vendorID
Device vendor ID(manufacture ID).
-
uint32_t partNumber
Device part number info
-
uint8_t dcr
Device characteristics register information.
-
uint8_t bcr
Bus characteristics register information.
-
uint8_t hdrMode
Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t.
-
bool nakAllRequest
Whether to reply NAK to all requests except broadcast CCC.
-
bool ignoreS0S1Error
Whether to ignore S0/S1 error in SDR mode.
-
bool offline
Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely.
-
bool matchSlaveStartStop
Whether to assert start/stop status only the time slave is addressed.
-
uint32_t maxWriteLength
Maximum write length.
-
uint32_t maxReadLength
Maximum read length.
-
bool enableSlave
-
struct _i3c_slave_transfer
- #include <fsl_i3c.h>
I3C slave transfer structure.
Public Members
-
uint32_t event
Reason the callback is being invoked.
-
uint8_t *txData
Transfer buffer
-
size_t txDataSize
Transfer size
-
uint8_t *rxData
Transfer buffer
-
size_t rxDataSize
Transfer size
-
status_t completionStatus
Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent.
-
size_t transferredCount
Number of bytes actually transferred since start or last repeated start.
-
uint32_t event
-
struct _i3c_slave_handle
- #include <fsl_i3c.h>
I3C slave handle structure.
Note
The contents of this structure are private and subject to change.
Public Members
-
i3c_slave_transfer_t transfer
I3C slave transfer copy.
-
bool isBusy
Whether transfer is busy.
-
bool wasTransmit
Whether the last transfer was a transmit.
-
uint32_t eventMask
Mask of enabled events.
-
uint32_t transferredCount
Count of bytes transferred.
-
i3c_slave_transfer_callback_t callback
Callback function called at transfer event.
-
void *userData
Callback parameter passed to callback.
-
uint8_t txFifoSize
Tx Fifo size
-
i3c_slave_transfer_t transfer
I3C Slave DMA Driver
-
void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)
Create a new handle for the I3C slave DMA APIs.
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C slave driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function.
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function.
-
status_t I3C_SlaveTransferEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_transfer_t *transfer, uint32_t eventMask)
Prepares for a non-blocking DMA-based transaction on the I3C bus.
The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when there’s bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned with master application to ensure the transfer is executed as expected. Callback specified when the handle was created is invoked when the transaction has completed.
- Parameters:
base – The I3C peripheral base address.
handle – Pointer to the I3C slave driver handle.
transfer – The pointer to the transfer descriptor.
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. The transmit and receive events is not allowed to be enabled.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.
kStatus_Fail – The transaction can’t be set.
-
void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
Abort a slave edma non-blocking transfer in a early time.
- Parameters:
base – I3C peripheral base address
handle – pointer to i3c_slave_edma_handle_t structure
-
void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)
Reusable routine to handle slave interrupts.
Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The I3C peripheral base address.
i3cHandle – Pointer to the I3C slave DMA driver handle.
-
typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t
-
typedef struct _i3c_slave_edma_transfer i3c_slave_edma_transfer_t
I3C slave transfer structure.
-
typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData)
Slave event callback function pointer type.
This callback is used only for the slave DMA transfer API.
- Param base:
Base address for the I3C instance on which the event occurred.
- Param handle:
Pointer to slave DMA transfer handle.
- Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback.
- Param userData:
Arbitrary pointer-sized value passed from the application.
-
struct _i3c_slave_edma_transfer
- #include <fsl_i3c_edma.h>
I3C slave transfer structure.
Public Members
-
uint32_t event
Reason the callback is being invoked.
-
uint8_t *txData
Transfer buffer
-
size_t txDataSize
Transfer size
-
uint8_t *rxData
Transfer buffer
-
size_t rxDataSize
Transfer size
-
status_t completionStatus
Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent.
-
uint32_t event
-
struct _i3c_slave_edma_handle
- #include <fsl_i3c_edma.h>
I3C slave edma handle structure.
Note
The contents of this structure are private and subject to change.
Public Members
-
I3C_Type *base
I3C base pointer.
-
i3c_slave_edma_transfer_t transfer
I3C slave transfer copy.
-
bool isBusy
Whether transfer is busy.
-
bool wasTransmit
Whether the last transfer was a transmit.
-
uint32_t eventMask
Mask of enabled events.
-
i3c_slave_edma_callback_t callback
Callback function called at transfer event.
-
edma_handle_t *rxDmaHandle
Handle for receive DMA channel.
-
edma_handle_t *txDmaHandle
Handle for transmit DMA channel.
-
void *userData
Callback parameter passed to callback.
-
I3C_Type *base
Iee
-
FSL_IEE_DRIVER_VERSION
IEE driver version. Version 2.1.1.
Current version: 2.1.1
Change log:
Version 2.0.0
Initial version
Version 2.1.0
Add region lock function IEE_LockRegionConfig() and driver clock control
Version 2.1.1
Fixed MISRA issues.
Version 2.2.0
Add ELE (EdgeLock Enclave) key provisioning feature.
-
enum _iee_region
IEE region.
Values:
-
enumerator kIEE_Region0
IEE region 0
-
enumerator kIEE_Region1
IEE region 1
-
enumerator kIEE_Region2
IEE region 2
-
enumerator kIEE_Region3
IEE region 3
-
enumerator kIEE_Region4
IEE region 4
-
enumerator kIEE_Region5
IEE region 5
-
enumerator kIEE_Region6
IEE region 6
-
enumerator kIEE_Region7
IEE region 7
-
enumerator kIEE_Region0
-
enum _iee_aes_bypass
IEE AES enablement/bypass.
Values:
-
enumerator kIEE_AesUseMdField
AES encryption/decryption enabled
-
enumerator kIEE_AesBypass
AES encryption/decryption bypass
-
enumerator kIEE_AesUseMdField
-
enum _iee_aes_mode
IEE AES mode.
Values:
-
enumerator kIEE_ModeNone
AES NONE mode
-
enumerator kIEE_ModeAesXTS
AES XTS mode
-
enumerator kIEE_ModeAesCTRWAddress
AES CTR w address binding mode
-
enumerator kIEE_ModeAesCTRWOAddress
AES CTR w/o address binding mode
-
enumerator kIEE_ModeAesCTRkeystream
AES CTR keystream only
-
enumerator kIEE_ModeNone
-
enum _iee_aes_key_size
IEE AES key size.
Values:
-
enumerator kIEE_AesCTR128XTS256
AES 128 bits (CTR), 256 bits (XTS)
-
enumerator kIEE_AesCTR256XTS512
AES 256 bits (CTR), 512 bits (XTS)
-
enumerator kIEE_AesCTR128XTS256
-
enum _iee_aes_key_num
IEE AES key number.
Values:
-
enumerator kIEE_AesKey1
AES Key 1
-
enumerator kIEE_AesKey2
AES Key 2
-
enumerator kIEE_AesKey1
-
typedef enum _iee_region iee_region_t
IEE region.
-
typedef enum _iee_aes_bypass iee_aes_bypass_t
IEE AES enablement/bypass.
-
typedef enum _iee_aes_mode iee_aes_mode_t
IEE AES mode.
-
typedef enum _iee_aes_key_size iee_aes_key_size_t
IEE AES key size.
-
typedef enum _iee_aes_key_num iee_aes_key_num_t
IEE AES key number.
-
typedef struct _iee_config iee_config_t
IEE configuration structure.
-
void IEE_Init(IEE_Type *base)
Resets IEE module to factory default values.
This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared.
- Parameters:
base – IEER peripheral address.
-
void IEE_GetDefaultConfig(iee_config_t *config)
Loads default values to the IEE configuration structure.
Loads default values to the IEE region configuration structure. The default values are as follows.
config->bypass = kIEE_AesUseMdField; config->mode = kIEE_ModeNone; config->keySize = kIEE_AesCTR128XTS256; config->pageOffset = 0U;
- Parameters:
config – Configuration for the selected IEE region.
-
void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config)
Sets the IEE module according to the configuration structure.
This function configures IEE region according to configuration structure.
- Parameters:
base – IEE peripheral address.
region – Selection of the IEE region to be configured.
config – Configuration for the selected IEE region.
-
status_t IEE_SetRegionKey(IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize)
Sets the IEE module key.
This function sets specified AES key for the given region.
- Parameters:
base – IEE peripheral address.
region – Selection of the IEE region to be configured.
keyNum – Selection of AES KEY1 or KEY2.
key – AES key.
keySize – Size of AES key.
-
static inline uint32_t IEE_GetOffset(uint32_t addressIee, uint32_t addressMemory)
Computes IEE offset to be set for specifed memory location.
This function calculates offset that must be set for IEE region to access physical memory location.
- Parameters:
addressIee – Address of IEE peripheral.
addressMemory – Address of physical memory location.
-
void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region)
Lock the IEE region configuration.
This function locks IEE region registers for Key, Offset and Attribute. Only system reset can clear the Lock bit.
- Parameters:
base – IEE peripheral address.
region – Selection of the IEE region to be locked.
-
struct _iee_config
- #include <fsl_iee.h>
IEE configuration structure.
Public Members
-
iee_aes_bypass_t bypass
AES encryption/decryption bypass
-
iee_aes_mode_t mode
AES mode
-
iee_aes_key_size_t keySize
size of AES key
-
uint32_t pageOffset
Offset to physical memory location from IEE start address
-
iee_aes_bypass_t bypass
Ieer
-
FSL_IEE_APC_DRIVER_VERSION
IEE_APC driver version. Version 2.0.2.
Current version: 2.0.2
Change log:
Version 2.0.0
Initial version
Version 2.0.1
Fixed MISRA issues.
Version 2.0.2
Update to newer version of implementation in HW.
-
enum _iee_apc_region
APC IEE regions.
Values:
-
enumerator kIEE_APC_Region0
APC IEE region 0
-
enumerator kIEE_APC_Region1
APC IEE region 1
-
enumerator kIEE_APC_Region2
APC IEE region 2
-
enumerator kIEE_APC_Region3
APC IEE region 3
-
enumerator kIEE_APC_Region4
APC IEE region 4
-
enumerator kIEE_APC_Region5
APC IEE region 5
-
enumerator kIEE_APC_Region6
APC IEE region 6
-
enumerator kIEE_APC_Region7
APC IEE region 7
-
enumerator kIEE_APC_Region0
-
enum _apc_iee_domain
APC IEE domains.
Values:
-
enumerator kIEE_APC_Domain0
APC IEE region 0
-
enumerator kIEE_APC_Domain1
APC IEE region 1
-
enumerator kIEE_APC_Domain0
-
typedef enum _iee_apc_region iee_apc_region_t
APC IEE regions.
-
typedef enum _apc_iee_domain iee_apc_domain_t
APC IEE domains.
-
void IEE_APC_GlobalEnable(IEE_APC_Type *base)
Enable the APC IEE Region setting.
This function enables IOMUXC LPSR GPR and APC IEE for setting the region.
- Parameters:
base – APC IEE peripheral address.
-
void IEE_APC_GlobalDisable(IEE_APC_Type *base)
Disables the APC IEE Region setting.
This function disables IOMUXC LPSR GPR and APC IEE for setting the region.
- Parameters:
base – APC IEE peripheral address.
-
status_t IEE_APC_SetRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, uint32_t startAddr, uint32_t endAddr)
Sets the APC IEE Memory Region Descriptors.
This function configures APC IEE Memory Region Descriptor according to region configuration structure.
- Parameters:
base – APC IEE peripheral address.
region – Selection of the APC IEE region to be configured.
startAddr – Start encryption adress for the selected APC IEE region.
endAddr – End encryption adress for the selected APC IEE region.
-
status_t IEE_APC_LockRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, iee_apc_domain_t domain)
Lock the LPSR GPR and APC IEE configuration.
This function locks writting to IOMUXC LPSR GPR and APC IEE encryption region setting registers. Only system reset can clear the LPSR GPR and APC IEE-RDC_D0/1 Lock bit
- Parameters:
base – APC IEE peripheral address.
region – Selection of the APC IEE region to be locked.
domain – Core domain ID
-
void IEE_APC_RegionEnable(IEE_APC_Type *base, iee_apc_region_t region)
Enable the IEE encryption/decryption and can lock this setting.
This function enables encryption/decryption by writting to IOMUXC LPSR GPR.
- Parameters:
base – APC IEE peripheral address.
region – Selection of the APC IEE region to be enabled.
IOMUXC: IOMUX Controller
-
enum _iomuxc_mqs_pwm_oversample_rate
Values:
-
enumerator kIOMUXC_MqsPwmOverSampleRate32
-
enumerator kIOMUXC_MqsPwmOverSampleRate64
-
enumerator kIOMUXC_MqsPwmOverSampleRate32
-
typedef enum _iomuxc_mqs_pwm_oversample_rate iomuxc_mqs_pwm_oversample_rate_t
-
IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
-
IOMUXC_GPIO_EMC_B1_00_XBAR1_XBAR_INOUT04
-
IOMUXC_GPIO_EMC_B1_00_SINC3_MOD_CLK0
-
IOMUXC_GPIO_EMC_B1_00_LPUART3_CTS_B
-
IOMUXC_GPIO_EMC_B1_00_NETC_PINMUX_ETH3_TXD03
-
IOMUXC_GPIO_EMC_B1_00_GPIO2_IO00
-
IOMUXC_GPIO_EMC_B1_00_KPP_ROW03
-
IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00
-
IOMUXC_GPIO_EMC_B1_00_NETC_PINMUX_ETH4_TXD03
-
IOMUXC_GPIO_EMC_B1_00_ECAT_TX_DATA3_0
-
IOMUXC_GPIO_EMC_B1_00_AHB_SRAMC_DATA00
-
IOMUXC_GPIO_EMC_B1_01_ECAT_TX_DATA2_0
-
IOMUXC_GPIO_EMC_B1_01_AHB_SRAMC_DATA01
-
IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
-
IOMUXC_GPIO_EMC_B1_01_XBAR1_XBAR_INOUT05
-
IOMUXC_GPIO_EMC_B1_01_SINC3_MOD_CLK1
-
IOMUXC_GPIO_EMC_B1_01_LPUART3_RTS_B
-
IOMUXC_GPIO_EMC_B1_01_NETC_PINMUX_ETH3_TXD02
-
IOMUXC_GPIO_EMC_B1_01_GPIO2_IO01
-
IOMUXC_GPIO_EMC_B1_01_KPP_COL03
-
IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01
-
IOMUXC_GPIO_EMC_B1_01_NETC_PINMUX_ETH4_TXD02
-
IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
-
IOMUXC_GPIO_EMC_B1_02_XBAR1_XBAR_INOUT06
-
IOMUXC_GPIO_EMC_B1_02_SINC3_MOD_CLK2
-
IOMUXC_GPIO_EMC_B1_02_LPUART3_RX
-
IOMUXC_GPIO_EMC_B1_02_NETC_PINMUX_ETH3_RX_CLK
-
IOMUXC_GPIO_EMC_B1_02_GPIO2_IO02
-
IOMUXC_GPIO_EMC_B1_02_KPP_ROW02
-
IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02
-
IOMUXC_GPIO_EMC_B1_02_NETC_PINMUX_ETH4_RX_CLK
-
IOMUXC_GPIO_EMC_B1_02_ECAT_RX_CLK_0
-
IOMUXC_GPIO_EMC_B1_02_AHB_SRAMC_DATA02
-
IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
-
IOMUXC_GPIO_EMC_B1_03_XBAR1_XBAR_INOUT07
-
IOMUXC_GPIO_EMC_B1_03_SINC3_EMCLK00
-
IOMUXC_GPIO_EMC_B1_03_LPUART3_TX
-
IOMUXC_GPIO_EMC_B1_03_NETC_PINMUX_ETH3_RXD03
-
IOMUXC_GPIO_EMC_B1_03_GPIO2_IO03
-
IOMUXC_GPIO_EMC_B1_03_KPP_COL02
-
IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03
-
IOMUXC_GPIO_EMC_B1_03_NETC_PINMUX_ETH4_RXD03
-
IOMUXC_GPIO_EMC_B1_03_ECAT_RX_DATA3_0
-
IOMUXC_GPIO_EMC_B1_03_AHB_SRAMC_DATA03
-
IOMUXC_GPIO_EMC_B1_04_ECAT_RX_DATA2_0
-
IOMUXC_GPIO_EMC_B1_04_AHB_SRAMC_DATA04
-
IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
-
IOMUXC_GPIO_EMC_B1_04_XBAR1_XBAR_INOUT08
-
IOMUXC_GPIO_EMC_B1_04_SINC3_EMBIT00
-
IOMUXC_GPIO_EMC_B1_04_LPUART3_DSR_B
-
IOMUXC_GPIO_EMC_B1_04_NETC_PINMUX_ETH3_RXD02
-
IOMUXC_GPIO_EMC_B1_04_GPIO2_IO04
-
IOMUXC_GPIO_EMC_B1_04_KPP_ROW01
-
IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04
-
IOMUXC_GPIO_EMC_B1_04_NETC_PINMUX_ETH4_RXD02
-
IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
-
IOMUXC_GPIO_EMC_B1_05_XBAR1_XBAR_INOUT09
-
IOMUXC_GPIO_EMC_B1_05_SINC3_EMCLK01
-
IOMUXC_GPIO_EMC_B1_05_LPUART3_DCD_B
-
IOMUXC_GPIO_EMC_B1_05_NETC_PINMUX_ETH3_TXD00
-
IOMUXC_GPIO_EMC_B1_05_GPIO2_IO05
-
IOMUXC_GPIO_EMC_B1_05_KPP_ROW07
-
IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05
-
IOMUXC_GPIO_EMC_B1_05_NETC_PINMUX_ETH4_TXD00
-
IOMUXC_GPIO_EMC_B1_05_ECAT_TX_DATA0_0
-
IOMUXC_GPIO_EMC_B1_05_AHB_SRAMC_DATA05
-
IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
-
IOMUXC_GPIO_EMC_B1_06_FLEXPWM4_PWMB03
-
IOMUXC_GPIO_EMC_B1_06_SINC3_EMBIT01
-
IOMUXC_GPIO_EMC_B1_06_LPUART3_RI_B
-
IOMUXC_GPIO_EMC_B1_06_NETC_PINMUX_ETH3_TXD01
-
IOMUXC_GPIO_EMC_B1_06_GPIO2_IO06
-
IOMUXC_GPIO_EMC_B1_06_KPP_COL07
-
IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06
-
IOMUXC_GPIO_EMC_B1_06_NETC_PINMUX_ETH4_TXD01
-
IOMUXC_GPIO_EMC_B1_06_ECAT_TX_DATA1_0
-
IOMUXC_GPIO_EMC_B1_06_AHB_SRAMC_DATA06
-
IOMUXC_GPIO_EMC_B1_07_ECAT_TX_EN_0
-
IOMUXC_GPIO_EMC_B1_07_AHB_SRAMC_DATA07
-
IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
-
IOMUXC_GPIO_EMC_B1_07_FLEXPWM4_PWMA03
-
IOMUXC_GPIO_EMC_B1_07_SINC3_EMCLK02
-
IOMUXC_GPIO_EMC_B1_07_LPUART3_DTR_B
-
IOMUXC_GPIO_EMC_B1_07_NETC_PINMUX_ETH3_TX_EN
-
IOMUXC_GPIO_EMC_B1_07_GPIO2_IO07
-
IOMUXC_GPIO_EMC_B1_07_KPP_ROW06
-
IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07
-
IOMUXC_GPIO_EMC_B1_07_NETC_PINMUX_ETH4_TX_EN
-
IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
-
IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWMB03
-
IOMUXC_GPIO_EMC_B1_08_SINC3_EMBIT02
-
IOMUXC_GPIO_EMC_B1_08_LPUART4_DSR_B
-
IOMUXC_GPIO_EMC_B1_08_NETC_PINMUX_ETH3_TX_CLK
-
IOMUXC_GPIO_EMC_B1_08_GPIO2_IO08
-
IOMUXC_GPIO_EMC_B1_08_KPP_COL06
-
IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08
-
IOMUXC_GPIO_EMC_B1_08_NETC_PINMUX_ETH4_TX_CLK
-
IOMUXC_GPIO_EMC_B1_08_ECAT_TX_CLK_0
-
IOMUXC_GPIO_EMC_B1_08_AHB_SRAMC_LBB
-
IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
-
IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWMA03
-
IOMUXC_GPIO_EMC_B1_09_SINC3_EMCLK03
-
IOMUXC_GPIO_EMC_B1_09_LPUART4_DCD_B
-
IOMUXC_GPIO_EMC_B1_09_NETC_PINMUX_ETH3_RXD00
-
IOMUXC_GPIO_EMC_B1_09_GPIO2_IO09
-
IOMUXC_GPIO_EMC_B1_09_KPP_ROW05
-
IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09
-
IOMUXC_GPIO_EMC_B1_09_NETC_PINMUX_ETH4_RXD00
-
IOMUXC_GPIO_EMC_B1_09_ECAT_RX_DATA0_0
-
IOMUXC_GPIO_EMC_B1_09_AHB_SRAMC_ADDR00
-
IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
-
IOMUXC_GPIO_EMC_B1_10_FLEXPWM3_PWMB03
-
IOMUXC_GPIO_EMC_B1_10_SINC3_EMBIT03
-
IOMUXC_GPIO_EMC_B1_10_LPUART4_RI_B
-
IOMUXC_GPIO_EMC_B1_10_NETC_PINMUX_ETH3_RXD01
-
IOMUXC_GPIO_EMC_B1_10_GPIO2_IO10
-
IOMUXC_GPIO_EMC_B1_10_KPP_COL05
-
IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10
-
IOMUXC_GPIO_EMC_B1_10_NETC_PINMUX_ETH4_RXD01
-
IOMUXC_GPIO_EMC_B1_10_ECAT_RX_DATA1_0
-
IOMUXC_GPIO_EMC_B1_10_AHB_SRAMC_ADDR01
-
IOMUXC_GPIO_EMC_B1_11_ECAT_RX_DV_0
-
IOMUXC_GPIO_EMC_B1_11_AHB_SRAMC_ADDR02
-
IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
-
IOMUXC_GPIO_EMC_B1_11_FLEXPWM3_PWMA03
-
IOMUXC_GPIO_EMC_B1_11_SINC_FILTER_GLUE3_BREAK
-
IOMUXC_GPIO_EMC_B1_11_LPUART4_DTR_B
-
IOMUXC_GPIO_EMC_B1_11_NETC_PINMUX_ETH3_RX_DV
-
IOMUXC_GPIO_EMC_B1_11_GPIO2_IO11
-
IOMUXC_GPIO_EMC_B1_11_KPP_ROW04
-
IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11
-
IOMUXC_GPIO_EMC_B1_11_NETC_PINMUX_ETH4_RX_DV
-
IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
-
IOMUXC_GPIO_EMC_B1_12_FLEXPWM4_PWMA00
-
IOMUXC_GPIO_EMC_B1_12_LPUART4_TX
-
IOMUXC_GPIO_EMC_B1_12_NETC_PINMUX_ETH3_RX_ER
-
IOMUXC_GPIO_EMC_B1_12_GPIO2_IO12
-
IOMUXC_GPIO_EMC_B1_12_KPP_COL04
-
IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12
-
IOMUXC_GPIO_EMC_B1_12_NETC_PINMUX_ETH4_RX_ER
-
IOMUXC_GPIO_EMC_B1_12_ECAT_PT0_RX_ER
-
IOMUXC_GPIO_EMC_B1_12_AHB_SRAMC_ADDR03
-
IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
-
IOMUXC_GPIO_EMC_B1_13_FLEXPWM4_PWMB00
-
IOMUXC_GPIO_EMC_B1_13_LPUART4_RX
-
IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH2_RX_DV
-
IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH3_TX_ER
-
IOMUXC_GPIO_EMC_B1_13_GPIO2_IO13
-
IOMUXC_GPIO_EMC_B1_13_KPP_COL01
-
IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13
-
IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH4_TX_ER
-
IOMUXC_GPIO_EMC_B1_13_QTIMER1_TIMER1
-
IOMUXC_GPIO_EMC_B1_13_AHB_SRAMC_ADDR04
-
IOMUXC_GPIO_EMC_B1_14_LPUART4_CTS_B
-
IOMUXC_GPIO_EMC_B1_14_AHB_SRAMC_ADDR05
-
IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
-
IOMUXC_GPIO_EMC_B1_14_FLEXPWM4_PWMA01
-
IOMUXC_GPIO_EMC_B1_14_LPUART5_TX
-
IOMUXC_GPIO_EMC_B1_14_NETC_PINMUX_ETH2_TX_EN
-
IOMUXC_GPIO_EMC_B1_14_NETC_ETH3_CRS
-
IOMUXC_GPIO_EMC_B1_14_GPIO2_IO14
-
IOMUXC_GPIO_EMC_B1_14_KPP_ROW00
-
IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14
-
IOMUXC_GPIO_EMC_B1_14_NETC_ETH4_CRS
-
IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
-
IOMUXC_GPIO_EMC_B1_15_FLEXPWM4_PWMB01
-
IOMUXC_GPIO_EMC_B1_15_LPUART5_RX
-
IOMUXC_GPIO_EMC_B1_15_NETC_PINMUX_ETH2_TX_CLK
-
IOMUXC_GPIO_EMC_B1_15_NETC_ETH3_COL
-
IOMUXC_GPIO_EMC_B1_15_GPIO2_IO15
-
IOMUXC_GPIO_EMC_B1_15_KPP_COL00
-
IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15
-
IOMUXC_GPIO_EMC_B1_15_NETC_ETH4_COL
-
IOMUXC_GPIO_EMC_B1_15_LPUART4_RTS_B
-
IOMUXC_GPIO_EMC_B1_15_AHB_SRAMC_ADDR06
-
IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
-
IOMUXC_GPIO_EMC_B1_16_FLEXPWM4_PWMB02
-
IOMUXC_GPIO_EMC_B1_16_LPUART9_TX
-
IOMUXC_GPIO_EMC_B1_16_NETC_PINMUX_ETH2_RXD00
-
IOMUXC_GPIO_EMC_B1_16_NETC_ETH3_SLV_MDC
-
IOMUXC_GPIO_EMC_B1_16_GPIO2_IO16
-
IOMUXC_GPIO_EMC_B1_16_NETC_ETH4_SLV_MDC
-
IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16
-
IOMUXC_GPIO_EMC_B1_16_NETC_ETH2_SLV_MDC
-
IOMUXC_GPIO_EMC_B1_16_LPSPI6_PCS2
-
IOMUXC_GPIO_EMC_B1_16_AHB_SRAMC_ADDR07
-
IOMUXC_GPIO_EMC_B1_17_LPSPI6_PCS1
-
IOMUXC_GPIO_EMC_B1_17_AHB_SRAMC_ADDR08
-
IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
-
IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWMA02
-
IOMUXC_GPIO_EMC_B1_17_LPUART9_RX
-
IOMUXC_GPIO_EMC_B1_17_NETC_PINMUX_ETH2_RXD01
-
IOMUXC_GPIO_EMC_B1_17_NETC_ETH3_SLV_MDIO
-
IOMUXC_GPIO_EMC_B1_17_GPIO2_IO17
-
IOMUXC_GPIO_EMC_B1_17_NETC_ETH4_SLV_MDIO
-
IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17
-
IOMUXC_GPIO_EMC_B1_17_NETC_ETH2_SLV_MDIO
-
IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
-
IOMUXC_GPIO_EMC_B1_18_FLEXPWM2_PWMA00
-
IOMUXC_GPIO_EMC_B1_18_QTIMER1_TIMER0
-
IOMUXC_GPIO_EMC_B1_18_LPSPI6_SCK
-
IOMUXC_GPIO_EMC_B1_18_NETC_ETH2_CRS
-
IOMUXC_GPIO_EMC_B1_18_GPIO2_IO18
-
IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18
-
IOMUXC_GPIO_EMC_B1_18_NETC_EMDC
-
IOMUXC_GPIO_EMC_B1_18_AHB_SRAMC_ADDR09
-
IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
-
IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWMB00
-
IOMUXC_GPIO_EMC_B1_19_QTIMER2_TIMER0
-
IOMUXC_GPIO_EMC_B1_19_LPSPI6_SDI
-
IOMUXC_GPIO_EMC_B1_19_NETC_ETH2_COL
-
IOMUXC_GPIO_EMC_B1_19_GPIO2_IO19
-
IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19
-
IOMUXC_GPIO_EMC_B1_19_NETC_EMDIO
-
IOMUXC_GPIO_EMC_B1_19_AHB_SRAMC_ADDR11
-
IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
-
IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWMA01
-
IOMUXC_GPIO_EMC_B1_20_QTIMER3_TIMER0
-
IOMUXC_GPIO_EMC_B1_20_LPSPI6_SDO
-
IOMUXC_GPIO_EMC_B1_20_NETC_PINMUX_ETH2_TX_ER
-
IOMUXC_GPIO_EMC_B1_20_GPIO2_IO20
-
IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20
-
IOMUXC_GPIO_EMC_B1_20_AHB_SRAMC_ADDR12
-
IOMUXC_GPIO_EMC_B1_21_FLEXSPI2_BUS2BIT_B_DQS
-
IOMUXC_GPIO_EMC_B1_21_AHB_SRAMC_ADDR13
-
IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
-
IOMUXC_GPIO_EMC_B1_21_FLEXPWM2_PWMB01
-
IOMUXC_GPIO_EMC_B1_21_QTIMER4_TIMER0
-
IOMUXC_GPIO_EMC_B1_21_LPSPI6_PCS0
-
IOMUXC_GPIO_EMC_B1_21_NETC_PINMUX_ETH2_RX_CLK
-
IOMUXC_GPIO_EMC_B1_21_GPIO2_IO21
-
IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21
-
IOMUXC_GPIO_EMC_B1_21_LPUART4_CTS_B
-
IOMUXC_GPIO_EMC_B1_22_FLEXSPI2_BUS2BIT_B_DATA03
-
IOMUXC_GPIO_EMC_B1_22_AHB_SRAMC_ADDR14
-
IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
-
IOMUXC_GPIO_EMC_B1_22_FLEXPWM2_PWMB02
-
IOMUXC_GPIO_EMC_B1_22_QTIMER5_TIMER0
-
IOMUXC_GPIO_EMC_B1_22_LPSPI4_SCK
-
IOMUXC_GPIO_EMC_B1_22_NETC_PINMUX_ETH2_RXD02
-
IOMUXC_GPIO_EMC_B1_22_GPIO2_IO22
-
IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22
-
IOMUXC_GPIO_EMC_B1_22_LPUART4_RTS_B
-
IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
-
IOMUXC_GPIO_EMC_B1_23_FLEXPWM2_PWMA02
-
IOMUXC_GPIO_EMC_B1_23_QTIMER6_TIMER0
-
IOMUXC_GPIO_EMC_B1_23_LPSPI4_SDI
-
IOMUXC_GPIO_EMC_B1_23_NETC_PINMUX_ETH2_RXD03
-
IOMUXC_GPIO_EMC_B1_23_GPIO2_IO23
-
IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23
-
IOMUXC_GPIO_EMC_B1_23_FLEXSPI2_BUS2BIT_B_DATA02
-
IOMUXC_GPIO_EMC_B1_23_AHB_SRAMC_ADDR10
-
IOMUXC_GPIO_EMC_B1_24_FLEXSPI2_BUS2BIT_B_DATA01
-
IOMUXC_GPIO_EMC_B1_24_AHB_SRAMC_ADDR15
-
IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
-
IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWMA00
-
IOMUXC_GPIO_EMC_B1_24_QTIMER7_TIMER0
-
IOMUXC_GPIO_EMC_B1_24_LPSPI4_SDO
-
IOMUXC_GPIO_EMC_B1_24_NETC_PINMUX_ETH2_TXD03
-
IOMUXC_GPIO_EMC_B1_24_GPIO2_IO24
-
IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24
-
IOMUXC_GPIO_EMC_B1_24_NETC_ETH3_SLV_MDC
-
IOMUXC_GPIO_EMC_B1_25_FLEXSPI2_BUS2BIT_B_DATA00
-
IOMUXC_GPIO_EMC_B1_25_AHB_SRAMC_ADDR16
-
IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
-
IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWMB00
-
IOMUXC_GPIO_EMC_B1_25_QTIMER8_TIMER0
-
IOMUXC_GPIO_EMC_B1_25_LPSPI4_PCS0
-
IOMUXC_GPIO_EMC_B1_25_NETC_PINMUX_ETH2_TXD02
-
IOMUXC_GPIO_EMC_B1_25_GPIO2_IO25
-
IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25
-
IOMUXC_GPIO_EMC_B1_25_NETC_ETH3_SLV_MDIO
-
IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
-
IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWMA01
-
IOMUXC_GPIO_EMC_B1_26_XBAR1_XBAR_INOUT10
-
IOMUXC_GPIO_EMC_B1_26_FLEXSPI2_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_EMC_B1_26_NETC_PINMUX_ETH2_TXD01
-
IOMUXC_GPIO_EMC_B1_26_GPIO2_IO26
-
IOMUXC_GPIO_EMC_B1_26_ECAT_TX_DATA1_1
-
IOMUXC_GPIO_EMC_B1_26_LPSPI6_SCK
-
IOMUXC_GPIO_EMC_B1_26_AHB_SRAMC_WE
-
IOMUXC_GPIO_EMC_B1_27_LPSPI6_SDI
-
IOMUXC_GPIO_EMC_B1_27_AHB_SRAMC_OEB
-
IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
-
IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWMB01
-
IOMUXC_GPIO_EMC_B1_27_XBAR1_XBAR_INOUT11
-
IOMUXC_GPIO_EMC_B1_27_FLEXSPI2_BUS2BIT_B_SS1_B
-
IOMUXC_GPIO_EMC_B1_27_NETC_PINMUX_ETH2_TXD00
-
IOMUXC_GPIO_EMC_B1_27_GPIO2_IO27
-
IOMUXC_GPIO_EMC_B1_27_ECAT_TX_DATA0_1
-
IOMUXC_GPIO_EMC_B1_27_LPUART6_RI_B
-
IOMUXC_GPIO_EMC_B1_28_LPSPI6_SDO
-
IOMUXC_GPIO_EMC_B1_28_AHB_SRAMC_ADV
-
IOMUXC_GPIO_EMC_B1_28_SEMC_WE
-
IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWMB02
-
IOMUXC_GPIO_EMC_B1_28_XBAR1_XBAR_INOUT12
-
IOMUXC_GPIO_EMC_B1_28_FLEXSPI2_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_EMC_B1_28_NETC_PINMUX_ETH2_TX_EN
-
IOMUXC_GPIO_EMC_B1_28_GPIO2_IO28
-
IOMUXC_GPIO_EMC_B1_28_ECAT_TX_EN_1
-
IOMUXC_GPIO_EMC_B1_28_LPUART6_DTR_B
-
IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
-
IOMUXC_GPIO_EMC_B1_29_FLEXPWM1_PWMA02
-
IOMUXC_GPIO_EMC_B1_29_XBAR1_XBAR_INOUT13
-
IOMUXC_GPIO_EMC_B1_29_FLEXSPI2_BUS2BIT_B_DQS
-
IOMUXC_GPIO_EMC_B1_29_NETC_PINMUX_ETH2_TX_CLK
-
IOMUXC_GPIO_EMC_B1_29_GPIO2_IO29
-
IOMUXC_GPIO_EMC_B1_29_ECAT_TX_CLK_1
-
IOMUXC_GPIO_EMC_B1_29_LPUART6_DCD_B
-
IOMUXC_GPIO_EMC_B1_29_LPSPI6_PCS0
-
IOMUXC_GPIO_EMC_B1_29_AHB_SRAMC_CS0
-
IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
-
IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWMA00
-
IOMUXC_GPIO_EMC_B1_30_XBAR1_XBAR_INOUT14
-
IOMUXC_GPIO_EMC_B1_30_FLEXSPI2_BUS2BIT_B_DATA03
-
IOMUXC_GPIO_EMC_B1_30_NETC_PINMUX_ETH2_RXD00
-
IOMUXC_GPIO_EMC_B1_30_GPIO2_IO30
-
IOMUXC_GPIO_EMC_B1_30_ECAT_RX_DATA0_1
-
IOMUXC_GPIO_EMC_B1_30_LPUART6_DSR_B
-
IOMUXC_GPIO_EMC_B1_30_LPSPI6_PCS1
-
IOMUXC_GPIO_EMC_B1_30_AHB_SRAMC_DATA08
-
IOMUXC_GPIO_EMC_B1_31_LPSPI6_PCS2
-
IOMUXC_GPIO_EMC_B1_31_AHB_SRAMC_DATA09
-
IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
-
IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWMB00
-
IOMUXC_GPIO_EMC_B1_31_LPUART6_TX
-
IOMUXC_GPIO_EMC_B1_31_FLEXSPI2_BUS2BIT_B_DATA02
-
IOMUXC_GPIO_EMC_B1_31_NETC_PINMUX_ETH2_RXD01
-
IOMUXC_GPIO_EMC_B1_31_GPIO2_IO31
-
IOMUXC_GPIO_EMC_B1_31_ECAT_RX_DATA1_1
-
IOMUXC_GPIO_EMC_B1_31_LPSPI5_SCK
-
IOMUXC_GPIO_EMC_B1_32_LPSPI6_PCS3
-
IOMUXC_GPIO_EMC_B1_32_AHB_SRAMC_DATA10
-
IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
-
IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWMA01
-
IOMUXC_GPIO_EMC_B1_32_LPUART6_RX
-
IOMUXC_GPIO_EMC_B1_32_FLEXSPI2_BUS2BIT_B_DATA01
-
IOMUXC_GPIO_EMC_B1_32_NETC_PINMUX_ETH2_RX_DV
-
IOMUXC_GPIO_EMC_B1_32_GPIO3_IO00
-
IOMUXC_GPIO_EMC_B1_32_ECAT_RX_DV_1
-
IOMUXC_GPIO_EMC_B1_32_LPSPI5_SDO
-
IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
-
IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWMB01
-
IOMUXC_GPIO_EMC_B1_33_LPUART6_CTS_B
-
IOMUXC_GPIO_EMC_B1_33_FLEXSPI2_BUS2BIT_B_DATA00
-
IOMUXC_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_ER
-
IOMUXC_GPIO_EMC_B1_33_GPIO3_IO01
-
IOMUXC_GPIO_EMC_B1_33_ECAT_RX_ER_1
-
IOMUXC_GPIO_EMC_B1_33_LPSPI5_SDI
-
IOMUXC_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_CLK
-
IOMUXC_GPIO_EMC_B1_33_AHB_SRAMC_DATA11
-
IOMUXC_GPIO_EMC_B1_34_LPSPI5_PCS0
-
IOMUXC_GPIO_EMC_B1_34_AHB_SRAMC_DATA12
-
IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
-
IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWMB02
-
IOMUXC_GPIO_EMC_B1_34_LPUART6_RTS_B
-
IOMUXC_GPIO_EMC_B1_34_FLEXSPI2_BUS2BIT_B_SCLK
-
IOMUXC_GPIO_EMC_B1_34_NETC_PINMUX_ETH2_RXD02
-
IOMUXC_GPIO_EMC_B1_34_GPIO3_IO02
-
IOMUXC_GPIO_EMC_B1_34_ECAT_RX_DATA2_1
-
IOMUXC_GPIO_EMC_B1_34_NETC_PINMUX_ETH0_TXD00
-
IOMUXC_GPIO_EMC_B1_35_LPSPI5_PCS1
-
IOMUXC_GPIO_EMC_B1_35_AHB_SRAMC_DATA13
-
IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
-
IOMUXC_GPIO_EMC_B1_35_FLEXPWM3_PWMA02
-
IOMUXC_GPIO_EMC_B1_35_LPUART5_TX
-
IOMUXC_GPIO_EMC_B1_35_FLEXSPI2_BUS2BIT_A_DATA00
-
IOMUXC_GPIO_EMC_B1_35_NETC_PINMUX_ETH2_RXD03
-
IOMUXC_GPIO_EMC_B1_35_GPIO3_IO03
-
IOMUXC_GPIO_EMC_B1_35_ECAT_RX_DATA3_1
-
IOMUXC_GPIO_EMC_B1_35_NETC_PINMUX_ETH0_TXD01
-
IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
-
IOMUXC_GPIO_EMC_B1_36_FLEXPWM1_PWMA00
-
IOMUXC_GPIO_EMC_B1_36_LPUART5_RX
-
IOMUXC_GPIO_EMC_B1_36_FLEXSPI2_BUS2BIT_A_DATA01
-
IOMUXC_GPIO_EMC_B1_36_NETC_PINMUX_ETH2_TXD03
-
IOMUXC_GPIO_EMC_B1_36_GPIO3_IO04
-
IOMUXC_GPIO_EMC_B1_36_ECAT_TX_DATA3_1
-
IOMUXC_GPIO_EMC_B1_36_NETC_PINMUX_ETH0_TX_EN
-
IOMUXC_GPIO_EMC_B1_36_AHB_SRAMC_DATA14
-
IOMUXC_GPIO_EMC_B1_37_AHB_SRAMC_DATA15
-
IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
-
IOMUXC_GPIO_EMC_B1_37_FLEXPWM1_PWMB00
-
IOMUXC_GPIO_EMC_B1_37_LPUART5_CTS_B
-
IOMUXC_GPIO_EMC_B1_37_FLEXSPI2_BUS2BIT_A_DATA02
-
IOMUXC_GPIO_EMC_B1_37_NETC_PINMUX_ETH2_TXD02
-
IOMUXC_GPIO_EMC_B1_37_GPIO3_IO05
-
IOMUXC_GPIO_EMC_B1_37_ECAT_TX_DATA2_1
-
IOMUXC_GPIO_EMC_B1_37_NETC_PINMUX_ETH0_TX_CLK
-
IOMUXC_GPIO_EMC_B1_38_AHB_SRAMC_UBB
-
IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
-
IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWMB03
-
IOMUXC_GPIO_EMC_B1_38_LPUART5_RTS_B
-
IOMUXC_GPIO_EMC_B1_38_FLEXSPI2_BUS2BIT_A_DATA03
-
IOMUXC_GPIO_EMC_B1_38_NETC_PINMUX_ETH2_RX_CLK
-
IOMUXC_GPIO_EMC_B1_38_GPIO3_IO06
-
IOMUXC_GPIO_EMC_B1_38_ECAT_RX_CLK_1
-
IOMUXC_GPIO_EMC_B1_38_NETC_PINMUX_ETH0_RXD00
-
IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
-
IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWMA03
-
IOMUXC_GPIO_EMC_B1_39_XBAR1_XBAR_INOUT15
-
IOMUXC_GPIO_EMC_B1_39_FLEXSPI2_BUS2BIT_A_SS0_B
-
IOMUXC_GPIO_EMC_B1_39_NETC_PINMUX_ETH2_TX_ER
-
IOMUXC_GPIO_EMC_B1_39_GPIO3_IO07
-
IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1
-
IOMUXC_GPIO_EMC_B1_39_NETC_PINMUX_ETH0_RXD01
-
IOMUXC_GPIO_EMC_B1_39_AHB_SRAMC_CS1
-
IOMUXC_GPIO_EMC_B1_40_SEMC_RDY
-
IOMUXC_GPIO_EMC_B1_40_NETC_EMDC
-
IOMUXC_GPIO_EMC_B1_40_NETC_ETH2_SLV_MDC
-
IOMUXC_GPIO_EMC_B1_40_FLEXSPI2_BUS2BIT_A_DQS
-
IOMUXC_GPIO_EMC_B1_40_NETC_ETH2_CRS
-
IOMUXC_GPIO_EMC_B1_40_GPIO3_IO08
-
IOMUXC_GPIO_EMC_B1_40_QTIMER3_TIMER1
-
IOMUXC_GPIO_EMC_B1_40_NETC_PINMUX_ETH0_RX_DV
-
IOMUXC_GPIO_EMC_B1_40_AHB_SRAMC_CS2
-
IOMUXC_GPIO_EMC_B1_41_AHB_SRAMC_CS3
-
IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00
-
IOMUXC_GPIO_EMC_B1_41_NETC_EMDIO
-
IOMUXC_GPIO_EMC_B1_41_NETC_ETH2_SLV_MDIO
-
IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_BUS2BIT_A_SCLK
-
IOMUXC_GPIO_EMC_B1_41_NETC_ETH2_COL
-
IOMUXC_GPIO_EMC_B1_41_GPIO3_IO09
-
IOMUXC_GPIO_EMC_B1_41_QTIMER4_TIMER1
-
IOMUXC_GPIO_EMC_B1_41_NETC_PINMUX_ETH0_RX_ER
-
IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
-
IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M
-
IOMUXC_GPIO_EMC_B2_00_QTIMER5_TIMER1
-
IOMUXC_GPIO_EMC_B2_00_NETC_EMDC
-
IOMUXC_GPIO_EMC_B2_00_NETC_PINMUX_ETH0_RX_CLK
-
IOMUXC_GPIO_EMC_B2_00_GPIO3_IO10
-
IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20
-
IOMUXC_GPIO_EMC_B2_00_LPSPI5_SCK
-
IOMUXC_GPIO_EMC_B2_00_LPI2C3_SCL
-
IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWMA00
-
IOMUXC_GPIO_EMC_B2_00_ECAT_RX_CLK_0
-
IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
-
IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B
-
IOMUXC_GPIO_EMC_B2_01_QTIMER6_TIMER1
-
IOMUXC_GPIO_EMC_B2_01_NETC_EMDIO
-
IOMUXC_GPIO_EMC_B2_01_NETC_PINMUX_ETH0_RXD02
-
IOMUXC_GPIO_EMC_B2_01_GPIO3_IO11
-
IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21
-
IOMUXC_GPIO_EMC_B2_01_LPSPI5_PCS0
-
IOMUXC_GPIO_EMC_B2_01_LPI2C3_SDA
-
IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWMB00
-
IOMUXC_GPIO_EMC_B2_01_ECAT_RX_DATA2_0
-
IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
-
IOMUXC_GPIO_EMC_B2_02_USDHC2_WP
-
IOMUXC_GPIO_EMC_B2_02_QTIMER7_TIMER1
-
IOMUXC_GPIO_EMC_B2_02_NETC_PINMUX_ETH0_RXD03
-
IOMUXC_GPIO_EMC_B2_02_GPIO3_IO12
-
IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22
-
IOMUXC_GPIO_EMC_B2_02_LPSPI5_SDO
-
IOMUXC_GPIO_EMC_B2_02_CCM_CLKO1
-
IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWMA01
-
IOMUXC_GPIO_EMC_B2_02_ECAT_RX_DATA3_0
-
IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
-
IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT
-
IOMUXC_GPIO_EMC_B2_03_QTIMER8_TIMER1
-
IOMUXC_GPIO_EMC_B2_03_NETC_PINMUX_ETH0_TXD02
-
IOMUXC_GPIO_EMC_B2_03_GPIO3_IO13
-
IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23
-
IOMUXC_GPIO_EMC_B2_03_LPSPI5_SDI
-
IOMUXC_GPIO_EMC_B2_03_NETC_ETH3_CRS
-
IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWMB01
-
IOMUXC_GPIO_EMC_B2_03_ECAT_TX_DATA2_0
-
IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
-
IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B
-
IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK
-
IOMUXC_GPIO_EMC_B2_04_NETC_PINMUX_ETH0_TXD03
-
IOMUXC_GPIO_EMC_B2_04_GPIO3_IO14
-
IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24
-
IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK
-
IOMUXC_GPIO_EMC_B2_04_NETC_ETH3_COL
-
IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWMB02
-
IOMUXC_GPIO_EMC_B2_04_ECAT_TX_DATA3_0
-
IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
-
IOMUXC_GPIO_EMC_B2_05_NETC_ETH4_SLV_MDC
-
IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC
-
IOMUXC_GPIO_EMC_B2_05_NETC_PINMUX_ETH0_TXD00
-
IOMUXC_GPIO_EMC_B2_05_NETC_ETH4_CRS
-
IOMUXC_GPIO_EMC_B2_05_GPIO3_IO15
-
IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25
-
IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0
-
IOMUXC_GPIO_EMC_B2_05_NETC_PINMUX_ETH3_TXD00
-
IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWMA02
-
IOMUXC_GPIO_EMC_B2_05_ECAT_TX_DATA0_0
-
IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
-
IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWMB03
-
IOMUXC_GPIO_EMC_B2_06_NETC_ETH4_SLV_MDIO
-
IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK
-
IOMUXC_GPIO_EMC_B2_06_ECAT_TX_DATA1_0
-
IOMUXC_GPIO_EMC_B2_06_NETC_PINMUX_ETH0_TXD01
-
IOMUXC_GPIO_EMC_B2_06_NETC_ETH4_COL
-
IOMUXC_GPIO_EMC_B2_06_GPIO3_IO16
-
IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26
-
IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO
-
IOMUXC_GPIO_EMC_B2_06_NETC_PINMUX_ETH3_TXD01
-
IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
-
IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH4_TX_ER
-
IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA
-
IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH0_TX_EN
-
IOMUXC_GPIO_EMC_B2_07_GPIO3_IO17
-
IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27
-
IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI
-
IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH3_TX_EN
-
IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWMA03
-
IOMUXC_GPIO_EMC_B2_07_ECAT_TX_EN_0
-
IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
-
IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH4_RX_CLK
-
IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA
-
IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH0_TX_CLK
-
IOMUXC_GPIO_EMC_B2_08_GPIO3_IO18
-
IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28
-
IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS3
-
IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH3_TX_CLK
-
IOMUXC_GPIO_EMC_B2_08_CCM_CLKO2
-
IOMUXC_GPIO_EMC_B2_08_ECAT_TX_CLK_0
-
IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0
-
IOMUXC_GPIO_EMC_B2_09_ECAT_RX_DATA0_0
-
IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
-
IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH4_RXD03
-
IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK
-
IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH0_RXD00
-
IOMUXC_GPIO_EMC_B2_09_GPIO3_IO19
-
IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29
-
IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2
-
IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH3_RXD00
-
IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1
-
IOMUXC_GPIO_EMC_B2_10_ECAT_RX_DATA1_0
-
IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
-
IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH4_RXD02
-
IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC
-
IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH0_RXD01
-
IOMUXC_GPIO_EMC_B2_10_GPIO3_IO20
-
IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30
-
IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS1
-
IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH3_RXD01
-
IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
-
IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH4_TXD03
-
IOMUXC_GPIO_EMC_B2_11_SPDIF_OUT
-
IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH0_RX_DV
-
IOMUXC_GPIO_EMC_B2_11_LPSPI5_PCS3
-
IOMUXC_GPIO_EMC_B2_11_GPIO3_IO21
-
IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31
-
IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC
-
IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH3_RX_DV
-
IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2
-
IOMUXC_GPIO_EMC_B2_11_ECAT_RX_DV_0
-
IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
-
IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH4_TXD02
-
IOMUXC_GPIO_EMC_B2_12_SPDIF_IN
-
IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH0_RX_ER
-
IOMUXC_GPIO_EMC_B2_12_LPSPI5_PCS2
-
IOMUXC_GPIO_EMC_B2_12_GPIO3_IO22
-
IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32
-
IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK
-
IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH3_RX_ER
-
IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3
-
IOMUXC_GPIO_EMC_B2_12_ECAT_PT0_RX_ER
-
IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0
-
IOMUXC_GPIO_EMC_B2_13_ECAT_TX_DATA0_1
-
IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
-
IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH4_TXD00
-
IOMUXC_GPIO_EMC_B2_13_LPUART11_TX
-
IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH0_TXD03
-
IOMUXC_GPIO_EMC_B2_13_LPSPI5_PCS1
-
IOMUXC_GPIO_EMC_B2_13_GPIO3_IO23
-
IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33
-
IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA
-
IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH3_TXD03
-
IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
-
IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH4_TXD01
-
IOMUXC_GPIO_EMC_B2_14_LPUART11_RX
-
IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH0_TXD02
-
IOMUXC_GPIO_EMC_B2_14_LPUART5_DSR_B
-
IOMUXC_GPIO_EMC_B2_14_GPIO3_IO24
-
IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34
-
IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA
-
IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH3_TXD02
-
IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1
-
IOMUXC_GPIO_EMC_B2_14_ECAT_TX_DATA1_1
-
IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
-
IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH4_TX_EN
-
IOMUXC_GPIO_EMC_B2_15_LPUART11_CTS_B
-
IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH0_RX_CLK
-
IOMUXC_GPIO_EMC_B2_15_LPUART5_DCD_B
-
IOMUXC_GPIO_EMC_B2_15_GPIO3_IO25
-
IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35
-
IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK
-
IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH3_RX_CLK
-
IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2
-
IOMUXC_GPIO_EMC_B2_15_ECAT_TX_EN_1
-
IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3
-
IOMUXC_GPIO_EMC_B2_16_ECAT_TX_CLK_1
-
IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
-
IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH4_TX_CLK
-
IOMUXC_GPIO_EMC_B2_16_LPUART11_RTS_B
-
IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH0_RXD02
-
IOMUXC_GPIO_EMC_B2_16_LPUART5_DTR_B
-
IOMUXC_GPIO_EMC_B2_16_GPIO3_IO26
-
IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14
-
IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC
-
IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH3_RXD02
-
IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
-
IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH4_RXD00
-
IOMUXC_GPIO_EMC_B2_17_LPUART5_TX
-
IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH0_RXD03
-
IOMUXC_GPIO_EMC_B2_17_GPIO3_IO27
-
IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15
-
IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK
-
IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH3_RXD03
-
IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0
-
IOMUXC_GPIO_EMC_B2_17_ECAT_RX_DATA0_1
-
IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4
-
IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH4_RXD01
-
IOMUXC_GPIO_EMC_B2_18_LPUART5_RX
-
IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH0_TX_ER
-
IOMUXC_GPIO_EMC_B2_18_GPIO3_IO28
-
IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16
-
IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B
-
IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH3_TX_ER
-
IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1
-
IOMUXC_GPIO_EMC_B2_18_ECAT_RX_DATA1_1
-
IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2
-
IOMUXC_GPIO_EMC_B2_19_ECAT_RX_DV_1
-
IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00
-
IOMUXC_GPIO_EMC_B2_19_NETC_PINMUX_ETH4_RX_DV
-
IOMUXC_GPIO_EMC_B2_19_LPUART5_CTS_B
-
IOMUXC_GPIO_EMC_B2_19_NETC_ETH0_CRS
-
IOMUXC_GPIO_EMC_B2_19_NETC_EMDC
-
IOMUXC_GPIO_EMC_B2_19_GPIO3_IO29
-
IOMUXC_GPIO_EMC_B2_19_XBAR1_XBAR_INOUT36
-
IOMUXC_GPIO_EMC_B2_19_LPI2C3_SCL
-
IOMUXC_GPIO_EMC_B2_19_NETC_ETH3_SLV_MDC
-
IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3
-
IOMUXC_GPIO_EMC_B2_20_ECAT_RX_ER_1
-
IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01
-
IOMUXC_GPIO_EMC_B2_20_NETC_PINMUX_ETH4_RX_ER
-
IOMUXC_GPIO_EMC_B2_20_LPUART5_RTS_B
-
IOMUXC_GPIO_EMC_B2_20_NETC_ETH0_COL
-
IOMUXC_GPIO_EMC_B2_20_NETC_EMDIO
-
IOMUXC_GPIO_EMC_B2_20_GPIO3_IO30
-
IOMUXC_GPIO_EMC_B2_20_XBAR1_XBAR_INOUT37
-
IOMUXC_GPIO_EMC_B2_20_LPI2C3_SDA
-
IOMUXC_GPIO_EMC_B2_20_NETC_ETH3_SLV_MDIO
-
IOMUXC_GPIO_AD_00_CAN2_TX
-
IOMUXC_GPIO_AD_00_MIC_CLK
-
IOMUXC_GPIO_AD_00_GPT2_CAPTURE1
-
IOMUXC_GPIO_AD_00_FLEXPWM1_PWMA00
-
IOMUXC_GPIO_AD_00_GPIO4_IO00
-
IOMUXC_GPIO_AD_00_SINC1_MOD_CLK0
-
IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00
-
IOMUXC_GPIO_AD_00_QTIMER4_TIMER0
-
IOMUXC_GPIO_AD_01_CAN2_RX
-
IOMUXC_GPIO_AD_01_MIC_BITSTREAM00
-
IOMUXC_GPIO_AD_01_GPT2_CAPTURE2
-
IOMUXC_GPIO_AD_01_FLEXPWM1_PWMB00
-
IOMUXC_GPIO_AD_01_GPIO4_IO01
-
IOMUXC_GPIO_AD_01_SINC1_MOD_CLK1
-
IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01
-
IOMUXC_GPIO_AD_01_QTIMER4_TIMER1
-
IOMUXC_GPIO_AD_02_MIC_BITSTREAM01
-
IOMUXC_GPIO_AD_02_GPT2_COMPARE1
-
IOMUXC_GPIO_AD_02_FLEXPWM1_PWMA01
-
IOMUXC_GPIO_AD_02_GPIO4_IO02
-
IOMUXC_GPIO_AD_02_SINC1_MOD_CLK2
-
IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02
-
IOMUXC_GPIO_AD_02_QTIMER4_TIMER2
-
IOMUXC_GPIO_AD_03_MIC_BITSTREAM02
-
IOMUXC_GPIO_AD_03_GPT2_COMPARE2
-
IOMUXC_GPIO_AD_03_FLEXPWM1_PWMB01
-
IOMUXC_GPIO_AD_03_GPIO4_IO03
-
IOMUXC_GPIO_AD_03_SINC1_EMCLK00
-
IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03
-
IOMUXC_GPIO_AD_03_QTIMER4_TIMER3
-
IOMUXC_GPIO_AD_04_MIC_BITSTREAM03
-
IOMUXC_GPIO_AD_04_GPT2_COMPARE3
-
IOMUXC_GPIO_AD_04_FLEXPWM1_PWMB02
-
IOMUXC_GPIO_AD_04_GPIO4_IO04
-
IOMUXC_GPIO_AD_04_SINC1_EMBIT00
-
IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04
-
IOMUXC_GPIO_AD_04_QTIMER5_TIMER0
-
IOMUXC_GPIO_AD_05_GPT2_CLK
-
IOMUXC_GPIO_AD_05_FLEXPWM1_PWMA02
-
IOMUXC_GPIO_AD_05_GPIO4_IO05
-
IOMUXC_GPIO_AD_05_SINC1_EMCLK01
-
IOMUXC_GPIO_AD_05_CCM_ENET_REF_CLK_25M
-
IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05
-
IOMUXC_GPIO_AD_05_QTIMER5_TIMER1
-
IOMUXC_GPIO_AD_06_USB_OTG2_OC
-
IOMUXC_GPIO_AD_06_CAN3_TX
-
IOMUXC_GPIO_AD_06_FLEXPWM1_PWMX00
-
IOMUXC_GPIO_AD_06_GPIO4_IO06
-
IOMUXC_GPIO_AD_06_SINC1_EMBIT01
-
IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06
-
IOMUXC_GPIO_AD_06_QTIMER5_TIMER2
-
IOMUXC_GPIO_AD_07_USB_OTG2_PWR
-
IOMUXC_GPIO_AD_07_CAN3_RX
-
IOMUXC_GPIO_AD_07_FLEXPWM1_PWMX01
-
IOMUXC_GPIO_AD_07_GPIO4_IO07
-
IOMUXC_GPIO_AD_07_SINC1_EMCLK02
-
IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07
-
IOMUXC_GPIO_AD_07_QTIMER5_TIMER3
-
IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID
-
IOMUXC_GPIO_AD_08_LPI2C5_SCL
-
IOMUXC_GPIO_AD_08_FLEXPWM1_PWMX02
-
IOMUXC_GPIO_AD_08_GPIO4_IO08
-
IOMUXC_GPIO_AD_08_SINC1_EMBIT02
-
IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08
-
IOMUXC_GPIO_AD_08_QTIMER6_TIMER0
-
IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID
-
IOMUXC_GPIO_AD_09_LPI2C5_SDA
-
IOMUXC_GPIO_AD_09_FLEXPWM1_PWMX03
-
IOMUXC_GPIO_AD_09_GPIO4_IO09
-
IOMUXC_GPIO_AD_09_SINC1_EMCLK03
-
IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09
-
IOMUXC_GPIO_AD_09_QTIMER6_TIMER1
-
IOMUXC_GPIO_AD_10_USB_OTG1_PWR
-
IOMUXC_GPIO_AD_10_FLEXPWM2_PWMX00
-
IOMUXC_GPIO_AD_10_GPIO4_IO10
-
IOMUXC_GPIO_AD_10_SINC1_EMBIT03
-
IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10
-
IOMUXC_GPIO_AD_10_QTIMER6_TIMER2
-
IOMUXC_GPIO_AD_11_USB_OTG1_OC
-
IOMUXC_GPIO_AD_11_FLEXPWM2_PWMX01
-
IOMUXC_GPIO_AD_11_GPIO4_IO11
-
IOMUXC_GPIO_AD_11_SINC_FILTER_GLUE1_BREAK
-
IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11
-
IOMUXC_GPIO_AD_11_QTIMER6_TIMER3
-
IOMUXC_GPIO_AD_12_SPDIF_LOCK
-
IOMUXC_GPIO_AD_12_LPI2C5_SCLS
-
IOMUXC_GPIO_AD_12_GPT1_CAPTURE1
-
IOMUXC_GPIO_AD_12_KPP_ROW07
-
IOMUXC_GPIO_AD_12_FLEXPWM2_PWMX02
-
IOMUXC_GPIO_AD_12_GPIO4_IO12
-
IOMUXC_GPIO_AD_12_XBAR1_XBAR_INOUT18
-
IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B
-
IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12
-
IOMUXC_GPIO_AD_13_SPDIF_SR_CLK
-
IOMUXC_GPIO_AD_13_LPI2C5_SDAS
-
IOMUXC_GPIO_AD_13_GPT1_CAPTURE2
-
IOMUXC_GPIO_AD_13_KPP_COL07
-
IOMUXC_GPIO_AD_13_FLEXPWM2_PWMX03
-
IOMUXC_GPIO_AD_13_GPIO4_IO13
-
IOMUXC_GPIO_AD_13_LPUART3_TX
-
IOMUXC_GPIO_AD_13_USDHC2_CD_B
-
IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13
-
IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK
-
IOMUXC_GPIO_AD_14_LPI2C5_HREQ
-
IOMUXC_GPIO_AD_14_GPT1_COMPARE1
-
IOMUXC_GPIO_AD_14_KPP_ROW06
-
IOMUXC_GPIO_AD_14_FLEXPWM3_PWMX00
-
IOMUXC_GPIO_AD_14_GPIO4_IO14
-
IOMUXC_GPIO_AD_14_LPUART3_RX
-
IOMUXC_GPIO_AD_14_USDHC2_WP
-
IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14
-
IOMUXC_GPIO_AD_15_ECAT_CLK_ECAT_CLK25
-
IOMUXC_GPIO_AD_15_SPDIF_IN
-
IOMUXC_GPIO_AD_15_LPUART10_TX
-
IOMUXC_GPIO_AD_15_GPT1_COMPARE2
-
IOMUXC_GPIO_AD_15_KPP_COL06
-
IOMUXC_GPIO_AD_15_FLEXPWM3_PWMX01
-
IOMUXC_GPIO_AD_15_GPIO4_IO15
-
IOMUXC_GPIO_AD_15_LPUART3_CTS_B
-
IOMUXC_GPIO_AD_15_LPSPI3_PCS1
-
IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15
-
IOMUXC_GPIO_AD_15_CAN1_TX
-
IOMUXC_GPIO_AD_16_SPDIF_OUT
-
IOMUXC_GPIO_AD_16_LPUART10_RX
-
IOMUXC_GPIO_AD_16_GPT1_COMPARE3
-
IOMUXC_GPIO_AD_16_KPP_ROW05
-
IOMUXC_GPIO_AD_16_FLEXPWM3_PWMX02
-
IOMUXC_GPIO_AD_16_GPIO4_IO16
-
IOMUXC_GPIO_AD_16_LPUART3_RTS_B
-
IOMUXC_GPIO_AD_16_LPSPI3_SCK
-
IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16
-
IOMUXC_GPIO_AD_16_CAN1_RX
-
IOMUXC_GPIO_AD_16_ECAT_LINK_0
-
IOMUXC_GPIO_AD_17_SAI4_MCLK
-
IOMUXC_GPIO_AD_17_ACMP1_CMPO
-
IOMUXC_GPIO_AD_17_GPT1_CLK
-
IOMUXC_GPIO_AD_17_KPP_COL05
-
IOMUXC_GPIO_AD_17_FLEXPWM3_PWMX03
-
IOMUXC_GPIO_AD_17_GPIO4_IO17
-
IOMUXC_GPIO_AD_17_I3C2_PUR
-
IOMUXC_GPIO_AD_17_LPSPI3_PCS0
-
IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17
-
IOMUXC_GPIO_AD_17_LPI2C3_HREQ
-
IOMUXC_GPIO_AD_17_ECAT_LINK_1
-
IOMUXC_GPIO_AD_18_ECAT_PROM_CLK
-
IOMUXC_GPIO_AD_18_SAI4_RX_SYNC
-
IOMUXC_GPIO_AD_18_ACMP2_CMPO
-
IOMUXC_GPIO_AD_18_LPUART5_RI_B
-
IOMUXC_GPIO_AD_18_KPP_ROW04
-
IOMUXC_GPIO_AD_18_FLEXPWM4_PWMX00
-
IOMUXC_GPIO_AD_18_GPIO4_IO18
-
IOMUXC_GPIO_AD_18_I3C2_SCL
-
IOMUXC_GPIO_AD_18_LPSPI3_SDO
-
IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18
-
IOMUXC_GPIO_AD_18_LPI2C3_SCL
-
IOMUXC_GPIO_AD_19_SAI4_RX_BCLK
-
IOMUXC_GPIO_AD_19_ACMP3_CMPO
-
IOMUXC_GPIO_AD_19_XBAR1_XBAR_INOUT19
-
IOMUXC_GPIO_AD_19_KPP_COL04
-
IOMUXC_GPIO_AD_19_FLEXPWM4_PWMX01
-
IOMUXC_GPIO_AD_19_GPIO4_IO19
-
IOMUXC_GPIO_AD_19_I3C2_SDA
-
IOMUXC_GPIO_AD_19_LPSPI3_SDI
-
IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19
-
IOMUXC_GPIO_AD_19_LPI2C3_SDA
-
IOMUXC_GPIO_AD_19_ECAT_PROM_DATA
-
IOMUXC_GPIO_AD_20_SAI4_RX_DATA00
-
IOMUXC_GPIO_AD_20_ACMP4_CMPO
-
IOMUXC_GPIO_AD_20_LPIT2_TRIGGER00
-
IOMUXC_GPIO_AD_20_SINC1_EMCLK00
-
IOMUXC_GPIO_AD_20_FLEXPWM4_PWMX02
-
IOMUXC_GPIO_AD_20_GPIO4_IO20
-
IOMUXC_GPIO_AD_20_NETC_TMR_TRIG1
-
IOMUXC_GPIO_AD_20_NETC_1588_CLK
-
IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20
-
IOMUXC_GPIO_AD_21_SAI4_TX_DATA00
-
IOMUXC_GPIO_AD_21_LPIT2_TRIGGER01
-
IOMUXC_GPIO_AD_21_SINC1_EMBIT00
-
IOMUXC_GPIO_AD_21_FLEXPWM4_PWMX03
-
IOMUXC_GPIO_AD_21_GPIO4_IO21
-
IOMUXC_GPIO_AD_21_NETC_TMR_TRIG2
-
IOMUXC_GPIO_AD_21_NETC_TMR_GCLK
-
IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21
-
IOMUXC_GPIO_AD_21_ECAT_LED_RUN
-
IOMUXC_GPIO_AD_22_ECAT_LED_ERR
-
IOMUXC_GPIO_AD_22_SAI4_TX_BCLK
-
IOMUXC_GPIO_AD_22_LPIT2_TRIGGER02
-
IOMUXC_GPIO_AD_22_SINC1_EMCLK01
-
IOMUXC_GPIO_AD_22_GPIO4_IO22
-
IOMUXC_GPIO_AD_22_NETC_TMR_ALARM1
-
IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22
-
IOMUXC_GPIO_AD_23_SAI4_TX_SYNC
-
IOMUXC_GPIO_AD_23_LPIT2_TRIGGER03
-
IOMUXC_GPIO_AD_23_SINC1_EMBIT01
-
IOMUXC_GPIO_AD_23_GPIO4_IO23
-
IOMUXC_GPIO_AD_23_NETC_TMR_ALARM2
-
IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23
-
IOMUXC_GPIO_AD_23_ECAT_LED_STATE_RUN
-
IOMUXC_GPIO_AD_24_LPUART6_TX
-
IOMUXC_GPIO_AD_24_LPI2C4_SCL
-
IOMUXC_GPIO_AD_24_SINC2_MOD_CLK1
-
IOMUXC_GPIO_AD_24_FLEXPWM2_PWMA00
-
IOMUXC_GPIO_AD_24_GPIO4_IO24
-
IOMUXC_GPIO_AD_24_NETC_TMR_TRIG1
-
IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24
-
IOMUXC_GPIO_AD_24_ECAT_LINK_ACT00
-
IOMUXC_GPIO_AD_25_ECAT_LINK_ACT01
-
IOMUXC_GPIO_AD_25_LPUART6_RX
-
IOMUXC_GPIO_AD_25_LPI2C4_SDA
-
IOMUXC_GPIO_AD_25_LPSPI5_PCS3
-
IOMUXC_GPIO_AD_25_SINC2_MOD_CLK2
-
IOMUXC_GPIO_AD_25_FLEXPWM2_PWMB00
-
IOMUXC_GPIO_AD_25_GPIO4_IO25
-
IOMUXC_GPIO_AD_25_NETC_TMR_TRIG2
-
IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25
-
IOMUXC_GPIO_AD_26_LPUART6_CTS_B
-
IOMUXC_GPIO_AD_26_LPUART5_TX
-
IOMUXC_GPIO_AD_26_LPSPI5_PCS2
-
IOMUXC_GPIO_AD_26_SINC2_EMCLK00
-
IOMUXC_GPIO_AD_26_FLEXPWM2_PWMA01
-
IOMUXC_GPIO_AD_26_GPIO4_IO26
-
IOMUXC_GPIO_AD_26_KPP_ROW00
-
IOMUXC_GPIO_AD_26_NETC_TMR_PP1
-
IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26
-
IOMUXC_GPIO_AD_26_USDHC2_CD_B
-
IOMUXC_GPIO_AD_26_MIC_BITSTREAM02
-
IOMUXC_GPIO_AD_27_LPUART6_RTS_B
-
IOMUXC_GPIO_AD_27_LPUART5_RX
-
IOMUXC_GPIO_AD_27_LPSPI5_PCS1
-
IOMUXC_GPIO_AD_27_SINC2_EMBIT00
-
IOMUXC_GPIO_AD_27_FLEXPWM2_PWMB01
-
IOMUXC_GPIO_AD_27_GPIO4_IO27
-
IOMUXC_GPIO_AD_27_KPP_COL00
-
IOMUXC_GPIO_AD_27_NETC_TMR_PP2
-
IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27
-
IOMUXC_GPIO_AD_27_USDHC2_WP
-
IOMUXC_GPIO_AD_27_MIC_CLK
-
IOMUXC_GPIO_AD_28_MIC_BITSTREAM00
-
IOMUXC_GPIO_AD_28_LPSPI5_SCK
-
IOMUXC_GPIO_AD_28_I3C1_PUR
-
IOMUXC_GPIO_AD_28_SINC2_EMCLK01
-
IOMUXC_GPIO_AD_28_FLEXPWM2_PWMB02
-
IOMUXC_GPIO_AD_28_GPIO4_IO28
-
IOMUXC_GPIO_AD_28_KPP_ROW03
-
IOMUXC_GPIO_AD_28_NETC_TMR_PP3
-
IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28
-
IOMUXC_GPIO_AD_28_USDHC2_RESET_B
-
IOMUXC_GPIO_AD_29_LPSPI5_PCS0
-
IOMUXC_GPIO_AD_29_USDHC2_CD_B
-
IOMUXC_GPIO_AD_29_SINC2_EMBIT01
-
IOMUXC_GPIO_AD_29_FLEXPWM2_PWMA02
-
IOMUXC_GPIO_AD_29_GPIO4_IO29
-
IOMUXC_GPIO_AD_29_KPP_COL03
-
IOMUXC_GPIO_AD_29_EWM_EWM_OUT_B
-
IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29
-
IOMUXC_GPIO_AD_29_USDHC2_VSELECT
-
IOMUXC_GPIO_AD_29_MIC_BITSTREAM01
-
IOMUXC_GPIO_AD_30_LPSPI5_SDO
-
IOMUXC_GPIO_AD_30_USB_OTG2_OC
-
IOMUXC_GPIO_AD_30_CAN2_TX
-
IOMUXC_GPIO_AD_30_SINC2_EMCLK02
-
IOMUXC_GPIO_AD_30_LPUART8_TX
-
IOMUXC_GPIO_AD_30_GPIO4_IO30
-
IOMUXC_GPIO_AD_30_KPP_ROW02
-
IOMUXC_GPIO_AD_30_NETC_EMDC
-
IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30
-
IOMUXC_GPIO_AD_30_XBAR1_XBAR_INOUT24
-
IOMUXC_GPIO_AD_30_ECAT_MCLK
-
IOMUXC_GPIO_AD_31_LPSPI5_SDI
-
IOMUXC_GPIO_AD_31_USB_OTG2_PWR
-
IOMUXC_GPIO_AD_31_CAN2_RX
-
IOMUXC_GPIO_AD_31_SINC2_EMBIT02
-
IOMUXC_GPIO_AD_31_LPUART8_RX
-
IOMUXC_GPIO_AD_31_GPIO4_IO31
-
IOMUXC_GPIO_AD_31_KPP_COL02
-
IOMUXC_GPIO_AD_31_NETC_EMDIO
-
IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31
-
IOMUXC_GPIO_AD_31_XBAR1_XBAR_INOUT25
-
IOMUXC_GPIO_AD_31_ECAT_MDIO
-
IOMUXC_GPIO_AD_32_MIC_BITSTREAM03
-
IOMUXC_GPIO_AD_32_LPI2C5_SCL
-
IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID
-
IOMUXC_GPIO_AD_32_GPC_PMIC_RDY
-
IOMUXC_GPIO_AD_32_SINC2_EMCLK03
-
IOMUXC_GPIO_AD_32_USDHC1_CD_B
-
IOMUXC_GPIO_AD_32_GPIO5_IO00
-
IOMUXC_GPIO_AD_32_KPP_ROW01
-
IOMUXC_GPIO_AD_32_NETC_TMR_TRIG1
-
IOMUXC_GPIO_AD_32_LPUART10_TX
-
IOMUXC_GPIO_AD_33_LPI2C5_SDA
-
IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID
-
IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17
-
IOMUXC_GPIO_AD_33_SINC2_EMBIT03
-
IOMUXC_GPIO_AD_33_USDHC1_WP
-
IOMUXC_GPIO_AD_33_GPIO5_IO01
-
IOMUXC_GPIO_AD_33_KPP_COL01
-
IOMUXC_GPIO_AD_33_NETC_TMR_TRIG2
-
IOMUXC_GPIO_AD_33_LPUART10_RX
-
IOMUXC_GPIO_AD_34_I3C2_SCL
-
IOMUXC_GPIO_AD_34_USB_OTG1_PWR
-
IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18
-
IOMUXC_GPIO_AD_34_SINC_FILTER_GLUE2_BREAK
-
IOMUXC_GPIO_AD_34_USDHC1_VSELECT
-
IOMUXC_GPIO_AD_34_GPIO5_IO02
-
IOMUXC_GPIO_AD_34_NETC_TMR_ALARM1
-
IOMUXC_GPIO_AD_34_LPUART10_CTS_B
-
IOMUXC_GPIO_AD_35_I3C2_SDA
-
IOMUXC_GPIO_AD_35_USB_OTG1_OC
-
IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19
-
IOMUXC_GPIO_AD_35_SINC2_MOD_CLK0
-
IOMUXC_GPIO_AD_35_USDHC1_RESET_B
-
IOMUXC_GPIO_AD_35_GPIO5_IO03
-
IOMUXC_GPIO_AD_35_NETC_TMR_ALARM2
-
IOMUXC_GPIO_AD_35_LPUART10_RTS_B
-
IOMUXC_GPIO_SD_B1_00_USDHC1_CMD
-
IOMUXC_GPIO_SD_B1_00_SINC1_EMCLK02
-
IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20
-
IOMUXC_GPIO_SD_B1_00_LPTMR2_ALT1
-
IOMUXC_GPIO_SD_B1_00_XSPI_SLV_CS
-
IOMUXC_GPIO_SD_B1_00_GPIO5_IO04
-
IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0
-
IOMUXC_GPIO_SD_B1_00_KPP_ROW07
-
IOMUXC_GPIO_SD_B1_00_CCM_CLKO1
-
IOMUXC_GPIO_SD_B1_01_USDHC1_CLK
-
IOMUXC_GPIO_SD_B1_01_SINC1_EMBIT02
-
IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21
-
IOMUXC_GPIO_SD_B1_01_LPTMR2_ALT2
-
IOMUXC_GPIO_SD_B1_01_XSPI_SLV_CLK
-
IOMUXC_GPIO_SD_B1_01_GPIO5_IO05
-
IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK
-
IOMUXC_GPIO_SD_B1_01_KPP_COL07
-
IOMUXC_GPIO_SD_B1_01_CCM_CLKO2
-
IOMUXC_GPIO_SD_B1_02_ECAT_RESET_OUT
-
IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0
-
IOMUXC_GPIO_SD_B1_02_SINC1_EMCLK03
-
IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22
-
IOMUXC_GPIO_SD_B1_02_LPTMR2_ALT3
-
IOMUXC_GPIO_SD_B1_02_XSPI_SLV_DATA04
-
IOMUXC_GPIO_SD_B1_02_GPIO5_IO06
-
IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO
-
IOMUXC_GPIO_SD_B1_02_KPP_ROW06
-
IOMUXC_GPIO_SD_B1_02_FLEXSPI1_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1
-
IOMUXC_GPIO_SD_B1_03_SINC1_EMBIT03
-
IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23
-
IOMUXC_GPIO_SD_B1_03_LPTMR3_ALT1
-
IOMUXC_GPIO_SD_B1_03_XSPI_SLV_DATA05
-
IOMUXC_GPIO_SD_B1_03_GPIO5_IO07
-
IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI
-
IOMUXC_GPIO_SD_B1_03_KPP_COL06
-
IOMUXC_GPIO_SD_B1_03_FLEXSPI1_BUS2BIT_B_SS1_B
-
IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2
-
IOMUXC_GPIO_SD_B1_04_SINC_FILTER_GLUE1_BREAK
-
IOMUXC_GPIO_SD_B1_04_SINC2_EMCLK02
-
IOMUXC_GPIO_SD_B1_04_LPTMR3_ALT2
-
IOMUXC_GPIO_SD_B1_04_XSPI_SLV_DATA06
-
IOMUXC_GPIO_SD_B1_04_GPIO5_IO08
-
IOMUXC_GPIO_SD_B1_04_LPSPI3_PCS1
-
IOMUXC_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3
-
IOMUXC_GPIO_SD_B1_05_SINC2_EMBIT02
-
IOMUXC_GPIO_SD_B1_05_LPTMR3_ALT3
-
IOMUXC_GPIO_SD_B1_05_XSPI_SLV_DATA07
-
IOMUXC_GPIO_SD_B1_05_GPIO5_IO09
-
IOMUXC_GPIO_SD_B1_05_LPSPI3_PCS2
-
IOMUXC_GPIO_SD_B1_05_FLEXSPI1_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_SD_B2_00_MIC_BITSTREAM00
-
IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3
-
IOMUXC_GPIO_SD_B2_00_FLEXSPI1_BUS2BIT_B_DATA04
-
IOMUXC_GPIO_SD_B2_00_XSPI_SLV_DATA04
-
IOMUXC_GPIO_SD_B2_00_XBAR1_XBAR_INOUT17
-
IOMUXC_GPIO_SD_B2_00_KPP_ROW01
-
IOMUXC_GPIO_SD_B2_00_GPIO5_IO10
-
IOMUXC_GPIO_SD_B2_00_LPSPI3_PCS3
-
IOMUXC_GPIO_SD_B2_00_NETC_1588_CLK
-
IOMUXC_GPIO_SD_B2_00_LPUART8_TX
-
IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2
-
IOMUXC_GPIO_SD_B2_01_FLEXSPI1_BUS2BIT_B_DATA05
-
IOMUXC_GPIO_SD_B2_01_XSPI_SLV_DATA05
-
IOMUXC_GPIO_SD_B2_01_QTIMER6_TIMER0
-
IOMUXC_GPIO_SD_B2_01_KPP_COL01
-
IOMUXC_GPIO_SD_B2_01_GPIO5_IO11
-
IOMUXC_GPIO_SD_B2_01_NETC_TMR_GCLK
-
IOMUXC_GPIO_SD_B2_01_LPUART8_RX
-
IOMUXC_GPIO_SD_B2_01_MIC_BITSTREAM01
-
IOMUXC_GPIO_SD_B2_02_MIC_BITSTREAM02
-
IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1
-
IOMUXC_GPIO_SD_B2_02_FLEXSPI1_BUS2BIT_B_DATA06
-
IOMUXC_GPIO_SD_B2_02_XSPI_SLV_DATA06
-
IOMUXC_GPIO_SD_B2_02_QTIMER6_TIMER1
-
IOMUXC_GPIO_SD_B2_02_KPP_ROW00
-
IOMUXC_GPIO_SD_B2_02_GPIO5_IO12
-
IOMUXC_GPIO_SD_B2_02_NETC_TMR_ALARM1
-
IOMUXC_GPIO_SD_B2_02_LPUART8_CTS_B
-
IOMUXC_GPIO_SD_B2_03_MIC_BITSTREAM03
-
IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0
-
IOMUXC_GPIO_SD_B2_03_FLEXSPI1_BUS2BIT_B_DATA07
-
IOMUXC_GPIO_SD_B2_03_XSPI_SLV_DATA07
-
IOMUXC_GPIO_SD_B2_03_QTIMER6_TIMER2
-
IOMUXC_GPIO_SD_B2_03_KPP_COL00
-
IOMUXC_GPIO_SD_B2_03_GPIO5_IO13
-
IOMUXC_GPIO_SD_B2_03_NETC_TMR_ALARM2
-
IOMUXC_GPIO_SD_B2_03_LPUART8_RTS_B
-
IOMUXC_GPIO_SD_B2_04_USDHC2_CLK
-
IOMUXC_GPIO_SD_B2_04_FLEXSPI1_BUS2BIT_B_SS1_B
-
IOMUXC_GPIO_SD_B2_04_QTIMER7_TIMER0
-
IOMUXC_GPIO_SD_B2_04_KPP_ROW03
-
IOMUXC_GPIO_SD_B2_04_GPIO5_IO14
-
IOMUXC_GPIO_SD_B2_04_LPUART5_RI_B
-
IOMUXC_GPIO_SD_B2_04_NETC_TMR_PP1
-
IOMUXC_GPIO_SD_B2_04_MIC_CLK
-
IOMUXC_GPIO_SD_B2_05_USDHC2_CMD
-
IOMUXC_GPIO_SD_B2_05_FLEXSPI1_BUS2BIT_B_DQS
-
IOMUXC_GPIO_SD_B2_05_XSPI_SLV_DQS
-
IOMUXC_GPIO_SD_B2_05_QTIMER7_TIMER1
-
IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS3
-
IOMUXC_GPIO_SD_B2_05_GPIO5_IO15
-
IOMUXC_GPIO_SD_B2_05_LPUART5_DTR_B
-
IOMUXC_GPIO_SD_B2_05_NETC_TMR_PP2
-
IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B
-
IOMUXC_GPIO_SD_B2_06_FLEXSPI1_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_SD_B2_06_XSPI_SLV_CS
-
IOMUXC_GPIO_SD_B2_06_QTIMER7_TIMER2
-
IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS2
-
IOMUXC_GPIO_SD_B2_06_GPIO5_IO16
-
IOMUXC_GPIO_SD_B2_06_LPUART5_CTS_B
-
IOMUXC_GPIO_SD_B2_06_NETC_TMR_PP3
-
IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE
-
IOMUXC_GPIO_SD_B2_07_FLEXSPI1_BUS2BIT_B_SCLK
-
IOMUXC_GPIO_SD_B2_07_XSPI_SLV_CLK
-
IOMUXC_GPIO_SD_B2_07_QTIMER7_TIMER3
-
IOMUXC_GPIO_SD_B2_07_LPSPI4_PCS1
-
IOMUXC_GPIO_SD_B2_07_GPIO5_IO17
-
IOMUXC_GPIO_SD_B2_07_LPUART5_RTS_B
-
IOMUXC_GPIO_SD_B2_07_NETC_TMR_ALARM1
-
IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4
-
IOMUXC_GPIO_SD_B2_08_FLEXSPI1_BUS2BIT_B_DATA00
-
IOMUXC_GPIO_SD_B2_08_XSPI_SLV_DATA00
-
IOMUXC_GPIO_SD_B2_08_QTIMER8_TIMER0
-
IOMUXC_GPIO_SD_B2_08_LPSPI4_SCK
-
IOMUXC_GPIO_SD_B2_08_GPIO5_IO18
-
IOMUXC_GPIO_SD_B2_08_LPUART5_TX
-
IOMUXC_GPIO_SD_B2_08_NETC_TMR_ALARM2
-
IOMUXC_GPIO_SD_B2_08_NETC_TMR_PP2
-
IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5
-
IOMUXC_GPIO_SD_B2_09_FLEXSPI1_BUS2BIT_B_DATA01
-
IOMUXC_GPIO_SD_B2_09_XSPI_SLV_DATA01
-
IOMUXC_GPIO_SD_B2_09_QTIMER8_TIMER1
-
IOMUXC_GPIO_SD_B2_09_LPSPI4_PCS0
-
IOMUXC_GPIO_SD_B2_09_GPIO5_IO19
-
IOMUXC_GPIO_SD_B2_09_LPUART5_RX
-
IOMUXC_GPIO_SD_B2_09_NETC_TMR_PP1
-
IOMUXC_GPIO_SD_B2_10_NETC_EMDIO
-
IOMUXC_GPIO_SD_B2_10_ECAT_MDIO
-
IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6
-
IOMUXC_GPIO_SD_B2_10_FLEXSPI1_BUS2BIT_B_DATA02
-
IOMUXC_GPIO_SD_B2_10_XSPI_SLV_DATA02
-
IOMUXC_GPIO_SD_B2_10_QTIMER8_TIMER2
-
IOMUXC_GPIO_SD_B2_10_LPSPI4_SDO
-
IOMUXC_GPIO_SD_B2_10_GPIO5_IO20
-
IOMUXC_GPIO_SD_B2_10_LPUART5_DCD_B
-
IOMUXC_GPIO_SD_B2_10_NETC_TMR_TRIG2
-
IOMUXC_GPIO_SD_B2_10_NETC_TMR_PP3
-
IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7
-
IOMUXC_GPIO_SD_B2_11_FLEXSPI1_BUS2BIT_B_DATA03
-
IOMUXC_GPIO_SD_B2_11_XSPI_SLV_DATA03
-
IOMUXC_GPIO_SD_B2_11_QTIMER8_TIMER3
-
IOMUXC_GPIO_SD_B2_11_LPSPI4_SDI
-
IOMUXC_GPIO_SD_B2_11_GPIO5_IO21
-
IOMUXC_GPIO_SD_B2_11_LPUART5_DSR_B
-
IOMUXC_GPIO_SD_B2_11_SFA_ATX_CLK_OUT
-
IOMUXC_GPIO_SD_B2_11_NETC_TMR_TRIG1
-
IOMUXC_GPIO_SD_B2_11_NETC_EMDC
-
IOMUXC_GPIO_SD_B2_11_ECAT_MCLK
-
IOMUXC_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_A_DQS
-
IOMUXC_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_B_DQS
-
IOMUXC_GPIO_SD_B2_12_DUMMY_GPIO5_IO22
-
IOMUXC_GPIO_B1_00_NETC_PINMUX_ETH1_TXD00
-
IOMUXC_GPIO_B1_00_ADC2_CONV_D00
-
IOMUXC_GPIO_B1_00_SEMC_CSX01
-
IOMUXC_GPIO_B1_00_QTIMER1_TIMER0
-
IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT26
-
IOMUXC_GPIO_B1_00_GPIO6_IO00
-
IOMUXC_GPIO_B1_00_TPM5_CH00
-
IOMUXC_GPIO_B1_00_NETC_PINMUX_ETH4_TXD00
-
IOMUXC_GPIO_B1_01_NETC_PINMUX_ETH1_TXD01
-
IOMUXC_GPIO_B1_01_ADC2_CONV_D01
-
IOMUXC_GPIO_B1_01_SEMC_CSX02
-
IOMUXC_GPIO_B1_01_QTIMER1_TIMER1
-
IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT27
-
IOMUXC_GPIO_B1_01_GPIO6_IO01
-
IOMUXC_GPIO_B1_01_TPM5_CH01
-
IOMUXC_GPIO_B1_01_NETC_PINMUX_ETH4_TXD01
-
IOMUXC_GPIO_B1_01_SAI4_RX_DATA00
-
IOMUXC_GPIO_B1_02_NETC_PINMUX_ETH1_TX_EN
-
IOMUXC_GPIO_B1_02_ADC2_CONV_D02
-
IOMUXC_GPIO_B1_02_LPI2C6_SCL
-
IOMUXC_GPIO_B1_02_QTIMER1_TIMER2
-
IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT28
-
IOMUXC_GPIO_B1_02_GPIO6_IO02
-
IOMUXC_GPIO_B1_02_TPM5_CH02
-
IOMUXC_GPIO_B1_02_FLEXSPI1_BUS2BIT_B_SS1_B
-
IOMUXC_GPIO_B1_02_NETC_PINMUX_ETH4_TX_EN
-
IOMUXC_GPIO_B1_02_LPUART11_TX
-
IOMUXC_GPIO_B1_02_SAI4_RX_DATA01
-
IOMUXC_GPIO_B1_03_NETC_PINMUX_ETH1_TX_CLK
-
IOMUXC_GPIO_B1_03_ADC2_CONV_D03
-
IOMUXC_GPIO_B1_03_LPI2C6_SDA
-
IOMUXC_GPIO_B1_03_QTIMER2_TIMER0
-
IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT29
-
IOMUXC_GPIO_B1_03_GPIO6_IO03
-
IOMUXC_GPIO_B1_03_TPM5_CH03
-
IOMUXC_GPIO_B1_03_FLEXSPI1_BUS2BIT_B_DQS
-
IOMUXC_GPIO_B1_03_NETC_PINMUX_ETH4_TX_CLK
-
IOMUXC_GPIO_B1_03_LPUART11_RX
-
IOMUXC_GPIO_B1_03_SAI4_RX_DATA02
-
IOMUXC_GPIO_B1_04_NETC_PINMUX_ETH1_RXD00
-
IOMUXC_GPIO_B1_04_ADC2_CONV_D04
-
IOMUXC_GPIO_B1_04_LPUART9_RX
-
IOMUXC_GPIO_B1_04_QTIMER2_TIMER1
-
IOMUXC_GPIO_B1_04_XBAR1_XBAR_INOUT30
-
IOMUXC_GPIO_B1_04_GPIO6_IO04
-
IOMUXC_GPIO_B1_04_TPM5_EXTCLK
-
IOMUXC_GPIO_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_B1_04_NETC_PINMUX_ETH4_RXD00
-
IOMUXC_GPIO_B1_04_SAI4_RX_DATA03
-
IOMUXC_GPIO_B1_05_NETC_PINMUX_ETH1_RXD01
-
IOMUXC_GPIO_B1_05_ADC2_CONV_D05
-
IOMUXC_GPIO_B1_05_LPUART9_CTS_B
-
IOMUXC_GPIO_B1_05_QTIMER2_TIMER2
-
IOMUXC_GPIO_B1_05_XBAR1_XBAR_INOUT31
-
IOMUXC_GPIO_B1_05_GPIO6_IO05
-
IOMUXC_GPIO_B1_05_TPM6_EXTCLK
-
IOMUXC_GPIO_B1_05_FLEXSPI1_BUS2BIT_B_SCLK
-
IOMUXC_GPIO_B1_05_NETC_PINMUX_ETH4_RXD01
-
IOMUXC_GPIO_B1_05_SAI4_MCLK
-
IOMUXC_GPIO_B1_06_NETC_PINMUX_ETH1_RX_DV
-
IOMUXC_GPIO_B1_06_ADC2_CONV_D06
-
IOMUXC_GPIO_B1_06_LPUART9_TX
-
IOMUXC_GPIO_B1_06_QTIMER3_TIMER0
-
IOMUXC_GPIO_B1_06_XBAR1_XBAR_INOUT32
-
IOMUXC_GPIO_B1_06_GPIO6_IO06
-
IOMUXC_GPIO_B1_06_TPM6_CH00
-
IOMUXC_GPIO_B1_06_FLEXSPI1_BUS2BIT_B_DATA07
-
IOMUXC_GPIO_B1_06_NETC_PINMUX_ETH4_RX_DV
-
IOMUXC_GPIO_B1_06_SAI4_RX_BCLK
-
IOMUXC_GPIO_B1_07_NETC_PINMUX_ETH1_TXD02
-
IOMUXC_GPIO_B1_07_ADC2_CONV_D07
-
IOMUXC_GPIO_B1_07_LPUART9_RTS_B
-
IOMUXC_GPIO_B1_07_QTIMER3_TIMER1
-
IOMUXC_GPIO_B1_07_XBAR1_XBAR_INOUT33
-
IOMUXC_GPIO_B1_07_GPIO6_IO07
-
IOMUXC_GPIO_B1_07_TPM6_CH01
-
IOMUXC_GPIO_B1_07_FLEXSPI1_BUS2BIT_B_DATA06
-
IOMUXC_GPIO_B1_07_NETC_PINMUX_ETH4_TXD02
-
IOMUXC_GPIO_B1_07_LPSPI6_SDI
-
IOMUXC_GPIO_B1_07_SAI4_RX_SYNC
-
IOMUXC_GPIO_B1_08_SAI4_TX_BCLK
-
IOMUXC_GPIO_B1_08_NETC_PINMUX_ETH1_TXD03
-
IOMUXC_GPIO_B1_08_ADC2_CONV_RDY_CLK
-
IOMUXC_GPIO_B1_08_USDHC1_CD_B
-
IOMUXC_GPIO_B1_08_QTIMER3_TIMER2
-
IOMUXC_GPIO_B1_08_XBAR1_XBAR_INOUT36
-
IOMUXC_GPIO_B1_08_GPIO6_IO08
-
IOMUXC_GPIO_B1_08_TPM6_CH02
-
IOMUXC_GPIO_B1_08_FLEXSPI1_BUS2BIT_B_DATA05
-
IOMUXC_GPIO_B1_08_NETC_PINMUX_ETH4_TXD03
-
IOMUXC_GPIO_B1_08_LPSPI6_SDO
-
IOMUXC_GPIO_B1_09_NETC_PINMUX_ETH1_RXD02
-
IOMUXC_GPIO_B1_09_USDHC1_WP
-
IOMUXC_GPIO_B1_09_QTIMER4_TIMER0
-
IOMUXC_GPIO_B1_09_XBAR1_XBAR_INOUT37
-
IOMUXC_GPIO_B1_09_GPIO6_IO09
-
IOMUXC_GPIO_B1_09_TPM6_CH03
-
IOMUXC_GPIO_B1_09_FLEXSPI1_BUS2BIT_B_DATA04
-
IOMUXC_GPIO_B1_09_NETC_PINMUX_ETH4_RXD02
-
IOMUXC_GPIO_B1_09_LPSPI6_PCS1
-
IOMUXC_GPIO_B1_09_SAI4_TX_SYNC
-
IOMUXC_GPIO_B1_10_NETC_PINMUX_ETH1_RXD03
-
IOMUXC_GPIO_B1_10_USDHC1_RESET_B
-
IOMUXC_GPIO_B1_10_QTIMER4_TIMER1
-
IOMUXC_GPIO_B1_10_XBAR1_XBAR_INOUT34
-
IOMUXC_GPIO_B1_10_GPIO6_IO10
-
IOMUXC_GPIO_B1_10_FLEXSPI1_BUS2BIT_B_DATA03
-
IOMUXC_GPIO_B1_10_NETC_PINMUX_ETH4_RXD03
-
IOMUXC_GPIO_B1_10_LPSPI6_PCS2
-
IOMUXC_GPIO_B1_10_SAI4_TX_DATA00
-
IOMUXC_GPIO_B1_11_NETC_PINMUX_ETH1_RX_CLK
-
IOMUXC_GPIO_B1_11_QTIMER4_TIMER2
-
IOMUXC_GPIO_B1_11_XBAR1_XBAR_INOUT35
-
IOMUXC_GPIO_B1_11_GPIO6_IO11
-
IOMUXC_GPIO_B1_11_FLEXSPI1_BUS2BIT_B_DATA02
-
IOMUXC_GPIO_B1_11_NETC_PINMUX_ETH4_RX_CLK
-
IOMUXC_GPIO_B1_11_LPSPI6_PCS3
-
IOMUXC_GPIO_B1_11_SAI4_TX_DATA01
-
IOMUXC_GPIO_B1_12_SAI4_TX_DATA02
-
IOMUXC_GPIO_B1_12_NETC_PINMUX_ETH1_RX_ER
-
IOMUXC_GPIO_B1_12_NETC_EMDIO
-
IOMUXC_GPIO_B1_12_GPIO6_IO12
-
IOMUXC_GPIO_B1_12_FLEXSPI1_BUS2BIT_B_DATA01
-
IOMUXC_GPIO_B1_12_NETC_PINMUX_ETH4_RX_ER
-
IOMUXC_GPIO_B1_12_LPSPI6_PCS0
-
IOMUXC_GPIO_B1_13_NETC_PINMUX_ETH1_TX_ER
-
IOMUXC_GPIO_B1_13_NETC_EMDC
-
IOMUXC_GPIO_B1_13_USDHC1_VSELECT
-
IOMUXC_GPIO_B1_13_CCM_ENET_REF_CLK_25M
-
IOMUXC_GPIO_B1_13_GPIO6_IO13
-
IOMUXC_GPIO_B1_13_FLEXSPI1_BUS2BIT_B_DATA00
-
IOMUXC_GPIO_B1_13_NETC_PINMUX_ETH4_TX_ER
-
IOMUXC_GPIO_B1_13_LPSPI6_SCK
-
IOMUXC_GPIO_B1_13_SAI4_TX_DATA03
-
IOMUXC_GPIO_B2_00_NETC_ETH2_SLV_MDIO
-
IOMUXC_GPIO_B2_00_ECAT_CLK_ECAT_CLK25
-
IOMUXC_GPIO_B2_00_NETC_ETH1_CRS
-
IOMUXC_GPIO_B2_00_SEMC_CSX03
-
IOMUXC_GPIO_B2_00_LPIT3_TRIGGER00
-
IOMUXC_GPIO_B2_00_SAI4_MCLK
-
IOMUXC_GPIO_B2_00_GPIO6_IO14
-
IOMUXC_GPIO_B2_00_NETC_ETH4_CRS
-
IOMUXC_GPIO_B2_00_LPSPI6_SDI
-
IOMUXC_GPIO_B2_01_NETC_ETH2_SLV_MDC
-
IOMUXC_GPIO_B2_01_NETC_PINMUX_ETH2_RX_ER
-
IOMUXC_GPIO_B2_01_ECAT_RX_ER_1
-
IOMUXC_GPIO_B2_01_NETC_ETH1_COL
-
IOMUXC_GPIO_B2_01_LPIT3_TRIGGER01
-
IOMUXC_GPIO_B2_01_SAI4_TX_BCLK
-
IOMUXC_GPIO_B2_01_GPIO6_IO15
-
IOMUXC_GPIO_B2_01_FLEXSPI1_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_B2_01_NETC_ETH4_COL
-
IOMUXC_GPIO_B2_01_LPSPI6_SDO
-
IOMUXC_GPIO_B2_02_EWM_EWM_OUT_B
-
IOMUXC_GPIO_B2_02_NETC_PINMUX_ETH2_RXD02
-
IOMUXC_GPIO_B2_02_ECAT_RX_DATA2_1
-
IOMUXC_GPIO_B2_02_LPIT3_TRIGGER02
-
IOMUXC_GPIO_B2_02_NETC_EMDIO
-
IOMUXC_GPIO_B2_02_SAI4_TX_SYNC
-
IOMUXC_GPIO_B2_02_GPIO6_IO16
-
IOMUXC_GPIO_B2_02_FLEXSPI1_BUS2BIT_B_SCLK
-
IOMUXC_GPIO_B2_02_CCM_ENET_REF_CLK_25M
-
IOMUXC_GPIO_B2_03_XSPI_SLV_DATA04
-
IOMUXC_GPIO_B2_03_NETC_PINMUX_ETH2_RXD03
-
IOMUXC_GPIO_B2_03_ECAT_RX_DATA3_1
-
IOMUXC_GPIO_B2_03_LPIT3_TRIGGER03
-
IOMUXC_GPIO_B2_03_NETC_EMDC
-
IOMUXC_GPIO_B2_03_SAI4_TX_DATA00
-
IOMUXC_GPIO_B2_03_GPIO6_IO17
-
IOMUXC_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04
-
IOMUXC_GPIO_B2_04_XSPI_SLV_DATA05
-
IOMUXC_GPIO_B2_04_NETC_PINMUX_ETH2_TXD02
-
IOMUXC_GPIO_B2_04_ECAT_TX_DATA2_1
-
IOMUXC_GPIO_B2_04_SINC1_MOD_CLK0
-
IOMUXC_GPIO_B2_04_SINC2_MOD_CLK0
-
IOMUXC_GPIO_B2_04_SINC3_MOD_CLK0
-
IOMUXC_GPIO_B2_04_SAI4_RX_SYNC
-
IOMUXC_GPIO_B2_04_GPIO6_IO18
-
IOMUXC_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05
-
IOMUXC_GPIO_B2_04_TPM3_EXTCLK
-
IOMUXC_GPIO_B2_05_XSPI_SLV_DATA06
-
IOMUXC_GPIO_B2_05_NETC_PINMUX_ETH2_TXD03
-
IOMUXC_GPIO_B2_05_ECAT_TX_DATA3_1
-
IOMUXC_GPIO_B2_05_SINC1_MOD_CLK1
-
IOMUXC_GPIO_B2_05_SINC2_MOD_CLK1
-
IOMUXC_GPIO_B2_05_SINC3_MOD_CLK1
-
IOMUXC_GPIO_B2_05_SAI4_RX_BCLK
-
IOMUXC_GPIO_B2_05_GPIO6_IO19
-
IOMUXC_GPIO_B2_05_MIC_CLK
-
IOMUXC_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06
-
IOMUXC_GPIO_B2_05_TPM3_CH00
-
IOMUXC_GPIO_B2_06_XSPI_SLV_DATA07
-
IOMUXC_GPIO_B2_06_NETC_PINMUX_ETH2_TXD00
-
IOMUXC_GPIO_B2_06_ECAT_TX_DATA0_1
-
IOMUXC_GPIO_B2_06_SINC1_MOD_CLK2
-
IOMUXC_GPIO_B2_06_SINC2_MOD_CLK2
-
IOMUXC_GPIO_B2_06_SINC3_MOD_CLK2
-
IOMUXC_GPIO_B2_06_LPUART6_DSR_B
-
IOMUXC_GPIO_B2_06_SAI4_RX_DATA00
-
IOMUXC_GPIO_B2_06_GPIO6_IO20
-
IOMUXC_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07
-
IOMUXC_GPIO_B2_06_TPM3_CH01
-
IOMUXC_GPIO_B2_06_LPUART11_TX
-
IOMUXC_GPIO_B2_07_XSPI_SLV_DQS
-
IOMUXC_GPIO_B2_07_NETC_PINMUX_ETH2_TXD01
-
IOMUXC_GPIO_B2_07_ECAT_TX_DATA1_1
-
IOMUXC_GPIO_B2_07_QTIMER5_TIMER0
-
IOMUXC_GPIO_B2_07_LPUART6_DCD_B
-
IOMUXC_GPIO_B2_07_SAI4_TX_DATA01
-
IOMUXC_GPIO_B2_07_GPIO6_IO21
-
IOMUXC_GPIO_B2_07_SAI4_RX_DATA01
-
IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS
-
IOMUXC_GPIO_B2_07_TPM3_CH02
-
IOMUXC_GPIO_B2_07_LPUART11_RX
-
IOMUXC_GPIO_B2_08_XSPI_SLV_CLK
-
IOMUXC_GPIO_B2_08_NETC_PINMUX_ETH2_TX_EN
-
IOMUXC_GPIO_B2_08_ECAT_TX_EN_1
-
IOMUXC_GPIO_B2_08_QTIMER5_TIMER1
-
IOMUXC_GPIO_B2_08_SINC2_EMCLK02
-
IOMUXC_GPIO_B2_08_LPUART6_RI_B
-
IOMUXC_GPIO_B2_08_GPIO6_IO22
-
IOMUXC_GPIO_B2_08_LPI2C6_SCL
-
IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK
-
IOMUXC_GPIO_B2_08_TPM3_CH03
-
IOMUXC_GPIO_B2_08_SPDIF_IN
-
IOMUXC_GPIO_B2_09_XSPI_SLV_CS
-
IOMUXC_GPIO_B2_09_NETC_PINMUX_ETH2_TX_CLK
-
IOMUXC_GPIO_B2_09_ECAT_TX_CLK_1
-
IOMUXC_GPIO_B2_09_QTIMER5_TIMER2
-
IOMUXC_GPIO_B2_09_SINC2_EMBIT02
-
IOMUXC_GPIO_B2_09_LPUART6_DTR_B
-
IOMUXC_GPIO_B2_09_GPIO6_IO23
-
IOMUXC_GPIO_B2_09_LPI2C6_SDA
-
IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B
-
IOMUXC_GPIO_B2_09_TPM4_EXTCLK
-
IOMUXC_GPIO_B2_09_SPDIF_OUT
-
IOMUXC_GPIO_B2_10_XSPI_SLV_DATA00
-
IOMUXC_GPIO_B2_10_NETC_PINMUX_ETH2_RXD00
-
IOMUXC_GPIO_B2_10_ECAT_RX_DATA0_1
-
IOMUXC_GPIO_B2_10_MIC_BITSTREAM00
-
IOMUXC_GPIO_B2_10_SINC2_EMCLK03
-
IOMUXC_GPIO_B2_10_CAN3_TX
-
IOMUXC_GPIO_B2_10_LPUART8_CTS_B
-
IOMUXC_GPIO_B2_10_LPUART6_TX
-
IOMUXC_GPIO_B2_10_GPIO6_IO24
-
IOMUXC_GPIO_B2_10_LPI2C4_SCL
-
IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00
-
IOMUXC_GPIO_B2_10_TPM4_CH00
-
IOMUXC_GPIO_B2_10_LPSPI4_SCK
-
IOMUXC_GPIO_B2_11_XSPI_SLV_DATA01
-
IOMUXC_GPIO_B2_11_NETC_PINMUX_ETH2_RXD01
-
IOMUXC_GPIO_B2_11_ECAT_RX_DATA1_1
-
IOMUXC_GPIO_B2_11_MIC_BITSTREAM01
-
IOMUXC_GPIO_B2_11_SINC2_EMBIT03
-
IOMUXC_GPIO_B2_11_CAN3_RX
-
IOMUXC_GPIO_B2_11_LPUART8_RTS_B
-
IOMUXC_GPIO_B2_11_LPUART6_RX
-
IOMUXC_GPIO_B2_11_GPIO6_IO25
-
IOMUXC_GPIO_B2_11_LPI2C4_SDA
-
IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01
-
IOMUXC_GPIO_B2_11_TPM4_CH01
-
IOMUXC_GPIO_B2_11_LPSPI4_SDI
-
IOMUXC_GPIO_B2_12_MIC_BITSTREAM02
-
IOMUXC_GPIO_B2_12_SINC_FILTER_GLUE2_BREAK
-
IOMUXC_GPIO_B2_12_LPUART8_TX
-
IOMUXC_GPIO_B2_12_LPUART6_CTS_B
-
IOMUXC_GPIO_B2_12_GPIO6_IO26
-
IOMUXC_GPIO_B2_12_CAN3_TX
-
IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02
-
IOMUXC_GPIO_B2_12_TPM4_CH02
-
IOMUXC_GPIO_B2_12_LPSPI4_SDO
-
IOMUXC_GPIO_B2_12_XSPI_SLV_DATA02
-
IOMUXC_GPIO_B2_12_NETC_PINMUX_ETH2_RX_DV
-
IOMUXC_GPIO_B2_12_ECAT_RX_DV_1
-
IOMUXC_GPIO_B2_13_MIC_BITSTREAM03
-
IOMUXC_GPIO_B2_13_SINC2_EMCLK00
-
IOMUXC_GPIO_B2_13_LPUART8_RX
-
IOMUXC_GPIO_B2_13_LPUART6_RTS_B
-
IOMUXC_GPIO_B2_13_GPIO6_IO27
-
IOMUXC_GPIO_B2_13_CAN3_RX
-
IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03
-
IOMUXC_GPIO_B2_13_TPM4_CH03
-
IOMUXC_GPIO_B2_13_LPSPI4_PCS0
-
IOMUXC_GPIO_B2_13_XSPI_SLV_DATA03
-
IOMUXC_GPIO_B2_13_NETC_PINMUX_ETH2_RX_CLK
-
IOMUXC_GPIO_B2_13_ECAT_RX_CLK_1
-
IOMUXC_GPIO_AON_00_SRC_BOOT_MODE00
-
IOMUXC_GPIO_AON_00_CAN1_TX
-
IOMUXC_GPIO_AON_00_LPTMR1_ALT1
-
IOMUXC_GPIO_AON_00_GPIO1_IO00
-
IOMUXC_GPIO_AON_00_LPUART2_TX
-
IOMUXC_GPIO_AON_00_TPM1_EXTCLK
-
IOMUXC_GPIO_AON_01_SRC_BOOT_MODE01
-
IOMUXC_GPIO_AON_01_CAN1_RX
-
IOMUXC_GPIO_AON_01_LPTMR1_ALT2
-
IOMUXC_GPIO_AON_01_GPIO1_IO01
-
IOMUXC_GPIO_AON_01_LPUART2_RX
-
IOMUXC_GPIO_AON_01_TPM1_CH00
-
IOMUXC_GPIO_AON_02_SRC_BOOT_MODE02
-
IOMUXC_GPIO_AON_02_CAN3_TX
-
IOMUXC_GPIO_AON_02_LPSPI2_PCS3
-
IOMUXC_GPIO_AON_02_LPSPI2_SDO
-
IOMUXC_GPIO_AON_02_LPTMR1_ALT3
-
IOMUXC_GPIO_AON_02_GPIO1_IO02
-
IOMUXC_GPIO_AON_02_LPUART2_RTS_B
-
IOMUXC_GPIO_AON_02_TPM1_CH01
-
IOMUXC_GPIO_AON_02_ECAT_CLK_ECAT_CLK25
-
IOMUXC_GPIO_AON_03_CAN3_RX
-
IOMUXC_GPIO_AON_03_LPSPI1_PCS1
-
IOMUXC_GPIO_AON_03_LPSPI2_SDI
-
IOMUXC_GPIO_AON_03_LPSPI1_PCS3
-
IOMUXC_GPIO_AON_03_GPIO1_IO03
-
IOMUXC_GPIO_AON_03_LPUART2_CTS_B
-
IOMUXC_GPIO_AON_03_TPM1_CH02
-
IOMUXC_GPIO_AON_03_ECAT_LED_STATE_RUN
-
IOMUXC_GPIO_AON_04_ECAT_LED_RUN
-
IOMUXC_GPIO_AON_04_LPSPI1_SCK
-
IOMUXC_GPIO_AON_04_SAI1_TX_DATA00
-
IOMUXC_GPIO_AON_04_SAI1_RX_DATA01
-
IOMUXC_GPIO_AON_04_GPIO1_IO04
-
IOMUXC_GPIO_AON_04_LPUART7_CTS_B
-
IOMUXC_GPIO_AON_04_TPM1_CH03
-
IOMUXC_GPIO_AON_05_LPSPI1_PCS0
-
IOMUXC_GPIO_AON_05_SAI1_TX_SYNC
-
IOMUXC_GPIO_AON_05_GPIO1_IO05
-
IOMUXC_GPIO_AON_05_LPUART7_RTS_B
-
IOMUXC_GPIO_AON_05_NMI_GLUE_NMI
-
IOMUXC_GPIO_AON_05_ECAT_LED_ERR
-
IOMUXC_GPIO_AON_06_LPSPI1_SDO
-
IOMUXC_GPIO_AON_06_I3C1_PUR
-
IOMUXC_GPIO_AON_06_SAI1_TX_BCLK
-
IOMUXC_GPIO_AON_06_LPI2C1_SDA
-
IOMUXC_GPIO_AON_06_GPIO1_IO06
-
IOMUXC_GPIO_AON_06_CAN1_TX
-
IOMUXC_GPIO_AON_06_ECAT_SDA
-
IOMUXC_GPIO_AON_07_ECAT_SCL
-
IOMUXC_GPIO_AON_07_LPSPI1_SDI
-
IOMUXC_GPIO_AON_07_SAI1_MCLK
-
IOMUXC_GPIO_AON_07_LPI2C1_SCL
-
IOMUXC_GPIO_AON_07_GPIO1_IO07
-
IOMUXC_GPIO_AON_07_CAN1_RX
-
IOMUXC_GPIO_AON_08_LPUART1_TX
-
IOMUXC_GPIO_AON_08_S400_TX
-
IOMUXC_GPIO_AON_08_SAI1_RX_DATA00
-
IOMUXC_GPIO_AON_08_SAI1_TX_DATA01
-
IOMUXC_GPIO_AON_08_GPIO1_IO08
-
IOMUXC_GPIO_AON_08_LPI2C1_SDA
-
IOMUXC_GPIO_AON_08_LPSPI1_PCS1
-
IOMUXC_GPIO_AON_08_ECAT_LINK_ACT00
-
IOMUXC_GPIO_AON_09_LPUART1_RX
-
IOMUXC_GPIO_AON_09_S400_RX
-
IOMUXC_GPIO_AON_09_SAI1_RX_BCLK
-
IOMUXC_GPIO_AON_09_LPIT1_TRIGGER00
-
IOMUXC_GPIO_AON_09_GPIO1_IO09
-
IOMUXC_GPIO_AON_09_LPI2C1_SCL
-
IOMUXC_GPIO_AON_09_LPSPI1_PCS2
-
IOMUXC_GPIO_AON_09_ECAT_LINK_ACT01
-
IOMUXC_GPIO_AON_10_JTAG_MUX_TRSTB
-
IOMUXC_GPIO_AON_10_LPSPI2_PCS0
-
IOMUXC_GPIO_AON_10_SAI1_RX_SYNC
-
IOMUXC_GPIO_AON_10_LPIT1_TRIGGER01
-
IOMUXC_GPIO_AON_10_TPM2_EXTCLK
-
IOMUXC_GPIO_AON_10_GPIO1_IO10
-
IOMUXC_GPIO_AON_10_LPI2C1_SCLS
-
IOMUXC_GPIO_AON_11_JTAG_MUX_TDO
-
IOMUXC_GPIO_AON_11_LPUART1_CTS_B
-
IOMUXC_GPIO_AON_11_LPIT1_TRIGGER02
-
IOMUXC_GPIO_AON_11_TPM2_CH00
-
IOMUXC_GPIO_AON_11_GPIO1_IO11
-
IOMUXC_GPIO_AON_11_LPI2C1_SDAS
-
IOMUXC_GPIO_AON_12_JTAG_MUX_TDI
-
IOMUXC_GPIO_AON_12_LPUART1_RTS_B
-
IOMUXC_GPIO_AON_12_LPIT1_TRIGGER03
-
IOMUXC_GPIO_AON_12_TPM2_CH01
-
IOMUXC_GPIO_AON_12_GPIO1_IO12
-
IOMUXC_GPIO_AON_12_LPI2C1_HREQ
-
IOMUXC_GPIO_AON_12_LPSPI1_SCK
-
IOMUXC_GPIO_AON_13_JTAG_MUX_TCK
-
IOMUXC_GPIO_AON_13_LPUART12_CTS_B
-
IOMUXC_GPIO_AON_13_LPUART1_DSR_B
-
IOMUXC_GPIO_AON_13_TPM2_CH02
-
IOMUXC_GPIO_AON_13_GPIO1_IO13
-
IOMUXC_GPIO_AON_13_LPTMR1_ALT1
-
IOMUXC_GPIO_AON_13_LPSPI1_PCS0
-
IOMUXC_GPIO_AON_14_JTAG_MUX_TMS
-
IOMUXC_GPIO_AON_14_LPUART12_RTS_B
-
IOMUXC_GPIO_AON_14_LPUART1_DCD_B
-
IOMUXC_GPIO_AON_14_TPM2_CH03
-
IOMUXC_GPIO_AON_14_GPIO1_IO14
-
IOMUXC_GPIO_AON_14_LPTMR1_ALT2
-
IOMUXC_GPIO_AON_14_LPSPI1_SDO
-
IOMUXC_GPIO_AON_15_FLEXSPI2_BUS2BIT_B_DATA03
-
IOMUXC_GPIO_AON_15_LPSPI2_PCS1
-
IOMUXC_GPIO_AON_15_LPUART12_TX
-
IOMUXC_GPIO_AON_15_LPUART1_RI_B
-
IOMUXC_GPIO_AON_15_LPI2C2_SDA
-
IOMUXC_GPIO_AON_15_GPIO1_IO15
-
IOMUXC_GPIO_AON_15_LPTMR1_ALT3
-
IOMUXC_GPIO_AON_15_LPSPI1_SDI
-
IOMUXC_GPIO_AON_15_I3C1_SDA
-
IOMUXC_GPIO_AON_16_FLEXSPI2_BUS2BIT_B_DATA02
-
IOMUXC_GPIO_AON_16_LPSPI2_PCS0
-
IOMUXC_GPIO_AON_16_LPUART12_RX
-
IOMUXC_GPIO_AON_16_LPUART1_DTR_B
-
IOMUXC_GPIO_AON_16_LPI2C2_SCL
-
IOMUXC_GPIO_AON_16_GPIO1_IO16
-
IOMUXC_GPIO_AON_16_CAN1_TX
-
IOMUXC_GPIO_AON_16_LPUART7_CTS_B
-
IOMUXC_GPIO_AON_16_I3C1_SCL
-
IOMUXC_GPIO_AON_17_FLEXSPI2_BUS2BIT_B_DATA01
-
IOMUXC_GPIO_AON_17_LPSPI2_SDI
-
IOMUXC_GPIO_AON_17_LPUART7_TX
-
IOMUXC_GPIO_AON_17_LPI2C2_SDA
-
IOMUXC_GPIO_AON_17_LPUART1_DSR_B
-
IOMUXC_GPIO_AON_17_GPIO1_IO17
-
IOMUXC_GPIO_AON_17_CAN1_RX
-
IOMUXC_GPIO_AON_18_FLEXSPI2_BUS2BIT_B_DATA00
-
IOMUXC_GPIO_AON_18_LPSPI2_SDO
-
IOMUXC_GPIO_AON_18_LPUART7_RX
-
IOMUXC_GPIO_AON_18_LPI2C2_SCL
-
IOMUXC_GPIO_AON_18_LPUART1_DCD_B
-
IOMUXC_GPIO_AON_18_GPIO1_IO18
-
IOMUXC_GPIO_AON_18_CAN3_TX
-
IOMUXC_GPIO_AON_19_FLEXSPI2_BUS2BIT_B_SCLK
-
IOMUXC_GPIO_AON_19_LPSPI2_SCK
-
IOMUXC_GPIO_AON_19_FLEXSPI2_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_AON_19_LPUART1_CTS_B
-
IOMUXC_GPIO_AON_19_GPIO1_IO19
-
IOMUXC_GPIO_AON_19_CAN3_RX
-
IOMUXC_GPIO_AON_19_LPUART7_RTS_B
-
IOMUXC_GPIO_AON_19_LPUART12_TX
-
IOMUXC_GPIO_AON_19_ADC1_CONV_D00
-
IOMUXC_GPIO_AON_20_FLEXSPI2_BUS2BIT_B_DQS
-
IOMUXC_GPIO_AON_20_FLEXSPI2_BUS2BIT_A_SS1_B
-
IOMUXC_GPIO_AON_20_LPI2C1_SDA
-
IOMUXC_GPIO_AON_20_I3C1_SDA
-
IOMUXC_GPIO_AON_20_LPUART1_RTS_B
-
IOMUXC_GPIO_AON_20_GPIO1_IO20
-
IOMUXC_GPIO_AON_20_LPUART12_RX
-
IOMUXC_GPIO_AON_20_ADC1_CONV_D01
-
IOMUXC_GPIO_AON_21_ADC1_CONV_D02
-
IOMUXC_GPIO_AON_21_FLEXSPI2_BUS2BIT_B_SS0_B
-
IOMUXC_GPIO_AON_21_LPSPI2_PCS1
-
IOMUXC_GPIO_AON_21_LPI2C1_SCL
-
IOMUXC_GPIO_AON_21_I3C1_SCL
-
IOMUXC_GPIO_AON_21_SAI1_TX_DATA00
-
IOMUXC_GPIO_AON_21_GPIO1_IO21
-
IOMUXC_GPIO_AON_21_FLEXSPI2_BUS2BIT_A_DQS
-
IOMUXC_GPIO_AON_21_SAI1_RX_DATA01
-
IOMUXC_GPIO_AON_22_CCMSRCGPC_CCMOBS1
-
IOMUXC_GPIO_AON_22_ADC1_CONV_D03
-
IOMUXC_GPIO_AON_22_FLEXSPI2_BUS2BIT_A_SS0_B
-
IOMUXC_GPIO_AON_22_LPI2C2_SDA
-
IOMUXC_GPIO_AON_22_LPUART7_TX
-
IOMUXC_GPIO_AON_22_LPUART12_CTS_B
-
IOMUXC_GPIO_AON_22_SAI1_TX_SYNC
-
IOMUXC_GPIO_AON_22_GPIO1_IO22
-
IOMUXC_GPIO_AON_22_LPSPI2_SCK
-
IOMUXC_GPIO_AON_23_FLEXSPI2_BUS2BIT_A_SCLK
-
IOMUXC_GPIO_AON_23_LPI2C2_SCL
-
IOMUXC_GPIO_AON_23_LPUART7_RX
-
IOMUXC_GPIO_AON_23_LPUART12_RTS_B
-
IOMUXC_GPIO_AON_23_SAI1_TX_BCLK
-
IOMUXC_GPIO_AON_23_GPIO1_IO23
-
IOMUXC_GPIO_AON_23_LPSPI2_SDO
-
IOMUXC_GPIO_AON_23_CCMSRCGPC_CCMOBS2
-
IOMUXC_GPIO_AON_23_ADC1_CONV_D04
-
IOMUXC_GPIO_AON_24_ADC1_CONV_D05
-
IOMUXC_GPIO_AON_24_FLEXSPI2_BUS2BIT_A_DATA00
-
IOMUXC_GPIO_AON_24_LPI2C1_SDA
-
IOMUXC_GPIO_AON_24_LPUART2_RTS_B
-
IOMUXC_GPIO_AON_24_LPUART7_CTS_B
-
IOMUXC_GPIO_AON_24_SAI1_MCLK
-
IOMUXC_GPIO_AON_24_GPIO1_IO24
-
IOMUXC_GPIO_AON_24_LPSPI2_SDI
-
IOMUXC_GPIO_AON_25_ADC1_CONV_D06
-
IOMUXC_GPIO_AON_25_FLEXSPI2_BUS2BIT_A_DATA01
-
IOMUXC_GPIO_AON_25_LPI2C1_SCL
-
IOMUXC_GPIO_AON_25_LPUART2_CTS_B
-
IOMUXC_GPIO_AON_25_LPUART7_RTS_B
-
IOMUXC_GPIO_AON_25_SAI1_RX_DATA00
-
IOMUXC_GPIO_AON_25_GPIO1_IO25
-
IOMUXC_GPIO_AON_25_LPSPI2_PCS0
-
IOMUXC_GPIO_AON_25_SAI1_TX_DATA01
-
IOMUXC_GPIO_AON_26_FLEXSPI2_BUS2BIT_A_DATA02
-
IOMUXC_GPIO_AON_26_LPSPI2_PCS2
-
IOMUXC_GPIO_AON_26_LPUART2_TX
-
IOMUXC_GPIO_AON_26_SAI1_RX_BCLK
-
IOMUXC_GPIO_AON_26_GPIO1_IO26
-
IOMUXC_GPIO_AON_26_ADC1_CONV_D07
-
IOMUXC_GPIO_AON_27_ADC1_CONV_RDY_CLK
-
IOMUXC_GPIO_AON_27_FLEXSPI2_BUS2BIT_A_DATA03
-
IOMUXC_GPIO_AON_27_LPSPI2_PCS3
-
IOMUXC_GPIO_AON_27_LPUART2_RX
-
IOMUXC_GPIO_AON_27_SAI1_RX_SYNC
-
IOMUXC_GPIO_AON_27_GPIO1_IO27
-
IOMUXC_GPIO_AON_27_EWM_EWM_OUT_B
-
IOMUXC_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_A_DQS
-
IOMUXC_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_B_DQS
-
IOMUXC_GPIO_AON_28_DUMMY_GPIO1_IO28
-
IOMUXC_GPR_SAIMCLK_LOWBITMASK
-
IOMUXC_GPR_SAIMCLK_HIGHBITMASK
-
static inline void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)
Sets the IOMUXC pin mux mode.
This is an example to set the PTA6 as the lpuart0_tx:
IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
This is an example to set the PTA0 as GPIOA0:
IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
Note
The first five parameters can be filled with the pin function ID macros.
- Parameters:
muxRegister – The pin mux register.
muxMode – The pin mux mode.
inputRegister – The select input register.
inputDaisy – The input daisy.
configRegister – The config register.
inputOnfield – Software input on field.
-
static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)
Sets the IOMUXC pin configuration.
This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
Note
The previous five parameters can be filled with the pin function ID macros.
- Parameters:
muxRegister – The pin mux register.
muxMode – The pin mux mode.
inputRegister – The select input register.
inputDaisy – The input daisy.
configRegister – The config register.
configValue – The pin config value.
-
FSL_IOMUXC_DRIVER_VERSION
IOMUXC driver version 2.0.0.
-
FSL_COMPONENT_ID
KPP: KeyPad Port Driver
-
void KPP_Init(KPP_Type *base, kpp_config_t *configure)
KPP initialize. This function ungates the KPP clock and initializes KPP. This function must be called before calling any other KPP driver functions.
- Parameters:
base – KPP peripheral base address.
configure – The KPP configuration structure pointer.
-
void KPP_Deinit(KPP_Type *base)
Deinitializes the KPP module and gates the clock. This function gates the KPP clock. As a result, the KPP module doesn’t work after calling this function.
- Parameters:
base – KPP peripheral base address.
-
static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask)
Enable the interrupt.
- Parameters:
base – KPP peripheral base address.
mask – KPP interrupts to enable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.
-
static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask)
Disable the interrupt.
- Parameters:
base – KPP peripheral base address.
mask – KPP interrupts to disable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.
-
static inline uint16_t KPP_GetStatusFlag(KPP_Type *base)
Gets the KPP interrupt event status.
- Parameters:
base – KPP peripheral base address.
- Returns:
The status of the KPP. Application can use the enum type in the “kpp_interrupt_enable_t” to get the right status of the related event.
-
static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask)
Clears KPP status flag.
- Parameters:
base – KPP peripheral base address.
mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.
-
static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask)
Set KPP synchronization chain.
- Parameters:
base – KPP peripheral base address.
mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_sync_operation_t.
-
void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)
Keypad press scanning.
This function will scanning all columns and rows. so all scanning data will be stored in the data pointer.
- Parameters:
base – KPP peripheral base address.
data – KPP key press scanning data. The data buffer should be prepared with length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. for example the data[2] = 4, that means in column 1 row 2 has a key press event.
clockSrc_Hz – Source clock.
-
FSL_KPP_DRIVER_VERSION
KPP driver version.
-
enum _kpp_interrupt_enable
List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.
Values:
-
enumerator kKPP_keyDepressInterrupt
Keypad depress interrupt source
-
enumerator kKPP_keyReleaseInterrupt
Keypad release interrupt source
-
enumerator kKPP_keyDepressInterrupt
-
enum _kpp_sync_operation
Lists of KPP synchronize chain operation.
Values:
-
enumerator kKPP_ClearKeyDepressSyncChain
Keypad depress interrupt status.
-
enumerator kKPP_SetKeyReleasesSyncChain
Keypad release interrupt status.
-
enumerator kKPP_ClearKeyDepressSyncChain
-
typedef enum _kpp_interrupt_enable kpp_interrupt_enable_t
List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.
-
typedef enum _kpp_sync_operation kpp_sync_operation_t
Lists of KPP synchronize chain operation.
-
typedef struct _kpp_config kpp_config_t
Lists of KPP status.
-
KPP_KEYPAD_COLUMNNUM_MAX
-
KPP_KEYPAD_ROWNUM_MAX
-
struct _kpp_config
- #include <fsl_kpp.h>
Lists of KPP status.
Public Members
-
uint8_t activeRow
The row number: bit 7 ~ 0 represents the row 7 ~ 0.
-
uint8_t activeColumn
The column number: bit 7 ~ 0 represents the column 7 ~ 0.
-
uint16_t interrupt
KPP interrupt source. A logical OR of “kpp_interrupt_enable_t”.
-
uint8_t activeRow
Common Driver
-
FSL_COMMON_DRIVER_VERSION
common driver version.
-
DEBUG_CONSOLE_DEVICE_TYPE_NONE
No debug console.
-
DEBUG_CONSOLE_DEVICE_TYPE_UART
Debug console based on UART.
-
DEBUG_CONSOLE_DEVICE_TYPE_LPUART
Debug console based on LPUART.
-
DEBUG_CONSOLE_DEVICE_TYPE_LPSCI
Debug console based on LPSCI.
-
DEBUG_CONSOLE_DEVICE_TYPE_USBCDC
Debug console based on USBCDC.
-
DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM
Debug console based on FLEXCOMM.
-
DEBUG_CONSOLE_DEVICE_TYPE_IUART
Debug console based on i.MX UART.
-
DEBUG_CONSOLE_DEVICE_TYPE_VUSART
Debug console based on LPC_VUSART.
-
DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART
Debug console based on LPC_USART.
-
DEBUG_CONSOLE_DEVICE_TYPE_SWO
Debug console based on SWO.
-
DEBUG_CONSOLE_DEVICE_TYPE_QSCI
Debug console based on QSCI.
-
MIN(a, b)
Computes the minimum of a and b.
-
MAX(a, b)
Computes the maximum of a and b.
-
UINT16_MAX
Max value of uint16_t type.
-
UINT32_MAX
Max value of uint32_t type.
-
SDK_ATOMIC_LOCAL_ADD(addr, val)
Add value val from the variable at address address.
-
SDK_ATOMIC_LOCAL_SUB(addr, val)
Subtract value val to the variable at address address.
-
SDK_ATOMIC_LOCAL_SET(addr, bits)
Set the bits specifiled by bits to the variable at address address.
-
SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
Clear the bits specifiled by bits to the variable at address address.
-
SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
Toggle the bits specifiled by bits to the variable at address address.
-
SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.
-
SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)
For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .
-
SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)
For the variable at address address, set as newValue value and return old value.
-
USEC_TO_COUNT(us, clockFreqInHz)
Macro to convert a microsecond period to raw count value
-
COUNT_TO_USEC(count, clockFreqInHz)
Macro to convert a raw count value to microsecond
-
MSEC_TO_COUNT(ms, clockFreqInHz)
Macro to convert a millisecond period to raw count value
-
COUNT_TO_MSEC(count, clockFreqInHz)
Macro to convert a raw count value to millisecond
-
SDK_ISR_EXIT_BARRIER
-
SDK_L1DCACHE_ALIGN(var)
Macro to define a variable with L1 d-cache line size alignment
-
SDK_SIZEALIGN(var, alignbytes)
Macro to define a variable with L2 cache line size alignment
Macro to change a value to a given size aligned value
-
CACHE_LINE_DATA
-
enum _status_groups
Status group numbers.
Values:
-
enumerator kStatusGroup_Generic
Group number for generic status codes.
-
enumerator kStatusGroup_FLASH
Group number for FLASH status codes.
-
enumerator kStatusGroup_LPSPI
Group number for LPSPI status codes.
-
enumerator kStatusGroup_FLEXIO_SPI
Group number for FLEXIO SPI status codes.
-
enumerator kStatusGroup_DSPI
Group number for DSPI status codes.
-
enumerator kStatusGroup_FLEXIO_UART
Group number for FLEXIO UART status codes.
-
enumerator kStatusGroup_FLEXIO_I2C
Group number for FLEXIO I2C status codes.
-
enumerator kStatusGroup_LPI2C
Group number for LPI2C status codes.
-
enumerator kStatusGroup_UART
Group number for UART status codes.
-
enumerator kStatusGroup_I2C
Group number for UART status codes.
-
enumerator kStatusGroup_LPSCI
Group number for LPSCI status codes.
-
enumerator kStatusGroup_LPUART
Group number for LPUART status codes.
-
enumerator kStatusGroup_SPI
Group number for SPI status code.
-
enumerator kStatusGroup_XRDC
Group number for XRDC status code.
-
enumerator kStatusGroup_SEMA42
Group number for SEMA42 status code.
-
enumerator kStatusGroup_SDHC
Group number for SDHC status code
-
enumerator kStatusGroup_SDMMC
Group number for SDMMC status code
-
enumerator kStatusGroup_SAI
Group number for SAI status code
-
enumerator kStatusGroup_MCG
Group number for MCG status codes.
-
enumerator kStatusGroup_SCG
Group number for SCG status codes.
-
enumerator kStatusGroup_SDSPI
Group number for SDSPI status codes.
-
enumerator kStatusGroup_FLEXIO_I2S
Group number for FLEXIO I2S status codes
-
enumerator kStatusGroup_FLEXIO_MCULCD
Group number for FLEXIO LCD status codes
-
enumerator kStatusGroup_FLASHIAP
Group number for FLASHIAP status codes
-
enumerator kStatusGroup_FLEXCOMM_I2C
Group number for FLEXCOMM I2C status codes
-
enumerator kStatusGroup_I2S
Group number for I2S status codes
-
enumerator kStatusGroup_IUART
Group number for IUART status codes
-
enumerator kStatusGroup_CSI
Group number for CSI status codes
-
enumerator kStatusGroup_MIPI_DSI
Group number for MIPI DSI status codes
-
enumerator kStatusGroup_SDRAMC
Group number for SDRAMC status codes.
-
enumerator kStatusGroup_POWER
Group number for POWER status codes.
-
enumerator kStatusGroup_ENET
Group number for ENET status codes.
-
enumerator kStatusGroup_PHY
Group number for PHY status codes.
-
enumerator kStatusGroup_TRGMUX
Group number for TRGMUX status codes.
-
enumerator kStatusGroup_SMARTCARD
Group number for SMARTCARD status codes.
-
enumerator kStatusGroup_LMEM
Group number for LMEM status codes.
-
enumerator kStatusGroup_QSPI
Group number for QSPI status codes.
-
enumerator kStatusGroup_DMA
Group number for DMA status codes.
-
enumerator kStatusGroup_EDMA
Group number for EDMA status codes.
-
enumerator kStatusGroup_DMAMGR
Group number for DMAMGR status codes.
-
enumerator kStatusGroup_FLEXCAN
Group number for FlexCAN status codes.
-
enumerator kStatusGroup_LTC
Group number for LTC status codes.
-
enumerator kStatusGroup_FLEXIO_CAMERA
Group number for FLEXIO CAMERA status codes.
-
enumerator kStatusGroup_LPC_SPI
Group number for LPC_SPI status codes.
-
enumerator kStatusGroup_LPC_USART
Group number for LPC_USART status codes.
-
enumerator kStatusGroup_DMIC
Group number for DMIC status codes.
-
enumerator kStatusGroup_SDIF
Group number for SDIF status codes.
-
enumerator kStatusGroup_SPIFI
Group number for SPIFI status codes.
-
enumerator kStatusGroup_OTP
Group number for OTP status codes.
-
enumerator kStatusGroup_MCAN
Group number for MCAN status codes.
-
enumerator kStatusGroup_CAAM
Group number for CAAM status codes.
-
enumerator kStatusGroup_ECSPI
Group number for ECSPI status codes.
-
enumerator kStatusGroup_USDHC
Group number for USDHC status codes.
-
enumerator kStatusGroup_LPC_I2C
Group number for LPC_I2C status codes.
-
enumerator kStatusGroup_DCP
Group number for DCP status codes.
-
enumerator kStatusGroup_MSCAN
Group number for MSCAN status codes.
-
enumerator kStatusGroup_ESAI
Group number for ESAI status codes.
-
enumerator kStatusGroup_FLEXSPI
Group number for FLEXSPI status codes.
-
enumerator kStatusGroup_MMDC
Group number for MMDC status codes.
-
enumerator kStatusGroup_PDM
Group number for MIC status codes.
-
enumerator kStatusGroup_SDMA
Group number for SDMA status codes.
-
enumerator kStatusGroup_ICS
Group number for ICS status codes.
-
enumerator kStatusGroup_SPDIF
Group number for SPDIF status codes.
-
enumerator kStatusGroup_LPC_MINISPI
Group number for LPC_MINISPI status codes.
-
enumerator kStatusGroup_HASHCRYPT
Group number for Hashcrypt status codes
-
enumerator kStatusGroup_LPC_SPI_SSP
Group number for LPC_SPI_SSP status codes.
-
enumerator kStatusGroup_I3C
Group number for I3C status codes
-
enumerator kStatusGroup_LPC_I2C_1
Group number for LPC_I2C_1 status codes.
-
enumerator kStatusGroup_NOTIFIER
Group number for NOTIFIER status codes.
-
enumerator kStatusGroup_DebugConsole
Group number for debug console status codes.
-
enumerator kStatusGroup_SEMC
Group number for SEMC status codes.
-
enumerator kStatusGroup_ApplicationRangeStart
Starting number for application groups.
-
enumerator kStatusGroup_IAP
Group number for IAP status codes
-
enumerator kStatusGroup_SFA
Group number for SFA status codes
-
enumerator kStatusGroup_SPC
Group number for SPC status codes.
-
enumerator kStatusGroup_PUF
Group number for PUF status codes.
-
enumerator kStatusGroup_TOUCH_PANEL
Group number for touch panel status codes
-
enumerator kStatusGroup_VBAT
Group number for VBAT status codes
-
enumerator kStatusGroup_XSPI
Group number for XSPI status codes
-
enumerator kStatusGroup_PNGDEC
Group number for PNGDEC status codes
-
enumerator kStatusGroup_JPEGDEC
Group number for JPEGDEC status codes
-
enumerator kStatusGroup_HAL_GPIO
Group number for HAL GPIO status codes.
-
enumerator kStatusGroup_HAL_UART
Group number for HAL UART status codes.
-
enumerator kStatusGroup_HAL_TIMER
Group number for HAL TIMER status codes.
-
enumerator kStatusGroup_HAL_SPI
Group number for HAL SPI status codes.
-
enumerator kStatusGroup_HAL_I2C
Group number for HAL I2C status codes.
-
enumerator kStatusGroup_HAL_FLASH
Group number for HAL FLASH status codes.
-
enumerator kStatusGroup_HAL_PWM
Group number for HAL PWM status codes.
-
enumerator kStatusGroup_HAL_RNG
Group number for HAL RNG status codes.
-
enumerator kStatusGroup_HAL_I2S
Group number for HAL I2S status codes.
-
enumerator kStatusGroup_HAL_ADC_SENSOR
Group number for HAL ADC SENSOR status codes.
-
enumerator kStatusGroup_TIMERMANAGER
Group number for TiMER MANAGER status codes.
-
enumerator kStatusGroup_SERIALMANAGER
Group number for SERIAL MANAGER status codes.
-
enumerator kStatusGroup_LED
Group number for LED status codes.
-
enumerator kStatusGroup_BUTTON
Group number for BUTTON status codes.
-
enumerator kStatusGroup_EXTERN_EEPROM
Group number for EXTERN EEPROM status codes.
-
enumerator kStatusGroup_SHELL
Group number for SHELL status codes.
-
enumerator kStatusGroup_MEM_MANAGER
Group number for MEM MANAGER status codes.
-
enumerator kStatusGroup_LIST
Group number for List status codes.
-
enumerator kStatusGroup_OSA
Group number for OSA status codes.
-
enumerator kStatusGroup_COMMON_TASK
Group number for Common task status codes.
-
enumerator kStatusGroup_MSG
Group number for messaging status codes.
-
enumerator kStatusGroup_SDK_OCOTP
Group number for OCOTP status codes.
-
enumerator kStatusGroup_SDK_FLEXSPINOR
Group number for FLEXSPINOR status codes.
-
enumerator kStatusGroup_CODEC
Group number for codec status codes.
-
enumerator kStatusGroup_ASRC
Group number for codec status ASRC.
-
enumerator kStatusGroup_OTFAD
Group number for codec status codes.
-
enumerator kStatusGroup_SDIOSLV
Group number for SDIOSLV status codes.
-
enumerator kStatusGroup_MECC
Group number for MECC status codes.
-
enumerator kStatusGroup_ENET_QOS
Group number for ENET_QOS status codes.
-
enumerator kStatusGroup_LOG
Group number for LOG status codes.
-
enumerator kStatusGroup_I3CBUS
Group number for I3CBUS status codes.
-
enumerator kStatusGroup_QSCI
Group number for QSCI status codes.
-
enumerator kStatusGroup_ELEMU
Group number for ELEMU status codes.
-
enumerator kStatusGroup_QUEUEDSPI
Group number for QSPI status codes.
-
enumerator kStatusGroup_POWER_MANAGER
Group number for POWER_MANAGER status codes.
-
enumerator kStatusGroup_IPED
Group number for IPED status codes.
-
enumerator kStatusGroup_ELS_PKC
Group number for ELS PKC status codes.
-
enumerator kStatusGroup_CSS_PKC
Group number for CSS PKC status codes.
-
enumerator kStatusGroup_HOSTIF
Group number for HOSTIF status codes.
-
enumerator kStatusGroup_CLIF
Group number for CLIF status codes.
-
enumerator kStatusGroup_BMA
Group number for BMA status codes.
-
enumerator kStatusGroup_NETC
Group number for NETC status codes.
-
enumerator kStatusGroup_ELE
Group number for ELE status codes.
-
enumerator kStatusGroup_GLIKEY
Group number for GLIKEY status codes.
-
enumerator kStatusGroup_AON_POWER
Group number for AON_POWER status codes.
-
enumerator kStatusGroup_AON_COMMON
Group number for AON_COMMON status codes.
-
enumerator kStatusGroup_ENDAT3
Group number for ENDAT3 status codes.
-
enumerator kStatusGroup_HIPERFACE
Group number for HIPERFACE status codes.
-
enumerator kStatusGroup_Generic
Generic status return codes.
Values:
-
enumerator kStatus_Success
Generic status for Success.
-
enumerator kStatus_Fail
Generic status for Fail.
-
enumerator kStatus_ReadOnly
Generic status for read only failure.
-
enumerator kStatus_OutOfRange
Generic status for out of range access.
-
enumerator kStatus_InvalidArgument
Generic status for invalid argument check.
-
enumerator kStatus_Timeout
Generic status for timeout.
-
enumerator kStatus_NoTransferInProgress
Generic status for no transfer in progress.
-
enumerator kStatus_Busy
Generic status for module is busy.
-
enumerator kStatus_NoData
Generic status for no data is found for the operation.
-
enumerator kStatus_Success
-
typedef int32_t status_t
Type used for all status and error return values.
-
void *SDK_Malloc(size_t size, size_t alignbytes)
Allocate memory with given alignment and aligned size.
This is provided to support the dynamically allocated memory used in cache-able region.
- Parameters:
size – The length required to malloc.
alignbytes – The alignment size.
- Return values:
The – allocated memory.
-
void SDK_Free(void *ptr)
Free memory.
- Parameters:
ptr – The memory to be release.
-
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.
- Parameters:
delayTime_us – Delay time in unit of microsecond.
coreClock_Hz – Core clock frequency with Hz.
-
static inline status_t EnableIRQ(IRQn_Type interrupt)
Enable specific interrupt.
Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- Parameters:
interrupt – The IRQ number.
- Return values:
kStatus_Success – Interrupt enabled successfully
kStatus_Fail – Failed to enable the interrupt
-
static inline status_t DisableIRQ(IRQn_Type interrupt)
Disable specific interrupt.
Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- Parameters:
interrupt – The IRQ number.
- Return values:
kStatus_Success – Interrupt disabled successfully
kStatus_Fail – Failed to disable the interrupt
-
static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)
Enable the IRQ, and also set the interrupt priority.
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- Parameters:
interrupt – The IRQ to Enable.
priNum – Priority number set to interrupt controller register.
- Return values:
kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.
-
static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)
Set the IRQ priority.
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- Parameters:
interrupt – The IRQ to set.
priNum – Priority number set to interrupt controller register.
- Return values:
kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.
-
static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)
Clear the pending IRQ flag.
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- Parameters:
interrupt – The flag which IRQ to clear.
- Return values:
kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.
-
static inline uint32_t DisableGlobalIRQ(void)
Disable the global IRQ.
Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().
- Returns:
Current primask value.
-
static inline void EnableGlobalIRQ(uint32_t primask)
Enable the global IRQ.
Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
- Parameters:
primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().
-
static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)
-
static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)
-
FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
Macro to use the default weak IRQ handler in drivers.
-
MAKE_STATUS(group, code)
Construct a status code value from a group and code number.
-
MAKE_VERSION(major, minor, bugfix)
Construct the version number for drivers.
The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).
| Unused || Major Version || Minor Version || Bug Fix | 31 25 24 17 16 9 8 0
-
ARRAY_SIZE(x)
Computes the number of elements in an array.
-
UINT64_H(X)
Macro to get upper 32 bits of a 64-bit value
-
UINT64_L(X)
Macro to get lower 32 bits of a 64-bit value
-
SUPPRESS_FALL_THROUGH_WARNING()
For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.
-
MSDK_REG_SECURE_ADDR(x)
Convert the register address to the one used in secure mode.
-
MSDK_REG_NONSECURE_ADDR(x)
Convert the register address to the one used in non-secure mode.
Lin_lpuart_driver
-
FSL_LIN_LPUART_DRIVER_VERSION
LIN LPUART driver version.
-
enum _lin_lpuart_stop_bit_count
Values:
-
enumerator kLPUART_OneStopBit
One stop bit
-
enumerator kLPUART_TwoStopBit
Two stop bits
-
enumerator kLPUART_OneStopBit
-
enum _lin_lpuart_flags
Values:
-
enumerator kLPUART_TxDataRegEmptyFlag
Transmit data register empty flag, sets when transmit buffer is empty
-
enumerator kLPUART_TransmissionCompleteFlag
Transmission complete flag, sets when transmission activity complete
-
enumerator kLPUART_RxDataRegFullFlag
Receive data register full flag, sets when the receive data buffer is full
-
enumerator kLPUART_IdleLineFlag
Idle line detect flag, sets when idle line detected
-
enumerator kLPUART_RxOverrunFlag
Receive Overrun, sets when new data is received before data is read from receive register
-
enumerator kLPUART_NoiseErrorFlag
Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets
-
enumerator kLPUART_FramingErrorFlag
Frame error flag, sets if logic 0 was detected where stop bit expected
-
enumerator kLPUART_ParityErrorFlag
If parity enabled, sets upon parity error detection
-
enumerator kLPUART_LinBreakFlag
LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled
-
enumerator kLPUART_RxActiveEdgeFlag
Receive pin active edge interrupt flag, sets when active edge detected
-
enumerator kLPUART_RxActiveFlag
Receiver Active Flag (RAF), sets at beginning of valid start bit
-
enumerator kLPUART_DataMatch1Flag
The next character to be read from LPUART_DATA matches MA1
-
enumerator kLPUART_DataMatch2Flag
The next character to be read from LPUART_DATA matches MA2
-
enumerator kLPUART_NoiseErrorInRxDataRegFlag
NOISY bit, sets if noise detected in current data word
-
enumerator kLPUART_ParityErrorInRxDataRegFlag
PARITY bit, sets if noise detected in current data word
-
enumerator kLPUART_TxFifoEmptyFlag
TXEMPT bit, sets if transmit buffer is empty
-
enumerator kLPUART_RxFifoEmptyFlag
RXEMPT bit, sets if receive buffer is empty
-
enumerator kLPUART_TxFifoOverflowFlag
TXOF bit, sets if transmit buffer overflow occurred
-
enumerator kLPUART_RxFifoUnderflowFlag
RXUF bit, sets if receive buffer underflow occurred
-
enumerator kLPUART_TxDataRegEmptyFlag
-
enum _lin_lpuart_interrupt_enable
Values:
-
enumerator kLPUART_LinBreakInterruptEnable
LIN break detect.
-
enumerator kLPUART_RxActiveEdgeInterruptEnable
Receive Active Edge.
-
enumerator kLPUART_TxDataRegEmptyInterruptEnable
Transmit data register empty.
-
enumerator kLPUART_TransmissionCompleteInterruptEnable
Transmission complete.
-
enumerator kLPUART_RxDataRegFullInterruptEnable
Receiver data register full.
-
enumerator kLPUART_IdleLineInterruptEnable
Idle line.
-
enumerator kLPUART_RxOverrunInterruptEnable
Receiver Overrun.
-
enumerator kLPUART_NoiseErrorInterruptEnable
Noise error flag.
-
enumerator kLPUART_FramingErrorInterruptEnable
Framing error flag.
-
enumerator kLPUART_ParityErrorInterruptEnable
Parity error flag.
-
enumerator kLPUART_TxFifoOverflowInterruptEnable
Transmit FIFO Overflow.
-
enumerator kLPUART_RxFifoUnderflowInterruptEnable
Receive FIFO Underflow.
-
enumerator kLPUART_LinBreakInterruptEnable
-
enum _lin_lpuart_status
Values:
-
enumerator kStatus_LPUART_TxBusy
TX busy
-
enumerator kStatus_LPUART_RxBusy
RX busy
-
enumerator kStatus_LPUART_TxIdle
LPUART transmitter is idle.
-
enumerator kStatus_LPUART_RxIdle
LPUART receiver is idle.
-
enumerator kStatus_LPUART_TxWatermarkTooLarge
TX FIFO watermark too large
-
enumerator kStatus_LPUART_RxWatermarkTooLarge
RX FIFO watermark too large
-
enumerator kStatus_LPUART_FlagCannotClearManually
Some flag can’t manually clear
-
enumerator kStatus_LPUART_Error
Error happens on LPUART.
-
enumerator kStatus_LPUART_RxRingBufferOverrun
LPUART RX software ring buffer overrun.
-
enumerator kStatus_LPUART_RxHardwareOverrun
LPUART RX receiver overrun.
-
enumerator kStatus_LPUART_NoiseError
LPUART noise error.
-
enumerator kStatus_LPUART_FramingError
LPUART framing error.
-
enumerator kStatus_LPUART_ParityError
LPUART parity error.
-
enumerator kStatus_LPUART_TxBusy
-
enum lin_lpuart_bit_count_per_char_t
Values:
-
enumerator LPUART_8_BITS_PER_CHAR
8-bit data characters
-
enumerator LPUART_9_BITS_PER_CHAR
9-bit data characters
-
enumerator LPUART_10_BITS_PER_CHAR
10-bit data characters
-
enumerator LPUART_8_BITS_PER_CHAR
-
typedef enum _lin_lpuart_stop_bit_count lin_lpuart_stop_bit_count_t
-
static inline bool LIN_LPUART_GetRxDataPolarity(const LPUART_Type *base)
-
static inline void LIN_LPUART_SetRxDataPolarity(LPUART_Type *base, bool polarity)
-
static inline void LIN_LPUART_WriteByte(LPUART_Type *base, uint8_t data)
-
static inline void LIN_LPUART_ReadByte(const LPUART_Type *base, uint8_t *readData)
-
status_t LIN_LPUART_CalculateBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *osr, uint16_t *sbr)
Calculates the best osr and sbr value for configured baudrate.
- Parameters:
base – LPUART peripheral base address
baudRate_Bps – user configuration structure of type #lin_user_config_t
srcClock_Hz – pointer to the LIN_LPUART driver state structure
osr – pointer to osr value
sbr – pointer to sbr value
- Returns:
An error code or lin_status_t
-
void LIN_LPUART_SetBaudRate(LPUART_Type *base, uint32_t *osr, uint16_t *sbr)
Configure baudrate according to osr and sbr value.
- Parameters:
base – LPUART peripheral base address
osr – pointer to osr value
sbr – pointer to sbr value
-
lin_status_t LIN_LPUART_Init(LPUART_Type *base, lin_user_config_t *linUserConfig, lin_state_t *linCurrentState, uint32_t linSourceClockFreq)
Initializes an LIN_LPUART instance for LIN Network.
The caller provides memory for the driver state structures during initialization. The user must select the LIN_LPUART clock source in the application to initialize the LIN_LPUART. This function initializes a LPUART instance for operation. This function will initialize the run-time state structure to keep track of the on-going transfers, initialize the module to user defined settings and default settings, set break field length to be 13 bit times minimum, enable the break detect interrupt, Rx complete interrupt, frame error detect interrupt, and enable the LPUART module transmitter and receiver
- Parameters:
base – LPUART peripheral base address
linUserConfig – user configuration structure of type #lin_user_config_t
linCurrentState – pointer to the LIN_LPUART driver state structure
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_Deinit(LPUART_Type *base)
Shuts down the LIN_LPUART by disabling interrupts and transmitter/receiver.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_SendFrameDataBlocking(LPUART_Type *base, const uint8_t *txBuff, uint8_t txSize, uint32_t timeoutMSec)
Sends Frame data out through the LIN_LPUART module using blocking method. This function will calculate the checksum byte and send it with the frame data. Blocking means that the function does not return until the transmission is complete.
- Parameters:
base – LPUART peripheral base address
txBuff – source buffer containing 8-bit data chars to send
txSize – the number of bytes to send
timeoutMSec – timeout value in milli seconds
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_SendFrameData(LPUART_Type *base, const uint8_t *txBuff, uint8_t txSize)
Sends frame data out through the LIN_LPUART module using non-blocking method. This enables an a-sync method for transmitting data. Non-blocking means that the function returns immediately. The application has to get the transmit status to know when the transmit is complete. This function will calculate the checksum byte and send it with the frame data.
- Parameters:
base – LPUART peripheral base address
txBuff – source buffer containing 8-bit data chars to send
txSize – the number of bytes to send
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_GetTransmitStatus(LPUART_Type *base, uint8_t *bytesRemaining)
Get status of an on-going non-blocking transmission While sending frame data using non-blocking method, users can use this function to get status of that transmission. This function return LIN_TX_BUSY while sending, or LIN_TIMEOUT if timeout has occurred, or return LIN_SUCCESS when the transmission is complete. The bytesRemaining shows number of bytes that still needed to transmit.
- Parameters:
base – LPUART peripheral base address
bytesRemaining – Number of bytes still needed to transmit
- Returns:
lin_status_t LIN_TX_BUSY, LIN_SUCCESS or LIN_TIMEOUT
-
lin_status_t LIN_LPUART_RecvFrmDataBlocking(LPUART_Type *base, uint8_t *rxBuff, uint8_t rxSize, uint32_t timeoutMSec)
Receives frame data through the LIN_LPUART module using blocking method. This function will check the checksum byte. If the checksum is correct, it will receive the frame data. Blocking means that the function does not return until the reception is complete.
- Parameters:
base – LPUART peripheral base address
rxBuff – buffer containing 8-bit received data
rxSize – the number of bytes to receive
timeoutMSec – timeout value in milli seconds
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_RecvFrmData(LPUART_Type *base, uint8_t *rxBuff, uint8_t rxSize)
Receives frame data through the LIN_LPUART module using non-blocking method. This function will check the checksum byte. If the checksum is correct, it will receive it with the frame data. Non-blocking means that the function returns immediately. The application has to get the receive status to know when the reception is complete.
- Parameters:
base – LPUART peripheral base address
rxBuff – buffer containing 8-bit received data
rxSize – the number of bytes to receive
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_AbortTransferData(LPUART_Type *base)
Aborts an on-going non-blocking transmission/reception. While performing a non-blocking transferring data, users can call this function to terminate immediately the transferring.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_GetReceiveStatus(LPUART_Type *base, uint8_t *bytesRemaining)
Get status of an on-going non-blocking reception While receiving frame data using non-blocking method, users can use this function to get status of that receiving. This function return the current event ID, LIN_RX_BUSY while receiving and return LIN_SUCCESS, or timeout (LIN_TIMEOUT) when the reception is complete. The bytesRemaining shows number of bytes that still needed to receive.
- Parameters:
base – LPUART peripheral base address
bytesRemaining – Number of bytes still needed to receive
- Returns:
lin_status_t LIN_RX_BUSY, LIN_TIMEOUT or LIN_SUCCESS
-
lin_status_t LIN_LPUART_GoToSleepMode(LPUART_Type *base)
This function puts current node to sleep mode This function changes current node state to LIN_NODE_STATE_SLEEP_MODE.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_GotoIdleState(LPUART_Type *base)
Puts current LIN node to Idle state This function changes current node state to LIN_NODE_STATE_IDLE.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_SendWakeupSignal(LPUART_Type *base)
Sends a wakeup signal through the LIN_LPUART interface.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_MasterSendHeader(LPUART_Type *base, uint8_t id)
Sends frame header out through the LIN_LPUART module using a non-blocking method. This function sends LIN Break field, sync field then the ID with correct parity.
- Parameters:
base – LPUART peripheral base address
id – Frame Identifier
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_EnableIRQ(LPUART_Type *base)
Enables LIN_LPUART hardware interrupts.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_DisableIRQ(LPUART_Type *base)
Disables LIN_LPUART hardware interrupts.
- Parameters:
base – LPUART peripheral base address
- Returns:
An error code or lin_status_t
-
lin_status_t LIN_LPUART_AutoBaudCapture(uint32_t instance)
This function capture bits time to detect break char, calculate baudrate from sync bits and enable transceiver if autobaud successful. This function should only be used in Slave. The timer should be in mode input capture of both rising and falling edges. The timer input capture pin should be externally connected to RXD pin.
- Parameters:
instance – LPUART instance
- Returns:
lin_status_t
-
void LIN_LPUART_IRQHandler(LPUART_Type *base)
LIN_LPUART RX TX interrupt handler.
- Parameters:
base – LPUART peripheral base address
- Returns:
void
-
AUTOBAUD_BAUDRATE_TOLERANCE
-
BIT_RATE_TOLERANCE_UNSYNC
-
BIT_DURATION_MAX_19200
-
BIT_DURATION_MIN_19200
-
BIT_DURATION_MAX_14400
-
BIT_DURATION_MIN_14400
-
BIT_DURATION_MAX_9600
-
BIT_DURATION_MIN_9600
-
BIT_DURATION_MAX_4800
-
BIT_DURATION_MIN_4800
-
BIT_DURATION_MAX_2400
-
BIT_DURATION_MIN_2400
-
TWO_BIT_DURATION_MAX_19200
-
TWO_BIT_DURATION_MIN_19200
-
TWO_BIT_DURATION_MAX_14400
-
TWO_BIT_DURATION_MIN_14400
-
TWO_BIT_DURATION_MAX_9600
-
TWO_BIT_DURATION_MIN_9600
-
TWO_BIT_DURATION_MAX_4800
-
TWO_BIT_DURATION_MIN_4800
-
TWO_BIT_DURATION_MAX_2400
-
TWO_BIT_DURATION_MIN_2400
-
AUTOBAUD_BREAK_TIME_MIN
LPADC: 12-bit SAR Analog-to-Digital Converter Driver
-
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
Initializes the LPADC module.
- Parameters:
base – LPADC peripheral base address.
config – Pointer to configuration structure. See “lpadc_config_t”.
-
void LPADC_GetDefaultConfig(lpadc_config_t *config)
Gets an available pre-defined settings for initial configuration.
This function initializes the converter configuration structure with an available settings. The default values are:
config->enableInDozeMode = true; config->enableAnalogPreliminary = false; config->powerUpDelay = 0x80; config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; config->powerLevelMode = kLPADC_PowerLevelAlt1; config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; config->enableConvPause = false; config->convPauseDelay = 0U; config->FIFOWatermark = 0U;
- Parameters:
config – Pointer to configuration structure.
-
void LPADC_Deinit(ADC_Type *base)
De-initializes the LPADC module.
- Parameters:
base – LPADC peripheral base address.
-
static inline void LPADC_Enable(ADC_Type *base, bool enable)
Switch on/off the LPADC module.
- Parameters:
base – LPADC peripheral base address.
enable – switcher to the module.
-
static inline void LPADC_DoResetFIFO(ADC_Type *base)
Do reset the conversion FIFO.
- Parameters:
base – LPADC peripheral base address.
-
static inline void LPADC_DoResetConfig(ADC_Type *base)
Do reset the module’s configuration.
Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).
- Parameters:
base – LPADC peripheral base address.
-
static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
Get status flags.
- Parameters:
base – LPADC peripheral base address.
- Returns:
status flags’ mask. See to _lpadc_status_flags.
-
static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
Clear status flags.
Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.
- Parameters:
base – LPADC peripheral base address.
mask – Mask value for flags to be cleared. See to _lpadc_status_flags.
-
static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)
Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high priority trigger exception.
- Parameters:
base – LPADC peripheral base address.
- Returns:
The OR’ed value of _lpadc_trigger_status_flags.
-
static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
Clear trigger status flags.
- Parameters:
base – LPADC peripheral base address.
mask – The mask of trigger status flags to be cleared, should be the OR’ed value of _lpadc_trigger_status_flags.
-
static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
Enable interrupts.
- Parameters:
base – LPADC peripheral base address.
mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.
-
static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
Disable interrupts.
- Parameters:
base – LPADC peripheral base address.
mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.
-
static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
Switch on/off the DMA trigger for FIFO watermark event.
- Parameters:
base – LPADC peripheral base address.
enable – Switcher to the event.
-
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
Get the count of result kept in conversion FIFO.
- Parameters:
base – LPADC peripheral base address.
- Returns:
The count of result kept in conversion FIFO.
-
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
Get the result in conversion FIFO.
- Parameters:
base – LPADC peripheral base address.
result – Pointer to structure variable that keeps the conversion result in conversion FIFO.
- Returns:
Status whether FIFO entry is valid.
-
void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)
Get the result in conversion FIFO using blocking method.
- Parameters:
base – LPADC peripheral base address.
result – Pointer to structure variable that keeps the conversion result in conversion FIFO.
-
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)
Configure the conversion trigger source.
Each programmable trigger can launch the conversion command in command buffer.
- Parameters:
base – LPADC peripheral base address.
triggerId – ID for each trigger. Typically, the available value range is from 0.
config – Pointer to configuration structure. See to lpadc_conv_trigger_config_t.
-
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
Gets an available pre-defined settings for trigger’s configuration.
This function initializes the trigger’s configuration structure with an available settings. The default values are:
config->targetCommandId = 0U; config->delayPower = 0U; config->priority = 0U; config->channelAFIFOSelect = 0U; config->channelBFIFOSelect = 0U; config->enableHardwareTrigger = false;
- Parameters:
config – Pointer to configuration structure.
-
static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
Do software trigger to conversion command.
- Parameters:
base – LPADC peripheral base address.
triggerIdMask – Mask value for software trigger indexes, which count from zero.
-
static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)
Enable hardware trigger command selection.
This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL].
- Parameters:
base – LPADC peripheral base address.
triggerId – ID for each trigger. Typically, the available value range is from 0.
enable – True to enable or flase to disable.
-
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)
Configure conversion command.
Note
The number of compare value register on different chips is different, that is mean in some chips, some command buffers do not have the compare functionality.
- Parameters:
base – LPADC peripheral base address.
commandId – ID for command in command buffer. Typically, the available value range is 1 - 15.
config – Pointer to configuration structure. See to lpadc_conv_command_config_t.
-
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
Gets an available pre-defined settings for conversion command’s configuration.
This function initializes the conversion command’s configuration structure with an available settings. The default values are:
config->sampleScaleMode = kLPADC_SampleFullScale; config->channelBScaleMode = kLPADC_SampleFullScale; config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; config->channelNumber = 0U; config->channelBNumber = 0U; config->chainedNextCommandNumber = 0U; config->enableAutoChannelIncrement = false; config->loopCount = 0U; config->hardwareAverageMode = kLPADC_HardwareAverageCount1; config->sampleTimeMode = kLPADC_SampleTimeADCK3; config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; config->hardwareCompareValueHigh = 0U; config->hardwareCompareValueLow = 0U; config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; config->enableWaitTrigger = false; config->enableChannelB = false;
- Parameters:
config – Pointer to configuration structure.
-
void LPADC_EnableCalibration(ADC_Type *base, bool enable)
Enable the calibration function.
When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
- Parameters:
base – LPADC peripheral base address.
enable – switcher to the calibration function.
-
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
Set proper offset value to trim ADC.
To minimize the offset during normal operation, software should read the conversion result from the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.
- Parameters:
base – LPADC peripheral base address.
value – Setting offset value.
-
void LPADC_DoAutoCalibration(ADC_Type *base)
Do auto calibration.
Calibration function should be executed before using converter in application. It used the software trigger and a dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -LPADC_EnableCalibration(…) -LPADC_LPADC_SetOffsetValue(…) -LPADC_SetConvCommandConfig(…) -LPADC_SetConvTriggerConfig(…)
- Parameters:
base – LPADC peripheral base address.
base – LPADC peripheral base address.
-
static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
Enable the offset calibration function.
- Parameters:
base – LPADC peripheral base address.
enable – switcher to the calibration function.
-
static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)
Set offset calibration mode.
- Parameters:
base – LPADC peripheral base address.
mode – set offset calibration mode.see to lpadc_offset_calibration_mode_t .
-
void LPADC_DoOffsetCalibration(ADC_Type *base)
Do offset calibration.
- Parameters:
base – LPADC peripheral base address.
-
void LPADC_PrepareAutoCalibration(ADC_Type *base)
Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.
- Parameters:
base – LPADC peripheral base address.
-
void LPADC_FinishAutoCalibration(ADC_Type *base)
Finish auto calibration start with LPADC_PrepareAutoCalibration.
Note
This feature is used for LPADC with CTRL[CALOFSMODE].
- Parameters:
base – LPADC peripheral base address.
-
void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue)
Get calibration value into the memory which is defined by invoker.
Note
Please note the ADC will be disabled temporary.
Note
This function should be used after finish calibration.
- Parameters:
base – LPADC peripheral base address.
ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure, this memory block should be always powered on even in low power modes.
-
void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue)
Set calibration value into ADC calibration registers.
Note
Please note the ADC will be disabled temporary.
- Parameters:
base – LPADC peripheral base address.
ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure which contains ADC’s calibration value.
-
FSL_LPADC_DRIVER_VERSION
LPADC driver version 2.9.1.
-
enum _lpadc_status_flags
Define hardware flags of the module.
Values:
-
enumerator kLPADC_ResultFIFO0OverflowFlag
Indicates that more data has been written to the Result FIFO 0 than it can hold.
-
enumerator kLPADC_ResultFIFO0ReadyFlag
Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level.
-
enumerator kLPADC_TriggerExceptionFlag
Indicates that a trigger exception event has occurred.
-
enumerator kLPADC_TriggerCompletionFlag
Indicates that a trigger completion event has occurred.
-
enumerator kLPADC_CalibrationReadyFlag
Indicates that the calibration process is done.
-
enumerator kLPADC_ActiveFlag
Indicates that the ADC is in active state.
-
enumerator kLPADC_ResultFIFOOverflowFlag
To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowFlag as instead.
-
enumerator kLPADC_ResultFIFOReadyFlag
To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0ReadyFlag as instead.
-
enumerator kLPADC_ResultFIFO0OverflowFlag
-
enum _lpadc_interrupt_enable
Define interrupt switchers of the module.
Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.
Values:
-
enumerator kLPADC_ResultFIFO0OverflowInterruptEnable
Configures ADC to generate overflow interrupt requests when FOF0 flag is asserted.
-
enumerator kLPADC_FIFO0WatermarkInterruptEnable
Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted.
-
enumerator kLPADC_ResultFIFOOverflowInterruptEnable
To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowInterruptEnable as instead.
-
enumerator kLPADC_FIFOWatermarkInterruptEnable
To compilitable with old version, do not recommend using this, please use kLPADC_FIFO0WatermarkInterruptEnable as instead.
-
enumerator kLPADC_TriggerExceptionInterruptEnable
Configures ADC to generate trigger exception interrupt.
-
enumerator kLPADC_Trigger0CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 0 completion.
-
enumerator kLPADC_Trigger1CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 1 completion.
-
enumerator kLPADC_Trigger2CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 2 completion.
-
enumerator kLPADC_Trigger3CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 3 completion.
-
enumerator kLPADC_Trigger4CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 4 completion.
-
enumerator kLPADC_Trigger5CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 5 completion.
-
enumerator kLPADC_Trigger6CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 6 completion.
-
enumerator kLPADC_Trigger7CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 7 completion.
-
enumerator kLPADC_Trigger8CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 8 completion.
-
enumerator kLPADC_Trigger9CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 9 completion.
-
enumerator kLPADC_Trigger10CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 10 completion.
-
enumerator kLPADC_Trigger11CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 11 completion.
-
enumerator kLPADC_Trigger12CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 12 completion.
-
enumerator kLPADC_Trigger13CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 13 completion.
-
enumerator kLPADC_Trigger14CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 14 completion.
-
enumerator kLPADC_Trigger15CompletionInterruptEnable
Configures ADC to generate interrupt when trigger 15 completion.
-
enumerator kLPADC_ResultFIFO0OverflowInterruptEnable
-
enum _lpadc_trigger_status_flags
The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.
Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.
Values:
-
enumerator kLPADC_Trigger0InterruptedFlag
Trigger 0 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger1InterruptedFlag
Trigger 1 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger2InterruptedFlag
Trigger 2 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger3InterruptedFlag
Trigger 3 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger4InterruptedFlag
Trigger 4 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger5InterruptedFlag
Trigger 5 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger6InterruptedFlag
Trigger 6 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger7InterruptedFlag
Trigger 7 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger8InterruptedFlag
Trigger 8 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger9InterruptedFlag
Trigger 9 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger10InterruptedFlag
Trigger 10 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger11InterruptedFlag
Trigger 11 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger12InterruptedFlag
Trigger 12 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger13InterruptedFlag
Trigger 13 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger14InterruptedFlag
Trigger 14 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger15InterruptedFlag
Trigger 15 is interrupted by a high priority exception.
-
enumerator kLPADC_Trigger0CompletedFlag
Trigger 0 is completed and trigger 0 has enabled completion interrupts.
-
enumerator kLPADC_Trigger1CompletedFlag
Trigger 1 is completed and trigger 1 has enabled completion interrupts.
-
enumerator kLPADC_Trigger2CompletedFlag
Trigger 2 is completed and trigger 2 has enabled completion interrupts.
-
enumerator kLPADC_Trigger3CompletedFlag
Trigger 3 is completed and trigger 3 has enabled completion interrupts.
-
enumerator kLPADC_Trigger4CompletedFlag
Trigger 4 is completed and trigger 4 has enabled completion interrupts.
-
enumerator kLPADC_Trigger5CompletedFlag
Trigger 5 is completed and trigger 5 has enabled completion interrupts.
-
enumerator kLPADC_Trigger6CompletedFlag
Trigger 6 is completed and trigger 6 has enabled completion interrupts.
-
enumerator kLPADC_Trigger7CompletedFlag
Trigger 7 is completed and trigger 7 has enabled completion interrupts.
-
enumerator kLPADC_Trigger8CompletedFlag
Trigger 8 is completed and trigger 8 has enabled completion interrupts.
-
enumerator kLPADC_Trigger9CompletedFlag
Trigger 9 is completed and trigger 9 has enabled completion interrupts.
-
enumerator kLPADC_Trigger10CompletedFlag
Trigger 10 is completed and trigger 10 has enabled completion interrupts.
-
enumerator kLPADC_Trigger11CompletedFlag
Trigger 11 is completed and trigger 11 has enabled completion interrupts.
-
enumerator kLPADC_Trigger12CompletedFlag
Trigger 12 is completed and trigger 12 has enabled completion interrupts.
-
enumerator kLPADC_Trigger13CompletedFlag
Trigger 13 is completed and trigger 13 has enabled completion interrupts.
-
enumerator kLPADC_Trigger14CompletedFlag
Trigger 14 is completed and trigger 14 has enabled completion interrupts.
-
enumerator kLPADC_Trigger15CompletedFlag
Trigger 15 is completed and trigger 15 has enabled completion interrupts.
-
enumerator kLPADC_Trigger0InterruptedFlag
-
enum _lpadc_sample_scale_mode
Define enumeration of sample scale mode.
The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
Values:
-
enumerator kLPADC_SamplePartScale
Use divided input voltage signal. (For scale select,please refer to the reference manual).
-
enumerator kLPADC_SampleFullScale
Full scale (Factor of 1).
-
enumerator kLPADC_SamplePartScale
-
enum _lpadc_sample_channel_mode
Define enumeration of channel sample mode.
The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.
Values:
-
enumerator kLPADC_SampleChannelSingleEndSideA
Single-end mode, only A-side channel is converted.
-
enumerator kLPADC_SampleChannelSingleEndSideB
Single-end mode, only B-side channel is converted.
-
enumerator kLPADC_SampleChannelDiffBothSideAB
Differential mode, the ADC result is (CHnA-CHnB).
-
enumerator kLPADC_SampleChannelDiffBothSideBA
Differential mode, the ADC result is (CHnB-CHnA).
-
enumerator kLPADC_SampleChannelDiffBothSide
Differential mode, the ADC result is (CHnA-CHnB).
-
enumerator kLPADC_SampleChannelDualSingleEndBothSide
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
-
enumerator kLPADC_SampleChannelSingleEndSideA
-
enum _lpadc_hardware_average_mode
Define enumeration of hardware average selection.
It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.
Note
Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.
Values:
-
enumerator kLPADC_HardwareAverageCount1
Single conversion.
-
enumerator kLPADC_HardwareAverageCount2
2 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount4
4 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount8
8 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount16
16 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount32
32 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount64
64 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount128
128 conversions averaged.
-
enumerator kLPADC_HardwareAverageCount1
-
enum _lpadc_sample_time_mode
Define enumeration of sample time selection.
The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.
Values:
-
enumerator kLPADC_SampleTimeADCK3
3 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK5
5 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK7
7 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK11
11 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK19
19 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK35
35 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK67
69 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK131
131 ADCK cycles total sample time.
-
enumerator kLPADC_SampleTimeADCK3
-
enum _lpadc_hardware_compare_mode
Define enumeration of hardware compare mode.
After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.
Values:
-
enumerator kLPADC_HardwareCompareDisabled
Compare disabled.
-
enumerator kLPADC_HardwareCompareStoreOnTrue
Compare enabled. Store on true.
-
enumerator kLPADC_HardwareCompareRepeatUntilTrue
Compare enabled. Repeat channel acquisition until true.
-
enumerator kLPADC_HardwareCompareDisabled
-
enum _lpadc_conversion_resolution_mode
Define enumeration of conversion resolution mode.
Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t
Values:
-
enumerator kLPADC_ConversionResolutionStandard
Standard resolution. Single-ended 12-bit conversion, Differential 13-bit conversion with 2’s complement output.
-
enumerator kLPADC_ConversionResolutionHigh
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2’s complement output.
-
enumerator kLPADC_ConversionResolutionStandard
-
enum _lpadc_conversion_average_mode
Define enumeration of conversion averages mode.
Configure the converion average number for auto-calibration.
Note
Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.
Values:
-
enumerator kLPADC_ConversionAverage1
Single conversion.
-
enumerator kLPADC_ConversionAverage2
2 conversions averaged.
-
enumerator kLPADC_ConversionAverage4
4 conversions averaged.
-
enumerator kLPADC_ConversionAverage8
8 conversions averaged.
-
enumerator kLPADC_ConversionAverage16
16 conversions averaged.
-
enumerator kLPADC_ConversionAverage32
32 conversions averaged.
-
enumerator kLPADC_ConversionAverage64
64 conversions averaged.
-
enumerator kLPADC_ConversionAverage128
128 conversions averaged.
-
enumerator kLPADC_ConversionAverage1
-
enum _lpadc_reference_voltage_mode
Define enumeration of reference voltage source.
For detail information, need to check the SoC’s specification.
Values:
-
enumerator kLPADC_ReferenceVoltageAlt1
Option 1 setting.
-
enumerator kLPADC_ReferenceVoltageAlt2
Option 2 setting.
-
enumerator kLPADC_ReferenceVoltageAlt3
Option 3 setting.
-
enumerator kLPADC_ReferenceVoltageAlt1
-
enum _lpadc_power_level_mode
Define enumeration of power configuration.
Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.
Values:
-
enumerator kLPADC_PowerLevelAlt1
Lowest power setting.
-
enumerator kLPADC_PowerLevelAlt2
Next lowest power setting.
-
enumerator kLPADC_PowerLevelAlt3
…
-
enumerator kLPADC_PowerLevelAlt4
Highest power setting.
-
enumerator kLPADC_PowerLevelAlt1
-
enum _lpadc_offset_calibration_mode
Define enumeration of offset calibration mode.
Values:
-
enumerator kLPADC_OffsetCalibration12bitMode
12 bit offset calibration mode.
-
enumerator kLPADC_OffsetCalibration16bitMode
16 bit offset calibration mode.
-
enumerator kLPADC_OffsetCalibration12bitMode
-
enum _lpadc_trigger_priority_policy
Define enumeration of trigger priority policy.
This selection controls how higher priority triggers are handled.
Note
kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.
Values:
-
enumerator kLPADC_ConvPreemptImmediatelyNotAutoResumed
If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion is not automatically resumed or restarted.
-
enumerator kLPADC_ConvPreemptSoftlyNotAutoResumed
If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion is not resumed or restarted.
-
enumerator kLPADC_ConvPreemptImmediatelyAutoRestarted
If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be restarted.
-
enumerator kLPADC_ConvPreemptSoftlyAutoRestarted
If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will automatically be restarted.
-
enumerator kLPADC_ConvPreemptImmediatelyAutoResumed
If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be resumed.
-
enumerator kLPADC_ConvPreemptSoftlyAutoResumed
If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will be automatically be resumed.
-
enumerator kLPADC_TriggerPriorityPreemptImmediately
Legacy support is not recommended as it only ensures compatibility with older versions.
-
enumerator kLPADC_TriggerPriorityPreemptSoftly
Legacy support is not recommended as it only ensures compatibility with older versions.
-
enumerator kLPADC_TriggerPriorityExceptionDisabled
High priority trigger exception disabled.
-
enumerator kLPADC_ConvPreemptImmediatelyNotAutoResumed
-
typedef enum _lpadc_sample_scale_mode lpadc_sample_scale_mode_t
Define enumeration of sample scale mode.
The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
-
typedef enum _lpadc_sample_channel_mode lpadc_sample_channel_mode_t
Define enumeration of channel sample mode.
The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.
-
typedef enum _lpadc_hardware_average_mode lpadc_hardware_average_mode_t
Define enumeration of hardware average selection.
It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.
Note
Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.
-
typedef enum _lpadc_sample_time_mode lpadc_sample_time_mode_t
Define enumeration of sample time selection.
The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.
-
typedef enum _lpadc_hardware_compare_mode lpadc_hardware_compare_mode_t
Define enumeration of hardware compare mode.
After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.
-
typedef enum _lpadc_conversion_resolution_mode lpadc_conversion_resolution_mode_t
Define enumeration of conversion resolution mode.
Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t
-
typedef enum _lpadc_conversion_average_mode lpadc_conversion_average_mode_t
Define enumeration of conversion averages mode.
Configure the converion average number for auto-calibration.
Note
Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.
-
typedef enum _lpadc_reference_voltage_mode lpadc_reference_voltage_source_t
Define enumeration of reference voltage source.
For detail information, need to check the SoC’s specification.
-
typedef enum _lpadc_power_level_mode lpadc_power_level_mode_t
Define enumeration of power configuration.
Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.
-
typedef enum _lpadc_offset_calibration_mode lpadc_offset_calibration_mode_t
Define enumeration of offset calibration mode.
-
typedef enum _lpadc_trigger_priority_policy lpadc_trigger_priority_policy_t
Define enumeration of trigger priority policy.
This selection controls how higher priority triggers are handled.
Note
kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.
-
typedef struct _lpadc_calibration_value lpadc_calibration_value_t
A structure of calibration value.
-
LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal)
Define the MACRO function to get command status from status value.
The statusVal is the return value from LPADC_GetStatusFlags().
-
LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal)
Define the MACRO function to get trigger status from status value.
The statusVal is the return value from LPADC_GetStatusFlags().
-
struct lpadc_config_t
- #include <fsl_lpadc.h>
LPADC global configuration.
This structure would used to keep the settings for initialization.
Public Members
-
bool enableInternalClock
Enables the internally generated clock source. The clock source is used in clock selection logic at the chip level and is optionally used for the ADC clock source.
-
bool enableVref1LowVoltage
If voltage reference option1 input is below 1.8V, it should be “true”. If voltage reference option1 input is above 1.8V, it should be “false”.
-
bool enableInDozeMode
Control system transition to Stop and Wait power modes while ADC is converting. When enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.
-
lpadc_conversion_average_mode_t conversionAverageMode
Auto-Calibration Averages.
-
bool enableAnalogPreliminary
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).
-
uint32_t powerUpDelay
When the analog circuits are not pre-enabled, the ADC analog circuits are only powered while the ADC is active and there is a counted delay defined by this field after an initial trigger transitions the ADC from its Idle state to allow time for the analog circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must result in a longer delay than the analog startup time.
-
lpadc_reference_voltage_source_t referenceVoltageSource
Selects the voltage reference high used for conversions.
-
lpadc_power_level_mode_t powerLevelMode
Power Configuration Selection.
-
lpadc_trigger_priority_policy_t triggerPriorityPolicy
Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t.
-
bool enableConvPause
Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations, between commands in a sequence, and between conversions when command is executing in “Compare Until True” configuration.
-
uint32_t convPauseDelay
Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing function is enabled. The available value range is in 9-bit.
-
uint32_t FIFOWatermark
FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold.
-
bool enableInternalClock
-
struct lpadc_conv_command_config_t
- #include <fsl_lpadc.h>
Define structure to keep the configuration for conversion command.
Public Members
-
lpadc_sample_scale_mode_t sampleScaleMode
Sample scale mode.
-
lpadc_sample_scale_mode_t channelBScaleMode
Alternate channe B Scale mode.
-
lpadc_sample_channel_mode_t sampleChannelMode
Channel sample mode.
-
uint32_t channelNumber
Channel number, select the channel or channel pair.
-
uint32_t channelBNumber
Alternate Channel B number, select the channel.
-
uint32_t chainedNextCommandNumber
Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command.
-
bool enableAutoChannelIncrement
Loop with increment: when disabled, the “loopCount” field selects the number of times the selected channel is converted consecutively; when enabled, the “loopCount” field defines how many consecutive channels are converted as part of the command execution.
-
uint32_t loopCount
Selects how many times this command executes before finish and transition to the next command or Idle state. Command executes LOOP+1 times. 0-15 is available.
-
lpadc_hardware_average_mode_t hardwareAverageMode
Hardware average selection.
-
lpadc_sample_time_mode_t sampleTimeMode
Sample time selection.
-
lpadc_hardware_compare_mode_t hardwareCompareMode
Hardware compare selection.
-
uint32_t hardwareCompareValueHigh
Compare Value High. The available value range is in 16-bit.
-
uint32_t hardwareCompareValueLow
Compare Value Low. The available value range is in 16-bit.
-
lpadc_conversion_resolution_mode_t conversionResolutionMode
Conversion resolution mode.
-
bool enableWaitTrigger
Wait for trigger assertion before execution: when disabled, this command will be automatically executed; when enabled, the active trigger must be asserted again before executing this command.
-
lpadc_sample_scale_mode_t sampleScaleMode
-
struct lpadc_conv_trigger_config_t
- #include <fsl_lpadc.h>
Define structure to keep the configuration for conversion trigger.
Public Members
-
uint32_t targetCommandId
Select the command from command buffer to execute upon detect of the associated trigger event.
-
uint32_t delayPower
Select the trigger delay duration to wait at the start of servicing a trigger event. When this field is clear, then no delay is incurred. When this field is set to a non-zero value, the duration for the delay is 2^delayPower ADCK cycles. The available value range is 4-bit.
-
uint32_t priority
Sets the priority of the associated trigger source. If two or more triggers have the same priority level setting, the lower order trigger event has the higher priority. The lower value for this field is for the higher priority, the available value range is 1-bit.
-
bool enableHardwareTrigger
Enable hardware trigger source to initiate conversion on the rising edge of the input trigger source or not. THe software trigger is always available.
-
uint32_t targetCommandId
-
struct lpadc_conv_result_t
- #include <fsl_lpadc.h>
Define the structure to keep the conversion result.
Public Members
-
uint32_t commandIdSource
Indicate the command buffer being executed that generated this result.
-
uint32_t loopCountIndex
Indicate the loop count value during command execution that generated this result.
-
uint32_t triggerIdSource
Indicate the trigger source that initiated a conversion and generated this result.
-
uint16_t convValue
Data result.
-
uint32_t commandIdSource
-
struct _lpadc_calibration_value
- #include <fsl_lpadc.h>
A structure of calibration value.
LPI2C: Low Power Inter-Integrated Circuit Driver
-
FSL_LPI2C_DRIVER_VERSION
LPI2C driver version.
LPI2C status return codes.
Values:
-
enumerator kStatus_LPI2C_Busy
The master is already performing a transfer.
-
enumerator kStatus_LPI2C_Idle
The slave driver is idle.
-
enumerator kStatus_LPI2C_Nak
The slave device sent a NAK in response to a byte.
-
enumerator kStatus_LPI2C_FifoError
FIFO under run or overrun.
-
enumerator kStatus_LPI2C_BitError
Transferred bit was not seen on the bus.
-
enumerator kStatus_LPI2C_ArbitrationLost
Arbitration lost error.
-
enumerator kStatus_LPI2C_PinLowTimeout
SCL or SDA were held low longer than the timeout.
-
enumerator kStatus_LPI2C_NoTransferInProgress
Attempt to abort a transfer when one is not in progress.
-
enumerator kStatus_LPI2C_DmaRequestFail
DMA request failed.
-
enumerator kStatus_LPI2C_Timeout
Timeout polling status flags.
-
enumerator kStatus_LPI2C_Busy
-
IRQn_Type const kLpi2cIrqs[]
Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs.
-
lpi2c_master_isr_t s_lpi2cMasterIsr
Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.
-
void *s_lpi2cMasterHandle[]
Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.
-
uint32_t LPI2C_GetInstance(LPI2C_Type *base)
Returns an instance number given a base address.
If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
LPI2C instance number starting from 0.
-
I2C_RETRY_TIMES
Retry times for waiting flag.
LPI2C Master Driver
-
void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)
Provides a default configuration for the LPI2C master peripheral.
This function provides the following default configuration for the LPI2C master peripheral:
masterConfig->enableMaster = true; masterConfig->debugEnable = false; masterConfig->ignoreAck = false; masterConfig->pinConfig = kLPI2C_2PinOpenDrain; masterConfig->baudRate_Hz = 100000U; masterConfig->busIdleTimeout_ns = 0; masterConfig->pinLowTimeout_ns = 0; masterConfig->sdaGlitchFilterWidth_ns = 0; masterConfig->sclGlitchFilterWidth_ns = 0; masterConfig->hostRequest.enable = false; masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().
- Parameters:
masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t.
-
void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
Initializes the LPI2C master peripheral.
This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.
- Parameters:
base – The LPI2C peripheral base address.
masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.
-
void LPI2C_MasterDeinit(LPI2C_Type *base)
Deinitializes the LPI2C master peripheral.
This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.
- Parameters:
base – The LPI2C peripheral base address.
-
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)
Configures LPI2C master data match feature.
- Parameters:
base – The LPI2C peripheral base address.
matchConfig – Settings for the data match feature.
-
status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
Convert provided flags to status code, and clear any errors if present.
- Parameters:
base – The LPI2C peripheral base address.
status – Current status flags value that will be checked.
- Return values:
kStatus_Success –
kStatus_LPI2C_PinLowTimeout –
kStatus_LPI2C_ArbitrationLost –
kStatus_LPI2C_Nak –
kStatus_LPI2C_FifoError –
-
status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
Make sure the bus isn’t already busy.
A busy bus is allowed if we are the one driving it.
- Parameters:
base – The LPI2C peripheral base address.
- Return values:
kStatus_Success –
kStatus_LPI2C_Busy –
-
static inline void LPI2C_MasterReset(LPI2C_Type *base)
Performs a software reset.
Restores the LPI2C master peripheral to reset conditions.
- Parameters:
base – The LPI2C peripheral base address.
-
static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)
Enables or disables the LPI2C module as master.
- Parameters:
base – The LPI2C peripheral base address.
enable – Pass true to enable or false to disable the specified LPI2C as master.
-
static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)
Gets the LPI2C master status flags.
A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_lpi2c_master_flags
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
State of the status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)
Clears the LPI2C master status flag state.
The following status register flags can be cleared:
kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag
Attempts to clear other flags has no effect.
See also
_lpi2c_master_flags.
- Parameters:
base – The LPI2C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags().
-
static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)
Enables the LPI2C master interrupt requests.
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.
- Parameters:
base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)
Disables the LPI2C master interrupt requests.
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.
- Parameters:
base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)
Returns the set of currently enabled LPI2C master interrupt requests.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.
-
static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)
Enables or disables LPI2C master DMA requests.
- Parameters:
base – The LPI2C peripheral base address.
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.
-
static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)
Gets LPI2C master transmit data register address for DMA transfer.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
The LPI2C Master Transmit Data Register address.
-
static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)
Gets LPI2C master receive data register address for DMA transfer.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
The LPI2C Master Receive Data Register address.
-
static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)
Sets the watermarks for LPI2C master FIFOs.
- Parameters:
base – The LPI2C peripheral base address.
txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated.
rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated.
-
static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)
Gets the current number of words in the LPI2C master FIFOs.
- Parameters:
base – The LPI2C peripheral base address.
txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required.
-
void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)
Sets the I2C bus frequency for master transactions.
The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.
Note
Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.
- Parameters:
base – The LPI2C peripheral base address.
sourceClock_Hz – LPI2C functional clock frequency in Hertz.
baudRate_Hz – Requested bus frequency in Hertz.
-
static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)
Returns whether the bus is idle.
Requires the master mode to be enabled.
- Parameters:
base – The LPI2C peripheral base address.
- Return values:
true – Bus is busy.
false – Bus is idle.
-
status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)
Sends a START signal and slave address on the I2C bus.
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.
- Parameters:
base – The LPI2C peripheral base address.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
- Return values:
kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
-
static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)
Sends a repeated START signal and slave address on the I2C bus.
This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.
Note
This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.
- Parameters:
base – The LPI2C peripheral base address.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.
- Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
-
status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)
Performs a polling send transfer on the I2C bus.
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.
- Parameters:
base – The LPI2C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
- Return values:
kStatus_Success – Data was sent successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or over run.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.
-
status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
Performs a polling receive transfer on the I2C bus.
- Parameters:
base – The LPI2C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
- Return values:
kStatus_Success – Data was received successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.
-
status_t LPI2C_MasterStop(LPI2C_Type *base)
Sends a STOP signal on the I2C bus.
This function does not return until the STOP signal is seen on the bus, or an error occurs.
- Parameters:
base – The LPI2C peripheral base address.
- Return values:
kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.
-
status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)
Performs a master polling transfer on the I2C bus.
Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.
- Parameters:
base – The LPI2C peripheral base address.
transfer – Pointer to the transfer structure.
- Return values:
kStatus_Success – Data was received successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.
-
void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)
Creates a new handle for the LPI2C master non-blocking APIs.
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.
Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.
- Parameters:
base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C master driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
-
status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)
Performs a non-blocking transaction on the I2C bus.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
transfer – The pointer to the transfer descriptor.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.
-
status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)
Returns number of bytes transferred so far.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
Terminates a non-blocking LPI2C master transmission early.
Note
It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
-
void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)
Reusable routine to handle master interrupts.
Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The LPI2C peripheral base address.
lpi2cMasterHandle – Pointer to the LPI2C master driver handle.
-
enum _lpi2c_master_flags
LPI2C master peripheral flags.
The following status register flags can be cleared:
kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.
Note
These enums are meant to be OR’d together to form a bit mask.
Values:
-
enumerator kLPI2C_MasterTxReadyFlag
Transmit data flag
-
enumerator kLPI2C_MasterRxReadyFlag
Receive data flag
-
enumerator kLPI2C_MasterEndOfPacketFlag
End Packet flag
-
enumerator kLPI2C_MasterStopDetectFlag
Stop detect flag
-
enumerator kLPI2C_MasterNackDetectFlag
NACK detect flag
-
enumerator kLPI2C_MasterArbitrationLostFlag
Arbitration lost flag
-
enumerator kLPI2C_MasterFifoErrFlag
FIFO error flag
-
enumerator kLPI2C_MasterPinLowTimeoutFlag
Pin low timeout flag
-
enumerator kLPI2C_MasterDataMatchFlag
Data match flag
-
enumerator kLPI2C_MasterBusyFlag
Master busy flag
-
enumerator kLPI2C_MasterBusBusyFlag
Bus busy flag
-
enumerator kLPI2C_MasterClearFlags
All flags which are cleared by the driver upon starting a transfer.
-
enumerator kLPI2C_MasterIrqFlags
IRQ sources enabled by the non-blocking transactional API.
-
enumerator kLPI2C_MasterErrorFlags
Errors to check for.
-
enum _lpi2c_direction
Direction of master and slave transfers.
Values:
-
enumerator kLPI2C_Write
Master transmit.
-
enumerator kLPI2C_Read
Master receive.
-
enumerator kLPI2C_Write
-
enum _lpi2c_master_pin_config
LPI2C pin configuration.
Values:
-
enumerator kLPI2C_2PinOpenDrain
LPI2C Configured for 2-pin open drain mode
-
enumerator kLPI2C_2PinOutputOnly
LPI2C Configured for 2-pin output only mode (ultra-fast mode)
-
enumerator kLPI2C_2PinPushPull
LPI2C Configured for 2-pin push-pull mode
-
enumerator kLPI2C_4PinPushPull
LPI2C Configured for 4-pin push-pull mode
-
enumerator kLPI2C_2PinOpenDrainWithSeparateSlave
LPI2C Configured for 2-pin open drain mode with separate LPI2C slave
-
enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave
LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave
-
enumerator kLPI2C_2PinPushPullWithSeparateSlave
LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave
-
enumerator kLPI2C_4PinPushPullWithInvertedOutput
LPI2C Configured for 4-pin push-pull mode(inverted outputs)
-
enumerator kLPI2C_2PinOpenDrain
-
enum _lpi2c_host_request_source
LPI2C master host request selection.
Values:
-
enumerator kLPI2C_HostRequestExternalPin
Select the LPI2C_HREQ pin as the host request input
-
enumerator kLPI2C_HostRequestInputTrigger
Select the input trigger as the host request input
-
enumerator kLPI2C_HostRequestExternalPin
-
enum _lpi2c_host_request_polarity
LPI2C master host request pin polarity configuration.
Values:
-
enumerator kLPI2C_HostRequestPinActiveLow
Configure the LPI2C_HREQ pin active low
-
enumerator kLPI2C_HostRequestPinActiveHigh
Configure the LPI2C_HREQ pin active high
-
enumerator kLPI2C_HostRequestPinActiveLow
-
enum _lpi2c_data_match_config_mode
LPI2C master data match configuration modes.
Values:
-
enumerator kLPI2C_MatchDisabled
LPI2C Match Disabled
-
enumerator kLPI2C_1stWordEqualsM0OrM1
LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1
-
enumerator kLPI2C_AnyWordEqualsM0OrM1
LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1
-
enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1
LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1
-
enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1
LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1
-
enumerator kLPI2C_1stWordAndM1EqualsM0AndM1
LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1
-
enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1
LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1
-
enumerator kLPI2C_MatchDisabled
-
enum _lpi2c_master_transfer_flags
Transfer option flags.
Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field.
Values:
-
enumerator kLPI2C_TransferDefaultFlag
Transfer starts with a start signal, stops with a stop signal.
-
enumerator kLPI2C_TransferNoStartFlag
Don’t send a start condition, address, and sub address
-
enumerator kLPI2C_TransferRepeatedStartFlag
Send a repeated start condition
-
enumerator kLPI2C_TransferNoStopFlag
Don’t send a stop condition.
-
enumerator kLPI2C_TransferDefaultFlag
-
typedef enum _lpi2c_direction lpi2c_direction_t
Direction of master and slave transfers.
-
typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t
LPI2C pin configuration.
-
typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t
LPI2C master host request selection.
-
typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t
LPI2C master host request pin polarity configuration.
-
typedef struct _lpi2c_master_config lpi2c_master_config_t
Structure with settings to initialize the LPI2C master module.
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
-
typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t
LPI2C master data match configuration modes.
-
typedef struct _lpi2c_match_config lpi2c_data_match_config_t
LPI2C master data match configuration structure.
-
typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t
LPI2C master descriptor of the transfer.
-
typedef struct _lpi2c_master_handle lpi2c_master_handle_t
LPI2C master handle of the transfer.
-
typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)
Master completion callback function pointer type.
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().
- Param base:
The LPI2C peripheral base address.
- Param handle:
Pointer to the LPI2C master driver handle.
- Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed.
- Param userData:
Arbitrary pointer-sized value passed from the application.
-
typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)
Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs.
-
struct _lpi2c_master_config
- #include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C master module.
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
Public Members
-
bool enableMaster
Whether to enable master mode.
-
bool enableDoze
Whether master is enabled in doze mode.
-
bool debugEnable
Enable transfers to continue when halted in debug mode.
-
bool ignoreAck
Whether to ignore ACK/NACK.
-
lpi2c_master_pin_config_t pinConfig
The pin configuration option.
-
uint32_t baudRate_Hz
Desired baud rate in Hertz.
-
uint32_t busIdleTimeout_ns
Bus idle timeout in nanoseconds. Set to 0 to disable.
-
uint32_t pinLowTimeout_ns
Pin low timeout in nanoseconds. Set to 0 to disable.
-
uint8_t sdaGlitchFilterWidth_ns
Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable.
-
uint8_t sclGlitchFilterWidth_ns
Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable.
-
struct _lpi2c_master_config hostRequest
Host request options.
-
bool enableMaster
-
struct _lpi2c_match_config
- #include <fsl_lpi2c.h>
LPI2C master data match configuration structure.
Public Members
-
lpi2c_data_match_config_mode_t matchMode
Data match configuration setting.
-
bool rxDataMatchOnly
When set to true, received data is ignored until a successful match.
-
uint32_t match0
Match value 0.
-
uint32_t match1
Match value 1.
-
lpi2c_data_match_config_mode_t matchMode
-
struct _lpi2c_master_transfer
- #include <fsl_lpi2c.h>
Non-blocking transfer descriptor structure.
This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API.
Public Members
-
uint32_t flags
Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers.
-
uint16_t slaveAddress
The 7-bit slave address.
-
lpi2c_direction_t direction
Either kLPI2C_Read or kLPI2C_Write.
-
uint32_t subaddress
Sub address. Transferred MSB first.
-
size_t subaddressSize
Length of sub address to send in bytes. Maximum size is 4 bytes.
-
void *data
Pointer to data to transfer.
-
size_t dataSize
Number of bytes to transfer.
-
uint32_t flags
-
struct _lpi2c_master_handle
- #include <fsl_lpi2c.h>
Driver handle for master non-blocking APIs.
Note
The contents of this structure are private and subject to change.
Public Members
-
uint8_t state
Transfer state machine current state.
-
uint16_t remainingBytes
Remaining byte count in current state.
-
uint8_t *buf
Buffer pointer for current state.
-
uint16_t commandBuffer[6]
LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word]
-
lpi2c_master_transfer_t transfer
Copy of the current transfer info.
-
lpi2c_master_transfer_callback_t completionCallback
Callback function pointer.
-
void *userData
Application data passed to callback.
-
uint8_t state
-
struct hostRequest
Public Members
-
bool enable
Enable host request.
-
lpi2c_host_request_source_t source
Host request source.
-
lpi2c_host_request_polarity_t polarity
Host request pin polarity.
-
bool enable
LPI2C Master DMA Driver
-
void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)
Create a new handle for the LPI2C master DMA APIs.
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.
For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.
- Parameters:
base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C master driver handle.
rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function.
txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
-
status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)
Performs a non-blocking DMA-based transaction on the I2C bus.
The callback specified when the handle was created is invoked when the transaction has completed.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
transfer – The pointer to the transfer descriptor.
- Return values:
kStatus_Success – The transaction was started successfully.
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.
-
status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)
Returns number of bytes transferred so far.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.
-
status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)
Terminates a non-blocking LPI2C master transmission early.
Note
It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
- Return values:
kStatus_Success – A transaction was successfully aborted.
kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress.
-
typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t
LPI2C master EDMA handle of the transfer.
-
typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)
Master DMA completion callback function pointer type.
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().
- Param base:
The LPI2C peripheral base address.
- Param handle:
Handle associated with the completed transfer.
- Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed.
- Param userData:
Arbitrary pointer-sized value passed from the application.
-
struct _lpi2c_master_edma_handle
- #include <fsl_lpi2c_edma.h>
Driver handle for master DMA APIs.
Note
The contents of this structure are private and subject to change.
Public Members
-
LPI2C_Type *base
LPI2C base pointer.
-
bool isBusy
Transfer state machine current state.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
uint16_t commandBuffer[10]
LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words]
-
lpi2c_master_transfer_t transfer
Copy of the current transfer info.
-
lpi2c_master_edma_transfer_callback_t completionCallback
Callback function pointer.
-
void *userData
Application data passed to callback.
-
edma_handle_t *rx
Handle for receive DMA channel.
-
edma_handle_t *tx
Handle for transmit DMA channel.
-
edma_tcd_t tcds[3]
Software TCD. Three are allocated to provide enough room to align to 32-bytes.
-
LPI2C_Type *base
LPI2C Slave Driver
-
void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)
Provides a default configuration for the LPI2C slave peripheral.
This function provides the following default configuration for the LPI2C slave peripheral:
slaveConfig->enableSlave = true; slaveConfig->address0 = 0U; slaveConfig->address1 = 0U; slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; slaveConfig->filterDozeEnable = true; slaveConfig->filterEnable = true; slaveConfig->enableGeneralCall = false; slaveConfig->sclStall.enableAck = false; slaveConfig->sclStall.enableTx = true; slaveConfig->sclStall.enableRx = true; slaveConfig->sclStall.enableAddress = true; slaveConfig->ignoreAck = false; slaveConfig->enableReceivedAddressRead = false; slaveConfig->sdaGlitchFilterWidth_ns = 0; slaveConfig->sclGlitchFilterWidth_ns = 0; slaveConfig->dataValidDelay_ns = 0; slaveConfig->clockHoldTime_ns = 0;
After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.
- Parameters:
slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t.
-
void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)
Initializes the LPI2C slave peripheral.
This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.
- Parameters:
base – The LPI2C peripheral base address.
slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time.
-
void LPI2C_SlaveDeinit(LPI2C_Type *base)
Deinitializes the LPI2C slave peripheral.
This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.
- Parameters:
base – The LPI2C peripheral base address.
-
static inline void LPI2C_SlaveReset(LPI2C_Type *base)
Performs a software reset of the LPI2C slave peripheral.
- Parameters:
base – The LPI2C peripheral base address.
-
static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)
Enables or disables the LPI2C module as slave.
- Parameters:
base – The LPI2C peripheral base address.
enable – Pass true to enable or false to disable the specified LPI2C as slave.
-
static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)
Gets the LPI2C slave status flags.
A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.
See also
_lpi2c_slave_flags
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
State of the status flags:
1: related status flag is set.
0: related status flag is not set.
-
static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)
Clears the LPI2C status flag state.
The following status register flags can be cleared:
kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag
Attempts to clear other flags has no effect.
See also
_lpi2c_slave_flags.
- Parameters:
base – The LPI2C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags().
-
static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)
Enables the LPI2C slave interrupt requests.
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.
- Parameters:
base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)
Disables the LPI2C slave interrupt requests.
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.
- Parameters:
base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.
-
static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)
Returns the set of currently enabled LPI2C slave interrupt requests.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.
-
static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)
Enables or disables the LPI2C slave peripheral DMA requests.
- Parameters:
base – The LPI2C peripheral base address.
enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request.
enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable.
enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable.
-
static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)
Returns whether the bus is idle.
Requires the slave mode to be enabled.
- Parameters:
base – The LPI2C peripheral base address.
- Return values:
true – Bus is busy.
false – Bus is idle.
-
static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)
Transmits either an ACK or NAK on the I2C bus in response to a byte from the master.
Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.
- Parameters:
base – The LPI2C peripheral base address.
ackOrNack – Pass true for an ACK or false for a NAK.
-
static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)
Enables or disables ACKSTALL.
When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.
- Parameters:
base – The LPI2C peripheral base address.
enable – True will enable ACKSTALL,false will disable ACKSTALL.
-
static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)
Returns the slave address sent by the I2C master.
This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.
- Parameters:
base – The LPI2C peripheral base address.
- Returns:
The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits.
-
status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)
Performs a polling send transfer on the I2C bus.
- Parameters:
base – The LPI2C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
actualTxSize – [out]
- Returns:
Error or success status returned by API.
-
status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)
Performs a polling receive transfer on the I2C bus.
- Parameters:
base – The LPI2C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
actualRxSize – [out]
- Returns:
Error or success status returned by API.
-
void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)
Creates a new handle for the LPI2C slave non-blocking APIs.
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.
Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.
- Parameters:
base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C slave driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.
-
status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)
Starts accepting slave transfers.
Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.
- Return values:
kStatus_Success – Slave transfers were successfully started.
kStatus_LPI2C_Busy – Slave transfers have already been started on this handle.
-
status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)
Gets the slave transfer status during a non-blocking transfer.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to i2c_slave_handle_t structure.
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.
- Return values:
kStatus_Success –
kStatus_NoTransferInProgress –
-
void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
Aborts the slave non-blocking transfers.
Note
This API could be called at any time to stop slave for handling the bus events.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
-
void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
Reusable routine to handle slave interrupts.
Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.
- Parameters:
base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
-
enum _lpi2c_slave_flags
LPI2C slave peripheral flags.
The following status register flags can be cleared:
kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.
Note
These enumerations are meant to be OR’d together to form a bit mask.
Values:
-
enumerator kLPI2C_SlaveTxReadyFlag
Transmit data flag
-
enumerator kLPI2C_SlaveRxReadyFlag
Receive data flag
-
enumerator kLPI2C_SlaveAddressValidFlag
Address valid flag
-
enumerator kLPI2C_SlaveTransmitAckFlag
Transmit ACK flag
-
enumerator kLPI2C_SlaveRepeatedStartDetectFlag
Repeated start detect flag
-
enumerator kLPI2C_SlaveStopDetectFlag
Stop detect flag
-
enumerator kLPI2C_SlaveBitErrFlag
Bit error flag
-
enumerator kLPI2C_SlaveFifoErrFlag
FIFO error flag
-
enumerator kLPI2C_SlaveAddressMatch0Flag
Address match 0 flag
-
enumerator kLPI2C_SlaveAddressMatch1Flag
Address match 1 flag
-
enumerator kLPI2C_SlaveGeneralCallFlag
General call flag
-
enumerator kLPI2C_SlaveBusyFlag
Master busy flag
-
enumerator kLPI2C_SlaveBusBusyFlag
Bus busy flag
-
enumerator kLPI2C_SlaveClearFlags
All flags which are cleared by the driver upon starting a transfer.
-
enumerator kLPI2C_SlaveIrqFlags
IRQ sources enabled by the non-blocking transactional API.
-
enumerator kLPI2C_SlaveErrorFlags
Errors to check for.
-
enum _lpi2c_slave_address_match
LPI2C slave address match options.
Values:
-
enumerator kLPI2C_MatchAddress0
Match only address 0.
-
enumerator kLPI2C_MatchAddress0OrAddress1
Match either address 0 or address 1.
-
enumerator kLPI2C_MatchAddress0ThroughAddress1
Match a range of slave addresses from address 0 through address 1.
-
enumerator kLPI2C_MatchAddress0
-
enum _lpi2c_slave_transfer_event
Set of events sent to the callback for non blocking slave transfers.
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.
Note
These enumerations are meant to be OR’d together to form a bit mask of events.
Values:
-
enumerator kLPI2C_SlaveAddressMatchEvent
Received the slave address after a start or repeated start.
-
enumerator kLPI2C_SlaveTransmitEvent
Callback is requested to provide data to transmit (slave-transmitter role).
-
enumerator kLPI2C_SlaveReceiveEvent
Callback is requested to provide a buffer in which to place received data (slave-receiver role).
-
enumerator kLPI2C_SlaveTransmitAckEvent
Callback needs to either transmit an ACK or NACK.
-
enumerator kLPI2C_SlaveRepeatedStartEvent
A repeated start was detected.
-
enumerator kLPI2C_SlaveCompletionEvent
A stop was detected, completing the transfer.
-
enumerator kLPI2C_SlaveAllEvents
Bit mask of all available events.
-
enumerator kLPI2C_SlaveAddressMatchEvent
-
typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t
LPI2C slave address match options.
-
typedef struct _lpi2c_slave_config lpi2c_slave_config_t
Structure with settings to initialize the LPI2C slave module.
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
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typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t
Set of events sent to the callback for non blocking slave transfers.
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.
Note
These enumerations are meant to be OR’d together to form a bit mask of events.
-
typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t
LPI2C slave transfer structure.
-
typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t
LPI2C slave handle structure.
-
typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)
Slave event callback function pointer type.
This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.
- Param base:
Base address for the LPI2C instance on which the event occurred.
- Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback.
- Param userData:
Arbitrary pointer-sized value passed from the application.
-
struct _lpi2c_slave_config
- #include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C slave module.
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash.
Public Members
-
bool enableSlave
Enable slave mode.
-
uint8_t address0
Slave’s 7-bit address.
-
uint8_t address1
Alternate slave 7-bit address.
-
lpi2c_slave_address_match_t addressMatchMode
Address matching options.
-
bool filterDozeEnable
Enable digital glitch filter in doze mode.
-
bool filterEnable
Enable digital glitch filter.
-
bool enableGeneralCall
Enable general call address matching.
-
struct _lpi2c_slave_config sclStall
SCL stall enable options.
-
bool ignoreAck
Continue transfers after a NACK is detected.
-
bool enableReceivedAddressRead
Enable reading the address received address as the first byte of data.
-
uint32_t sdaGlitchFilterWidth_ns
Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable.
-
uint32_t sclGlitchFilterWidth_ns
Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable.
-
uint32_t dataValidDelay_ns
Width in nanoseconds of the data valid delay.
-
uint32_t clockHoldTime_ns
Width in nanoseconds of the clock hold time.
-
bool enableSlave
-
struct _lpi2c_slave_transfer
- #include <fsl_lpi2c.h>
LPI2C slave transfer structure.
Public Members
-
lpi2c_slave_transfer_event_t event
Reason the callback is being invoked.
-
uint8_t receivedAddress
Matching address send by master.
-
uint8_t *data
Transfer buffer
-
size_t dataSize
Transfer size
-
status_t completionStatus
Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent.
-
size_t transferredCount
Number of bytes actually transferred since start or last repeated start.
-
lpi2c_slave_transfer_event_t event
-
struct _lpi2c_slave_handle
- #include <fsl_lpi2c.h>
LPI2C slave handle structure.
Note
The contents of this structure are private and subject to change.
Public Members
-
lpi2c_slave_transfer_t transfer
LPI2C slave transfer copy.
-
bool isBusy
Whether transfer is busy.
-
bool wasTransmit
Whether the last transfer was a transmit.
-
uint32_t eventMask
Mask of enabled events.
-
uint32_t transferredCount
Count of bytes transferred.
-
lpi2c_slave_transfer_callback_t callback
Callback function called at transfer event.
-
void *userData
Callback parameter passed to callback.
-
lpi2c_slave_transfer_t transfer
-
struct sclStall
Public Members
-
bool enableAck
Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall.
-
bool enableTx
Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer.
-
bool enableRx
Enables SCL clock stretching when receive data flag is set during a slave-receive transfer.
-
bool enableAddress
Enables SCL clock stretching when the address valid flag is asserted.
-
bool enableAck
LPIT: Low-Power Interrupt Timer
-
enum _lpit_chnl
List of LPIT channels.
Note
Actual number of available channels is SoC-dependent
Values:
-
enumerator kLPIT_Chnl_0
LPIT channel number 0
-
enumerator kLPIT_Chnl_1
LPIT channel number 1
-
enumerator kLPIT_Chnl_2
LPIT channel number 2
-
enumerator kLPIT_Chnl_3
LPIT channel number 3
-
enumerator kLPIT_Chnl_0
-
enum _lpit_timer_modes
Mode options available for the LPIT timer.
Values:
-
enumerator kLPIT_PeriodicCounter
Use the all 32-bits, counter loads and decrements to zero
-
enumerator kLPIT_DualPeriodicCounter
Counter loads, lower 16-bits decrement to zero, then upper 16-bits decrement
-
enumerator kLPIT_TriggerAccumulator
Counter loads on first trigger and decrements on each trigger
-
enumerator kLPIT_InputCapture
Counter loads with 0xFFFFFFFF, decrements to zero. It stores the inverse of the current value when a input trigger is detected
-
enumerator kLPIT_PeriodicCounter
-
enum _lpit_trigger_select
Trigger options available.
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual.
Values:
-
enumerator kLPIT_Trigger_TimerChn0
Channel 0 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn1
Channel 1 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn2
Channel 2 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn3
Channel 3 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn4
Channel 4 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn5
Channel 5 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn6
Channel 6 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn7
Channel 7 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn8
Channel 8 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn9
Channel 9 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn10
Channel 10 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn11
Channel 11 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn12
Channel 12 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn13
Channel 13 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn14
Channel 14 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn15
Channel 15 is selected as a trigger source
-
enumerator kLPIT_Trigger_TimerChn0
-
enum _lpit_trigger_source
Trigger source options available.
Values:
-
enumerator kLPIT_TriggerSource_External
Use external trigger input
-
enumerator kLPIT_TriggerSource_Internal
Use internal trigger
-
enumerator kLPIT_TriggerSource_External
-
enum _lpit_interrupt_enable
List of LPIT interrupts.
Note
Number of timer channels are SoC-specific. See the SoC Reference Manual.
Values:
-
enumerator kLPIT_Channel0TimerInterruptEnable
Channel 0 Timer interrupt
-
enumerator kLPIT_Channel1TimerInterruptEnable
Channel 1 Timer interrupt
-
enumerator kLPIT_Channel2TimerInterruptEnable
Channel 2 Timer interrupt
-
enumerator kLPIT_Channel3TimerInterruptEnable
Channel 3 Timer interrupt
-
enumerator kLPIT_Channel0TimerInterruptEnable
-
enum _lpit_status_flags
List of LPIT status flags.
Note
Number of timer channels are SoC-specific. See the SoC Reference Manual.
Values:
-
enumerator kLPIT_Channel0TimerFlag
Channel 0 Timer interrupt flag
-
enumerator kLPIT_Channel1TimerFlag
Channel 1 Timer interrupt flag
-
enumerator kLPIT_Channel2TimerFlag
Channel 2 Timer interrupt flag
-
enumerator kLPIT_Channel3TimerFlag
Channel 3 Timer interrupt flag
-
enumerator kLPIT_Channel0TimerFlag
-
typedef enum _lpit_chnl lpit_chnl_t
List of LPIT channels.
Note
Actual number of available channels is SoC-dependent
-
typedef enum _lpit_timer_modes lpit_timer_modes_t
Mode options available for the LPIT timer.
-
typedef enum _lpit_trigger_select lpit_trigger_select_t
Trigger options available.
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual.
-
typedef enum _lpit_trigger_source lpit_trigger_source_t
Trigger source options available.
-
typedef enum _lpit_interrupt_enable lpit_interrupt_enable_t
List of LPIT interrupts.
Note
Number of timer channels are SoC-specific. See the SoC Reference Manual.
-
typedef enum _lpit_status_flags lpit_status_flags_t
List of LPIT status flags.
Note
Number of timer channels are SoC-specific. See the SoC Reference Manual.
-
typedef struct _lpit_chnl_params lpit_chnl_params_t
Structure to configure the channel timer.
-
typedef struct _lpit_config lpit_config_t
LPIT configuration structure.
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash.
-
FSL_LPIT_DRIVER_VERSION
Version 2.1.1
-
void LPIT_Init(LPIT_Type *base, const lpit_config_t *config)
Ungates the LPIT clock and configures the peripheral for a basic operation.
This function issues a software reset to reset all channels and registers except the Module Control register.
Note
This API should be called at the beginning of the application using the LPIT driver.
- Parameters:
base – LPIT peripheral base address.
config – Pointer to the user configuration structure.
-
void LPIT_Deinit(LPIT_Type *base)
Disables the module and gates the LPIT clock.
- Parameters:
base – LPIT peripheral base address.
-
void LPIT_GetDefaultConfig(lpit_config_t *config)
Fills in the LPIT configuration structure with default settings.
The default values are:
config->enableRunInDebug = false; config->enableRunInDoze = false;
- Parameters:
config – Pointer to the user configuration structure.
-
status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl_params_t *chnlSetup)
Sets up an LPIT channel based on the user’s preference.
This function sets up the operation mode to one of the options available in the enumeration lpit_timer_modes_t. It sets the trigger source as either internal or external, trigger selection and the timers behaviour when a timeout occurs. It also chains the timer if a prior timer if requested by the user.
- Parameters:
base – LPIT peripheral base address.
channel – Channel that is being configured.
chnlSetup – Configuration parameters.
-
static inline void LPIT_EnableInterrupts(LPIT_Type *base, uint32_t mask)
Enables the selected PIT interrupts.
- Parameters:
base – LPIT peripheral base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t
-
static inline void LPIT_DisableInterrupts(LPIT_Type *base, uint32_t mask)
Disables the selected PIT interrupts.
- Parameters:
base – LPIT peripheral base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t
-
static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type *base)
Gets the enabled LPIT interrupts.
- Parameters:
base – LPIT peripheral base address.
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lpit_interrupt_enable_t
-
static inline uint32_t LPIT_GetStatusFlags(LPIT_Type *base)
Gets the LPIT status flags.
- Parameters:
base – LPIT peripheral base address.
- Returns:
The status flags. This is the logical OR of members of the enumeration lpit_status_flags_t
-
static inline void LPIT_ClearStatusFlags(LPIT_Type *base, uint32_t mask)
Clears the LPIT status flags.
- Parameters:
base – LPIT peripheral base address.
mask – The status flags to clear. This is a logical OR of members of the enumeration lpit_status_flags_t
-
static inline void LPIT_SetTimerPeriod(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)
Sets the timer period in units of count.
Timers begin counting down from the value set by this function until it reaches 0, at which point it generates an interrupt and loads this register value again. Writing a new value to this register does not restart the timer. Instead, the value is loaded after the timer expires.
Note
User can call the utility macros provided in fsl_common.h to convert to ticks.
- Parameters:
base – LPIT peripheral base address.
channel – Timer channel number.
ticks – Timer period in units of ticks.
-
static inline void LPIT_SetTimerValue(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)
Sets the timer period in units of count.
In the Dual 16-bit Periodic Counter mode, the counter will load and then the lower 16-bits will decrement down to zero, which will assert the output pre-trigger. The upper 16-bits will then decrement down to zero, which will negate the output pre-trigger and set the timer interrupt flag.
Note
Set TVAL register to 0 or 1 is invalid in compare mode.
- Parameters:
base – LPIT peripheral base address.
channel – Timer channel number.
ticks – Timer period in units of ticks.
-
static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type *base, lpit_chnl_t channel)
Reads the current timer counting value.
This function returns the real-time timer counting value, in a range from 0 to a timer period.
Note
User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds.
- Parameters:
base – LPIT peripheral base address.
channel – Timer channel number.
- Returns:
Current timer counting value in ticks.
-
static inline void LPIT_StartTimer(LPIT_Type *base, lpit_chnl_t channel)
Starts the timer counting.
After calling this function, timers load the period value and count down to 0. When the timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.
- Parameters:
base – LPIT peripheral base address.
channel – Timer channel number.
-
static inline void LPIT_StopTimer(LPIT_Type *base, lpit_chnl_t channel)
Stops the timer counting.
- Parameters:
base – LPIT peripheral base address.
channel – Timer channel number.
-
static inline void LPIT_Reset(LPIT_Type *base)
Performs a software reset on the LPIT module.
This resets all channels and registers except the Module Control Register.
- Parameters:
base – LPIT peripheral base address.
-
struct _lpit_chnl_params
- #include <fsl_lpit.h>
Structure to configure the channel timer.
Public Members
-
bool chainChannel
true: Timer chained to previous timer; false: Timer not chained
-
lpit_timer_modes_t timerMode
Timers mode of operation.
-
lpit_trigger_select_t triggerSelect
Trigger selection for the timer
-
lpit_trigger_source_t triggerSource
Decides if we use external or internal trigger.
-
bool enableReloadOnTrigger
true: Timer reloads when a trigger is detected; false: No effect
-
bool enableStopOnTimeout
true: Timer will stop after timeout; false: does not stop after timeout
-
bool enableStartOnTrigger
true: Timer starts when a trigger is detected; false: decrement immediately
-
bool chainChannel
-
struct _lpit_config
- #include <fsl_lpit.h>
LPIT configuration structure.
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash.
Public Members
-
bool enableRunInDebug
true: Timers run in debug mode; false: Timers stop in debug mode
-
bool enableRunInDoze
true: Timers run in doze mode; false: Timers stop in doze mode
-
bool enableRunInDebug
LPSPI: Low Power Serial Peripheral Interface
LPSPI Peripheral driver
-
void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
Initializes the LPSPI master.
- Parameters:
base – LPSPI peripheral address.
masterConfig – Pointer to structure lpspi_master_config_t.
srcClock_Hz – Module source input clock in Hertz
-
void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
Sets the lpspi_master_config_t structure to default values.
This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:
lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig);
- Parameters:
masterConfig – pointer to lpspi_master_config_t structure
-
void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
LPSPI slave configuration.
- Parameters:
base – LPSPI peripheral address.
slaveConfig – Pointer to a structure lpspi_slave_config_t.
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void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)
Sets the lpspi_slave_config_t structure to default values.
This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:
lpspi_slave_config_t slaveConfig; LPSPI_SlaveGetDefaultConfig(&slaveConfig);
- Parameters:
slaveConfig – pointer to lpspi_slave_config_t structure.
-
void LPSPI_Deinit(LPSPI_Type *base)
De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
- Parameters:
base – LPSPI peripheral address.
-
void LPSPI_Reset(LPSPI_Type *base)
Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API.
- Parameters:
base – LPSPI peripheral address.
-
uint32_t LPSPI_GetInstance(LPSPI_Type *base)
Get the LPSPI instance from peripheral base address.
- Parameters:
base – LPSPI peripheral base address.
- Returns:
LPSPI instance.
-
static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
Enables the LPSPI peripheral and sets the MCR MDIS to 0.
- Parameters:
base – LPSPI peripheral address.
enable – Pass true to enable module, false to disable module.
-
static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
Gets the LPSPI status flag state.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The LPSPI status(in SR register).
-
static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
Gets the LPSPI Tx FIFO size.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The LPSPI Tx FIFO size.
-
static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
Gets the LPSPI Rx FIFO size.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The LPSPI Rx FIFO size.
-
static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
Gets the LPSPI Tx FIFO count.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The number of words in the transmit FIFO.
-
static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
Gets the LPSPI Rx FIFO count.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The number of words in the receive FIFO.
-
static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
Clears the LPSPI status flag.
This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:
LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);
- Parameters:
base – LPSPI peripheral address.
statusFlags – The status flag used from type _lpspi_flags.
-
static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)
-
static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
Enables the LPSPI interrupts.
This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
- Parameters:
base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.
-
static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
Disables the LPSPI interrupts.
LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
- Parameters:
base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.
-
static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
Enables the LPSPI DMA request.
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
- Parameters:
base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_dma_enable.
-
static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
Disables the LPSPI DMA request.
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
- Parameters:
base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_dma_enable.
-
static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
Gets the LPSPI Transmit Data Register address for a DMA operation.
This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The LPSPI Transmit Data Register address.
-
static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
Gets the LPSPI Receive Data Register address for a DMA operation.
This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The LPSPI Receive Data Register address.
-
bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)
Check the argument for transfer .
- Parameters:
base – LPSPI peripheral address.
transfer – the transfer struct to be used.
isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer
- Returns:
Return true for right and false for wrong.
-
static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
Configures the LPSPI for either master or slave.
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
- Parameters:
base – LPSPI peripheral address.
mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t.
-
static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)
Configures the peripheral chip select used for the transfer.
- Parameters:
base – LPSPI peripheral address.
select – LPSPI Peripheral Chip Select (PCS) configuration.
-
static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)
Set the PCS signal to continuous or uncontinuous mode.
Note
In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).
- Parameters:
base – LPSPI peripheral address.
IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.
-
static inline bool LPSPI_IsMaster(LPSPI_Type *base)
Returns whether the LPSPI module is in master mode.
- Parameters:
base – LPSPI peripheral address.
- Returns:
Returns true if the module is in master mode or false if the module is in slave mode.
-
static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
Flushes the LPSPI FIFOs.
- Parameters:
base – LPSPI peripheral address.
flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.
-
static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
Sets the transmit and receive FIFO watermark values.
This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.
- Parameters:
base – LPSPI peripheral address.
txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
-
static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
Configures all LPSPI peripheral chip select polarities simultaneously.
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.
LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);
- Parameters:
base – LPSPI peripheral address.
mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity.
-
static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
Configures the frame size.
The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.
Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.
- Parameters:
base – LPSPI peripheral address.
frameSize – The frame size in number of bits.
-
uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)
Sets the LPSPI baud rate in bits per second.
This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.
- Parameters:
base – LPSPI peripheral address.
baudRate_Bps – The desired baud rate in bits per second.
srcClock_Hz – Module source input clock in Hertz.
tcrPrescaleValue – The TCR prescale value needed to program the TCR.
- Returns:
The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.
-
void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)
Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).
This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.
The delay names are available in type lpspi_delay_type_t.
The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.
- Parameters:
base – LPSPI peripheral address.
scaler – The 8-bit delay value 0x00 to 0xFF (255).
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.
-
uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)
Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).
This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.
The delay names are available in type lpspi_delay_type_t.
The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.
Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
- Parameters:
base – LPSPI peripheral address.
delayTimeInNanoSec – The desired delay value in nano-seconds.
whichDelay – The desired delay to configuration, which must be of type lpspi_delay_type_t.
srcClock_Hz – Module source input clock in Hertz.
- Returns:
actual Calculated delay value in nano-seconds.
-
static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)
Writes data into the transmit data buffer.
This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.
- Parameters:
base – LPSPI peripheral address.
data – The data word to be sent.
-
static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)
Reads data from the data buffer.
This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.
- Parameters:
base – LPSPI peripheral address.
- Returns:
The data read from the data buffer.
-
void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)
Set up the dummy data.
- Parameters:
base – LPSPI peripheral address.
dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.
-
void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)
Initializes the LPSPI master handle.
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
- Parameters:
base – LPSPI peripheral address.
handle – LPSPI handle pointer to lpspi_master_handle_t.
callback – DSPI callback.
userData – callback function parameter.
-
status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)
LPSPI master transfer data using a polling method.
This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral address.
transfer – pointer to lpspi_transfer_t structure.
- Returns:
status of status_t.
-
status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)
LPSPI master transfer data using an interrupt method.
This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.
- Returns:
status of status_t.
-
status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)
Gets the master transfer remaining bytes.
This function gets the master transfer remaining bytes.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Returns:
status of status_t.
-
void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)
LPSPI master abort transfer which uses an interrupt method.
This function aborts a transfer which uses an interrupt method.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
-
void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)
LPSPI Master IRQ handler function.
This function processes the LPSPI transmit and receive IRQ.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
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void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)
Initializes the LPSPI slave handle.
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
- Parameters:
base – LPSPI peripheral address.
handle – LPSPI handle pointer to lpspi_slave_handle_t.
callback – DSPI callback.
userData – callback function parameter.
-
status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)
LPSPI slave transfer data using an interrupt method.
This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.
- Returns:
status of status_t.
-
status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)
Gets the slave transfer remaining bytes.
This function gets the slave transfer remaining bytes.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.
- Returns:
status of status_t.
-
void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
LPSPI slave aborts a transfer which uses an interrupt method.
This function aborts a transfer which uses an interrupt method.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
-
void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)
LPSPI Slave IRQ handler function.
This function processes the LPSPI transmit and receives an IRQ.
- Parameters:
base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
-
bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)
Wait for tx FIFO to be empty.
This function wait the tx fifo empty
- Parameters:
base – LPSPI peripheral address.
- Returns:
true for the tx FIFO is ready, false is not.
-
FSL_LPSPI_DRIVER_VERSION
LPSPI driver version.
Status for the LPSPI driver.
Values:
-
enumerator kStatus_LPSPI_Busy
LPSPI transfer is busy.
-
enumerator kStatus_LPSPI_Error
LPSPI driver error.
-
enumerator kStatus_LPSPI_Idle
LPSPI is idle.
-
enumerator kStatus_LPSPI_OutOfRange
LPSPI transfer out Of range.
-
enumerator kStatus_LPSPI_Timeout
LPSPI timeout polling status flags.
-
enumerator kStatus_LPSPI_Busy
-
enum _lpspi_flags
LPSPI status flags in SPIx_SR register.
Values:
-
enumerator kLPSPI_TxDataRequestFlag
Transmit data flag
-
enumerator kLPSPI_RxDataReadyFlag
Receive data flag
-
enumerator kLPSPI_WordCompleteFlag
Word Complete flag
-
enumerator kLPSPI_FrameCompleteFlag
Frame Complete flag
-
enumerator kLPSPI_TransferCompleteFlag
Transfer Complete flag
-
enumerator kLPSPI_TransmitErrorFlag
Transmit Error flag (FIFO underrun)
-
enumerator kLPSPI_ReceiveErrorFlag
Receive Error flag (FIFO overrun)
-
enumerator kLPSPI_DataMatchFlag
Data Match flag
-
enumerator kLPSPI_ModuleBusyFlag
Module Busy flag
-
enumerator kLPSPI_AllStatusFlag
Used for clearing all w1c status flags
-
enumerator kLPSPI_TxDataRequestFlag
-
enum _lpspi_interrupt_enable
LPSPI interrupt source.
Values:
-
enumerator kLPSPI_TxInterruptEnable
Transmit data interrupt enable
-
enumerator kLPSPI_RxInterruptEnable
Receive data interrupt enable
-
enumerator kLPSPI_WordCompleteInterruptEnable
Word complete interrupt enable
-
enumerator kLPSPI_FrameCompleteInterruptEnable
Frame complete interrupt enable
-
enumerator kLPSPI_TransferCompleteInterruptEnable
Transfer complete interrupt enable
-
enumerator kLPSPI_TransmitErrorInterruptEnable
Transmit error interrupt enable(FIFO underrun)
-
enumerator kLPSPI_ReceiveErrorInterruptEnable
Receive Error interrupt enable (FIFO overrun)
-
enumerator kLPSPI_DataMatchInterruptEnable
Data Match interrupt enable
-
enumerator kLPSPI_AllInterruptEnable
All above interrupts enable.
-
enumerator kLPSPI_TxInterruptEnable
-
enum _lpspi_dma_enable
LPSPI DMA source.
Values:
-
enumerator kLPSPI_TxDmaEnable
Transmit data DMA enable
-
enumerator kLPSPI_RxDmaEnable
Receive data DMA enable
-
enumerator kLPSPI_TxDmaEnable
-
enum _lpspi_master_slave_mode
LPSPI master or slave mode configuration.
Values:
-
enumerator kLPSPI_Master
LPSPI peripheral operates in master mode.
-
enumerator kLPSPI_Slave
LPSPI peripheral operates in slave mode.
-
enumerator kLPSPI_Master
-
enum _lpspi_which_pcs_config
LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).
Values:
-
enumerator kLPSPI_Pcs0
PCS[0]
-
enumerator kLPSPI_Pcs1
PCS[1]
-
enumerator kLPSPI_Pcs2
PCS[2]
-
enumerator kLPSPI_Pcs3
PCS[3]
-
enumerator kLPSPI_Pcs0
-
enum _lpspi_pcs_polarity_config
LPSPI Peripheral Chip Select (PCS) Polarity configuration.
Values:
-
enumerator kLPSPI_PcsActiveHigh
PCS Active High (idles low)
-
enumerator kLPSPI_PcsActiveLow
PCS Active Low (idles high)
-
enumerator kLPSPI_PcsActiveHigh
-
enum _lpspi_pcs_polarity
LPSPI Peripheral Chip Select (PCS) Polarity.
Values:
-
enumerator kLPSPI_Pcs0ActiveLow
Pcs0 Active Low (idles high).
-
enumerator kLPSPI_Pcs1ActiveLow
Pcs1 Active Low (idles high).
-
enumerator kLPSPI_Pcs2ActiveLow
Pcs2 Active Low (idles high).
-
enumerator kLPSPI_Pcs3ActiveLow
Pcs3 Active Low (idles high).
-
enumerator kLPSPI_PcsAllActiveLow
Pcs0 to Pcs5 Active Low (idles high).
-
enumerator kLPSPI_Pcs0ActiveLow
-
enum _lpspi_clock_polarity
LPSPI clock polarity configuration.
Values:
-
enumerator kLPSPI_ClockPolarityActiveHigh
CPOL=0. Active-high LPSPI clock (idles low)
-
enumerator kLPSPI_ClockPolarityActiveLow
CPOL=1. Active-low LPSPI clock (idles high)
-
enumerator kLPSPI_ClockPolarityActiveHigh
-
enum _lpspi_clock_phase
LPSPI clock phase configuration.
Values:
-
enumerator kLPSPI_ClockPhaseFirstEdge
CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.
-
enumerator kLPSPI_ClockPhaseSecondEdge
CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.
-
enumerator kLPSPI_ClockPhaseFirstEdge
-
enum _lpspi_shift_direction
LPSPI data shifter direction options.
Values:
-
enumerator kLPSPI_MsbFirst
Data transfers start with most significant bit.
-
enumerator kLPSPI_LsbFirst
Data transfers start with least significant bit.
-
enumerator kLPSPI_MsbFirst
-
enum _lpspi_host_request_select
LPSPI Host Request select configuration.
Values:
-
enumerator kLPSPI_HostReqExtPin
Host Request is an ext pin.
-
enumerator kLPSPI_HostReqInternalTrigger
Host Request is an internal trigger.
-
enumerator kLPSPI_HostReqExtPin
-
enum _lpspi_match_config
LPSPI Match configuration options.
Values:
-
enumerator kLPSI_MatchDisabled
LPSPI Match Disabled.
-
enumerator kLPSI_1stWordEqualsM0orM1
LPSPI Match Enabled.
-
enumerator kLPSI_AnyWordEqualsM0orM1
LPSPI Match Enabled.
-
enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1
LPSPI Match Enabled.
-
enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1
LPSPI Match Enabled.
-
enumerator kLPSI_1stWordAndM1EqualsM0andM1
LPSPI Match Enabled.
-
enumerator kLPSI_AnyWordAndM1EqualsM0andM1
LPSPI Match Enabled.
-
enumerator kLPSI_MatchDisabled
-
enum _lpspi_pin_config
LPSPI pin (SDO and SDI) configuration.
Values:
-
enumerator kLPSPI_SdiInSdoOut
LPSPI SDI input, SDO output.
-
enumerator kLPSPI_SdiInSdiOut
LPSPI SDI input, SDI output.
-
enumerator kLPSPI_SdoInSdoOut
LPSPI SDO input, SDO output.
-
enumerator kLPSPI_SdoInSdiOut
LPSPI SDO input, SDI output.
-
enumerator kLPSPI_SdiInSdoOut
-
enum _lpspi_data_out_config
LPSPI data output configuration.
Values:
-
enumerator kLpspiDataOutRetained
Data out retains last value when chip select is de-asserted
-
enumerator kLpspiDataOutTristate
Data out is tristated when chip select is de-asserted
-
enumerator kLpspiDataOutRetained
-
enum _lpspi_transfer_width
LPSPI transfer width configuration.
Values:
-
enumerator kLPSPI_SingleBitXfer
1-bit shift at a time, data out on SDO, in on SDI (normal mode)
-
enumerator kLPSPI_TwoBitXfer
2-bits shift out on SDO/SDI and in on SDO/SDI
-
enumerator kLPSPI_FourBitXfer
4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]
-
enumerator kLPSPI_SingleBitXfer
-
enum _lpspi_delay_type
LPSPI delay type selection.
Values:
-
enumerator kLPSPI_PcsToSck
PCS-to-SCK delay.
-
enumerator kLPSPI_LastSckToPcs
Last SCK edge to PCS delay.
-
enumerator kLPSPI_BetweenTransfer
Delay between transfers.
-
enumerator kLPSPI_PcsToSck
-
enum _lpspi_transfer_config_flag_for_master
Use this enumeration for LPSPI master transfer configFlags.
Values:
-
enumerator kLPSPI_MasterPcs0
LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal
-
enumerator kLPSPI_MasterPcs1
LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal
-
enumerator kLPSPI_MasterPcs2
LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal
-
enumerator kLPSPI_MasterPcs3
LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal
-
enumerator kLPSPI_MasterPcsContinuous
Is PCS signal continuous
-
enumerator kLPSPI_MasterByteSwap
Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).
If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
-
enumerator kLPSPI_MasterPcs0
-
enum _lpspi_transfer_config_flag_for_slave
Use this enumeration for LPSPI slave transfer configFlags.
Values:
-
enumerator kLPSPI_SlavePcs0
LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal
-
enumerator kLPSPI_SlavePcs1
LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal
-
enumerator kLPSPI_SlavePcs2
LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal
-
enumerator kLPSPI_SlavePcs3
LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal
-
enumerator kLPSPI_SlaveByteSwap
Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).
If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
-
enumerator kLPSPI_SlavePcs0
-
enum _lpspi_transfer_state
LPSPI transfer state, which is used for LPSPI transactional API state machine.
Values:
-
enumerator kLPSPI_Idle
Nothing in the transmitter/receiver.
-
enumerator kLPSPI_Busy
Transfer queue is not finished.
-
enumerator kLPSPI_Error
Transfer error.
-
enumerator kLPSPI_Idle
-
typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t
LPSPI master or slave mode configuration.
-
typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t
LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).
-
typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t
LPSPI Peripheral Chip Select (PCS) Polarity configuration.
-
typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t
LPSPI clock polarity configuration.
-
typedef enum _lpspi_clock_phase lpspi_clock_phase_t
LPSPI clock phase configuration.
-
typedef enum _lpspi_shift_direction lpspi_shift_direction_t
LPSPI data shifter direction options.
-
typedef enum _lpspi_host_request_select lpspi_host_request_select_t
LPSPI Host Request select configuration.
-
typedef enum _lpspi_match_config lpspi_match_config_t
LPSPI Match configuration options.
-
typedef enum _lpspi_pin_config lpspi_pin_config_t
LPSPI pin (SDO and SDI) configuration.
-
typedef enum _lpspi_data_out_config lpspi_data_out_config_t
LPSPI data output configuration.
-
typedef enum _lpspi_transfer_width lpspi_transfer_width_t
LPSPI transfer width configuration.
-
typedef enum _lpspi_delay_type lpspi_delay_type_t
LPSPI delay type selection.
-
typedef struct _lpspi_master_config lpspi_master_config_t
LPSPI master configuration structure.
-
typedef struct _lpspi_slave_config lpspi_slave_config_t
LPSPI slave configuration structure.
-
typedef struct _lpspi_master_handle lpspi_master_handle_t
Forward declaration of the _lpspi_master_handle typedefs.
-
typedef struct _lpspi_slave_handle lpspi_slave_handle_t
Forward declaration of the _lpspi_slave_handle typedefs.
-
typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)
Master completion callback function pointer type.
- Param base:
LPSPI peripheral address.
- Param handle:
Pointer to the handle for the LPSPI master.
- Param status:
Success or error code describing whether the transfer is completed.
- Param userData:
Arbitrary pointer-dataSized value passed from the application.
-
typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)
Slave completion callback function pointer type.
- Param base:
LPSPI peripheral address.
- Param handle:
Pointer to the handle for the LPSPI slave.
- Param status:
Success or error code describing whether the transfer is completed.
- Param userData:
Arbitrary pointer-dataSized value passed from the application.
-
typedef struct _lpspi_transfer lpspi_transfer_t
LPSPI master/slave transfer structure.
-
volatile uint8_t g_lpspiDummyData[]
Global variable for dummy data value setting.
-
LPSPI_DUMMY_DATA
LPSPI dummy data if no Tx data.
Dummy data used for tx if there is not txData.
-
SPI_RETRY_TIMES
Retry times for waiting flag.
-
LPSPI_MASTER_PCS_SHIFT
LPSPI master PCS shift macro , internal used.
-
LPSPI_MASTER_PCS_MASK
LPSPI master PCS shift macro , internal used.
-
LPSPI_SLAVE_PCS_SHIFT
LPSPI slave PCS shift macro , internal used.
-
LPSPI_SLAVE_PCS_MASK
LPSPI slave PCS shift macro , internal used.
-
struct _lpspi_master_config
- #include <fsl_lpspi.h>
LPSPI master configuration structure.
Public Members
-
uint32_t baudRate
Baud Rate for LPSPI.
-
uint32_t bitsPerFrame
Bits per frame, minimum 8, maximum 4096.
-
lpspi_clock_polarity_t cpol
Clock polarity.
-
lpspi_clock_phase_t cpha
Clock phase.
-
lpspi_shift_direction_t direction
MSB or LSB data shift direction.
-
uint32_t pcsToSckDelayInNanoSec
PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.
-
uint32_t lastSckToPcsDelayInNanoSec
Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.
-
uint32_t betweenTransferDelayInNanoSec
After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.
-
lpspi_which_pcs_t whichPcs
Desired Peripheral Chip Select (PCS).
-
lpspi_pcs_polarity_config_t pcsActiveHighOrLow
Desired PCS active high or low
-
lpspi_pin_config_t pinCfg
Configures which pins are used for input and output data during single bit transfers.
-
lpspi_data_out_config_t dataOutConfig
Configures if the output data is tristated between accesses (LPSPI_PCS is negated).
-
bool enableInputDelay
Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length.
-
uint32_t baudRate
-
struct _lpspi_slave_config
- #include <fsl_lpspi.h>
LPSPI slave configuration structure.
Public Members
-
uint32_t bitsPerFrame
Bits per frame, minimum 8, maximum 4096.
-
lpspi_clock_polarity_t cpol
Clock polarity.
-
lpspi_clock_phase_t cpha
Clock phase.
-
lpspi_shift_direction_t direction
MSB or LSB data shift direction.
-
lpspi_which_pcs_t whichPcs
Desired Peripheral Chip Select (pcs)
-
lpspi_pcs_polarity_config_t pcsActiveHighOrLow
Desired PCS active high or low
-
lpspi_pin_config_t pinCfg
Configures which pins are used for input and output data during single bit transfers.
-
lpspi_data_out_config_t dataOutConfig
Configures if the output data is tristated between accesses (LPSPI_PCS is negated).
-
uint32_t bitsPerFrame
-
struct _lpspi_transfer
- #include <fsl_lpspi.h>
LPSPI master/slave transfer structure.
Public Members
-
const uint8_t *txData
Send buffer.
-
uint8_t *rxData
Receive buffer.
-
volatile size_t dataSize
Transfer bytes.
-
uint32_t configFlags
Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.
-
const uint8_t *txData
-
struct _lpspi_master_handle
- #include <fsl_lpspi.h>
LPSPI master transfer handle structure used for transactional API.
Public Members
-
volatile bool isPcsContinuous
Is PCS continuous in transfer.
-
volatile bool writeTcrInIsr
A flag that whether should write TCR in ISR.
-
volatile bool isByteSwap
A flag that whether should byte swap.
-
volatile bool isTxMask
A flag that whether TCR[TXMSK] is set.
-
volatile uint16_t bytesPerFrame
Number of bytes in each frame
-
volatile uint8_t fifoSize
FIFO dataSize.
-
volatile uint8_t rxWatermark
Rx watermark.
-
volatile uint8_t bytesEachWrite
Bytes for each write TDR.
-
volatile uint8_t bytesEachRead
Bytes for each read RDR.
-
const uint8_t *volatile txData
Send buffer.
-
uint8_t *volatile rxData
Receive buffer.
-
volatile size_t txRemainingByteCount
Number of bytes remaining to send.
-
volatile size_t rxRemainingByteCount
Number of bytes remaining to receive.
-
volatile uint32_t writeRegRemainingTimes
Write TDR register remaining times.
-
volatile uint32_t readRegRemainingTimes
Read RDR register remaining times.
-
uint32_t totalByteCount
Number of transfer bytes
-
uint32_t txBuffIfNull
Used if the txData is NULL.
-
volatile uint8_t state
LPSPI transfer state , _lpspi_transfer_state.
-
lpspi_master_transfer_callback_t callback
Completion callback.
-
void *userData
Callback user data.
-
volatile bool isPcsContinuous
-
struct _lpspi_slave_handle
- #include <fsl_lpspi.h>
LPSPI slave transfer handle structure used for transactional API.
Public Members
-
volatile bool isByteSwap
A flag that whether should byte swap.
-
volatile uint8_t fifoSize
FIFO dataSize.
-
volatile uint8_t rxWatermark
Rx watermark.
-
volatile uint8_t bytesEachWrite
Bytes for each write TDR.
-
volatile uint8_t bytesEachRead
Bytes for each read RDR.
-
const uint8_t *volatile txData
Send buffer.
-
uint8_t *volatile rxData
Receive buffer.
-
volatile size_t txRemainingByteCount
Number of bytes remaining to send.
-
volatile size_t rxRemainingByteCount
Number of bytes remaining to receive.
-
volatile uint32_t writeRegRemainingTimes
Write TDR register remaining times.
-
volatile uint32_t readRegRemainingTimes
Read RDR register remaining times.
-
uint32_t totalByteCount
Number of transfer bytes
-
volatile uint8_t state
LPSPI transfer state , _lpspi_transfer_state.
-
volatile uint32_t errorCount
Error count for slave transfer.
-
lpspi_slave_transfer_callback_t callback
Completion callback.
-
void *userData
Callback user data.
-
volatile bool isByteSwap
LPSPI eDMA Driver
-
FSL_LPSPI_EDMA_DRIVER_VERSION
LPSPI EDMA driver version.
-
DMA_MAX_TRANSFER_COUNT
DMA max transfer size.
-
typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t
Forward declaration of the _lpspi_master_edma_handle typedefs.
-
typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t
Forward declaration of the _lpspi_slave_edma_handle typedefs.
-
typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)
Completion callback function pointer type.
- Param base:
LPSPI peripheral base address.
- Param handle:
Pointer to the handle for the LPSPI master.
- Param status:
Success or error code describing whether the transfer completed.
- Param userData:
Arbitrary pointer-dataSized value passed from the application.
-
typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)
Completion callback function pointer type.
- Param base:
LPSPI peripheral base address.
- Param handle:
Pointer to the handle for the LPSPI slave.
- Param status:
Success or error code describing whether the transfer completed.
- Param userData:
Arbitrary pointer-dataSized value passed from the application.
-
void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)
Initializes the LPSPI master eDMA handle.
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.
- Parameters:
base – LPSPI peripheral base address.
handle – LPSPI handle pointer to lpspi_master_edma_handle_t.
callback – LPSPI callback.
userData – callback function parameter.
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.
-
status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
LPSPI master transfer data using eDMA.
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.
- Returns:
status of status_t.
-
status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)
LPSPI master config transfer parameter while using eDMA.
This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master.
- Return values:
kStatus_Success – Execution successfully.
kStatus_LPSPI_Busy – The LPSPI device is busy.
- Returns:
Indicates whether LPSPI master transfer was successful or not.
-
status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
LPSPI master transfer data using eDMA without configs.
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure, config field is not uesed.
- Return values:
kStatus_Success – Execution successfully.
kStatus_LPSPI_Busy – The LPSPI device is busy.
kStatus_InvalidArgument – The transfer structure is invalid.
- Returns:
Indicates whether LPSPI master transfer was successful or not.
-
void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)
LPSPI master aborts a transfer which is using eDMA.
This function aborts a transfer which is using eDMA.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
-
status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)
Gets the master eDMA transfer remaining bytes.
This function gets the master eDMA transfer remaining bytes.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the EDMA transaction.
- Returns:
status of status_t.
-
void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)
Initializes the LPSPI slave eDMA handle.
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.
(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .
- Parameters:
base – LPSPI peripheral base address.
handle – LPSPI handle pointer to lpspi_slave_edma_handle_t.
callback – LPSPI callback.
userData – callback function parameter.
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.
-
status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)
LPSPI slave transfers data using eDMA.
This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.
- Returns:
status of status_t.
-
void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)
LPSPI slave aborts a transfer which is using eDMA.
This function aborts a transfer which is using eDMA.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
-
status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)
Gets the slave eDMA transfer remaining bytes.
This function gets the slave eDMA transfer remaining bytes.
- Parameters:
base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the eDMA transaction.
- Returns:
status of status_t.
-
struct _lpspi_master_edma_handle
- #include <fsl_lpspi_edma.h>
LPSPI master eDMA transfer handle structure used for transactional API.
Public Members
-
volatile bool isPcsContinuous
Is PCS continuous in transfer.
-
volatile bool isByteSwap
A flag that whether should byte swap.
-
volatile uint8_t fifoSize
FIFO dataSize.
-
volatile uint8_t rxWatermark
Rx watermark.
-
volatile uint8_t bytesEachWrite
Bytes for each write TDR.
-
volatile uint8_t bytesEachRead
Bytes for each read RDR.
-
volatile uint8_t bytesLastRead
Bytes for last read RDR.
-
volatile bool isThereExtraRxBytes
Is there extra RX byte.
-
const uint8_t *volatile txData
Send buffer.
-
uint8_t *volatile rxData
Receive buffer.
-
volatile size_t txRemainingByteCount
Number of bytes remaining to send.
-
volatile size_t rxRemainingByteCount
Number of bytes remaining to receive.
-
volatile uint32_t writeRegRemainingTimes
Write TDR register remaining times.
-
volatile uint32_t readRegRemainingTimes
Read RDR register remaining times.
-
uint32_t totalByteCount
Number of transfer bytes
-
edma_tcd_t *lastTimeTCD
Pointer to the lastTime TCD
-
bool isMultiDMATransmit
Is there multi DMA transmit
-
volatile uint8_t dmaTransmitTime
DMA Transfer times.
-
uint32_t lastTimeDataBytes
DMA transmit last Time data Bytes
-
uint32_t dataBytesEveryTime
Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT
-
edma_transfer_config_t transferConfigRx
Config of DMA rx channel.
-
edma_transfer_config_t transferConfigTx
Config of DMA tx channel.
-
uint32_t txBuffIfNull
Used if there is not txData for DMA purpose.
-
uint32_t rxBuffIfNull
Used if there is not rxData for DMA purpose.
-
uint32_t transmitCommand
Used to write TCR for DMA purpose.
-
volatile uint8_t state
LPSPI transfer state , _lpspi_transfer_state.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
lpspi_master_edma_transfer_callback_t callback
Completion callback.
-
void *userData
Callback user data.
-
edma_handle_t *edmaRxRegToRxDataHandle
edma_handle_t handle point used for RxReg to RxData buff
-
edma_handle_t *edmaTxDataToTxRegHandle
edma_handle_t handle point used for TxData to TxReg buff
-
edma_tcd_t lpspiSoftwareTCD[3]
SoftwareTCD, internal used
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volatile bool isPcsContinuous
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struct _lpspi_slave_edma_handle
- #include <fsl_lpspi_edma.h>
LPSPI slave eDMA transfer handle structure used for transactional API.
Public Members
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volatile bool isByteSwap
A flag that whether should byte swap.
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volatile uint8_t fifoSize
FIFO dataSize.
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volatile uint8_t rxWatermark
Rx watermark.
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volatile uint8_t bytesEachWrite
Bytes for each write TDR.
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volatile uint8_t bytesEachRead
Bytes for each read RDR.
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volatile uint8_t bytesLastRead
Bytes for last read RDR.
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volatile bool isThereExtraRxBytes
Is there extra RX byte.
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uint8_t nbytes
eDMA minor byte transfer count initially configured.
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const uint8_t *volatile txData
Send buffer.
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uint8_t *volatile rxData
Receive buffer.
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volatile size_t txRemainingByteCount
Number of bytes remaining to send.
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volatile size_t rxRemainingByteCount
Number of bytes remaining to receive.
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volatile uint32_t writeRegRemainingTimes
Write TDR register remaining times.
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volatile uint32_t readRegRemainingTimes
Read RDR register remaining times.
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uint32_t totalByteCount
Number of transfer bytes
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uint32_t txBuffIfNull
Used if there is not txData for DMA purpose.
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uint32_t rxBuffIfNull
Used if there is not rxData for DMA purpose.
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volatile uint8_t state
LPSPI transfer state.
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uint32_t errorCount
Error count for slave transfer.
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lpspi_slave_edma_transfer_callback_t callback
Completion callback.
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void *userData
Callback user data.
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edma_handle_t *edmaRxRegToRxDataHandle
edma_handle_t handle point used for RxReg to RxData buff
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edma_handle_t *edmaTxDataToTxRegHandle
edma_handle_t handle point used for TxData to TxReg
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edma_tcd_t lpspiSoftwareTCD[2]
SoftwareTCD, internal used
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volatile bool isByteSwap
LPTMR: Low-Power Timer
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void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)
Ungates the LPTMR clock and configures the peripheral for a basic operation.
Note
This API should be called at the beginning of the application using the LPTMR driver.
- Parameters:
base – LPTMR peripheral base address
config – A pointer to the LPTMR configuration structure.
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void LPTMR_Deinit(LPTMR_Type *base)
Gates the LPTMR clock.
- Parameters:
base – LPTMR peripheral base address
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void LPTMR_GetDefaultConfig(lptmr_config_t *config)
Fills in the LPTMR configuration structure with default settings.
The default values are as follows.
config->timerMode = kLPTMR_TimerModeTimeCounter; config->pinSelect = kLPTMR_PinSelectInput_0; config->pinPolarity = kLPTMR_PinPolarityActiveHigh; config->enableFreeRunning = false; config->bypassPrescaler = true; config->prescalerClockSource = kLPTMR_PrescalerClock_1; config->value = kLPTMR_Prescale_Glitch_0;
- Parameters:
config – A pointer to the LPTMR configuration structure.
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static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
Enables the selected LPTMR interrupts.
- Parameters:
base – LPTMR peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t
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static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
Disables the selected LPTMR interrupts.
- Parameters:
base – LPTMR peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t.
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static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
Gets the enabled LPTMR interrupts.
- Parameters:
base – LPTMR peripheral base address
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lptmr_interrupt_enable_t
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static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
Gets the LPTMR status flags.
- Parameters:
base – LPTMR peripheral base address
- Returns:
The status flags. This is the logical OR of members of the enumeration lptmr_status_flags_t
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static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
Clears the LPTMR status flags.
- Parameters:
base – LPTMR peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration lptmr_status_flags_t.
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static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
Sets the timer period in units of count.
Timers counts from 0 until it equals the count value set here. The count value is written to the CMR register.
Note
The TCF flag is set with the CNR equals the count provided here and then increments.
Call the utility macros provided in the fsl_common.h to convert to ticks.
- Parameters:
base – LPTMR peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.
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static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
Reads the current timer counting value.
This function returns the real-time timer counting value in a range from 0 to a timer period.
Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
- Parameters:
base – LPTMR peripheral base address
- Returns:
The current counter value in ticks
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static inline void LPTMR_StartTimer(LPTMR_Type *base)
Starts the timer.
After calling this function, the timer counts up to the CMR register value. Each time the timer reaches the CMR value and then increments, it generates a trigger pulse and sets the timeout interrupt flag. An interrupt is also triggered if the timer interrupt is enabled.
- Parameters:
base – LPTMR peripheral base address
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static inline void LPTMR_StopTimer(LPTMR_Type *base)
Stops the timer.
This function stops the timer and resets the timer’s counter register.
- Parameters:
base – LPTMR peripheral base address
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FSL_LPTMR_DRIVER_VERSION
Driver Version
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enum _lptmr_pin_select
LPTMR pin selection used in pulse counter mode.
Values:
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enumerator kLPTMR_PinSelectInput_0
Pulse counter input 0 is selected
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enumerator kLPTMR_PinSelectInput_1
Pulse counter input 1 is selected
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enumerator kLPTMR_PinSelectInput_2
Pulse counter input 2 is selected
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enumerator kLPTMR_PinSelectInput_3
Pulse counter input 3 is selected
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enumerator kLPTMR_PinSelectInput_0
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enum _lptmr_pin_polarity
LPTMR pin polarity used in pulse counter mode.
Values:
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enumerator kLPTMR_PinPolarityActiveHigh
Pulse Counter input source is active-high
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enumerator kLPTMR_PinPolarityActiveLow
Pulse Counter input source is active-low
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enumerator kLPTMR_PinPolarityActiveHigh
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enum _lptmr_timer_mode
LPTMR timer mode selection.
Values:
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enumerator kLPTMR_TimerModeTimeCounter
Time Counter mode
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enumerator kLPTMR_TimerModePulseCounter
Pulse Counter mode
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enumerator kLPTMR_TimerModeTimeCounter
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enum _lptmr_prescaler_glitch_value
LPTMR prescaler/glitch filter values.
Values:
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enumerator kLPTMR_Prescale_Glitch_0
Prescaler divide 2, glitch filter does not support this setting
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enumerator kLPTMR_Prescale_Glitch_1
Prescaler divide 4, glitch filter 2
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enumerator kLPTMR_Prescale_Glitch_2
Prescaler divide 8, glitch filter 4
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enumerator kLPTMR_Prescale_Glitch_3
Prescaler divide 16, glitch filter 8
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enumerator kLPTMR_Prescale_Glitch_4
Prescaler divide 32, glitch filter 16
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enumerator kLPTMR_Prescale_Glitch_5
Prescaler divide 64, glitch filter 32
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enumerator kLPTMR_Prescale_Glitch_6
Prescaler divide 128, glitch filter 64
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enumerator kLPTMR_Prescale_Glitch_7
Prescaler divide 256, glitch filter 128
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enumerator kLPTMR_Prescale_Glitch_8
Prescaler divide 512, glitch filter 256
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enumerator kLPTMR_Prescale_Glitch_9
Prescaler divide 1024, glitch filter 512
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enumerator kLPTMR_Prescale_Glitch_10
Prescaler divide 2048 glitch filter 1024
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enumerator kLPTMR_Prescale_Glitch_11
Prescaler divide 4096, glitch filter 2048
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enumerator kLPTMR_Prescale_Glitch_12
Prescaler divide 8192, glitch filter 4096
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enumerator kLPTMR_Prescale_Glitch_13
Prescaler divide 16384, glitch filter 8192
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enumerator kLPTMR_Prescale_Glitch_14
Prescaler divide 32768, glitch filter 16384
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enumerator kLPTMR_Prescale_Glitch_15
Prescaler divide 65536, glitch filter 32768
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enumerator kLPTMR_Prescale_Glitch_0
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enum _lptmr_prescaler_clock_select
LPTMR prescaler/glitch filter clock select.
Note
Clock connections are SoC-specific
Values:
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enum _lptmr_interrupt_enable
List of the LPTMR interrupts.
Values:
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enumerator kLPTMR_TimerInterruptEnable
Timer interrupt enable
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enumerator kLPTMR_TimerInterruptEnable
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enum _lptmr_status_flags
List of the LPTMR status flags.
Values:
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enumerator kLPTMR_TimerCompareFlag
Timer compare flag
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enumerator kLPTMR_TimerCompareFlag
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typedef enum _lptmr_pin_select lptmr_pin_select_t
LPTMR pin selection used in pulse counter mode.
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typedef enum _lptmr_pin_polarity lptmr_pin_polarity_t
LPTMR pin polarity used in pulse counter mode.
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typedef enum _lptmr_timer_mode lptmr_timer_mode_t
LPTMR timer mode selection.
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typedef enum _lptmr_prescaler_glitch_value lptmr_prescaler_glitch_value_t
LPTMR prescaler/glitch filter values.
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typedef enum _lptmr_prescaler_clock_select lptmr_prescaler_clock_select_t
LPTMR prescaler/glitch filter clock select.
Note
Clock connections are SoC-specific
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typedef enum _lptmr_interrupt_enable lptmr_interrupt_enable_t
List of the LPTMR interrupts.
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typedef enum _lptmr_status_flags lptmr_status_flags_t
List of the LPTMR status flags.
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typedef struct _lptmr_config lptmr_config_t
LPTMR config structure.
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash.
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static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)
Enable or disable timer DMA request.
- Parameters:
base – base LPTMR peripheral base address
enable – Switcher of timer DMA feature. “true” means to enable, “false” means to disable.
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struct _lptmr_config
- #include <fsl_lptmr.h>
LPTMR config structure.
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash.
Public Members
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lptmr_timer_mode_t timerMode
Time counter mode or pulse counter mode
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lptmr_pin_select_t pinSelect
LPTMR pulse input pin select; used only in pulse counter mode
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lptmr_pin_polarity_t pinPolarity
LPTMR pulse input pin polarity; used only in pulse counter mode
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bool enableFreeRunning
True: enable free running, counter is reset on overflow False: counter is reset when the compare flag is set
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bool bypassPrescaler
True: bypass prescaler; false: use clock from prescaler
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lptmr_prescaler_clock_select_t prescalerClockSource
LPTMR clock source
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lptmr_prescaler_glitch_value_t value
Prescaler or glitch filter value
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lptmr_timer_mode_t timerMode
LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver
LPUART Driver
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static inline void LPUART_SoftwareReset(LPUART_Type *base)
Resets the LPUART using software.
This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.
- Parameters:
base – LPUART peripheral base address.
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status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
Initializes an LPUART instance with the user configuration structure and the peripheral clock.
This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART.
lpuart_config_t lpuartConfig; lpuartConfig.baudRate_Bps = 115200U; lpuartConfig.parityMode = kLPUART_ParityDisabled; lpuartConfig.dataBitsCount = kLPUART_EightDataBits; lpuartConfig.isMsb = false; lpuartConfig.stopBitCount = kLPUART_OneStopBit; lpuartConfig.txFifoWatermark = 0; lpuartConfig.rxFifoWatermark = 1; LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
- Parameters:
base – LPUART peripheral base address.
config – Pointer to a user-defined configuration structure.
srcClock_Hz – LPUART clock source frequency in HZ.
- Return values:
kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source.
kStatus_Success – LPUART initialize succeed
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void LPUART_Deinit(LPUART_Type *base)
Deinitializes a LPUART instance.
This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
- Parameters:
base – LPUART peripheral base address.
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void LPUART_GetDefaultConfig(lpuart_config_t *config)
Gets the default configuration structure.
This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;
- Parameters:
config – Pointer to a configuration structure.
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status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
Sets the LPUART instance baudrate.
This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
- Parameters:
base – LPUART peripheral base address.
baudRate_Bps – LPUART baudrate to be set.
srcClock_Hz – LPUART clock source frequency in HZ.
- Return values:
kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source.
kStatus_Success – Set baudrate succeeded.
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void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)
Enable 9-bit data mode for LPUART.
This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.
- Parameters:
base – LPUART peripheral base address.
enable – true to enable, flase to disable.
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static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)
Set the LPUART address.
This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.
Note
Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
- Parameters:
base – LPUART peripheral base address.
address1 – LPUART slave address1.
address2 – LPUART slave address2.
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static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)
Enable the LPUART match address feature.
- Parameters:
base – LPUART peripheral base address.
match1 – true to enable match address1, false to disable.
match2 – true to enable match address2, false to disable.
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static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)
Sets the rx FIFO watermark.
- Parameters:
base – LPUART peripheral base address.
water – Rx FIFO watermark.
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static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)
Sets the tx FIFO watermark.
- Parameters:
base – LPUART peripheral base address.
water – Tx FIFO watermark.
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static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)
Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.
This function Enable 16bit Data transmit in lpuart_handle_t.
- Parameters:
handle – LPUART handle pointer.
enable – true to enable, false to disable.
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uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
Gets LPUART status flags.
This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty:
if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) { ... }
- Parameters:
base – LPUART peripheral base address.
- Returns:
LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
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status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
Clears status flags with a provided mask.
This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
- Parameters:
base – LPUART peripheral base address.
mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask.
- Return values:
kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware.
kStatus_Success – Status in the mask are cleared.
- Returns:
0 succeed, others failed.
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void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
Enables LPUART interrupts according to a provided mask.
This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt:
LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
- Parameters:
base – LPUART peripheral base address.
mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable.
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void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
Disables LPUART interrupts according to a provided mask.
This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt:
LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
- Parameters:
base – LPUART peripheral base address.
mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable.
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uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
Gets enabled LPUART interrupts.
This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:
uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) { ... }
- Parameters:
base – LPUART peripheral base address.
- Returns:
LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable.
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static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
Gets the LPUART data register address.
This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
- Parameters:
base – LPUART peripheral base address.
- Returns:
LPUART data register addresses which are used both by the transmitter and receiver.
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static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
Enables or disables the LPUART transmitter DMA request.
This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
- Parameters:
base – LPUART peripheral base address.
enable – True to enable, false to disable.
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static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
Enables or disables the LPUART receiver DMA.
This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
- Parameters:
base – LPUART peripheral base address.
enable – True to enable, false to disable.
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uint32_t LPUART_GetInstance(LPUART_Type *base)
Get the LPUART instance from peripheral base address.
- Parameters:
base – LPUART peripheral base address.
- Returns:
LPUART instance.
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static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
Enables or disables the LPUART transmitter.
This function enables or disables the LPUART transmitter.
- Parameters:
base – LPUART peripheral base address.
enable – True to enable, false to disable.
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static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
Enables or disables the LPUART receiver.
This function enables or disables the LPUART receiver.
- Parameters:
base – LPUART peripheral base address.
enable – True to enable, false to disable.
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static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
Writes to the transmitter register.
This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.
- Parameters:
base – LPUART peripheral base address.
data – Data write to the TX register.
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static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
Reads the receiver register.
This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.
- Parameters:
base – LPUART peripheral base address.
- Returns:
Data read from data register.
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static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)
Gets the rx FIFO data count.
- Parameters:
base – LPUART peripheral base address.
- Returns:
rx FIFO data count.
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static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)
Gets the tx FIFO data count.
- Parameters:
base – LPUART peripheral base address.
- Returns:
tx FIFO data count.
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void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
Transmit an address frame in 9-bit data mode.
- Parameters:
base – LPUART peripheral base address.
address – LPUART slave address.
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status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
Writes to the transmitter register using a blocking method.
This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.
- Parameters:
base – LPUART peripheral base address.
data – Start address of the data to write.
length – Size of the data to write.
- Return values:
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.
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status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
Note
This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.
- Parameters:
base – LPUART peripheral base address.
data – Start address of the data to write.
length – Size of the data to write.
- Return values:
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.
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status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
Reads the receiver data register using a blocking method.
This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.
- Parameters:
base – LPUART peripheral base address.
data – Start address of the buffer to store the received data.
length – Size of the buffer.
- Return values:
kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.
kStatus_LPUART_NoiseError – Noise error happened while receiving data.
kStatus_LPUART_FramingError – Framing error happened while receiving data.
kStatus_LPUART_ParityError – Parity error happened while receiving data.
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.
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status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
Reads the receiver data register in 9bit or 10bit mode.
Note
This function only support 9bit or 10bit transfer.
- Parameters:
base – LPUART peripheral base address.
data – Start address of the buffer to store the received data by 16bit, only 10bit is valid.
length – Size of the buffer.
- Return values:
kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.
kStatus_LPUART_NoiseError – Noise error happened while receiving data.
kStatus_LPUART_FramingError – Framing error happened while receiving data.
kStatus_LPUART_ParityError – Parity error happened while receiving data.
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.
-
void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)
Initializes the LPUART handle.
This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.
The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as
ringBuffer
.- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
callback – Callback function.
userData – User data.
-
status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
Transmits a buffer of data using the interrupt method.
This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.
Note
The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART transfer structure, see lpuart_transfer_t.
- Return values:
kStatus_Success – Successfully start the data transmission.
kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register.
kStatus_InvalidArgument – Invalid argument.
-
void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
Sets up the RX ring buffer.
This function sets up the RX ring buffer to a specific UART handle.
When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.
Note
When using RX ring buffer, one byte is reserved for internal use. In other words, if
ringBufferSize
is 32, then only 31 bytes are used for saving data.- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – size of the ring buffer.
-
void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
Aborts the background transfer and uninstalls the ring buffer.
This function aborts the background transfer and uninstalls the ring buffer.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
-
size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
Get the length of received data in RX ring buffer.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
- Returns:
Length of received data in RX ring buffer.
-
void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
Aborts the interrupt-driven data transmit.
This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
-
status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
Gets the number of bytes that have been sent out to bus.
This function gets the number of bytes that have been sent out to bus by an interrupt method.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Send bytes count.
- Return values:
kStatus_NoTransferInProgress – No send in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter
count
;
-
status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)
Receives a buffer of data using the interrupt method.
This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter
receivedBytes
shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameterreceivedBytes
set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART transfer structure, see uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.
- Return values:
kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_LPUART_RxBusy – Previous receive request is not finished.
kStatus_InvalidArgument – Invalid argument.
-
void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
Aborts the interrupt-driven data receiving.
This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
-
status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
Gets the number of bytes that have been received.
This function gets the number of bytes that have been received.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Receive bytes count.
- Return values:
kStatus_NoTransferInProgress – No receive in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter
count
;
-
void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)
LPUART IRQ handle function.
This function handles the LPUART transmit and receive IRQ request.
- Parameters:
base – LPUART peripheral base address.
irqHandle – LPUART handle pointer.
-
void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)
LPUART Error IRQ handle function.
This function handles the LPUART error IRQ request.
- Parameters:
base – LPUART peripheral base address.
irqHandle – LPUART handle pointer.
-
FSL_LPUART_DRIVER_VERSION
LPUART driver version.
Error codes for the LPUART driver.
Values:
-
enumerator kStatus_LPUART_TxBusy
TX busy
-
enumerator kStatus_LPUART_RxBusy
RX busy
-
enumerator kStatus_LPUART_TxIdle
LPUART transmitter is idle.
-
enumerator kStatus_LPUART_RxIdle
LPUART receiver is idle.
-
enumerator kStatus_LPUART_TxWatermarkTooLarge
TX FIFO watermark too large
-
enumerator kStatus_LPUART_RxWatermarkTooLarge
RX FIFO watermark too large
-
enumerator kStatus_LPUART_FlagCannotClearManually
Some flag can’t manually clear
-
enumerator kStatus_LPUART_Error
Error happens on LPUART.
-
enumerator kStatus_LPUART_RxRingBufferOverrun
LPUART RX software ring buffer overrun.
-
enumerator kStatus_LPUART_RxHardwareOverrun
LPUART RX receiver overrun.
-
enumerator kStatus_LPUART_NoiseError
LPUART noise error.
-
enumerator kStatus_LPUART_FramingError
LPUART framing error.
-
enumerator kStatus_LPUART_ParityError
LPUART parity error.
-
enumerator kStatus_LPUART_BaudrateNotSupport
Baudrate is not support in current clock source
-
enumerator kStatus_LPUART_IdleLineDetected
IDLE flag.
-
enumerator kStatus_LPUART_Timeout
LPUART times out.
-
enumerator kStatus_LPUART_TxBusy
-
enum _lpuart_parity_mode
LPUART parity mode.
Values:
-
enumerator kLPUART_ParityDisabled
Parity disabled
-
enumerator kLPUART_ParityEven
Parity enabled, type even, bit setting: PE|PT = 10
-
enumerator kLPUART_ParityOdd
Parity enabled, type odd, bit setting: PE|PT = 11
-
enumerator kLPUART_ParityDisabled
-
enum _lpuart_data_bits
LPUART data bits count.
Values:
-
enumerator kLPUART_EightDataBits
Eight data bit
-
enumerator kLPUART_SevenDataBits
Seven data bit
-
enumerator kLPUART_EightDataBits
-
enum _lpuart_stop_bit_count
LPUART stop bit count.
Values:
-
enumerator kLPUART_OneStopBit
One stop bit
-
enumerator kLPUART_TwoStopBit
Two stop bits
-
enumerator kLPUART_OneStopBit
-
enum _lpuart_transmit_cts_source
LPUART transmit CTS source.
Values:
-
enumerator kLPUART_CtsSourcePin
CTS resource is the LPUART_CTS pin.
-
enumerator kLPUART_CtsSourceMatchResult
CTS resource is the match result.
-
enumerator kLPUART_CtsSourcePin
-
enum _lpuart_transmit_cts_config
LPUART transmit CTS configure.
Values:
-
enumerator kLPUART_CtsSampleAtStart
CTS input is sampled at the start of each character.
-
enumerator kLPUART_CtsSampleAtIdle
CTS input is sampled when the transmitter is idle
-
enumerator kLPUART_CtsSampleAtStart
-
enum _lpuart_idle_type_select
LPUART idle flag type defines when the receiver starts counting.
Values:
-
enumerator kLPUART_IdleTypeStartBit
Start counting after a valid start bit.
-
enumerator kLPUART_IdleTypeStopBit
Start counting after a stop bit.
-
enumerator kLPUART_IdleTypeStartBit
-
enum _lpuart_idle_config
LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.
Values:
-
enumerator kLPUART_IdleCharacter1
the number of idle characters.
-
enumerator kLPUART_IdleCharacter2
the number of idle characters.
-
enumerator kLPUART_IdleCharacter4
the number of idle characters.
-
enumerator kLPUART_IdleCharacter8
the number of idle characters.
-
enumerator kLPUART_IdleCharacter16
the number of idle characters.
-
enumerator kLPUART_IdleCharacter32
the number of idle characters.
-
enumerator kLPUART_IdleCharacter64
the number of idle characters.
-
enumerator kLPUART_IdleCharacter128
the number of idle characters.
-
enumerator kLPUART_IdleCharacter1
-
enum _lpuart_interrupt_enable
LPUART interrupt configuration structure, default settings all disabled.
This structure contains the settings for all LPUART interrupt configurations.
Values:
-
enumerator kLPUART_LinBreakInterruptEnable
LIN break detect. bit 7
-
enumerator kLPUART_RxActiveEdgeInterruptEnable
Receive Active Edge. bit 6
-
enumerator kLPUART_TxDataRegEmptyInterruptEnable
Transmit data register empty. bit 23
-
enumerator kLPUART_TransmissionCompleteInterruptEnable
Transmission complete. bit 22
-
enumerator kLPUART_RxDataRegFullInterruptEnable
Receiver data register full. bit 21
-
enumerator kLPUART_IdleLineInterruptEnable
Idle line. bit 20
-
enumerator kLPUART_RxOverrunInterruptEnable
Receiver Overrun. bit 27
-
enumerator kLPUART_NoiseErrorInterruptEnable
Noise error flag. bit 26
-
enumerator kLPUART_FramingErrorInterruptEnable
Framing error flag. bit 25
-
enumerator kLPUART_ParityErrorInterruptEnable
Parity error flag. bit 24
-
enumerator kLPUART_Match1InterruptEnable
Parity error flag. bit 15
-
enumerator kLPUART_Match2InterruptEnable
Parity error flag. bit 14
-
enumerator kLPUART_TxFifoOverflowInterruptEnable
Transmit FIFO Overflow. bit 9
-
enumerator kLPUART_RxFifoUnderflowInterruptEnable
Receive FIFO Underflow. bit 8
-
enumerator kLPUART_AllInterruptEnable
-
enumerator kLPUART_LinBreakInterruptEnable
-
enum _lpuart_flags
LPUART status flags.
This provides constants for the LPUART status flags for use in the LPUART functions.
Values:
-
enumerator kLPUART_TxDataRegEmptyFlag
Transmit data register empty flag, sets when transmit buffer is empty. bit 23
-
enumerator kLPUART_TransmissionCompleteFlag
Transmission complete flag, sets when transmission activity complete. bit 22
-
enumerator kLPUART_RxDataRegFullFlag
Receive data register full flag, sets when the receive data buffer is full. bit 21
-
enumerator kLPUART_IdleLineFlag
Idle line detect flag, sets when idle line detected. bit 20
-
enumerator kLPUART_RxOverrunFlag
Receive Overrun, sets when new data is received before data is read from receive register. bit 19
-
enumerator kLPUART_NoiseErrorFlag
Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18
-
enumerator kLPUART_FramingErrorFlag
Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17
-
enumerator kLPUART_ParityErrorFlag
If parity enabled, sets upon parity error detection. bit 16
-
enumerator kLPUART_LinBreakFlag
LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31
-
enumerator kLPUART_RxActiveEdgeFlag
Receive pin active edge interrupt flag, sets when active edge detected. bit 30
-
enumerator kLPUART_RxActiveFlag
Receiver Active Flag (RAF), sets at beginning of valid start. bit 24
-
enumerator kLPUART_DataMatch1Flag
The next character to be read from LPUART_DATA matches MA1. bit 15
-
enumerator kLPUART_DataMatch2Flag
The next character to be read from LPUART_DATA matches MA2. bit 14
-
enumerator kLPUART_TxFifoEmptyFlag
TXEMPT bit, sets if transmit buffer is empty. bit 7
-
enumerator kLPUART_RxFifoEmptyFlag
RXEMPT bit, sets if receive buffer is empty. bit 6
-
enumerator kLPUART_TxFifoOverflowFlag
TXOF bit, sets if transmit buffer overflow occurred. bit 1
-
enumerator kLPUART_RxFifoUnderflowFlag
RXUF bit, sets if receive buffer underflow occurred. bit 0
-
enumerator kLPUART_AllClearFlags
-
enumerator kLPUART_AllFlags
-
enumerator kLPUART_TxDataRegEmptyFlag
-
typedef enum _lpuart_parity_mode lpuart_parity_mode_t
LPUART parity mode.
-
typedef enum _lpuart_data_bits lpuart_data_bits_t
LPUART data bits count.
-
typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t
LPUART stop bit count.
-
typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t
LPUART transmit CTS source.
-
typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t
LPUART transmit CTS configure.
-
typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t
LPUART idle flag type defines when the receiver starts counting.
-
typedef enum _lpuart_idle_config lpuart_idle_config_t
LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.
-
typedef struct _lpuart_config lpuart_config_t
LPUART configuration structure.
-
typedef struct _lpuart_transfer lpuart_transfer_t
LPUART transfer structure.
-
typedef struct _lpuart_handle lpuart_handle_t
-
typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)
LPUART transfer callback function.
-
typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)
-
void *s_lpuartHandle[]
-
const IRQn_Type s_lpuartTxIRQ[]
-
lpuart_isr_t s_lpuartIsr[]
-
UART_RETRY_TIMES
Retry times for waiting flag.
-
struct _lpuart_config
- #include <fsl_lpuart.h>
LPUART configuration structure.
Public Members
-
uint32_t baudRate_Bps
LPUART baud rate
-
lpuart_parity_mode_t parityMode
Parity mode, disabled (default), even, odd
-
lpuart_data_bits_t dataBitsCount
Data bits count, eight (default), seven
-
bool isMsb
Data bits order, LSB (default), MSB
-
lpuart_stop_bit_count_t stopBitCount
Number of stop bits, 1 stop bit (default) or 2 stop bits
-
uint8_t txFifoWatermark
TX FIFO watermark
-
uint8_t rxFifoWatermark
RX FIFO watermark
-
bool enableRxRTS
RX RTS enable
-
bool enableTxCTS
TX CTS enable
-
lpuart_transmit_cts_source_t txCtsSource
TX CTS source
-
lpuart_transmit_cts_config_t txCtsConfig
TX CTS configure
-
lpuart_idle_type_select_t rxIdleType
RX IDLE type.
-
lpuart_idle_config_t rxIdleConfig
RX IDLE configuration.
-
bool enableTx
Enable TX
-
bool enableRx
Enable RX
-
uint32_t baudRate_Bps
-
struct _lpuart_transfer
- #include <fsl_lpuart.h>
LPUART transfer structure.
Public Members
-
size_t dataSize
The byte count to be transfer.
-
size_t dataSize
-
struct _lpuart_handle
- #include <fsl_lpuart.h>
LPUART handle structure.
Public Members
-
volatile size_t txDataSize
Size of the remaining data to send.
-
size_t txDataSizeAll
Size of the data to send out.
-
volatile size_t rxDataSize
Size of the remaining data to receive.
-
size_t rxDataSizeAll
Size of the data to receive.
-
size_t rxRingBufferSize
Size of the ring buffer.
-
volatile uint16_t rxRingBufferHead
Index for the driver to store received data into ring buffer.
-
volatile uint16_t rxRingBufferTail
Index for the user to get data from the ring buffer.
-
lpuart_transfer_callback_t callback
Callback function.
-
void *userData
LPUART callback function parameter.
-
volatile uint8_t txState
TX transfer state.
-
volatile uint8_t rxState
RX transfer state.
-
bool isSevenDataBits
Seven data bits flag.
-
bool is16bitData
16bit data bits flag, only used for 9bit or 10bit data
-
volatile size_t txDataSize
-
union __unnamed86__
Public Members
-
uint8_t *data
The buffer of data to be transfer.
-
uint8_t *rxData
The buffer to receive data.
-
uint16_t *rxData16
The buffer to receive data.
-
const uint8_t *txData
The buffer of data to be sent.
-
const uint16_t *txData16
The buffer of data to be sent.
-
uint8_t *data
-
union __unnamed88__
Public Members
-
const uint8_t *volatile txData
Address of remaining data to send.
-
const uint16_t *volatile txData16
Address of remaining data to send.
-
const uint8_t *volatile txData
-
union __unnamed90__
Public Members
-
uint8_t *volatile rxData
Address of remaining data to receive.
-
uint16_t *volatile rxData16
Address of remaining data to receive.
-
uint8_t *volatile rxData
-
union __unnamed92__
Public Members
-
uint8_t *rxRingBuffer
Start address of the receiver ring buffer.
-
uint16_t *rxRingBuffer16
Start address of the receiver ring buffer.
-
uint8_t *rxRingBuffer
LPUART eDMA Driver
-
void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)
Initializes the LPUART handle which is used in transactional functions.
Note
This function disables all LPUART interrupts.
- Parameters:
base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
callback – Callback function.
userData – User data.
txEdmaHandle – User requested DMA handle for TX DMA transfer.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.
-
status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
Sends data using eDMA.
This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART eDMA transfer structure. See lpuart_transfer_t.
- Return values:
kStatus_Success – if succeed, others failed.
kStatus_LPUART_TxBusy – Previous transfer on going.
kStatus_InvalidArgument – Invalid argument.
-
status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
Receives data using eDMA.
This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.
- Parameters:
base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
xfer – LPUART eDMA transfer structure, see lpuart_transfer_t.
- Return values:
kStatus_Success – if succeed, others fail.
kStatus_LPUART_RxBusy – Previous transfer ongoing.
kStatus_InvalidArgument – Invalid argument.
-
void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
Aborts the sent data using eDMA.
This function aborts the sent data using eDMA.
- Parameters:
base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
-
void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
Aborts the received data using eDMA.
This function aborts the received data using eDMA.
- Parameters:
base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
-
status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
Gets the number of bytes written to the LPUART TX register.
This function gets the number of bytes written to the LPUART TX register by DMA.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Send bytes count.
- Return values:
kStatus_NoTransferInProgress – No send in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter
count
;
-
status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
Gets the number of received bytes.
This function gets the number of received bytes.
- Parameters:
base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Receive bytes count.
- Return values:
kStatus_NoTransferInProgress – No receive in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter
count
;
-
void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)
LPUART eDMA IRQ handle function.
This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application.
Note
This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.
- Parameters:
base – LPUART peripheral base address.
lpuartEdmaHandle – LPUART handle pointer.
-
FSL_LPUART_EDMA_DRIVER_VERSION
LPUART EDMA driver version.
-
typedef struct _lpuart_edma_handle lpuart_edma_handle_t
-
typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)
LPUART transfer callback function.
-
struct _lpuart_edma_handle
- #include <fsl_lpuart_edma.h>
LPUART eDMA handle.
Public Members
-
lpuart_edma_transfer_callback_t callback
Callback function.
-
void *userData
LPUART callback function parameter.
-
size_t rxDataSizeAll
Size of the data to receive.
-
size_t txDataSizeAll
Size of the data to send out.
-
edma_handle_t *txEdmaHandle
The eDMA TX channel used.
-
edma_handle_t *rxEdmaHandle
The eDMA RX channel used.
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
volatile uint8_t txState
TX transfer state.
-
volatile uint8_t rxState
RX transfer state
-
lpuart_edma_transfer_callback_t callback
MECC: internal error correction code
-
void MECC_Init(MECC_Type *base, mecc_config_t *config)
MECC module initialization function.
- Parameters:
base – MECC base address.
config – pointer to the MECC configuration structure.
-
void MECC_Deinit(MECC_Type *base)
Deinitializes the MECC.
- Parameters:
base – MECC base address.
-
void MECC_GetDefaultConfig(mecc_config_t *config)
Sets the MECC configuration structure to default values.
- Parameters:
config – pointer to the MECC configuration structure.
-
static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)
Gets MECC status flags.
- Parameters:
base – MECC peripheral base address.
- Returns:
MECC status flags.
-
static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)
MECC module clear interrupt status.
- Parameters:
base – MECC base address.
mask – status to clear.
-
static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)
MECC module enable interrupt status.
- Parameters:
base – MECC base address.
mask – status to enable.
-
static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)
MECC module disable interrupt status.
- Parameters:
base – MECC base address.
mask – status to disable.
-
static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)
MECC module enable interrupt.
- Parameters:
base – MECC base address.
mask – The interrupts to enable.
-
static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)
MECC module disable interrupt.
- Parameters:
base – MECC base address.
mask – The interrupts to disable.
-
status_t MECC_ErrorInjection(MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)
MECC module error injection.
Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..
- Parameters:
base – MECC base address.
lowerrordata – low 32 bits data.
higherrordata – high 32 bits data.
eccdata – ecc code.
banknumber – ocram bank number.
- Return values:
kStatus_Success. –
-
status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber)
MECC module get single error information.
Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..
- Parameters:
base – MECC base address.
info – single error information.
banknumber – ocram bank number.
- Return values:
kStatus_Success. –
kStatus_MECC_BankMiss. –
-
status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber)
MECC module get multiple error information.
Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..
- Parameters:
base – MECC base address.
info – multiple error information.
banknumber – ocram bank number.
- Return values:
kStatus_Success. –
kStatus_MECC_BankMiss. –
-
static inline uint32_t MECC_GetPendingFlags(MECC_Type *base)
Get pending flags for OCRAM wait and pipeline enable.
- Parameters:
base – MECC base address.
- Returns:
Pending flags, should be the OR’ed value of mecc_pending_flag_t.
-
FSL_MECC_DRIVER_VERSION
Driver version 2.1.0.
Error codes for the MECC driver.
Values:
-
enumerator kStatus_MECC_BankMiss
Ocram bank miss
-
enumerator kStatus_MECC_BankMiss
MECC interrupt configuration structure, default settings all disabled.
This structure contains the settings for all of the MECC interrupt configurations.
Values:
-
enumerator kMECC_SingleError0InterruptEnable
Single Bit Error On Ocram Bank0 interrupt enable.
-
enumerator kMECC_SingleError1InterruptEnable
Single Bit Error On Ocram Bank1 interrupt enable
-
enumerator kMECC_SingleError2InterruptEnable
Single Bit Error On Ocram Bank2 interrupt enable
-
enumerator kMECC_SingleError3InterruptEnable
Single Bit Error On Ocram Bank3 interrupt enable
-
enumerator kMECC_MultiError0InterruptEnable
Multiple Bits Error On Ocram Bank0 interrupt enable
-
enumerator kMECC_MultiError1InterruptEnable
Multiple Bits Error On Ocram Bank1 interrupt enable
-
enumerator kMECC_MultiError2InterruptEnable
Multiple Bits Error On Ocram Bank2 interrupt enable
-
enumerator kMECC_MultiError3InterruptEnable
Multiple Bits Error On Ocram Bank3 interrupt enable
-
enumerator kMECC_StrobeError0InterruptEnable
AXI Strobe Error On Ocram Bank0 interrupt enable
-
enumerator kMECC_StrobeError1InterruptEnable
AXI Strobe Error On Ocram Bank1 interrupt enable
-
enumerator kMECC_StrobeError2InterruptEnable
AXI Strobe Error On Ocram Bank2 interrupt enable
-
enumerator kMECC_StrobeError3InterruptEnable
AXI Strobe Error On Ocram Bank3 interrupt enable
-
enumerator kMECC_AccessError0InterruptEnable
Ocram Access Error On Bank0 interrupt enable
-
enumerator kMECC_AccessError1InterruptEnable
Ocram Access Error On Bank1 interrupt enable
-
enumerator kMECC_AccessError2InterruptEnable
Ocram Access Error On Bank2 interrupt enable
-
enumerator kMECC_AccessError3InterruptEnable
Ocram Access Error On Bank3 interrupt enable
-
enumerator kMECC_AllInterruptsEnable
all interrupts enable
-
enumerator kMECC_SingleError0InterruptEnable
MECC interrupt status configuration structure, default settings all disabled.
This structure contains the settings for all of the MECC interrupt status configurations.
Values:
-
enumerator kMECC_SingleError0InterruptStatusEnable
Single Bit Error On Ocram Bank0 interrupt status enable.
-
enumerator kMECC_SingleError1InterruptStatusEnable
Single Bit Error On Ocram Bank1 interrupt status enable
-
enumerator kMECC_SingleError2InterruptStatusEnable
Single Bit Error On Ocram Bank2 interrupt status enable
-
enumerator kMECC_SingleError3InterruptStatusEnable
Single Bit Error On Ocram Bank3 interrupt status enable
-
enumerator kMECC_MultiError0InterruptStatusEnable
Multiple Bits Error On Ocram Bank0 interrupt status enable
-
enumerator kMECC_MultiError1InterruptStatusEnable
Multiple Bits Error On Ocram Bank1 interrupt status enable
-
enumerator kMECC_MultiError2InterruptStatusEnable
Multiple Bits Error On Ocram Bank2 interrupt status enable
-
enumerator kMECC_MultiError3InterruptStatusEnable
Multiple Bits Error On Ocram Bank3 interrupt status enable
-
enumerator kMECC_StrobeError0InterruptStatusEnable
AXI Strobe Error On Ocram Bank0 interrupt status enable
-
enumerator kMECC_StrobeError1InterruptStatusEnable
AXI Strobe Error On Ocram Bank1 interrupt status enable
-
enumerator kMECC_StrobeError2InterruptStatusEnable
AXI Strobe Error On Ocram Bank2 interrupt status enable
-
enumerator kMECC_StrobeError3InterruptStatusEnable
AXI Strobe Error On Ocram Bank3 interrupt status enable
-
enumerator kMECC_AccessError0InterruptStatusEnable
Ocram Access Error On Bank0 interrupt status enable
-
enumerator kMECC_AccessError1InterruptStatusEnable
Ocram Access Error On Bank1 interrupt status enable
-
enumerator kMECC_AccessError2InterruptStatusEnable
Ocram Access Error On Bank2 interrupt status enable
-
enumerator kMECC_AccessError3InterruptStatusEnable
Ocram Access Error On Bank3 interrupt status enable
-
enumerator kMECC_AllInterruptsStatusEnable
all interrupts enable
-
enumerator kMECC_SingleError0InterruptStatusEnable
MECC status flags.
This provides constants for the MECC status flags for use in the MECC functions.
Values:
-
enumerator kMECC_SingleError0InterruptFlag
Single Bit Error On Ocram Bank0 interrupt flag
-
enumerator kMECC_SingleError1InterruptFlag
Single Bit Error On Ocram Bank1 interrupt flag
-
enumerator kMECC_SingleError2InterruptFlag
Single Bit Error On Ocram Bank2 interrupt flag
-
enumerator kMECC_SingleError3InterruptFlag
Single Bit Error On Ocram Bank3 interrupt flag
-
enumerator kMECC_MultiError0InterruptFlag
Multiple Bits Error On Ocram Bank0 interrupt flag
-
enumerator kMECC_MultiError1InterruptFlag
Multiple Bits Error On Ocram Bank1 interrupt flag
-
enumerator kMECC_MultiError2InterruptFlag
Multiple Bits Error On Ocram Bank2 interrupt flag
-
enumerator kMECC_MultiError3InterruptFlag
Multiple Bits Error On Ocram Bank3 interrupt flag
-
enumerator kMECC_StrobeError0InterruptFlag
AXI Strobe Error On Ocram Bank0 interrupt flag
-
enumerator kMECC_StrobeError1InterruptFlag
AXI Strobe Error On Ocram Bank1 interrupt flag
-
enumerator kMECC_StrobeError2InterruptFlag
AXI Strobe Error On Ocram Bank2 interrupt flag
-
enumerator kMECC_StrobeError3InterruptFlag
AXI Strobe Error On Ocram Bank3 interrupt flag
-
enumerator kMECC_AccessError0InterruptFlag
Ocram Access Error On Bank0 interrupt flag
-
enumerator kMECC_AccessError1InterruptFlag
Ocram Access Error On Bank1 interrupt flag
-
enumerator kMECC_AccessError2InterruptFlag
Ocram Access Error On Bank2 interrupt flag
-
enumerator kMECC_AccessError3InterruptFlag
Ocram Access Error On Bank3 interrupt flag
-
enumerator kMECC_AllInterruptsFlag
all interrupts interrupt flag
-
enumerator kMECC_SingleError0InterruptFlag
MECC ocram bank number.
Values:
-
enumerator kMECC_OcramBank0
ocram bank number 0: ocram_base_address+0x20*i
-
enumerator kMECC_OcramBank1
ocram bank number 1: ocram_base_address+0x20*i+0x8
-
enumerator kMECC_OcramBank2
ocram bank number 2: ocram_base_address+0x20*i+0x10
-
enumerator kMECC_OcramBank3
ocram bank number 3: ocram_base_address+0x20*i+0x18
-
enumerator kMECC_OcramBank0
-
enum _mecc_pending_flag
Pending flags for OCRAM wait and pipeline enable. .
Values:
-
enumerator kMECC_ReadDataWaitPendingFlag
Indicate an update pending status for read data wait.
-
enumerator kMECC_ReadAddrPipelinePendingFlag
Indicate an update pending status for read address pipeline.
-
enumerator kMECC_WriteDataPipelinePendingFlag
Indicate an update pending status for write data pipeline.
-
enumerator kMECC_WriteAddrPipelinePendingFlag
Indicate an update pending status for write address pipeline.
-
enumerator kMECC_AllPendingFlags
Indicate all pending status flags.
-
enumerator kMECC_ReadDataWaitPendingFlag
-
typedef struct _mecc_config mecc_config_t
MECC user configuration.
Note
Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.
-
typedef struct _mecc_single_error_info mecc_single_error_info_t
MECC ocram single error information, including single error address, ECC code, error data and error bit position.
-
typedef struct _mecc_multi_error_info mecc_multi_error_info_t
MECC ocram multiple error information, including multiple error address, ECC code, error data.
-
struct _mecc_config
- #include <fsl_mecc.h>
MECC user configuration.
Note
Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.
Public Members
-
bool enableMecc
Enable the MECC function.
-
uint32_t startAddress
Start address of corresponding OCRAM memory region to enable ECC.
-
uint32_t endAddress
end address of corresponding OCRAM memory region to enable ECC.
-
bool enableReadDataWait
uint32_t Ocram1StartAddress; Ocram 1 start address, deprecated since 2.1.0
uint32_t Ocram1EndAddress; Ocram 1 end address, deprecated since 2.1.0
uint32_t Ocram2StartAddress; Ocram 2 start address, deprecated since 2.1.0.
uint32_t Ocram2EndAddress; Ocram 2 end address, deprecated since 2.1.0 If enabled, 1-cycle wait state will be inserted into each read access:
true Enable read data wait;
false Disable read data wait.
-
bool enableReadAddrPipeline
If enabled, the read address will be registered before can be applied to memory cell:
true Enable Read address pipeline;
false Disable Read address pipeline.
-
bool enableWriteDataPipeline
If enabled, the write data will be registered before can be applied to memory cell:
true Enable write data pipeline;
false Disable write data pipeline.
-
bool enableWriteAddrPipeline
If enabled, write address will be registered before can be applied to memory cell:
true Enable write address pipeline;
false Disable write address pipeline.
-
bool enableMecc
-
struct _mecc_single_error_info
- #include <fsl_mecc.h>
MECC ocram single error information, including single error address, ECC code, error data and error bit position.
Public Members
-
uint32_t singleErrorAddress
Single error address on Ocram bank n
-
uint32_t singleErrorDataLow
Single error low 32 bits uncorrected read data on Ocram bank n
-
uint32_t singleErrorDataHigh
Single error high 32 bits uncorrected read data on Ocram bank n
-
uint32_t singleErrorPosLow
Single error bit postion of low 32 bits read data on Ocram bank n
-
uint32_t singleErrorPosHigh
Single error bit postion of high 32 bits read data on Ocram bank n
-
uint8_t singleErrorEccCode
Single error ECC code on Ocram bank n
-
uint32_t singleErrorAddress
-
struct _mecc_multi_error_info
- #include <fsl_mecc.h>
MECC ocram multiple error information, including multiple error address, ECC code, error data.
Public Members
-
uint32_t multiErrorAddress
Multiple error address on Ocram bank n
-
uint32_t multiErrorDataLow
Multiple error low 32 bits read data on Ocram bank n
-
uint32_t multiErrorDataHigh
Multiple error high 32 bits read data on Ocram bank n
-
uint8_t multiErrorEccCode
Multiple error ECC code on Ocram bank n
-
uint32_t multiErrorAddress
MSGINTR: Message Unit
MSGINTR Driver
MU: Messaging Unit
-
uint32_t MU_GetInstance(MU_Type *base)
Get the MU instance index.
- Parameters:
base – MU peripheral base address.
- Returns:
MU instance index.
-
void MU_Init(MU_Type *base)
Initializes the MU module.
This function enables the MU clock only.
- Parameters:
base – MU peripheral base address.
-
void MU_Deinit(MU_Type *base)
De-initializes the MU module.
This function disables the MU clock only.
- Parameters:
base – MU peripheral base address.
-
static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)
Writes a message to the TX register.
This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.
while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty. MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL); Write message to the TX0 register.
- Parameters:
base – MU peripheral base address.
regIndex – TX register index, see mu_msg_reg_index_t.
msg – Message to send.
-
void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)
Blocks to send a message.
This function waits until the TX register is empty and sends the message.
- Parameters:
base – MU peripheral base address.
regIndex – MU message register, see mu_msg_reg_index_t.
msg – Message to send.
-
static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)
Reads a message from the RX register.
This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.
uint32_t msg; while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base))) { } Wait for the RX0 register full. msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0); Read message from RX0 register.
- Parameters:
base – MU peripheral base address.
regIndex – RX register index, see mu_msg_reg_index_t.
- Returns:
The received message.
-
uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)
Blocks to receive a message.
This function waits until the RX register is full and receives the message.
- Parameters:
base – MU peripheral base address.
regIndex – MU message register, see mu_msg_reg_index_t
- Returns:
The received message.
-
static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)
Sets the 3-bit MU flags reflect on the other MU side.
This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag
kMU_FlagsUpdatingFlag
asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flagkMU_FlagsUpdatingFlag
is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flagkMU_FlagsUpdatingFlag
is cleared before calling this function.while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base)) { } Wait for previous MU flags updating. MU_SetFlagsNonBlocking(base, 0U); Set the mU flags.
- Parameters:
base – MU peripheral base address.
flags – The 3-bit MU flags to set.
-
void MU_SetFlags(MU_Type *base, uint32_t flags)
Blocks setting the 3-bit MU flags reflect on the other MU side.
This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag
kMU_FlagsUpdatingFlag
asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flagkMU_FlagsUpdatingFlag
is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flagkMU_FlagsUpdatingFlag
cleared and sets the 3-bit MU flags.- Parameters:
base – MU peripheral base address.
flags – The 3-bit MU flags to set.
-
static inline uint32_t MU_GetFlags(MU_Type *base)
Gets the current value of the 3-bit MU flags set by the other side.
This function gets the current 3-bit MU flags on the current side.
- Parameters:
base – MU peripheral base address.
- Returns:
flags Current value of the 3-bit flags.
-
uint32_t MU_GetStatusFlags(MU_Type *base)
Gets the MU status flags.
This function returns the bit mask of the MU status flags. See _mu_status_flags.
uint32_t flags; flags = MU_GetStatusFlags(base); Get all status flags. if (kMU_Tx0EmptyFlag & flags) { The TX0 register is empty. Message can be sent. MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL); } if (kMU_Tx1EmptyFlag & flags) { The TX1 register is empty. Message can be sent. MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL); }
If there are more than 4 general purpose interrupts, use MU_GetGeneralPurposeStatusFlags.
- Parameters:
base – MU peripheral base address.
- Returns:
Bit mask of the MU status flags, see _mu_status_flags.
-
static inline uint32_t MU_GetInterruptsPending(MU_Type *base)
Gets the MU IRQ pending status of enabled interrupts.
This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag
- Parameters:
base – MU peripheral base address.
- Returns:
Bit mask of the MU IRQs pending.
-
static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)
Clears the specific MU status flags.
This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.
Clear general interrupt 0 and general interrupt 1 pending flags. MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);
If there are more than 4 general purpose interrupts, use MU_ClearGeneralPurposeStatusFlags.
- Parameters:
base – MU peripheral base address.
flags – Bit mask of the MU status flags. See _mu_status_flags. Only the following flags can be cleared by software, other flags are cleared by hardware:
kMU_GenInt0Flag
kMU_GenInt1Flag
kMU_GenInt2Flag
kMU_GenInt3Flag
kMU_MuResetInterruptFlag
#kMU_OtherSideEnterRunInterruptFlag
#kMU_OtherSideEnterHaltInterruptFlag
#kMU_OtherSideEnterWaitInterruptFlag
#kMU_OtherSideEnterStopInterruptFlag
#kMU_OtherSideEnterPowerDownInterruptFlag
#kMU_ResetAssertInterruptFlag
#kMU_HardwareResetInterruptFlag
-
static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)
Enables the specific MU interrupts.
This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.
Enable general interrupt 0 and TX0 empty interrupt. MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
If there are more than 4 general purpose interrupts, use MU_EnableGeneralPurposeInterrupts.
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.
-
static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)
Disables the specific MU interrupts.
This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.
Disable general interrupt 0 and TX0 empty interrupt. MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
If there are more than 4 general purpose interrupts, use MU_DisableGeneralPurposeInterrupts.
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.
-
status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts)
Triggers interrupts to the other core.
This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) { Previous general purpose interrupt 0 or general purpose interrupt 2 has not been processed by the other core. }
If there are more than 4 general purpose interrupts, use MU_TriggerGeneralPurposeInterrupts.
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.
- Return values:
kStatus_Success – Interrupts have been triggered successfully.
kStatus_Fail – Previous interrupts have not been accepted.
-
static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)
Enables the MU general purpose interrupts.
This function enables the MU general purpose interrupts. The interrupts to enable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_EnableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to enable general purpose interrupt 0 and 3, use like this:
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the MU general purpose interrupts, see mu_general_purpose_interrupt_t.
-
static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)
Disables the MU general purpose interrupts.
This function disables the MU general purpose interrupts. The interrupts to disable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_DisableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to disable general purpose interrupt 0 and 3, use like this:
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the MU general purpose interrupts. see mu_general_purpose_interrupt_t.
-
static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)
Gets the MU general purpose interrupt status flags.
This function returns the bit mask of the MU general purpose interrupt status flags. MU_GetStatusFlags can only get general purpose interrupt status 0~3, this function can get all general purpose interrupts status.
This example shows to check whether general purpose interrupt 0 and 3 happened.
uint32_t flags; flags = MU_GetGeneralPurposeStatusFlags(base); if (kMU_GeneralPurposeInterrupt0 & flags) { } if (kMU_GeneralPurposeInterrupt3 & flags) { }
- Parameters:
base – MU peripheral base address.
- Returns:
Bit mask of the MU general purpose interrupt status flags.
-
static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)
Clear the MU general purpose interrupt status flags.
This function clears the specific MU general purpose interrupt status flags. The flags to clear should be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.
Example to clear general purpose interrupt 0 and general interrupt 1 pending flags.
MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);
- Parameters:
base – MU peripheral base address.
flags – Bit mask of the MU general purpose interrupt status flags. See mu_general_purpose_interrupt_t.
-
static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)
Return the RX status flags in reverse numerical order.
This function return the RX status flags in reverse order. Note: RFn bits of SR[3-0](mu status register) are mapped in ascending numerical order: RF0 -> SR[0] RF1 -> SR[1] RF2 -> SR[2] RF3 -> SR[3] This function will return these bits in reverse numerical order(RF3->RF1) to comply with MU_GetRxStatusFlags() of mu driver. See MU_GetRxStatusFlags() from drivers/mu/fsl_mu.h
status_reg = MU_GetRxStatusFlags(base);
- Parameters:
base – MU peripheral base address.
- Returns:
MU RX status flags in reverse order
-
status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)
Triggers general purpose interrupts to the other core.
This function triggers the specific general purpose interrupts to the other core. The interrupts to trigger are passed in as bit mask. See mu_general_purpose_interrupt_t. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
status_t status; status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2); if (kStatus_Success != status) { Previous general purpose interrupt 0 or general purpose interrupt 2 has not been processed by the other core. }
- Parameters:
base – MU peripheral base address.
interrupts – Bit mask of the interrupts to trigger. See mu_general_purpose_interrupt_t.
- Return values:
kStatus_Success – Interrupts have been triggered successfully.
kStatus_Fail – Previous interrupts have not been accepted.
-
void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)
Boots the other core.
This function boots the other core with a boot configuration.
- Parameters:
base – MU peripheral base address.
mode – The other core boot mode.
-
void MU_HoldOtherCoreReset(MU_Type *base)
Holds the other core reset.
This function causes the other core to be held in reset following any reset event.
- Parameters:
base – MU peripheral base address.
-
static inline void MU_ResetBothSides(MU_Type *base)
Resets the MU for both A side and B side.
This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.
- Parameters:
base – MU peripheral base address.
-
void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)
Hardware reset the other core.
This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.
Example 1: Reset the other core, and no hold reset
In this example, the core at MU side B will reset with the specified boot mode.MU_HardwareResetOtherCore(MU_A, true, false, bootMode);
Example 2: Reset the other core and hold it, then boot the other core later.
Here the other core enters reset, and the reset is hold MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); Current core boot the other core when necessary. MU_BootOtherCore(MU_A, bootMode);
Note
The feature waitReset, holdReset, and bootMode might be not supported for some platforms. waitReset is only available for platforms that FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not defined as 0.
- Parameters:
base – MU peripheral base address.
waitReset – Wait the other core enters reset. Only work when there is CSSR0[RAIP]
true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked.
false: Don’t wait the reset.
holdReset – Hold the other core reset or not. Only work when there is CCR0[RSTH]
true: Hold the other core in reset, this function returns directly when the other core enters reset.
false: Don’t hold the other core in reset, this function waits until the other core out of reset.
bootMode – Boot mode of the other core, if
holdReset
is true, this parameter is useless.
-
FSL_MU_DRIVER_VERSION
MU driver version.
-
enum _mu_status_flags
MU status flags.
Values:
-
enumerator kMU_Tx0EmptyFlag
TX0 empty.
-
enumerator kMU_Tx1EmptyFlag
TX1 empty.
-
enumerator kMU_Tx2EmptyFlag
TX2 empty.
-
enumerator kMU_Tx3EmptyFlag
TX3 empty.
-
enumerator kMU_Rx0FullFlag
RX0 full.
-
enumerator kMU_Rx1FullFlag
RX1 full.
-
enumerator kMU_Rx2FullFlag
RX2 full.
-
enumerator kMU_Rx3FullFlag
RX3 full.
-
enumerator kMU_GenInt0Flag
General purpose interrupt 0 pending.
-
enumerator kMU_GenInt1Flag
General purpose interrupt 1 pending.
-
enumerator kMU_GenInt2Flag
General purpose interrupt 2 pending.
-
enumerator kMU_GenInt3Flag
General purpose interrupt 3 pending.
-
enumerator kMU_RxFullPendingFlag
Any RX full flag is pending.
-
enumerator kMU_TxEmptyPendingFlag
Any TX empty flag is pending.
-
enumerator kMU_GenIntPendingFlag
Any general interrupt flag is pending.
-
enumerator kMU_EventPendingFlag
MU event pending.
-
enumerator kMU_FlagsUpdatingFlag
MU flags update is on-going.
-
enumerator kMU_MuInResetFlag
MU of any side is in reset.
-
enumerator kMU_MuResetInterruptFlag
The other side initializes MU reset.
-
enumerator kMU_Tx0EmptyFlag
-
enum _mu_interrupt_enable
MU interrupt source to enable.
Values:
-
enumerator kMU_Tx0EmptyInterruptEnable
TX0 empty.
-
enumerator kMU_Tx1EmptyInterruptEnable
TX1 empty.
-
enumerator kMU_Tx2EmptyInterruptEnable
TX2 empty.
-
enumerator kMU_Tx3EmptyInterruptEnable
TX3 empty.
-
enumerator kMU_Rx0FullInterruptEnable
RX0 full.
-
enumerator kMU_Rx1FullInterruptEnable
RX1 full.
-
enumerator kMU_Rx2FullInterruptEnable
RX2 full.
-
enumerator kMU_Rx3FullInterruptEnable
RX3 full.
-
enumerator kMU_GenInt0InterruptEnable
General purpose interrupt 0.
-
enumerator kMU_GenInt1InterruptEnable
General purpose interrupt 1.
-
enumerator kMU_GenInt2InterruptEnable
General purpose interrupt 2.
-
enumerator kMU_GenInt3InterruptEnable
General purpose interrupt 3.
-
enumerator kMU_MuResetInterruptEnable
The other side initializes MU reset.
-
enumerator kMU_Tx0EmptyInterruptEnable
-
enum _mu_interrupt_trigger
MU interrupt that could be triggered to the other core.
Values:
-
enumerator kMU_GenInt0InterruptTrigger
General purpose interrupt 0.
-
enumerator kMU_GenInt1InterruptTrigger
General purpose interrupt 1.
-
enumerator kMU_GenInt2InterruptTrigger
General purpose interrupt 2.
-
enumerator kMU_GenInt3InterruptTrigger
General purpose interrupt 3.
-
enumerator kMU_GenInt0InterruptTrigger
-
enum _mu_msg_reg_index
MU message register index.
Values:
-
enumerator kMU_MsgReg0
Message register 0.
-
enumerator kMU_MsgReg1
Message register 1.
-
enumerator kMU_MsgReg2
Message register 2.
-
enumerator kMU_MsgReg3
Message register 3.
-
enumerator kMU_MsgReg0
-
enum _mu_general_purpose_interrupt
MU general purpose interrupts.
Values:
-
enumerator kMU_GeneralPurposeInterrupt0
General purpose interrupt 0
-
enumerator kMU_GeneralPurposeInterrupt1
General purpose interrupt 1
-
enumerator kMU_GeneralPurposeInterrupt2
General purpose interrupt 2
-
enumerator kMU_GeneralPurposeInterrupt3
General purpose interrupt 3
-
enumerator kMU_GeneralPurposeInterrupt0
-
typedef enum _mu_msg_reg_index mu_msg_reg_index_t
MU message register index.
-
typedef enum _mu_general_purpose_interrupt mu_general_purpose_interrupt_t
MU general purpose interrupts.
-
MU_CORE_INTR(intr)
-
MU_MISC_INTR(intr)
-
MU_TX_INTR(intr)
-
MU_RX_INTR(intr)
-
MU_GI_INTR(intr)
-
MU_GET_CORE_INTR(intrs)
-
MU_GET_TX_INTR(intrs)
-
MU_GET_RX_INTR(intrs)
-
MU_GET_GI_INTR(intrs)
-
MU_CORE_FLAG(flag)
-
MU_STAT_FLAG(flag)
-
MU_TX_FLAG(flag)
-
MU_RX_FLAG(flag)
-
MU_GI_FLAG(flag)
-
MU_GET_CORE_FLAG(flags)
-
MU_GET_STAT_FLAG(flags)
-
MU_GET_TX_FLAG(flags)
-
MU_GET_RX_FLAG(flags)
-
MU_GET_GI_FLAG(flags)
NETC driver
Status code for the NETC module.
Values:
-
enumerator kStatus_NETC_RxFrameEmpty
Rx BD ring empty.
-
enumerator kStatus_NETC_RxTsrResp
Rx timestamp reference response
-
enumerator kStatus_NETC_RxFrameError
Rx frame error.
-
enumerator kStatus_NETC_TxFrameOverLen
Tx frame over length.
-
enumerator kStatus_NETC_LackOfResource
Lack of resources to configure certain features.
-
enumerator kStatus_NETC_Unsupported
Unsupported operation/feature.
-
enumerator kStatus_NETC_RxHRZeroFrame
Rx frame host reason is zero
-
enumerator kStatus_NETC_RxHRNotZeroFrame
Rx frame host reason is not zero
-
enumerator kStatus_NETC_NotFound
No entry found in hardware tables
-
enumerator kStatus_NETC_EntryExists
An entry already exists in hardware tables
-
enumerator kStatus_NETC_RxFrameEmpty
-
enum _netc_ep_event
Defines the common interrupt event for callback use.
Values:
-
enumerator kNETC_EPRxEvent
EP Rx interrupt event.
-
enumerator kNETC_EPTxEvent
EP Tx interrupt event.
-
enumerator kNETC_EPRxEvent
-
enum _netc_ep_tx_status
Status for the transmit buffer descriptor.
Values:
-
enumerator kNETC_EPTxSuccess
Success transmission.
-
enumerator kNETC_EPTxProgramErr
Error exists in either the Tx BD, the Tx ring registers, or both.
-
enumerator kNETC_EPTxTsdDrop
The time defined in TX_START expired before frame could be transmitted.
-
enumerator kNETC_EPTxFrameSizeErr
Frame size error.
-
enumerator kNETC_EPTxNullAddr
Null address.
-
enumerator kNETC_EPTxInvalidLength
Invalid frame/buffer/chain length.
-
enumerator kNETC_EPTxSrcMacSpoofingDetect
Source MAC address spoofing detected.
-
enumerator kNETC_EPTxPortRestDrop
Frame dropped due to port reset.
-
enumerator kNETC_EPTxPortDisableDrop
Frame dropped due to port disable.
-
enumerator kNETC_EPTxVlanTpidDrop
VLAN TPID not allowed.
-
enumerator kNETC_EPTxSmsoParamErr
Programming error in buffer descriptor used for direct switch enqueue.
-
enumerator kNETC_EPTxFrameGateErr
Frame too large for time gating window.
-
enumerator kNETC_EPTxAxiReadErr
AXI read error.
-
enumerator kNETC_EPTxAxiWriteErr
AXI write error.
-
enumerator kNETC_EPTxMultiBitECCErr
Frame not transmitted(dropped) due to a multi-bit ECC error detected.
-
enumerator kNETC_EPTxParityErr
Parity error.
-
enumerator kNETC_EPTxSwCongestion
Frame dropped due to switch congestion.
-
enumerator kNETC_EPTxSuccess
-
enum _netc_vlan_tpid_select
Ethernet VLAN Tag protocol identifier.
Values:
-
enumerator kNETC_StanCvlan
0x8100.
-
enumerator kNETC_StanSvlan
0x88A8.
-
enumerator kNETC_CustomVlan1
CVLANR1[ETYPE]
-
enumerator kNETC_CustomVlan2
CVLANR2[ETYPE]
-
enumerator kNETC_StanCvlan
-
enum _netc_packet_type
Ethernet packet type enumerator.
Values:
-
enumerator kNETC_PacketUnicast
-
enumerator kNETC_PacketMulticast
-
enumerator kNETC_PacketBroadcast
-
enumerator kNETC_PacketUnicast
-
enum _netc_host_reason
Host reason.
Values:
-
enumerator kNETC_RegularFrame
-
enumerator kNETC_IngressMirror
-
enumerator kNETC_MACLearning
-
enumerator kNETC_TimestampResp
-
enumerator kNETC_SoftwareDefHR0
-
enumerator kNETC_SoftwareDefHR1
-
enumerator kNETC_SoftwareDefHR2
-
enumerator kNETC_SoftwareDefHR3
-
enumerator kNETC_SoftwareDefHR4
-
enumerator kNETC_SoftwareDefHR5
-
enumerator kNETC_SoftwareDefHR6
-
enumerator kNETC_SoftwareDefHR7
-
enumerator kNETC_RegularFrame
-
enum _netc_msix_vector_ctrl
MSIX vector control field.
Values:
-
enumerator kNETC_MsixIntrMaskBit
MSIX vector control interrupt mask bit.
-
enumerator kNETC_MsixIntrMaskBit
-
enum _netc_tx_ext_flags
METC Extension Transmit Buffer Descriptor Extension flags field.
Values:
-
enumerator kNETC_TxExtVlanInsert
Enable VLAN insert.
-
enumerator kNETC_TxExtTwoStepTs
Enable two-step timestamp offload.
-
enumerator kNETC_TxExtVlanInsert
-
typedef enum _netc_ep_event netc_ep_event_t
Defines the common interrupt event for callback use.
-
typedef enum _netc_ep_tx_status netc_ep_tx_status_t
Status for the transmit buffer descriptor.
-
typedef struct _netc_vlan netc_vlan_t
VLAN tag struct.
-
typedef enum _netc_vlan_tpid_select netc_vlan_tpid_select_t
Ethernet VLAN Tag protocol identifier.
-
typedef enum _netc_packet_type netc_packet_type_t
Ethernet packet type enumerator.
-
typedef enum _netc_host_reason netc_host_reason_t
Host reason.
-
typedef struct _ep_buffer_struct netc_buffer_struct_t
Buffer structure. Driver can send/receive one frame spread across multiple buffers.
-
typedef struct _ep_frame_struct netc_frame_struct_t
Frame structure for single Tx/Rx frame.
-
typedef struct _netc_frame_attr_struct netc_frame_attr_t
Frame attribute struct.
-
typedef struct _netc_tx_frame_info_struct netc_tx_frame_info_t
Frame attribute structure.
-
typedef enum _netc_msix_vector_ctrl netc_msix_vector_ctrl_t
MSIX vector control field.
-
typedef struct _netc_msix_entry netc_msix_entry_t
NETC MSIX entry structure.
-
typedef enum _netc_tx_ext_flags netc_tx_ext_flags_t
METC Extension Transmit Buffer Descriptor Extension flags field.
-
FSL_NETC_DRIVER_VERSION
Driver Version.
-
NETC_ADDR_LOW_32BIT(x)
Macro to divides an address into a low 32 bits and a possible high 32 bits.
-
NETC_ADDR_HIGH_32BIT(x)
-
struct _netc_vlan
- #include <fsl_netc.h>
VLAN tag struct.
Public Members
-
uint32_t vid
Vlan Identifier.
-
uint32_t dei
Drop Eligible indicator.
-
uint32_t pcp
Priority.
-
uint32_t tpid
Tag protocol identifier.
-
uint32_t vid
-
struct _ep_buffer_struct
- #include <fsl_netc.h>
Buffer structure. Driver can send/receive one frame spread across multiple buffers.
Public Members
-
void *buffer
Buffer address.
-
uint16_t length
Buffer data length.
-
void *buffer
-
struct _ep_frame_struct
- #include <fsl_netc.h>
Frame structure for single Tx/Rx frame.
Public Members
-
netc_buffer_struct_t *buffArray
Buffer array. Tx: [in]App sets, Rx: [in/out]App sets prepared array, driver sets back received buffers array.
-
uint16_t length
Buffer array length. Tx: [in]App sets, Rx: [in/out]App sets prepared array length, driver sets back received buffers array length.
-
netc_buffer_struct_t *buffArray
-
struct _netc_frame_attr_struct
- #include <fsl_netc.h>
Frame attribute struct.
Public Members
-
bool isTsAvail
Rx frame timestamp is available or not.
-
bool isVlanExtracted
Rx frame VLAN header is available or not.
-
uint32_t timestamp
The timestamp of this Rx frame.
-
bool isTsAvail
-
struct _netc_tx_frame_info_struct
- #include <fsl_netc.h>
Frame attribute structure.
Public Members
-
bool isTsAvail
Tx frame timestamp is available or not.
-
uint32_t timestamp
The timestamp of this Tx frame, valid when isTsAvail is true.
-
void *context
Private context provided by the user.
-
netc_ep_tx_status_t status
Transmit status.
-
bool isTsAvail
-
struct _netc_msix_entry
- #include <fsl_netc.h>
NETC MSIX entry structure.
Public Members
-
uint64_t msgAddr
Message address.
-
uint32_t msgData
Message data.
-
uint32_t control
Vector control, netc_msix_vector_ctrl_t.
-
uint64_t msgAddr
Abbreviation in NETC driver
API layer
NETC Endpoint (EP) Driver
Endpoint (EP) Generic Configuration
-
typedef struct _ep_handle ep_handle_t
Endpoint handle.
-
typedef status_t (*ep_reclaim_cb_t)(ep_handle_t *handle, uint8_t ring, netc_tx_frame_info_t *frameInfo, void *userData)
Callback for reclaimed tx frames.
-
typedef void *(*ep_rx_alloc_cb_t)(ep_handle_t *handle, uint8_t ring, uint32_t length, void *userData)
Defines the EP Rx memory buffer alloc function pointer.
-
typedef void (*ep_rx_free_cb_t)(ep_handle_t *handle, uint8_t ring, void *address, void *userData)
Defines the EP Rx memory buffer free function pointer.
-
typedef status_t (*ep_get_link_status_cb_t)(ep_handle_t *handle, uint8_t *link)
Callback for getting link status.
-
typedef status_t (*ep_get_link_speed_cb_t)(ep_handle_t *handle, netc_hw_mii_speed_t *speed, netc_hw_mii_duplex_t *duplex)
Callback for getting link speed.
-
typedef struct _ep_config ep_config_t
Configuration for the endpoint handle.
-
typedef struct _ep_config_const ep_config_const_t
Configuration constant in handle.
-
status_t EP_Init(ep_handle_t *handle, uint8_t *macAddr, const ep_config_t *config, const netc_bdr_config_t *bdrConfig)
Initialize the endpoint with specified station interface.
Each station interface needs to call this API. In the case of a virtual station interface it’s necessary that the physical station interface has been initialized beforehand.
- Parameters:
handle –
macAddr – Primary MAC address
config – The user configuration
bdrConfig – Array of buffer configurations (for each queue/ring)
- Returns:
status_t
-
status_t EP_Deinit(ep_handle_t *handle)
De-initialize the endpoint.
- Parameters:
handle –
- Returns:
status_t
-
status_t EP_GetDefaultConfig(ep_config_t *config)
Get the default configuration.
- Parameters:
config –
- Returns:
status_t
-
status_t EP_Up(ep_handle_t *handle, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)
Enable MAC transmission/reception To be called when the PHY link is up.
- Parameters:
handle –
speed –
duplex –
- Returns:
status_t
-
status_t EP_Down(ep_handle_t *handle)
Disable MAC transmission/reception To be called when the PHY link is down.
Note
Must ensure all active Tx rings finish current transmission before call this API.
- Parameters:
handle –
- Returns:
status_t
-
status_t EP_SetPrimaryMacAddr(ep_handle_t *handle, uint8_t *macAddr)
Set the Primary MAC address.
- Parameters:
handle –
macAddr –
- Returns:
status_t
-
static inline void EP_SetPortSpeed(ep_handle_t *handle, uint16_t pSpeed)
Set EP port speed.
- Parameters:
handle –
pSpeed –
-
struct _ep_config
- #include <fsl_netc_endpoint.h>
Configuration for the endpoint handle.
Public Members
-
netc_hw_si_idx_t si
Station interface index.
-
netc_hw_enetc_si_config_t siConfig
Station interface configuration.
-
uint8_t txPrioToTC[8]
Tx BD ring priority to Tx traffic class queue index mapping, range in TC0 ~ TC7.
-
netc_port_tx_tc_config_t txTcCfg[8]
Tx traffic class related configuration, vaild only on ENETC 0.
-
netc_ep_psfp_config_t psfpCfg
PSFP configuration,cover the ISI key construction profile and port ingress stream identification configuration.
-
bool enOuterAsInner
Enable use outer VLAN tag as the inner tag if only one tag is found.
-
netc_enetc_native_vlan_config_t rxOuterVLANCfg
Port outer native VLAN config.
-
netc_enetc_native_vlan_config_t rxInnerVLANCfg
Port inner native VLAN config.
-
netc_enetc_parser_config_t parserCfg
ENETC parser configuration.
-
uint32_t pauseOnThr
ENETC Port pause ON threshold value, value 0 means disables pause generation.
-
uint32_t pauseOffThr
ENETC Port pause OFF threshold value, value 0 means disables pause generation.
-
netc_msix_entry_t *msixEntry
MSIX table entry array.
-
uint8_t entryNum
MSIX entry number.
-
uint8_t cmdBdEntryIdx
MSIX entry index of command BD ring interrupt.
-
uint8_t siComEntryIdx
MSIX entry index of PSI-VSI communication interrupt.
-
uint8_t timerSyncEntryIdx
MSIX entry index of timer synchronous state change interrupt.
-
ep_reclaim_cb_t reclaimCallback
Callback for reclaimed Tx frames.
-
void *userData
User data, return in callback.
-
bool rxCacheMaintain
Enable/Disable Rx buffer cache maintain in driver.
-
bool txCacheMaintain
Enable/Disable Tx buffer cache maintain in driver.
-
bool rxZeroCopy
Enable/Disable zero-copy receive mode.
-
ep_rx_alloc_cb_t rxBuffAlloc
Callback function to alloc memory, must be provided for zero-copy Rx.
-
ep_rx_free_cb_t rxBuffFree
Callback function to free memory, must be provided for zero-copy Rx.
-
netc_cmd_bdr_config_t cmdBdrConfig
Command BD ring configuration.
-
netc_hw_si_idx_t si
-
struct _ep_config_const
- #include <fsl_netc_endpoint.h>
Configuration constant in handle.
Public Members
-
netc_hw_si_idx_t si
Station interface index.
-
uint32_t rxRingUse
Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings.
-
uint32_t txRingUse
Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0.
-
uint32_t rxBdrGroupNum
Rx BD ring group number, range in 0 ~ 2.
-
uint32_t ringPerBdrGroup
The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero.
-
bool rxCacheMaintain
Enable/Disable Rx buffer cache maintain in driver.
-
bool txCacheMaintain
Enable/Disable Tx buffer cache maintain in driver.
-
bool rxZeroCopy
Enable/Disable zero-copy receive mode.
-
uint8_t entryNum
MSIX entry number.
-
ep_reclaim_cb_t reclaimCallback
Callback for reclaimed Tx frames.
-
void *userData
User data, return in callback.
-
ep_rx_alloc_cb_t rxBuffAlloc
Callback function to alloc memory, must be provided for zero-copy Rx.
-
ep_rx_free_cb_t rxBuffFree
Callback function to free memory, must be provided for zero-copy Rx.
-
netc_hw_si_idx_t si
-
struct _ep_handle
- #include <fsl_netc_endpoint.h>
Handle for the endpoint Private internal data.
Public Members
-
netc_enetc_hw_t hw
Hardware register map resource.
-
netc_enetc_cap_t capability
ENETC capability.
-
ep_config_const_t cfg
Endpoint configuration constant.
-
netc_rx_bdr_t rxBdRing[1]
Receive buffer descriptor ring.
-
netc_tx_bdr_t txBdRing[1]
Transmit buffer descriptor ring.
-
netc_cmd_bdr_t cmdBdRing
Command BD ring handle for endpoint.
-
uint8_t unicastHashCount[64]
Unicast hash index collisions counter.
-
uint8_t multicastHashCount[64]
Multicast hash index collisions counter.
-
uint8_t vlanHashCount[64]
VLAN hash index collisions counter.
-
uint8_t macFilterCount[64]
mac address filter index collisions counter.
-
uint8_t vlanFilterCount[64]
vlan address filter index collisions counter.
-
ep_get_link_status_cb_t getLinkStatus
Callback to get link status
-
ep_get_link_speed_cb_t getLinkSpeed
Callback to get link speed
-
uint16_t vsiBitMapNotifyLinkStatus
VSI bit map for link status notify
-
uint16_t vsiBitMapNotifyLinkSpeed
VSI bit map for link speed notify
-
netc_enetc_hw_t hw
-
struct port
Public Members
-
netc_port_ethmac_t ethMac
Ethernet MAC configuration.
-
netc_port_common_t common
Port common configuration.
-
bool enableTg
Enable port time gate scheduling.
-
bool enPseudoMacTxPad
Enable pseudo MAC Port Transmit Padding, will pad the frame to a minimum of 60 bytes and append 4 octets of FCS.
-
netc_port_ethmac_t ethMac
Endpoint (EP) data path
-
typedef struct _netc_ep_ipf_config netc_ep_ipf_config_t
Port Ingress Filter config.
-
typedef struct _netc_ep_psfp_config netc_ep_psfp_config_t
PSFP config.
-
struct _netc_ep_ipf_config
- #include <fsl_netc_endpoint.h>
Port Ingress Filter config.
Public Members
-
netc_ipf_config_t dosCfg
Configuration for L2/3 DOS.
-
netc_port_ipf_config_t portConfig
Configuration for port connected to enetc peripheral.
-
netc_ipf_config_t dosCfg
-
struct _netc_ep_psfp_config
- #include <fsl_netc_endpoint.h>
PSFP config.
Endpoint (EP) Interrupt Module
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enum _ep_interrupt_flag
Interrupt enable/disable flags.
The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER
Values:
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enumerator kNETC_EPPSIResetInterruptEnable
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enumerator kNETC_EPPSIMsgRxInterruptEnable
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enumerator kNETC_EPPSIResetInterruptEnable
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typedef enum _ep_interrupt_flag ep_interrupt_flag_t
Interrupt enable/disable flags.
The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER
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static inline void EP_CleanTxIntrFlags(ep_handle_t *handle, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)
Clean the SI transmit interrupt flags.
- Parameters:
handle – The EP handle.
txFrameIntrMask – IPV value to be mapped, bit x represents ring x.
txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x.
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static inline void EP_CleanRxIntrFlags(ep_handle_t *handle, uint32_t rxIntrMask)
Clean the SI receive interrupt flags.
- Parameters:
handle – The EP handle.
rxIntrMask – Rx interrupt bit mask, bit x represents ring x.
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status_t EP_MsixSetGlobalMask(ep_handle_t *handle, bool mask)
Set the global MSIX mask status.
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.
- Parameters:
handle – The EP handle
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
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status_t EP_MsixSetEntryMask(ep_handle_t *handle, uint8_t entryIdx, bool mask)
Set the MSIX entry mask status for specified entry.
This function masks/unmasks MSIX message for specified entry.
- Parameters:
handle – The EP handle
entryIdx – The entry index in the table.
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
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status_t EP_MsixGetPendingStatus(ep_handle_t *handle, uint8_t pbaIdx, uint64_t *status)
Get the MSIX pending status in MSIX PBA table.
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.
- Parameters:
handle – The EP handle
pbaIdx – The index of PBA array with 64-bit unit.
status – Pending status bit mask, bit n for entry n.
- Returns:
status_t
Endpoint (EP) Table Management Module
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status_t EP_CmdBDRInit(ep_handle_t *handle, const netc_cmd_bdr_config_t *config)
Initialize endpoint command BD ring.
- Parameters:
handle –
config – The command BD ring configuration
- Returns:
status_t
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status_t EP_CmdBDRDeinit(ep_handle_t *handle)
Deinit endpoint command BD ring.
- Parameters:
handle –
- Returns:
status_t
Endpoint (EP) PSI/VSI
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void EP_PsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)
PSI enables/disables specified interrupt.
- Parameters:
handle – The EP handle.
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
enable – Enable/Disable the interrupt.
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uint32_t EP_PsiGetStatus(ep_handle_t *handle)
PSI gets interrupt event flag status.
- Parameters:
handle – The EP handle.
- Returns:
The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
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void EP_PsiClearStatus(ep_handle_t *handle, uint32_t mask)
PSI clears interrupt event flag.
- Parameters:
handle – The EP handle.
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
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status_t EP_PsiSendMsg(ep_handle_t *handle, uint16_t msg, netc_vsi_number_t vsi)
PSI sends message to specified VSI(s)
- Parameters:
handle – The EP handle.
msg – The message to be sent.
vsi – The VSI number.
- Returns:
status_t
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bool EP_PsiCheckTxBusy(ep_handle_t *handle, netc_vsi_number_t vsi)
PSI checks Tx busy flag which should be cleaned when VSI receive the message data.
- Parameters:
handle – The EP handle.
vsi – The VSI number.
- Returns:
The busy status of specified VSI.
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status_t EP_PsiSetRxBuffer(ep_handle_t *handle, netc_vsi_number_t vsi, uint64_t buffAddr)
PSI sets Rx buffer to receive message from specified VSI.
Note
The buffer memory size should be big enough for the message data from VSI
- Parameters:
handle – The EP handle.
vsi – The VSI number.
buffAddr – The buffer address to store message data from VSI.
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status_t EP_PsiGetRxMsg(ep_handle_t *handle, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)
PSI gets Rx message from specified VSI.
- Parameters:
handle – The EP handle.
vsi – The VSI number.
msgInfo – The Rx message information.
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void EP_VsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)
Enable VSI interrupt.
- Parameters:
handle – The EP handle.
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.
enable – Enable/Disable interrupt.
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uint32_t EP_VsiGetStatus(ep_handle_t *handle)
Get VSI interrupt status.
- Parameters:
handle – The EP handle.
- Returns:
A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together.
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void EP_VsiClearStatus(ep_handle_t *handle, uint32_t mask)
Clear VSI interrupt status.
- Parameters:
handle – The EP handle.
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.
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status_t EP_VsiSendMsg(ep_handle_t *handle, uint64_t msgAddr, uint32_t msgLen)
VSI sends message to PSI.
- Parameters:
handle – The EP handle.
msgAddr – Address to store message ready to be sent, must be 64 bytes aligned.
msgLen – The message length, must be 32 bytes aligned.
- Returns:
status_t
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void EP_VsiCheckTxStatus(ep_handle_t *handle, netc_vsi_msg_tx_status_t *status)
Check VSI Tx status.
- Parameters:
handle – The EP handle.
status – The VSI Tx status structure.
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status_t EP_VsiReceiveMsg(ep_handle_t *handle, uint16_t *msg)
VSI receives message from PSI.
- Parameters:
handle – The EP handle.
msg – The message from PSI.
- Returns:
status_t
Endpoint (EP) Ingress data path configuration
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static inline status_t EP_RxParserConfig(ep_handle_t *handle, netc_port_parser_config_t *config)
Configure Parser in Receive Data Path.
- Parameters:
handle –
config –
- Returns:
status_t
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static inline status_t EP_RxVlanCInit(ep_handle_t *handle, const netc_vlan_classify_config_t *config)
Configure the customer vlan type.
- Parameters:
handle –
config –
- Returns:
status_t
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static inline status_t EP_RxVlanCConfigPort(ep_handle_t *handle, netc_port_vlan_classify_config_t *config)
Configure the Accepted Vlan.
- Parameters:
handle –
config –
- Returns:
status_t
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status_t EP_RxIPFInit(ep_handle_t *handle, netc_ep_ipf_config_t *config)
Enable / Disable Ingress Port Filtering.
Applied for both Switch and ENETC
- Parameters:
handle –
config – IPF general features
- Returns:
status_t
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static inline uint32_t EP_RxIPFGetTableRemainWordNum(ep_handle_t *handle)
Get remaining available word number (words size is 6 bytes) of the ingress Port Filter Table.
Note
This is a ternary match table, and the entries can vary in size, from 2 to 14 words.
- Parameters:
handle –
- Returns:
uint32_t
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status_t EP_RxIPFAddTableEntry(ep_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)
Add an entry for the ingress Port Filter Table.
This function do an add & query with return hardware id which can be used as future query / delete / update.
- Parameters:
handle –
config – IPF instance configuaration
entryID – The table entry ID read out
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxIPFUpdateTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)
Update entry in the ingress Port Filter Table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxIPFDelTableEntry(ep_handle_t *handle, uint32_t entryID)
Delete an entry for the ingress Port Filter Table.
- Parameters:
handle –
entryID – The table entry ID
- Returns:
status_t
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status_t EP_RxIPFResetMatchCounter(ep_handle_t *handle, uint32_t entryID)
Reset the counter of an ingress port filter entry.
- Parameters:
handle –
entryID – The table entry ID
- Returns:
status_t
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status_t EP_RxIPFGetMatchedCount(ep_handle_t *handle, uint32_t entryID, uint64_t *count)
Get the matched count for entry in IPF.
- Parameters:
handle –
entryID – The table entry ID
count – A count of how many times this entry has been matched.
- Returns:
status_t
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static inline status_t EP_RxPSFPInit(ep_handle_t *handle, const netc_ep_psfp_config_t *config)
Init the ENETC PSFP, inlcude.
- Parameters:
handle –
config –
- Returns:
status_t
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static inline uint32_t EP_RxPSFPGetISITableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of stream identification table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Filter, table.
- Parameters:
handle –
- Returns:
uint32_t
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status_t EP_RxPSFPAddISITableEntry(ep_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)
Add an entry into the stream identification table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxPSFPDelISITableEntry(ep_handle_t *handle, uint32_t entryID)
Delete an entry in the stream identification table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t EP_RxPSFPGetISTableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number of ingress stream table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
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status_t EP_RxPSFPAddISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)
Add an entry into the ingress stream table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxPSFPUpdateISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)
Update an entry in the ingress stream table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxPSFPDelISTableEntry(ep_handle_t *handle, uint32_t entryID)
Delete an entry in the stream identification table.
- Parameters:
handle –
entryID –
- Returns:
status_t
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static inline uint32_t EP_RxPSFPGetISFTableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of ingress stream filter table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification table.
- Parameters:
handle –
- Returns:
uint32_t
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status_t EP_RxPSFPAddISFTableEntry(ep_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)
Add an entry into the ingress stream filter table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t EP_RxPSFPUpdateISFTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)
Update an entry into the ingress stream filter table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPDelISFTableEntry(ep_handle_t *handle, uint32_t entryID)
Del an entry into the stream filter table.
- Parameters:
handle –
entryID –
- Returns:
status_t
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static inline uint32_t EP_RxPSFPGetRPTableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number of Rate Policer table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
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status_t EP_RxPSFPAddRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)
Add entry to Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)
Update entry in Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPAddOrUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)
Add or update entry in Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPDelRPTableEntry(ep_handle_t *handle, uint32_t entryID)
Delete entry in the Rate Policer table.
- Parameters:
handle –
entryID –
- Returns:
status_t
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status_t EP_RxPSFPGetRPStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)
Get statistic of specified Rate Policer entry.
- Parameters:
handle –
entryID –
statis –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t EP_RxPSFPGetISCTableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number of ingress stream count table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
status_t EP_RxPSFPAddISCTableEntry(ep_handle_t *handle, uint32_t entryID)
Add entry in ingress stream count table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPGetISCStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)
Get ingress stream count statistic.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPResetISCStatistic(ep_handle_t *handle, uint32_t entryID)
Reset the count of the ingress stream count.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t EP_RxPSFPGetSGITableRemainEntryNum(ep_handle_t *handle)
Get remaining available entry number of stream gate instance table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
status_t EP_RxPSFPAddSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)
Add entry in stream gate instance table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPUpdateSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)
Update entry in stream gate instance table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPDelSGITableEntry(ep_handle_t *handle, uint32_t entryID)
Delete entry in stream gate instance table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPGetSGIState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state)
Get state of the stream gate instance for specified entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t EP_RxPSFPGetSGCLTableRemainWordNum(ep_handle_t *handle)
Get remaining available words number of Stream Gate Control List table.
Note
This is a dynamic bounded index table, and number of words required for a stream gate control list is 1+N/2 where N is number of gate time slots in the stream gate control list. The remaining word should be greater than the want added entry size
- Parameters:
handle –
- Returns:
uint32_t
-
status_t EP_RxPSFPAddSGCLTableEntry(ep_handle_t *handle, netc_tb_sgcl_gcl_t *config)
Add entry into Stream Gate Control List Table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPDelSGCLTableEntry(ep_handle_t *handle, uint32_t entryID)
Delete entry of Stream Gate Control List Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPGetSGCLGateList(ep_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)
Get Stream Gate Control List Table entry gate control list.
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxPSFPGetSGCLState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)
Get state (ref count) for Stream Gate Control List table entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxL2MFInit(ep_handle_t *handle, netc_si_l2mf_config_t *config)
Init the L2 MAC Filter for a specified SI.
- Parameters:
handle – EP handle
config – The L2 MAC Filter configuration
- Returns:
status_t
-
status_t EP_RxL2MFAddHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)
Add entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.
- Parameters:
handle – EP handle
type – Unicast or multicast MAC address
macAddr – MAC address to be added in filter table
- Returns:
status_t
-
status_t EP_RxL2MFDelHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)
Delete entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.
- Parameters:
handle – EP handle
type – Unicast or multicast MAC address
macAddr – MAC address to be deleted from filter table
- Returns:
status_t
-
status_t EP_RxL2MFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint8_t *macAddr)
Add entry into the MAC filter exact match table.
The entry is associated to the current Station Interface
- Parameters:
handle –
idx – Index in the entry table
macAddr – MAC address for filter
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxL2MFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)
Delete entry into the MAC filter exact match table.
- Parameters:
handle – EP handle
idx – Index in the entry table
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxL2VFInit(ep_handle_t *handle, netc_si_l2vf_config_t *config)
For VLAN filter, use inner vlan tag or outer vlan tag.
- Parameters:
handle –
config –
- Returns:
status_t
-
status_t EP_RxL2VFAddHashEntry(ep_handle_t *handle, uint16_t vlanId)
Add entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.
- Parameters:
handle –
vlanId – VLAN identifier for filter
- Returns:
status_t
-
status_t EP_RxL2VFDelHashEntry(ep_handle_t *handle, uint16_t vlanId)
Delete entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.
- Parameters:
handle –
vlanId – VLAN identifier for filter
- Returns:
status_t
-
status_t EP_RxL2VFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint16_t vlanId, netc_vlan_tpid_select_t tpid)
Add entry into the MAC filter exact match table.
The entry is associated to the current Station Interface
- Parameters:
handle –
idx – Index in the entry table
vlanId – VLAN identifier
tpid – VLAN TPID
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_RxL2VFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)
Delete entry into the VLAN filter exact match table.
- Parameters:
handle –
idx – Index in the entry table
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline status_t EP_RxMapVlanToIpv(ep_handle_t *handle, netc_vlan_t vlan, uint8_t ipv)
Set the received Frame vlan to IPV mapping.
- Parameters:
handle –
vlan – Frame VLAN tag.
ipv – The IPV value to be mapped.
- Returns:
status_t
-
static inline status_t EP_RxMapIpvToRing(ep_handle_t *handle, uint8_t ipv, uint8_t ring)
Set the IPV to Rx ring mapping.
- Parameters:
handle –
ipv – IPV value to be mapped.
ring – The Rx BD ring index to be mapped.
- Returns:
status_t
-
static inline status_t EP_RxSetDefaultBDRGroup(ep_handle_t *handle, netc_hw_enetc_si_rxr_group groupIdx)
Set the default used receive Rx BD ring group.
Note
The IPV mapped ring index is the relative index inside the default used group.
- Parameters:
handle –
groupIdx – The default Rx group index.
- Returns:
status_t
Endpoint (EP) Statistic Module
-
enum _ep_flags
Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR.
Values:
-
enumerator kNETC_EPTimerSyncedFlag
-
enumerator kNETC_EPICMBlockedFlag
-
enumerator kNETC_EPWakeOnLANActiveFlag
-
enumerator kNETC_EPTimerSyncedFlag
-
typedef enum _ep_flags ep_flags_t
Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR.
-
static inline status_t EP_GetPortDiscardStatistic(ep_handle_t *handle, bool useTx, netc_port_discard_statistic_t *statistic)
Get the ENETC port discard statistic and reason.
Get the discarded count of frames and its reasons.
- Parameters:
handle –
useTx – true - Tx port. false - Rx port.
statistic – pointer to the statistic data
- Returns:
status_t
-
static inline status_t EP_ClearPortDiscardReason(ep_handle_t *handle, bool useTx, uint32_t reason0, uint32_t reason1)
Clean the EP Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.
- Parameters:
handle –
useTx – true - Tx port. false - Rx port.
reason0 –
reason1 –
- Returns:
status_t
-
static inline uint32_t EP_GetPortTGSListStatus(ep_handle_t *handle)
Get EP port time gate scheduling gate list status.
- Parameters:
handle –
- Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t
Endpoint (EP) Egress data path configuration
-
status_t EP_TxTGSConfigAdminGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *config)
Config the Time Gate Scheduling entry admin gate control list.
This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_TxPortTGSEnable(ep_handle_t *handle, bool enable, uint8_t gateState)
Enable the EP port time gate scheduling.
- Parameters:
handle –
enable –
gateState –
- Returns:
status_t
-
status_t EP_TxtTGSGetOperGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)
Get Time Gate Scheduling entry operation gate control list.
This function is used to read the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t EP_TxTrafficClassConfig(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config)
Config the TC (traffic class) property.
- Parameters:
handle –
tcIdx –
config –
- Returns:
status_t
Endpoint (EP) Transmit/Receive
-
enum _ep_rx_flags
Values:
-
enumerator kEP_RX_RSS_VALID
Request timestamp.
-
enumerator kEP_RX_VLAN_VALID
Specifiy frame departure time.
-
enumerator kEP_RX_TIMESTAMP_VALID
Enable port masquerading.
-
enumerator kEP_RX_RSS_VALID
-
enum _ep_tx_opt_flags
Values:
-
enumerator kEP_TX_OPT_REQ_TS
Request timestamp (IEEE 1588 PTP two-step timestamp).
-
enumerator kEP_TX_OPT_VLAN_INSERT
Enable VLAN insert.
-
enumerator kEP_TX_OPT_START_TIME
Specifiy frame departure time.
-
enumerator kEP_TX_OPT_REQ_TS
-
typedef enum _ep_rx_flags ep_rx_flags_t
-
typedef enum _ep_tx_opt_flags ep_tx_opt_flags
-
typedef struct _ep_tx_offload netc_tx_offload_t
-
typedef struct _ep_tx_opt ep_tx_opt
-
status_t EP_SendFrameCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, netc_frame_struct_t *frame, void *context, netc_tx_bd_t *txDesc, bool txCacheMaintain)
Common part for transfer regular frame or Switch management frame.
Note
This function is internal used. Please use EP_SendFrame() or SWT_SendFrame() API to send frames.
- Parameters:
handle –
txBdRing – The Transmit buffer descriptor ring handle
hwRing – The hardware Tx ring index
frame – The frame descriptor pointer
context – Private context provided back by ep_reclaim_cb_t
txDesc – Point to the Transmits BD Description array.
txCacheMaintain – Enable/Disable Tx buffer Cache Maintain.
- Return values:
status_t –
-
status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, void *context, ep_tx_opt *opt)
Transmits a frame for specified ring. This API is zero-copy and requires the ep_reclaim_cb_t to be called to free the transmitted frame.
- Parameters:
handle –
ring – The ring index
frame – The frame descriptor pointer
context – Private context provided back by ep_reclaim_cb_t
opt – Additional tx options. If NULL, default is tx timestamping enabled, no start time and no masquerading.
- Return values:
status_t –
-
static inline void EP_WaitUnitilTxComplete(ep_handle_t *handle, uint8_t ring)
Wait until the EP Tx ring has completed the transfer.
Note
Only call after EP_SendFrame() to do a no-interrupt transfer
- Parameters:
handle –
ring – The ring index
-
netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, bool enCallback)
Common part of Reclaim tx descriptors for regular frame or Switch management frame.
Note
This function is internal used. Please use EP_ReclaimTxDescriptor() or SWT_ReclaimTxDescriptor() API to Reclaim tx descriptors.
- Parameters:
handle –
txBdRing – The Transmit buffer descriptor ring handle
hwRing – The hardware Tx ring index
enCallback – Enable/Disable call the Tx Reclaim callback functions.
-
void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring)
Reclaim tx descriptors. This function is used to update the tx descriptor status and get the tx timestamp. For each reclaimed transmit frame the ep_reclaim_cb_t is called.
This is called after being notified of a transmit completion from ISR. It runs until there are no more frames to be reclaimed in the BD ring.
- Parameters:
handle –
ring – The ring index
-
status_t EP_ReceiveFrameCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr, bool rxCacheMaintain)
Common part of receives one frame with zero copy from specified ring.
Note
This function is internal used. Please use EP_ReceiveFrame() or SWT_ReceiveFrame() API.
- Parameters:
handle –
rxBdRing – Rx BD ring handle
ring – Ring index
frame – Frame buffer point
attr – Frame attribute pointer
rxCacheMaintain – Enable/Disable Rx buffer Cache maintain
- Returns:
status_t
-
status_t EP_ReceiveFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr)
Receives one frame with zero copy from specified ring.
Note
The sufficient rx frame data structure MUST be provided by appliction.
- Parameters:
handle –
ring – The ring index
frame – The frame descriptor pointer
attr – Frame attribute pointer
- Returns:
kStatus_Success Successfully receive a regular frame
- Returns:
kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_ReceiveFrame()
- Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response
- Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty
- Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped
- Returns:
kStatus_InvalidArgument Rx BD ring index is out of range
- Returns:
kStatus_NETC_LackOfResource Appliction provided buffer is not enough
-
void EP_DropFrame(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring)
Drop one frame.
Note
This function is internal used.
- Parameters:
handle –
rxBdRing – Rx BD ring handle
ring – Ring index
-
status_t EP_ReceiveFrameCopyCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr, bool rxCacheMaintain)
Common part of receive regular frame or Switch management frame which will be copied in the provided buffer.
Note
This function is internal used. Please use EP_ReceiveFrameCopy() or SWT_ReceiveFrameCopy() API.
- Parameters:
handle –
rxBdRing – Rx BD ring handle
ring – Ring index
buffer – Buffer address
length – Buffer length
attr – Frame attribute pointer
rxCacheMaintain – Enable/Disable Rx buffer Cache maintain
- Returns:
status_t
-
status_t EP_ReceiveFrameCopy(ep_handle_t *handle, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr)
Receives one frame which will be copied in the provided buffer from specified ring.
Note
The buffer size MUST be queried using EP_GetRxFrameSize() beforehand.
- Parameters:
handle –
ring – Ring index
buffer – Buffer address
length – Buffer length
attr – Frame attribute pointer
- Returns:
kStatus_Success Successfully receive a regular frame
- Returns:
kStatus_InvalidArgument Rx BD ring index is out of range
-
status_t EP_GetRxFrameSizeCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint32_t *length)
Common part of get pending frame size API for regular frame or Switch management frame.
Note
This function is internal used. Please use EP_GetRxFrameSize() or SWT_GetRxFrameSize() API.
- Parameters:
handle –
rxBdRing – Rx BD ring handle
length – The length of the valid frame received.
- Returns:
status_t
-
status_t EP_GetRxFrameSize(ep_handle_t *handle, uint8_t ring, uint32_t *length)
Gets the size of the pending frame in the specified receive ring buffer.
Note
Frame size without FCS
- Parameters:
handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.
ring – The ring index
length – The length of the valid frame received.
- Returns:
kStatus_Success Successfully get the length of a regular frame
- Returns:
kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_GetRxFrameSize() to get frame size
- Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response
- Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty
- Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped
- Returns:
kStatus_InvalidArgument Rx BD ring index is out of range
-
struct _ep_tx_offload
- #include <fsl_netc_endpoint.h>
Public Members
-
bool lso
Large send offload.
-
bool l4Checksum
L4 checksum offload.
-
bool ipv4Checksum
IPv4 checksum offload.
-
uint32_t lsoMaxSegSize
Large send offload maximum segment size.
-
uint32_t l4Type
L4 type. 1-UDP, 2-TCP.
-
uint32_t l3Type
L3 type. 0-IPv4, 1-IPv6.
-
uint32_t l3HeaderSize
L3 IP header size in units of 32-bit words.
-
uint32_t l3Start
Offset of the IPv4/IPv6 header in units of bytes.
-
bool lso
-
struct _ep_tx_opt
- #include <fsl_netc_endpoint.h>
Public Members
-
uint32_t flags
A bitmask of ep_tx_opt_flags
-
uint32_t timestamp
Departure timestamp, used if kEP_TX_OPT_START_TIME is set
-
netc_enetc_vlan_tag_t vlan
VLAN tag which will be inserted, used if kEP_TX_OPT_VLAN_INSERT is set
-
uint32_t flags
Hardware layer
-
enum _netc_hw_enetc_idx
ENETC index enumerator.
Values:
-
enumerator kNETC_ENETC0
ENETC hardware 0
-
enumerator kNETC_ENETC1
ENETC hardware 0
-
enumerator kNETC_ENETC0
-
enum _netc_hw_switch_idx
SWITCH index enumerator.
Values:
-
enumerator kNETC_SWITCH0
SWITCH hardware 0
-
enumerator kNETC_SWITCH0
-
enum _netc_hw_port_idx
Port Resource for the NETC module.
Values:
-
enumerator kNETC_ENETC0Port
MAC port for ENETC0
-
enumerator kNETC_ENETC1Port
Pseudo MAC port for ENETC1
-
enumerator kNETC_SWITCH0Port0
MAC port0 for SWITCH
-
enumerator kNETC_SWITCH0Port1
MAC port1 for SWITCH
-
enumerator kNETC_SWITCH0Port2
MAC port2 for SWITCH
-
enumerator kNETC_SWITCH0Port3
MAC port3 for SWITCH
-
enumerator kNETC_SWITCH0Port4
Pseudo port4 for SWITCH
-
enumerator kNETC_ENETC0Port
-
enum _netc_hw_tc_idx
Traffic class enumerator.
Values:
-
enumerator kNETC_TxTC0
Traffic class 0
-
enumerator kNETC_TxTC1
Traffic class 1
-
enumerator kNETC_TxTC2
Traffic class 2
-
enumerator kNETC_TxTC3
Traffic class 3
-
enumerator kNETC_TxTC4
Traffic class 4
-
enumerator kNETC_TxTC5
Traffic class 5
-
enumerator kNETC_TxTC6
Traffic class 6
-
enumerator kNETC_TxTC7
Traffic class 7
-
enumerator kNETC_TxTC0
-
enum _netc_hw_bdr_idx
Enumeration for the ENETC SI BDR identifier.
Values:
-
enumerator kNETC_BDR0
-
enumerator kNETC_BDR1
-
enumerator kNETC_BDR2
-
enumerator kNETC_BDR3
-
enumerator kNETC_BDR4
-
enumerator kNETC_BDR5
-
enumerator kNETC_BDR6
-
enumerator kNETC_BDR7
-
enumerator kNETC_BDR8
-
enumerator kNETC_BDR9
-
enumerator kNETC_BDR10
-
enumerator kNETC_BDR11
-
enumerator kNETC_BDR12
-
enumerator kNETC_BDR13
-
enumerator kNETC_BDR0
-
enum _netc_hw_swt_cbdr_idx
Switch command BD ring index enumerator.
Values:
-
enumerator kNETC_SWTCBDR0
Switch command BD ring 0
-
enumerator kNETC_SWTCBDR1
Switch command BD ring 1
-
enumerator kNETC_SWTCBDR0
-
enum _netc_hw_classs_queue_idx
Enumerator for ETM class queue identifier.
Values:
-
enumerator kNETC_ClassQueue0
ETM Class Queue 0
-
enumerator kNETC_ClassQueue1
ETM Class Queue 1
-
enumerator kNETC_ClassQueue2
ETM Class Queue 2
-
enumerator kNETC_ClassQueue3
ETM Class Queue 3
-
enumerator kNETC_ClassQueue4
ETM Class Queue 4
-
enumerator kNETC_ClassQueue5
ETM Class Queue 5
-
enumerator kNETC_ClassQueue6
ETM Class Queue 6
-
enumerator kNETC_ClassQueue7
ETM Class Queue 7
-
enumerator kNETC_ClassQueue0
-
enum _netc_hw_congestion_group_idx
Enumerator for the ETM congestion group.
Values:
-
enumerator kNETC_CongGroup0
-
enumerator kNETC_CongGroup1
-
enumerator kNETC_CongGroup0
-
enum _netc_hw_mii_mode
Defines the MII/RGMII mode for data interface between the MAC and the PHY.
Values:
-
enumerator kNETC_XgmiiMode
XGMII mode for data interface.
-
enumerator kNETC_MiiMode
MII mode for data interface.
-
enumerator kNETC_GmiiMode
GMII mode for data interface.
-
enumerator kNETC_RmiiMode
RMII mode for data interface.
-
enumerator kNETC_RgmiiMode
RGMII mode for data interface.
-
enumerator kNETC_SgmiiMode
SGMII mode for data interface.
-
enumerator kNETC_XgmiiMode
-
enum _netc_hw_mii_speed
Defines the speed for the *MII data interface.
Values:
-
enumerator kNETC_MiiSpeed10M
Speed 10 Mbps.
-
enumerator kNETC_MiiSpeed100M
Speed 100 Mbps.
-
enumerator kNETC_MiiSpeed1000M
Speed 1000 Mbps.
-
enumerator kNETC_MiiSpeed2500M
Speed 2500 Mbps.
-
enumerator kNETC_MiiSpeed5G
Speed 5Gbps.
-
enumerator kNETC_MiiSpeed10G
Speed 10Gbps Mbps.
-
enumerator kNETC_MiiSpeed10M
-
enum _netc_hw_mii_duplex
Defines the half or full duplex for the MII data interface.
Values:
-
enumerator kNETC_MiiHalfDuplex
Half duplex mode.
-
enumerator kNETC_MiiFullDuplex
Full duplex mode.
-
enumerator kNETC_MiiHalfDuplex
-
typedef enum _netc_hw_enetc_idx netc_hw_enetc_idx_t
ENETC index enumerator.
-
typedef enum _netc_hw_switch_idx netc_hw_switch_idx_t
SWITCH index enumerator.
-
typedef enum _netc_hw_port_idx netc_hw_port_idx_t
Port Resource for the NETC module.
-
typedef enum _netc_hw_tc_idx netc_hw_tc_idx_t
Traffic class enumerator.
-
typedef enum _netc_hw_bdr_idx netc_hw_bdr_idx_t
Enumeration for the ENETC SI BDR identifier.
-
typedef enum _netc_hw_swt_cbdr_idx netc_hw_swt_cbdr_idx_t
Switch command BD ring index enumerator.
-
typedef enum _netc_hw_classs_queue_idx netc_hw_etm_class_queue_idx_t
Enumerator for ETM class queue identifier.
-
typedef enum _netc_hw_congestion_group_idx netc_hw_congestion_group_idx_t
Enumerator for the ETM congestion group.
-
typedef enum _netc_hw_mii_mode netc_hw_mii_mode_t
Defines the MII/RGMII mode for data interface between the MAC and the PHY.
-
typedef enum _netc_hw_mii_speed netc_hw_mii_speed_t
Defines the speed for the *MII data interface.
-
typedef enum _netc_hw_mii_duplex netc_hw_mii_duplex_t
Defines the half or full duplex for the MII data interface.
-
typedef struct _netc_psfp_kc_profile netc_isi_kc_rule_t
NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes.
-
typedef struct _netc_vlan_classify_config netc_vlan_classify_config_t
NETC Vlan classification config.
-
typedef struct _netc_qos_classify_profile netc_qos_classify_profile_t
NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map)
-
typedef struct _netc_ipf_config netc_ipf_config_t
NETC Ingress Filter config.
-
typedef struct _netc_func netc_func_t
Register groups for the PCIe function.
-
typedef struct _netc_port_hw netc_port_hw_t
Register groups for the Port/Link hardware.
-
typedef struct _netc_enetc_hw netc_enetc_hw_t
Register group for the ENETC peripheral hardware.
-
typedef struct _netc_timer_hw netc_timer_hw_t
Register group for the Timer peripheral hardware.
-
typedef struct _netc_mdio_hw netc_mdio_hw_t
Register group for both EMDIO and port external MDIO.
-
getSiInstance(si)
Get SI information from netc_hw_si_idx_t.
The ENETC instance of this SI.
-
getSiNum(si)
The SI number in the ENETC.
-
getSiIdx(si)
The actaul index in the netc_hw_si_idx_t.
-
NETC_MSIX_TABLE_OFFSET
MSIX table address offset.
-
NETC_MSIX_TABLE_PBA_OFFSET
MSIX PBA address offset.
-
NETC_NANOSECOND_ONE_SECOND
Nanosecond in one second.
-
struct _netc_psfp_kc_profile
- #include <fsl_netc.h>
NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes.
Public Members
-
bool etp
2 Byte Ethertype field present in the key
-
bool sqtp
1 Byte Sequence Tag present in the key
-
bool ipcpp
inner VLAN header’s PCP field present in the key
-
bool ividp
inner VLAN ID present in the key
-
bool opcpp
outer VLAN header’s PCP field present in the key
-
bool ovidp
outer VLAN ID present in the key
-
bool smacp
6 bytes of source MAC address present in the key
-
bool dmacp
6 bytes of destination MAC address present in the key
-
bool spmp
switch port masquerading flag present in the key
-
bool portp
source port present in the key
-
bool valid
Key Construction is valid
-
bool etp
-
struct _netc_vlan_classify_config
- #include <fsl_netc.h>
NETC Vlan classification config.
Public Members
-
bool enableCustom1
Enable/Disable custom0 ether type
-
uint16_t custom1EtherType
Ethertype
-
bool enableCustom2
Enable/Disable custom0 ether type
-
uint16_t custom2EtherType
Ethertype
-
uint16_t preStandRTAGType
802.1CB draft 2.0 R-TAG Ethertype value. PSRTAGETR. Only applicable for switch
-
bool enableCustom1
-
struct _netc_qos_classify_profile
- #include <fsl_netc.h>
NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map)
Public Members
-
uint8_t ipv[16]
Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped IPV for Qos.
-
uint8_t dr[16]
Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped DR for QoS.
-
uint8_t ipv[16]
-
struct _netc_ipf_config
- #include <fsl_netc.h>
NETC Ingress Filter config.
Public Members
-
bool l2DiscardMCSmac
DOSL2CR. Discard received frames with Multicast SMAC address
-
bool l2DiscardSmacEquDmac
DOSL2CR. Discard received frames with SMAC = DMAC
-
bool l3DiscardSipEquDip
DOSL3CR. Discard IPV3/IPV6 source address == destination address
-
bool l2DiscardMCSmac
-
struct _netc_func
- #include <fsl_netc_hw.h>
Register groups for the PCIe function.
-
struct _netc_port_hw
- #include <fsl_netc_hw.h>
Register groups for the Port/Link hardware.
Public Members
-
NETC_PORT_Type *port
Port Address
-
NETC_PORT_Type *port
-
struct _netc_enetc_hw
- #include <fsl_netc_hw.h>
Register group for the ENETC peripheral hardware.
Public Members
-
netc_func_t func
PCIE function register
-
NETC_ENETC_Type *base
Base register of ENETC module
-
NETC_SW_ENETC_Type *common
Common register of ENETC module
-
netc_port_hw_t portGroup
Port register group
-
ENETC_GLOBAL_Type *global
Global NETC address
-
ENETC_SI_Type *si
Station Interfce for the P/V SI
-
netc_msix_entry_t *msixTable
MSIX table address
-
netc_func_t func
-
struct _netc_timer_hw
- #include <fsl_netc_hw.h>
Register group for the Timer peripheral hardware.
Public Members
-
ENETC_PCI_TYPE0_Type *func
PCIE function register
-
ENETC_PF_TMR_Type *base
Base register address for timer module
-
ENETC_GLOBAL_Type *global
Global NETC register address
-
netc_msix_entry_t *msixTable
MSIX table address
-
ENETC_PCI_TYPE0_Type *func
-
struct _netc_mdio_hw
- #include <fsl_netc_hw.h>
Register group for both EMDIO and port external MDIO.
Public Members
- __IO uint32_t EMDIO_CFG
External MDIO configuration register, offset: 0x1C00
- __IO uint32_t EMDIO_CTL
External MDIO interface control register, offset: 0x1C04
- __IO uint32_t EMDIO_DATA
External MDIO interface data register, offset: 0x1C08
- __IO uint32_t EMDIO_ADDR
External MDIO register address register, offset: 0x1C0C
- __I uint32_t EMDIO_STAT
External MDIO status register, offset: 0x1C10
- __IO uint32_t PHY_STATUS_CFG
PHY status configuration register, offset: 0x1C20
- __IO uint32_t PHY_STATUS_CTL
PHY status control register, offset: 0x1C24
- __I uint32_t PHY_STATUS_DATA
PHY status data register, offset: 0x1C28
- __IO uint32_t PHY_STATUS_ADDR
PHY status register address register, offset: 0x1C2C
- __IO uint32_t PHY_STATUS_EVENT
PHY status event register, offset: 0x1C30
- __IO uint32_t PHY_STATUS_MASK
PHY status mask register, offset: 0x1C34
-
struct payload
Public Members
-
uint8_t lbMask
Payload Last Byte Mask
-
uint8_t fbMask
Payload First Byte Mask
-
uint8_t byteOffset
Payload Byte Offset where field extraction begins
-
uint8_t numBytes
Specify the size (numBytes + 1) of the payload key field
-
uint8_t pfp
Payload field Present
-
uint8_t lbMask
-
union __unnamed213__
Public Members
-
ENETC_PCI_TYPE0_Type *pf
PSI function
-
ENETC_VF_PCI_TYPE0_Type *vf
VSI function
-
ENETC_PCI_TYPE0_Type *pf
-
union __unnamed215__
Public Members
-
NETC_ETH_LINK_Type *eth
MAC Port Address
-
NETC_ETH_LINK_Type *eth
Hardware Common Functions
-
static inline uint16_t EP_IncreaseIndex(uint16_t index, uint32_t max)
-
uint16_t NETC_SIGetVsiIndex(netc_vsi_number_t vsi)
Get the VSI index.
- Parameters:
vsi – The VSI number.
-
static inline void NETC_IPFInit(NETC_SW_ENETC_Type *base, const netc_ipf_config_t *config)
Set layer2/3 Dos configuration.
- Parameters:
base –
config –
-
void NETC_PSFPKcProfileInit(NETC_SW_ENETC_Type *base, const netc_isi_kc_rule_t *rule, bool enKcPair1)
Initialize the Ingress Stream Identification Key construction rule profiles.
- Parameters:
base –
rule –
enKcPair1 –
- Returns:
void
-
void NETC_RxVlanCInit(NETC_SW_ENETC_Type *base, const netc_vlan_classify_config_t *config, bool enRtag)
Initialize the customer vlan type.
- Parameters:
base –
config –
enRtag –
- Returns:
void
-
void NETC_RxQosCInit(NETC_SW_ENETC_Type *base, const netc_qos_classify_profile_t *profile, bool enProfile1)
Initialize the ingress QoS classification.
- Parameters:
base –
profile –
enProfile1 –
Hardware ENETC
-
typedef struct _netc_enetc_vlan_tag_t netc_enetc_vlan_tag_t
ENETC Port outer/inner VLAN tag.
-
typedef struct _netc_enetc_discard_statistic netc_enetc_port_discard_statistic_t
PORT discard count statistic.
-
typedef struct _netc_enetc_native_vlan_config_t netc_enetc_native_vlan_config_t
ENETC Port outer/inner native VLAN config.
-
typedef struct _netc_enetc_parser_config_t netc_enetc_parser_config_t
ENETC parser configuration.
-
typedef struct _netc_enetc_cap netc_enetc_cap_t
ENETC capability.
-
static inline bool NETC_EnetcHasManagement(NETC_ENETC_Type *base)
Check whether ENETC has switch management capability.
- Parameters:
base – NETC peripheral base address.
- Returns:
true or false
-
void NETC_EnetcGetCapability(NETC_ENETC_Type *base, netc_enetc_cap_t *capability)
Get ENETC capability.
- Parameters:
base – NETC peripheral base address.
capability – Pointer to capability structure.
-
void NETC_EnetcSetSIMacAddr(NETC_ENETC_Type *base, uint8_t si, uint8_t *macAddr)
Set MAC address for specified VSI of ENETC.
- Parameters:
base –
macAddr –
-
status_t NETC_EnetcConfigureSI(NETC_ENETC_Type *base, uint8_t si, const netc_hw_enetc_si_config_t *psConfig)
Configure SI.
- Parameters:
base – ENETC peripheral base address.
si – The SI number
psConfig – The SI configuration
- Returns:
status_t
-
status_t NETC_EnetcSetMsixEntryNum(NETC_ENETC_Type *base, uint8_t si, uint32_t msixNum)
Set SI MSIX table entry number.
- Parameters:
base – ENETC peripheral base address.
si – The SI number.
msixNum – The MSIX table entry number.
- Returns:
status_t
-
static inline void NETC_EnetcEnableSI(NETC_ENETC_Type *base, uint8_t si, bool enable)
Enable/Disable specified SI.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
enable – Enable/Disable SI from ENETC layer.
-
void NETC_EnetcGetPortDiscardStatistic(NETC_ENETC_Type *base, netc_enetc_port_discard_statistic_t *statistic)
Get ENETC discard statistic data.
- Parameters:
base – ENETC peripheral base address.
statistic – Statistic data.
-
void NETC_EnetcEnablePromiscuous(NETC_ENETC_Type *base, uint8_t si, bool enableUCPromis, bool enableMCPromis)
Enable MAC promiscuous mode.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
enableUCPromis – Enable unicast frame promiscuous.
enableMCPromis – Enable multicast frame promiscuous.
-
void NETC_EnetcConfigureVlanFilter(NETC_ENETC_Type *base, uint8_t si, netc_si_l2vf_config_t *config)
Configure VLAN filter.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
config – Enable untagged VLAN frame promiscuous.
-
void NETC_EnetcAddMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)
Add the hash filter for the MAC address.
Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
type – Unicast or multicast frame type.
hashIndex – The calculated hash index of MAC address.
-
void NETC_EnetcDelMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)
Remove the hash filter for the MAC address.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
type – Unicast or multicast frame type.
hashIndex – The calculated hash index of MAC address.
-
void NETC_EnetcAddVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)
Add the hash filter for the VLAN.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
hashIndex – The calculated hash index of MAC address.
-
void NETC_EnetcDelVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)
Remove the hash filter for the VLAN.
- Parameters:
base – ENETC peripheral base address.
si – SI index.
hashIndex – The calculated hash index of MAC address.
-
static inline status_t NETC_EnetcPortEnableTSD(NETC_ENETC_Type *base, netc_hw_tc_idx_t tcIdx, bool isEnable)
Enable / Disable ENETC Port Time Specific Departure (TSD) feature.
It can’t work with QBV CBS
- Parameters:
base –
tcIdx –
isEnable –
- Returns:
status_t
-
static inline void NETC_EnetcPortSetNativeVLAN(NETC_ENETC_Type *base, const netc_enetc_native_vlan_config_t *config, bool isOuter)
Set ENETC Rx native outer/inner VLAN.
It is used for classification when untagged frames are received by the port.
- Parameters:
base –
config –
isOunter –
-
static inline void NETC_EnetcSetParser(NETC_ENETC_Type *base, const netc_enetc_parser_config_t *config)
Set ENETC Parser configuration.
PARCSCR and PARCE0CR - PARCE3CR.
- Parameters:
base –
config –
-
static inline void NETC_EnetcEnableWakeOnLan(NETC_ENETC_Type *base, bool isEnable)
Enable / Disable ENETC Wake-on-LAN mode.
Only available on ENETC 0
- Parameters:
base –
isEnable –
- Returns:
status_t
-
struct _netc_enetc_vlan_tag_t
- #include <fsl_netc.h>
ENETC Port outer/inner VLAN tag.
Public Members
-
uint16_t pcp
Priority code point
-
uint16_t dei
Drop eligible indicator
-
uint16_t vid
VLAN identifier
-
netc_vlan_tpid_select_t tpid
Tag protocol identifier
-
uint16_t pcp
-
struct _netc_enetc_discard_statistic
- #include <fsl_netc.h>
PORT discard count statistic.
Public Members
-
uint32_t ingressDR[4]
Discard count for port ingress congestion different DR
-
uint32_t broadcastReject
Broadcast frame drops count due to all SI enable broadcast reject
-
uint32_t smacPruning
Frames discard count due to port MAC source address pruning
-
uint32_t unicastMacFilt
Unicast frame discard count due to port MAC filtering
-
uint32_t multicastMacFilt
Multicast frame discard count due to MAC filtering
-
uint32_t unicastVlanFilt
Unicast frame discard count due to VLAN filtering
-
uint32_t multicastVlanFilt
Multicast frame discard count due to VLAN filtering
-
uint32_t boradcastVlanFilt
Broadcast frame discard count due to VLAN filtering
-
uint32_t ingressDR[4]
-
struct _netc_enetc_native_vlan_config_t
- #include <fsl_netc.h>
ENETC Port outer/inner native VLAN config.
Public Members
-
bool enUnderZeroVid
Enable use the port default VLAN VID when the VID in the packet’s is zero
-
bool enUnderNoVlan
Enable use the port default VLAN VID when the VLAN tag is not present
-
netc_enetc_vlan_tag_t vlanTag
Port native outer/inner VLAN tag, valid when enUnderZeroVid or enUnderNoVlan is true
-
bool enUnderZeroVid
-
struct _netc_enetc_parser_config_t
- #include <fsl_netc.h>
ENETC parser configuration.
Public Members
-
bool disL3Checksum
Disable Layer 3 IPv4 Header checksum validation.
-
bool disL4Checksum
Disable Layer 4 TCP and UDP checksum validation.
-
bool disL3Checksum
-
struct _netc_enetc_cap
- #include <fsl_netc_hw_enetc.h>
ENETC capability.
Public Members
-
bool funcSafety
Support for safety capability.
-
bool wol
Support for Wake-on-LAN in low-power mode.
-
bool rss
Support for RSS.
-
bool tsd
Support for time specific departure.
-
bool rfs
Support for RFS.
-
uint32_t ipvNum
IPV number.
-
uint32_t vsiNum
VSI number.
-
uint32_t msixNum
MSIX table vector/entry number.
-
uint32_t tcsNum
Traffic class number.
-
uint16_t uchNum
Unicast hash entry number.
-
uint16_t mchNum
Multicast hash entry number.
-
uint16_t rxBdrNum
Rx BD ring number.
-
uint16_t txBdrNum
Tx BD ring number.
-
bool funcSafety
-
struct custEtype
Public Members
-
uint16_t etype
Custom Ethertype value. Upon detecting this ether type the associated code point will be mapped to the parse summary as a Non IP code point.
-
bool en
Enables the detection and mapping.
-
uint8_t cp
This value is mapped to the parse summary as a Non IP code point.
-
uint16_t etype
Hardware Port
-
enum _netc_port_tgsl_status
Port time gate scheduling gate list status.
Values:
-
enumerator kNETC_OperListActive
Port operational gate control list is active.
-
enumerator kNETC_AdminListPending
Administrative gate control list is pending (configured but not installed yet).
-
enumerator kNETC_OperListActive
-
enum _netc_port_discard_tpye
Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function.
Values:
-
enumerator kNETC_RxDiscard
Discarded frames in the receive port datapath processing pipeline.
-
enumerator kNETC_TxDiscard
Discarded frames in the egress datapath processing pipeline, only for switch.
-
enumerator kNETC_BridgeDiscard
Discarded frames in the bridge forwarding processing function, only for switch.
-
enumerator kNETC_RxDiscard
-
enum _netc_port_tpidlist
Defines Port TPID acceptance.
Values:
-
enumerator kNETC_OuterStanCvlan
Accept outer Standard C-VLAN 0x8100.
-
enumerator kNETC_OuterStanSvlan
Accept outer Standard S-VLAN 0x88A8.
-
enumerator kNETC_OuterCustomVlan1
Accept outer Custom VLAN as defined by CVLANR1[ETYPE].
-
enumerator kNETC_OuterCustomVlan2
Accept outer Custom VLAN as defined by CVLANR2[ETYPE].
-
enumerator kNETC_InnerStanCvlan
Accept inner Standard C-VLAN 0x8100.
-
enumerator kNETC_InnerStanSvlan
Accept inner Standard S-VLAN 0x88A8.
-
enumerator kNETC_InnerCustomVlan1
Accept inner Custom VLAN as defined by CVLANR1[ETYPE].
-
enumerator kNETC_InnerCustomVlan2
Accept inner Custom VLAN as defined by CVLANR2[ETYPE].
-
enumerator kNETC_OuterStanCvlan
-
enum _netc_port_ts_select
Defines port timestamp selection.
Values:
-
enumerator kNETC_SyncTime
Synchronized time.
-
enumerator kNETC_FreeRunningTime
Free running time.
-
enumerator kNETC_SyncTime
-
enum _netc_hw_preemption_mode
Port MAC preemption mode.
Values:
-
enumerator kNETC_PreemptDisable
Frame preemption is not enabled
-
enumerator kNETC_PreemptOn64B
Frame preemption is enabled, but transmit only preempts frames on 64B boundaries
-
enumerator kNETC_PreemptOn4B
Frame preemption is enabled, but transmit only preempts frames on 4B boundaries
-
enumerator kNETC_PreemptDisable
-
enum _netc_tc_sdu_type
Type of PDU/SDU (Protocol/Service Data Unit).
Note
Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:
PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes
MPDU = add rxMacsecBco/txMacsecBco bytes
MSDU = minus 16B (12B MAC Header + 4B FCS)
Values:
-
enumerator kNETC_PDU
Physical Layer PDU, Preamble, IFG, SFD along with MPDU. Not supported if cut-through frames are expected
-
enumerator kNETC_MPDU
MAC PDU, MAC Header, MSDU and FCS
-
enumerator kNETC_MSDU
MAC SDU, MPDU minus 12B MAC Header and 4B FCS. Not supported if cut-through frames are expected
-
enum _netc_port_sg_ogc_mode
Defines the Port’s Stream Gate Open Gate Check mode.
Values:
-
enumerator kNETC_SGCheckSFD
Check whether frame SFD is within the open gate interval.
-
enumerator kNETC_SGCheckEntire
Check whether the entire frame is within the open gate interval.
-
enumerator kNETC_SGCheckSFD
-
enum _netc_port_intr_flags
Values:
-
enumerator kNETC_TxEmptyFlag
Tx FIFO empty flag.
-
enumerator kNETC_RxEmptyFlag
Rx FIFO empty flag.
-
enumerator kNETC_TxOverflowFlag
Tx overflow flag.
-
enumerator kNETC_TxUnderflowFlag
Tx underflow flag.
-
enumerator kNETC_RxOverflowFlag
Rx overflow flag.
-
enumerator kNETC_MagicPacketFlag
Magic packet detection indication flag.
-
enumerator kNETC_TxClkStopFlag
Tx clock stop detection flag.
-
enumerator kNETC_RxClkStopFlag
Rx clock stop detection flag.
-
enumerator kNETC_SpeedDuplexChangeFlag
Speed/Duplex Change flag
-
enumerator kNETC_MacMergeSMDErrFlag
MAC merge frame SMD error received event flag
-
enumerator kNETC_MacMergeAssemblyErrFlag
MAC merge frame assembly error event flag
-
enumerator kNETC_TxEmptyFlag
-
enum _netc_port_loopback_mode_t
Defines the port MAC frame loopback mode.
Values:
-
enumerator kNETC_PortLpbWithExtTxClk
Port MAC frame loopback with external Tx clock.
-
enumerator kNETC_PortLpbWithIntTxClk
Port MAC frame loopback with internal Tx clock.
-
enumerator kNETC_PortLpbWithExtTxClk
-
typedef enum _netc_port_tgsl_status netc_port_tgsl_status_t
Port time gate scheduling gate list status.
-
typedef enum _netc_port_discard_tpye netc_port_discard_tpye_t
Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function.
-
typedef enum _netc_port_tpidlist netc_port_tpidlist_t
Defines Port TPID acceptance.
-
typedef enum _netc_port_ts_select netc_port_ts_select_t
Defines port timestamp selection.
-
typedef struct _netc_port_qos_mode netc_port_qos_mode_t
Port Qos mode.
-
typedef struct _netc_port_parser_config netc_port_parser_config_t
Port Parser config.
-
typedef struct _netc_port_tg_config netc_port_tg_config_t
Port time gate config.
-
typedef enum _netc_hw_preemption_mode netc_hw_preemption_mode_t
Port MAC preemption mode.
-
typedef struct _netc_port_tc_cbs_config netc_port_tc_cbs_config_t
Configuration for the Credit Based Shaped for port TC.
Note
The 802.1Qav bandwidth availability parameters is is calculated as follows:
idleSlope (bits) = portTxRate * bwWeight / 100
sendSlope (bits) = portTxRate * (100 - bwWeight) / 100
lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100
hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.
hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits)
-
typedef enum _netc_tc_sdu_type netc_tc_sdu_type_t
Type of PDU/SDU (Protocol/Service Data Unit).
Note
Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:
PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes
MPDU = add rxMacsecBco/txMacsecBco bytes
MSDU = minus 16B (12B MAC Header + 4B FCS)
-
typedef struct _netc_port_tc_sdu_config netc_port_tc_sdu_config_t
-
typedef struct _netc_port_tx_tc_config netc_port_tx_tc_config_t
Configuration for the port Tx Traffic Class.
-
typedef struct _netc_port_discard_statistic netc_port_discard_statistic_t
Switch or ENETC port Tx/Rx/Bridge discard statistic / reason.
-
typedef struct _netc_port_vlan_classify_config netc_port_vlan_classify_config_t
Port accepted Vlan classification config.
-
typedef struct _netc_port_qos_classify_configs netc_port_qos_classify_config_t
Port Qos Classification Config.
-
typedef struct _netc_port_ipf_config_t netc_port_ipf_config_t
Port Ingress Filter Config.
-
typedef struct _netc_port_psfp_isi_config netc_port_psfp_isi_config
PSFP port config.
Port ingress stream identification config
Note
The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows
RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID
RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID
RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID
-
typedef struct _netc_port_ethmac netc_port_ethmac_t
-
typedef enum _netc_port_sg_ogc_mode netc_port_sg_ogc_mode_t
Defines the Port’s Stream Gate Open Gate Check mode.
-
typedef struct _netc_port_common netc_port_common_t
Port common configuration.
-
typedef enum _netc_port_intr_flags netc_port_intr_flags_t
-
typedef enum _netc_port_loopback_mode_t netc_port_loopback_mode_t
Defines the port MAC frame loopback mode.
-
status_t NETC_PortConfig(NETC_PORT_Type *base, const netc_port_common_t *config)
Configure specified PORT.
- Parameters:
base – NETC port module base address.
config – Port configuration structure.
- Returns:
status_t
-
void NETC_PortSetMacAddr(NETC_PORT_Type *base, const uint8_t *macAddr)
Set the MAC address.
- Parameters:
handle –
macAddr –
-
bool NETC_PortIsPseudo(NETC_PORT_Type *base)
Check whether this port a pseudo MAC port.
- Parameters:
base – PORT peripheral base address.
-
void NETC_PortGetDiscardStatistic(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, netc_port_discard_statistic_t *statistic)
Get specified PORT discard counter.
- Parameters:
base – NETC port module base address.
discardType – Port discard type.
statistic – pointer to the statistic data
-
void NETC_PortClearDiscardReason(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, uint32_t reason0, uint32_t reason1)
Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.
- Parameters:
base – NETC port module base address.
discardType – Port discard type.
reason0 –
reason1 –
-
static inline uint32_t NETC_PortGetTGSListStatus(NETC_PORT_Type *base)
Get port time gate scheduling gate list status.
- Parameters:
base – NETC port module base address.
- Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t
-
void NETC_PortEthMacGracefulStop(NETC_PORT_Type *base)
Do graceful stop for Port Ethernet MAC receive/transmit.
- Parameters:
base – NETC port module base address.
-
static inline void NETC_PortSetSpeed(NETC_PORT_Type *base, uint16_t pSpeed)
Set port speed.
- Parameters:
base – NETC port module base address.
pSpeed – Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable.
-
NETC_PORT_MIN_FRAME_SIZE
The port supported minimum/maximum frame size.
-
NETC_PORT_MAX_FRAME_SIZE
-
struct _netc_port_qos_mode
- #include <fsl_netc.h>
Port Qos mode.
Public Members
-
uint8_t qosVlanMap
Transmit QoS to VLAN PCP Mapping Profile index, only active on switch port
-
uint8_t vlanQosMap
Receive VLAN PCP/DE to QoS Mapping Profile index, only active on switch port
-
uint8_t defaultIpv
Port default IPV
-
uint8_t defaultDr
Port default DR
-
bool enVlanInfo
Enable use VLAN info to determine IPV and DR (base on VLANIPVMPaR0/1 and VLANDRMPaR)
-
bool vlanTagSelect
True: Outer VLAN, False: Innner VLAN. Active when enVlanInfo is true
-
uint8_t qosVlanMap
-
struct _netc_port_parser_config
- #include <fsl_netc.h>
Port Parser config.
Public Members
-
uint8_t l2PloadCount
L2 payload fields size in bytes
-
bool enableL3Parser
Enable/Disable parser for L3
-
uint8_t l3PayloadCount
L3 payload fields size in bytes
-
bool enableL4Parser
Enable/Disable parser for L4
-
uint8_t l4PayloadCount
L4 payload fields size in bytes
-
uint8_t l2PloadCount
-
struct _netc_port_tg_config
- #include <fsl_netc.h>
Port time gate config.
Public Members
-
uint16_t advOffset
Advance time offset in ns.
-
uint32_t holdSkew
Hold-Skew in ns, not effective on ports connected to a pseudo-MAC
-
uint16_t advOffset
-
struct _netc_port_tc_cbs_config
- #include <fsl_netc.h>
Configuration for the Credit Based Shaped for port TC.
Note
The 802.1Qav bandwidth availability parameters is is calculated as follows:
idleSlope (bits) = portTxRate * bwWeight / 100
sendSlope (bits) = portTxRate * (100 - bwWeight) / 100
lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100
hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.
hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits)
Public Members
-
uint8_t bwWeight
Percentage units of the port transmit rate and the credit-based shaper (range from 0 ~ 100), the sum of all traffic class credit-based shaper’s bandwidth cannot exceed 100
-
uint32_t hiCredit
The maximum allowed accumulation of credits when conflicting transfers occur, in credit units ((enetClockFrequency / portTxRate) * 100)
-
struct _netc_port_tc_sdu_config
- #include <fsl_netc.h>
Public Members
-
bool enTxMaxSduCheck
Enable Tx Max SDU check for Store and Forward frames, the frame which greater than maxSduSized wiil be discarded, Cut-Through frames will always perform Max SDU check
-
netc_tc_sdu_type_t sduType
Specifies the type of PDU/SDU whose length is being validated as seen on the link
-
uint16_t maxSduSized
Transmit Maximum SDU size in bytes, the dequeued frame will be discarded when it SDU size exceeds this value
-
bool enTxMaxSduCheck
-
struct _netc_port_tx_tc_config
- #include <fsl_netc.h>
Configuration for the port Tx Traffic Class.
Public Members
-
bool enPreemption
Frames from traffic class are transmitted on the preemptable MAC, not supported on internal port (ENETC 1 port and Switch port 4)
-
bool enTcGate
Enable the traffic class gate when no gate control list is operational, or when time gate scheduling is disabled.
-
bool enableTsd
Enable Time Specific Departure traffic class, only applicable to ENETC
-
bool enableCbs
Enable Credit based shaper for traffic class
-
netc_port_tc_cbs_config_t cbsCfg
Configure transmit traffic class credit based shaper (PTC0CBSR0/PTC0CBSR1) if enableCbs set to ture
-
bool enPreemption
-
struct _netc_port_discard_statistic
- #include <fsl_netc.h>
Switch or ENETC port Tx/Rx/Bridge discard statistic / reason.
Public Members
-
uint32_t count
Count of discarded frames. PRXDCR, PTXDCR or BPDCR.
-
uint32_t reason0
Discard Reason. Find bit detail from PT/RXDCRR0 or BPDCRR0.
-
uint32_t reason1
Discard Reason. Find bit detail from PT/RXDCRR1 or BPDCRR1.
-
uint32_t count
-
struct _netc_port_vlan_classify_config
- #include <fsl_netc.h>
Port accepted Vlan classification config.
Public Members
-
uint8_t innerMask
Bitmap identifying which TPIDs are acceptable as Inner VLAN tag. See PTAR
-
uint8_t outerMask
Bitmap identifying which TPIDs are acceptable as Outter VLAN tag. See PTAR
-
uint8_t innerMask
-
struct _netc_port_qos_classify_configs
- #include <fsl_netc.h>
Port Qos Classification Config.
Public Members
-
uint8_t vlanQosMap
Receive VLAN PCP/DE to QoS Mapping Profile index
-
uint8_t defaultIpv
Port default IPV
-
uint8_t defaultDr
Port default DR
-
bool enVlanInfo
Enable use VLAN info to determine IPV and DR ,base on VLAN to IPV map (VLANIPVMPaR0/1) and VLAN to DR map (VLANDRMPaR)
-
bool vlanTagSelect
True: Use received Outer VLAN, False: Use received Innner VLAN. Active when enVlanInfo is true
-
uint8_t vlanQosMap
-
struct _netc_port_ipf_config_t
- #include <fsl_netc.h>
Port Ingress Filter Config.
Public Members
-
bool enL2Dos
Enable port L2 Ethernet DoS Protection
-
bool enL3Dos
Enable port L3 IP DoS Protection
-
bool enIPFTable
Enable port IPF lookup
-
bool enL2Dos
-
struct _netc_port_psfp_isi_config
- #include <fsl_netc.h>
PSFP port config.
Port ingress stream identification config
Note
The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows
RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID
RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID
RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID
Public Members
-
uint16_t defaultISEID
Default Ingress Stream Entry ID, has lower precedence value than ISI entry and IPF entry defined IS_EID. 0xFFFF means NULL
-
bool enKC1
Enable do the second stream identification with key construction rule 1 or rule 3
-
bool enKC0
Enable do the first stream identification with key construction rule 0 or rule 2
-
bool kcPair
Indicates which Key Construction pair to use for this port, false - user pair0. true - use pair1 only applicable for Switch
-
struct _netc_port_ethmac
- #include <fsl_netc.h>
Public Members
-
bool enableRevMii
Enable RevMII mode.
-
netc_port_ts_select_t txTsSelect
Tx timestamp clock source.
-
bool isTsPointPhy
True: Timestamp is captured based on PHY SFD detect pulse on Rx and Tx for 2-step timestamping. False: Based on SFD detect at boundary of MAC merge layer and pins/protocol gaskets.
-
netc_hw_mii_mode_t miiMode
MII mode.
-
netc_hw_mii_speed_t miiSpeed
MII Speed.
-
netc_hw_mii_duplex_t miiDuplex
MII duplex.
-
bool enTxPad
Enable ETH MAC Tx Padding, which will pad the frame to a minimum of 60 bytes and append 4 octets of FCS.
-
uint8_t rxMinFrameSize
Receive Minimum Frame Length size in bytes, range in 18 ~ 64, received frames shorter than 18B are discarded silently. Both for express MAC and preemptable MAC.
-
uint16_t rxMaxFrameSize
Receive Maximum Frame Length size in bytes, up to 2000, received frames that exceed this stated maximum are truncated. Both for express MAC and preemptable MAC.
-
bool enMergeVerify
Enable verify the merged preemption frame, need to enable when preemptMode is not zero
-
uint8_t mergeVerifyTime
The nominal wait time between verification attempts in milliseconds, range in 1 ~ 128
-
netc_hw_preemption_mode_t preemptMode
When set to not zero, PMAC frames may be preempted by EMAC frames
-
bool rgmiiClkStop
True: RGMII transmit clock is stoppable during low power idle. False: It’s not stoppable.
-
bool enableHalfDuplexFlowCtrl
Enable/Disable half-duplex flow control.
-
uint16_t maxBackPressOn
Maximum amount of time backpressure can stay asserted before stopping to prevent excess defer on link partner, in byte times.
-
uint16_t minBackPressOff
Minimum amount of time backpressure will stay off after reaching the ON max, before backpressure can reassert after checking if icm_pause_notification is still or again asserted, in byte times.
-
uint32_t txWakeupTimeCycleEEE
Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) required by the PHY to wait before transmitting a new frame after the application has indicated it wants to end the low power state.
-
uint32_t txSleepTimeCycleEEE
Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) where Tx is idle before mac transmits low power EEE. A value of 0 does not activate low power EEE transmission.
-
bool enableRevMii
-
struct _netc_port_common
- #include <fsl_netc.h>
Port common configuration.
Public Members
-
netc_port_vlan_classify_config_t acceptTpid
Port acceptable VLAN tpid configure.
-
netc_port_ts_select_t rxTsSelect
Eth MAC Rx or pseudo MAC Tx timestamp clock source
-
uint16_t pSpeed
Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable
-
uint8_t rxMacsecBco
Port receive MACSec byte count overhead which due to MACSec encapsulation
-
uint8_t rxPpduBco
Port receive PPDU Byte count overhead which includes IPG, SFD and Preamble
-
uint8_t txMacsecBco
Port transmit MACSec byte count overhead which due to MACSec encapsulation
-
uint8_t txPpduBco
Port transmit PPDU Byte count overhead which includes IPG, SFD and Preamble
-
netc_port_sg_ogc_mode_t ogcMode
Stream Gate Open Gate Check mode, 0b is check whether SFD is within the open gate interval, 1b is check whether the entire frame is within the open gate interval
-
uint32_t pDelay
Link propagation delay in ns
-
uint8_t macAddr[6]
Port MAC address, used for Switch egress frame modification action or ENETC SI0 primary MAC address
-
netc_port_qos_classify_config_t qosMode
Port Rx Qos Classification config
-
netc_port_ipf_config_t ipfCfg
Port ingress port filter configuration
-
netc_port_tg_config_t timeGate
Port Tx time gate config
-
netc_port_parser_config_t parser
Port Rx Parser config
-
netc_port_vlan_classify_config_t acceptTpid
Hardware Port MAC
-
enum _netc_port_phy_mac_type
Defines the Ethernet MAC physical port type.
Values:
-
enumerator kNETC_ExpressMAC
The MAC which handles express traffic when frame preemption is enabled or handles all traffic when frame preemption is disabled.
-
enumerator kNETC_PreemptableMAC
The MAC which handles preemptive traffic when frame preemption is enabled.
-
enumerator kNETC_ExpressMAC
-
enum _netc_port_preemption_verify_status
Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016.
Values:
-
enumerator kNETC_VerifyDisable
Verification is disabled
-
enumerator kNETC_VerifyInProgress
Verification is in progress
-
enumerator kNETC_VerifySuccess
Verification was successful
-
enumerator kNETC_VerifyFaile
Verification failed
-
enumerator kNETC_VerifyUndefined
Verification is in an undefined state
-
enumerator kNETC_VerifyDisable
-
typedef enum _netc_port_phy_mac_type netc_port_phy_mac_type_t
Defines the Ethernet MAC physical port type.
-
typedef enum _netc_port_preemption_verify_status netc_port_preemption_verify_status_t
Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016.
-
typedef struct _netc_port_phy_mac_preemption_status netc_port_phy_mac_preemption_status_t
Port MAC preemption Status.
-
typedef struct _netc_port_phy_mac_traffic_statistic netc_port_phy_mac_traffic_statistic_t
Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.
-
typedef struct _netc_port_phy_mac_discard_statistic netc_port_phy_mac_discard_statistic_t
Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.
-
typedef struct _netc_port_phy_mac_preemption_statistic netc_port_phy_mac_preemption_statistic_t
Ethernet physical MAC port preemption (Tx/Rx) related statistics counters.
-
typedef struct _netc_port_pseudo_mac_traffic_statistic netc_port_pseudo_mac_traffic_statistic_t
Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters.
-
uint32_t NETC_GetPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType)
Get port MAC interrupt flags.
- Parameters:
base – NETC ETH link base register.
mac – MAC type.
-
void NETC_ClearPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask)
Clear port MAC interrupt flags.
- Parameters:
base – NETC ETH link base register.
mac – MAC type.
mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask.
-
void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask, bool enable)
Enable/Disable port MAC interrupts.
- Parameters:
base – NETC ETH link base register.
mac – MAC type.
mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask.
enable – Enable/Disable interrupts.
-
status_t NETC_PortEnableLoopback(NETC_ETH_LINK_Type *base, netc_port_loopback_mode_t loopMode, bool enable)
Enable/Disable Loopback for specified MAC.
- Parameters:
base –
loopMode –
enable –
- Returns:
status_t
-
static inline netc_hw_mii_mode_t NETC_PortGetMIIMode(NETC_ETH_LINK_Type *base)
Get ethernet MAC port MII mode.
- Parameters:
base – Ethernet MAC port peripheral base address.
- Returns:
netc_hw_mii_mode_t
-
status_t NETC_PortSetMII(NETC_ETH_LINK_Type *base, netc_hw_mii_mode_t miiMode, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)
Configure ethernet MAC interface mode, speed and duplex for specified PORT.
- Parameters:
base – Ethernet MAC port peripheral base address.
miiMode – The Ethernet MAC MII mode.
speed – The Ethernet MAC speed.
duplex – The Ethernet MAC duplex.
- Returns:
status_t
-
status_t NETC_PortSetMaxFrameSize(NETC_ETH_LINK_Type *base, uint16_t size)
Set the maximum supported received frame size.
- Parameters:
base – Ethernet MAC port peripheral base address.
size – Maximum frame size to set.
- Returns:
status_t
-
status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_t *config)
Configure ethernet MAC for specified PORT. Set the MII mode, speed/duplex, reverse mode, etc.
- Parameters:
base – Ethernet MAC port peripheral base address.
config – The Ethernet MAC configuration.
- Returns:
status_t
-
static inline void NETC_PortSoftwareResetEthMac(NETC_ETH_LINK_Type *base)
Do software reset for Ethernet MAC.
Note
This can reset all statistic counters.
- Parameters:
base – PORT MAC peripheral base address.
-
static inline void NETC_PortGetPhyMacPreemptionStatus(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_status_t *status)
Get Ethernet MAC preemption status.
- Parameters:
base – PORT MAC peripheral base address.
status – Point to the buffer which store status.
-
void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)
Get Ethernet MAC Tx Traffic Statistics .
- Parameters:
base – PORT MAC peripheral base address.
macType – Express MAC or Preemptable MAC.
status – Point to the buffer which store statistics.
-
void NETC_PortGetPhyMacRxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)
Get Ethernet MAC Rx Traffic Statistics .
- Parameters:
base – PORT MAC peripheral base address.
macType – Express MAC or Preemptable MAC.
status – Point to the buffer which store statistics.
-
void NETC_PortGetPhyMacDiscardStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_discard_statistic_t *statistic)
Get Ethernet MAC Rx/Tx Drops/Errors Statistics .
- Parameters:
base – PORT MAC peripheral base address.
macType – Express MAC or Preemptable MAC.
status – Point to the buffer which store statistics.
-
void NETC_PortGetPhyMacPreemptionStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_statistic_t *statistic)
Get Ethernet Preemptable MAC preemption Statistics .
- Parameters:
base – PORT MAC peripheral base address.
status – Point to the buffer which store statistics.
-
status_t NETC_PortConfigTxIpgPreamble(NETC_ETH_LINK_Type *base, uint8_t preambleCnt, uint8_t ipgLen)
Configure the port MAC flexible preamble and IPG length.
- Parameters:
base – PORT MAC peripheral base address.
preambleCnt – Flexible Preamble Count. Valid values are 1 to 7(default).
ipgLen – Transmit inter-packet gap value. Valid values are 4 to 24(default) with 12 being default.
- Returns:
status_t
-
struct _netc_port_phy_mac_preemption_status
- #include <fsl_netc.h>
Port MAC preemption Status.
Public Members
-
bool mergeActive
Transmit preemption is active or not
-
netc_port_preemption_verify_status_t verifyStatus
Transmit preemption is active or not
-
bool mergeActive
-
struct _netc_port_phy_mac_traffic_statistic
- #include <fsl_netc.h>
Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.
Public Members
-
uint64_t totalOctet
Count of MAC received/transmitted good/error Ethernet octets.
-
uint64_t validOctet
Count of MAC received/transmitted good Ethernet octets.
-
uint64_t pauseFrame
Count of MAC received/transmitted valid PAUSE frames.
-
uint64_t validFrame
Count of MAC received/transmitted valid frames.
-
uint64_t vlanFrame
Count of MAC received/transmitted valid VLAN tagged frames.
-
uint64_t unicastFrame
Count of MAC received/transmitted valid unicast frames.
-
uint64_t multicastFrame
Count of MAC received/transmitted valid multicast frames.
-
uint64_t boradcastFrame
Count of MAC received/transmitted valid broadcast frames.
-
uint64_t totalPacket
Count of MAC received/transmitted good/error packets.
-
uint64_t rxMinPacket
Count of MAC received min to 63-octet packets.
-
uint64_t total64BPacket
Count of MAC received/transmitted 64 octet packets.
-
uint64_t total65To127BPacket
Count of MAC received/transmitted 65 to 127 octet packets.
-
uint64_t total128To255BPacket
Count of MAC received/transmitted 128 to 255 octet packets.
-
uint64_t total256To511BPacket
Count of MAC received/transmitted 256 to 511 octet packets.
-
uint64_t total511To1023BPacket
Count of MAC received/transmitted 512 to 1023 octet packets.
-
uint64_t total1024To1522BPacket
Count of MAC received/transmitted 1024 to 1522 octet packets.
-
uint64_t total1523ToMaxBPacket
Count of MAC received/transmitted 1523 to Max octet packets.
-
uint64_t controlPacket
Count of MAC received/transmitted control packets.
-
uint64_t totalOctet
-
struct _netc_port_phy_mac_discard_statistic
- #include <fsl_netc.h>
Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.
Public Members
-
uint64_t rxError
Count of MAC received error frames.
-
uint64_t rxUndersized
Count of MAC received undersized frames.
-
uint64_t rxOversized
Count of MAC received oversized frames.
-
uint64_t rxErrorFCS
Count of MAC received check sequence (FCS) error frames.
-
uint64_t rxFragment
Count of MAC frames which is shorter than the MIN length and received with a wrong FCS/CRC.
-
uint64_t rxJabber
Count of MAC frames which is larger than the MAX length and received with a wrong FCS/CRC.
-
uint64_t rxDiscard
Count of MAC drops frame.
-
uint64_t rxDiscardNoTruncated
Count of MAC non-truncated drops frame.
-
uint64_t txErrorFCS
Count of MAC transmitted bad FCS frames.
-
uint64_t txUndersized
Count of MAC transmitted less than 64B with good FCS frames.
-
uint64_t rxError
-
struct _netc_port_phy_mac_preemption_statistic
- #include <fsl_netc.h>
Ethernet physical MAC port preemption (Tx/Rx) related statistics counters.
Public Members
-
uint32_t rxReassembledFrame
Count of MAC frames that were successfully reassembled and delivered to the MAC.
-
uint32_t rxReassembledError
Count of MAC frames with reassembly errors.
-
uint32_t rxMPacket
Count of the number of additional mPackets received due to preemption.
-
uint32_t rxSMDError
Count of received MAC frames / MAC frame fragments rejected due to unknown SMD.
-
uint32_t txPreemptionReq
Count of the number of tx preemption HOLD requests.
-
uint32_t txMPacket
Count of the number of additional mPackets transmitted due to preemption.
-
uint32_t rxReassembledFrame
-
struct _netc_port_pseudo_mac_traffic_statistic
- #include <fsl_netc.h>
Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters.
Public Members
-
uint64_t totalOctet
Count of MAC received/transmitted octets.
-
uint64_t unicastFrame
Count of MAC received/transmitted unicast frames.
-
uint64_t multicastFrame
Count of MAC received/transmitted multicast frames.
-
uint64_t boradcastFrame
Count of MAC received/transmitted broadcast frames .
-
uint64_t totalOctet
Hardware Port Rx
-
static inline void NETC_PortSetParser(NETC_PORT_Type *base, const netc_port_parser_config_t *config)
Set port Parser.
- Parameters:
base – PORT peripheral base address.
config – The port Parser configuration.
-
static inline void NETC_PortSetVlanClassify(NETC_PORT_Type *base, const netc_port_vlan_classify_config_t *config)
Set port acceptable VLAN.
- Parameters:
base – PORT peripheral base address.
config – The port acceptable vlan classification configuration.
-
static inline status_t NETC_PortSetQosClassify(NETC_PORT_Type *base, const netc_port_qos_classify_config_t *config)
Set port Qos Classification.
- Parameters:
base – PORT peripheral base address.
config – The port QoS classification configuration.
- Returns:
status_t
-
static inline void NETC_PortSetIPF(NETC_PORT_Type *base, const netc_port_ipf_config_t *config)
Set port ingress filter.
- Parameters:
base – PORT peripheral base address.
config – The port ingress filter configuration.
-
static inline void NETC_PortSetISI(NETC_PORT_Type *base, const netc_port_psfp_isi_config *config)
Set port Ingress stream identification.
- Parameters:
base – PORT peripheral base address.
config – The port Ingress stream identification configuration.
Hardware Port Tx
-
static inline status_t NETC_PortConfigTGS(NETC_PORT_Type *base, const netc_port_tg_config_t *config)
Configure the port time gating Scheduling.
- Parameters:
base –
config –
- Returns:
status_t
-
status_t NETC_PortConfigTcCBS(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_cbs_config_t *config)
Config the Credit-Based Shaper (CBS) for specified Port Traffic Class.
- Parameters:
base –
tcIdx –
config –
- Returns:
status_t
-
static inline status_t NETC_PortConfigTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_sdu_config_t *config)
Config the max Transmit max SDU for specified Port Traffic Class.
- Parameters:
base –
tcIdx –
config –
- Returns:
status_t
-
static inline status_t NETC_PortGetTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, netc_port_tc_sdu_config_t *config)
Read the max Transmit max SDU for specified Port Traffic Class.
- Parameters:
base –
tcIdx –
config –
- Returns:
status_t
Hardware Station Interface(SI)
-
NETC_SI_TXDESCRIP_RD_FL(n)
Defines for read format.
-
NETC_SI_TXDESCRIP_RD_TSE_MASK
-
NETC_SI_TXDESCRIP_RD_TXSTART(n)
-
NETC_SI_TXDESCRIP_RD_L3START(n)
-
NETC_SI_TXDESCRIP_RD_IPCS(n)
-
NETC_SI_TXDESCRIP_RD_L3HDRSIZE(n)
-
NETC_SI_TXDESCRIP_RD_L3T(n)
-
NETC_SI_TXDESCRIP_RD_L4T(n)
-
NETC_SI_TXDESCRIP_RD_L4CS(n)
-
NETC_SI_TXDESCRIP_RD_LSO(n)
-
NETC_SI_TXDESCRIP_RD_LSO_MASK
-
enum _netc_hw_enetc_si_vlan_type
VLAN Ethertypes.
Values:
-
enumerator kNETC_ENETC_StanCVlan
Standard C-VLAN 0x8100.
-
enumerator kNETC_ENETC_StanSVlan
Standard S-VLAN 0x88A8.
-
enumerator kNETC_ENETC_CustomVlan1
Custom VLAN as defined by CVLANR1[ETYPE].
-
enumerator kNETC_ENETC_CustomVlan2
Custom VLAN as defined by CVLANR2[ETYPE].
-
enumerator kNETC_ENETC_StanCVlan
-
enum _netc_hw_enetc_si_rxr_group
SI receive BD ring group index.
Values:
-
enumerator kNETC_SiBDRGroupOne
SI Rx BD ring group index one.
-
enumerator kNETC_SiBDRGroupTwo
SI Rx BD ring group index two.
-
enumerator kNETC_SiBDRGroupOne
-
enum _netc_tx_bdr_flags
Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation.
Values:
-
enumerator kNETC_TxBDRSystemBusErrorFlag
-
enumerator kNETC_TxBDRBusyFlag
-
enumerator kNETC_TxBDRStatusFlagsMask
-
enumerator kNETC_TxBDRSystemBusErrorFlag
-
enum _netc_rx_bdr_flags
Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation.
Values:
-
enumerator kNETC_RxBDRSystemBusErrorFlag
-
enumerator kNETC_RxBDREmptyFlag
-
enumerator kNETC_RxBDRSystemBusErrorFlag
-
enum _netc_psi_msg_flags_t
PSI message interrupt type.
Values:
-
enumerator kNETC_PsiRxMsgFromVsi1Flag
Message receive interrupt enable, initiated by VSI1.
-
enumerator kNETC_PsiRxMsgFromVsi2Flag
Message receive interrupt enable, initiated by VSI2.
-
enumerator kNETC_PsiFLRFromVsi1Flag
Function level reset interrupt enable, initiated by VSI1.
-
enumerator kNETC_PsiRxMsgFromVsi1Flag
-
enum _netc_vsi_msg_flags
VSI message interrupt flags.
Values:
-
enumerator kNETC_VsiMsgTxFlag
Message sent to PSI has completed and response received.
-
enumerator kNETC_VsiMsgRxFlag
Message received from PSI.
-
enumerator kNETC_VsiMsgTxFlag
-
enum _netc_vsi_number
VSI number bit map, VSI1 starts from bit1.
Values:
-
enumerator kNETC_Vsi1
-
enumerator kNETC_Vsi2
-
enumerator kNETC_Vsi1
-
enum _enetc_si_bdr_priority
ENETC Station Interface BD Ring priority enumeration.
Values:
-
enumerator kNETC_SIBdrPriorityLowest
-
enumerator kNETC_SIBdrPriority0
-
enumerator kNETC_SIBdrPriority1
-
enumerator kNETC_SIBdrPriority2
-
enumerator kNETC_SIBdrPriority3
-
enumerator kNETC_SIBdrPriority4
-
enumerator kNETC_SIBdrPriority5
-
enumerator kNETC_SIBdrPriority6
-
enumerator kNETC_SIBdrPriority7
-
enumerator kNETC_SIBdrPriorityHighest
-
enumerator kNETC_SIBdrPriorityLowest
-
typedef enum _netc_hw_enetc_si_vlan_type netc_hw_enetc_si_vlan_type
VLAN Ethertypes.
-
typedef enum _netc_hw_enetc_si_rxr_group netc_hw_enetc_si_rxr_group
SI receive BD ring group index.
-
typedef struct _netc_hw_enetc_si_config netc_hw_enetc_si_config_t
Station Interface configuration.
-
typedef struct _netc_si_l2mf_config netc_si_l2mf_config_t
L2 Mac Filter Configuration for SI.
-
typedef struct _netc_si_l2vf_config netc_si_l2vf_config_t
L2 VLAN Filter Configuration for SI.
-
typedef struct _netc_si_discard_statistic netc_si_discard_statistic_t
SI frame drop statistic struct.
-
typedef struct _netc_si_traffic_statistic netc_si_traffic_statistic_t
SI traffic statistic struct.
-
typedef struct _netc_si_config netc_si_config_t
SI Configuration.
-
typedef union _netc_tx_bd netc_tx_bd_t
Transmit Buffer Descriptor format.
A union type cover the BD used as Standard/Extended/WriteBack format.
-
typedef union _netc_rx_bd netc_rx_bd_t
Receive Buffer Descriptor format.
-
typedef struct _netc_tx_bdr_config netc_tx_bdr_config_t
Configuration for the SI Tx Buffer Descriptor Ring Configuration.
-
typedef struct _netc_tx_bdr netc_tx_bdr_t
Transmit BD ring handler data structure.
-
typedef enum _netc_tx_bdr_flags netc_tx_bdr_flags_t
Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation.
-
typedef struct _netc_rx_bdr_config netc_rx_bdr_config_t
Configuration for the SI Rx Buffer Descriptor Ring Configuration.
-
typedef struct _netc_rx_bdr netc_rx_bdr_t
Receive BD ring handler data structure.
-
typedef enum _netc_rx_bdr_flags netc_rx_bdr_flags_t
Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation.
-
typedef struct _netc_bdr_config netc_bdr_config_t
Configuration for the buffer descriptors ring.
-
typedef enum _netc_psi_msg_flags_t netc_psi_msg_flags_t
PSI message interrupt type.
-
typedef enum _netc_vsi_msg_flags netc_vsi_msg_flags_t
VSI message interrupt flags.
-
typedef enum _netc_vsi_number netc_vsi_number_t
VSI number bit map, VSI1 starts from bit1.
-
typedef struct _netc_psi_rx_msg netc_psi_rx_msg_t
PSI receive message information.
-
typedef struct _netc_vsi_msg_tx_status netc_vsi_msg_tx_status_t
VSI message transmit status.
-
typedef enum _enetc_si_bdr_priority enetc_si_bdr_priority_t
ENETC Station Interface BD Ring priority enumeration.
-
static inline void NETC_SIEnable(ENETC_SI_Type *base, bool enable)
Enable the Station Interface(SI)
- Parameters:
base –
-
static inline void NETC_SIRxRingEnable(ENETC_SI_Type *base, uint8_t ring, bool enable)
Enable the specified Rx BD ring.
- Parameters:
base –
ring – The ring index.
base – Enable/Disable the ring.
-
static inline void NETC_SIEnablePromisc(ENETC_SI_Type *base, netc_packet_type_t type, bool enable)
Enable/Disable unicast/multicast/boardcast promisc mode for specified SI.
- Parameters:
base –
type –
enable –
-
static inline void NETC_SISetTxProducer(ENETC_SI_Type *base, uint8_t ring, uint16_t producer)
Set producer index of specified Tx BD ring.
- Parameters:
base – SI base address.
ring – BD ring index.
producer – The producer index of specified ring.
-
static inline uint16_t NETC_SIGetTxConsumer(ENETC_SI_Type *base, uint8_t ring)
Get consumer index of specified Tx BD ring.
- Parameters:
base – SI base address.
ring – BD ring index.
- Returns:
consumer The consumer index of specified ring.
-
static inline void NETC_SISetRxConsumer(ENETC_SI_Type *base, uint8_t ring, uint16_t consumer)
Set consumer index of specified Rx BD ring.
- Parameters:
base – SI base address.
ring – BD ring index.
consumer – The consumer index of specified ring.
-
static inline uint16_t NETC_SIGetRxProducer(ENETC_SI_Type *base, uint8_t ring)
Get producer index of specified Rx BD ring.
- Parameters:
base – SI base address.
ring – BD ring index.
- Returns:
producer The producer index of specified ring.
-
status_t NETC_SIConfigTxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_tx_bdr_config_t *bdrConfig)
Configure the Transmit Buffer Descriptor Ring for specified SI.
- Parameters:
base – SI base address.
ring – BD ring index.
bdrConfig – The BD ring configuration.
- Returns:
status_t
-
status_t NETC_SIConfigRxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_rx_bdr_config_t *bdrConfig)
Configure the Rx Buffer Descriptor Ring for specified SI.
- Parameters:
base – SI base address.
ring – BD ring index.
bdrConfig – The BD ring configuration.
- Returns:
status_t
-
static inline void NETC_SIMapVlanToIpv(ENETC_SI_Type *base, uint8_t pcpDei, uint8_t ipv)
Enable the mapping of VLAN to IPV.
- Parameters:
base – SI base address.
pcpDei – The VLAN tag pcp dei value (use NETC_VLAN_PCP_DEI_VALUE macro).
ipv – The IPV value for this VLAN mapping.
-
static inline void NETC_SIEnableVlanToIpv(ENETC_SI_Type *base, bool enable)
Enable the mapping of VLAN to IPV.
- Parameters:
base – SI base address.
enable – Whether enable mapping.
- Returns:
status_t
-
static inline void NETC_SIMapIpvToRing(ENETC_SI_Type *base, uint8_t ipv, uint8_t ring)
Set the IPV to ring mapping.
- Parameters:
base – SI base address.
ipv – IPV value to be mapped.
ring – The Rx BD ring index to be mapped.
- Returns:
status_t
-
static inline void NETC_SISetRxBDRGroup(ENETC_SI_Type *base, uint8_t groupNum, uint8_t ringPerGroup)
Set the group of Rx BD ring.
- Parameters:
base – SI base address.
groupNum – Total group number.
ringPerGroup – Rings per group.
- Returns:
status_t
-
static inline void NETC_SISetDefaultRxBDRGroup(ENETC_SI_Type *base, netc_hw_enetc_si_rxr_group groupIdx)
Set the default used receive Rx BD ring group.
Note
The IPV mapped ring index is the relative index inside the default used group.
- Parameters:
base – SI base address.
groupNum – The default Rx group index.
- Returns:
status_t
-
static inline void NETC_SICleanTxIntrFlags(ENETC_SI_Type *base, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)
Clean the SI transmit interrupt flags.
- Parameters:
base – SI base address.
txFrameIntrMask – IPV value to be mapped, bit x represents ring x.
txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x.
-
static inline void NETC_SICleanRxIntrFlags(ENETC_SI_Type *base, uint32_t rxIntrMask)
Clean the SI receive interrupt flags.
- Parameters:
base – SI base address.
rxIntrMask – Rx interrupt bit mask, bit x represents ring x.
-
void NETC_SIPsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)
PSI enables/disables specified interrupt.
- Parameters:
base – SI base address.
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
enable – Enable/Disable the interrupt.
-
static inline uint32_t NETC_SIPsiGetStatus(ENETC_SI_Type *base)
PSI gets interrupt event flag status.
- Parameters:
base – SI base address.
- Returns:
The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
-
static inline void NETC_SIPsiClearStatus(ENETC_SI_Type *base, uint32_t mask)
PSI clears interrupt event flag.
- Parameters:
base – SI base address.
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.
-
status_t NETC_SIPsiSendMsg(ENETC_SI_Type *base, uint16_t msg, netc_vsi_number_t vsi)
PSI sends message to specified VSI(s)
- Parameters:
base – SI base address.
msg – The message to be sent.
vsi – The VSI number.
- Returns:
status_t
-
static inline bool NETC_SIPsiCheckTxBusy(ENETC_SI_Type *base, netc_vsi_number_t vsi)
PSI checks Tx busy flag which should be cleaned when VSI receive the message data.
- Parameters:
base – SI base address.
vsi – The VSI number.
- Returns:
The busy status of specified VSI.
-
status_t NETC_SIPsiSetRxBuffer(ENETC_SI_Type *base, netc_vsi_number_t vsi, uint64_t buffAddr)
PSI sets Rx buffer to receive message from specified VSI.
Note
The buffer memory size should be big enough for the message data from VSI
- Parameters:
base – SI base address.
vsi – The VSI number.
buffAddr – The buffer address to store message data from VSI, must be 64 bytes aligned.
- Returns:
status_t
-
status_t NETC_SIPsiGetRxMsg(ENETC_SI_Type *base, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)
PSI gets Rx message from specified VSI.
- Parameters:
base – SI base address.
vsi – The VSI number.
msgInfo – The Rx message information.
-
void NETC_SIVsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)
Enable VSI interrupt.
- Parameters:
base – SI base address.
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.
enable – Enable/Disable interrupt.
-
static inline uint32_t NETC_SIVsiGetStatus(ENETC_SI_Type *base)
Get VSI interrupt status.
- Parameters:
base – SI base address.
- Returns:
A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together.
-
static inline void NETC_SIVsiClearStatus(ENETC_SI_Type *base, uint32_t mask)
Clear VSI interrupt status.
- Parameters:
base – SI base address.
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.
-
status_t NETC_SIVsiSendMsg(ENETC_SI_Type *base, uint64_t msgAddr, uint32_t msgLen)
VSI sends message to PSI.
- Parameters:
base – SI base address.
msgAddr – Address to store message ready to be sent, must be 64 bytes aligned.
msgLen – The message length, must be 32 bytes aligned.
- Returns:
status_t
-
void NETC_SIVsiCheckTxStatus(ENETC_SI_Type *base, netc_vsi_msg_tx_status_t *status)
Check VSI Tx status.
- Parameters:
base – SI base address.
status – The VSI Tx status structure.
-
status_t NETC_SIVsiReceiveMsg(ENETC_SI_Type *base, uint16_t *msg)
VSI receives message from PSI.
- Parameters:
base – SI base address.
msg – The message from PSI.
- Returns:
status_t
-
void NETC_SIGetDiscardStatistic(ENETC_SI_Type *base, netc_si_discard_statistic_t *statistic)
Get the discard statistic from SI layer.
- Parameters:
base – SI base address.
statistic – The statistic data.
-
void NETC_SIGetTrafficStatistic(ENETC_SI_Type *base, netc_si_traffic_statistic_t *statistic)
Get the traffic statistic from SI layer.
- Parameters:
base – SI base address.
statistic – The statistic data.
-
NETC_VLAN_PCP_DEI_VALUE(pcp, dei)
Macro to cover VLAN PCP, DEI value to internal used pcpDei value.
-
struct _netc_hw_enetc_si_config
- #include <fsl_netc.h>
Station Interface configuration.
Public Members
-
uint32_t bandWeight
Station interface traffic class bandwidth weight
-
uint32_t vlanCtrl
VLAN Ethertypes can be inserted by the SI driver, set with OR of netc_hw_enetc_si_vlan_type.
-
uint32_t antiSpoofEnable
Anti-spoofing enable
-
uint32_t vlanInsertEnable
Software SI-based VLAN Insertion enable, avtive when enSIBaseVlan is true
-
uint32_t vlanExtractEnable
SI-based VLAN removed from frame enable, avtive when enSIBaseVlan is true
-
uint32_t sourcePruneEnable
Source pruning enable
-
uint32_t rxRingUse
Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings.
-
uint32_t txRingUse
Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0.
-
uint32_t valnToIpvEnable
Enable the VLAN PCP/DEI value (use NETC_VLAN_PCP_DEI_VALUE marco) to internal priority value mapping.
-
uint32_t rxBdrGroupNum
Rx BD ring group number, range in 0 ~ 2.
-
uint32_t ringPerBdrGroup
The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero.
-
netc_hw_enetc_si_rxr_group defaultRxBdrGroup
The selected Rx BD ring group, active when rxBdrGroupNum not equal zero.
-
uint8_t vlanToIpvMap[16]
Frame VLAN pcp|dei to IPV mapping, active when valnToIpvEnable is true.
-
uint8_t ipvToRingMap[8]
BD ring used within the default Rx BD ring group for IPV n, active when rxBdrGroupNum not equal zero.
-
uint8_t vsiTcToTC[8]
Maps the VSI traffic class to transmit traffic class, done after the ENETC txPrio to TC mapping, only available for VSI.
-
bool enSIBaseVlan
Enable use SI-based VLAN information.
-
netc_enetc_vlan_tag_t siBaseVlan
SI-based VLAN information, active when enSIBaseVlan is true.
-
uint32_t bandWeight
-
struct _netc_si_l2mf_config
- #include <fsl_netc.h>
L2 Mac Filter Configuration for SI.
Public Members
-
bool macUCPromis
Enable/Disable MAC unicast promiscuous.
-
bool macMCPromis
Enable/Disable MAC multicast promiscuous.
-
bool rejectUC
Reject Unicast.
-
bool rejectMC
Reject Multicast.
-
bool rejectBC
Reject Broadcast.
-
bool macUCPromis
-
struct _netc_si_l2vf_config
- #include <fsl_netc.h>
L2 VLAN Filter Configuration for SI.
Public Members
-
bool acceptUntagged
Accept/Reject untagged frame.
-
bool enPromis
Enable/Disable VLAN promiscuous.
-
bool useOuterVlanTag
Use outer/inner VLAN tag for filtering.
-
bool acceptUntagged
-
struct _netc_si_discard_statistic
- #include <fsl_netc.h>
SI frame drop statistic struct.
Public Members
-
uint32_t programError
Due to programming error ( non-existing BD ring or non-existing group, or SI disabled or BD ring disabled).
-
uint32_t busError
Due to system bus error.
-
uint32_t lackBD[14]
Due to lack of Rx BDs available.
-
uint32_t programError
-
struct _netc_si_traffic_statistic
- #include <fsl_netc.h>
SI traffic statistic struct.
-
struct _netc_si_config
- #include <fsl_netc.h>
SI Configuration.
Public Members
-
uint32_t tcBWWeight
SI traffic class bandwidth weight.
-
uint32_t tcBWWeight
-
union _netc_tx_bd
- #include <fsl_netc.h>
Transmit Buffer Descriptor format.
A union type cover the BD used as Standard/Extended/WriteBack format.
-
union _netc_rx_bd
- #include <fsl_netc.h>
Receive Buffer Descriptor format.
-
struct _netc_tx_bdr_config
- #include <fsl_netc.h>
Configuration for the SI Tx Buffer Descriptor Ring Configuration.
Public Members
-
uint32_t len
Size of BD ring which shall be multiple of 8 BD.
-
netc_tx_bd_t *bdArray
BDR base address which shall be 128 bytes aligned.
-
netc_tx_frame_info_t *dirtyArray
Tx cleanup ring.
-
bool enIntr
Enable/Disable completion interrupt.
-
bool enThresIntr
Enable/Disable threshold interrupt.
-
bool enCoalIntr
Enable/Disable interrupt coalescing.
-
uint32_t intrThreshold
Interrupt coalescing packet threshold.
-
uint32_t intrTimerThres
Interrupt coalescing timer threshold, specified in NETC clock cycles.
-
uint8_t msixEntryIdx
MSIX entry index of Tx ring interrupt.
-
bool isVlanInsert
Enable/Disable VLAN insert offload.
-
bool isUserCRC
Enable/Disable user provided the CRC32 - FCS at end of frame.
-
uint8_t wrrWeight
Weight used for arbitration when rings have same priority.
-
uint8_t priority
Priority of the Tx BDR.
-
uint32_t len
-
struct _netc_tx_bdr
- #include <fsl_netc.h>
Transmit BD ring handler data structure.
Public Members
-
netc_tx_bd_t *bdBase
Tx BDR base address.
-
netc_tx_frame_info_t *dirtyBase
Tx cleanup ring base address.
-
uint16_t producerIndex
Current index for transmit.
-
uint16_t cleanIndex
Current index for tx cleaning.
-
uint32_t len
Length of this BD ring.
-
netc_tx_bd_t *bdBase
-
struct _netc_rx_bdr_config
- #include <fsl_netc.h>
Configuration for the SI Rx Buffer Descriptor Ring Configuration.
Public Members
-
bool extendDescEn
False - Use 16Bytes standard BD. True - Use 32Bytes extended BD.
-
netc_rx_bd_t *bdArray
BD ring base address which shall be 128 bytes aligned.
-
uint32_t len
BD ring length in the unit of 16Bytes standard BD. Shall be multiple of 8/16 for standard/exteneded BD.
-
uint64_t *buffAddrArray
Rx buffers array with BD length(half of BD length if use exteneded BD).
-
uint16_t buffSize
Size of all Rx buffers in this BD ring.
-
bool enThresIntr
Enable/Disable threshold interrupt.
-
bool enCoalIntr
Enable/Disable interrupt coalescing.
-
uint32_t intrThreshold
Interrupt coalescing packet threshold.
-
uint32_t intrTimerThres
Interrupt coalescing timer threshold, specified in NETC clock cycles.
-
uint8_t msixEntryIdx
MSIX entry index of Rx ring interrupt.
-
bool disVlanPresent
Disable/Enable VLAN in BD.
-
bool enVlanExtract
Enable/Disable VLAN extract.
-
bool isKeepCRC
Whether user provided the CRC32 - FCS at end of frame.
-
bool congestionMode
False - lossy. True - lossless.
-
bool enHeaderAlign
Enable/disable +2B alignment to frame.
-
bool extendDescEn
-
struct _netc_rx_bdr
- #include <fsl_netc.h>
Receive BD ring handler data structure.
Public Members
-
netc_rx_bd_t *bdBase
Rx BDR base address.
-
bool extendDesc
Use extended buffer descriptor.
-
uint16_t index
Current index for read.
-
uint32_t len
Length of this BD ring, unit of 16Bytes standard BD.
-
uint64_t *buffArray
Rx buffers array of this ring.
-
uint32_t buffSize
Rx buffers size for all BDs in this ring.
-
netc_rx_bd_t *bdBase
-
struct _netc_bdr_config
- #include <fsl_netc.h>
Configuration for the buffer descriptors ring.
Public Members
-
netc_rx_bdr_config_t *rxBdrConfig
Receive buffer ring configuration array.
-
netc_tx_bdr_config_t *txBdrConfig
Transmit buffer ring configuration array.
-
netc_rx_bdr_config_t *rxBdrConfig
-
struct _netc_psi_rx_msg
- #include <fsl_netc.h>
PSI receive message information.
Public Members
-
uint8_t *msgBuff
The buffer address application set before receiving message.
-
uint32_t msgLen
Received message length.
-
uint8_t *msgBuff
-
struct _netc_vsi_msg_tx_status
- #include <fsl_netc.h>
VSI message transmit status.
Public Members
-
bool txBusy
The VSI Tx busy flag, become idle when the PSI receive and clear the related status.
-
bool isTxErr
Tx error flag.
-
uint16_t msgCode
The error code or user-defined content.
-
bool txBusy
-
struct standard
Public Members
-
uint64_t addr
Address of the buffer. Little Endian.
-
uint16_t bufLen
Length of buffer specifying effective number of bytes.
-
uint16_t frameLen
Length of Frame.
-
uint32_t flags
Flags qualified setting.
-
uint32_t enableInterrupt
Whether enable interrupt on complete of BD.
-
uint32_t isExtended
Extended BD format flag.
-
uint32_t isFinal
Final BD flag.
-
uint64_t addr
-
struct ext
Public Members
-
uint32_t timestamp
IEEE1588 PTP one-step timestamp.
-
uint32_t __pad0__
Ignore 2-bit MSB.
-
uint16_t tpid
VLAN TPID type, see netc_vlan_tpid_select_t.
-
uint16_t vid
VLAN ID.
-
uint16_t dei
VLAN DEI.
-
uint16_t pcp
VLAN PCP.
-
uint8_t eFlags
Tx extension flags.
-
uint8_t isFinal
Final BD flag.
-
uint32_t timestamp
-
struct writeback
Public Members
-
uint32_t timestamp
Timestamp write back.
-
uint32_t status
Status.
-
uint32_t written
Write-back flag.
-
uint32_t timestamp
-
struct standard
Public Members
-
uint64_t addr
Software write address.
-
uint64_t addr
-
struct writeback
Public Members
-
uint16_t internetChecksum
Internet Checksum.
-
uint16_t parserSummary
Parser Summary.
-
uint16_t bufLen
Length of received buffer.
-
uint16_t vid
VLAN ID.
-
uint16_t dei
VLAN DEI.
-
uint16_t pcp
VLAN PCP.
-
uint8_t tpid
VLAN TPID.
-
uint8_t hr
Host Reason.
-
uint8_t flags
Rx information flags.
-
uint8_t error
Rx error code.
-
uint8_t isReady
Received data ready flag.
-
uint8_t isFinal
Final BD flag.
-
uint16_t internetChecksum
-
union __unnamed207__
Public Members
- struct _netc_rx_bd
-
uint32_t rssHashSwt
RSS hash while not used as switch management port.
-
struct __unnamed209__
Public Members
-
uint32_t srcPort
Source port received from switch management port.
-
uint32_t rssHash
RSS Hash high field value.
-
uint32_t srcPort
-
struct ext
Public Members
-
uint32_t timestamp
Rx Timestamp.
-
uint32_t timestamp
Hardware Switch
-
enum _netc_swt_port_bitmap
The switch port bitmap.
Values:
-
enumerator kNETC_SWTPort0Bit
Switch port0 bitmap
-
enumerator kNETC_SWTPort1Bit
Switch port1 bitmap
-
enumerator kNETC_SWTPort2Bit
Switch port2 bitmap
-
enumerator kNETC_SWTPort3Bit
Switch port3 bitmap
-
enumerator kNETC_SWTPort4Bit
Switch port4 (internal port) bitmap
-
enumerator kNETC_SWTPort0Bit
-
enum _netc_swt_imr_dest_port
The switch ingress mirror destination port.
Values:
-
enumerator kNETC_SWTPort0
Switch port0
-
enumerator kNETC_SWTPort1
Switch port1
-
enumerator kNETC_SWTPort2
Switch port2
-
enumerator kNETC_SWTPort3
Switch port3
-
enumerator kNETC_SWTPort4
Switch port4
-
enumerator kNETC_SWTMPort
Switch management port
-
enumerator kNETC_SWTPort0
-
enum _netc_swt_mac_forward_mode
The switch MAC forwarding options.
Values:
-
enumerator kNETC_NoFDBLookUp
No FDB lookup is performed, the frame is flooded.
-
enumerator kNETC_FDBLookUpWithFlood
FDB lookup is performed, and if there is no match, the frame is flooded to the port bitmap in VLAN filter entry.
-
enumerator kNETC_FDBLookUpWithDiscard
FDB lookup is performed, and if there is no match, the frame is discarded.
-
enumerator kNETC_NoFDBLookUp
-
enum _netc_swt_mac_learn_mode
The switch MAC learning options.
Values:
-
enumerator kNETC_DisableMACLearn
Disable MAC learning. SMAC FDB lookup is by-passed.
-
enumerator kNETC_HardwareMACLearn
Hardware MAC learning is enabled.
-
enumerator kNETC_SeSoftwareMACLearn
Software MAC learning secure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is redirected to the switch management port.
-
enumerator kNETC_UnseSoftwareMACLearn
Software MAC learning unsecure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is copied to the switch management port.
-
enumerator kNETC_DisableMACLearnWithSMAC
Disable MAC learning with SMAC validation. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is discarded.
-
enumerator kNETC_DisableMACLearn
-
enum _netc_swt_port_tx_vlan_act
Switch transmit Bridge Port VLAN Tag Action.
Values:
-
enumerator kNETC_NoTxVlanModify
No egress VLAN modification performed
-
enumerator kNETC_TxDelOuterVlan
Delete outer VLAN tag
-
enumerator kNETC_TxReplOuterVlanVid
Replace outer VLAN tag’s VID with 0; frame to be transmitted as a priority tag frame
-
enumerator kNETC_NoTxVlanModify
-
enum _netc_swt_port_stg_mode
Switch port spanning tree group work mode.
Values:
-
enumerator kNETC_DiscardFrame
Tx or RX Frames on this port with current spanning tree group ID will be discarded
-
enumerator kNETC_LearnWithoutFowrad
RX Frames on this port with current spanning tree group ID will do Learn SMAC, but do not forward, Tx Frame will be discarded
-
enumerator kNETC_ForwardFrame
RX Frames on this port with current spanning tree group ID will do both MAC learning and forwarding, , Tx Frame will be forwarded.
-
enumerator kNETC_DiscardFrame
-
typedef enum _netc_swt_port_bitmap netc_swt_port_bitmap_t
The switch port bitmap.
-
typedef enum _netc_swt_imr_dest_port netc_swt_imr_dest_port_t
The switch ingress mirror destination port.
-
typedef enum _netc_swt_mac_forward_mode netc_swt_mac_forward_mode_t
The switch MAC forwarding options.
-
typedef enum _netc_swt_mac_learn_mode netc_swt_mac_learn_mode_t
The switch MAC learning options.
-
typedef enum _netc_swt_port_tx_vlan_act netc_swt_port_tx_vlan_act_t
Switch transmit Bridge Port VLAN Tag Action.
-
typedef enum _netc_swt_port_stg_mode netc_swt_port_stg_mode_t
Switch port spanning tree group work mode.
-
typedef struct _etc_swt_imr_config netc_swt_imr_config_t
Switch Ingress mirror destination config.
-
typedef struct _netc_swt_port_config netc_swt_port_bridge_config_t
Switch port bridge configuration.
-
typedef struct _netc_swt_port_fm_config netc_swt_port_fm_config_t
Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP])
-
typedef struct _netc_swt_default_vlan_filter netc_swt_default_vlan_filter_t
Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup.
-
typedef struct _netc_swt_bridge_config netc_swt_bridge_config_t
Bridge config.
-
typedef struct _netc_swt_psfp_config netc_swt_psfp_config_t
Switch PSFP configuration.
-
typedef struct _netc_qos_classify_config netc_swt_qos_classify_config_t
Switch Qos Classification configuration (include two profiles)
-
typedef struct _netc_swt_qos_to_vlan_config netc_swt_qos_to_vlan_config_t
Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag.
-
typedef struct _netc_switch_inuse_fdb_statistic netc_switch_inuse_fdb_statistic_t
Switch static/dynamic FDB entries in-use statistic.
-
struct _etc_swt_imr_config
- #include <fsl_netc.h>
Switch Ingress mirror destination config.
Public Members
-
bool enMirror
Enable ingress mirroring
-
netc_swt_imr_dest_port_t destPort
Port where ingress mirrored frames are sent
-
uint8_t dr
Mirrored packet’s DR (drop resilience)
-
uint8_t ipv
Mirrored packet’s IPV (internal priority value)
-
uint8_t efmLengthChange
Egress Frame Modification Frame Length change in 2s complement notation, Vaild if efmEntryID is noy null
-
uint16_t efmEntryID
Egress Frame Modification Entry Id, note 0xFFFF is a Null Frame Modification Entry, Only applicable if destPort != kNETC_SWTMPort
-
bool enMirror
-
struct _netc_swt_port_config
- #include <fsl_netc.h>
Switch port bridge configuration.
Public Members
-
netc_swt_port_tx_vlan_act_t txVlanAction
Only applies for the frame outer VLAN tag’s VID is equal to the port default VID
-
bool isRxVlanAware
Receive VLAN Aware Mode
-
bool acceptUntag
Accept untagged frame
-
bool acceptPriorityTag
Accept priority tagged frame (VID = 0)
-
bool acceptSingleTag
Accept single tagged frame
-
bool acceptDoubleTag
Accept double tagged frame (ounter and inner)
-
bool enSrcPortPrun
Enable/Disable received frame be transmitted to same port it was received
-
bool enMacStationMove
Enable/Disable received frame which ingress port not match the FDB entry Destination Port Bitmap
-
bool enBcastStormCtrl
Enable/Disable Storm control for broadcast frames
-
bool enMcastStormCtrl
Enable/Disable Storm control for multicast frames
-
bool enUnMcastStormCtrl
Enable/Disable Storm control for unknown multicast frames
-
bool enUnUcastStormCtrl
Enable/Disable Storm control for unknown unicast frames
-
uint32_t bcastRpEntryID
Broadcast rate policer entry ID. Valid if enBroadStormCtrl = true
-
uint32_t mcastEntryID
Known multicast rate policer entry ID. Valid if enBroadStormCtrl = true
-
uint32_t unMcastRpEntryID
Unknown multicast policer entry ID. Valid if enUnMultiStormCtrl = true
-
uint32_t unUcastRpEntryID
Unknown unicast rate policer entry ID. Valid if enUnUniStormCtrl = true
-
uint16_t maxDynaFDBEntry
The maximium number of dynamic entries in the FDB table, 0 means no limit
-
netc_swt_port_tx_vlan_act_t txVlanAction
-
struct _netc_swt_port_fm_config
- #include <fsl_netc.h>
Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP])
Public Members
-
bool ignoreFMMiscfg
Enable/Disable ignore the Frame Modification Misconfiguration Action
-
bool enEgressPcpMap
Enable egress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action
-
bool enIngressPcpMap
Enable ingress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action
-
bool enUpdateVlanDei
Enable update DR value in the outer VLAN based on DEnDEI field, used for egress Frame Modification Outer DEI action
-
uint8_t drToDeiMap
Mapping of internal QoS’s DR value n to VLAN DEI, The 4 bits correspond to the DR3 ~ DR0, and 1 means DRn mapping to DEI 1, 0 means DRn mapping to DEI 0
-
uint8_t egressPcpMap
Egress PCP to PCP Mapping Profile instance, active when enEgressPcpMap is true
-
uint8_t ingressPcpMap
Ingress PCP to PCP Mapping Profile instance, active when enIngressPcpMap is true
-
uint8_t qosVlanMap
Transmit QoS to VLAN PCP Mapping Profile index, used for egress Frame Modification VLAN Add/Replace Action
-
bool ignoreFMMiscfg
-
struct _netc_swt_default_vlan_filter
- #include <fsl_netc.h>
Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup.
Public Members
-
bool enIPMFlood
Enable IP Multicast Flooding
-
bool enIPMFilter
Enable IP Multicast Filtering
-
uint8_t stgID
Spanning Tree Group Member ID, range in 0 ~ 15
-
uint8_t portMembership
The bit 0 ~ 4 correspond to the 5 ports, When bit set (0b1), means the port is a member of this VLAN. Port membership is used for source/destination pruning
-
bool enUseFilterID
Enable use the specified filterID as FID, otherwise will use the frame VID
-
uint16_t filterID
Used as a key value to do FDB table and the L2 IPV4 Multicast Filter table lookup. Valid if enUseFilterID is true
-
netc_swt_mac_forward_mode_t mfo
MAC forwarding options
-
netc_swt_mac_learn_mode_t mlo
MAC learning options
-
uint16_t baseETEID
Base Egress Treatment Entry ID
-
uint8_t etaPortBitmap
Egress Treatment Applicability Port. Valid if baseETEID is not null.
-
bool enIPMFlood
-
struct _netc_swt_bridge_config
- #include <fsl_netc.h>
Bridge config.
Public Members
-
netc_swt_default_vlan_filter_t dVFCfg
Default VLAN filter entry configuration when not found in VLAN filter lookup
-
netc_swt_default_vlan_filter_t dVFCfg
-
struct _netc_swt_psfp_config
- #include <fsl_netc.h>
Switch PSFP configuration.
Public Members
-
netc_isi_kc_rule_t kcRule[4]
Key construction rules
-
netc_isi_kc_rule_t kcRule[4]
-
struct _netc_qos_classify_config
- #include <fsl_netc.h>
Switch Qos Classification configuration (include two profiles)
-
struct _netc_swt_qos_to_vlan_config
- #include <fsl_netc.h>
Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag.
-
struct fsl_netc
- #include <fsl_netc.h>
Public Members
-
uint8_t qos[32]
Index is created from IPV (3 bits) + DR (2 bits) field. Value is the mapped PCP for VLAN tag.
-
uint8_t pcp[8]
Index is created from outer PCP (3 bits) field. Value is the mapped PCP for VLAN tag.
-
uint8_t qos[32]
-
struct fsl_netc
-
struct _netc_switch_inuse_fdb_statistic
- #include <fsl_netc.h>
Switch static/dynamic FDB entries in-use statistic.
Public Members
-
uint16_t camEntries
Number of FDB entries in-use in the CAM.
-
uint16_t staticEntries
Number of static FDB entries in-use (both hash-based and CAM-based entries).
-
uint16_t dynamicEntries
Number of dynamic FDB entries in-use (hash-based and CAM-based entries).
-
uint16_t dynamicEntriesHWM
High water mark of dynamic entries in-use in the FDB table.
-
uint16_t camEntries
-
struct defaultVlan
Public Members
-
uint32_t vid
Vlan Identifier.
-
uint32_t dei
Drop eligible indicator
-
uint32_t pcp
Priority code point.
-
uint32_t tpid
Tag protocol identifier, 0 = Standard C-VLAN 0x8100, 1 = Standard S-VLAN 0x88A8.
-
uint32_t vid
Hardware Table Access Functions
-
enum _netc_tb_index
Table index.
Values:
-
enumerator kNETC_TGSTable
Time Gate Scheduling table index
-
enumerator kNETC_RPTable
Rate Policer table index
-
enumerator kNETC_IPFTable
Ingress Port filter table index
-
enumerator kNETC_FDBTable
FDB table index
-
enumerator kNETC_L2MCFTable
L2 IPV4 Multicast Filter table index
-
enumerator kNETC_VFTable
VLAN Filter table index
-
enumerator kNETC_ECQTable
ETM Class Queue table index
-
enumerator kNETC_ECSTable
ETM Class Scheduler table index
-
enumerator kNETC_ISITable
Ingress Stream Identification table index
-
enumerator kNETC_ISTable
Ingress Stream table index
-
enumerator kNETC_ISFTable
Ingress Stream Filter table index
-
enumerator kNETC_ETTable
Egress Treatment table index
-
enumerator kNETC_ISGTable
Ingress Sequence Generation table index
-
enumerator kNETC_ESRTable
Egress Sequence Recovery table index
-
enumerator kNETC_SGITable
Stream Gate Instance table index
-
enumerator kNETC_SGCLTable
Stream Gate Control List table index
-
enumerator kNETC_ISCTable
Ingress Stream Count table index
-
enumerator kNETC_ECTable
Egress Count table index
-
enumerator kNETC_FMTable
Frame Modification table index
-
enumerator kNETC_BPTable
Buffer Pool table index
-
enumerator kNETC_SBPTable
Shared Buffer Pool table index
-
enumerator kNETC_ECGTable
ETM Class Group table index
-
enumerator kNETC_FMDTable
Frame Modification Data table index
-
enumerator kNETC_TGSTable
-
enum _netc_tb_cmd
Table management command operations.
Values:
-
enumerator kNETC_DeleteEntry
Delete operation
-
enumerator kNETC_UpdateEntry
Update operation
-
enumerator kNETC_QueryEntry
Query operation
-
enumerator kNETC_QueryAndDeleteEntry
Query operation followed by a delete operation
-
enumerator kNETC_QueryAndUpdateEntry
Query operation followed by a update operation
-
enumerator kNETC_AddEntry
Add operation
-
enumerator kNETC_AddOrUpdateEntry
If the entry exists, is update operation, if not exist, is the Add operation
-
enumerator kNETC_AddAndQueryEntry
Add operation followed by a query operation
-
enumerator kNETC_AddQueryAndUpdateEntry
Add operation followed by a query operation, Then, if the entry existed prior to the Add operation of this command, the Update operation will be performed.
-
enumerator kNETC_DeleteEntry
-
enum _netc_tb_access_mode
Table Access Method.
Values:
-
enumerator kNETC_EntryIDMatch
Entry ID Match
-
enumerator kNETC_ExactKeyMatch
Exact Match Key Element Match
-
enumerator kNETC_Search
Search with search criteria
-
enumerator kNETC_TernaryKeyMatch
Ternary Match Key Element Match
-
enumerator kNETC_EntryIDMatch
-
enum _netc_cbd_version
NTMP version.
Values:
-
enumerator kNETC_NtmpV1_0
NTMP Version 1.0
-
enumerator kNETC_NtmpV2_0
NTMP Version 2.0
-
enumerator kNETC_NtmpV1_0
-
enum _netc_cmd_error
Table command response error status.
Values:
-
enumerator kNETC_FormatError
Format error : 1. Illegal class or command. 2. Invalid SF bit setting. 3. LENGTH is zero for long format. 4. LENGTH is too small for buffer size.
-
enumerator kNETC_SizeError
Size error : 1. Invalid table index, out of range. 2. Table overflow, no additional entries available.
-
enumerator kNETC_AccessError
Access violation error, the entity is not allowed to perform the task requested
-
enumerator kNETC_ClassError
Class specific error
-
enumerator kNETC_IntegrityError
Integrity error, the command did not execute due to a data integrity error (ECC on internal memory or AXI read/write error)
-
enumerator kNETC_InvTableID
Invalid table ID
-
enumerator kNETC_InvAccMethod
Invalid Access method
-
enumerator kNETC_TableIdxOutRange
Table index out of range
-
enumerator kNETC_DBNotEnough
Request data buffer size or response data buffer size is not sufficient
-
enumerator kNETC_InvCmd
Invalid command
-
enumerator kNETC_ReqDBError
Request Data buffer error
-
enumerator kNETC_MultiBitError
Multi-bit ECC or parity error observed during command processing
-
enumerator kNETC_HashEntryLimit
Exceeded hash entry limit
-
enumerator kNETC_HashChainLimit
Exceeded maximum hash collision chain limit and the CAM if present is full
-
enumerator kNETC_InvHWGenEntryID
Invalid ENTRY_ID for ENTRY_ID generated by hardware
-
enumerator kNETC_SrchResDBNotEnough
Search command filled the response data buffer before completing the command
-
enumerator kNETC_CmdIdxTableWithITM
Command for index table before OSR[ITM_STATE]=0
-
enumerator kNETC_InvQueryAction
Invalid Query action
-
enumerator kNETC_InvTableAccPrivilege
Invalid table access privilege
-
enumerator kNETC_ReadSysBusErr
System Bus Read Error
-
enumerator kNETC_WriteSysBusErr
System Bus Write Error
-
enumerator kNETC_ClientErr
Client encountered a fault
-
enumerator kNETC_TGSCmdIssue
Command issued when time gating function is disabled for the port.
-
enumerator kNETC_TGSUpdateExistList
Update action attempted on an existing admin gate control list. (should delete admin gate control list first before creating a new admin list)
-
enumerator kNETC_TGSUpdateOverLength
Update action attempted exceeds TGSTCAPR[MAX_GCL_LEN]
-
enumerator kNETC_TGSUpdateOverSize
Update action attempted exceeds TGSTCAPR[NUM_WORDS].
-
enumerator kNETC_TGSEntryNotEnough
Insufficient resources to perform the requested operation (not enough free time gate list entries)
-
enumerator kNETC_TGSUpdateNSList
Update action attempted with ADMIN_CYCLE_TIME, ADMIN_TIME_INTERVAL_GE_i or truncated ADMIN_TIME_INTERVAL_GE_n due ADMIN_CYCLE_TIME specified is not sufficient to transmit 64 byte of frame data + header overhead.
-
enumerator kNETC_TGSUpdateEarlierStartTime
Update action attempted with ADMIN_BASE_TIME specified s more than one second in the past from tcs advance time.
-
enumerator kNETC_TGSUpdateOverflowCycle
Update action attempted with ADMIN_CYCLE_TIME + ADMIN_CYCLE_TIME_EXT is greater than 2^32-1.
-
enumerator kNETC_TGSQueryBeforeListActive
Query action issued when config change occurred. Retry query.
-
enumerator kNETC_TGSUpdateInvGateValue
Update action attempted with ADMIN_HR_CB_GE_i set to an invalid value
-
enumerator kNETC_RPSDUTypeOutRange
SDU_TYPE specified in entry CFGE_DATA is out of range
-
enumerator kNETC_IPFInvHR
HR value not valid. Only checked if command issued from the Switch and FLTFA=0x2 or FLTFA=0x3
-
enumerator kNETC_IPFEntryNotFit
Entry being added does not fit in table
-
enumerator kNETC_IPFWithoutSTSE
CFGE_DATA update without STSE_DATA update
-
enumerator kNETC_IPFInvRPP
RPR set to a reserved value. Only checked if FLTA=0x2.
-
enumerator kNETC_IPFFLTATGTOutRange
FLTA_TGT is outside valid range and not NULL. Only checked if FLTA>0x0
-
enumerator kNETC_IPFInvSwtFLTA
FLTA=0x3 when command issued from the Switch.
-
enumerator kNETC_IPFInvEnetcFLTA
FLTFA>0x1 when command issued from an ENETC PF.
-
enumerator kNETC_FDBReachPortLimit
Failed to add or update and entry because the Port BPCR[DYN_LIMIT] has been reached
-
enumerator kNETC_FDBReachSwtLimit
Failed to add entry because the Switch FDBHTMCR[DYN_LIMIT] has been reached.
-
enumerator kNETC_FDBInvEPORT
EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1)
-
enumerator kNETC_FDBETEIDOutRange
ET_EID is out of range and not NULL. Only checked if OETEID>0x0
-
enumerator kNETC_FDBParityErr
Parity error encountered when adding guaranteed entry
-
enumerator kNETC_L2MCFInvEPORT
EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1)
-
enumerator kNETC_L2MCFETEIDOutRange
ET_EID is not NULL or within the valid range. Only checked if OETEID>0x0.
-
enumerator kNETC_L2MCFInvKEYTYPE
KEY_TYPE value not valid
-
enumerator kNETC_VFBASEETEIDOutRange
BASE_ET_EID is out of range or MLO is not valid.
-
enumerator kNETC_ECQCQ2CGMAPOutRange
CQ2CG_MAP value out-of-range in update command.
-
enumerator kNETC_ISIPortIDOutRange
Port ID specified in KEYE_DATA is out of range.
-
enumerator kNETC_ISIInvISEID
IS_EID in invalid.
-
enumerator kNETC_ISInvOpt
Option specified in one or more of the following fields is not valid – FA, CTD or ISQA, SDU_TYPE.
-
enumerator kNETC_ISInvID
One or more of following : 1. Entry IDs are not in valid range or Entry ID is not Null. 2. Check valid ranges specified for these Entry IDs in Ingress Stream table entry – RP_EID, SGI_EID, ISQ_EID, ET_EID or EPORT. 3. ET_EID is checked if (FA =010b .. 101b) & (OETEID!=0). 4. EPORT is checked if (FA = 010b .. 101b) & (OETEID= 0x1 OR CTD= 0x1). 5. HR is chked if FA = 001b, 100b, or 101b. HR specified cannot be 0x0
-
enumerator kNETC_ISInvFMEID
FM_EID format or index is out of range : 1. FM_EID format option type is invalid. 2. FM_EID format is option 1 and the Index is out of range and not Null, or FM_EID format is option 2 and VUDA or SQTA is out of range.
-
enumerator kNETC_ISFInvISEID
IS_EID in KEYE_DATA is invalid.
-
enumerator kNETC_ISFInvCFGE
Any of the following in CFGE_DATA is invalid : 1. One or more of following Entry IDs are not in valid range or Entry ID specified is not Null. Checks are performed for following Entry IDs CFGE DATA – RP_EID, SGI_EID, ISC_EID. 2. SDU_TYPE is invalid
-
enumerator kNETC_ETInvOpt
Command option specified is invalid or not supported. ESQA is not 00 or 10 (others are reserved), or ECA > 1 (reserved).
-
enumerator kNETC_ETInvFMEID
FM_EID format or index is out of range. Check performed is as follows : 1. EFM_EID format option type is invalid, or EFM_EID format is option 1 and the Index is out of range and not Null, or EFM_EID format is option 2 and VUDA or SQTA is out of range . 2. the Egress Counter Table index EC_EID is out of range. 3. The Egress Sequence Actions Target Entry ID ESQA_TGT_EID is out of range
-
enumerator kNETC_ISGInvQSTAG
SQ_TAG specified is not valid
-
enumerator kNETC_SGISGCLEIDOutRange
SGCL_EID specified in out of range for Add or Update operation.
-
enumerator kNETC_SGIInvSDUTYPE
SDU_TYPE is specified is invalid for Add or Update operation.
-
enumerator kNETC_SGISGCLEIDNotAlloc
Either the SGCL_EID specified as admin gate control list in Add or Update operation has not been allocated or SGCL_EID is not the first entry in gate control list or the reference count in SGCL entry is not 0.
-
enumerator kNETC_SGIInvSGCLEID
SGCL_EID specified for Update operation is in invalid.
-
enumerator kNETC_SGIInvADMINBASETIME
ADMIN_BASE_TIME specified for Add or Update operation is more than 2^30ns in the past.
-
enumerator kNETC_SGIInvCYCLETIME
Cumulated time value of CYCLE_TIME in Stream gate Control list plus CYCLE_TIME_EXT specified in Add or Update operation is >=2^30ns or CYCLE_TIME specified is 0.
-
enumerator kNETC_SGCLOverLength
Number words required for the LIST_LENGTH specified for the Add operation exceeds the number of words allocated for SGCL table
-
enumerator kNETC_SGCLTimeIntervalZero
TIME_INTERVAL_GE_N specified in Add operation is 0. Note that upper 2 bits of TIME_INTERVAL_GE_N are ignored, TIME_INTERVAL_GE_N[29:0] must not be 0.
-
enumerator kNETC_SGCLTimeIntervalOverflow
Cumulated time value of TIME_INTERVAL_GE_N[29:0] for the gate list specified in Add operation is >= 2^30ns.
-
enumerator kNETC_FMInvEMEID
FM_EID format is invalid
-
enumerator kNETC_FMOptOutRange
Following fields specified are out of range - MAC_HDR_ACT, VLAN_HDR_ACT, SQT_ACT, OUTER_PCP_DEI_ACT, PLD_ACT.
-
enumerator kNETC_FMFMDOutRange
FMD_EID,FMD_BYTES specified is out of range. When FMD_EID is not set to Null, valid range is FMD_EID[15:0]*24 + FMD_BYTES <= (FMDITCAPR[NUM_WORDS]*24).
-
enumerator kNETC_BPSBPEIDOutRange
SBP_EN is 1 and SBP_EID value is out-of-range in update command
-
enumerator kNETC_FormatError
-
enum _netc_fm_vlan_ud_act
Frame Modification VLAN Update/Delete Action.
Note
Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame.
Values:
-
enumerator kNETC_NoUDVlanAction
No Update/Delete VLAN action
-
enumerator kNETC_ReplVlanPcpAndDei
Replace outer VLAN’s PCP/DEI based on the port’s PPCPDEIMR. The tag’s original VID and TPID are preserved
-
enumerator kNETC_DelVlan
Delete outer VLAN Tag
-
enumerator kNETC_NoUDVlanAction
-
enum _netc_fm_sqt_act
Frame Modification Sequence Tag Action.
Note
Must be set to 000b for Ingress frame modification, otherwise misconfiguration error..
Values:
-
enumerator kNETC_NoSqtAction
No SQT action
-
enumerator kNETC_ReomveRTag
Remove R-TAG/draft 2.0 R-TAG/HSR tag, If R-TAG/HSR tag not present, misconfiguration error.
-
enumerator kNETC_NoSqtAction
-
enum _netc_fm_vlan_ar_act
Frame Modification VLAN Add/Replace Action.
Note
For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value.
Values:
-
enumerator kNETC_AddCVlanPcpAndDei
Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x8100
-
enumerator kNETC_AddSVlanPcpAndDei
Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x88A8
-
enumerator kNETC_ReplVidOnly
Replace VLAN with VID. The tag’s original PCP, DEI and TPID are preserved
-
enumerator kNETC_ReplVidPcpAndDei
Replace VLAN with VID and PCP/DEI updated by port’s PPCPDEIMR. The tag’s original TPID is preserved
-
enumerator kNETC_AddCVlanPcpAndDei
-
enum _netc_tb_eteid_access_mode
Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode.
Note
The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached
Values:
-
enumerator kNETC_NoETAccess
No Egress Treatment table access
-
enumerator kNETC_SinglePortETAccess
Only frame sent to a special port (define in ePort) can access a single Egress Treatment table entry, the applicability bitmap specified by FDB/L2MCF/IS ePort field
-
enumerator kNETC_MulitPortPackedETAccess
Only frames sent to a special set of ports (ports set to 1 in ePortBitmap) can access the Egress Treatment table, the applicability bitmap = IS ePortBitmap field or FDB/L2MCF portBitmap field
-
enumerator kNETC_MulitPortAbsETAccess
Frames sent to all of ports can access the Egress Treatment table, means the applicability bitmap is set with 1 for all ports
-
enumerator kNETC_NoETAccess
-
enum _netc_tb_ipf_update_action
Ingress Port Filter Table Update Actions.
Values:
-
enumerator kNETC_IPFCfgEUpdate
Configuration Element Update
-
enumerator kNETC_IPFStsEUpdate
Statistics Element Update
-
enumerator kNETC_IPFCfgEUpdate
-
enum _netc_tb_ipf_attr_mask
Ingress Port Filter frame attribute mask.
Values:
-
enumerator kNETC_IPFSwtPortMasMask
Switch port masquerading Mask
-
enumerator kNETC_IPFEthernetMask
Ethernet type Mask
-
enumerator kNETC_IPFOuterVlanMask
Outer VLAN Mask
-
enumerator kNETC_IPFInnerVlanMask
Inner VLAN Mask
-
enumerator kNETC_IPFSeqTagMask
Sequence Tag Code Mask
-
enumerator kNETC_IPFIpHeaderMask
IP Header Mask
-
enumerator kNETC_IPFIpVersionMask
IP Version Mask
-
enumerator kNETC_IPFIpExtMask
IPv4 option / IPv6 extension Mask
-
enumerator kNETC_IPFL4HeaderMask
L4 Code Mask
-
enumerator kNETC_IPFWakeOnLanMask
Wake-on-LAN Magic Packet Mask
-
enumerator kNETC_IPFSwtPortMasMask
-
enum _netc_tb_ipf_seq_tag
Ingress Port Filter frame attribute Sequence Tag Code.
Values:
-
enumerator kNETC_IPFNoRtag
R-TAG/HSR tag is not present
-
enumerator kNETC_IPFDraftRtag
802.1CB draft 2.0 R-TAG is present
-
enumerator kNETC_IPFRtag
802.1CB R-TAG is present
-
enumerator kNETC_IPFHsrTag
HSR Tag is present
-
enumerator kNETC_IPFNoRtag
-
enum _netc_tb_ipf_l4_header
Ingress Port Filter frame attribute L4 Header Code.
Values:
-
enumerator kNETC_IPFOtherL4
The L4 Header is considered as other L4 if it is not one of the following L4 Headers
-
enumerator kNETC_IPFTcp
TCP header is present
-
enumerator kNETC_IPFUdp
UDP header is present
-
enumerator kNETC_IPFSctp
SCTP header is present
-
enumerator kNETC_IPFOtherL4
-
enum _netc_tb_ipf_forward_action
Ingress port filter forwarding Action.
Values:
-
enumerator kNETC_IPFForwardDiscard
Frame be discard
-
enumerator kNETC_IPFForwardPermit
Frame be permit
-
enumerator kNETC_IPFRedirectToMgmtPort
Redirect frame to switch management port without any frame modification, Switch only
-
enumerator kNETC_IPFCopyToMgmtPort
Copy frame to switch management port without any frame modification, Switch only
-
enumerator kNETC_IPFForwardDiscard
-
enum _netc_tb_ipf_filter_action
Ingress port filter Filter Action.
Values:
-
enumerator kNETC_IPFNoAction
No action
-
enumerator kNETC_IPFWithRatePolicer
Rate action with the Rate Policer Entry ID (RP_EID) set to the value configured in the fltaTgt field
-
enumerator kNETC_IPFWithIngressStream
Ingress stream identification action where the Ingress Stream Entry ID (IS_EID) is set to the value configured in the fltaTgt field
-
enumerator kNETC_IPFWithL2Filtering
Setting a pre L2 filtering SI bitmap (set to the value configured in the fltaTgt) that will be used by the L2 filtering function to determine the final SI bitmap, ENETC only
-
enumerator kNETC_IPFNoAction
-
enum _netc_tb_isi_key_type
Stream identification table key type.
Values:
-
enumerator kNETC_KCRule0
Use key construction rule 0 (ISIDKC0CR0)
-
enumerator kNETC_KCRule1
Use key construction rule 1 (ISIDKC1CR0)
-
enumerator kNETC_KCRule2
Use key construction rule 2 (ISIDKC2CR0). Only for SWITCH
-
enumerator kNETC_KCRule3
Use key construction rule 3 (ISIDKC3CR0). Only for SWITCH
-
enumerator kNETC_KCRule0
-
enum _netc_tb_is_isq_action
Ingress Stream table Ingress Sequence Action.
Values:
-
enumerator kNETC_ISNotPerformFRER
Not perform Frame FRER sequence generation function
-
enumerator kNETC_ISPerformFRER
Perform Frame FRER sequence generation function
-
enumerator kNETC_ISNotPerformFRER
-
enum _netc_tb_is_forward_action
Ingress Stream table forwarding Action.
Values:
-
enumerator kNETC_ISDiscard
Frame be discard
-
enumerator kNETC_ISRedirectToMgmtPort
Frame be Re-direct frame to switch management port, Switch only
-
enumerator kNETC_ISAllow
Frame is allow without setting the pre L2 filtering SI bitmap, ENETC only
-
enumerator kNETC_ISAllowWithSIMap
Frame is allow with setting the pre L2 filtering SI bitmap to the value configured in the SI_MAP field, ENETC only
-
enumerator kNETC_ISStreamForward
Frame is forwarded to the port(s) specified in the EGRESS_PORT_BITMAP field, Switch only
-
enumerator kNETC_ISBridgeForward
Frame is do 802.1Q Bridge forwarding (VLAN processing and L2 forwarding), Switch only
-
enumerator kNETC_ISCopyToMgmtPortAndStream
Copy frame to switch management port with specified HR and stream forwarding, Switch only
-
enumerator kNETC_ISCopyToMgmtPortAndBridge
Copy frame to switch management port with specified HR and Bridge forwarding, Switch only
-
enumerator kNETC_ISDiscard
-
enum _netc_tb_is_ctd_mode
Ingress Stream table Cut-Through Disable mode.
Values:
-
enumerator kNETC_ISNoCTD
Do not override cut-through state
-
enumerator kNETC_ISSinglePortCTD
Disable cut-through for the outgoing port specified in the cfge ePort field
-
enumerator kNETC_ISAllPortCTD
Disable cut-through for all ports specified in cfge portBitmap field
-
enumerator kNETC_ISNoCTD
-
enum _netc_tb_rp_update_action
Rate Policer Table Update Actions.
Values:
-
enumerator kNETC_RPCfgEUpdate
Configuration Element Update
-
enumerator kNETC_RPFeEUpdate
Functional Enable Element Update
-
enumerator kNETC_RPPsEUpdate
Policer State Element Update Element Update
-
enumerator kNETC_RPStsEUpdate
Statistics Element Update
-
enumerator kNETC_RPCfgEUpdate
-
enum _netc_tb_sgi_update_action
Stream Gate Instance table Update Actions.
Values:
-
enumerator kNETC_SGIAcfEUpdate
Admin Configuration Element
-
enumerator kNETC_SGICfgEUpdate
Configuration Element Update
-
enumerator kNETC_SGISgisEUpdate
Stream Gate Instance State Element Update
-
enumerator kNETC_SGIAcfEUpdate
-
enum _netc_tb_sgi_state
Stream Gate Instance State.
Values:
-
enumerator kNETC_GSNotOper
Gate instance is not operational or Gate instance and lists are not valid
-
enumerator kNETC_GSUseDefaultParam
Gate instance is operational but no stream gate control list specified, use default Gate Instance parameters
-
enumerator kNETC_GSUseDefUntilAdminAct
Use default Gate Instance parameters until administrative stream gate control list takes effect
-
enumerator kNETC_GSUseOperUntilAdminAct
Use Operational stream gate control list until new administrative stream gate control list takes effect
-
enumerator kNETC_GSUseOperList
Operational stream gate control list is in effect
-
enumerator kNETC_GSNotOper
-
enum _netc_tb_fm_layer2_act
Frame Modification table Layer 2 Actions.
Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.
Values:
-
enumerator kNETC_UseL2HeaderAct
L2 actions are specified in L2 header action fields macHdrAct, vlanHdrAct and sqtAct
-
enumerator kNETC_UseSpecPlayload
The entire L2 PDU is replaced with fmdBytes of data specified in fmdEID, not applicable for ingress frame modifications
-
enumerator kNETC_UseL2HeaderAct
-
enum _netc_tb_fm_mac_header_act
Frame Modification table Layer 2 Header MAC Actions.
Note
Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac.
Values:
-
enumerator kNETC_NoMacAction
No Mac header action
-
enumerator kNETC_ReplSmac
Replace SMAC with the contents of the port’s PMAR0/1 register, The port is specified by smacPort field
-
enumerator kNETC_ReplSmacAndDmacAct1
Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by dmac[6] field
-
enumerator kNETC_ReplSmacAndDmacAct2
Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by frame’s SMAC
-
enumerator kNETC_ReplDmac
Replace DMAC with specified dmac[6] field value
-
enumerator kNETC_SwapDmacAndSmac
Swap DMAC and SMAC
-
enumerator kNETC_NoMacAction
-
enum _netc_tb_fm_vlan_header_act
Frame Modification table Layer 2 VLAN Actions.
Note
For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
Values:
-
enumerator kNETC_NoVlanAction
No VLAN header action
-
enumerator kNETC_DelOuterVlan
Delete outer VLAN header
-
enumerator kNETC_AddOuterVlan
Add outer VLAN header (new VLAN data will be inserted in the outer position), the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field
-
enumerator kNETC_ReplOuterVlan
Replace outer VLAN header, the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field
-
enumerator kNETC_NoVlanAction
-
enum _netc_tb_fm_outer_vid_act
Frame Modification table Layer 2 outer VLAN VID Actions.
Note
For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
Values:
-
enumerator kNETC_UseFrameVid
Use the VID from the valid outer VLAN header of the received frame
-
enumerator kNETC_UseSpecVid
Use the VID specified in the outerVlanID field
-
enumerator kNETC_UseFrameVid
-
enum _netc_tb_fm_outer_tpid_act
Frame Modification table Outer TPID action.
Note
For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
Values:
-
enumerator kNETC_UseFrameTpid
Use TPID from outer VLAN header
-
enumerator kNETC_UseStdCVlan
Set TPID to Standard C-VLAN 0x8100
-
enumerator kNETC_UseStdSVlan
Set TPID to Standard S-VLAN 0x88A8
-
enumerator kNETC_UseCustomCVlan
Set TPID to Custom C-VLAN as defined by CVLANR1[ETYPE]
-
enumerator kNETC_UseCustomSVlan
Set TPID to Custom S-VLAN as defined by CVLANR2[ETYPE]
-
enumerator kNETC_UseFrameTpid
-
enum _netc_tb_fm_outer_pcp_act
Frame Modification table Outer PCP action.
Note
For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
Values:
-
enumerator kNETC_UseFramePcp
Use PCP from frame outer VLAN header
-
enumerator kNETC_UseSpecPcp
Use the PCP specified in the outerVlanPcp field
-
enumerator kNETC_UseFramePcpMap
The PCP is mapping from frame outer VLAN PCP (do mapping according to the PCP to PCP mapping profile which specified in PPCPDEIMR[IPCPMP/EPCPMP])
-
enumerator kNETC_UseQosMap
The PCP is mapping from internal QoS (IPV, DR) (do mapping according to the QOS to PCP mapping profile which specified in QOSVLANMPaR0/1/2/3), not applicable for ingress frame modifications
-
enumerator kNETC_UseFramePcp
-
enum _netc_tb_fm_outer_dei_act
Frame Modification table Outer DEI action.
Note
For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
Values:
-
enumerator kNETC_UseFrameDei
Use DEI from frame outer VLAN header
-
enumerator kNETC_UseSpecDei
Use the DEI specified in the outerVlanDei field
-
enumerator kNETC_UseDrMap
The DEI is mapping from internal DR (do mapping according to the DR to DEI mapping profile which specified in PPCPDEIMR[DRnDEI], not applicable for ingress frame modifications
-
enumerator kNETC_UseFrameDei
-
enum _netc_tb_fm_payload_act
Frame Modification table Payload Actions.
Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.
Values:
-
enumerator kNETC_NoAction
No Action
-
enumerator kNETC_ReplAllEthPld
Remove entire Ethernet payload and insert with fmdBytes of data specified in fmdEID
-
enumerator kNETC_ReplPldWithOffset
Replace fmdBytes of raw data in the Ethernet payload starting at pldOffset, data specified in fmdEID
-
enumerator kNETC_NoAction
-
enum _netc_tb_fdb_update_action
FDB table Update Actions.
Values:
-
enumerator kNETC_FDBCfgEUpdate
Configuration Element Update
-
enumerator kNETC_FDBActEUpdate
Activity Element Update
-
enumerator kNETC_FDBCfgEUpdate
-
enum _netc_tb_fdb_ctd_mode
FDB table Cut-Through Disable mode.
Values:
-
enumerator kNETC_FDBNoCTD
Do not override cut-through state
-
enumerator kNETC_FDBSinglePortCTD
Disable cut-through for the outgoing port specified in the cfge ePort field
-
enumerator kNETC_FDBAllPortCTD
Disable cut-through for all ports specified in cfge portBitmap field
-
enumerator kNETC_FDBNoCTD
-
enum _netc_tb_fdb_sc_keye_mc
FDB table search criteria Key Element Match Criteria.
Values:
-
enumerator kNETC_FDBKeyeMacthAny
Match any Key Element Criteria
-
enumerator kNETC_FDBKeyeMacthFID
Match Key Element FID
-
enumerator kNETC_FDBKeyeMacthMacMulticast
Match Key Element MAC Multicast bit (MAC_ADDR most significant byte’s least significant bit)
-
enumerator kNETC_FDBKeyeMacthBoth
Match both FID field and MAC Multicast bit
-
enumerator kNETC_FDBKeyeMacthAny
-
enum _netc_tb_fdb_sc_cfge_mc
FDB table search criteria Configuration Element Match Criteria.
Values:
-
enumerator kNETC_FDBCfgeMacthAny
Match any Configuration Element Criteria
-
enumerator kNETC_FDBCfgeMacthDynamic
Match Configuration Element dynamic field
-
enumerator kNETC_FDBCfgeMacthPortBitmap
Match Configuration Element portBitmap field
-
enumerator kNETC_FDBCfgeMacthBoth
Match both dynamic field and portBitmap
-
enumerator kNETC_FDBCfgeMacthAny
-
enum _netc_tb_fdb_sc_acte_mc
FDB table search criteria Activity Element Match Criteria.
Values:
-
enumerator kNETC_FDBActeMacthAny
Match any Activity Element Criteria
-
enumerator kNETC_FDBActeMatchExact
Exact match with Activity Element
-
enumerator kNETC_FDBActeMacthAny
-
enum _netc_tb_l2mcf_key_type
L2 IPV4 Multicast Filter table key type.
Values:
-
enumerator kNETC_IPv4ASMKey
Key consists of a filtering ID (FID) and destination multicast IPv4 address
-
enumerator kNETC_IPv4SSMKey
Key consists of a filtering ID (FID), IPv4 source address and multicast IPv4 destination address
-
enumerator kNETC_IPv4ASMKey
-
enum _etc_tb_l2mcf_sc_keye_mc
L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria.
Values:
-
enumerator kNETC_L2MCFKeyeMacthAny
Match any Key Element Criteria
-
enumerator kNETC_L2MCFKeyeMacthFID
Match Key Element FID
-
enumerator kNETC_L2MCFKeyeMacthAny
-
enum _etc_tb_l2mcf_sc_cfge_mc
L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria.
Values:
-
enumerator kNETC_L2MCFCfgeMacthAny
Match any Configuration Element Criteria
-
enumerator kNETC_L2MCFCfgeMacthDynamic
Match Configuration Element dynamic field
-
enumerator kNETC_L2MCFCfgeMacthPortBitmap
Match Configuration Element portBitmap field
-
enumerator kNETC_L2MCFCfgeMacthBoth
Match both dynamic field and portBitmap
-
enumerator kNETC_L2MCFCfgeMacthAny
-
enum _etc_tb_l2mcf_sc_acte_mc
FDB table search criteria Activity Element Match Criteria.
Values:
-
enumerator kNETC_L2MCFActeMacthAny
Match any Activity Element Criteria
-
enumerator kNETC_L2MCFActeMatchExact
Exact match with Activity Element
-
enumerator kNETC_L2MCFActeMacthAny
-
enum _netc_tb_iseqg_sqtag
Sequence Tag Type.
Values:
-
enumerator kNETC_SqDraftRTag
802.1CB draft 2.0 R-TAG.
-
enumerator kNETC_SqRTag
802.1CB R-TAG.
-
enumerator kNETC_SqHsrTag
HSR Tag.
-
enumerator kNETC_SqDraftRTag
-
enum _netc_tb_iseqg_update_action
Ingress Sequence Generation Table Update Actions.
Values:
-
enumerator kNETC_ISEQGCfgEUpdate
Configuration Element Update
-
enumerator kNETC_ISEQGSgsEUpdate
Sequence Generation Element Update
-
enumerator kNETC_ISEQGCfgEUpdate
-
enum _netc_tb_eseqr_sqtag
Egress Sequence Recovery table Sequence Tag Type.
Values:
-
enumerator kNETC_AcceptAnyTag
Accept any incoming tag type (802.1CB draft 2.0 R-TAG, 802.1CB R-TAG or HSR Tag)
-
enumerator kNETC_AcceptDraftRTag
802.1CB draft 2.0 R-TAG.
-
enumerator kNETC_AcceptRTag
802.1CB R-TAG.
-
enumerator kNETC_AcceptHsrTag
HSR Tag.
-
enumerator kNETC_AcceptAnyTag
-
enum _netc_tb_tgs_entry_id
Time Gate Scheduling table entry ID for switch and ENETC.
Values:
-
enumerator kNETC_TGSSwtPort0
Switch PORT 0 entry ID
-
enumerator kNETC_TGSSwtPort1
Switch PORT 1 entry ID
-
enumerator kNETC_TGSSwtPort2
Switch PORT 2 entry ID
-
enumerator kNETC_TGSSwtPort3
Switch PORT 3 entry ID
-
enumerator kNETC_TGSSwtPort4
Switch PORT 4 entry ID
-
enumerator kNETC_TGSEnetc0Port
ENETC 0 port entry ID
-
enumerator kNETC_TGSEnetc1Port
ENETC 1 port entry ID
-
enumerator kNETC_TGSSwtPort0
-
enum _netc_tb_tgs_gate_type
Administrative gate operation type.
Values:
-
enumerator kNETC_SetGateStates
HoldRequest is unchanged
-
enumerator kNETC_SetAndHoldMac
HoldRequest is set to value hold, only active when enable preemption
-
enumerator kNETC_SetAndReleaseMac
HoldRequest is set to value release, only active when enable preemption
-
enumerator kNETC_SetGateStates
-
enum _netc_tb_et_efm_mode
Egress Frame Modification entry mode.
Values:
-
enumerator kNETC_NormalMode
Egress Frame Modification entry use normal/Default mode
-
enumerator kNETC_L2Act1
Egress Frame Modification entry l2Act = kNETC_UseSpecPlayload
-
enumerator kNETC_PldAct1
Egress Frame Modification entry pldAct = kNETC_ReplAllEthPld
-
enumerator kNETC_NormalMode
-
enum _netc_tb_et_esq_act
Egress Sequence Actions.
Values:
-
enumerator kNETC_NoEsqAction
No Egress Sequence Action required
-
enumerator kNETC_HasEsqAction
Has Egress Sequence Recovery action
-
enumerator kNETC_NoEsqAction
-
enum _netc_tb_et_ec_act
Egress Counter Action.
Values:
-
enumerator kNETC_NoEcCounter
Do not increment egress frame counter
-
enumerator kNETC_HasEcCounter
Increment egress frame counter
-
enumerator kNETC_NoEcCounter
-
enum _netc_tb_etmcq_update_action
ETM Class Queue table Update Actions.
Values:
-
enumerator kNETC_CQCfgEUpdate
Configuration Element Update
-
enumerator kNETC_CQStsEUpdate
Statistics Element Update, all counters (except FRM_CNT) within the Statistics Element are reset
-
enumerator kNETC_CQCfgEUpdate
-
enum _netc_tb_etmcs_entry_id
ETM Class Scheduler table entry ID.
Values:
-
enumerator kNETC_CSSwtPort0
CS Switch PORT 0 entry ID
-
enumerator kNETC_CSSwtPort1
CS Switch PORT 1 entry ID
-
enumerator kNETC_CSSwtPort2
CS Switch PORT 2 entry ID
-
enumerator kNETC_CSSwtPort3
CS Switch PORT 3 entry ID
-
enumerator kNETC_CSSwtPort4
CS Switch PORT 4 entry ID
-
enumerator kNETC_CSSwtPort0
-
enum _netc_tb_etmcs_ca_assg
ETM Class Scheduler table Class queue assignment to scheduler inputs mode.
Values:
-
enumerator kNETC_CQ7AssignToSchedIn15
CQ 7 assignment to scheduler input 15, means all CQ use strict priority
-
enumerator kNETC_CQ7AssignToSchedIn14
CQ 7 assignment to scheduler input 14
-
enumerator kNETC_CQ7AssignToSchedIn13
CQ 7 assignment to scheduler input 13
-
enumerator kNETC_CQ7AssignToSchedIn12
CQ 7 assignment to scheduler input 12
-
enumerator kNETC_CQ7AssignToSchedIn11
CQ 7 assignment to scheduler input 11
-
enumerator kNETC_CQ7AssignToSchedIn10
CQ 7 assignment to scheduler input 10
-
enumerator kNETC_CQ7AssignToSchedIn9
CQ 7 assignment to scheduler input 9
-
enumerator kNETC_CQ7AssignToSchedIn8
CQ 7 assignment to scheduler input 8
-
enumerator kNETC_CQ7AssignToSchedIn7
CQ 7 assignment to scheduler input 7, means all CQ use weighted fair
-
enumerator kNETC_CQ7AssignToSchedIn15
-
enum _netc_tb_bp_fc_cfg
Buffer Pool Flow Control (FC) Configuration.
Values:
-
enumerator kNETC_FlowCtrlDisable
Flow Control disabled
-
enumerator kNETC_FlowCtrlWithBP
Flow Control enabled using only buffer pool FC state.
-
enumerator kNETC_FlowCtrlWithSBP
Flow Control enabled using only shared buffer pool FC state.
-
enumerator kNETC_FlowCtrlWithBPAndSBP
Flow Control enabled using both buffer pool and shared buffer pool FC state, only both 1 trigger the Flow Control ON
-
enumerator kNETC_FlowCtrlDisable
-
typedef enum _netc_tb_index netc_tb_index_t
Table index.
-
typedef enum _netc_tb_cmd netc_tb_cmd_t
Table management command operations.
-
typedef enum _netc_tb_access_mode netc_tb_access_mode_t
Table Access Method.
-
typedef enum _netc_cbd_version netc_cbd_version_t
NTMP version.
-
typedef enum _netc_cmd_error netc_cmd_error_t
Table command response error status.
-
typedef union _netc_cmd_bd netc_cmd_bd_t
The Switch/SI command BD data structure.
-
typedef struct _netc_cmd_bdr_config netc_cmd_bdr_config_t
Configuration for the Switch/SI command BD Ring Configuration.
-
typedef struct _netc_cmd_bdr netc_cmd_bdr_t
The Switch/SI command BD ring handle data structure.
-
typedef struct _netc_tb_common_header netc_tb_common_header_t
Table request data buffer common header.
-
typedef enum _netc_fm_vlan_ud_act netc_fm_vlan_ud_act_t
Frame Modification VLAN Update/Delete Action.
Note
Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame.
-
typedef enum _netc_fm_sqt_act netc_fm_sqt_act_t
Frame Modification Sequence Tag Action.
Note
Must be set to 000b for Ingress frame modification, otherwise misconfiguration error..
-
typedef enum _netc_fm_vlan_ar_act netc_fm_vlan_ar_act_t
Frame Modification VLAN Add/Replace Action.
Note
For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value.
-
typedef enum _netc_tb_eteid_access_mode netc_tb_eteid_access_mode_t
Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode.
Note
The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached
-
typedef enum _netc_tb_ipf_update_action netc_tb_ipf_update_action_t
Ingress Port Filter Table Update Actions.
-
typedef enum _netc_tb_ipf_attr_mask netc_tb_ipf_attr_mask_t
Ingress Port Filter frame attribute mask.
-
typedef enum _netc_tb_ipf_seq_tag netc_tb_ipf_seq_tag_t
Ingress Port Filter frame attribute Sequence Tag Code.
-
typedef enum _netc_tb_ipf_l4_header netc_tb_ipf_l4_header_t
Ingress Port Filter frame attribute L4 Header Code.
-
typedef struct _netc_tb_ipf_keye netc_tb_ipf_keye_t
Ingress Port Filter key element.
-
typedef enum _netc_tb_ipf_forward_action netc_tb_ipf_forward_action_t
Ingress port filter forwarding Action.
-
typedef enum _netc_tb_ipf_filter_action netc_tb_ipf_filter_action_t
Ingress port filter Filter Action.
-
typedef struct _netc_tb_ipf_cfge netc_tb_ipf_cfge_t
Ingress port filter config element.
-
typedef struct _netc_tb_ipf_stse netc_tb_ipf_stse_t
Ingress port filter statistic element.
-
typedef struct _netc_tb_ipf_req_data netc_tb_ipf_req_data_t
Ingress port filter table entry config.
-
typedef struct _netc_tb_ipf_rsp_data netc_tb_ipf_rsp_data_t
Ingress port filter table response data.
-
typedef struct _netc_tb_ipf_data netc_tb_ipf_data_t
Ingress Port filter table data buffer.
-
typedef struct _netc_tb_ipf_config netc_tb_ipf_config_t
Ingress Port filter entry config.
-
typedef enum _netc_tb_isi_key_type netc_tb_isi_key_type
Stream identification table key type.
-
typedef struct _netc_tb_isi_keye netc_tb_isi_keye_t
Stream identification table key element.
-
typedef struct _netc_tb_isi_cfge netc_tb_isi_cfge_t
Stream identification table config element.
-
typedef struct _netc_tb_isi_req_data netc_tb_isi_req_data_t
Stream identification table request data buffer.
-
typedef struct _netc_tb_isi_rsp_data netc_tb_isi_rsp_data_t
Stream identification table request response data buffer.
-
typedef struct _netc_tb_isi_data netc_tb_isi_data_t
Stream identification table data buffer.
-
typedef struct _netc_tb_isi_config netc_tb_isi_config_t
Stream identification table entry config.
-
typedef enum _netc_tb_is_isq_action netc_tb_is_isq_action_t
Ingress Stream table Ingress Sequence Action.
-
typedef enum _netc_tb_is_forward_action netc_tb_is_forward_action_t
Ingress Stream table forwarding Action.
-
typedef enum _netc_tb_is_ctd_mode netc_tb_is_ctd_mode_t
Ingress Stream table Cut-Through Disable mode.
-
typedef netc_tb_eteid_access_mode_t netc_tb_is_oeteid_mode_t
Ingress Stream table Override ET_EID mode.
-
typedef struct _netc_tb_is_cfge netc_tb_is_cfge_t
Ingress Stream table config element.
-
typedef struct _netc_tb_is_req_data netc_tb_is_req_data_t
Ingress Stream table request data buffer.
-
typedef struct _netc_tb_is_rsp_data netc_tb_is_rsp_data_t
Ingress Stream table request response data buffer.
-
typedef struct _netc_tb_is_data netc_tb_is_data_t
Ingress Stream table data buffer.
-
typedef struct _netc_tb_is_config netc_tb_is_config_t
Ingress Stream table entry config.
-
typedef struct _netc_tb_isf_keye netc_tb_isf_keye_t
Ingress Stream Filter table key element.
-
typedef struct _netc_tb_isf_cfge netc_tb_isf_cfge_t
Ingress Stream Filter table config element.
-
typedef struct _netc_tb_isf_req_data netc_tb_isf_req_data_t
Ingress Stream Filter table request data buffer.
-
typedef struct _netc_tb_isf_rsp_data netc_tb_isf_rsp_data_t
Ingress Stream Filter table request response data buffer.
-
typedef struct _netc_tb_isf_data netc_tb_isf_data_t
Ingress Stream Filter table data buffer.
-
typedef struct _netc_tb_isf_config netc_tb_isf_config_t
Ingress Stream Filter table entry config.
-
typedef enum _netc_tb_rp_update_action netc_tb_rp_update_action_t
Rate Policer Table Update Actions.
-
typedef netc_tc_sdu_type_t netc_tb_rp_sdu_type_t
Rate Policer Table Protocol/Service Data Unit Type.
-
typedef struct _netc_tb_rp_cfge netc_tb_rp_cfge_t
Rate Policer table config element.
-
typedef struct _netc_tb_rp_fee netc_tb_rp_fee_t
Rate Policer table Function Enable element.
-
typedef struct _netc_tb_rp_pse netc_tb_rp_pse_t
Rate Policer table Policer State element.
-
typedef struct _netc_tb_rp_stse netc_tb_rp_stse_t
Rate Policer table statistic element.
-
typedef struct _netc_tb_rp_req_data netc_tb_rp_req_data_t
Rate Policer table request data buffer.
-
typedef struct _netc_tb_rp_rsp_data netc_tb_rp_rsp_data_t
Rate Policer table request response data buffer.
-
typedef struct _netc_tb_rp_data netc_tb_rp_data_t
Rate Policer table data buffer.
-
typedef struct _netc_tb_rp_config netc_tb_rp_config_t
Rate Policer table entry config.
-
typedef struct _netc_tb_isc_stse netc_tb_isc_stse_t
Ingress Stream Count table statistic element.
-
typedef struct _netc_tb_isc_req_data netc_tb_isc_req_data_t
Ingress Stream Count table request data buffer.
-
typedef struct _netc_tb_isc_rsp_data netc_tb_isc_rsp_data_t
Ingress Stream Count table request response data buffer.
-
typedef struct _netc_tb_isc_data netc_tb_isc_data_t
Ingress Stream Count table data buffer.
-
typedef enum _netc_tb_sgi_update_action netc_tb_sgi_update_action_t
Stream Gate Instance table Update Actions.
-
typedef netc_tc_sdu_type_t netc_tb_sgi_sdu_type_t
Stream Gate Instance table Protocol/Service Data Unit Type.
-
typedef enum _netc_tb_sgi_state netc_tb_sgi_state_t
Stream Gate Instance State.
-
typedef struct _netc_tb_sgi_cfge netc_tb_sgi_cfge_t
Stream Gate Instance table config element.
-
typedef struct _netc_tb_sgi_acfge netc_tb_sgi_acfge_t
Stream Gate Instance table Admin Configuration element.
-
typedef struct _netc_tb_sgi_icfge netc_tb_sgi_icfge_t
Stream Gate Instance table Initial Configuration element.
-
typedef struct _netc_tb_sgi_sgise netc_tb_sgi_sgise_t
Stream Gate Instance table stream gate instance state element.
-
typedef struct _netc_tb_sgi_req_data netc_tb_sgi_req_data_t
Stream Gate Instance table request data buffer.
-
typedef struct _netc_tb_sgi_rsp_data netc_tb_sgi_rsp_data_t
Stream Gate Instance table request response data buffer.
-
typedef struct _netc_tb_sgi_data netc_tb_sgi_data_t
Stream Gate Instance table data buffer.
-
typedef struct _netc_tb_sgi_config netc_tb_sgi_config_t
Stream Gate Instance table entry config.
-
typedef struct _netc_sgcl_gate_entry netc_sgcl_gate_entry_t
Defines the Stream Gate Control entry structure.
-
typedef struct _netc_tb_sgcl_cfge netc_tb_sgcl_cfge_t
Stream Gate Control List table config element.
-
typedef struct _netc_tb_sgcl_sgclse netc_tb_sgcl_sgclse_t
Stream Gate Control List table Stream Gate Control List State element.
-
typedef struct _netc_tb_sgcl_req_data netc_tb_sgcl_req_data_t
Stream Gate Control List table request data buffer.
-
typedef struct _netc_tb_sgcl_rsp_data netc_tb_sgcl_rsp_data_t
Stream Gate Control List table request response data buffer.
-
typedef struct _netc_tb_sgcl_data netc_tb_sgcl_data_t
Stream Gate Control List table data buffer.
-
typedef struct _netc_tb_sgcl_gcl netc_tb_sgcl_gcl_t
Stream Gate Control List table entry gate control list structure.
-
typedef enum _netc_tb_fm_layer2_act netc_tb_fm_layer2_act_t
Frame Modification table Layer 2 Actions.
Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.
-
typedef enum _netc_tb_fm_mac_header_act netc_tb_fm_mac_header_act_t
Frame Modification table Layer 2 Header MAC Actions.
Note
Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac.
-
typedef enum _netc_tb_fm_vlan_header_act netc_tb_fm_vlan_header_act_t
Frame Modification table Layer 2 VLAN Actions.
Note
For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef enum _netc_tb_fm_outer_vid_act netc_tb_fm_outer_vid_act_t
Frame Modification table Layer 2 outer VLAN VID Actions.
Note
For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef netc_fm_sqt_act_t netc_tb_fm_sqt_act_t
Frame Modification table Sequence Tag Action.
Note
For use kNETC_ReomveTag action, If R-TAG/draft 2.0 R-TAG/HSR tag not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef enum _netc_tb_fm_outer_tpid_act netc_tb_fm_outer_tpid_act_t
Frame Modification table Outer TPID action.
Note
For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef enum _netc_tb_fm_outer_pcp_act netc_tb_fm_outer_pcp_act_t
Frame Modification table Outer PCP action.
Note
For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef enum _netc_tb_fm_outer_dei_act netc_tb_fm_outer_dei_act_t
Frame Modification table Outer DEI action.
Note
For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.
-
typedef enum _netc_tb_fm_payload_act netc_tb_fm_payload_act_t
Frame Modification table Payload Actions.
Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.
-
typedef struct _netc_tb_fm_cfge netc_tb_fm_cfge_t
Frame Modification table config element.
-
typedef struct _netc_tb_fm_req_data netc_tb_fm_req_data_t
Frame Modification table request data buffer.
-
typedef struct _netc_tb_fm_rsp_data netc_tb_fm_rsp_data_t
Frame Modification table request response data buffer.
-
typedef struct _netc_tb_fm_data netc_tb_fm_data_t
Frame Modification table data buffer.
-
typedef struct _netc_tb_fm_config netc_tb_fm_config_t
Frame Modification table entry config.
-
typedef struct _netc_tb_fmd_req_data netc_tb_fmd_req_data_t
Frame Modification Data table request data buffer.
-
typedef struct _netc_tb_fmd_rsp_data netc_tb_fmd_rsp_data_t
Frame Modification Data table request response data buffer.
-
typedef struct _netc_tb_fmd_data netc_tb_fmd_data_t
Frame Modification Data table data buffer.
-
typedef struct _netc_tb_fmd_update_config netc_tb_fmd_update_config_t
Frame Modification data table entry update config.
-
typedef struct _netc_tb_fmd_query_buffer netc_tb_fmd_query_buffer_t
Frame Modification data table entry query data buffer.
-
typedef struct _netc_tb_vf_keye netc_tb_vf_keye_t
Vlan Filter table key element.
-
typedef struct _netc_tb_vf_cfge netc_tb_vf_cfge_t
Vlan Filter table config element.
-
typedef struct _netc_tb_vf_search_criteria netc_tb_vf_search_criteria_t
Vlan Filter table search criteria format.
-
typedef struct _netc_tb_vf_req_data netc_tb_vf_req_data_t
Vlan Filter table request data buffer.
-
typedef struct _netc_tb_vf_rsp_data netc_tb_vf_rsp_data_t
Vlan Filter table request response data buffer.
-
typedef struct _netc_tb_vf_data netc_tb_vf_data_t
Vlan Filter table data buffer.
-
typedef struct _netc_tb_vf_config netc_tb_vf_config_t
Vlan Filter table entry config.
-
typedef enum _netc_tb_fdb_update_action netc_tb_fdb_update_action_t
FDB table Update Actions.
-
typedef netc_tb_eteid_access_mode_t netc_tb_fdb_oeteid_mode_t
FDB table entry defined the egress packet processing actions (will cover the actions which specified in the Egress Treatment table )
-
typedef enum _netc_tb_fdb_ctd_mode netc_tb_fdb_ctd_mode_t
FDB table Cut-Through Disable mode.
-
typedef struct _netc_tb_fdb_keye netc_tb_fdb_keye_t
-
typedef struct _netc_tb_fdb_cfge netc_tb_fdb_cfge_t
FDB table configuration element.
-
typedef struct _netc_tb_fdb_acte netc_tb_fdb_acte_t
FDB table Activity element.
-
typedef enum _netc_tb_fdb_sc_keye_mc netc_tb_fdb_sc_keye_mc_t
FDB table search criteria Key Element Match Criteria.
-
typedef enum _netc_tb_fdb_sc_cfge_mc netc_tb_fdb_sc_cfge_mc_t
FDB table search criteria Configuration Element Match Criteria.
-
typedef enum _netc_tb_fdb_sc_acte_mc netc_tb_fdb_sc_acte_mc_t
FDB table search criteria Activity Element Match Criteria.
-
typedef struct _netc_tb_fdb_search_criteria netc_tb_fdb_search_criteria_t
FDB table search criteria format.
-
typedef struct _netc_tb_fdb_req_data netc_tb_fdb_req_data_t
FDB table request data buffer.
-
typedef struct _netc_tb_fdb_rsp_data netc_tb_fdb_rsp_data_t
FDB table request response data buffer.
-
typedef struct _netc_tb_fdb_data netc_tb_fdb_data_t
FDB table data buffer.
-
typedef struct _netc_tb_fdb_config netc_tb_fdb_config_t
FDB table entry config.
-
typedef enum _netc_tb_l2mcf_key_type netc_tb_l2mcf_key_type_t
L2 IPV4 Multicast Filter table key type.
-
typedef struct _netc_tb_l2mcf_keye netc_tb_l2mcf_keye_t
L2 IPV4 Multicast Filter table key element.
-
typedef enum _etc_tb_l2mcf_sc_keye_mc etc_tb_l2mcf_sc_keye_mc_t
L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria.
-
typedef enum _etc_tb_l2mcf_sc_cfge_mc etc_tb_l2mcf_sc_cfge_mc_t
L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria.
-
typedef enum _etc_tb_l2mcf_sc_acte_mc etc_tb_l2mcf_sc_acte_mc_t
FDB table search criteria Activity Element Match Criteria.
-
typedef netc_tb_fdb_cfge_t netc_tb_l2mcf_cfge_t
L2 IPV4 Multicast Filter table config element.
-
typedef netc_tb_fdb_acte_t netc_tb_l2mcf_acte_t
L2 IPV4 Multicast Filter table activity lement.
-
typedef struct _etc_tb_l2mcf_search_criteria netc_tb_l2mcf_search_criteria_t
L2 IPV4 Multicast Filter table search criteria format.
-
typedef struct _netc_tb_l2mcf_req_data netc_tb_l2mcf_req_data_t
L2 IPV4 Multicast Filter table request data buffer.
-
typedef struct _netc_tb_l2mcf_rsp_data netc_tb_l2mcf_rsp_data_t
L2 IPV4 Multicast Filter table request response data buffer.
-
typedef struct _netc_tb_l2mcf_data netc_tb_l2mcf_data_t
L2 IPV4 Multicast Filter table data buffer.
-
typedef struct _netc_tb_l2mcf_config netc_tb_l2mcf_config_t
L2 IPV4 Multicast Filter table entry config.
-
typedef enum _netc_tb_iseqg_sqtag netc_tb_iseqg_sqtag_t
Sequence Tag Type.
-
typedef struct _netc_tb_iseqg_cfge netc_tb_iseqg_cfge_t
Ingress Sequence Generation table config element.
-
typedef struct _netc_tb_iseqg_sgse netc_tb_iseqg_sgse_t
Ingress Sequence Generation table Sequence generation state element.
-
typedef struct _netc_tb_iseqg_req_data netc_tb_iseqg_req_data_t
Ingress Sequence Generation table request data buffer.
-
typedef struct _netc_tb_iseqg_rsp_data netc_tb_iseqg_rsp_data_t
Ingress Sequence Generation table request response data buffer.
-
typedef struct _netc_tb_iseqg_data netc_tb_iseqg_data_t
Ingress Sequence Generation table data buffer.
-
typedef struct _netc_tb_iseqg_config netc_tb_iseqg_config_t
Ingress Sequence Generation table entry config.
-
typedef enum _netc_tb_iseqg_update_action netc_tb_iseqg_update_action_t
Ingress Sequence Generation Table Update Actions.
-
typedef enum _netc_tb_eseqr_sqtag netc_tb_eseqr_sqtag_t
Egress Sequence Recovery table Sequence Tag Type.
-
typedef struct _netc_tb_eseqr_cfge netc_tb_eseqr_cfge_t
Egress Sequence Recovery table config element.
-
typedef struct _netc_tb_eseqr_stse netc_tb_eseqr_stse_t
Egress Sequence Recovery table statistic element.
-
typedef struct _netc_tb_eseqr_srse netc_tb_eseqr_srse_t
Egress Sequence Recovery table sequence recovery state element.
-
typedef struct _netc_tb_eseqr_req_data netc_tb_eseqr_req_data_t
Egress Sequence Recovery table request data buffer.
-
typedef struct _netc_tb_eseqr_rsp_data netc_tb_eseqr_rsp_data_t
Egress Sequence Recovery table request response data buffer.
-
typedef struct _netc_tb_eseqr_data netc_tb_eseqr_data_t
Egress Sequence Recovery table data buffer.
-
typedef struct _netc_tb_eseqr_config netc_tb_eseqr_config_t
Egress Sequence Recovery table entry config.
-
typedef enum _netc_tb_tgs_entry_id netc_tb_tgs_entry_id_t
Time Gate Scheduling table entry ID for switch and ENETC.
-
typedef enum _netc_tb_tgs_gate_type netc_tb_tgs_gate_type_t
Administrative gate operation type.
-
typedef struct _netc_tgs_gate_entry netc_tgs_gate_entry_t
Defines the Time Gate Scheduling gate control entry structure.
-
typedef struct _netc_tb_tgs_cfge netc_tb_tgs_cfge_t
Time Gate Scheduling table config element.
-
typedef struct _netc_tb_tgs_olse netc_tb_tgs_olse_t
Time Gate Scheduling table statistic element.
-
typedef struct _netc_tb_tgs_req_data netc_tb_tgs_req_data_t
Time Gate Scheduling table request data buffer.
-
typedef struct _netc_tb_tgs_rsp_data netc_tb_tgs_rsp_data_t
Time Gate Scheduling table request response data buffer.
-
typedef struct _netc_tb_tgs_data netc_tb_tgs_data_t
Time Gate Scheduling table data buffer, set with max size.
-
typedef struct _netc_tb_tgs_gcl netc_tb_tgs_gcl_t
Time Gate Scheduling table entry gate control list structure.
-
typedef enum _netc_tb_et_efm_mode netc_tb_et_efm_mode_t
Egress Frame Modification entry mode.
-
typedef enum _netc_tb_et_esq_act netc_tb_et_esq_act_t
Egress Sequence Actions.
-
typedef enum _netc_tb_et_ec_act netc_tb_et_ec_act_t
Egress Counter Action.
-
typedef struct _netc_tb_et_cfge netc_tb_et_cfge_t
Egress Treatment table config element.
-
typedef struct _netc_tb_et_req_data netc_tb_et_req_data_t
Egress Treatment table request data buffer.
-
typedef struct _netc_tb_et_rsp_data netc_tb_et_rsp_data_t
Egress Treatment table request response data buffer.
-
typedef struct _netc_tb_et_data netc_tb_et_data_t
Egress Treatment table data buffer.
-
typedef struct _netc_tb_et_config netc_tb_et_config_t
Egress Treatment table entry config.
-
typedef enum _netc_tb_etmcq_update_action netc_tb_etmcq_update_action_t
ETM Class Queue table Update Actions.
-
typedef struct _netc_tb_etmcq_cfge netc_tb_etmcq_cfge_t
ETM Class Queue table config element.
-
typedef struct _netc_tb_etmcq_stse netc_tb_etmcq_stse_t
ETM Class Queue table statistic element.
-
typedef struct _netc_tb_etmcq_req_data netc_tb_etmcq_req_data_t
ETM Class Queue table request data buffer.
-
typedef struct _netc_tb_etmcq_rsp_data netc_tb_etmcq_rsp_data_t
ETM Class Queue table request response data buffer.
-
typedef struct _netc_tb_etmcq_data netc_tb_etmcq_data_t
ETM Class Queue table data buffer.
-
typedef struct _netc_tb_etmcq_config netc_tb_etmcq_config_t
ETM Class Queue table entry config.
-
typedef enum _netc_tb_etmcs_entry_id netc_tb_etmcs_entry_id_t
ETM Class Scheduler table entry ID.
-
typedef enum _netc_tb_etmcs_ca_assg netc_tb_etmcs_ca_assg_t
ETM Class Scheduler table Class queue assignment to scheduler inputs mode.
-
typedef struct _netc_tb_etmcs_cfge netc_tb_etmcs_cfge_t
ETM Class Scheduler table config element.
-
typedef struct _netc_tb_etmcs_req_data netc_tb_etmcs_req_data_t
ETM Class Scheduler table request data buffer.
-
typedef struct _netc_tb_etmcs_rsp_data netc_tb_etmcs_rsp_data_t
ETM Class Scheduler table request response data buffer.
-
typedef struct _netc_tb_etmcs_data netc_tb_etmcs_data_t
ETM Class Scheduler table data buffer.
-
typedef struct _netc_tb_etmcs_config netc_tb_etmcs_config_t
ETM Class Scheduler table entry config.
-
typedef struct _netc_tb_etmcg_cfge netc_tb_etmcg_cfge_t
ETM Congestion Group table config element.
-
typedef struct _netc_tb_etmcg_stse netc_tb_etmcg_stse_t
ETM Congestion Group table statistic element.
-
typedef struct _netc_tb_etmcg_req_data netc_tb_etmcg_req_data_t
ETM Congestion Group table request data buffer.
-
typedef struct _netc_tb_etmcg_rsp_data netc_tb_etmcg_rsp_data_t
ETM Congestion Group table request response data buffer.
-
typedef struct _netc_tb_etmcg_data netc_tb_etmcg_data_t
ETM Congestion Group table data buffer.
-
typedef struct _netc_tb_etmcg_config netc_tb_etmcg_config_t
ETM Congestion Group table entry config.
-
typedef struct _netc_tb_ec_stse netc_tb_ec_stse_t
Egress Count table statistic element.
-
typedef struct _netc_tb_ec_req_data netc_tb_ec_req_data_t
Egress Count table request data buffer.
-
typedef struct _netc_tb_ec_rsp_data netc_tb_ec_rsp_data_t
Egress Count table request response data buffer.
-
typedef struct _netc_tb_ec_data netc_tb_ec_data_t
Egress Count table data buffer.
-
typedef enum _netc_tb_bp_fc_cfg netc_tb_bp_fc_cfg_t
Buffer Pool Flow Control (FC) Configuration.
-
typedef struct _netc_tb_bp_cfge netc_tb_bp_cfge_t
Buffer Pool table config element.
-
typedef struct _netc_tb_bp_bpse netc_tb_bp_bpse_t
Buffer Pool table State Element Data.
-
typedef struct _netc_tb_bp_req_data netc_tb_bp_req_data_t
Buffer Pool table request data buffer.
-
typedef struct _netc_tb_bp_rsp_data netc_tb_bp_rsp_data_t
Buffer Pool table request response data buffer.
-
typedef struct _netc_tb_bp_data netc_tb_bp_data_t
Buffer Pool table data buffer.
-
typedef struct _netc_tb_bp_config netc_tb_bp_config_t
Buffer Pool table entry config.
-
typedef struct _netc_tb_sbp_cfge netc_tb_sbp_cfge_t
Shared Buffer Pool table config element.
-
typedef struct _netc_tb_sbp_sbpse netc_tb_sbp_sbpse_t
Shared Buffer Pool table State Element Data.
-
typedef struct _netc_tb_sbp_req_data netc_tb_sbp_req_data_t
Shared Buffer Pool table request data buffer.
-
typedef struct _netc_tb_sbp_rsp_data netc_tb_sbp_rsp_data_t
Shared Buffer Pool table request response data buffer.
-
typedef struct _netc_tb_sbp_data netc_tb_sbp_data_t
Shared Buffer Pool table data buffer.
-
typedef struct _netc_tb_sbp_config netc_tb_sbp_config_t
Shared Buffer Pool table entry config.
-
typedef union _netc_tb_data_buffer netc_tb_data_buffer_t
Table common data buffer.
-
typedef struct _netc_cbdr_hw netc_cbdr_hw_t
Register group for SI/Switch command bd ring.
-
typedef struct _netc_cbdr_handle netc_cbdr_handle_t
Handle for common part of EP/Switch NTMP.
-
status_t NETC_CmdBDRInit(netc_cbdr_hw_t *base, const netc_cmd_bdr_config_t *config)
Initialize the command BD ring.
- Parameters:
base –
config –
- Returns:
kStatus_Success
- Returns:
kStatus_Fail
-
status_t NETC_CmdBDRDeinit(netc_cbdr_hw_t *base)
Deinitialize the command BD ring.
- Parameters:
base –
- Returns:
kStatus_Success
-
status_t NETC_CmdBDSendCommand(netc_cbdr_hw_t *base, netc_cmd_bdr_t *cbdr, netc_cmd_bd_t *cbd, netc_cbd_version_t version)
Send the Command Buffer Descriptor to operate on a NTMP table.
- Parameters:
base –
cbdr –
cbd –
version –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddIPFTableEntry(netc_cbdr_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)
Add entry into the ingress Port Filter Table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_UpdateIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)
Update entry in the ingress Port Filter Table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_config_t *config)
Query entry in the ingress Port Filter Table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete an entry in the ingress Port Filter Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_ResetIPFMatchCounter(netc_cbdr_handle_t *handle, uint32_t entryID)
Reset the counter of an ingress port filter Table entry.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetIPFMatchedCount(netc_cbdr_handle_t *handle, uint32_t entryID, uint64_t *count)
Get the matched count of an ingress port filter Table entry.
- Parameters:
handle –
entryID –
count –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddISITableEntry(netc_cbdr_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)
Add entry into Ingress Stream Identification table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete an entry in Ingress stream identification table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isi_config_t *config)
Query Ingress Stream Identification table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp)
Query Ingress Stream Identification table with key.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddOrUpdateISTableEntry(netc_cbdr_handle_t *handle, netc_tb_is_config_t *config, bool isAdd)
Add or update entry in Ingress Stream table.
- Parameters:
handle –
config –
isAdd –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_is_config_t *config)
Query Ingress Stream table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete an entry in Ingress stream table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)
Add entry into ingress stream filter table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_UpdateISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)
Update entry into ingress stream filter table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete an entry in Ingress stream filter table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_keye_t *keye, netc_tb_isf_rsp_data_t *rsp)
Query entry from the Ingress stream filter table.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddISCTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Add entry in ingress stream count table.
- Parameters:
handle –
entryID –
- Returns:
status_t
-
status_t NETC_GetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)
Get ingress stream count statistic.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_ResetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID)
Reset the count of the ingress stream count.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddOrUpdateSGITableEntry(netc_cbdr_handle_t *handle, netc_tb_sgi_config_t *config, bool isAdd)
Add or update entry in stream gate instance table.
- Parameters:
handle –
config –
isAdd –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete entry in the stream gate instance table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *statis)
Get statistic of specified stream gate instance table entry.
- Parameters:
handle –
entryID –
statis –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp)
Query entry from the stream gate instance table.
- Parameters:
handle –
entryID –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddSGCLTableEntry(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *config)
Add entry into Stream Gate Control List Table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelSGCLTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete entry of Stream Gate Control List Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetSGCLGateList(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)
Get Stream Gate Control List Table entry gate control list.
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetSGCLState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)
Get state (ref count) for Stream Gate Control List table entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_QueryRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp)
Query entry from the Rate Policer table.
- Parameters:
handle –
entryID –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_AddOrUpdateRPTableEntry(netc_cbdr_handle_t *handle, netc_tb_rp_config_t *config, netc_tb_cmd_t cmd)
Add or update entry in Rate Policer table.
- Parameters:
handle –
config –
cmd –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_DelRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Delete entry in the Rate Policer table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetRPStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)
Get statistic of specified Rate Policer table entry.
- Parameters:
handle –
entryID –
statis –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_ResetMRRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)
Reset mark red parameter of specified Rate Policer table entry.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_ConfigTGSAdminList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *config)
Config the QBV (Time Gate Scheduling)
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t NETC_GetTGSOperationList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)
Get time gate table operation list.
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
NETC_FD_EID_ENCODE_OPTION_0(entryId)
Frame Modification Entry ID encode options.
Note
sqta should be netc_fm_sqt_act_t type, vuda should be netc_fm_vlan_ud_act_t type and vara should be netc_fm_vlan_ar_act_t type.
-
NETC_FD_EID_ENCODE_OPTION_1(sqta, vuda)
-
NETC_FD_EID_ENCODE_OPTION_2(vara, vid)
-
NETC_ISI_VLAN_FRAME_KEY(valid, pcp, vid)
2 Bytes VLAN field which may added to the frame Key
-
NETC_TB_SGCL_MAX_ENTRY
Stream Gate Control List Table maximum gate control list length.
-
NETC_TB_FMD_UPDATE_CONFIG_LENGTH(x)
TFrame Modification Data table update config Data Buffer length, x is the number of update data bytes.
-
NETC_TB_TGS_MAX_ENTRY
Time Gate Scheduling Table maximum gate control list length (TGSTCAPR[MAX_GCL_LEN])
-
NETC_TB_ETM_CQ_ENTRY_ID(portID, cqID)
ETM Class Queue table entry ID macro, cqID is represents the Class Queue ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4.
-
NETC_TB_ETM_CG_ENTRY_ID(portID, cgID)
ETM Congestion Group table entry ID macro, cgID is represents the Congestion Group ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4.
-
NETC_TB_BP_THRESH(mant, exp)
Buffer pool and shared buffer pool threshold macro, the threshold = MANT*2^EXP, uint is internal memory words (avergae of 20 bytes each)
-
union _netc_cmd_bd
- #include <fsl_netc.h>
The Switch/SI command BD data structure.
-
struct _netc_cmd_bdr_config
- #include <fsl_netc.h>
Configuration for the Switch/SI command BD Ring Configuration.
Public Members
-
netc_cmd_bd_t *bdBase
BDR base address which shall be 128 bytes aligned
-
uint16_t bdLength
Size of BD ring which shall be multiple of 8 BD
-
bool enCompInt
Enable/Disable command BD completion interrupt
-
netc_cmd_bd_t *bdBase
-
struct _netc_cmd_bdr
- #include <fsl_netc.h>
The Switch/SI command BD ring handle data structure.
Public Members
-
netc_cmd_bd_t *bdBase
BDR base address which shall be 128 bytes aligned
-
uint16_t bdLength
Size of BD ring
-
uint16_t producerIndex
Current index for execution.
-
uint16_t cleanIndex
Current index for cleaning.
-
bool bdrEnable
Current command BD ring is enable or not.
-
netc_cmd_bd_t *bdBase
-
struct _netc_tb_common_header
- #include <fsl_netc.h>
Table request data buffer common header.
Public Members
-
uint32_t updateActions
Update Actions
-
uint32_t queryActions
Query Actions
-
uint32_t updateActions
-
struct _netc_tb_ipf_keye
- #include <fsl_netc.h>
Ingress Port Filter key element.
Public Members
-
uint16_t precedence
Precedence value of an entry
-
struct _netc_tb_ipf_keye frameAttr
Frame Attribute flags
-
uint16_t frameAttrMask
Frame attribute mask, set with OR of netc_tb_ipf_attr_mask_t
-
uint16_t dscp
Differentiated Services Code Point
-
uint16_t dscpMask
Differentiated Services Code Point Mask
-
uint16_t srcPort
Source Port ID
-
uint16_t srcPortMask
Source Port ID Mask
-
uint16_t outerVlanTCI
Outer VLAN Tag Control Information
-
uint16_t outerVlanTCIMask
Outer VLAN Tag Control Information Mask
-
uint8_t dmac[6]
Destination MAC Address
-
uint8_t dmacMask[6]
Destination MAC Address Mask
-
uint8_t smac[6]
Source MAC Address
-
uint8_t smacMask[6]
Source MAC Address Mask
-
uint16_t innerVlanTCI
Inner VLAN Tag Control Information
-
uint16_t innerVlanTCIMask
Inner VLAN Tag Control Information Mask
-
uint16_t etherType
2-byte EtherType
-
uint16_t etherTypeMask
EtherType Mask
-
uint8_t IPProtocol
IP Protocol
-
uint8_t IPProtocolMask
IP Protocol Mask
-
uint8_t srcIPAddr[16]
IP Source Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address
-
uint8_t srcIPAddrMask[16]
IP Source Address Mask
-
uint16_t l4SrcPort
L4 Source Port
-
uint16_t l4SrcPortMask
L4 Source Port Mask
-
uint8_t destIPAddr[16]
IP Destination Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address
-
uint8_t destIPAddrMask[16]
IP Destination Address Mask
-
uint16_t l4DestPort
L4 Destination Port
-
uint16_t l4DestPortMask
L4 Destination Port Mask
-
uint16_t precedence
-
struct _netc_tb_ipf_cfge
- #include <fsl_netc.h>
Ingress port filter config element.
Public Members
-
uint32_t ipv
Internal Priority Value
-
uint32_t oipv
Overwrite IPV
-
uint32_t dr
Drop Resilience
-
uint32_t odr
Overwrite DR
-
netc_tb_ipf_forward_action_t fltfa
Filter Forwarding action.
-
uint32_t imire
Ingress Mirroring Enable
-
uint32_t wolte
Wake-onLAN trigger enable
-
netc_tb_ipf_filter_action_t flta
FIlter Action.
-
uint32_t rpr
Relative Precedent Resolution
-
uint32_t ctd
Cut through disable.
-
netc_host_reason_t hr
Host Reason metadata when frame is redirected/copied to the switch management port
-
uint32_t timecape
Timestam capture enable
-
uint32_t fltaTgt
Target for selected switch forwarding action or filter action
-
uint32_t ipv
-
struct _netc_tb_ipf_stse
- #include <fsl_netc.h>
Ingress port filter statistic element.
Public Members
-
uint32_t matchCount[2]
A count of how many times this entry has been matched.
-
uint32_t matchCount[2]
-
struct _netc_tb_ipf_req_data
- #include <fsl_netc.h>
Ingress port filter table entry config.
-
struct _netc_tb_ipf_rsp_data
- #include <fsl_netc.h>
Ingress port filter table response data.
Public Members
-
uint32_t entryID
Present only for commands which perform a query
-
netc_tb_ipf_keye_t keye
Present only for commands which perform a query
-
netc_tb_ipf_stse_t stse
Present only for commands which perform a query
-
netc_tb_ipf_cfge_t cfge
Present only for commands which perform a query
-
uint32_t entryID
-
struct _netc_tb_ipf_data
- #include <fsl_netc.h>
Ingress Port filter table data buffer.
-
struct _netc_tb_ipf_config
- #include <fsl_netc.h>
Ingress Port filter entry config.
-
struct _netc_tb_isi_keye
- #include <fsl_netc.h>
Stream identification table key element.
Public Members
-
netc_tb_isi_key_type keyType
Define the key type used for the current isi entry
-
uint8_t srcPortID
Source Port ID, used when kc portp filed is 1. Only for SWITCH
-
uint8_t spm
Source Port Masquerading, used when kc spm filed is 1. Only for SWITCH
-
uint8_t framekey[16]
Frame portion of the key.
-
netc_tb_isi_key_type keyType
-
struct _netc_tb_isi_cfge
- #include <fsl_netc.h>
Stream identification table config element.
Public Members
-
uint32_t iSEID
Ingress stream entry ID, 0xFFFFFFFF means NULL
-
uint32_t iSEID
-
struct _netc_tb_isi_req_data
- #include <fsl_netc.h>
Stream identification table request data buffer.
-
struct _netc_tb_isi_rsp_data
- #include <fsl_netc.h>
Stream identification table request response data buffer.
Public Members
-
uint32_t entryID
Only present for query command
-
netc_tb_isi_keye_t keye
Only present for query command
-
netc_tb_isi_cfge_t cfge
Only present for query command
-
uint32_t entryID
-
struct _netc_tb_isi_data
- #include <fsl_netc.h>
Stream identification table data buffer.
-
struct _netc_tb_isi_config
- #include <fsl_netc.h>
Stream identification table entry config.
-
struct _netc_tb_is_cfge
- #include <fsl_netc.h>
Ingress Stream table config element.
Public Members
-
uint32_t sfe
Stream Filtering Enable
-
uint32_t ipv
Internal Priority Value, active when opiv is set to 1
-
uint32_t oipv
Override internal priority value
-
uint32_t dr
Drop Resilience, active when odr is set to 1
-
uint32_t odr
Overwrite DR
-
uint32_t imire
Ingress Mirroring Enable, not applicable to ENETC
-
uint32_t timecape
Timestamp Capture Enable, not applicable to ENETC
-
uint32_t sppd
Source Port Pruning Disable, not applicable to ENETC
-
netc_tb_is_isq_action_t isqa
Ingress Sequence Action, not applicable to ENETC
-
uint32_t orp
Override Rate Policer ID
-
uint32_t osgi
Override stream gate instance entry id (default is NULL)
-
netc_host_reason_t hr
Host Reason when frame is redirected (fa = 01b) to the switch management port or copied to the switch management port (fa = 100b or 101b), value specified has to be a software defined Host Reason (8-15).
-
netc_tb_is_forward_action_t fa
Forwad Option
-
netc_tc_sdu_type_t sduType
Service Data Unit Type to user for MSDU
-
uint32_t msdu
Maximum Service Data Unit
-
uint32_t ifmeLenChange
Ingress Frame Modification Entry Frame Length Change, specified in unit of bytes using a 2’s complement notation
-
uint32_t eport
Egress Port which need do egress packet processing, active when oeteid is set to 1, not applicable to ENETC
-
netc_tb_is_oeteid_mode_t oETEID
Override ET_EID (Egress Treatment table entry, which specified egress packet processing actions)
-
netc_tb_is_ctd_mode_t ctd
Cut-Through Disable mode, valid if fa = 010b ~ 101b
-
uint32_t isqEID
Ingress Sequence Generation Entry ID, Valid when isqa is set to 1. 0xFFFF_FFFF is NULL. Not applicable to ENETC
-
uint32_t rpEID
Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL
-
uint32_t sgiEID
Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL
-
uint32_t ifmEID
Ingress Frame Modification Entry ID. 0xFFFF_FFFF is NULL
-
uint32_t etEID
Base Egress Treatment Entry ID for primary Egress Treatment group, Valid alid if fa = 010b ~ 101b. 0xFFFF_FFFF is NULL. Not applicable to ENETC
-
uint32_t iscEID
Ingress Stream counter Index. 0xFFFF_FFFF is NULL.
-
uint32_t ePortBitmap
Egress Port bitmap, identifies the ports to which the frame is to be forwarding or ET applicability port bitmap when oETEID = 10b. Not applicable to ENETC
-
uint32_t siMap
Station Interface Map, only valid for ENETC function when fa field is set to 10b
-
uint32_t sfe
-
struct _netc_tb_is_req_data
- #include <fsl_netc.h>
Ingress Stream table request data buffer.
Public Members
-
netc_tb_is_cfge_t cfge
Only perform for update or add command
-
netc_tb_is_cfge_t cfge
-
struct _netc_tb_is_rsp_data
- #include <fsl_netc.h>
Ingress Stream table request response data buffer.
Public Members
-
uint32_t entryID
Only perform for query command
-
netc_tb_is_cfge_t cfge
Only perform for query command
-
uint32_t entryID
-
struct _netc_tb_is_data
- #include <fsl_netc.h>
Ingress Stream table data buffer.
-
struct _netc_tb_is_config
- #include <fsl_netc.h>
Ingress Stream table entry config.
-
struct _netc_tb_isf_keye
- #include <fsl_netc.h>
Ingress Stream Filter table key element.
Public Members
-
uint32_t isEID
Ingress Stream Entry ID
-
uint8_t pcp
Priority Code Point, Outer VLAN TAG PCP of the received frame
-
uint32_t isEID
-
struct _netc_tb_isf_cfge
- #include <fsl_netc.h>
Ingress Stream Filter table config element.
Public Members
-
uint32_t ipv
Internal Priority Value, active when opiv is set to 1
-
uint32_t oipv
Override internal priority value
-
uint32_t dr
Drop Resilience, active when odr is set to 1
-
uint32_t odr
Overwrite DR
-
uint32_t imire
Ingress Mirroring Enable, not applicable to ENETC
-
uint32_t timecape
Timestamp Capture Enable, not applicable to ENETC
-
uint32_t osgi
Override stream gate instance entry id
-
uint32_t ctd
Cut-Through Disable, will disable cut-through for all destined ports when set 1, not applicable to ENETC
-
uint32_t orp
Override Rate Policer (instance) ID
-
netc_tc_sdu_type_t sduType
Service Data Unit Type to user for MSDU
-
uint32_t msdu
Maximum Service Data Unit
-
uint32_t rpEID
Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL
-
uint32_t sgiEID
Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL
-
uint32_t iscEID
Ingress Stream counter Index. 0xFFFF_FFFF is NULL.
-
uint32_t ipv
-
struct _netc_tb_isf_req_data
- #include <fsl_netc.h>
Ingress Stream Filter table request data buffer.
Public Members
-
netc_tb_isf_cfge_t cfge
Only perform for update or add command
-
netc_tb_isf_cfge_t cfge
-
struct _netc_tb_isf_rsp_data
- #include <fsl_netc.h>
Ingress Stream Filter table request response data buffer.
Public Members
-
uint32_t entryID
Only perform for query command
-
netc_tb_isf_keye_t keye
Only perform for query command
-
netc_tb_isf_cfge_t cfge
Only perform for query command
-
uint32_t entryID
-
struct _netc_tb_isf_data
- #include <fsl_netc.h>
Ingress Stream Filter table data buffer.
-
struct _netc_tb_isf_config
- #include <fsl_netc.h>
Ingress Stream Filter table entry config.
-
struct _netc_tb_rp_cfge
- #include <fsl_netc.h>
Rate Policer table config element.
Public Members
-
uint32_t cir
Committed information Rate
-
uint32_t cbs
Commited Burst Size
-
uint32_t eir
Excess information Rate
-
uint32_t ebs
Excess Burst Size
-
uint32_t mren
Mark All Frames Red Enable, Not valid when ndor=1
-
uint32_t doy
Drop on Yellow enable
-
uint32_t cm
Color mode, 0b = Color blind, 1b = Color aware
-
uint32_t cf
Coupling flag, enables coupling the Committed (C) bucket and Excess (E) bucket
-
uint32_t ndor
No drop on red
-
netc_tb_rp_sdu_type_t sduType
Service Data Unit Type
-
uint32_t __pad0__
Reserved
-
uint32_t cir
-
struct _netc_tb_rp_fee
- #include <fsl_netc.h>
Rate Policer table Function Enable element.
Public Members
-
uint8_t fen
Function Enable
-
uint8_t __pad0__
Reserved
-
uint8_t fen
-
struct _netc_tb_rp_pse
- #include <fsl_netc.h>
Rate Policer table Policer State element.
Public Members
-
uint8_t mr
Mark Red Flag
-
uint8_t res0
Reserved
-
uint8_t mr
-
struct _netc_tb_rp_stse
- #include <fsl_netc.h>
Rate Policer table statistic element.
Public Members
-
uint32_t byteCount[2]
Number of bytes received by the rate policer instance
-
uint32_t dropFrames[2]
Number of frames dropped by the rate policer instance
-
uint32_t dr0GrnFrames[2]
Number of frames marked green with DR=0 by the rate policer instance
-
uint32_t dr1GrnFrames[2]
Number of frames marked green with DR=1 by the rate policer instance
-
uint32_t dr2GrnFrames[2]
Number of frames marked yellow with DR=2 by the rate policer instance
-
uint32_t remarkYlwFrames[2]
Number of frames re-marked from green to yellow by the rate policer instance
-
uint32_t dr3RedFrames[2]
Number of frames marked red with DR=3 by the rate policer instance
-
uint32_t remarkRedFrames[2]
Number of frames re-marked from green or yellow to red by the rate policer instance
-
uint32_t lts
Last timestamp
-
uint32_t bci
Committed token bucket contents, integer portion (31 bits)
-
uint32_t bcs
Committed token bucket sign bit (1 bit)
-
uint32_t bcf
Committed token bucket contents, fractional portion (31 bits)
-
uint32_t bei
Excess token bucket contents, integer portion (32 bits)
-
uint32_t bef
Excess token bucket contents, fractional portion (31 bits)
-
uint32_t bes
Committed token bucket sign bit
-
uint32_t byteCount[2]
-
struct _netc_tb_rp_req_data
- #include <fsl_netc.h>
Rate Policer table request data buffer.
-
struct _netc_tb_rp_rsp_data
- #include <fsl_netc.h>
Rate Policer table request response data buffer.
Public Members
-
uint32_t entryID
Present only for commands which perform a query
-
netc_tb_rp_stse_t stse
Present only for commands which perform a query
-
uint32_t entryID
-
struct _netc_tb_rp_data
- #include <fsl_netc.h>
Rate Policer table data buffer.
-
struct _netc_tb_rp_config
- #include <fsl_netc.h>
Rate Policer table entry config.
-
struct _netc_tb_isc_stse
- #include <fsl_netc.h>
Ingress Stream Count table statistic element.
Public Members
-
uint32_t rxCount
Receive Count
-
uint32_t msduDropCount
MSDU Drop Count
-
uint32_t policerDropCount
Policer Drop Count
-
uint32_t sgDropCount
Stream Gating Drop Count
-
uint32_t rxCount
-
struct _netc_tb_isc_req_data
- #include <fsl_netc.h>
Ingress Stream Count table request data buffer.
-
struct _netc_tb_isc_rsp_data
- #include <fsl_netc.h>
Ingress Stream Count table request response data buffer.
-
struct _netc_tb_isc_data
- #include <fsl_netc.h>
Ingress Stream Count table data buffer.
-
struct _netc_tb_sgi_cfge
- #include <fsl_netc.h>
Stream Gate Instance table config element.
Public Members
-
uint8_t oexen
Octets Exceeded (Gate Closed Due To Octets Exceeded function) Enable
-
uint8_t irxen
Invalid Receive (Gate Closed Due To Invalid Rx) Enable
-
netc_tb_sgi_sdu_type_t sduType
The type of PDU/SDU for Interval Octets Maximum check for Gate Entry
-
uint8_t oexen
-
struct _netc_tb_sgi_acfge
- #include <fsl_netc.h>
Stream Gate Instance table Admin Configuration element.
Public Members
-
uint32_t adminSgclEID
Administrative Stream Gate Control List Entry ID, 0xFFFFFFFF is NULL
-
uint32_t adminBaseTime[2]
Admin Base Time
-
uint32_t adminCycleTimeExt
Admin Cycle Time Extension
-
uint32_t adminSgclEID
-
struct _netc_tb_sgi_icfge
- #include <fsl_netc.h>
Stream Gate Instance table Initial Configuration element.
Public Members
-
uint8_t ipv
Internal Priority Value (IPV), Valid if oipv is 1
-
uint8_t oipv
Override frame IPV, otherwise the IPV value is determined by the stream gate control list entry
-
uint8_t gst
Specifies Gate State before the administrative stream gate control list takes affect, 0b = Closed; 1b = Open
-
uint8_t ctd
Specifies Cut Through disable status before the administrative stream gate control list takes affect , Not applicable to ENETC function
-
uint8_t ipv
-
struct _netc_tb_sgi_sgise
- #include <fsl_netc.h>
Stream Gate Instance table stream gate instance state element.
Public Members
-
uint32_t operSgclEID
Operational Stream Gate Control List Entry ID
-
uint32_t configChangeTime[2]
Configuration Change Time
-
uint32_t operBaseTime[2]
Operational Base Time
-
uint32_t operCycleTimeExt
Oper Cycle Time Extension
-
uint32_t oex
Octets Exceeded Flag
-
uint32_t irx
Invalid Receive Flag
-
netc_tb_sgi_state_t state
Current Gate Instance State
-
uint32_t operSgclEID
-
struct _netc_tb_sgi_req_data
- #include <fsl_netc.h>
Stream Gate Instance table request data buffer.
-
struct _netc_tb_sgi_rsp_data
- #include <fsl_netc.h>
Stream Gate Instance table request response data buffer.
-
struct _netc_tb_sgi_data
- #include <fsl_netc.h>
Stream Gate Instance table data buffer.
-
struct _netc_tb_sgi_config
- #include <fsl_netc.h>
Stream Gate Instance table entry config.
-
struct _netc_sgcl_gate_entry
- #include <fsl_netc.h>
Defines the Stream Gate Control entry structure.
Public Members
-
uint32_t timeInterval
Time Interval for Gate Entry
-
uint32_t iom
Interval Octets Maximum for Gate Entry, specifies the maximum bytes (octets) allowed to pass (open), valid if iomen = 1
-
uint32_t ipv
Internal Priority Value for Gate Entry
-
uint32_t oipv
Override Internal Priority Value for Gate Entry
-
uint32_t ctd
Cut Through Disable for Gate Entry
-
uint32_t iomen
Interval Octet Maximum Enabled for Gate Entry, 0b = Don’track count, 1b = Track count
-
uint32_t gtst
Gate State for Gate Entry, 0b = Closed; 1b = Open
-
uint32_t timeInterval
-
struct _netc_tb_sgcl_cfge
- #include <fsl_netc.h>
Stream Gate Control List table config element.
Public Members
-
uint32_t cycleTime
Cycle Time
-
uint8_t listLength
List Length
-
uint16_t extOipv
Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value
-
uint16_t extIpv
List Extension Internal Priority Value, valid if extOipv = 1
-
uint16_t extCtd
Extension Cut Through Disabled, 0b = No action, 1b = Disabled
-
uint16_t extGtst
Extension Gate State, 0b = closed, 1b = Open
-
uint32_t cycleTime
-
struct _netc_tb_sgcl_sgclse
- #include <fsl_netc.h>
Stream Gate Control List table Stream Gate Control List State element.
Public Members
-
uint8_t refCount
Reference Count, 1 indicates that the gate control list is an administrative or an operational gate control list in a stream gate instance
-
uint8_t refCount
-
struct _netc_tb_sgcl_req_data
- #include <fsl_netc.h>
Stream Gate Control List table request data buffer.
-
struct _netc_tb_sgcl_rsp_data
- #include <fsl_netc.h>
Stream Gate Control List table request response data buffer.
-
struct _netc_tb_sgcl_data
- #include <fsl_netc.h>
Stream Gate Control List table data buffer.
-
struct _netc_tb_sgcl_gcl
- #include <fsl_netc.h>
Stream Gate Control List table entry gate control list structure.
Public Members
-
uint16_t extOipv
Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value
-
uint16_t extIpv
List Extension Internal Priority Value, valid if extOipv = 1
-
uint16_t extCtd
Extension Cut Through Disabled, 0b = No action, 1b = Disabled
-
uint16_t extGtst
Extension Gate State, 0b = closed, 1b = Open
-
uint32_t cycleTime
Cycle Time
-
uint32_t numEntries
Control List entry numbers
-
netc_sgcl_gate_entry_t *gcList
Pointer to stream gate control list array
-
uint16_t extOipv
-
struct _netc_tb_fm_cfge
- #include <fsl_netc.h>
Frame Modification table config element.
Public Members
-
netc_tb_fm_layer2_act_t l2Act
Layer 2 Actions
-
netc_tb_fm_mac_header_act_t macHdrAct
Layer 2 Header MAC Actions
-
netc_tb_fm_vlan_header_act_t vlanHdrAct
Layer 2 VLAN Actions
-
netc_tb_fm_outer_vid_act_t outerVidAct
Outer VID Actions
-
netc_tb_fm_sqt_act_t sqtAct
Sequence Tag Action, Not applicable for ingress frame modifications
-
uint16_t smacPort
Source MAC Address Register Port, valid if macHdrAct=010b,011b,100b
-
uint8_t dmac[6]
Destination MAC Address, valid if macHdrAct = 011b,101b
-
uint32_t outerVlanID
Outer VLAN VID, valid if outerVidAct = 01b
-
uint32_t outerVlanPcp
Outer VLAN PCP, valid if outerPcpAct = 01b
-
uint32_t outerVlanDei
Outer VLAN DEI, valid if outerDeiAct = 01b
-
netc_tb_fm_outer_tpid_act_t outerTpidAct
Outer TPID action
-
netc_tb_fm_outer_pcp_act_t outerPcpAct
Outer PCP action
-
netc_tb_fm_outer_dei_act_t outerDeiAct
Outer DEI action
-
netc_tb_fm_payload_act_t pldAct
Payload Actions, Not applicable for ingress frame modifications
-
uint8_t pldOffset
Payload Offset, valid if outerPldAct = 010b
-
uint16_t fmdBytes
Frame Modification Bytes, valid if outerPldAct = 001b,010b or l2Act = 1b
-
uint32_t fmdEID
Frame Modification Data Entry ID, valid if outerPldAct = 001b,010b or l2Act = 1b. 0xFFFF is null pointer
-
netc_tb_fm_layer2_act_t l2Act
-
struct _netc_tb_fm_req_data
- #include <fsl_netc.h>
Frame Modification table request data buffer.
-
struct _netc_tb_fm_rsp_data
- #include <fsl_netc.h>
Frame Modification table request response data buffer.
-
struct _netc_tb_fm_data
- #include <fsl_netc.h>
Frame Modification table data buffer.
-
struct _netc_tb_fm_config
- #include <fsl_netc.h>
Frame Modification table entry config.
-
struct _netc_tb_fmd_req_data
- #include <fsl_netc.h>
Frame Modification Data table request data buffer.
Public Members
-
uint8_t cfge[]
Configuration Element Data size is variable
-
uint8_t cfge[]
-
struct _netc_tb_fmd_rsp_data
- #include <fsl_netc.h>
Frame Modification Data table request response data buffer.
Public Members
-
uint8_t cfge[]
Configuration Element Data size is variable
-
uint8_t cfge[]
-
struct _netc_tb_fmd_data
- #include <fsl_netc.h>
Frame Modification Data table data buffer.
-
struct _netc_tb_fmd_update_config
- #include <fsl_netc.h>
Frame Modification data table entry update config.
Public Members
-
uint32_t res
Hold for request->commonHeader
-
uint8_t cfge[]
Configuration Element Data size is variable
-
uint32_t res
-
struct _netc_tb_fmd_query_buffer
- #include <fsl_netc.h>
Frame Modification data table entry query data buffer.
Public Members
-
uint32_t entryID
EntryID of the queried entry
-
uint8_t cfge[]
Configuration Element Data size is variable
-
uint32_t entryID
-
struct _netc_tb_vf_keye
- #include <fsl_netc.h>
Vlan Filter table key element.
-
struct _netc_tb_vf_cfge
- #include <fsl_netc.h>
Vlan Filter table config element.
Public Members
-
uint32_t portMembership
Port Membership Bitmap
-
uint32_t stgID
Spanning Tree Group Member ID
-
uint32_t fid
Filtering ID
-
uint32_t mlo
MAC Learning Options
-
uint32_t mfo
MAC Forwarding Options
-
uint32_t ipmfe
IP Multicast Filtering Enable
-
uint32_t ipmfle
IP Multicast Flooding Enable
-
uint32_t etaPortBitmap
Egress Treatment Applicability Port Bitmap for the secondary Egress Treatment group
-
uint32_t baseETEID
Base Egress Treatment Entry ID for the secondary Egress Treatment group
-
uint32_t portMembership
-
struct _netc_tb_vf_search_criteria
- #include <fsl_netc.h>
Vlan Filter table search criteria format.
Public Members
-
uint32_t resumeEntryId
Resume Entry ID, when starting a search, pass the NULL Entry ID.
-
uint32_t resumeEntryId
-
struct _netc_tb_vf_req_data
- #include <fsl_netc.h>
Vlan Filter table request data buffer.
Public Members
-
netc_tb_vf_cfge_t cfge
Present only for update or add commands
-
netc_tb_vf_cfge_t cfge
-
struct _netc_tb_vf_rsp_data
- #include <fsl_netc.h>
Vlan Filter table request response data buffer.
Public Members
-
uint32_t status
Present only for query command with search access method
-
uint32_t entryID
Present only for query command
-
netc_tb_vf_keye_t keye
Present only for query command
-
netc_tb_vf_cfge_t cfge
Present only for query command
-
uint32_t status
-
struct _netc_tb_vf_data
- #include <fsl_netc.h>
Vlan Filter table data buffer.
-
struct _netc_tb_vf_config
- #include <fsl_netc.h>
Vlan Filter table entry config.
-
struct _netc_tb_fdb_keye
- #include <fsl_netc.h>
Public Members
-
uint8_t macAddr[6]
Destination MAC address of the frame for MAC forwarding lookups and the source MAC address of the frame for MAC learning lookups
-
uint32_t fid
Filtering ID, is obtained from an ingress lookup into the VLAN Filter table
-
uint8_t macAddr[6]
-
struct _netc_tb_fdb_cfge
- #include <fsl_netc.h>
FDB table configuration element.
Public Members
-
uint32_t portBitmap
Forwarding destination Port Bitmap and ET applicability port bitmap when oETEID = 10b
-
netc_tb_fdb_oeteid_mode_t oETEID
Override ET_EID option
-
uint32_t ePort
Egress Ports, active when oETEid = 01b or ctd = 01b
-
uint32_t iMirE
Ingress Mirroring Enable
-
netc_tb_fdb_ctd_mode_t ctd
Cut-Through Disable
-
uint32_t dynamic
Static or Dynamic Entry, 0b = Static entry, 1b = Dynamic entry
-
uint32_t timeCapE
Timestamp Capture Enable when set
-
uint32_t etEID
Base egress treatment table entry id for primary Egress Treatment group, is valid if the oETEID field is set to value other than kNETC_FDBNoEPP. 0xFFFFFFFF is NULL.
-
uint32_t portBitmap
-
struct _netc_tb_fdb_acte
- #include <fsl_netc.h>
FDB table Activity element.
Public Members
-
uint8_t actCnt
Activity Counter
-
uint8_t actFlag
Activity Flag
-
uint8_t actCnt
-
struct _netc_tb_fdb_search_criteria
- #include <fsl_netc.h>
FDB table search criteria format.
Public Members
-
uint32_t resumeEntryId
Resume Entry ID, pass the NULL Entry ID when starting a search
-
netc_tb_fdb_keye_t keye
Key Element data which used to match against the table entries
-
netc_tb_fdb_cfge_t cfge
Configuration Element data which used to match against the table entries
-
uint32_t resumeEntryId
-
struct _netc_tb_fdb_req_data
- #include <fsl_netc.h>
FDB table request data buffer.
Public Members
-
netc_tb_common_header_t commonHeader
Define update actions (use netc_tb_fdb_update_action_t) and query actions
-
netc_tb_fdb_cfge_t cfge
Present only for commands which perform an update or add
-
netc_tb_common_header_t commonHeader
-
struct _netc_tb_fdb_rsp_data
- #include <fsl_netc.h>
FDB table request response data buffer.
Public Members
-
uint32_t status
RESUME_ENTRY_ID, valid only in responses for commands which use the Search Access Method
-
uint32_t entryID
Present only for query command
-
netc_tb_fdb_keye_t keye
Present only for query command
-
netc_tb_fdb_cfge_t cfge
Present only for query command
-
netc_tb_fdb_acte_t acte
Present only for query command
-
uint32_t status
-
struct _netc_tb_fdb_data
- #include <fsl_netc.h>
FDB table data buffer.
-
struct _netc_tb_fdb_config
- #include <fsl_netc.h>
FDB table entry config.
-
struct _netc_tb_l2mcf_keye
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table key element.
Public Members
-
netc_tb_l2mcf_key_type_t keyType
Key Type
-
uint32_t fid
Filtering ID
-
uint32_t ipv4DestAddr
IPv4 Destination Address
-
uint32_t ipv4SrcAddr
IPv4 Source Address
-
netc_tb_l2mcf_key_type_t keyType
-
struct _etc_tb_l2mcf_search_criteria
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table search criteria format.
Public Members
-
uint32_t resumeEntryId
Resume Entry ID, pass the NULL Entry ID when starting a search
-
netc_tb_l2mcf_keye_t keye
Key Element data which used to match against the table entries
-
netc_tb_l2mcf_cfge_t cfge
Configuration Element data which used to match against the table entries
-
uint32_t resumeEntryId
-
struct _netc_tb_l2mcf_req_data
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table request data buffer.
-
struct _netc_tb_l2mcf_rsp_data
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table request response data buffer.
-
struct _netc_tb_l2mcf_data
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table data buffer.
-
struct _netc_tb_l2mcf_config
- #include <fsl_netc.h>
L2 IPV4 Multicast Filter table entry config.
-
struct _netc_tb_iseqg_cfge
- #include <fsl_netc.h>
Ingress Sequence Generation table config element.
-
struct _netc_tb_iseqg_sgse
- #include <fsl_netc.h>
Ingress Sequence Generation table Sequence generation state element.
Public Members
-
uint16_t sqgNum
Sequence Generation Number
-
uint16_t sqgNum
-
struct _netc_tb_iseqg_req_data
- #include <fsl_netc.h>
Ingress Sequence Generation table request data buffer.
-
struct _netc_tb_iseqg_rsp_data
- #include <fsl_netc.h>
Ingress Sequence Generation table request response data buffer.
-
struct _netc_tb_iseqg_data
- #include <fsl_netc.h>
Ingress Sequence Generation table data buffer.
-
struct _netc_tb_iseqg_config
- #include <fsl_netc.h>
Ingress Sequence Generation table entry config.
-
struct _netc_tb_eseqr_cfge
- #include <fsl_netc.h>
Egress Sequence Recovery table config element.
Public Members
-
netc_tb_eseqr_sqtag_t sqTag
Sequence Tag, specify the expected sequence tag type in the frame
-
uint32_t sqrTnsq
Sequence Recovery Take No Sequence
-
uint32_t sqrAlg
Sequence Recovery Algorithm, 0b = Vector algorithm, 1b = Match algorithm
-
uint32_t sqrType
Sequence Recovery Function type, 0b = Sequence recovery function, 1b = Individual recovery function
-
uint32_t sqrHl
Sequence Recovery History Length, valid if sqrAlg = 0b
-
uint32_t sqrFwl
Sequence Recovery Future Window Length, valid if sqrAlg = 0b
-
uint32_t sqrTp
Sequence Timeout Period, the unit is 1.048576 milliseconds
-
netc_tb_eseqr_sqtag_t sqTag
-
struct _netc_tb_eseqr_stse
- #include <fsl_netc.h>
Egress Sequence Recovery table statistic element.
Public Members
-
uint32_t inOrderPackets[2]
In Order Packets
-
uint32_t outOfOrderPackets[2]
Out of Order Packets
-
uint32_t roguePackets[2]
Rogue Packets
-
uint32_t duplicatePackets[2]
Duplicate Packets
-
uint32_t lostPackets[2]
Lost Packets
-
uint32_t taglessPackets[2]
Tag-Less Packets
-
uint32_t esqrResetCounts
Sequence Recovery Resets
-
uint32_t inOrderPackets[2]
-
struct _netc_tb_eseqr_srse
- #include <fsl_netc.h>
Egress Sequence Recovery table sequence recovery state element.
Public Members
-
uint32_t sqrNum
Sequence Recovery Number
-
uint32_t takeAny
Take Any
-
uint32_t lce
Lost Count Enable
-
uint32_t sqrTs
Sequence Recovery Timestamp
-
uint32_t sqrHistory[4]
Recovery History bit vector, each bit corresponding to sequence numbers, bit 1 means a packet with that sequence number has been previously received
-
uint32_t sqrNum
-
struct _netc_tb_eseqr_req_data
- #include <fsl_netc.h>
Egress Sequence Recovery table request data buffer.
-
struct _netc_tb_eseqr_rsp_data
- #include <fsl_netc.h>
Egress Sequence Recovery table request response data buffer.
-
struct _netc_tb_eseqr_data
- #include <fsl_netc.h>
Egress Sequence Recovery table data buffer.
-
struct _netc_tb_eseqr_config
- #include <fsl_netc.h>
Egress Sequence Recovery table entry config.
-
struct _netc_tgs_gate_entry
- #include <fsl_netc.h>
Defines the Time Gate Scheduling gate control entry structure.
Public Members
-
uint32_t interval
Entry Time Interval
-
uint32_t interval
-
struct _netc_tb_tgs_cfge
- #include <fsl_netc.h>
Time Gate Scheduling table config element.
Public Members
-
uint64_t adminBaseTime
Administrative Base Time
-
uint32_t adminCycleTime
Administrative Cycle Time
-
uint32_t adminCycleTimeExt
Administrative Cycle Time Extension
-
uint32_t adminControlListLength
Administrative Control List Length
-
netc_tgs_gate_entry_t adminGcl[]
Administrative Gate control list
-
uint64_t adminBaseTime
-
struct _netc_tb_tgs_olse
- #include <fsl_netc.h>
Time Gate Scheduling table statistic element.
Public Members
-
uint64_t configChangeTime
The time at which this operational gate control list became active
-
uint64_t configChangeError
Count of error configuration changes
-
uint64_t operBaseTime
Operational Base Time
-
uint32_t operCycleTime
Operational Cycle Time
-
uint32_t operCycleTimeExt
Operational Cycle Time Extension
-
uint32_t operControlListLength
Operational Control List Length
-
netc_tgs_gate_entry_t operGcl[]
Operational Gate control list
-
uint64_t configChangeTime
-
struct _netc_tb_tgs_req_data
- #include <fsl_netc.h>
Time Gate Scheduling table request data buffer.
Public Members
-
netc_tb_tgs_cfge_t cfge
Present only for commands which perform a update
-
netc_tb_tgs_cfge_t cfge
-
struct _netc_tb_tgs_rsp_data
- #include <fsl_netc.h>
Time Gate Scheduling table request response data buffer.
Public Members
-
uint32_t entryID
Present only for commands which perform a query
-
netc_tb_tgs_cfge_t cfge
Present only for commands which perform a query
-
netc_tb_tgs_olse_t olse
Present only for commands which perform a query
-
uint32_t entryID
-
struct _netc_tb_tgs_data
- #include <fsl_netc.h>
Time Gate Scheduling table data buffer, set with max size.
-
struct _netc_tb_tgs_gcl
- #include <fsl_netc.h>
Time Gate Scheduling table entry gate control list structure.
Public Members
-
uint64_t baseTime
Base Time
-
uint32_t cycleTime
Cycle Time
-
uint32_t extTime
Cycle Time Extension
-
uint32_t numEntries
Control List entry numbers
-
netc_tgs_gate_entry_t *gcList
Pointer to time gate control list array
-
uint64_t baseTime
-
struct _netc_tb_et_cfge
- #include <fsl_netc.h>
Egress Treatment table config element.
Public Members
-
netc_tb_et_efm_mode_t efmMode
Egress Frame Modification mode
-
netc_tb_et_esq_act_t esqa
Egress Sequence Actions
-
netc_tb_et_ec_act_t eca
Egress Counter Action
-
uint8_t __pad1__
Reserve for data align
-
uint8_t efmLenChange
Egress Frame Modification Length Change, specified in units of bytes using a 2’s complement notation
-
uint16_t efmDataLen
Egress Frame Modification Data Length
-
uint32_t efmEID
Egress Frame Modification Entry Id
-
uint32_t ecEID
Egress Count Table Entry ID
-
uint32_t esqaTgtEID
Egress Sequence Actions Target Entry ID, active when esqa = 10b
-
netc_tb_et_efm_mode_t efmMode
-
struct _netc_tb_et_req_data
- #include <fsl_netc.h>
Egress Treatment table request data buffer.
-
struct _netc_tb_et_rsp_data
- #include <fsl_netc.h>
Egress Treatment table request response data buffer.
-
struct _netc_tb_et_data
- #include <fsl_netc.h>
Egress Treatment table data buffer.
-
struct _netc_tb_et_config
- #include <fsl_netc.h>
Egress Treatment table entry config.
-
struct _netc_tb_etmcq_cfge
- #include <fsl_netc.h>
ETM Class Queue table config element.
Public Members
-
netc_hw_etm_class_queue_idx_t cq2cgMap
Class Queue to Congestion Group Mapping
-
netc_hw_etm_class_queue_idx_t cq2cgMap
-
struct _netc_tb_etmcq_stse
- #include <fsl_netc.h>
ETM Class Queue table statistic element.
Public Members
-
uint32_t rejByteCnt[2]
Reject Byte Count
-
uint32_t rejFrameCnt[2]
Reject Frame Count
-
uint32_t deqByteCnt[2]
Dequeue Byte Count
-
uint32_t deqFrameCnt[2]
Dequeue Frame Count
-
uint32_t dropByteCnt[2]
Dropped Frames, Memory Lost
-
uint32_t dropFrameCnt[2]
Dropped Frames, Memory Recovered
-
uint32_t frmCnt
Frame Count
-
uint32_t rejByteCnt[2]
-
struct _netc_tb_etmcq_req_data
- #include <fsl_netc.h>
ETM Class Queue table request data buffer.
-
struct _netc_tb_etmcq_rsp_data
- #include <fsl_netc.h>
ETM Class Queue table request response data buffer.
-
struct _netc_tb_etmcq_data
- #include <fsl_netc.h>
ETM Class Queue table data buffer.
-
struct _netc_tb_etmcq_config
- #include <fsl_netc.h>
ETM Class Queue table entry config.
Public Members
-
uint32_t entryID
Need use NETC_TB_ETM_CQ_ENTRY_ID macro to create entry ID
-
uint32_t entryID
-
struct _netc_tb_etmcs_cfge
- #include <fsl_netc.h>
ETM Class Scheduler table config element.
Public Members
-
netc_tb_etmcs_ca_assg_t cqAssg
Class Queue Assignment, input 0 to 7 are weighted fair whereby input 8 to 15 are strict priority
-
uint32_t oal
Overead accounting length
-
struct _netc_tb_etmcs_cfge wbfsWeight[8]
Weight for scheduler input 0 ~ 7, effective weight is: (2^x)/(1-(y/64))
-
netc_tb_etmcs_ca_assg_t cqAssg
-
struct _netc_tb_etmcs_req_data
- #include <fsl_netc.h>
ETM Class Scheduler table request data buffer.
Public Members
-
netc_tb_etmcs_entry_id_t entryID
One class scheduler entry per port
-
netc_tb_etmcs_entry_id_t entryID
-
struct _netc_tb_etmcs_rsp_data
- #include <fsl_netc.h>
ETM Class Scheduler table request response data buffer.
-
struct _netc_tb_etmcs_data
- #include <fsl_netc.h>
ETM Class Scheduler table data buffer.
-
struct _netc_tb_etmcs_config
- #include <fsl_netc.h>
ETM Class Scheduler table entry config.
Public Members
-
netc_tb_etmcs_entry_id_t entryID
One class scheduler entry per port
-
netc_tb_etmcs_entry_id_t entryID
-
struct _netc_tb_etmcg_cfge
- #include <fsl_netc.h>
ETM Congestion Group table config element.
Public Members
-
uint16_t tdDr0En
Tail drop enable for DR0 Frame
-
uint16_t tdDr1En
Tail drop enable for DR1 Frame
-
uint16_t tdDr2En
Tail drop enable for DR2 Frame
-
uint16_t tdDr3En
Tail drop enable for DR3 Frame
-
uint16_t oal
Overhead accounting length, 2’s complement value (range -2048 to +2047)
-
struct _netc_tb_etmcg_cfge tdDRThresh[4]
Tail Drop Threshold (TA * 2^Tn) for DR0 ~ DR3 Frames, valid if tdDrnEn = 1b
-
uint16_t tdDr0En
-
struct _netc_tb_etmcg_stse
- #include <fsl_netc.h>
ETM Congestion Group table statistic element.
Public Members
-
uint32_t byteCount[2]
Number of bytes currently in use in all class queues that are members of this group.
-
uint32_t byteCount[2]
-
struct _netc_tb_etmcg_req_data
- #include <fsl_netc.h>
ETM Congestion Group table request data buffer.
-
struct _netc_tb_etmcg_rsp_data
- #include <fsl_netc.h>
ETM Congestion Group table request response data buffer.
-
struct _netc_tb_etmcg_data
- #include <fsl_netc.h>
ETM Congestion Group table data buffer.
-
struct _netc_tb_etmcg_config
- #include <fsl_netc.h>
ETM Congestion Group table entry config.
Public Members
-
uint32_t entryID
Need use NETC_TB_ETM_CG_ENTRY_ID macro to create entry ID
-
uint32_t entryID
-
struct _netc_tb_ec_stse
- #include <fsl_netc.h>
Egress Count table statistic element.
Public Members
-
uint32_t enqFrmCnt[2]
Enqueued Frame Count
-
uint32_t rejFrmCnt[2]
Rejected Frame Count
-
uint32_t enqFrmCnt[2]
-
struct _netc_tb_ec_req_data
- #include <fsl_netc.h>
Egress Count table request data buffer.
-
struct _netc_tb_ec_rsp_data
- #include <fsl_netc.h>
Egress Count table request response data buffer.
-
struct _netc_tb_ec_data
- #include <fsl_netc.h>
Egress Count table data buffer.
-
struct _netc_tb_bp_cfge
- #include <fsl_netc.h>
Buffer Pool table config element.
Public Members
-
bool sbpEn
Shared Buffer Pool Enable, set true measn a shared buffer pool is associated with this buffer pool
-
netc_tb_bp_fc_cfg_t gcCfg
Flow Control (FC) Configuration
-
uint8_t pfcVector
Priority Flow Control (PFC) Vector, not support in NETC 3.0 and 3.1 version
-
uint16_t maxThresh
Maximum Threshold, value 0 means disable maximum threshold checking, use NETC_TB_BP_THRESH macro to set this value
-
uint16_t fcOnThresh
Flow Control On Threshold, If the buffer pool usage crosses this threshold, and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool is set to 1, use NETC_TB_BP_THRESH macro to set this value.
-
uint16_t fcOffThresh
Flow Control Off Threshold, If buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, , use NETC_TB_BP_THRESH macro to set this value
-
uint32_t sbpThresh
Shared Buffer Pool Threshold, use NETC_TB_BP_THRESH macro to set this value
-
uint32_t sbpEid
Shared Buffer Pool Entry ID, valid if sbpEn is true
-
uint32_t fcPorts
Flow Control Port bitmap, indicates which ports are to be flow controlled for this buffer pool
-
bool sbpEn
-
struct _netc_tb_bp_bpse
- #include <fsl_netc.h>
Buffer Pool table State Element Data.
Public Members
-
uint32_t amountUsed
Amount Used, number of internal memory words (average of 20 bytes each) currently in use in this buffer pool.
-
uint32_t amountUsedHWM
Amount Used High Watermark, value sticks at the highest AMOUNT_USED seen since the last watermark reset
-
uint32_t fcState
Flow Control (FC) State, ON (1) or OFF (0)
-
uint32_t bpd
Buffer Pool Disabled, 1 means the buffer pool has been disabled due to an uncorrectable ECC error
-
uint32_t amountUsed
-
struct _netc_tb_bp_req_data
- #include <fsl_netc.h>
Buffer Pool table request data buffer.
-
struct _netc_tb_bp_rsp_data
- #include <fsl_netc.h>
Buffer Pool table request response data buffer.
-
struct _netc_tb_bp_data
- #include <fsl_netc.h>
Buffer Pool table data buffer.
-
struct _netc_tb_bp_config
- #include <fsl_netc.h>
Buffer Pool table entry config.
Public Members
-
uint32_t entryID
Buffer pool ID, range in 0 ~ (SWT_GetBPTableEntryNum() - 1)
-
netc_tb_bp_cfge_t cfge
Buffer Pool table config element
-
uint32_t entryID
-
struct _netc_tb_sbp_cfge
- #include <fsl_netc.h>
Shared Buffer Pool table config element.
Public Members
-
uint32_t maxThresh
Maximum Threshold, If shared buffer pool usage is greater than or equal to this threshold, use NETC_TB_BP_THRESH macro to set this value
-
uint16_t fcOnThresh
Flow Control On Threshold, If the shared buffer pool usage crosses this threshold, and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool is set to 1, use NETC_TB_BP_THRESH macro to set this value.
-
uint16_t fcOffThresh
Flow Control Off Threshold, If shared buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, use NETC_TB_BP_THRESH macro to set this value
-
uint32_t maxThresh
-
struct _netc_tb_sbp_sbpse
- #include <fsl_netc.h>
Shared Buffer Pool table State Element Data.
Public Members
-
uint32_t amountUsed
Amount Used, number of internal memory words (average of 20 bytes each) currently in use in this buffer pool.
-
uint32_t amountUsedHWM
Amount Used High Watermark, value sticks at the highest AMOUNT_USED seen since the last watermark reset
-
uint32_t fcState
Flow Control (FC) State, ON (1) or OFF (0)
-
uint32_t amountUsed
-
struct _netc_tb_sbp_req_data
- #include <fsl_netc.h>
Shared Buffer Pool table request data buffer.
-
struct _netc_tb_sbp_rsp_data
- #include <fsl_netc.h>
Shared Buffer Pool table request response data buffer.
-
struct _netc_tb_sbp_data
- #include <fsl_netc.h>
Shared Buffer Pool table data buffer.
-
struct _netc_tb_sbp_config
- #include <fsl_netc.h>
Shared Buffer Pool table entry config.
Public Members
-
uint32_t entryID
Shared Buffer pool ID, range in 0 ~ (SWT_GetSBPTableEntryNum() - 1)
-
netc_tb_sbp_cfge_t cfge
Shared Buffer Pool table config element
-
uint32_t entryID
-
union _netc_tb_data_buffer
- #include <fsl_netc.h>
Table common data buffer.
Public Members
-
netc_tb_tgs_data_t tgs
Time Gate Scheduling table data buffer
-
netc_tb_rp_data_t rp
Rate Policer table data buffer
-
netc_tb_ipf_data_t ipf
Ingress Port filter table data buffer
-
netc_tb_fdb_data_t fdb
FDB table data buffer
-
netc_tb_l2mcf_data_t l2mcf
L2 IPV4 Multicast Filter table data buffer
-
netc_tb_vf_data_t vf
VLAN Filter table data buffer
-
netc_tb_isi_data_t isi
Ingress Stream Identification table data buffer
-
netc_tb_is_data_t is
Ingress Stream table data buffer
-
netc_tb_isf_data_t isf
Ingress Stream Filter table data buffer
-
netc_tb_isc_data_t isc
Ingress Stream Count table data buffer
-
netc_tb_sgi_data_t sgi
Stream Gate Instance table data buffer
-
netc_tb_sgcl_data_t sgcl
Stream Gate Control List table data buffer
-
netc_tb_fm_data_t fm
Frame Modification table data buffer
-
netc_tb_fmd_data_t fmd
Frame Modification Data table data buffer
-
netc_tb_et_data_t et
Egress Treatment table data buffer
-
netc_tb_ec_data_t ec
Egress Count table data buffer
-
netc_tb_etmcq_data_t cq
ETM Class Queue table data buffer
-
netc_tb_etmcs_data_t cs
ETM Class Scheduler table data buffer
-
netc_tb_etmcg_data_t cg
ETM Class Group table data buffer
-
netc_tb_iseqg_data_t iseqg
Ingress Sequence Generation table data buffer
-
netc_tb_eseqr_data_t eseqr
Egress Sequence Recovery table data buffer
-
netc_tb_bp_data_t bp
Buffer Pool table data buffer
-
netc_tb_sbp_data_t sbp
Shared Buffer Pool table data buffer
-
netc_tb_tgs_data_t tgs
-
struct _netc_cbdr_hw
- #include <fsl_netc_hw.h>
Register group for SI/Switch command bd ring.
Public Members
- __IO uint32_t CBDRMR
Command BDR mode register.
- __I uint32_t CBDRSR
Command BDR status register.
- __IO uint32_t CBDRBAR0
Command BDR base address register 0
- __IO uint32_t CBDRBAR1
Command BDR base address register 1
- __IO uint32_t CBDRPIR
Command BDR producer index register
- __IO uint32_t CBDRCIR
Command BDR consumer index register
- __IO uint32_t CBDRLENR
Command BDR length register
-
struct _netc_cbdr_handle
- #include <fsl_netc_hw.h>
Handle for common part of EP/Switch NTMP.
Public Members
-
netc_cbdr_hw_t *base
Point to hardware command bd ring register group.
-
netc_cmd_bdr_t *cmdr
Point to command BD ring handle.
-
netc_tb_data_buffer_t *buffer
Point to table common data buffer.
-
netc_cbdr_hw_t *base
-
struct req
Public Members
-
uint64_t addr
The request and response data buffers address
-
uint64_t addr
-
struct __unnamed105__
Public Members
-
uint32_t resLength
The length of the Response Data Buffer
-
uint32_t reqLength
The length of the Request Data Buffer
-
uint32_t resLength
-
struct __unnamed107__
Public Members
-
netc_tb_cmd_t cmd
Access table entry command, see netc_tb_cmd_t .
-
netc_tb_access_mode_t accessType
Access table entry method, see netc_tb_access_mode_t.
-
uint32_t __pad1__
RSS Hash high field value.
-
uint32_t version
Protocol Version.
-
uint32_t enCompInt
Command Completion Interrupt.
-
uint32_t resReady
Response Ready.
-
netc_tb_cmd_t cmd
-
struct __unnamed109__
Public Members
-
uint32_t npf
NTMP Protocol Format.
-
uint32_t npf
-
struct resp
-
struct __unnamed111__
Public Members
-
uint32_t numMatched
Number of Entries Matched.
-
uint32_t error
Error status.
-
uint32_t resReady
Response Ready.
-
uint32_t numMatched
-
struct generic
Public Members
-
uint64_t addr
Data.
-
uint32_t en
Enable entry.
-
uint32_t siBitMap
Station interfaces 15-0 for which this filter applies.
-
uint32_t index
The index refers to an entry location within a table.
-
uint32_t length
NA
-
uint32_t cmd
Command.
-
uint32_t __pad2__
< Class of command.
-
uint32_t status
Status.
-
uint32_t ci
Completion interrupt.
-
uint32_t sf
Short format.
-
uint64_t addr
-
struct frameAttr
Public Members
-
uint16_t swtPortMas
Switch port masquerading, applicable only if the incoming port is designated as a switch management port
-
uint16_t ethernet
Ethernet type Present
-
uint16_t outerVlan
Outer VLAN Present
-
uint16_t innerVlan
Inner VLAN Present
-
netc_tb_ipf_seq_tag_t seqTag
Sequence Tag Code
-
uint16_t ipHeader
IP Header Present
-
uint16_t ipVersion
0b = IPv4, 1b = IPv6
-
uint16_t ipExt
IPv4 option / IPv6 extension present
-
netc_tb_ipf_l4_header_t l4Header
L4 Header code
-
uint16_t wakeOnLan
Wake-on-LAN Magic Packet Present
-
uint16_t swtPortMas
-
struct payload
Public Members
-
uint8_t data
Payload Byte n
-
uint8_t mask
Payload Byte n Mask
-
uint8_t data
-
union __unnamed115__
-
union __unnamed117__
-
union __unnamed119__
-
union __unnamed121__
-
union __unnamed123__
-
union __unnamed125__
-
union __unnamed127__
-
union __unnamed129__
Public Members
-
netc_tb_rp_cfge_t cfge
Present only for commands which perform an update or add
- struct _netc_tb_rp_req_data
-
netc_tb_rp_cfge_t cfge
-
struct __unnamed131__
Public Members
-
netc_tb_rp_fee_t fee
Present only for commands which perform an update or add
-
netc_tb_rp_fee_t fee
-
union __unnamed133__
Public Members
-
netc_tb_rp_cfge_t cfge
Present only for commands which perform a query
- struct _netc_tb_rp_rsp_data
- struct _netc_tb_rp_rsp_data
-
netc_tb_rp_cfge_t cfge
-
struct __unnamed135__
Public Members
-
netc_tb_rp_fee_t fee
Present only for commands which perform a query
-
netc_tb_rp_fee_t fee
-
struct __unnamed137__
Public Members
-
netc_tb_rp_pse_t pse
Present only for commands which perform a query
-
netc_tb_rp_pse_t pse
-
union __unnamed139__
-
union __unnamed141__
-
union __unnamed143__
-
struct __unnamed145__
-
union __unnamed147__
-
union __unnamed149__
Public Members
-
netc_tb_sgcl_req_data_t request
-
netc_tb_sgcl_rsp_data_t response
- struct _netc_tb_sgcl_data
-
netc_tb_sgcl_req_data_t request
-
struct __unnamed151__
-
union __unnamed153__
-
union __unnamed155__
-
union __unnamed157__
Public Members
-
uint32_t entryID
-
netc_tb_vf_search_criteria_t sCriteria
Active when access method is kNETC_Search
-
netc_tb_vf_keye_t keye
-
uint32_t entryID
-
union __unnamed159__
-
struct __unnamed161__
Public Members
-
netc_tb_fdb_acte_t acte
Activity Element data which used to match against the table entries
-
netc_tb_fdb_sc_keye_mc_t keyeMc
Key Element data match criteria
-
netc_tb_fdb_sc_cfge_mc_t cfgeMc
Configuration Element data match criteria
-
netc_tb_fdb_sc_acte_mc_t acteMc
Activity Element data match criteria
-
netc_tb_fdb_acte_t acte
-
union __unnamed163__
Public Members
-
uint32_t entryID
Active when access method is kNETC_EntryIDMatch
-
netc_tb_fdb_keye_t keye
Active when access method is kNETC_ExactKeyMatch
-
netc_tb_fdb_search_criteria_t sCriteria
Active when access method is kNETC_Search
-
uint32_t entryID
-
union __unnamed165__
-
struct __unnamed167__
Public Members
-
netc_tb_l2mcf_acte_t acte
Activity Element data which used to match against the table entries
-
etc_tb_l2mcf_sc_keye_mc_t keyeMc
Key Element data match criteria
-
etc_tb_l2mcf_sc_cfge_mc_t cfgeMc
Configuration Element data match criteria
-
etc_tb_l2mcf_sc_acte_mc_t acteMc
Activity Element data match criteria
-
netc_tb_l2mcf_acte_t acte
-
union __unnamed169__
-
union __unnamed171__
-
union __unnamed173__
-
union __unnamed175__
-
union __unnamed177__
Public Members
- struct _netc_tgs_gate_entry
-
uint32_t gate
Entry Gate Mask
-
struct __unnamed179__
Public Members
-
uint32_t tcGateState
Traffic Class Gate States for Gate Entry, 8 bits for 8 Traffic Class , 0b means Gate closed, 1b means Gate open
-
netc_tb_tgs_gate_type_t operType
Gate operation type ( IEEE 802.1Q-2018) field for gate control list entry i
-
uint32_t tcGateState
-
union __unnamed181__
Public Members
-
netc_tb_tgs_req_data_t request
-
netc_tb_tgs_rsp_data_t response
- struct _netc_tb_tgs_data
-
netc_tb_tgs_req_data_t request
-
struct __unnamed183__
-
union __unnamed185__
-
union __unnamed187__
-
struct wbfsWeight
Public Members
-
uint8_t xCode
Weight code x value
-
uint8_t yCode
Weight code y value
-
uint8_t xCode
-
union __unnamed190__
-
struct tdDRThresh
Public Members
-
uint16_t tn
TA
-
uint16_t ta
Tn
-
uint16_t tn
-
union __unnamed193__
-
union __unnamed195__
-
union __unnamed197__
-
union __unnamed199__
NETC MDIO Driver
MDIO initialization module
-
enum _netc_mdio_type
Enumeration for the MAC port MDIO type.
Values:
-
enumerator kNETC_EMdio
Bound handle to EMDIO access, submodule of NETC.
-
enumerator kNETC_InternalMdio
Bound handle to MAC port internal MDIO access, submodule of EP/Switch.
-
enumerator kNETC_ExternalMdio
Bound handle to MAC port external MDIO access, submodule of EP/Switch.
-
enumerator kNETC_EMdio
-
typedef enum _netc_mdio_type netc_mdio_type_t
Enumeration for the MAC port MDIO type.
-
typedef struct _netc_mdio netc_mdio_t
Structure to choose MDIO entity(Internal/external MDIO for specified EP/Switch port)
-
typedef struct _netc_mdio_handle netc_mdio_handle_t
MDIO handle.
-
typedef struct _netc_mdio_config netc_mdio_config_t
MDIO configuration structure.
-
status_t NETC_MDIOInit(netc_mdio_handle_t *handle, netc_mdio_config_t *config)
Initialize the MDIO.
Note
The EMDIO can be used independently. The port internal/external MDIO is a part of EP/Switch, should be initialized and used after EP/Switch is enabled.
- Parameters:
handle – MDIO handle.
config – MDIO configuration.
- Returns:
status_t
-
struct _netc_mdio
- #include <fsl_netc_mdio.h>
Structure to choose MDIO entity(Internal/external MDIO for specified EP/Switch port)
Public Members
-
netc_mdio_type_t type
Internal or external MAC port MDIO.
-
netc_hw_eth_port_idx_t port
MDIO port index, only meaningful when port MDIO type is used.
-
netc_mdio_type_t type
-
struct _netc_mdio_handle
- #include <fsl_netc_mdio.h>
MDIO handle.
Public Members
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netc_mdio_t mdio
MDIO identificator.
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netc_mdio_t mdio
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struct _netc_mdio_config
- #include <fsl_netc_mdio.h>
MDIO configuration structure.
Public Members
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netc_mdio_t mdio
MDIO identificator.
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uint32_t srcClockHz
MDIO reference clock for MDC frequency calculation.
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bool isNegativeDriven
MDIO driven at positive(false)/negative(true) of MDC edge.
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bool isPreambleDisable
Enable/Disable generation of MDIO preamble.
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netc_mdio_t mdio
MDIO PHY status module
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typedef struct _netc_mdio_phy_status netc_mdio_phy_status_t
PHY auto status check configuration structure.
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status_t NETC_MDIOSetPhyStatusCheck(netc_mdio_handle_t *handle, netc_mdio_phy_status_t *config)
Setup the mechanism to check PHY status automatically This is a hardware mechanism to read specified PHY register in a configured time interval instead of polling the PHY in software.
- Parameters:
handle – MDIO handle.
config – The configuration of the PHY status automatical check.
- Returns:
status_t
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void NETC_MDIOPhyStatusGetFlags(netc_mdio_handle_t *handle, uint16_t *low2HighMask, uint16_t *high2LowMask)
Get the PHY register bit status transition interrupt flag(s).
- Parameters:
handle – MDIO handle.
low2HighMask – The interrupt flag of a 0->1 transition on a corresponding bit of PHY register.
high2LowMask – The interrupt flag of a 1->0 transition on a corresponding bit of PHY register.
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void NETC_MDIOPhyStatusClearFlags(netc_mdio_handle_t *handle, uint16_t low2HighMask, uint16_t high2LowMask)
Clear the PHY register bit status transition interrupt flag(s).
- Parameters:
handle – MDIO handle.
low2HighMask – Clear the interrupt flag of a 0->1 transition on a corresponding bit of PHY register.
high2LowMask – Clear the interrupt flag of a 1->0 transition on a corresponding bit of PHY register.
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struct _netc_mdio_phy_status
- #include <fsl_netc_mdio.h>
PHY auto status check configuration structure.
Public Members
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uint16_t interval
PHY status read interval in units of 1-2 ms. A value of 0 indicates disable.
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bool isC45Used
PHY status read with Clause 22/45 MDIO access.
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uint8_t phyOrPortAddr
MDIO PHY address(Clause 22) / port address(Clause 45).
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uint8_t regiOrDevAddr
MDIO register address(Clause 22) / device address(Clause 45).
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uint16_t c45RegiAddr
MDIO register address(Clause 45).
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uint16_t enableIntrHigh2Low
Bit high-to-low event interrupt enable.
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uint16_t enableIntrLow2High
Bit low-to-high event interrupt enable.
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uint16_t interval
MDIO write/read module
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status_t NETC_MDIOWrite(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
IEEE802.3 Clause 22 MDIO write data.
- Parameters:
handle – MDIO handle.
phyAddr – The PHY address.
regAddr – The PHY register address.
data – The data written to PHY.
- Returns:
status_t
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status_t NETC_MDIORead(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)
IEEE802.3 Clause 22 MDIO read data.
- Parameters:
handle – MDIO handle.
phyAddr – The PHY address.
regAddr – The PHY register address.
pData – The received data from PHY.
- Returns:
status_t
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status_t NETC_MDIOC45Write(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)
IEEE802.3 Clause 45 MDIO write data.
- Parameters:
handle – MDIO handle.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
data – The data written to PHY.
- Returns:
status_t
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status_t NETC_MDIOC45Read(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)
IEEE802.3 Clause 45 MDIO read data.
- Parameters:
handle – MDIO handle.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
pData – The received data from PHY.
- Returns:
status_t
NETC SWITCH (SWT) Driver
Switch (SWT) data path
Switch (SWT) Generic Configuration
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typedef struct _swt_handle swt_handle_t
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typedef struct _swt_transfer_config swt_transfer_config_t
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typedef status_t (*swt_reclaim_cb_t)(swt_handle_t *handle, netc_tx_frame_info_t *frameInfo, void *userData)
Callback for reclaimed tx frames.
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typedef void *(*swt_rx_alloc_cb_t)(swt_handle_t *handle, uint32_t length, void *userData)
Defines the Switch Rx memory buffer alloc function pointer.
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typedef void (*swt_rx_free_cb_t)(swt_handle_t *handle, void *address, void *userData)
Defines the Switch Rx memory buffer free function pointer.
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typedef struct _swt_config swt_config_t
Configuration structure for Switch.
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typedef struct _swt_config_const swt_config_const_t
Configuration constant structure for Switch in handle.
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status_t SWT_Init(swt_handle_t *handle, const swt_config_t *config)
Init SWITCH.
- Parameters:
handle –
config – The user configuration
- Returns:
status_t
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status_t SWT_Deinit(swt_handle_t *handle)
Deinit switch.
- Parameters:
handle –
- Returns:
status_t
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status_t SWT_GetDefaultConfig(swt_config_t *config)
Get deafult configuration for switch.
- Parameters:
config –
- Returns:
status_t
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status_t SWT_SetEthPortMII(swt_handle_t *handle, uint8_t ethPort, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)
Set MII speed and duplex for switch ethernet port.
- Parameters:
handle –
ethPort –
speed –
duplex –
- Returns:
status_t
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static inline void SWT_SetPortSpeed(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t pSpeed)
Set switch port speed.
- Parameters:
handle –
portIdx –
pSpeed –
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status_t SWT_PortStop(swt_handle_t *handle, netc_hw_port_idx_t portIdx)
Stop Switch Port receive/transmit (disable both ETH and port)
- Parameters:
handle –
portIdx –
- Returns:
status_t
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status_t SWT_SetPortMaxFrameSize(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t size)
Set switch port maximum supported received frame size.
- Parameters:
handle –
portIdx –
size –
- Returns:
status_t
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struct _swt_config
- #include <fsl_netc_switch.h>
Configuration structure for Switch.
Public Members
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netc_hw_switch_idx_t switchIdx
Switch index
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struct _swt_config ports[5]
The common configuration required for all ports
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uint16_t dynFDBLimit
Maximum number of entries which can be dynamically learned by FDB table, a value of 0 implies no limit.
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netc_swt_psfp_config_t psfpCfg
The switch PSFP configuration, cover the ISI key construction profiles configuration
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netc_ipf_config_t ipfCfg
The switch ingress port filter configuration
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netc_vlan_classify_config_t vlanCfg
The switch ingress vlan classify configuration
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netc_swt_qos_classify_config_t rxqosCfg
The switch ingress VLAN to QoS mapping configuration
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netc_swt_qos_to_vlan_config_t txqosCfg
The switch egress QoS to VLAN mapping configuration
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netc_swt_imr_config_t imrCfg
The switch Ingress mirror configuration
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netc_swt_bridge_config_t bridgeCfg
The switch bridge configuration
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uint8_t cmdRingUse
Number of command BD rings to be used
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netc_cmd_bdr_config_t cmdBdrCfg[2]
The switch command BD rings configuration
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netc_msix_entry_t *msixEntry
MSIX table entry array.
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uint8_t entryNum
MSIX entry number.
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uint8_t cmdBdrEntryIdx[2]
MSIX entry index of command BD ring interrupt.
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uint8_t timeCaptureEntryIdx
MSIX entry index of time capture interrupt.
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netc_hw_switch_idx_t switchIdx
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struct _swt_config_const
- #include <fsl_netc_switch.h>
Configuration constant structure for Switch in handle.
Public Members
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uint8_t cmdRingUse
Number of command BD rings to be used
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uint8_t entryNum
MSIX entry number.
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bool rxCacheMaintain
Enable/Disable Rx buffer cache maintain in driver.
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bool txCacheMaintain
Enable/Disable Tx buffer cache maintain in driver.
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bool enUseMgmtRxBdRing
Enable/Disable use Switch management Rx BD ring.
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bool rxZeroCopy
Enable zero-copy receive mode.
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swt_rx_alloc_cb_t rxBuffAlloc
Callback function to alloc memory, must be provided for zero-copy Rx.
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swt_rx_free_cb_t rxBuffFree
Callback function to free memory, must be provided for zero-copy Rx.
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swt_reclaim_cb_t reclaimCallback
Callback for reclaimed Tx Switch management frames.
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void *userData
User data, return in callback.
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uint8_t cmdRingUse
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struct _swt_handle
- #include <fsl_netc_switch.h>
Handle for SWITCH.
Public Members
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netc_switch_hw_t hw
Hardware register map resource.
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swt_config_const_t cfg
Switch configuration constant.
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netc_cmd_bdr_t cmdBdRing[2]
Command BD ring handle for switch.
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ep_handle_t *epHandle
The EP handle to send/receive management frame.
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netc_rx_bdr_t mgmtRxBdRing
Management Receive BD ring for frames with Host Reason filed not zero.
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netc_tx_bdr_t mgmtTxBdRing
Management Transmit BD ring for Direct Switch Enqueue frames.
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netc_switch_hw_t hw
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struct ports
Public Members
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netc_port_ethmac_t ethMac
Ethernet MAC configuration, vaild only on port 0 ~ 3
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netc_port_common_t commonCfg
Port common configuration
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netc_swt_port_bridge_config_t bridgeCfg
Port bridge configuration
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netc_swt_port_fm_config_t fmCfg
Port Frame Modification configuration
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netc_port_tx_tc_config_t txTcCfg[8]
Port Tx traffic class related configuration, vaild only on port 0 ~ 3
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uint8_t ipvToTC[8]
Port IPV to Tx traffic class queue index mapping, value means TC index, range in 0 ~ 7
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uint8_t ipvToBP[8]
Port IPV to buffer pool ID mapping, value means BP ID, range in 0 ~ (SWT_GetBPTableEntryNum() - 1)
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netc_port_psfp_isi_config isiCfg
Port Ingress stream identification
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bool enMirror
Enable/Disable Ingress Mirroring on this port
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uint8_t lanID
The HSR’s LANID this port belong to
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bool inCutThrough
Enable/Disable Ingress Cut Through on this port, vaild only on port 0 ~ 3
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bool outCutThrough
Enable/Disable Egress Cut Through on this port, vaild only on port 0 ~ 3
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bool enableTg
Enable port time gate scheduling.
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bool enTxRx
Enable port transmit/receive path, if disabled, the tx/rx of the mac corresponding to the port will also be closed.
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netc_port_ethmac_t ethMac
Switch (SWT) Interrupt Module
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status_t SWT_MsixSetGlobalMask(swt_handle_t *handle, bool mask)
Set the global MSIX mask status.
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.
- Parameters:
handle – The EP handle
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
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status_t SWT_MsixSetEntryMask(swt_handle_t *handle, uint8_t entryIdx, bool mask)
Set the MSIX entry mask status for specified entry.
This function masks/unmasks MSIX message for specified entry.
- Parameters:
handle – SWT handle.
entryIdx – The entry index in the table.
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
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status_t SWT_MsixGetPendingStatus(swt_handle_t *handle, uint8_t pbaIdx, uint64_t *status)
Get the MSIX pending status in MSIX PBA table.
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.
- Parameters:
handle – SWT handle.
pbaIdx – The index of PBA array with 64-bit unit.
status – Pending status bit mask, bit n for entry n.
- Returns:
status_t
Switch (SWT) management
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status_t SWT_BridgeInit(swt_handle_t *handle, const netc_swt_bridge_config_t *config)
Config the Bridge.
Cover configuration below
Vlan filter table default VFHTDRCR0-2
Not Cover
Port specific Vlan config
Port Storm Control BPSCR0/R1
FDB entry
Vlan Filter Table entry
Multicast filter entry
- Parameters:
handle –
config –
- Returns:
status_t
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status_t SWT_BridgeConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_swt_port_bridge_config_t *config)
Config bridge port vlan Tx/Rx.
Cover configuration below
Port specific Vlan config
Port Storm Control BPSCR0/R1
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
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status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t vid)
Config bridge port default VID.
- Parameters:
handle –
portIdx –
vid –
- Returns:
status_t
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static inline uint32_t SWT_BridgeGetVFTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of bridge vlan filter table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, FDB, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_BridgeAddVFTableEntry(swt_handle_t *handle, netc_tb_vf_config_t *config, uint32_t *entryID)
Add entry into bridge vlan filter table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeUpdateVFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_vf_cfge_t *cfg)
Update entry in bridge vlan filter table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, netc_tb_vf_keye_t *keye, netc_tb_vf_rsp_data_t *rsp)
Query an entry in bridge VF Table.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeDelVFTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry in bridge vlan filter table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, netc_tb_vf_search_criteria_t *sCriteria, netc_tb_vf_rsp_data_t *rsp)
Search entry in bridge vlan filter table.
Note
Only support search and return one entry at a time.
- Parameters:
handle –
sCriteria –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t SWT_BridgeGetFDBTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of bridge FDB table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, VLAN Filter, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_BridgeAddFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_config_t *config, uint32_t *entryID)
Add entry into bridge FDB table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeUpdateFDBTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_fdb_cfge_t *cfg)
Update entry in bridge FDB table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeQueryFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_keye_t *keye, netc_tb_fdb_rsp_data_t *rsp)
Query an entry in bridge FDB Table.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeSearchFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_search_criteria_t *sCriteria, netc_tb_fdb_rsp_data_t *rsp)
Search entry in bridge FDB table.
Note
Only support search and return one entry at a time.
- Parameters:
handle –
sCriteria –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeDelFDBTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete an entry in bridge FDB Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeGetFDBActivityState(swt_handle_t *handle, uint32_t entryID, netc_tb_fdb_acte_t *state)
Get the activity data for FDB table entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t SWT_BridgeGetL2MCFTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of bridge L2 IPV4 multicast filter table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, VLAN Filter, FDB table.
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_BridgeAddL2MCFTableEntry(swt_handle_t *handle, netc_tb_l2mcf_config_t *config, uint32_t *entryID)
Add entry into Bridge L2 IPV4 multicast filter table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeUpdateL2MCFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_l2mcf_cfge_t *cfg)
Update entry in bridge L2 IPV4 multicast filter table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeSearchL2MCFTableEntry(swt_handle_t *handle, netc_tb_l2mcf_search_criteria_t *sCriteria, netc_tb_l2mcf_rsp_data_t *rsp)
Search entry in bridge L2 IPV4 multicast filter table.
Note
Only support search and return one entry at a time.
- Parameters:
handle –
sCriteria –
rsp –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeGetL2MCFActivityState(swt_handle_t *handle, uint32_t entryID, netc_tb_l2mcf_acte_t *state)
Get the activity data for bridge L2 IPV4 multicast filter table entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_BridgeDelL2MCFTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry in bridge L2 IPV4 multicast filter table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline status_t SWT_FMConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_swt_port_fm_config_t *config)
Config Port level Frame Modification.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
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static inline uint32_t SWT_FMGetTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of Frame Modification table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_FMAddTableEntry(swt_handle_t *handle, netc_tb_fm_config_t *config)
Add entry into the Frame Modification table.
Add entry of the frame modification table. Frame modification can be encoded into the table id directly or provided as index of the table entry. refer to the frame modification entry definition.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FMUpdateTableEntry(swt_handle_t *handle, netc_tb_fm_config_t *config)
Update entry in the Frame Modification table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FMDelTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete table entry in Frame Modification Table.
The provided ID must be table index. Error return if the id is action encoded id.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t SWT_FMDGetTableWordsNum(swt_handle_t *handle)
Get word number (word size is 24 bytes) of Frame Modification data table.
Note
This is a static bounded index table, when update or query table, should satisifed: numBytes + ENTRY_ID <= 24 * wordNumber .
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_FMDUpdateTableEntry(swt_handle_t *handle, netc_tb_fmd_update_config_t *config, uint32_t length)
Update Frame Modification data table contents.
- Parameters:
handle –
config –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FMDQueryTableEntry(swt_handle_t *handle, netc_tb_fmd_query_buffer_t *query, uint32_t length)
Query Frame Modification data table contents.
- Parameters:
handle –
query –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t SWT_FRERGetISEQGTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of ingress Sequence Generation table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_FRERAddISEQGTableEntry(swt_handle_t *handle, netc_tb_iseqg_config_t *config)
Add entry into FRER sequence number generation table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FRERUpdateISEQGTableEntry(swt_handle_t *handle, netc_tb_iseqg_config_t *config)
Update entry in FRER sequence number generation table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FRERResetSEQGTableEntry(swt_handle_t *handle, uint32_t entryID)
Reset sequence number generation in FRER sequence generation entry.
- Parameters:
handle –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FRERDelISEQGTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry in FRER sequence number generation table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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status_t SWT_FRERGetISEQGState(swt_handle_t *handle, uint32_t entryID, netc_tb_iseqg_sgse_t *state)
Get the Sequence generation number form sequence generation table for specified entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
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static inline uint32_t SWT_FRERGetESEQRTableEntryNum(swt_handle_t *handle)
Get the number of entries assigned to FRER sequence number recovery table.
Note
This is a static bounded index table, so all entries in the table are available for SWT_FRERConfigESEQRTableEntry() API
- Parameters:
handle –
- Returns:
uint32_t
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status_t SWT_FRERConfigESEQRTableEntry(swt_handle_t *handle, netc_tb_eseqr_config_t *config)
Config FRER sequence number recovery table entry.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_FRERQueryESEQRTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_eseqr_stse_t *statistic, netc_tb_eseqr_cfge_t *config, netc_tb_eseqr_srse_t *state)
Query FRER sequence recovery table entry.
- Parameters:
handle –
entryID –
statistic –
config –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_FRERGetESEQRStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_eseqr_stse_t *statistic, netc_tb_eseqr_srse_t *state)
Get FRER sequence recorvery table state and statistic.
- Parameters:
handle –
entryID –
statistic –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_GetBPTableEntryNum(swt_handle_t *handle)
Get Buffer Pool table entry number.
Note
This is a static bounded index table, so all entries in the table are available for SWT_UpdateBPTableEntry() API
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_UpdateBPTableEntry(swt_handle_t *handle, netc_tb_bp_config_t *config)
Update Buffer Pool table entry.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_GetBPEntryState(swt_handle_t *handle, uint32_t entryID, netc_tb_bp_bpse_t *state)
Get Buffer Pool table entry State.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_GetSBPTableEntryNum(swt_handle_t *handle)
Get Shared Buffer Pool table entry number.
Note
This is a static bounded index table, so all entries in the table are available for SWT_UpdateSBPTableEntry() API
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_UpdateSBPTableEntry(swt_handle_t *handle, netc_tb_sbp_config_t *config)
Update Shared Buffer Pool table entry.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_GetSBPEntryState(swt_handle_t *handle, uint32_t entryID, netc_tb_sbp_sbpse_t *state)
Get Shared Buffer Pool table entry State.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
Switch (SWT) Table Management Module
-
status_t SWT_CmdBDRInit(swt_handle_t *handle, netc_hw_swt_cbdr_idx_t ring, const netc_cmd_bdr_config_t *config)
Init SWITCH command BD ring.
- Parameters:
handle –
ring – Command BD ring index
config – The user configuration
- Returns:
status_t
-
status_t SWT_CmdBDRDeinit(swt_handle_t *handle, netc_hw_swt_cbdr_idx_t ring)
Deinit switch command BD ring.
- Parameters:
handle –
ring – Command BD ring index
- Returns:
status_t
Switch (SWT) Ingress data path configuration
-
status_t SWT_RxMirrorConfig(swt_handle_t *handle, const netc_swt_imr_config_t *config)
Configure switch ingress mirror.
- Parameters:
handle –
config –
- Returns:
status_t
-
static inline status_t SWT_RxParserConfig(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_parser_config_t *config)
Configure Parser in Receive Data Path.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
-
static inline status_t SWT_RxVlanCInit(swt_handle_t *handle, const netc_vlan_classify_config_t *config)
Configure the customer vlan type.
- Parameters:
handle –
config –
- Returns:
status_t
-
static inline status_t SWT_RxVlanCConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_vlan_classify_config_t *config)
Configure the Accepted Vlan for PORT.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
-
static inline status_t SWT_RxQosCInit(swt_handle_t *handle, const netc_swt_qos_classify_config_t *config)
Init the ingress QoS classification for Switch.
- Parameters:
handle –
config –
- Returns:
status_t
-
static inline status_t SWT_RxQosCConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_qos_classify_config_t *config)
Configure the QoS Classification for Switch Port.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
-
static inline status_t SWT_RxIPFInit(swt_handle_t *handle, const netc_ipf_config_t *config)
Enable/Disable Ingress Port Filtering.
Applied for both Switch and ENETC
- Parameters:
handle –
config –
- Returns:
status_t
-
static inline status_t SWT_RxIPFConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_ipf_config_t *config)
Config the IPF for specified Port.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
-
static inline uint32_t SWT_RxIPFGetTableRemainWordNum(swt_handle_t *handle)
Get remaining available word number (words size is 6 bytes) of the ingress Port Filter Table.
Note
This is a ternary match table, and the entries can vary in size, from 2 to 14 words.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxIPFAddTableEntry(swt_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)
Add an entry for the ingress Port Filter Table.
This function do an add & query with return hardware id which can be used as future query / delete / update.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxIPFUpdateTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)
Update entry in the ingress Port Filter Table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxIPFQueryTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_ipf_config_t *config)
Query an entry for the ingress Port Filter Table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxIPFDelTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete an entry for the ingress Port Filter Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxIPFResetMatchCounter(swt_handle_t *handle, uint32_t entryID)
Reset the counter of an ingress port filter entry.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxIPFGetMatchedCount(swt_handle_t *handle, uint32_t entryID, uint64_t *count)
Get the matched count for entry in IPF.
- Parameters:
handle –
entryID –
count –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline status_t SWT_RxPSFPInit(swt_handle_t *handle, const netc_swt_psfp_config_t *config)
Init the Switch PSFP Cover configuration below.
ISI key construction profiles (ISIDKC0CR0 - ISIDKC3CR0)
Not Cover
Port specific isi config
- Parameters:
handle –
config –
- Returns:
status_t
-
static inline status_t SWT_RxPSFPConfigPortISI(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_psfp_isi_config *config)
Configure Ingress stream identification for specified port.
- Parameters:
handle –
portIdx –
config –
- Returns:
status_t
-
static inline uint32_t SWT_RxPSFPGetISITableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of stream identification table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Filter, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddISITableEntry(swt_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)
Add an entry into the stream identification table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPQueryISITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_isi_config_t *config)
Query an entry in ingress stream identification table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
-
status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp)
Query an entry in ingress stream identification table using key match.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
-
status_t SWT_RxPSFPDelISITableEntry(swt_handle_t *handle, uint32_t entryID)
Delete an entry in the stream identification table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetISTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of ingress stream table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddISTableEntry(swt_handle_t *handle, netc_tb_is_config_t *config)
Add an entry into the ingress stream table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPUpdateISTableEntry(swt_handle_t *handle, netc_tb_is_config_t *config)
Updtae an entry in the ingress stream table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPQueryISTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_is_config_t *config)
Query an entry in ingress stream table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPDelISTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete an entry in the stream identification table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetISFTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number (entry size is 24 bytes) of ingress stream filter table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
-
static inline uint32_t SWT_RxPSFPGetISFTableMaxEntryNum(swt_handle_t *handle)
Get maximum available entry number (entry size is 24 bytes) of ingress stream filter table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddISFTableEntry(swt_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)
Add an entry into the ingress stream filter table.
- Parameters:
handle –
config –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPUpdateISFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)
Update an entry in the ingress stream filter table.
- Parameters:
handle –
entryID –
cfg –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPDelISFTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete an entry in the ingress stream filter table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetRPTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of Rate Policer table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
static inline uint32_t SWT_RxPSFPGetRPTableMaxEntryNum(swt_handle_t *handle)
Get maximum available entry number (entry size is 24 bytes) of Rate Policer table.
Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)
Add entry to Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPUpdateRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)
Update entry in Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPAddOrUpdateRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)
Add or update entry in Rate Policer table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPDelRPTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry in the Rate Policer table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPQueryRPTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp)
Query entry in the stream Rate Policer table.
- Parameters:
handle –
entryID –
rsp –
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPGetRPStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)
Get statistic of specified Rate Policer entry.
- Parameters:
handle –
entryID –
statis –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPResetMRRPTableEntry(swt_handle_t *handle, uint32_t entryID)
Reset mark red parameter of specified Rate Policer entry.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetISCTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of ingress stream count table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPQueryISFTableEntry(swt_handle_t *handle, netc_tb_isf_keye_t *keye, netc_tb_isf_rsp_data_t *rsp)
Query entry from the Ingress Stream Filter table.
- Parameters:
handle –
keye –
rsp –
- Returns:
status_t
-
status_t SWT_RxPSFPAddISCTableEntry(swt_handle_t *handle, uint32_t entryID)
Add entry in ingress stream count table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPGetISCStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)
Get ingress stream count statistic.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPResetISCStatistic(swt_handle_t *handle, uint32_t entryID)
Reset the count of the ingress stream count.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetSGITableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of stream gate instance table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
static inline uint32_t SWT_RxPSFPGetSGITableMaxEntryNum(swt_handle_t *handle)
Get maximum entry number of stream gate instance table.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_t *config)
Add entry in stream gate instance table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPUpdateSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_t *config)
Update entry in stream gate instance table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPDelSGITableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry in stream gate instance table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPGetSGIState(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state)
Get state of the stream gate instance for specified entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp)
Query entry in the stream gate instance table.
- Parameters:
handle –
entryID –
rsp –
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_RxPSFPGetSGCLTableRemainWordNum(swt_handle_t *handle)
Get remaining available words number of Stream Gate Control List table.
Note
This is a dynamic bounded index table, and number of words required for a stream gate control list is 1+N/2 where N is number of gate time slots in the stream gate control list. The remaining word should be greater than the want added entry size
- Parameters:
handle –
- Returns:
uint32_t
-
static inline uint32_t SWT_RxPSFPGetSGCLTableMaxWordNum(swt_handle_t *handle)
Get maximum words number of Stream Gate Control List table.
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_RxPSFPAddSGCLTableEntry(swt_handle_t *handle, netc_tb_sgcl_gcl_t *config)
Add entry into Stream Gate Control List Table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPDelSGCLTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry of Stream Gate Control List Table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPGetSGCLGateList(swt_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)
Get Stream Gate Control List Table entry gate control list.
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_RxPSFPGetSGCLState(swt_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)
Get state (ref count) for Stream Gate Control List table entry.
- Parameters:
handle –
entryID –
state –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
Switch (SWT) Statistic Module
-
static inline status_t SWT_GetCutThroughForwardStatistic(swt_handle_t *handle, uint32_t *statistic)
Get Switch cut through forwarding count.
Get the Cut-through frames counter of frames forwarded to at least one egress port.
- Parameters:
handle –
statistic – pointer to the statistic count data
- Returns:
kStatus_Success
-
status_t SWT_GetETMCongestionGroupStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_etmcg_stse_t *statistic)
Get statistic of the congestion group.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_GetETMClassQueueStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_etmcq_stse_t *statistic)
Get the statistic for the class queue in specified switch port.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline uint32_t SWT_GetECEntryNum(swt_handle_t *handle)
Get egress count table entry number.
Note
This is a static bounded index table, so all entries in the table are available for SWT_GetECStatistic()/SWT_ResetECStatistic() API
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_GetECStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_ec_stse_t *statistic)
Get statistic for specified egress count table entry.
- Parameters:
handle –
entryID –
statistic –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_ResetECStatistic(swt_handle_t *handle, uint32_t entryID)
Reset statistic for specified egress count table entry.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
static inline status_t SWT_GetPortDiscardStatistic(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_discard_tpye_t discardType, netc_port_discard_statistic_t *statistic)
Get the port discard statistic and reason.
Get the discarded count of frames and its reasons.
- Parameters:
handle –
portIdx – port index
discardType – Port discard type.
statistic – pointer to the statistic data
- Returns:
kStatus_Success
-
static inline status_t SWT_ClearPortDiscardReason(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_discard_tpye_t discardType, uint32_t reason0, uint32_t reason1)
Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.
- Parameters:
handle –
portIdx – port index
discardType – Port discard type.
reason0 –
reason1 –
- Returns:
kStatus_Success
-
static inline status_t SWT_GetFDBInUseEntriesNumber(swt_handle_t *handle, netc_switch_inuse_fdb_statistic_t *statistic)
Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.
- Parameters:
handle –
statistic –
- Returns:
kStatus_Success
-
static inline uint32_t SWT_GetPortTGSListStatus(swt_handle_t *handle, netc_hw_port_idx_t portIdx)
Get Switch port time gate scheduling gate list status.
- Parameters:
handle –
portIdx – port index
- Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t
Switch (SWT) Egress data path configuration
-
static inline status_t SWT_TxSDUConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tc_sdu_config_t *config)
Configure the transmit maximum SDU for port Traffic Class.
- Parameters:
handle –
portIdx –
tcIdx –
config –
- Returns:
status_t
-
static inline status_t SWT_TxCBSConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tc_cbs_config_t *config)
Configure the Credit Based Shaper for port Traffic Class.
- Parameters:
handle –
portIdx –
tcIdx –
config –
- Returns:
status_t
-
status_t SWT_TxTGSConfigAdminGcl(swt_handle_t *handle, netc_tb_tgs_gcl_t *config)
Config the Time Gate Scheduling entry admin gate control list.
This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxtTGSGetOperGcl(swt_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)
Get Time Gate Scheduling entry operation gate control list.
This function is used to read the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
- Parameters:
handle –
gcl –
length –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxTrafficClassConfig(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config)
Config the TC (traffic class) property.
- Parameters:
handle –
portIdx –
tcIdx –
config –
- Returns:
status_t
-
status_t SWT_TxPortTGSEnable(swt_handle_t *handle, netc_hw_port_idx_t portIdx, bool enable, uint8_t gateState)
Enable the switch port time gate scheduling.
- Parameters:
handle –
portIdx –
enable –
gateState –
- Returns:
status_t
-
static inline uint32_t SWT_TxEPPGetETTableRemainEntryNum(swt_handle_t *handle)
Get remaining available entry number of egress treatment table.
Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it
- Parameters:
handle –
- Returns:
uint32_t
-
status_t SWT_TxEPPAddETTableEntry(swt_handle_t *handle, netc_tb_et_config_t *config)
Add entry in the egress treatment table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxEPPUpdateETTableEntry(swt_handle_t *handle, netc_tb_et_config_t *config)
Update entry in the egress treatment table.
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxEPPQueryETTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_et_config_t *config)
Query an entry in the egress treatment table.
- Parameters:
handle –
entryID –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxEPPDelETTableEntry(swt_handle_t *handle, uint32_t entryID)
Delete entry for the egress treatment table.
- Parameters:
handle –
entryID –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxEPPQosToVlanConfig(swt_handle_t *handle, const netc_swt_qos_to_vlan_config_t *config)
Configure switch egress QOS to VLAN map classification.
- Parameters:
handle –
config –
- Returns:
status_t
-
status_t SWT_TxETMConfigClassScheduler(swt_handle_t *handle, netc_tb_etmcs_config_t *config)
Configure the WBFS and Strict priority for each PORT by using ETM Class Scheduler table.
Note
There is one class queue scheduler per switch port, and there is limitation between TSD and class queue scheduler configuration
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxETMConfigClassQueue(swt_handle_t *handle, netc_tb_etmcq_config_t *config)
Configure the class queue to congestion group map by using ETM class queue table.
Note
The number of class queue table entry is equal to the number of class queues in the switch
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
-
status_t SWT_TxETMConfigCongestionGroup(swt_handle_t *handle, netc_tb_etmcg_config_t *config)
Config congestion group map by using ETM congestion group table.
Note
The number of congestion groups table entry is equal to the number of class queues in the switch
- Parameters:
handle –
config –
- Returns:
status_t
- Returns:
See netc_cmd_error_t
Switch (SWT) Transmit/Receive
-
enum _swt_mgmt_tx_opt_flags
Switch management Tx Option flags.
Values:
-
enumerator kSWT_TX_OPT_VLAN_INSERT
Enable VLAN insert, only active when use Switch Port masquerading Tx option.
-
enumerator kSWT_TX_OPT_OFFLOAD
Tx offload.
-
enumerator kSWT_TX_OPT_VLAN_INSERT
-
typedef union _swt_mgmt_tx_arg_t swt_mgmt_tx_arg_t
Switch management Tx parameter.
-
typedef enum _swt_mgmt_tx_opt_flags swt_mgmt_tx_opt_flags
Switch management Tx Option flags.
-
typedef struct _swt_tx_opt swt_tx_opt
-
status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, const swt_transfer_config_t *txRxConfig)
Set the EP handle used by switch frame management.
- Parameters:
handle –
epHandle – The EP handle
txRxConfig – Switch transfer config
- Return values:
status_t –
-
status_t SWT_SendFrame(swt_handle_t *handle, netc_frame_struct_t *frame, void *context, swt_tx_opt *opt)
Transmits a frame on management port.
- Parameters:
handle – The SWT handle
frame – The frame descriptor pointer
context – Private context provided back on reclaim
opt – Tx options.
- Return values:
status_t –
-
static inline void SWT_WaitUnitilTxComplete(swt_handle_t *handle, bool enMasquerade, uint8_t ring)
Wait until the EP Tx ring has completed the transfer.
Note
Only call after EP_SendFrame() to do a no-interrupt transfer
- Parameters:
handle –
ring – Tx ring.
-
void SWT_ReclaimTxDescriptor(swt_handle_t *handle, uint8_t ring)
Reclaim tx descriptors. This function is used to update the tx descriptor status. For each reclaimed transmit frame the ep_reclaim_cb_t is called.
This is called after being notified of a transmit completion from ISR. It runs until there are no more frames to be reclaimed in the BD ring.
- Parameters:
handle –
ring – Tx ring.
-
status_t SWT_ReceiveFrame(swt_handle_t *handle, netc_frame_struct_t *frame, netc_frame_attr_t *attr)
Receives management frames (host reason not zero) with zero copy.
- Parameters:
handle –
frame – The frame descriptor pointer
attr – Frame attribute pointer
- Returns:
kStatus_Success Successfully receive a management (host reason not zero) frame frame
- Returns:
kStatus_NETC_RxHRZeroFrame Frame in Rx BD ring is regular frame, need call EP_ReceiveFrame()
- Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response
- Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty
- Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped
- Returns:
kStatus_InvalidArgument No Rx BD ring is available
- Returns:
kStatus_NETC_LackOfResource Appliction provided buffer is not enough
-
status_t SWT_ReceiveFrameCopy(swt_handle_t *handle, void *buffer, uint32_t length, netc_frame_attr_t *attr)
Receives management frame (host reason not zero) which will be copied in the provided buffer.
Note
The buffer size MUST be queried using SWT_GetRxFrameSize() beforehand.
- Parameters:
handle –
buffer – Buffer address
length – Buffer length
attr – Frame attribute pointer
- Returns:
kStatus_Success Successfully receive a management (host reason not zero) frame frame
- Returns:
kStatus_InvalidArgument No Rx BD ring is available
-
status_t SWT_GetRxFrameSize(swt_handle_t *handle, uint32_t *length)
brief Gets the size of the pending frame in the specified receive ring buffer.
Note
Frame size without FCS, and the size will be zero when Rx BD is Timestamp Reference Response message.
- Parameters:
handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.
length – The length of the valid frame received.
- Returns:
kStatus_Success Successfully get the length of a management (host reason not zero) frame
- Returns:
kStatus_NETC_RxHRZeroFrame Frame in Rx BD ring is regular frame, need call EP_GetRxFrameSize() to get frame size
- Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response
- Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty
- Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped
- Returns:
kStatus_InvalidArgument No Rx BD ring is available
-
union _swt_mgmt_tx_arg_t
- #include <fsl_netc_switch.h>
Switch management Tx parameter.
Public Members
-
uint8_t ring
Tx ring index, use for Switch Port masquerading Tx option
- struct _swt_mgmt_tx_arg_t
-
uint8_t ring
-
struct _swt_tx_opt
- #include <fsl_netc_switch.h>
Public Members
-
uint8_t ring
Tx ring index.
-
uint32_t flags
A bitmask of @swt_mgmt_tx_opt_flags.
-
netc_enetc_vlan_tag_t vlan
VLAN tag which will be inserted, used if enVlanInsert is set.
-
netc_tx_offload_t offload
Offload parameters.
-
uint8_t ring
-
struct _swt_transfer_config
- #include <fsl_netc_switch.h>
Transfer configuration structure for Switch.
Note
When need use Switch/EP receive APIs, recommended enable mgmtRxBdrConfig to use special MgmtRxBdRing rings to receive these host reason not-zero frames
Public Members
-
bool rxCacheMaintain
Enable/Disable Rx buffer cache maintain in driver.
-
bool txCacheMaintain
Enable/Disable Tx buffer cache maintain in driver.
-
bool rxZeroCopy
Enable zero-copy receive mode.
-
swt_rx_alloc_cb_t rxBuffAlloc
Callback function to alloc memory, must be provided for zero-copy Rx.
-
swt_rx_free_cb_t rxBuffFree
Callback function to free memory, must be provided for zero-copy Rx.
-
bool enUseMgmtRxBdRing
Enable/Disable use Switch management Rx BD ring, if disabled, the Switch/EP receive APIs (SWT_GetRxFrameSize()/SWT_ReceiveFrameCopy()/SWT_GetTimestampRefResp()/SWT_ReceiveFrame()) will use EP Rx BD ring 0 to receive frames.
-
netc_rx_bdr_config_t mgmtRxBdrConfig
Switch management Rx BD ring configuration.
-
bool enUseMgmtTxBdRing
Enable/Disable use Switch management Tx BD ring, if disabled, can’t use Switch transfer API (SWT_SendFrame()) to send frames.
-
netc_tx_bdr_config_t mgmtTxBdrConfig
Switch management Rx BD ring configuration.
-
swt_reclaim_cb_t reclaimCallback
Callback for reclaimed Tx Switch management frames.
-
void *userData
User data, return in callback.
-
bool rxCacheMaintain
-
struct __unnamed218__
Public Members
-
uint8_t ipv
Internal Priority Value, use for Direct Switch Enqueue Tx option
-
uint8_t dr
Discard Resiliance, use for Direct Switch Enqueue Tx option
-
uint8_t ipv
NETC Timer Driver
Timer adjustment module
-
void NETC_TimerGetTime(ENETC_PF_TMR_Type *base, uint64_t *nanosecond)
Get the timer’s current or default time.
- Parameters:
base – NETC timer base address.
nanosecond – Time in nanosecond.
-
void NETC_TimerGetCurrentTime(netc_timer_handle_t *handle, uint64_t *nanosecond)
Get the timer’s current time.
- Parameters:
handle – NETC timer handle.
nanosecond – Time in nanosecond.
-
void NETC_TimerGetFreeRunningTime(netc_timer_handle_t *handle, uint64_t *nanosecond)
Get the timer’s freerunning time.
- Parameters:
handle – NETC timer handle.
nanosecond – Time in nanosecond.
-
void NETC_TimerAddOffset(netc_timer_handle_t *handle, int64_t nanosecond)
Correct the current timer.
Note
Need stop all mechanims based on 1588 timers during call this API. To take time gate scheduling as example, if the port is enabled with TGS and it contains an operational list, user need to call SWT_TxPortTGSEnable()/SWT_TxPortTGSEnable() to disable the port time gate before call this API, and re-enable and configure the port TGS after the execution of this API.
- Parameters:
handle – NETC timer handle.
nanosecond – Time in nanosecond.
-
void NETC_TimerAdjustFreq(netc_timer_handle_t *handle, int32_t ppb)
Adjust the timer frequency.
- Parameters:
handle – NETC timer handle.
ppb – Parts per billion.
-
void NETC_TimerGetFrtSrtTime(netc_timer_handle_t *handle, uint64_t *frt, uint64_t *srt)
Get the free running and synchronized current time with an atomic read.
- Parameters:
handle – NETC timer handle.
frt – The free-running time in nanosecond.
srt – The synchronized current time in nanosecond.
Timer initialization module
-
enum _netc_timer_irq_flags
Timer interrupt flags.
Values:
-
enumerator kNETC_TimerFiper1IrqFlag
Periodic pulse 1 interrupt.
-
enumerator kNETC_TimerFiper2IrqFlag
Periodic pulse 2 interrupt.
-
enumerator kNETC_TimerFiper3IrqFlag
Periodic pulse 3 interrupt.
-
enumerator kNETC_TimerAlarm1IrqFlag
Alarm 1 interrupt.
-
enumerator kNETC_TimerAlarm2IrqFlag
Alarm 2 interrupt.
-
enumerator kNETC_TimerExtTrig1ThresholdIrqFlag
External trigger 1 timestamp FIFO threshold hit interrupt.
-
enumerator kNETC_TimerExtTrig2ThresholdIrqFlag
External trigger 2 timestamp FIFO threshold hit interrupt.
-
enumerator kNETC_TimerExtTrig1TsAvailIrqFlag
External trigger 1 new timestamp available interrupt.
-
enumerator kNETC_TimerExtTrig2TsAvailIrqFlag
External trigger 2 new timestamp available interrupt.
-
enumerator kNETC_TimerExtTrig1OverflowIrqFlag
External trigger 1 timestamp FIFO overflow interrupt.
-
enumerator kNETC_TimerExtTrig2OverflowIrqFlag
External trigger 2 timestamp FIFO overflow interrupt.
-
enumerator kNETC_TimerFiper1IrqFlag
-
enum _netc_timer_ref_clk
Enumeration for NETC timer reference clock.
Values:
-
enumerator kNETC_TimerExtRefClk
-
enumerator kNETC_TimerSystemClk
-
enumerator kNETC_TimerExtRefClk
-
typedef enum _netc_timer_irq_flags netc_timer_irq_flags_t
Timer interrupt flags.
-
typedef struct _netc_timer_handle netc_timer_handle_t
-
typedef enum _netc_timer_ref_clk netc_timer_ref_clk_t
Enumeration for NETC timer reference clock.
-
typedef struct _netc_timer_config netc_timer_config_t
Structure to configure timer.
-
status_t NETC_TimerInit(netc_timer_handle_t *handle, const netc_timer_config_t *config)
Initialize the NETC PTP1588 timer.
- Parameters:
handle – NETC timer handle.
config – The configuration of the timer.
- Returns:
status_t
-
void NETC_TimerDeinit(netc_timer_handle_t *handle)
Deinitialize the NETC PTP1588 timer.
- Parameters:
handle – NETC timer handle.
-
void NETC_TimerInitHandle(netc_timer_handle_t *handle)
Initialize a NETC PTP1588 timer handle.
- Parameters:
handle – NETC timer handle.
-
void NETC_TimerEnable(netc_timer_handle_t *handle, bool enable)
Enable/Disable the NETC PTP1588 timer.
- Parameters:
handle – NETC timer handle.
enable – Whether enable the PTP1588 timer.
-
struct _netc_timer_handle
- #include <fsl_netc_timer.h>
Timer handler structure.
Public Members
-
netc_timer_hw_t hw
Hardware register map resource.
-
uint32_t timerFreq
Timer clock frequency(Hz).
-
uint8_t entryNum
MSIX entry number.
-
netc_timer_hw_t hw
-
struct _netc_timer_config
- #include <fsl_netc_timer.h>
Structure to configure timer.
Public Members
-
bool clkOutputPhase
True: Inverted divided clock is output, False: Non-inverted divided clock is output.
-
bool clkInputPhase
True: Inverted frequency tuned timer input clock, False: Non-inverted frequency tuned timer input clock.
-
bool enableTimer
True: Enable 1588 timer, False: Disable 1588 timer, use default counter.
-
bool atomicMode
True: Allow atomic updates to TMR_PERIOD and TMR_ADD, False: Disable it.
-
netc_timer_ref_clk_t clockSelect
Timer reference clock.
-
uint32_t refClkHz
Timer reference clock frequency in Hz.
-
int32_t defaultPpb
Default ppb.
-
netc_msix_entry_t *msixEntry
MSIX table entry array.
-
uint8_t entryNum
MSIX entry number.
-
bool clkOutputPhase
Local time synchronization module
-
enum _netc_timer_alarm_index
Enumeration for NETC timer alarm index.
Values:
-
enumerator kNETC_TimerAlarm1
-
enumerator kNETC_TimerAlarm2
-
enumerator kNETC_TimerAlarm1
-
enum _netc_timer_fiper_index
Enumeration for NETC timer FIPER index.
Values:
-
enumerator kNETC_TimerFiper1
-
enumerator kNETC_TimerFiper2
-
enumerator kNETC_TimerFiper3
-
enumerator kNETC_TimerFiper1
-
typedef enum _netc_timer_alarm_index netc_timer_alarm_index_t
Enumeration for NETC timer alarm index.
-
typedef struct _netc_timer_alarm_t netc_timer_alarm_t
Structure to configure timer alarm.
-
typedef enum _netc_timer_fiper_index netc_timer_fiper_index_t
Enumeration for NETC timer FIPER index.
-
typedef struct _netc_timer_fiper_config netc_timer_fiper_config_t
Structure to configure timer FIPER.
-
typedef struct _netc_timer_fiper netc_timer_fiper_t
Structure to set and start timer FIPER.
-
typedef struct _netc_timer_ext_pulse_trig netc_timer_ext_trig_t
Structure to configure external pulse trigger timestamp.
-
void NETC_TimerConfigureAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId, const netc_timer_alarm_t *alarm)
Configure the timer alarm feature.
- Parameters:
handle – NETC timer handle.
alarmId – The alarm index.
alarm – The timer alarm configuration structure.
-
void NETC_TimerStartAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId, uint64_t nanosecond)
Start the alarm with specified time after alarm feature is configured This function can generate a pulse on a GPIO and/or an interrupt at specified future time. It also can trigger FIPER at specified time.
- Parameters:
handle – NETC timer handle.
alarmId – The alarm index.
nanosecond – The time in nanosecond to generate alarm pulse.
-
void NETC_TimerStopAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId)
Stop the alarm before/after it’s fired This function can deactivate alarm.
- Parameters:
handle – NETC timer handle.
alarmId – The alarm index.
-
void NETC_TimerConfigureFIPER(netc_timer_handle_t *handle, const netc_timer_fiper_config_t *config)
Configure the timer FIPER feature.
- Parameters:
handle – NETC timer handle.
config – The timer FIPER configuration structure.
-
void NETC_TimerStartFIPER(netc_timer_handle_t *handle, netc_timer_fiper_index_t fiperId, const netc_timer_fiper_t *fiper)
Start the timer FIPER to generate pulse This function can generate a periodic(Fixed Period-FIPER) pulse on a GPIO pin and/or an interrupt to the host.
- Parameters:
handle – NETC timer handle.
fiperId – The timer FIPER index.
fiper – The timer FIPER configuration structure.
-
void NETC_TimerStopFIPER(netc_timer_handle_t *handle, netc_timer_fiper_index_t fiperId)
Stop the timer FIPER to generate pulse.
- Parameters:
handle – NETC timer handle.
fiperId – The timer FIPER index.
-
void NETC_TimerConfigureExtPulseTrig(netc_timer_handle_t *handle, netc_timer_exttrig_index_t extTrigId, const netc_timer_ext_trig_t *extTrig)
Configure the external pulse trigger timestamp capture.
- Parameters:
handle – NETC timer handle.
extTrigId – The timer FIPER index.
extTrig – The external pulse trigger configuration structure.
-
status_t NETC_TimerSetTsFifoThreshold(netc_timer_handle_t *handle, uint8_t threshold)
Set timestamp FIFO threshold of the external pulse trigger timestamp capture.
- Parameters:
handle – NETC timer handle.
threshold – Timestamp FIFO threshold.
- Returns:
status_t
-
status_t NETC_TimerReadExtPulseCaptureTime(netc_timer_handle_t *handle, netc_timer_exttrig_index_t extTrigId, uint64_t *nanosecond)
Read the timestamp captured by external pulse trigger in FIFO.
- Parameters:
handle – NETC timer handle.
extTrigId – The timer FIPER index.
nanosecond – Timestamp in nanosecond.
- Returns:
status_t
-
static inline void NETC_TimerClearInterruptStatus(netc_timer_handle_t *handle, uint32_t flags)
Clear timer interrupt flags.
- Parameters:
handle – NETC timer handle.
flags – Timer interrupt flags. This is a logical OR of enumeration :: netc_timer_irq_flags_t.
-
status_t NETC_TimerMsixSetGlobalMask(netc_timer_handle_t *handle, bool mask)
Set the global MSIX mask status.
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.
- Parameters:
handle – The timer handle
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
-
status_t NETC_TimerMsixSetEntryMask(netc_timer_handle_t *handle, uint8_t entryIdx, bool mask)
Set the MSIX entry mask status for specified entry.
This function masks/unmasks MSIX message for specified entry.
- Parameters:
handle – NETC timer handle.
entryIdx – The entry index in the table.
mask – The mask state. True: Mask, False: Unmask.
- Returns:
status_t
-
status_t NETC_TimerMsixGetPendingStatus(netc_timer_handle_t *handle, uint8_t pbaIdx, uint64_t *status)
Get the MSIX pending status in MSIX PBA table.
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.
- Parameters:
handle – NETC timer handle.
pbaIdx – The index of PBA array with 64-bit unit.
status – Pending status bit mask, bit n for entry n.
- Returns:
status_t
-
struct _netc_timer_alarm_t
- #include <fsl_netc_timer.h>
Structure to configure timer alarm.
Public Members
-
bool enableInterrupt
Enable/Disable ALARM interrupt enable.
-
bool polarity
True: Active low output, False: Active high output.
-
bool pulseGenSync
True: ALARM output asserted synchronous to timer generated clock, False: ALARM output asserted immediately.
-
uint8_t pulseWidth
Pulse width in number of timer generated clocks the alarm will be active for.
-
bool enableInterrupt
-
struct _netc_timer_fiper_config
- #include <fsl_netc_timer.h>
Structure to configure timer FIPER.
Public Members
-
bool startCondition
True: FIPER is enabled through timer enable and alarm getting set, False: FIPER is enabled through timer enable.
-
bool fiper1Loopback
True: FIPER1 pulse is looped back into Trigger1 input, False: Trigger1 input is based upon normal external trigger input.
-
bool fiper2Loopback
True: FIPER2 pulse is looped back into Trigger2 input, False: Trigger2 input is based upon normal external trigger input.
-
uint16_t prescale
Output FIPER pulse clock is generated by dividing the timer input clock by this number. Must be an even value.
-
bool startCondition
-
struct _netc_timer_fiper
- #include <fsl_netc_timer.h>
Structure to set and start timer FIPER.
Public Members
-
bool enableInterrupt
Enable/Disable FIPER interrupt interrupt.
-
bool pulseGenSync
True: FIPER output asserted synchronous to timer generated clock, False: FIPER output asserted immediately.
-
uint8_t pulseWidth
FIPER pulse width.
-
uint32_t pulsePeriod
Interval of FIPER pulses.
-
bool enableInterrupt
-
struct _netc_timer_ext_pulse_trig
- #include <fsl_netc_timer.h>
Structure to configure external pulse trigger timestamp.
Public Members
-
bool polarity
Time stamp on the falling(true)/rising(false) edge of the external trigger.
-
bool enableFifoOverflowInterrupt
Enable/Disable FIFO Overflow interrupt.
-
bool enableFifoThresholdHitInterrupt
Enable/Disable FIFO Threshold Hit interrupt.
-
bool enableTsAvailInterrupt
Enable/Disable timestamp capture interrupt.
-
bool polarity
OTFAD: On The Fly AES-128 Decryption Driver
-
void OTFAD_GetDefaultConfig(otfad_config_t *config)
OTFAD module initialization function.
- Parameters:
config – OTFAD configuration.
- AT_QUICKACCESS_SECTION_CODE (void OTFAD_Init(OTFAD_Type *base, const otfad_config_t *config))
OTFAD module initialization function.
- Parameters:
base – OTFAD base address.
config – OTFAD configuration.
- AT_QUICKACCESS_SECTION_CODE (void OTFAD_Deinit(OTFAD_Type *base))
Deinitializes the OTFAD.
-
static inline uint32_t OTFAD_GetOperateMode(OTFAD_Type *base)
OTFAD module get operate mode.
- Parameters:
base – OTFAD base address.
-
static inline uint32_t OTFAD_GetStatus(OTFAD_Type *base)
OTFAD module get status.
- Parameters:
base – OTFAD base address.
-
status_t OTFAD_SetEncryptionConfig(OTFAD_Type *base, const otfad_encryption_config_t *config)
OTFAD module set encryption configuration.
Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region.
- Parameters:
base – OTFAD base address.
config – encryption configuration.
-
status_t OTFAD_GetEncryptionConfig(OTFAD_Type *base, otfad_encryption_config_t *config)
OTFAD module get encryption configuration.
Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region.
- Parameters:
base – OTFAD base address.
config – encryption configuration.
-
status_t OTFAD_HitDetermination(OTFAD_Type *base, uint32_t address, uint8_t *contextIndex)
OTFAD module do hit determination.
- Parameters:
base – OTFAD base address.
address – the physical address space assigned to the QuadSPI(FlexSPI) module.
contextIndex – hitted context region index.
- Returns:
status, such as kStatus_Success or kStatus_OTFAD_ResRegAccessMode.
-
FSL_OTFAD_DRIVER_VERSION
Driver version.
Status codes for the OTFAD driver.
Values:
-
enumerator kStatus_OTFAD_ResRegAccessMode
Restricted register mode
-
enumerator kStatus_OTFAD_AddressError
End address less than start address
-
enumerator kStatus_OTFAD_RegionOverlap
the OTFAD does not support any form of memory region overlap, for system accesses that hit in multiple contexts or no contexts, the fetched data is simply bypassed
-
enumerator kStatus_OTFAD_RegionMiss
For accesses that hit in a single context, but not the selected one
-
enumerator kStatus_OTFAD_ResRegAccessMode
OTFAD context type.
Values:
-
enumerator kOTFAD_Context_0
context 0
-
enumerator kOTFAD_Context_1
context 1
-
enumerator kOTFAD_Context_2
context 2
-
enumerator kOTFAD_Context_3
context 3
-
enumerator kOTFAD_Context_0
OTFAD operate mode.
Values:
-
enumerator kOTFAD_NRM
Normal Mode
-
enumerator kOTFAD_SVM
Security Violation Mode
-
enumerator kOTFAD_LDM
Logically Disabled Mode
-
enumerator kOTFAD_NRM
-
typedef struct _otfad_encryption_config otfad_encryption_config_t
OTFAD encryption configuration structure.
-
typedef struct _otfad_config otfad_config_t
OTFAD configuration structure.
-
struct _otfad_encryption_config
- #include <fsl_otfad.h>
OTFAD encryption configuration structure.
Public Members
-
bool valid
The context is valid or not
-
bool AESdecryption
AES decryption enable
-
uint8_t readOnly
read write attribute for the entire set of context registers
-
uint8_t contextIndex
OTFAD context index
-
uint32_t startAddr
Start address
-
uint32_t endAddr
End address
-
uint32_t key[4]
Encryption key
-
uint32_t counter[2]
Encryption counter
-
bool valid
-
struct _otfad_config
- #include <fsl_otfad.h>
OTFAD configuration structure.
Public Members
-
bool forceSVM
Force entry into SVM after a write
-
bool forceLDM
Force entry into LDM after a write
-
bool restrictedRegAccess
Restricted register access enable
-
bool enableOTFAD
OTFAD has decryption enabled
-
bool forceSVM
PDM: Microphone Interface
PDM Driver
-
void PDM_Init(PDM_Type *base, const pdm_config_t *config)
Initializes the PDM peripheral.
Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. The configuration structure can be custom filled or set with default values by PDM_GetDefaultConfig().
Note
This API should be called at the beginning of the application to use the PDM driver. Otherwise, accessing the PDM module can cause a hard fault because the clock is not enabled.
- Parameters:
base – PDM base pointer
config – PDM configuration structure.
-
void PDM_Deinit(PDM_Type *base)
De-initializes the PDM peripheral.
This API gates the PDM clock. The PDM module can’t operate unless PDM_Init is called to enable the clock.
- Parameters:
base – PDM base pointer
-
static inline void PDM_Reset(PDM_Type *base)
Resets the PDM module.
- Parameters:
base – PDM base pointer
-
static inline void PDM_Enable(PDM_Type *base, bool enable)
Enables/disables PDM interface.
- Parameters:
base – PDM base pointer
enable – True means PDM interface is enabled, false means PDM interface is disabled.
-
static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable)
Enables/disables debug mode for PDM. The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode.
- Parameters:
base – PDM base pointer
enable – True means PDM interface enter debug mode, false means PDM interface in normal mode.
-
static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable)
Enables/disables PDM interface in debug mode.
- Parameters:
base – PDM base pointer
enable – True means PDM interface is enabled debug mode, false means PDM interface is disabled after after completing the current frame in debug mode.
-
static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable)
Enables/disables PDM interface disable/Low Leakage mode.
- Parameters:
base – PDM base pointer
enable – True means PDM interface is in disable/low leakage mode, False means PDM interface is in normal mode.
-
static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable)
Enables/disables the PDM channel.
- Parameters:
base – PDM base pointer
channel – PDM channel number need to enable or disable.
enable – True means enable PDM channel, false means disable.
-
void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config)
PDM one channel configurations.
- Parameters:
base – PDM base pointer
config – PDM channel configurations.
channel – channel number. after completing the current frame in debug mode.
-
status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ)
PDM set sample rate.
Note
This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is
PDM_Init(base, pdmConfig) PDM_SetChannelConfig(base, channel, &channelConfig) PDM_SetSampleRateConfig(base, source, sampleRate)
- Parameters:
base – PDM base pointer
sourceClock_HZ – PDM source clock frequency.
sampleRate_HZ – PDM sample rate.
-
status_t PDM_SetSampleRate(PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv)
PDM set sample rate.
- Deprecated:
Do not use this function. It has been superceded by PDM_SetSampleRateConfig
- Parameters:
base – PDM base pointer
enableChannelMask – PDM channel enable mask.
qualityMode – quality mode.
osr – cic oversample rate
clkDiv – clock divider
-
uint32_t PDM_GetInstance(PDM_Type *base)
Get the instance number for PDM.
- Parameters:
base – PDM base pointer.
-
static inline uint32_t PDM_GetStatus(PDM_Type *base)
Gets the PDM internal status flag. Use the Status Mask in _pdm_internal_status to get the status value needed.
- Parameters:
base – PDM base pointer
- Returns:
PDM status flag value.
-
static inline uint32_t PDM_GetFifoStatus(PDM_Type *base)
Gets the PDM FIFO status flag. Use the Status Mask in _pdm_fifo_status to get the status value needed.
- Parameters:
base – PDM base pointer
- Returns:
FIFO status.
-
static inline uint32_t PDM_GetRangeStatus(PDM_Type *base)
Gets the PDM Range status flag. Use the Status Mask in _pdm_range_status to get the status value needed.
- Parameters:
base – PDM base pointer
- Returns:
output status.
-
static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask)
Clears the PDM Tx status.
- Parameters:
base – PDM base pointer
mask – State mask. It can be a combination of the status between kPDM_StatusFrequencyLow and kPDM_StatusCh7FifoDataAvaliable.
-
static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask)
Clears the PDM Tx status.
- Parameters:
base – PDM base pointer
mask – State mask.It can be a combination of the status in _pdm_fifo_status.
-
static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask)
Clears the PDM range status.
- Parameters:
base – PDM base pointer
mask – State mask. It can be a combination of the status in _pdm_range_status.
-
void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask)
Enables the PDM interrupt requests.
- Parameters:
base – PDM base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kPDM_ErrorInterruptEnable
kPDM_FIFOInterruptEnable
-
static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask)
Disables the PDM interrupt requests.
- Parameters:
base – PDM base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kPDM_ErrorInterruptEnable
kPDM_FIFOInterruptEnable
-
static inline void PDM_EnableDMA(PDM_Type *base, bool enable)
Enables/disables the PDM DMA requests.
- Parameters:
base – PDM base pointer
enable – True means enable DMA, false means disable DMA.
-
static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel)
Gets the PDM data register address.
This API is used to provide a transfer address for the PDM DMA transfer configuration.
- Parameters:
base – PDM base pointer.
channel – Which data channel used.
- Returns:
data register address.
-
void PDM_ReadFifo(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth)
PDM read fifo.
Note
: This function support 16 bit only for IP version that only supports 16bit.
- Parameters:
base – PDM base pointer.
startChannel – start channel number.
channelNums – total enabled channelnums.
buffer – received buffer address.
size – number of samples to read.
dataWidth – sample width.
-
void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain)
Set the PDM channel gain.
Please note for different quality mode, the valid gain value is different, reference RM for detail.
- Parameters:
base – PDM base pointer.
channel – PDM channel index.
gain – channel gain, the register gain value range is 0 - 15.
-
void PDM_SetHwvadConfig(PDM_Type *base, const pdm_hwvad_config_t *config)
Configure voice activity detector.
- Parameters:
base – PDM base pointer
config – Voice activity detector configure structure pointer .
-
static inline void PDM_ForceHwvadOutputDisable(PDM_Type *base, bool enable)
PDM hwvad force output disable.
- Parameters:
base – PDM base pointer
enable – true is output force disable, false is output not force.
-
static inline void PDM_ResetHwvad(PDM_Type *base)
PDM hwvad reset. It will reset VADNDATA register and will clean all internal buffers, should be called when the PDM isn’t running.
- Parameters:
base – PDM base pointer
-
static inline void PDM_EnableHwvad(PDM_Type *base, bool enable)
Enable/Disable Voice activity detector. Should be called when the PDM isn’t running.
- Parameters:
base – PDM base pointer.
enable – True means enable voice activity detector, false means disable.
-
static inline void PDM_EnableHwvadInterrupts(PDM_Type *base, uint32_t mask)
Enables the PDM Voice Detector interrupt requests.
- Parameters:
base – PDM base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kPDM_HWVADErrorInterruptEnable
kPDM_HWVADInterruptEnable
-
static inline void PDM_DisableHwvadInterrupts(PDM_Type *base, uint32_t mask)
Disables the PDM Voice Detector interrupt requests.
- Parameters:
base – PDM base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kPDM_HWVADErrorInterruptEnable
kPDM_HWVADInterruptEnable
-
static inline void PDM_ClearHwvadInterruptStatusFlags(PDM_Type *base, uint32_t mask)
Clears the PDM voice activity detector status flags.
- Parameters:
base – PDM base pointer
mask – State mask,reference _pdm_hwvad_int_status.
-
static inline uint32_t PDM_GetHwvadInterruptStatusFlags(PDM_Type *base)
Clears the PDM voice activity detector status flags.
- Parameters:
base – PDM base pointer
- Returns:
status, reference _pdm_hwvad_int_status
-
static inline uint32_t PDM_GetHwvadInitialFlag(PDM_Type *base)
Get the PDM voice activity detector initial flags.
- Parameters:
base – PDM base pointer
- Returns:
initial flag.
-
static inline void PDM_EnableHwvadSignalFilter(PDM_Type *base, bool enable)
Enables/disables voice activity detector signal filter.
- Parameters:
base – PDM base pointer
enable – True means enable signal filter, false means disable.
-
void PDM_SetHwvadSignalFilterConfig(PDM_Type *base, bool enableMaxBlock, uint32_t signalGain)
Configure voice activity detector signal filter.
- Parameters:
base – PDM base pointer
enableMaxBlock – If signal maximum block enabled.
signalGain – Gain value for the signal energy.
-
void PDM_SetHwvadNoiseFilterConfig(PDM_Type *base, const pdm_hwvad_noise_filter_t *config)
Configure voice activity detector noise filter.
- Parameters:
base – PDM base pointer
config – Voice activity detector noise filter configure structure pointer .
-
static inline void PDM_EnableHwvadZeroCrossDetector(PDM_Type *base, bool enable)
Enables/disables voice activity detector zero cross detector.
- Parameters:
base – PDM base pointer
enable – True means enable zero cross detector, false means disable.
-
void PDM_SetHwvadZeroCrossDetectorConfig(PDM_Type *base, const pdm_hwvad_zero_cross_detector_t *config)
Configure voice activity detector zero cross detector.
- Parameters:
base – PDM base pointer
config – Voice activity detector zero cross detector configure structure pointer .
-
static inline uint16_t PDM_GetNoiseData(PDM_Type *base)
Reads noise data.
- Parameters:
base – PDM base pointer.
- Returns:
Data in PDM noise data register.
-
static inline void PDM_SetHwvadInternalFilterStatus(PDM_Type *base, pdm_hwvad_filter_status_t status)
set hwvad internal filter status . Note: filter initial status should be asserted for two more cycles, then set it to normal operation.
- Parameters:
base – PDM base pointer.
status – internal filter status.
-
void PDM_SetHwvadInEnvelopeBasedMode(PDM_Type *base, const pdm_hwvad_config_t *hwvadConfig, const pdm_hwvad_noise_filter_t *noiseConfig, const pdm_hwvad_zero_cross_detector_t *zcdConfig, uint32_t signalGain)
set HWVAD in envelope based mode . Recommand configurations,
static const pdm_hwvad_config_t hwvadConfig = { .channel = 0, .initializeTime = 10U, .cicOverSampleRate = 0U, .inputGain = 0U, .frameTime = 10U, .cutOffFreq = kPDM_HwvadHpfBypassed, .enableFrameEnergy = false, .enablePreFilter = true, }; static const pdm_hwvad_noise_filter_t noiseFilterConfig = { .enableAutoNoiseFilter = false, .enableNoiseMin = true, .enableNoiseDecimation = true, .noiseFilterAdjustment = 0U, .noiseGain = 7U, .enableNoiseDetectOR = true, };
- Parameters:
base – PDM base pointer.
hwvadConfig – internal filter status.
noiseConfig – Voice activity detector noise filter configure structure pointer.
zcdConfig – Voice activity detector zero cross detector configure structure pointer .
signalGain – signal gain value.
-
void PDM_SetHwvadInEnergyBasedMode(PDM_Type *base, const pdm_hwvad_config_t *hwvadConfig, const pdm_hwvad_noise_filter_t *noiseConfig, const pdm_hwvad_zero_cross_detector_t *zcdConfig, uint32_t signalGain)
brief set HWVAD in energy based mode . Recommand configurations, code static const pdm_hwvad_config_t hwvadConfig = { .channel = 0, .initializeTime = 10U, .cicOverSampleRate = 0U, .inputGain = 0U, .frameTime = 10U, .cutOffFreq = kPDM_HwvadHpfBypassed, .enableFrameEnergy = true, .enablePreFilter = true, };
static const pdm_hwvad_noise_filter_t noiseFilterConfig = { .enableAutoNoiseFilter = true, .enableNoiseMin = false, .enableNoiseDecimation = false, .noiseFilterAdjustment = 0U, .noiseGain = 7U, .enableNoiseDetectOR = false, }; code param base PDM base pointer. param hwvadConfig internal filter status. param noiseConfig Voice activity detector noise filter configure structure pointer. param zcdConfig Voice activity detector zero cross detector configure structure pointer . param signalGain signal gain value, signal gain value should be properly according to application.
-
void PDM_EnableHwvadInterruptCallback(PDM_Type *base, pdm_hwvad_callback_t vadCallback, void *userData, bool enable)
Enable/Disable hwvad callback.
This function enable/disable the hwvad interrupt for the selected PDM peripheral.
- Parameters:
base – Base address of the PDM peripheral.
vadCallback – callback Pointer to store callback function, should be NULL when disable.
userData – user data.
enable – true is enable, false is disable.
- Return values:
None. –
-
void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData)
Initializes the PDM handle.
This function initializes the handle for the PDM transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – PDM base pointer.
handle – PDM handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function.
-
status_t PDM_TransferSetChannelConfig(PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format)
PDM set channel transfer config.
- Parameters:
base – PDM base pointer.
handle – PDM handle pointer.
channel – PDM channel.
config – channel config.
format – data format, support data width configurations,_pdm_data_width.
- Return values:
kStatus_PDM_ChannelConfig_Failed – or kStatus_Success.
-
status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer)
Performs an interrupt non-blocking receive transfer on PDM.
Note
This API returns immediately after the transfer initiates. Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer is finished.
- Parameters:
base – PDM base pointer
handle – Pointer to the pdm_handle_t structure which stores the transfer state.
xfer – Pointer to the pdm_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_PDM_Busy – Previous receive still not finished.
-
void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle)
Aborts the current IRQ receive.
Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – PDM base pointer
handle – Pointer to the pdm_handle_t structure which stores the transfer state.
-
void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle)
Tx interrupt handler.
- Parameters:
base – PDM base pointer.
handle – Pointer to the pdm_handle_t structure.
-
FSL_PDM_DRIVER_VERSION
Version 2.9.1
PDM return status.
Values:
-
enumerator kStatus_PDM_Busy
PDM is busy.
-
enumerator kStatus_PDM_CLK_LOW
PDM clock frequency low
-
enumerator kStatus_PDM_FIFO_ERROR
PDM FIFO underrun or overflow
-
enumerator kStatus_PDM_QueueFull
PDM FIFO underrun or overflow
-
enumerator kStatus_PDM_Idle
PDM is idle
-
enumerator kStatus_PDM_Output_ERROR
PDM is output error
-
enumerator kStatus_PDM_ChannelConfig_Failed
PDM channel config failed
-
enumerator kStatus_PDM_HWVAD_VoiceDetected
PDM hwvad voice detected
-
enumerator kStatus_PDM_HWVAD_Error
PDM hwvad error
-
enumerator kStatus_PDM_Busy
-
enum _pdm_interrupt_enable
The PDM interrupt enable flag.
Values:
-
enumerator kPDM_ErrorInterruptEnable
PDM channel error interrupt enable.
-
enumerator kPDM_FIFOInterruptEnable
PDM channel FIFO interrupt
-
enumerator kPDM_ErrorInterruptEnable
-
enum _pdm_internal_status
The PDM status.
Values:
-
enumerator kPDM_StatusDfBusyFlag
Decimation filter is busy processing data
-
enumerator kPDM_StatusFrequencyLow
Mic app clock frequency not high enough
-
enumerator kPDM_StatusCh0FifoDataAvaliable
channel 0 fifo data reached watermark level
-
enumerator kPDM_StatusCh1FifoDataAvaliable
channel 1 fifo data reached watermark level
-
enumerator kPDM_StatusCh2FifoDataAvaliable
channel 2 fifo data reached watermark level
-
enumerator kPDM_StatusCh3FifoDataAvaliable
channel 3 fifo data reached watermark level
-
enumerator kPDM_StatusDfBusyFlag
-
enum _pdm_channel_enable_mask
PDM channel enable mask.
Values:
-
enumerator kPDM_EnableChannel0
channgel 0 enable mask
-
enumerator kPDM_EnableChannel1
channgel 1 enable mask
-
enumerator kPDM_EnableChannel2
channgel 2 enable mask
-
enumerator kPDM_EnableChannel3
channgel 3 enable mask
-
enumerator kPDM_EnableChannelAll
-
enumerator kPDM_EnableChannel0
-
enum _pdm_fifo_status
The PDM fifo status.
Values:
-
enumerator kPDM_FifoStatusUnderflowCh0
channel0 fifo status underflow
-
enumerator kPDM_FifoStatusUnderflowCh1
channel1 fifo status underflow
-
enumerator kPDM_FifoStatusUnderflowCh2
channel2 fifo status underflow
-
enumerator kPDM_FifoStatusUnderflowCh3
channel3 fifo status underflow
-
enumerator kPDM_FifoStatusOverflowCh0
channel0 fifo status overflow
-
enumerator kPDM_FifoStatusOverflowCh1
channel1 fifo status overflow
-
enumerator kPDM_FifoStatusOverflowCh2
channel2 fifo status overflow
-
enumerator kPDM_FifoStatusOverflowCh3
channel3 fifo status overflow
-
enumerator kPDM_FifoStatusUnderflowCh0
-
enum _pdm_range_status
The PDM output status.
Values:
-
enumerator kPDM_RangeStatusUnderFlowCh0
channel0 range status underflow
-
enumerator kPDM_RangeStatusUnderFlowCh1
channel1 range status underflow
-
enumerator kPDM_RangeStatusUnderFlowCh2
channel2 range status underflow
-
enumerator kPDM_RangeStatusUnderFlowCh3
channel3 range status underflow
-
enumerator kPDM_RangeStatusOverFlowCh0
channel0 range status overflow
-
enumerator kPDM_RangeStatusOverFlowCh1
channel1 range status overflow
-
enumerator kPDM_RangeStatusOverFlowCh2
channel2 range status overflow
-
enumerator kPDM_RangeStatusOverFlowCh3
channel3 range status overflow
-
enumerator kPDM_RangeStatusUnderFlowCh0
-
enum _pdm_dc_remover
PDM DC remover configurations.
Values:
-
enumerator kPDM_DcRemoverCutOff20Hz
DC remover cut off 20HZ
-
enumerator kPDM_DcRemoverCutOff13Hz
DC remover cut off 13.3HZ
-
enumerator kPDM_DcRemoverCutOff40Hz
DC remover cut off 40HZ
-
enumerator kPDM_DcRemoverBypass
DC remover bypass
-
enumerator kPDM_DcRemoverCutOff20Hz
-
enum _pdm_df_quality_mode
PDM decimation filter quality mode.
Values:
-
enumerator kPDM_QualityModeMedium
quality mode memdium
-
enumerator kPDM_QualityModeHigh
quality mode high
-
enumerator kPDM_QualityModeLow
quality mode low
-
enumerator kPDM_QualityModeVeryLow0
quality mode very low0
-
enumerator kPDM_QualityModeVeryLow1
quality mode very low1
-
enumerator kPDM_QualityModeVeryLow2
quality mode very low2
-
enumerator kPDM_QualityModeMedium
-
enum _pdm_qulaity_mode_k_factor
PDM quality mode K factor.
Values:
-
enumerator kPDM_QualityModeHighKFactor
high quality mode K factor = 1 / 2
-
enumerator kPDM_QualityModeMediumKFactor
medium/very low0 quality mode K factor = 2 / 2
-
enumerator kPDM_QualityModeLowKFactor
low/very low1 quality mode K factor = 4 / 2
-
enumerator kPDM_QualityModeVeryLow2KFactor
very low2 quality mode K factor = 8 / 2
-
enumerator kPDM_QualityModeHighKFactor
-
enum _pdm_df_output_gain
PDM decimation filter output gain.
Values:
-
enumerator kPDM_DfOutputGain0
Decimation filter output gain 0
-
enumerator kPDM_DfOutputGain1
Decimation filter output gain 1
-
enumerator kPDM_DfOutputGain2
Decimation filter output gain 2
-
enumerator kPDM_DfOutputGain3
Decimation filter output gain 3
-
enumerator kPDM_DfOutputGain4
Decimation filter output gain 4
-
enumerator kPDM_DfOutputGain5
Decimation filter output gain 5
-
enumerator kPDM_DfOutputGain6
Decimation filter output gain 6
-
enumerator kPDM_DfOutputGain7
Decimation filter output gain 7
-
enumerator kPDM_DfOutputGain8
Decimation filter output gain 8
-
enumerator kPDM_DfOutputGain9
Decimation filter output gain 9
-
enumerator kPDM_DfOutputGain10
Decimation filter output gain 10
-
enumerator kPDM_DfOutputGain11
Decimation filter output gain 11
-
enumerator kPDM_DfOutputGain12
Decimation filter output gain 12
-
enumerator kPDM_DfOutputGain13
Decimation filter output gain 13
-
enumerator kPDM_DfOutputGain14
Decimation filter output gain 14
-
enumerator kPDM_DfOutputGain15
Decimation filter output gain 15
-
enumerator kPDM_DfOutputGain0
-
enum _pdm_data_width
PDM data width.
Values:
-
enumerator kPDM_DataWwidth24
PDM data width 24bit
-
enumerator kPDM_DataWwidth32
PDM data width 32bit
-
enumerator kPDM_DataWwidth24
-
enum _pdm_hwvad_interrupt_enable
PDM voice activity detector interrupt type.
Values:
-
enumerator kPDM_HwvadErrorInterruptEnable
PDM channel HWVAD error interrupt enable.
-
enumerator kPDM_HwvadInterruptEnable
PDM channel HWVAD interrupt
-
enumerator kPDM_HwvadErrorInterruptEnable
-
enum _pdm_hwvad_int_status
The PDM hwvad interrupt status flag.
Values:
-
enumerator kPDM_HwvadStatusInputSaturation
HWVAD saturation condition
-
enumerator kPDM_HwvadStatusVoiceDetectFlag
HWVAD voice detect interrupt triggered
-
enumerator kPDM_HwvadStatusInputSaturation
-
enum _pdm_hwvad_hpf_config
High pass filter configure cut-off frequency.
Values:
-
enumerator kPDM_HwvadHpfBypassed
High-pass filter bypass
-
enumerator kPDM_HwvadHpfCutOffFreq1750Hz
High-pass filter cut off frequency 1750HZ
-
enumerator kPDM_HwvadHpfCutOffFreq215Hz
High-pass filter cut off frequency 215HZ
-
enumerator kPDM_HwvadHpfCutOffFreq102Hz
High-pass filter cut off frequency 102HZ
-
enumerator kPDM_HwvadHpfBypassed
-
enum _pdm_hwvad_filter_status
HWVAD internal filter status.
Values:
-
enumerator kPDM_HwvadInternalFilterNormalOperation
internal filter ready for normal operation
-
enumerator kPDM_HwvadInternalFilterInitial
interla filter are initial
-
enumerator kPDM_HwvadInternalFilterNormalOperation
-
enum _pdm_hwvad_zcd_result
PDM voice activity detector zero cross detector result.
Values:
-
enumerator kPDM_HwvadResultOREnergyBasedDetection
zero cross detector result will be OR with energy based detection
-
enumerator kPDM_HwvadResultANDEnergyBasedDetection
zero cross detector result will be AND with energy based detection
-
enumerator kPDM_HwvadResultOREnergyBasedDetection
-
typedef enum _pdm_dc_remover pdm_dc_remover_t
PDM DC remover configurations.
-
typedef enum _pdm_df_quality_mode pdm_df_quality_mode_t
PDM decimation filter quality mode.
-
typedef enum _pdm_df_output_gain pdm_df_output_gain_t
PDM decimation filter output gain.
-
typedef struct _pdm_channel_config pdm_channel_config_t
PDM channel configurations.
-
typedef struct _pdm_config pdm_config_t
PDM user configuration structure.
-
typedef enum _pdm_hwvad_hpf_config pdm_hwvad_hpf_config_t
High pass filter configure cut-off frequency.
-
typedef enum _pdm_hwvad_filter_status pdm_hwvad_filter_status_t
HWVAD internal filter status.
-
typedef struct _pdm_hwvad_config pdm_hwvad_config_t
PDM voice activity detector user configuration structure.
-
typedef struct _pdm_hwvad_noise_filter pdm_hwvad_noise_filter_t
PDM voice activity detector noise filter user configuration structure.
-
typedef enum _pdm_hwvad_zcd_result pdm_hwvad_zcd_result_t
PDM voice activity detector zero cross detector result.
-
typedef struct _pdm_hwvad_zero_cross_detector pdm_hwvad_zero_cross_detector_t
PDM voice activity detector zero cross detector configuration structure.
-
typedef struct _pdm_transfer pdm_transfer_t
PDM SDMA transfer structure.
-
typedef struct _pdm_handle pdm_handle_t
PDM handle.
-
typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData)
PDM transfer callback prototype.
-
typedef void (*pdm_hwvad_callback_t)(status_t status, void *userData)
PDM HWVAD callback prototype.
-
typedef struct _pdm_hwvad_notification pdm_hwvad_notification_t
PDM HWVAD notification structure.
-
PDM_XFER_QUEUE_SIZE
PDM XFER QUEUE SIZE.
-
struct _pdm_channel_config
- #include <fsl_pdm.h>
PDM channel configurations.
Public Members
-
pdm_dc_remover_t outputCutOffFreq
PDM output DC remover cut off frequency
-
pdm_df_output_gain_t gain
Decimation Filter Output Gain
-
pdm_dc_remover_t outputCutOffFreq
-
struct _pdm_config
- #include <fsl_pdm.h>
PDM user configuration structure.
Public Members
-
bool enableDoze
This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted
-
bool enableFilterBypass
Switchable bypass path for the decimation filter
-
uint8_t fifoWatermark
Watermark value for FIFO
-
pdm_df_quality_mode_t qualityMode
Quality mode
-
uint8_t cicOverSampleRate
CIC filter over sampling rate
-
bool enableDoze
-
struct _pdm_hwvad_config
- #include <fsl_pdm.h>
PDM voice activity detector user configuration structure.
Public Members
-
uint8_t channel
Which channel uses voice activity detector
-
uint8_t initializeTime
Number of frames or samples to initialize voice activity detector.
-
uint8_t cicOverSampleRate
CIC filter over sampling rate
-
uint8_t inputGain
Voice activity detector input gain
-
uint32_t frameTime
Voice activity frame time
-
pdm_hwvad_hpf_config_t cutOffFreq
High pass filter cut off frequency
-
bool enableFrameEnergy
If frame energy enabled, true means enable
-
bool enablePreFilter
If pre-filter enabled
-
uint8_t channel
-
struct _pdm_hwvad_noise_filter
- #include <fsl_pdm.h>
PDM voice activity detector noise filter user configuration structure.
Public Members
-
bool enableAutoNoiseFilter
If noise fileter automatically activated, true means enable
-
bool enableNoiseMin
If Noise minimum block enabled, true means enabled
-
bool enableNoiseDecimation
If enable noise input decimation
-
bool enableNoiseDetectOR
Enables a OR logic in the output of minimum noise estimator block
-
uint32_t noiseFilterAdjustment
The adjustment value of the noise filter
-
uint32_t noiseGain
Gain value for the noise energy or envelope estimated
-
bool enableAutoNoiseFilter
-
struct _pdm_hwvad_zero_cross_detector
- #include <fsl_pdm.h>
PDM voice activity detector zero cross detector configuration structure.
Public Members
-
bool enableAutoThreshold
If ZCD auto-threshold enabled, true means enabled.
-
pdm_hwvad_zcd_result_t zcdAnd
Is ZCD result is AND’ed with energy-based detection, false means OR’ed
-
uint32_t threshold
The adjustment value of the noise filter
-
uint32_t adjustmentThreshold
Gain value for the noise energy or envelope estimated
-
bool enableAutoThreshold
-
struct _pdm_transfer
- #include <fsl_pdm.h>
PDM SDMA transfer structure.
Public Members
-
volatile uint8_t *data
Data start address to transfer.
-
volatile size_t dataSize
Total Transfer bytes size.
-
volatile uint8_t *data
-
struct _pdm_hwvad_notification
- #include <fsl_pdm.h>
PDM HWVAD notification structure.
-
struct _pdm_handle
- #include <fsl_pdm.h>
PDM handle structure.
Public Members
-
uint32_t state
Transfer status
-
pdm_transfer_callback_t callback
Callback function called at transfer event
-
void *userData
Callback parameter passed to callback function
-
pdm_transfer_t pdmQueue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint32_t format
data format
-
uint8_t watermark
Watermark value
-
uint8_t startChannel
end channel
-
uint8_t channelNums
Enabled channel number
-
uint32_t state
PDM EDMA Driver
-
void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum)
Install EDMA descriptor memory.
- Parameters:
handle – Pointer to EDMA channel transfer handle.
tcdAddr – EDMA head descriptor address.
tcdNum – EDMA link descriptor address.
-
void PDM_TransferCreateHandleEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)
Initializes the PDM Rx eDMA handle.
This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. Usually, for a specified PDM instance, call this API once to get the initialized handle.
- Parameters:
base – PDM base pointer.
handle – PDM eDMA handle pointer.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
dmaHandle – eDMA handle pointer, this handle shall be static allocated by users.
-
void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, pdm_edma_multi_channel_interleave_t multiChannelInterleaveType)
Initializes the multi PDM channel interleave type.
This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is kPDM_EDMAMultiChannelInterleavePerChannelSample always
- Parameters:
handle – PDM eDMA handle pointer.
multiChannelInterleaveType – Multi channel interleave type.
-
void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, pdm_edma_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config)
Configures the PDM channel.
- Parameters:
base – PDM base pointer.
handle – PDM eDMA handle pointer.
channel – channel index.
config – pdm channel configurations.
-
status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer)
Performs a non-blocking PDM receive using eDMA.
Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally.
Scatter gather case: This functio support dynamic scatter gather and staic scatter gather, a. for the dynamic scatter gather case: Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit before the previous one finish. b. for the static scatter gather case: Application should use the link transfer feature and make sure a loop link transfer is provided, such as:
pdm_edma_transfer_t pdmXfer[2] = { { .data = s_buffer, .dataSize = BUFFER_SIZE, .linkTransfer = &pdmXfer[1], }, { .data = &s_buffer[BUFFER_SIZE], .dataSize = BUFFER_SIZE, .linkTransfer = &pdmXfer[0] }, };
Multi channel case: This function support receive multi pdm channel data, for example, if two channel is requested,
The output data will be formatted as below if handle->interleaveType =PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig); PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig); PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer);
Note
This interface returns immediately after the transfer initiates. Call the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished.
-
void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)
Terminate all PDM receive.
This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the current transfer slot, please call PDM_TransferAbortReceiveEDMA.
- Parameters:
base – PDM base pointer.
handle – PDM eDMA handle pointer.
-
void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)
Aborts a PDM receive using eDMA.
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA.
- Parameters:
base – PDM base pointer
handle – PDM eDMA handle pointer.
-
status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count)
Gets byte count received by PDM.
- Parameters:
base – PDM base pointer
handle – PDM eDMA handle pointer.
count – Bytes count received by PDM.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.
-
FSL_PDM_EDMA_DRIVER_VERSION
Version 2.6.3
-
enum _pdm_edma_multi_channel_interleave
pdm multi channel interleave type
Values:
-
enumerator kPDM_EDMAMultiChannelInterleavePerChannelSample
-
enumerator kPDM_EDMAMultiChannelInterleavePerChannelBlock
-
enumerator kPDM_EDMAMultiChannelInterleavePerChannelSample
-
typedef struct _pdm_edma_handle pdm_edma_handle_t
PDM edma handler.
-
typedef enum _pdm_edma_multi_channel_interleave pdm_edma_multi_channel_interleave_t
pdm multi channel interleave type
-
typedef struct _pdm_edma_transfer pdm_edma_transfer_t
PDM edma transfer.
-
typedef void (*pdm_edma_callback_t)(PDM_Type *base, pdm_edma_handle_t *handle, status_t status, void *userData)
PDM eDMA transfer callback function for finish and error.
-
MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL
the PDM enable position When calling PDM_TransferReceiveEDMA
-
struct _pdm_edma_transfer
- #include <fsl_pdm_edma.h>
PDM edma transfer.
Public Members
-
volatile uint8_t *data
Data start address to transfer.
-
volatile size_t dataSize
Total Transfer bytes size.
-
struct _pdm_edma_transfer *linkTransfer
linked transfer configurations
-
volatile uint8_t *data
-
struct _pdm_edma_handle
- #include <fsl_pdm_edma.h>
PDM DMA transfer handle, users should not touch the content of the handle.
Public Members
-
edma_handle_t *dmaHandle
DMA handler for PDM send
-
uint8_t count
The transfer data count in a DMA request
-
uint32_t receivedBytes
total transfer count
-
uint32_t state
Internal state for PDM eDMA transfer
-
pdm_edma_callback_t callback
Callback for users while transfer finish or error occurs
-
bool isLoopTransfer
loop transfer
-
void *userData
User callback parameter
-
edma_tcd_t *tcd
TCD pool for eDMA transfer.
-
uint32_t tcdNum
TCD number
-
uint32_t tcdUser
Index for user to queue transfer.
-
uint32_t tcdDriver
Index for driver to get the transfer data and size
-
volatile uint32_t tcdUsedNum
Index for user to queue transfer.
-
pdm_edma_multi_channel_interleave_t interleaveType
multi channel transfer interleave type
-
uint8_t endChannel
The last enabled channel
-
uint8_t channelNums
total channel numbers
-
edma_handle_t *dmaHandle
PMU Driver
-
void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)
brief Selects the control mode of the PLL LDO.
param base PMU peripheral base address. param mode The control mode of the PLL LDO. Please refer to pmu_control_mode_t.
-
void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base)
Enables PLL LDO via AI interface in Static/Software mode.
- Parameters:
base – PMU peripheral base address.
-
void PMU_StaticDisablePllLdo(void)
Disables PLL LDO via AI interface in Static/Software mode.
-
void PMU_StaticGetAonAnaLdoDefaultConfig(pmu_static_aon_ana_ldo_config_t *config)
Fill the AON ANA LDO configuration structure with default settings.
The default values are:
config->mode = kPMU_HighPowerMode; config->enable2mALoad = true; config->enable20uALoad = false; config->enable4mALoad = true; config->enableStandbyMode = false; config->driverStrength = kPMU_AonAnaLdoDriverStrength0; config->brownOutDetectorConfig = kPMU_AonAnaLdoBrownOutDetectorDisable; config->chargePumpCurrent = kPMU_AonAnaChargePump300nA; config->outputRange = kPMU_AonAnaLdoOutputFrom1P77To1P83;
- Parameters:
config – Pointer to the structure pmu_static_aon_ana_ldo_config_t.
-
void PMU_StaticAonAnaLdoInit(ANADIG_LDO_BBSM_Type *base, const pmu_static_aon_ana_ldo_config_t *config)
Initialize the AON ANA LDO in Static/Sofware Mode.
- Parameters:
base – ANADIG_LDO_BBSM peripheral base address.
config – Pointer to the structure pmu_static_aon_ana_ldo_config_t.
-
void PMU_StaticAonAnaLdoDeinit(ANADIG_LDO_BBSM_Type *base)
Disable the output of AON ANA LDO.
- Parameters:
base – ANADIG_LDO_BBSM peripheral base address.
-
void PMU_StaticGetAonDigLdoDefaultConfig(pmu_static_aon_dig_config_t *config)
Gets the default configuration of AON DIG LDO.
The default values are:
config->enableStableDetect = false; config->voltageStepTime = kPMU_AonDigVoltageStepInc50us; config->brownOutConfig = kPMU_AonDigBrownOutDisable; config->targetVoltage = kPMU_AonDigTargetStableVoltage1P0V; config->mode = kPMU_HighPowerMode;
- Parameters:
config – Pointer to the structure pmu_static_aon_dig_config_t.
-
void PMU_StaticAonDigLdoInit(ANADIG_LDO_BBSM_Type *base, const pmu_static_aon_dig_config_t *config)
Initialize the AON DIG LDO in static mode.
- Parameters:
base – ANADIG_LDO_BBSM peripheral base address.
config – Pointer to the structure pmu_static_aon_dig_config_t.
-
void PMU_StaticAonDigLdoDeinit(ANADIG_LDO_BBSM_Type *base)
Disable the AON DIG LDO.
- Parameters:
base – ANADIG_LDO_BBSM peripheral base address.
-
void PMU_GetBbsmDigLdoDefaultConfig(pmu_bbsm_dig_config_t *config)
Gets the default config of the BBSM DIG LDO.
The default values are:
config->mode = kPMU_LowPowerMode; config->chargePumpCurrent = kPMU_BbsmDigChargePump12P5nA; config->dischargeResistorValue = kPMU_BbsmDigDischargeResistor15K; config->trimValue = 0U; config->enablePullDown = true; config->enableLdoStable = false;
- Parameters:
config – Pointer to pmu_bbsm_dig_config_t.
-
void PMU_EnableLdoStandbyMode(pmu_ldo_name_t name, bool enable)
brief When STBY assert, enable/disable the selected LDO enter it’s Low power mode.
param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. param enable Enable GPC standby mode or not.
-
void PMU_DisableBandgapSelfBiasAfterPowerUp(void)
Disables Bandgap self bias for best noise performance.
This function should be invoked after powering up. This function will wait for the bandgap stable and disable the bandgap self bias. After powering up, it need to wait for the bandgap to get stable and then disable Bandgap Self bias for best noise performance.
-
void PMU_EnableBandgapSelfBiasBeforePowerDown(void)
Enables Bandgap self bias before power down.
This function will enable Bandgap self bias feature before powering down or there will be risk of Bandgap not starting properly.
-
void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config)
Initialize Bandgap.
- Parameters:
config – Pointer to the structure pmu_static_bandgap_config_t.
-
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config)
Configures Well bias, such as power source, clock source and so on.
- Parameters:
base – PMU peripheral base address.
config – Pointer to the pmu_well_bias_config_t structure.
-
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config)
Gets the default configuration of well bias.
- Parameters:
config – The pointer to the pmu_well_bias_config_t structure.
-
void PMU_EnableFBB(ANADIG_PMU_Type *base, bool enable)
brief Enables/disables FBB.
param base PMU peripheral base address. param enable Used to turn on/off FBB.
-
void PMU_EnableFBBStandbyMode(ANADIG_PMU_Type *base, bool enable)
brief Controls the ON/OFF of FBB when GPC send standby request.
param base PMU peripheral base address. param enable Enable GPC standby mode or not.
-
FSL_PMU_DRIVER_VERSION
PMU driver version.
Version 2.1.2.
-
enum _pmu_ldo_name
The name of LDOs.
Values:
-
enumerator kPMU_PllLdo
The PLL LDO in SOC domain.
-
enumerator kPMU_AonAnaLdo
The AON ANA LDO in AON domain.
-
enumerator kPMU_AonDigLdo
The AON DIG LDO in AON domain.
-
enumerator kPMU_PllLdo
-
enum _pmu_control_mode
The control mode of LDOs/Bandgaps/Body Bias.
Values:
-
enumerator kPMU_StaticMode
Static/Software Control mode.
-
enumerator kPMU_GPCMode
GPC/Hardware Control mode.
-
enumerator kPMU_StaticMode
-
enum _pmu_ldo_operate_mode
The operation mode for the LDOs.
Values:
-
enumerator kPMU_LowPowerMode
LDOs operate in Low power mode.
-
enumerator kPMU_HighPowerMode
LDOs operate in High power mode.
-
enumerator kPMU_LowPowerMode
-
enum _pmu_aon_ana_ldo_charge_pump_current
The enumeration of AON ANA LDO’s charge pump current.
Values:
-
enumerator kPMU_AonAnaChargePump300nA
The current of the charge pump is selected as 300nA.
-
enumerator kPMU_AonAnaChargePump400nA
The current of the charge pump is selected as 400nA.
-
enumerator kPMU_AonAnaChargePump500nA
The current of the charge pump is selected as 500nA.
-
enumerator kPMU_AonAnaChargePump600nA
The current of the charge pump is selected as 600nA.
-
enumerator kPMU_AonAnaChargePump300nA
-
enum _pmu_aon_ana_ldo_output_range
The enumeration of AON ANA LDO’s output range.
Values:
-
enumerator kPMU_AonAnaLdoOutputFrom1P77To1P83
The output voltage varies from 1.77V to 1.83V.
-
enumerator kPMU_AonAnaLdoOutputFrom1P72To1P77
The output voltage varies from 1.72V to 1.77V.
-
enumerator kPMU_AonAnaLdoOutputFrom1P82To1P88
The output voltage varies from 1.82V to 1.88V.
-
enumerator kPMU_AonAnaLdoOutputFrom1P77To1P83
-
enum _pmu_aon_dig_voltage_step_time
The enumeration of voltage step time for AON DIG LDO.
Values:
-
enumerator kPMU_AonDigVoltageStepInc15us
AON DIG LDO voltage step time selected as 15us.
-
enumerator kPMU_AonDigVoltageStepInc25us
AON DIG LDO voltage step time selected as 25us.
-
enumerator kPMU_AonDigVoltageStepInc50us
AON DIG LDO voltage step time selected as 50us.
-
enumerator kPMU_AonDigVoltageStepInc100us
AON DIG LDO voltage step time selected as 100us.
-
enumerator kPMU_AonDigVoltageStepInc15us
-
enum _pmu_aon_dig_target_output_voltage
The target output voltage of AON DIG LDO.
Values:
-
enumerator kPMU_AonDigTargetStableVoltage0P631V
The target voltage selected as 0.631V
-
enumerator kPMU_AonDigTargetStableVoltage0P65V
The target voltage selected as 0.65V
-
enumerator kPMU_AonDigTargetStableVoltage0P67V
The target voltage selected as 0.67V
-
enumerator kPMU_AonDigTargetStableVoltage0P689V
The target voltage selected as 0.689V
-
enumerator kPMU_AonDigTargetStableVoltage0P709V
The target voltage selected as 0.709V
-
enumerator kPMU_AonDigTargetStableVoltage0P728V
The target voltage selected as 0.728V
-
enumerator kPMU_AonDigTargetStableVoltage0P748V
The target voltage selected as 0.748V
-
enumerator kPMU_AonDigTargetStableVoltage0P767V
The target voltage selected as 0.767V
-
enumerator kPMU_AonDigTargetStableVoltage0P786V
The target voltage selected as 0.786V
-
enumerator kPMU_AonDigTargetStableVoltage0P806V
The target voltage selected as 0.806V
-
enumerator kPMU_AonDigTargetStableVoltage0P825V
The target voltage selected as 0.825V
-
enumerator kPMU_AonDigTargetStableVoltage0P845V
The target voltage selected as 0.845V
-
enumerator kPMU_AonDigTargetStableVoltage0P864V
The target voltage selected as 0.864V
-
enumerator kPMU_AonDigTargetStableVoltage0P883V
The target voltage selected as 0.883V
-
enumerator kPMU_AonDigTargetStableVoltage0P903V
The target voltage selected as 0.903V
-
enumerator kPMU_AonDigTargetStableVoltage0P922V
The target voltage selected as 0.922V
-
enumerator kPMU_AonDigTargetStableVoltage0P942V
The target voltage selected as 0.942V
-
enumerator kPMU_AonDigTargetStableVoltage0P961V
The target voltage selected as 0.961V
-
enumerator kPMU_AonDigTargetStableVoltage0P981V
The target voltage selected as 0.981V
-
enumerator kPMU_AonDigTargetStableVoltage1P0V
The target voltage selected as 1.0V
-
enumerator kPMU_AonDigTargetStableVoltage1P019V
The target voltage selected as 1.019V
-
enumerator kPMU_AonDigTargetStableVoltage1P039V
The target voltage selected as 1.039V
-
enumerator kPMU_AonDigTargetStableVoltage1P058V
The target voltage selected as 1.058V
-
enumerator kPMU_AonDigTargetStableVoltage1P078V
The target voltage selected as 1.078V
-
enumerator kPMU_AonDigTargetStableVoltage1P097V
The target voltage selected as 1.097V
-
enumerator kPMU_AonDigTargetStableVoltage1P117V
The target voltage selected as 1.117V
-
enumerator kPMU_AonDigTargetStableVoltage1P136V
The target voltage selected as 1.136V
-
enumerator kPMU_AonDigTargetStableVoltage1P155V
The target voltage selected as 1.155V
-
enumerator kPMU_AonDigTargetStableVoltage1P175V
The target voltage selected as 1.175V
-
enumerator kPMU_AonDigTargetStableVoltage1P194V
The target voltage selected as 1.194V
-
enumerator kPMU_AonDigTargetStableVoltage1P214V
The target voltage selected as 1.214V
-
enumerator kPMU_AonDigTargetStableVoltage1P233V
The target voltage selected as 1.233V
-
enumerator kPMU_AonDigTargetStableVoltage0P631V
-
enum _pmu_bbsm_dig_charge_pump_current
The enumeration of the BBSM DIG LDO’s charge pump current.
Values:
-
enumerator kPMU_BbsmDigChargePump12P5nA
The current of BBSM DIG LDO’s charge pump is selected as 12.5nA.
-
enumerator kPMU_BbsmDigChargePump6P25nA
The current of BBSM DIG LDO’s charge pump is selected as 6.25nA.
-
enumerator kPMU_BbsmDigChargePump18P75nA
The current of BBSM DIG LDO’s charge pump is selected as 18.75nA.
-
enumerator kPMU_BbsmDigChargePump12P5nA
-
enum _pmu_bbsm_dig_discharge_resistor_value
The enumeration of the BBSM DIG LDO’s discharge resistor.
Values:
-
enumerator kPMU_BbsmDigDischargeResistor15K
The Discharge Resistor is selected as 15K ohm
-
enumerator kPMU_BbsmDigDischargeResistor30K
The Discharge Resistor is selected as 30K ohm
-
enumerator kPMU_BbsmDigDischargeResistor9K
The Discharge Resistor is selected as 9K ohm
-
enumerator kPMU_BbsmDigDischargeResistor15K
-
enum _pmu_static_bandgap_power_down_option
The enumeration of bandgap power down option.
Values:
-
enumerator kPMU_PowerDownBandgapFully
Fully power down the bandgap module.
-
enumerator kPMU_PowerDownVoltageReferenceOutputOnly
Power down only the reference output section of the bandgap
-
enumerator kPMU_PowerDownBandgapVBGUPDetector
Power down the VBGUP detector of the bandgap without affecting any additional functionality.
-
enumerator kPMU_PowerDownBandgapFully
-
enum _pmu_bandgap_output_VBG_voltage_value
The enumeration of output VBG voltage.
Values:
-
enumerator kPMU_BandgapOutputVBGVoltageNominal
Output nominal voltage.
-
enumerator kPMU_BandgapOutputVBGVoltagePlus10mV
Output VBG voltage Plus 10mV.
-
enumerator kPMU_BandgapOutputVBGVoltagePlus20mV
Output VBG voltage Plus 20mV.
-
enumerator kPMU_BandgapOutputVBGVoltagePlus30mV
Output VBG voltage Plus 30mV.
-
enumerator kPMU_BandgapOutputVBGVoltageMinus10mV
Output VBG voltage Minus 10mV.
-
enumerator kPMU_BandgapOutputVBGVoltageMinus20mV
Output VBG voltage Minus 20mV.
-
enumerator kPMU_BandgapOutputVBGVoltageMinus30mV
Output VBG voltage Minus 30mV.
-
enumerator kPMU_BandgapOutputVBGVoltageMinus40mV
Output VBG voltage Minus 40mV.
-
enumerator kPMU_BandgapOutputVBGVoltageNominal
-
enum _pmu_bandgap_output_current_value
The enumeration of output current.
Values:
-
enumerator kPMU_OutputCurrent11P5uA
Output 11.5uA current from the bandgap.
-
enumerator kPMU_OutputCurrent11P8uA
Output 11.8uA current from the bandgap.
-
enumerator kPMU_OutputCurrent12P1uA
Output 12.1uA current from the bandgap.
-
enumerator kPMU_OutputCurrent12P4uA
Output 12.4uA current from the bandgap.
-
enumerator kPMU_OutputCurrent12P7uA
Output 12.7uA current from the bandgap.
-
enumerator kPMU_OutputCurrent13P0uA
Output 13.0uA current from the bandgap.
-
enumerator kPMU_OutputCurrent13P3uA
Output 13.3uA current from the bandgap.
-
enumerator kPMU_OutputCurrent11P5uA
-
enum _pmu_well_bias_power_source
The enumerator of well bias power source.
Values:
-
enumerator kPMU_WellBiasPowerFromAonDigLdo
AON Dig LDO supplies the power stage and NWELL sampler.
-
enumerator kPMU_WellBiasPowerFromDCDC
DCDC supplies the power stage and NWELL sampler.
-
enumerator kPMU_WellBiasPowerFromAonDigLdo
-
enum _pmu_bias_area_size
The enumerator of bias area size.
Values:
-
enumerator kPMU_180uA_6mm2At125C
Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C
-
enumerator kPMU_150uA_5mm2At125C
Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C
-
enumerator kPMU_120uA_4mm2At125C
Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C
-
enumerator kPMU_90uA_3mm2At125C
Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C
-
enumerator kPMU_60uA_2mm2At125C
Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C
-
enumerator kPMU_45uA_1P5mm2At125C
Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C
-
enumerator kPMU_30uA_1mm2At125C
Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C
-
enumerator kPMU_15uA_0P5mm2At125C
Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C
-
enumerator kPMU_180uA_6mm2At125C
-
enum _pmu_well_bias_typical_freq
The enumerator of well bias typical frequency.
Values:
-
enumerator kPMU_OscFreqDiv128
Typical frequency = osc_freq / 128.
-
enumerator kPMU_OscFreqDiv64
Typical frequency = osc_freq / 64.
-
enumerator kPMU_OscFreqDiv32
Typical frequency = osc_freq / 32.
-
enumerator kPMU_OscFreqDiv16
Typical frequency = osc_freq / 16.
-
enumerator kPMU_OscFreqDiv8
Typical frequency = osc_freq / 8.
-
enumerator kPMU_OscFreqDiv2
Typical frequency = osc_freq / 2.
-
enumerator kPMU_OscFreq
Typical frequency = oscillator frequency.
-
enumerator kPMU_OscFreqDiv128
-
enum _pmu_adaptive_clock_source
The enumerator of well bias adaptive clock source.
Values:
-
enumerator kPMU_AdaptiveClkSourceOscClk
The adaptive clock source is oscillator clock.
-
enumerator kPMU_AdaptiveClkSourceChargePumpClk
The adaptive clock source is charge pump clock.
-
enumerator kPMU_AdaptiveClkSourceOscClk
-
enum _pmu_freq_reduction
The enumerator of frequency reduction due to cap increment.
Values:
-
enumerator kPMU_FreqReductionNone
No frequency reduction.
-
enumerator kPMU_FreqReduction30PCT
30% frequency reduction due to cap increment.
-
enumerator kPMU_FreqReduction40PCT
40% frequency reduction due to cap increment.
-
enumerator kPMU_FreqReduction50PCT
50% frequency reduction due to cap increment.
-
enumerator kPMU_FreqReductionNone
-
enum _pmu_well_bias_1P8_adjustment
The enumerator of well bias 1P8 adjustment.
Values:
-
enumerator kPMU_Cref0fFCspl0fFDeltaC0fF
Cref = 0fF, Cspl = 0fF, DeltaC = 0fF.
-
enumerator kPMU_Cref0fFCspl30fFDeltaCN30fF
Cref = 0fF, Cspl = 30fF, DeltaC = -30fF.
-
enumerator kPMU_Cref0fFCspl43fFDeltaCN43fF
Cref = 0fF, Cspl = 43fF, DeltaC = -43fF.
-
enumerator kPMU_Cref0fFCspl62fFDeltaCN62fF
Cref = 0fF, Cspl = 62fF, DeltaC = -62fF.
-
enumerator kPMU_Cref0fFCspl105fFDeltaCN105fF
Cref = 0fF, Cspl = 105fF, DeltaC = -105fF.
-
enumerator kPMU_Cref30fFCspl0fFDeltaC30fF
Cref = 30fF, Cspl = 0fF, DeltaC = 30fF.
-
enumerator kPMU_Cref30fFCspl43fFDeltaCN12fF
Cref = 30fF, Cspl = 43fF, DeltaC = -12fF.
-
enumerator kPMU_Cref30fFCspl105fFDeltaCN75fF
Cref = 30fF, Cspl = 105fF, DeltaC = -75fF.
-
enumerator kPMU_Cref43fFCspl0fFDeltaC43fF
Cref = 43fF, Cspl = 0fF, DeltaC = 43fF.
-
enumerator kPMU_Cref43fFCspl30fFDeltaC13fF
Cref = 43fF, Cspl = 30fF, DeltaC = 13fF.
-
enumerator kPMU_Cref43fFCspl62fFDeltaCN19fF
Cref = 43fF, Cspl = 62fF, DeltaC = -19fF.
-
enumerator kPMU_Cref62fFCspl0fFDeltaC62fF
Cref = 62fF, Cspl = 0fF, DeltaC = 62fF.
-
enumerator kPMU_Cref62fFCspl43fFDeltaC19fF
Cref = 62fF, Cspl = 43fF, DeltaC = 19fF.
-
enumerator kPMU_Cref105fFCspl0fFDeltaC105fF
Cref = 105fF, Cspl = 0fF, DeltaC = 105fF.
-
enumerator kPMU_Cref105fFCspl30fFDeltaC75fF
Cref = 105fF, Cspl = 30fF, DeltaC = 75fF.
-
enumerator kPMU_Cref0fFCspl0fFDeltaC0fF
-
typedef enum _pmu_ldo_name pmu_ldo_name_t
The name of LDOs.
-
typedef enum _pmu_control_mode pmu_control_mode_t
The control mode of LDOs/Bandgaps/Body Bias.
-
typedef enum _pmu_ldo_operate_mode pmu_ldo_operate_mode_t
The operation mode for the LDOs.
-
typedef enum _pmu_aon_ana_ldo_charge_pump_current pmu_aon_ana_ldo_charge_pump_current_t
The enumeration of AON ANA LDO’s charge pump current.
-
typedef enum _pmu_aon_ana_ldo_output_range pmu_aon_ana_ldo_output_range_t
The enumeration of AON ANA LDO’s output range.
-
typedef enum _pmu_aon_dig_voltage_step_time pmu_aon_dig_voltage_step_time_t
The enumeration of voltage step time for AON DIG LDO.
-
typedef enum _pmu_aon_dig_target_output_voltage pmu_aon_dig_target_output_voltage_t
The target output voltage of AON DIG LDO.
-
typedef enum _pmu_bbsm_dig_charge_pump_current pmu_bbsm_dig_charge_pump_current_t
The enumeration of the BBSM DIG LDO’s charge pump current.
-
typedef enum _pmu_bbsm_dig_discharge_resistor_value pmu_bbsm_dig_discharge_resistor_value_t
The enumeration of the BBSM DIG LDO’s discharge resistor.
-
typedef enum _pmu_bandgap_output_VBG_voltage_value pmu_bandgap_output_VBG_voltage_value_t
The enumeration of output VBG voltage.
-
typedef enum _pmu_bandgap_output_current_value pmu_bandgap_output_current_value_t
The enumeration of output current.
-
typedef enum _pmu_well_bias_power_source pmu_well_bias_power_source_t
The enumerator of well bias power source.
-
typedef enum _pmu_bias_area_size pmu_bias_area_size_t
The enumerator of bias area size.
-
typedef enum _pmu_well_bias_typical_freq pmu_well_bias_typical_freq_t
The enumerator of well bias typical frequency.
-
typedef enum _pmu_adaptive_clock_source pmu_adaptive_clock_source_t
The enumerator of well bias adaptive clock source.
-
typedef enum _pmu_freq_reduction pmu_freq_reduction_t
The enumerator of frequency reduction due to cap increment.
-
typedef enum _pmu_well_bias_1P8_adjustment pmu_well_bias_1P8_adjustment_t
The enumerator of well bias 1P8 adjustment.
-
typedef struct _pmu_static_aon_ana_ldo_config pmu_static_aon_ana_ldo_config_t
AON ANA LDO config.
-
typedef struct _pmu_static_aon_dig_config pmu_static_aon_dig_config_t
AON DIG LDO Config in Static/Software Mode.
-
typedef struct _pmu_bbsm_dig_config pmu_bbsm_dig_config_t
BBSM DIG LDO config.
-
typedef struct _pmu_static_bandgap_config pmu_static_bandgap_config_t
Bandgap config in static mode.
-
typedef union _pmu_well_bias_option pmu_well_bias_option_t
The union of well bias basic options, such as clock source, power source and so on.
-
typedef struct _pmu_well_bias_config pmu_well_bias_config_t
The structure of well bias configuration.
-
struct _pmu_static_aon_ana_ldo_config
- #include <fsl_pmu.h>
AON ANA LDO config.
Public Members
-
pmu_ldo_operate_mode_t mode
The operate mode of AON ANA LDO.
-
bool enable2mALoad
Enable/Disable 2mA load.
true Enables 2mA loading to prevent overshoot;
false Disables 2mA loading.
-
bool enable4mALoad
Enable/Disable 4mA load.
true Enables 4mA loading to prevent dramatic voltage drop;
false Disables 4mA load.
-
bool enable20uALoad
Enable/Disable 20uA load.
true Enables 20uA loading to prevent overshoot;
false Disables 20uA load.
-
bool enableStandbyMode
Enable/Disable Standby Mode.
true Enables Standby mode, if the STBY assert, the AON ANA LDO enter LP mode
false Disables Standby mode.
-
pmu_ldo_operate_mode_t mode
-
struct _pmu_static_aon_dig_config
- #include <fsl_pmu.h>
AON DIG LDO Config in Static/Software Mode.
Public Members
-
bool enableStableDetect
Enable/Disable Stable Detect.
true Enables Stable Detect.
false Disables Stable Detect.
-
pmu_aon_dig_voltage_step_time_t voltageStepTime
Step time.
-
pmu_aon_dig_target_output_voltage_t targetVoltage
The target output voltage.
-
bool enableStableDetect
-
struct _pmu_bbsm_dig_config
- #include <fsl_pmu.h>
BBSM DIG LDO config.
Public Members
-
pmu_ldo_operate_mode_t mode
The operate mode the BBSM DIG LDO.
-
pmu_bbsm_dig_charge_pump_current_t chargePumpCurrent
The current of BBSM DIG LDO’s charge pump current.
-
pmu_bbsm_dig_discharge_resistor_value_t dischargeResistorValue
The value of BBSM DIG LDO’s Discharge Resistor.
-
uint8_t trimValue
The trim value.
-
bool enablePullDown
Enable/Disable Pull down.
true Enables the feature of using 1M ohm resistor to discharge the LDO output.
false Disables the feature of using 1M ohm resistor to discharge the LDO output.
-
bool enableLdoStable
Enable/Disable BBSM DIG LDO Stable.
-
pmu_ldo_operate_mode_t mode
-
struct _pmu_static_bandgap_config
- #include <fsl_pmu.h>
Bandgap config in static mode.
Public Members
-
uint8_t powerDownOption
The OR’ed value of _pmu_static_bandgap_power_down_option. Please refer to _pmu_static_bandgap_power_down_option.
-
bool enableLowPowerMode
Turn on/off the Low power mode.
true Turns on the low power operation of the bandgap.
false Turns off the low power operation of the bandgap.
-
pmu_bandgap_output_VBG_voltage_value_t outputVoltage
The output VBG voltage of Bandgap.
-
pmu_bandgap_output_current_value_t outputCurrent
The output current from the bandgap to the temperature sensors.
-
uint8_t powerDownOption
-
union _pmu_well_bias_option
- #include <fsl_pmu.h>
The union of well bias basic options, such as clock source, power source and so on.
Public Members
-
uint16_t wellBiasData
well bias configuration data.
-
struct _pmu_well_bias_option wellBiasStruct
-
uint16_t wellBiasData
-
struct _pmu_well_bias_config
- #include <fsl_pmu.h>
The structure of well bias configuration.
Public Members
-
pmu_well_bias_option_t wellBiasOption
Well bias basic function, please refer to pmu_well_bias_option_t.
-
pmu_well_bias_1P8_adjustment_t adjustment
Well bias adjustment 1P8, please refer to pmu_well_bias_1P8_adjustment_t.
-
pmu_well_bias_option_t wellBiasOption
-
struct wellBiasStruct
Public Members
-
uint16_t enablePWellOnly
Turn on both PWELL and NWELL, or only trun on PWELL.
1b0 PWELL and NEWLL are both turned on.
1b1 PWELL is turned on only.
-
uint16_t reserved1
Reserved.
-
uint16_t biasAreaSize
Select size of bias area, please refer to pmu_bias_area_size_t
-
uint16_t disableAdaptiveFreq
Enable/Disable adaptive frequency.
1b0 Frequency change after each half cycle minimum frequency determined by typical frequency.
1b1 Adaptive frequency disabled. Frequency determined by typical frequency.
-
uint16_t wellBiasFreq
Set well bias typical frequency, please refer to pmu_well_bias_typical_freq_t.
-
uint16_t clkSource
Config the adaptive clock source, please pmu_adaptive_clock_source_t.
-
uint16_t freqReduction
Config the percent of frequency reduction due to cap increment, please refer to pmu_freq_reduction_t.
-
uint16_t enablePullDownOption
Enable/Disable pull down option.
false Pull down option is disabled.
true Pull down option is enabled.
-
uint16_t reserved2
Reserved.
-
uint16_t powerSource
Set power source, please refer to pmu_well_bias_power_source_t.
-
uint16_t reserved3
Reserved.
-
uint16_t enablePWellOnly
PWM: Pulse Width Modulator
-
status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)
Ungates the PWM submodule clock and configures the peripheral for basic operation.
This API should be called at the beginning of the application using the PWM driver. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. When output PWMX in center aligned mode, VAL1 register controls both PWM period and PWMX duty cycle, PWMA and PWMB output will be corrupted. But edge aligned PWMX output do not have such limit. In master reload counter initialization mode, PWM period is depended by period of set LDOK in submodule 0 because this operation will reload register. Submodule 0 counter initialization cannot be master sync or master reload.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
config – Pointer to user’s PWM config structure.
- Returns:
kStatus_Success means success; else failed.
-
void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)
Gate the PWM submodule clock.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to deinitialize
-
void PWM_GetDefaultConfig(pwm_config_t *config)
Fill in the PWM config struct with the default settings.
The default values are:
config->enableDebugMode = false; config->enableWait = false; config->reloadSelect = kPWM_LocalReload; config->clockSource = kPWM_BusClock; config->prescale = kPWM_Prescale_Divide_1; config->initializationControl = kPWM_Initialize_LocalSync; config->forceTrigger = kPWM_Force_Local; config->reloadFrequency = kPWM_LoadEveryOportunity; config->reloadLogic = kPWM_ReloadImmediate; config->pairOperation = kPWM_Independent;
- Parameters:
config – Pointer to user’s PWM config structure.
-
status_t PWM_SetupPwm(PWM_Type *base, pwm_submodule_t subModule, const pwm_signal_param_t *chnlParams, uint8_t numOfChnls, pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)
Sets up the PWM signals for a PWM submodule.
The function initializes the submodule according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. Due to edge aligned PWMX is negative true signal, need to configure PWMX active low true level to get correct duty cycle. The half cycle point will not be exactly in the middle of the PWM cycle when PWMX enabled.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
chnlParams – Array of PWM channel parameters to configure the channel(s).
numOfChnls – Number of channels to configure, this should be the size of the array passed in. Array size should not be more than 3 as each submodule has 3 pins to output PWM.
mode – PWM operation mode, options available in enumeration pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 prescaler value instead of submodule0 source clock.
- Returns:
Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise
-
status_t PWM_SetupPwmPhaseShift(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, uint8_t shiftvalue, bool doSync)
Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – PWM main counter clock in Hz.
shiftvalue – Phase shift value, range in 0 ~ 50
doSync – true: Set LDOK bit for the submodule list; false: LDOK bit don’t set, need to call PWM_SetPwmLdok to sync update.
- Returns:
Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise
-
void PWM_UpdatePwmDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint8_t dutyCyclePercent)
Updates the PWM signal’s dutycycle.
The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A, PWM B, PWM X) to update
currPwmMode – The current PWM mode set during PWM setup
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)
-
void PWM_UpdatePwmDutycycleHighAccuracy(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle)
Updates the PWM signal’s dutycycle with 16-bit accuracy.
The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A, PWM B, PWM X) to update
currPwmMode – The current PWM mode set during PWM setup
dutyCycle – New PWM pulse width, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle)
-
void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t pulseCnt, uint16_t dutyCycle)
Update the PWM signal’s period and dutycycle for a PWM submodule.
The function updates PWM signal period generated by a specific submodule according to the parameters passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle or update new dutycycle. Call this function in local sync control mode because PWM period is depended by
INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. PWM signal will not be generated if its period is less than dead time duration.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A or PWM B) to update
currPwmMode – The current PWM mode set during PWM setup, options available in enumeration pwm_mode_t
pulseCnt – New PWM period, value should be between 0 to 65535 0=minimum PWM period… 65535=maximum PWM period
dutyCycle – New PWM pulse width of channel, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle) You can keep original duty cycle or update new duty cycle
-
static inline void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
Enables the selected PWM interrupts.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t
-
static inline void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
Disables the selected PWM interrupts.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t
-
static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)
Gets the enabled PWM interrupts.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t
-
static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, pwm_submodule_t subModule, pwm_watermark_control_t pwm_watermark_control)
Capture DMA Enable Source Select.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwm_watermark_control – PWM FIFO watermark and control
-
static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, pwm_submodule_t subModule, pwm_dma_source_select_t pwm_dma_source_select)
Capture DMA Enable Source Select.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwm_dma_source_select – PWM capture DMA enable source select
-
static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate)
Enables or disables the selected PWM DMA Capture read request.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The DMA to enable or disable. This is a logical OR of members of the enumeration pwm_dma_enable_t
activate – true: Enable DMA read request; false: Disable DMA read request
-
static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate)
Enables or disables the PWM DMA write request.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
activate – true: Enable DMA write request; false: Disable DMA write request
-
static inline uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)
Gets the PWM status flags.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
- Returns:
The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t
-
static inline void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
Clears the PWM status flags.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t
-
static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart)
Starts the PWM counter for a single or multiple submodules.
Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple submodules at the same time.
- Parameters:
base – PWM peripheral base address
subModulesToStart – PWM submodules to start. This is a logical OR of members of the enumeration pwm_module_control_t
-
static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop)
Stops the PWM counter for a single or multiple submodules.
Clears the Run bit which resets the submodule’s counter. This function can stop multiple submodules at the same time.
- Parameters:
base – PWM peripheral base address
subModulesToStop – PWM submodules to stop. This is a logical OR of members of the enumeration pwm_module_control_t
-
FSL_PWM_DRIVER_VERSION
Version 2.9.0
-
enum _pwm_submodule
List of PWM submodules.
Values:
-
enumerator kPWM_Module_0
Submodule 0
-
enumerator kPWM_Module_1
Submodule 1
-
enumerator kPWM_Module_2
Submodule 2
-
enumerator kPWM_Module_0
-
enum _pwm_channels
List of PWM channels in each module.
Values:
-
enumerator kPWM_PwmB
-
enumerator kPWM_PwmA
-
enumerator kPWM_PwmX
-
enumerator kPWM_PwmB
-
enum _pwm_value_register
List of PWM value registers.
Values:
-
enumerator kPWM_ValueRegister_0
PWM Value0 register
-
enumerator kPWM_ValueRegister_1
PWM Value1 register
-
enumerator kPWM_ValueRegister_2
PWM Value2 register
-
enumerator kPWM_ValueRegister_3
PWM Value3 register
-
enumerator kPWM_ValueRegister_4
PWM Value4 register
-
enumerator kPWM_ValueRegister_5
PWM Value5 register
-
enumerator kPWM_ValueRegister_0
-
enum _pwm_value_register_mask
List of PWM value registers mask.
Values:
-
enumerator kPWM_ValueRegisterMask_0
PWM Value0 register mask
-
enumerator kPWM_ValueRegisterMask_1
PWM Value1 register mask
-
enumerator kPWM_ValueRegisterMask_2
PWM Value2 register mask
-
enumerator kPWM_ValueRegisterMask_3
PWM Value3 register mask
-
enumerator kPWM_ValueRegisterMask_4
PWM Value4 register mask
-
enumerator kPWM_ValueRegisterMask_5
PWM Value5 register mask
-
enumerator kPWM_ValueRegisterMask_0
-
enum _pwm_clock_source
PWM clock source selection.
Values:
-
enumerator kPWM_BusClock
The IPBus clock is used as the clock
-
enumerator kPWM_ExternalClock
EXT_CLK is used as the clock
-
enumerator kPWM_Submodule0Clock
Clock of the submodule 0 (AUX_CLK) is used as the source clock
-
enumerator kPWM_BusClock
-
enum _pwm_clock_prescale
PWM prescaler factor selection for clock source.
Values:
-
enumerator kPWM_Prescale_Divide_1
PWM clock frequency = fclk/1
-
enumerator kPWM_Prescale_Divide_2
PWM clock frequency = fclk/2
-
enumerator kPWM_Prescale_Divide_4
PWM clock frequency = fclk/4
-
enumerator kPWM_Prescale_Divide_8
PWM clock frequency = fclk/8
-
enumerator kPWM_Prescale_Divide_16
PWM clock frequency = fclk/16
-
enumerator kPWM_Prescale_Divide_32
PWM clock frequency = fclk/32
-
enumerator kPWM_Prescale_Divide_64
PWM clock frequency = fclk/64
-
enumerator kPWM_Prescale_Divide_128
PWM clock frequency = fclk/128
-
enumerator kPWM_Prescale_Divide_1
-
enum _pwm_force_output_trigger
Options that can trigger a PWM FORCE_OUT.
Values:
-
enumerator kPWM_Force_Local
The local force signal, CTRL2[FORCE], from the submodule is used to force updates
-
enumerator kPWM_Force_Master
The master force signal from submodule 0 is used to force updates
-
enumerator kPWM_Force_LocalReload
The local reload signal from this submodule is used to force updates without regard to the state of LDOK
-
enumerator kPWM_Force_MasterReload
The master reload signal from submodule 0 is used to force updates if LDOK is set
-
enumerator kPWM_Force_LocalSync
The local sync signal from this submodule is used to force updates
-
enumerator kPWM_Force_MasterSync
The master sync signal from submodule0 is used to force updates
-
enumerator kPWM_Force_External
The external force signal, EXT_FORCE, from outside the PWM module causes updates
-
enumerator kPWM_Force_ExternalSync
The external sync signal, EXT_SYNC, from outside the PWM module causes updates
-
enumerator kPWM_Force_Local
-
enum _pwm_output_state
PWM channel output status.
Values:
-
enumerator kPWM_HighState
The output state of PWM channel is high
-
enumerator kPWM_LowState
The output state of PWM channel is low
-
enumerator kPWM_NormalState
The output state of PWM channel is normal
-
enumerator kPWM_InvertState
The output state of PWM channel is invert
-
enumerator kPWM_MaskState
The output state of PWM channel is mask
-
enumerator kPWM_HighState
-
enum _pwm_init_source
PWM counter initialization options.
Values:
-
enumerator kPWM_Initialize_LocalSync
Local sync causes initialization
-
enumerator kPWM_Initialize_MasterReload
Master reload from submodule 0 causes initialization
-
enumerator kPWM_Initialize_MasterSync
Master sync from submodule 0 causes initialization
-
enumerator kPWM_Initialize_ExtSync
EXT_SYNC causes initialization
-
enumerator kPWM_Initialize_LocalSync
-
enum _pwm_load_frequency
PWM load frequency selection.
Values:
-
enumerator kPWM_LoadEveryOportunity
Every PWM opportunity
-
enumerator kPWM_LoadEvery2Oportunity
Every 2 PWM opportunities
-
enumerator kPWM_LoadEvery3Oportunity
Every 3 PWM opportunities
-
enumerator kPWM_LoadEvery4Oportunity
Every 4 PWM opportunities
-
enumerator kPWM_LoadEvery5Oportunity
Every 5 PWM opportunities
-
enumerator kPWM_LoadEvery6Oportunity
Every 6 PWM opportunities
-
enumerator kPWM_LoadEvery7Oportunity
Every 7 PWM opportunities
-
enumerator kPWM_LoadEvery8Oportunity
Every 8 PWM opportunities
-
enumerator kPWM_LoadEvery9Oportunity
Every 9 PWM opportunities
-
enumerator kPWM_LoadEvery10Oportunity
Every 10 PWM opportunities
-
enumerator kPWM_LoadEvery11Oportunity
Every 11 PWM opportunities
-
enumerator kPWM_LoadEvery12Oportunity
Every 12 PWM opportunities
-
enumerator kPWM_LoadEvery13Oportunity
Every 13 PWM opportunities
-
enumerator kPWM_LoadEvery14Oportunity
Every 14 PWM opportunities
-
enumerator kPWM_LoadEvery15Oportunity
Every 15 PWM opportunities
-
enumerator kPWM_LoadEvery16Oportunity
Every 16 PWM opportunities
-
enumerator kPWM_LoadEveryOportunity
-
enum _pwm_fault_input
List of PWM fault selections.
Values:
-
enumerator kPWM_Fault_0
Fault 0 input pin
-
enumerator kPWM_Fault_1
Fault 1 input pin
-
enumerator kPWM_Fault_2
Fault 2 input pin
-
enumerator kPWM_Fault_3
Fault 3 input pin
-
enumerator kPWM_Fault_0
-
enum _pwm_fault_disable
List of PWM fault disable mapping selections.
Values:
-
enumerator kPWM_FaultDisable_0
Fault 0 disable mapping
-
enumerator kPWM_FaultDisable_1
Fault 1 disable mapping
-
enumerator kPWM_FaultDisable_2
Fault 2 disable mapping
-
enumerator kPWM_FaultDisable_3
Fault 3 disable mapping
-
enumerator kPWM_FaultDisable_0
-
enum _pwm_fault_channels
List of PWM fault channels.
Values:
-
enumerator kPWM_faultchannel_0
-
enumerator kPWM_faultchannel_1
-
enumerator kPWM_faultchannel_0
-
enum _pwm_input_capture_edge
PWM capture edge select.
Values:
-
enumerator kPWM_Disable
Disabled
-
enumerator kPWM_FallingEdge
Capture on falling edge only
-
enumerator kPWM_RisingEdge
Capture on rising edge only
-
enumerator kPWM_RiseAndFallEdge
Capture on rising or falling edge
-
enumerator kPWM_Disable
-
enum _pwm_force_signal
PWM output options when a FORCE_OUT signal is asserted.
Values:
-
enumerator kPWM_UsePwm
Generated PWM signal is used by the deadtime logic.
-
enumerator kPWM_InvertedPwm
Inverted PWM signal is used by the deadtime logic.
-
enumerator kPWM_SoftwareControl
Software controlled value is used by the deadtime logic.
-
enumerator kPWM_UseExternal
PWM_EXTA signal is used by the deadtime logic.
-
enumerator kPWM_UsePwm
-
enum _pwm_chnl_pair_operation
Options available for the PWM A & B pair operation.
Values:
-
enumerator kPWM_Independent
PWM A & PWM B operate as 2 independent channels
-
enumerator kPWM_ComplementaryPwmA
PWM A & PWM B are complementary channels, PWM A generates the signal
-
enumerator kPWM_ComplementaryPwmB
PWM A & PWM B are complementary channels, PWM B generates the signal
-
enumerator kPWM_Independent
-
enum _pwm_register_reload
Options available on how to load the buffered-registers with new values.
Values:
-
enumerator kPWM_ReloadImmediate
Buffered-registers get loaded with new values as soon as LDOK bit is set
-
enumerator kPWM_ReloadPwmHalfCycle
Registers loaded on a PWM half cycle
-
enumerator kPWM_ReloadPwmFullCycle
Registers loaded on a PWM full cycle
-
enumerator kPWM_ReloadPwmHalfAndFullCycle
Registers loaded on a PWM half & full cycle
-
enumerator kPWM_ReloadImmediate
-
enum _pwm_fault_recovery_mode
Options available on how to re-enable the PWM output when recovering from a fault.
Values:
-
enumerator kPWM_NoRecovery
PWM output will stay inactive
-
enumerator kPWM_RecoverHalfCycle
PWM output re-enabled at the first half cycle
-
enumerator kPWM_RecoverFullCycle
PWM output re-enabled at the first full cycle
-
enumerator kPWM_RecoverHalfAndFullCycle
PWM output re-enabled at the first half or full cycle
-
enumerator kPWM_NoRecovery
-
enum _pwm_interrupt_enable
List of PWM interrupt options.
Values:
-
enumerator kPWM_CompareVal0InterruptEnable
PWM VAL0 compare interrupt
-
enumerator kPWM_CompareVal1InterruptEnable
PWM VAL1 compare interrupt
-
enumerator kPWM_CompareVal2InterruptEnable
PWM VAL2 compare interrupt
-
enumerator kPWM_CompareVal3InterruptEnable
PWM VAL3 compare interrupt
-
enumerator kPWM_CompareVal4InterruptEnable
PWM VAL4 compare interrupt
-
enumerator kPWM_CompareVal5InterruptEnable
PWM VAL5 compare interrupt
-
enumerator kPWM_CaptureX0InterruptEnable
PWM capture X0 interrupt
-
enumerator kPWM_CaptureX1InterruptEnable
PWM capture X1 interrupt
-
enumerator kPWM_CaptureB0InterruptEnable
PWM capture B0 interrupt
-
enumerator kPWM_CaptureB1InterruptEnable
PWM capture B1 interrupt
-
enumerator kPWM_CaptureA0InterruptEnable
PWM capture A0 interrupt
-
enumerator kPWM_CaptureA1InterruptEnable
PWM capture A1 interrupt
-
enumerator kPWM_ReloadInterruptEnable
PWM reload interrupt
-
enumerator kPWM_ReloadErrorInterruptEnable
PWM reload error interrupt
-
enumerator kPWM_Fault0InterruptEnable
PWM fault 0 interrupt
-
enumerator kPWM_Fault1InterruptEnable
PWM fault 1 interrupt
-
enumerator kPWM_Fault2InterruptEnable
PWM fault 2 interrupt
-
enumerator kPWM_Fault3InterruptEnable
PWM fault 3 interrupt
-
enumerator kPWM_CompareVal0InterruptEnable
-
enum _pwm_status_flags
List of PWM status flags.
Values:
-
enumerator kPWM_CompareVal0Flag
PWM VAL0 compare flag
-
enumerator kPWM_CompareVal1Flag
PWM VAL1 compare flag
-
enumerator kPWM_CompareVal2Flag
PWM VAL2 compare flag
-
enumerator kPWM_CompareVal3Flag
PWM VAL3 compare flag
-
enumerator kPWM_CompareVal4Flag
PWM VAL4 compare flag
-
enumerator kPWM_CompareVal5Flag
PWM VAL5 compare flag
-
enumerator kPWM_CaptureX0Flag
PWM capture X0 flag
-
enumerator kPWM_CaptureX1Flag
PWM capture X1 flag
-
enumerator kPWM_CaptureB0Flag
PWM capture B0 flag
-
enumerator kPWM_CaptureB1Flag
PWM capture B1 flag
-
enumerator kPWM_CaptureA0Flag
PWM capture A0 flag
-
enumerator kPWM_CaptureA1Flag
PWM capture A1 flag
-
enumerator kPWM_ReloadFlag
PWM reload flag
-
enumerator kPWM_ReloadErrorFlag
PWM reload error flag
-
enumerator kPWM_RegUpdatedFlag
PWM registers updated flag
-
enumerator kPWM_Fault0Flag
PWM fault 0 flag
-
enumerator kPWM_Fault1Flag
PWM fault 1 flag
-
enumerator kPWM_Fault2Flag
PWM fault 2 flag
-
enumerator kPWM_Fault3Flag
PWM fault 3 flag
-
enumerator kPWM_CompareVal0Flag
-
enum _pwm_dma_enable
List of PWM DMA options.
Values:
-
enumerator kPWM_CaptureX0DMAEnable
PWM capture X0 DMA
-
enumerator kPWM_CaptureX1DMAEnable
PWM capture X1 DMA
-
enumerator kPWM_CaptureB0DMAEnable
PWM capture B0 DMA
-
enumerator kPWM_CaptureB1DMAEnable
PWM capture B1 DMA
-
enumerator kPWM_CaptureA0DMAEnable
PWM capture A0 DMA
-
enumerator kPWM_CaptureA1DMAEnable
PWM capture A1 DMA
-
enumerator kPWM_CaptureX0DMAEnable
-
enum _pwm_dma_source_select
List of PWM capture DMA enable source select.
Values:
-
enumerator kPWM_DMARequestDisable
Read DMA requests disabled
-
enumerator kPWM_DMAWatermarksEnable
Exceeding a FIFO watermark sets the DMA read request
-
enumerator kPWM_DMALocalSync
A local sync (VAL1 matches counter) sets the read DMA request
-
enumerator kPWM_DMALocalReload
A local reload (STS[RF] being set) sets the read DMA request
-
enumerator kPWM_DMARequestDisable
-
enum _pwm_watermark_control
PWM FIFO Watermark AND Control.
Values:
-
enumerator kPWM_FIFOWatermarksOR
Selected FIFO watermarks are OR’ed together
-
enumerator kPWM_FIFOWatermarksAND
Selected FIFO watermarks are AND’ed together
-
enumerator kPWM_FIFOWatermarksOR
-
enum _pwm_mode
PWM operation mode.
Values:
-
enumerator kPWM_SignedCenterAligned
Signed center-aligned
-
enumerator kPWM_CenterAligned
Unsigned cente-aligned
-
enumerator kPWM_SignedEdgeAligned
Signed edge-aligned
-
enumerator kPWM_EdgeAligned
Unsigned edge-aligned
-
enumerator kPWM_SignedCenterAligned
-
enum _pwm_level_select
PWM output pulse mode, high-true or low-true.
Values:
-
enumerator kPWM_HighTrue
High level represents “on” or “active” state
-
enumerator kPWM_LowTrue
Low level represents “on” or “active” state
-
enumerator kPWM_HighTrue
-
enum _pwm_fault_state
PWM output fault status.
Values:
-
enumerator kPWM_PwmFaultState0
Output is forced to logic 0 state prior to consideration of output polarity control.
-
enumerator kPWM_PwmFaultState1
Output is forced to logic 1 state prior to consideration of output polarity control.
-
enumerator kPWM_PwmFaultState2
Output is tristated.
-
enumerator kPWM_PwmFaultState3
Output is tristated.
-
enumerator kPWM_PwmFaultState0
-
enum _pwm_reload_source_select
PWM reload source select.
Values:
-
enumerator kPWM_LocalReload
The local reload signal is used to reload registers
-
enumerator kPWM_MasterReload
The master reload signal (from submodule 0) is used to reload
-
enumerator kPWM_LocalReload
-
enum _pwm_fault_clear
PWM fault clearing options.
Values:
-
enumerator kPWM_Automatic
Automatic fault clearing
-
enumerator kPWM_ManualNormal
Manual fault clearing with no fault safety mode
-
enumerator kPWM_ManualSafety
Manual fault clearing with fault safety mode
-
enumerator kPWM_Automatic
-
enum _pwm_module_control
Options for submodule master control operation.
Values:
-
enumerator kPWM_Control_Module_0
Control submodule 0’s start/stop,buffer reload operation
-
enumerator kPWM_Control_Module_1
Control submodule 1’s start/stop,buffer reload operation
-
enumerator kPWM_Control_Module_2
Control submodule 2’s start/stop,buffer reload operation
-
enumerator kPWM_Control_Module_3
Control submodule 3’s start/stop,buffer reload operation
-
enumerator kPWM_Control_Module_0
-
typedef enum _pwm_submodule pwm_submodule_t
List of PWM submodules.
-
typedef enum _pwm_channels pwm_channels_t
List of PWM channels in each module.
-
typedef enum _pwm_value_register pwm_value_register_t
List of PWM value registers.
-
typedef enum _pwm_clock_source pwm_clock_source_t
PWM clock source selection.
-
typedef enum _pwm_clock_prescale pwm_clock_prescale_t
PWM prescaler factor selection for clock source.
-
typedef enum _pwm_force_output_trigger pwm_force_output_trigger_t
Options that can trigger a PWM FORCE_OUT.
-
typedef enum _pwm_output_state pwm_output_state_t
PWM channel output status.
-
typedef enum _pwm_init_source pwm_init_source_t
PWM counter initialization options.
-
typedef enum _pwm_load_frequency pwm_load_frequency_t
PWM load frequency selection.
-
typedef enum _pwm_fault_input pwm_fault_input_t
List of PWM fault selections.
-
typedef enum _pwm_fault_disable pwm_fault_disable_t
List of PWM fault disable mapping selections.
-
typedef enum _pwm_fault_channels pwm_fault_channels_t
List of PWM fault channels.
-
typedef enum _pwm_input_capture_edge pwm_input_capture_edge_t
PWM capture edge select.
-
typedef enum _pwm_force_signal pwm_force_signal_t
PWM output options when a FORCE_OUT signal is asserted.
-
typedef enum _pwm_chnl_pair_operation pwm_chnl_pair_operation_t
Options available for the PWM A & B pair operation.
-
typedef enum _pwm_register_reload pwm_register_reload_t
Options available on how to load the buffered-registers with new values.
-
typedef enum _pwm_fault_recovery_mode pwm_fault_recovery_mode_t
Options available on how to re-enable the PWM output when recovering from a fault.
-
typedef enum _pwm_interrupt_enable pwm_interrupt_enable_t
List of PWM interrupt options.
-
typedef enum _pwm_status_flags pwm_status_flags_t
List of PWM status flags.
-
typedef enum _pwm_dma_enable pwm_dma_enable_t
List of PWM DMA options.
-
typedef enum _pwm_dma_source_select pwm_dma_source_select_t
List of PWM capture DMA enable source select.
-
typedef enum _pwm_watermark_control pwm_watermark_control_t
PWM FIFO Watermark AND Control.
-
typedef enum _pwm_mode pwm_mode_t
PWM operation mode.
-
typedef enum _pwm_level_select pwm_level_select_t
PWM output pulse mode, high-true or low-true.
-
typedef enum _pwm_fault_state pwm_fault_state_t
PWM output fault status.
-
typedef enum _pwm_reload_source_select pwm_reload_source_select_t
PWM reload source select.
-
typedef enum _pwm_fault_clear pwm_fault_clear_t
PWM fault clearing options.
-
typedef enum _pwm_module_control pwm_module_control_t
Options for submodule master control operation.
-
typedef struct _pwm_signal_param pwm_signal_param_t
Structure for the user to define the PWM signal characteristics.
-
typedef struct _pwm_config pwm_config_t
PWM config structure.
This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
-
typedef struct _pwm_fault_input_filter_param pwm_fault_input_filter_param_t
Structure for the user to configure the fault input filter.
-
typedef struct _pwm_fault_param pwm_fault_param_t
Structure is used to hold the parameters to configure a PWM fault.
-
typedef struct _pwm_input_capture_param pwm_input_capture_param_t
Structure is used to hold parameters to configure the capture capability of a signal pin.
-
void PWM_SetupInputCapture(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, const pwm_input_capture_param_t *inputCaptureParams)
Sets up the PWM input capture.
Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function sets up the capture parameters for each pin and enables the pin for input capture operation.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel in the submodule to setup
inputCaptureParams – Parameters passed in to set up the input pin
-
void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams)
Sets up the PWM fault input filter.
- Parameters:
base – PWM peripheral base address
faultInputFilterParams – Parameters passed in to set up the fault input filter.
-
void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)
Sets up the PWM fault protection.
PWM has 4 fault inputs.
- Parameters:
base – PWM peripheral base address
faultNum – PWM fault to configure.
faultParams – Pointer to the PWM fault config structure
-
void PWM_FaultDefaultConfig(pwm_fault_param_t *config)
Fill in the PWM fault config struct with the default settings.
The default values are:
config->faultClearingMode = kPWM_Automatic; config->faultLevel = false; config->enableCombinationalPath = true; config->recoverMode = kPWM_NoRecovery;
- Parameters:
config – Pointer to user’s PWM fault config structure.
-
void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)
Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted.
The user specifies which channel to configure by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
mode – Signal to output when a FORCE_OUT is triggered
-
static inline void PWM_SetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, uint16_t value)
Set the PWM VALx registers.
This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is reached.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – VALx register that will be writen new value
value – Value that will been write into VALx register
-
static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister)
Get the PWM VALx registers.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – VALx register that will be read value
- Returns:
The VALx register value
-
static inline void PWM_OutputTriggerEnable(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, bool activate)
Enables or disables the PWM output trigger.
This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated when the counter matches VAL 1, VAL 3, or VAL 5 register.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – Value register that will activate the trigger
activate – true: Enable the trigger; false: Disable the trigger
-
static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)
Enables the PWM output trigger.
This function allows the user to enable one or more (VAL0-5) PWM trigger.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegisterMask – Value register mask that will activate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask
-
static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)
Disables the PWM output trigger.
This function allows the user to disables one or more (VAL0-5) PWM trigger.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegisterMask – Value register mask that will Deactivate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask
-
static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value)
Sets the software control output for a pin to high or low.
The user specifies which channel to modify by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
value – true: Supply a logic 1, false: Supply a logic 0.
-
static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value)
Sets or clears the PWM LDOK bit on a single or multiple submodules.
Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the values are loaded at the next PWM reload point. This function can issue the load command to multiple submodules at the same time.
- Parameters:
base – PWM peripheral base address
subModulesToUpdate – PWM submodules to update with buffered values. This is a logical OR of members of the enumeration pwm_module_control_t
value – true: Set LDOK bit for the submodule list; false: Clear LDOK bit
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static inline void PWM_SetPwmFaultState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_state_t faultState)
Set PWM output fault status.
These bits determine the fault state for the PWM_A output in fault conditions and STOP mode. It may also define the output state in WAIT and DEBUG modes depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. This function can update PWM output fault status.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
faultState – PWM output fault status
-
static inline void PWM_SetupFaultDisableMap(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_channels_t pwm_fault_channels, uint16_t value)
Set PWM fault disable mapping.
Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned off if there is a logic 1 on an FAULTx input and a 1 in the corresponding bit of this field. A reset sets all bits in this field.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
pwm_fault_channels – PWM fault channel to configure
value – Fault disable mapping mask value enumeration pwm_fault_disable_t
-
static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)
Set PWM output enable.
This feature allows the user to enable the PWM Output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.
- Parameters:
base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
-
static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)
Set PWM output disable.
This feature allows the user to disable the PWM output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.
- Parameters:
base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
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uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel)
Get the dutycycle value.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
- Returns:
Current channel dutycycle value.
-
status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus)
Set PWM output in idle status (high or low).
Note
This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported.
- Parameters:
base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.
- Returns:
kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success
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void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler)
Set the pwm submodule prescaler.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
prescaler – Set prescaler value
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void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero)
This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0.
- Parameters:
base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
forcetozero – True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal function.
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void PWM_SetChannelOutput(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_output_state_t outputstate)
This function set the output state of the PWM pin as requested for the current cycle.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
outputstate – Set pwm output state, see pwm_output_state_t.
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status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles)
This function set the phase delay from the master sync signal of submodule 0.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
delayCycles – Number of cycles delayed from submodule 0.
- Returns:
kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; kStatus_Success if set phase delay success
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static inline void PWM_SetFilterSampleCount(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSampleCount)
This function set the number of consecutive samples that must agree prior to the input filter.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
filterSampleCount – Number of consecutive samples.
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static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSamplePeriod)
This function set the sampling period of the fault pin input filter.
- Parameters:
base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
filterSamplePeriod – Sampling period of input filter.
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PWM_SUBMODULE_SWCONTROL_WIDTH
Number of bits per submodule for software output control
-
PWM_SUBMODULE_CHANNEL
Submodule channels include PWMA, PWMB, PWMX.
-
struct _pwm_signal_param
- #include <fsl_pwm.h>
Structure for the user to define the PWM signal characteristics.
Public Members
-
pwm_channels_t pwmChannel
PWM channel being configured; PWM A or PWM B
-
uint8_t dutyCyclePercent
PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle)
-
pwm_level_select_t level
PWM output active level select
-
uint16_t deadtimeValue
The deadtime value; only used if channel pair is operating in complementary mode
-
pwm_fault_state_t faultState
PWM output fault status
-
bool pwmchannelenable
Enable PWM output
-
pwm_channels_t pwmChannel
-
struct _pwm_config
- #include <fsl_pwm.h>
PWM config structure.
This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
Public Members
-
bool enableDebugMode
true: PWM continues to run in debug mode; false: PWM is paused in debug mode
-
pwm_init_source_t initializationControl
Option to initialize the counter
-
pwm_clock_source_t clockSource
Clock source for the counter
-
pwm_clock_prescale_t prescale
Pre-scaler to divide down the clock
-
pwm_chnl_pair_operation_t pairOperation
Channel pair in indepedent or complementary mode
-
pwm_register_reload_t reloadLogic
PWM Reload logic setup
-
pwm_reload_source_select_t reloadSelect
Reload source select
-
pwm_load_frequency_t reloadFrequency
Specifies when to reload, used when user’s choice is not immediate reload
-
pwm_force_output_trigger_t forceTrigger
Specify which signal will trigger a FORCE_OUT
-
bool enableDebugMode
-
struct _pwm_fault_input_filter_param
- #include <fsl_pwm.h>
Structure for the user to configure the fault input filter.
Public Members
-
uint8_t faultFilterCount
Fault filter count
-
uint8_t faultFilterPeriod
Fault filter period;value of 0 will bypass the filter
-
bool faultGlitchStretch
Fault Glitch Stretch Enable: A logic 1 means that input fault signals will be stretched to at least 2 IPBus clock cycles
-
uint8_t faultFilterCount
-
struct _pwm_fault_param
- #include <fsl_pwm.h>
Structure is used to hold the parameters to configure a PWM fault.
Public Members
-
pwm_fault_clear_t faultClearingMode
Fault clearing mode to use
-
bool faultLevel
true: Logic 1 indicates fault; false: Logic 0 indicates fault
-
bool enableCombinationalPath
true: Combinational Path from fault input is enabled; false: No combination path is available
-
pwm_fault_recovery_mode_t recoverMode
Specify when to re-enable the PWM output
-
pwm_fault_clear_t faultClearingMode
-
struct _pwm_input_capture_param
- #include <fsl_pwm.h>
Structure is used to hold parameters to configure the capture capability of a signal pin.
Public Members
-
bool captureInputSel
true: Use the edge counter signal as source false: Use the raw input signal from the pin as source
-
uint8_t edgeCompareValue
Compare value, used only if edge counter is used as source
-
pwm_input_capture_edge_t edge0
Specify which edge causes a capture for input circuitry 0
-
pwm_input_capture_edge_t edge1
Specify which edge causes a capture for input circuitry 1
-
bool enableOneShotCapture
true: Use one-shot capture mode; false: Use free-running capture mode
-
uint8_t fifoWatermark
Watermark level for capture FIFO. The capture flags in the status register will set if the word count in the FIFO is greater than this watermark level
-
bool captureInputSel
QTMR: Quad Timer Driver
-
void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)
Ungates the Quad Timer clock and configures the peripheral for basic operation.
Note
This API should be called at the beginning of the application using the Quad Timer driver.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
config – Pointer to user’s Quad Timer config structure
-
void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)
Stops the counter and gates the Quad Timer clock.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
-
void QTMR_GetDefaultConfig(qtmr_config_t *config)
Fill in the Quad Timer config struct with the default settings.
The default values are:
config->debugMode = kQTMR_RunNormalInDebug; config->enableExternalForce = false; config->enableMasterMode = false; config->faultFilterCount = 0; config->faultFilterPeriod = 0; config->primarySource = kQTMR_ClockDivide_2; config->secondarySource = kQTMR_Counter0InputPin;
- Parameters:
config – Pointer to user’s Quad Timer config structure.
-
void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
Enables the selected Quad Timer interrupts.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t
-
void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
Disables the selected Quad Timer interrupts.
- Parameters:
base – Quad Timer peripheral base addres
channel – Quad Timer channel number
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t
-
uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)
Gets the enabled Quad Timer interrupts.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration qtmr_interrupt_enable_t
-
uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)
Gets the Quad Timer status flags.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
- Returns:
The status flags. This is the logical OR of members of the enumeration qtmr_status_flags_t
-
void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
Clears the Quad Timer status flags.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The status flags to clear. This is a logical OR of members of the enumeration qtmr_status_flags_t
-
void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
Sets the timer period in ticks.
Timers counts from initial value till it equals the count value set here. The counter will then reinitialize to the value specified in the Load register.
Note
This function will write the time period in ticks to COMP1 or COMP2 register depending on the count direction
User can call the utility macros provided in fsl_common.h to convert to ticks
This function supports cases, providing only primary source clock without secondary source clock.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
ticks – Timer period in units of ticks
-
void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
Set compare value.
This function sets the value used for comparison with the counter value.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
ticks – Timer period in units of ticks.
-
static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value)
Set load value.
This function sets the value used to initialize the counter after a counter comparison.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
value – Load register initialization value.
-
static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)
Reads the current timer counting value.
This function returns the real-time timer counting value, in a range from 0 to a timer period.
Note
User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
- Returns:
Current counter value in ticks
-
static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)
Starts the Quad Timer counter.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
clockSource – Quad Timer clock source
-
static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)
Stops the Quad Timer counter.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
-
void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
Enable the Quad Timer DMA.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t
-
void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
Disable the Quad Timer DMA.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t
-
void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus)
Set PWM output in idle status (high or low).
Note
When the PWM is set again, the counting needs to be restarted.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.
-
static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)
Get the channel output status.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
- Returns:
Current channel output status.
-
uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)
Get the PWM channel dutycycle value.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
- Returns:
Current channel dutycycle value.
-
void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler)
This function set the value of the prescaler on QTimer channels.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
prescaler – Set prescaler value
-
FSL_QTMR_DRIVER_VERSION
Version
-
enum _qtmr_primary_count_source
Quad Timer primary clock source selection.
Values:
-
enumerator kQTMR_ClockCounter0InputPin
Use counter 0 input pin
-
enumerator kQTMR_ClockCounter1InputPin
Use counter 1 input pin
-
enumerator kQTMR_ClockCounter2InputPin
Use counter 2 input pin
-
enumerator kQTMR_ClockCounter3InputPin
Use counter 3 input pin
-
enumerator kQTMR_ClockCounter0Output
Use counter 0 output
-
enumerator kQTMR_ClockCounter1Output
Use counter 1 output
-
enumerator kQTMR_ClockCounter2Output
Use counter 2 output
-
enumerator kQTMR_ClockCounter3Output
Use counter 3 output
-
enumerator kQTMR_ClockDivide_1
IP bus clock divide by 1 prescaler
-
enumerator kQTMR_ClockDivide_2
IP bus clock divide by 2 prescaler
-
enumerator kQTMR_ClockDivide_4
IP bus clock divide by 4 prescaler
-
enumerator kQTMR_ClockDivide_8
IP bus clock divide by 8 prescaler
-
enumerator kQTMR_ClockDivide_16
IP bus clock divide by 16 prescaler
-
enumerator kQTMR_ClockDivide_32
IP bus clock divide by 32 prescaler
-
enumerator kQTMR_ClockDivide_64
IP bus clock divide by 64 prescaler
-
enumerator kQTMR_ClockDivide_128
IP bus clock divide by 128 prescaler
-
enumerator kQTMR_ClockCounter0InputPin
-
enum _qtmr_input_source
Quad Timer input sources selection.
Values:
-
enumerator kQTMR_Counter0InputPin
Use counter 0 input pin
-
enumerator kQTMR_Counter1InputPin
Use counter 1 input pin
-
enumerator kQTMR_Counter2InputPin
Use counter 2 input pin
-
enumerator kQTMR_Counter3InputPin
Use counter 3 input pin
-
enumerator kQTMR_Counter0InputPin
-
enum _qtmr_counting_mode
Quad Timer counting mode selection.
Values:
-
enumerator kQTMR_NoOperation
No operation
-
enumerator kQTMR_PriSrcRiseEdge
Count rising edges of primary source
-
enumerator kQTMR_PriSrcRiseAndFallEdge
Count rising and falling edges of primary source
-
enumerator kQTMR_PriSrcRiseEdgeSecInpHigh
Count rise edges of pri SRC while sec inp high active
-
enumerator kQTMR_QuadCountMode
Quadrature count mode, uses pri and sec sources
-
enumerator kQTMR_PriSrcRiseEdgeSecDir
Count rising edges of pri SRC; sec SRC specifies dir
-
enumerator kQTMR_SecSrcTrigPriCnt
Edge of sec SRC trigger primary count until compare
-
enumerator kQTMR_CascadeCount
Cascaded count mode (up/down)
-
enumerator kQTMR_NoOperation
-
enum _qtmr_pwm_out_state
Quad Timer PWM output state.
Values:
-
enumerator kQTMR_PwmLow
The output state of PWM channel is low
-
enumerator kQTMR_PwmHigh
The output state of PWM channel is low
-
enumerator kQTMR_PwmLow
-
enum _qtmr_output_mode
Quad Timer output mode selection.
Values:
-
enumerator kQTMR_AssertWhenCountActive
Assert OFLAG while counter is active
-
enumerator kQTMR_ClearOnCompare
Clear OFLAG on successful compare
-
enumerator kQTMR_SetOnCompare
Set OFLAG on successful compare
-
enumerator kQTMR_ToggleOnCompare
Toggle OFLAG on successful compare
-
enumerator kQTMR_ToggleOnAltCompareReg
Toggle OFLAG using alternating compare registers
-
enumerator kQTMR_SetOnCompareClearOnSecSrcInp
Set OFLAG on compare, clear on sec SRC input edge
-
enumerator kQTMR_SetOnCompareClearOnCountRoll
Set OFLAG on compare, clear on counter rollover
-
enumerator kQTMR_EnableGateClock
Enable gated clock output while count is active
-
enumerator kQTMR_AssertWhenCountActive
-
enum _qtmr_input_capture_edge
Quad Timer input capture edge mode, rising edge, or falling edge.
Values:
-
enumerator kQTMR_NoCapture
Capture is disabled
-
enumerator kQTMR_RisingEdge
Capture on rising edge (IPS=0) or falling edge (IPS=1)
-
enumerator kQTMR_FallingEdge
Capture on falling edge (IPS=0) or rising edge (IPS=1)
-
enumerator kQTMR_RisingAndFallingEdge
Capture on both edges
-
enumerator kQTMR_NoCapture
-
enum _qtmr_preload_control
Quad Timer input capture edge mode, rising edge, or falling edge.
Values:
-
enumerator kQTMR_NoPreload
Never preload
-
enumerator kQTMR_LoadOnComp1
Load upon successful compare with value in COMP1
-
enumerator kQTMR_LoadOnComp2
Load upon successful compare with value in COMP2
-
enumerator kQTMR_NoPreload
-
enum _qtmr_debug_action
List of Quad Timer run options when in Debug mode.
Values:
-
enumerator kQTMR_RunNormalInDebug
Continue with normal operation
-
enumerator kQTMR_HaltCounter
Halt counter
-
enumerator kQTMR_ForceOutToZero
Force output to logic 0
-
enumerator kQTMR_HaltCountForceOutZero
Halt counter and force output to logic 0
-
enumerator kQTMR_RunNormalInDebug
-
enum _qtmr_interrupt_enable
List of Quad Timer interrupts.
Values:
-
enumerator kQTMR_CompareInterruptEnable
Compare interrupt.
-
enumerator kQTMR_Compare1InterruptEnable
Compare 1 interrupt.
-
enumerator kQTMR_Compare2InterruptEnable
Compare 2 interrupt.
-
enumerator kQTMR_OverflowInterruptEnable
Timer overflow interrupt.
-
enumerator kQTMR_EdgeInterruptEnable
Input edge interrupt.
-
enumerator kQTMR_CompareInterruptEnable
-
enum _qtmr_status_flags
List of Quad Timer flags.
Values:
-
enumerator kQTMR_CompareFlag
Compare flag
-
enumerator kQTMR_Compare1Flag
Compare 1 flag
-
enumerator kQTMR_Compare2Flag
Compare 2 flag
-
enumerator kQTMR_OverflowFlag
Timer overflow flag
-
enumerator kQTMR_EdgeFlag
Input edge flag
-
enumerator kQTMR_CompareFlag
-
enum _qtmr_channel_selection
List of channel selection.
Values:
-
enumerator kQTMR_Channel_0
TMR Channel 0
-
enumerator kQTMR_Channel_1
TMR Channel 1
-
enumerator kQTMR_Channel_2
TMR Channel 2
-
enumerator kQTMR_Channel_3
TMR Channel 3
-
enumerator kQTMR_Channel_0
-
enum _qtmr_dma_enable
List of Quad Timer DMA enable.
Values:
-
enumerator kQTMR_InputEdgeFlagDmaEnable
Input Edge Flag DMA Enable.
-
enumerator kQTMR_ComparatorPreload1DmaEnable
Comparator Preload Register 1 DMA Enable.
-
enumerator kQTMR_ComparatorPreload2DmaEnable
Comparator Preload Register 2 DMA Enable.
-
enumerator kQTMR_InputEdgeFlagDmaEnable
-
typedef enum _qtmr_primary_count_source qtmr_primary_count_source_t
Quad Timer primary clock source selection.
-
typedef enum _qtmr_input_source qtmr_input_source_t
Quad Timer input sources selection.
-
typedef enum _qtmr_counting_mode qtmr_counting_mode_t
Quad Timer counting mode selection.
-
typedef enum _qtmr_pwm_out_state qtmr_pwm_out_state_t
Quad Timer PWM output state.
-
typedef enum _qtmr_output_mode qtmr_output_mode_t
Quad Timer output mode selection.
-
typedef enum _qtmr_input_capture_edge qtmr_input_capture_edge_t
Quad Timer input capture edge mode, rising edge, or falling edge.
-
typedef enum _qtmr_preload_control qtmr_preload_control_t
Quad Timer input capture edge mode, rising edge, or falling edge.
-
typedef enum _qtmr_debug_action qtmr_debug_action_t
List of Quad Timer run options when in Debug mode.
-
typedef enum _qtmr_interrupt_enable qtmr_interrupt_enable_t
List of Quad Timer interrupts.
-
typedef enum _qtmr_status_flags qtmr_status_flags_t
List of Quad Timer flags.
-
typedef enum _qtmr_channel_selection qtmr_channel_selection_t
List of channel selection.
-
typedef enum _qtmr_dma_enable qtmr_dma_enable_t
List of Quad Timer DMA enable.
-
typedef struct _qtmr_config qtmr_config_t
Quad Timer config structure.
This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
-
status_t QTMR_SetupPwm(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)
Sets up Quad timer module for PWM signal output.
The function initializes the timer module according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
pwmFreqHz – PWM signal frequency in Hz
dutyCyclePercent – PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)
outputPolarity – true: invert polarity of the output signal, false: no inversion
srcClock_Hz – Main counter clock in Hz.
- Returns:
Returns an error if there was error setting up the signal.
-
void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, bool inputPolarity, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode)
Allows the user to count the source clock cycles until a capture event arrives.
The count is stored in the capture register.
- Parameters:
base – Quad Timer peripheral base address
channel – Quad Timer channel number
capturePin – Pin through which we receive the input signal to trigger the capture
inputPolarity – true: invert polarity of the input signal, false: no inversion
reloadOnCapture – true: reload the counter when an input capture occurs, false: no reload
captureMode – Specifies which edge of the input signal triggers a capture
-
TMR_CSCTRL_OFLAG_MASK
-
TMR_CSCTRL_OFLAG_SHIFT
-
struct _qtmr_config
- #include <fsl_qtmr.h>
Quad Timer config structure.
This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
Public Members
-
qtmr_primary_count_source_t primarySource
Specify the primary count source
-
qtmr_input_source_t secondarySource
Specify the secondary count source
-
bool enableMasterMode
true: Broadcast compare function output to other counters; false no broadcast
-
bool enableExternalForce
true: Compare from another counter force state of OFLAG signal false: OFLAG controlled by local counter
-
uint8_t faultFilterCount
Fault filter count
-
uint8_t faultFilterPeriod
Fault filter period;value of 0 will bypass the filter
-
qtmr_debug_action_t debugMode
Operation in Debug mode
-
qtmr_primary_count_source_t primarySource
RGPIO: Rapid General-Purpose Input/Output Driver
-
FSL_RGPIO_DRIVER_VERSION
RGPIO driver version 2.1.0.
-
enum _rgpio_pin_direction
RGPIO direction definition.
Values:
-
enumerator kRGPIO_DigitalInput
Set current pin as digital input
-
enumerator kRGPIO_DigitalOutput
Set current pin as digital output
-
enumerator kRGPIO_DigitalInput
-
enum _rgpio_checker_attribute
RGPIO checker attribute.
Values:
-
enumerator kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW
User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW
User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW
User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW
User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW
User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW
User nonsecure:None; User Secure:None; Privileged Secure:Read+Write
-
enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR
User nonsecure:None; User Secure:None; Privileged Secure:Read
-
enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN
User nonsecure:None; User Secure:None; Privileged Secure:None
-
enumerator kRGPIO_IgnoreAttributeCheck
Ignores the attribute check
-
enumerator kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW
-
enum _rgpio_interrupt_sel
Configures the interrupt generation condition.
Values:
-
enumerator kRGPIO_InterruptOutput0
Interrupt/DMA request/trigger output 0.
-
enumerator kRGPIO_InterruptOutput1
Interrupt/DMA request/trigger output 1.
-
enumerator kRGPIO_InterruptOutput2
Interrupt/DMA request/trigger output 2.
-
enumerator kRGPIO_InterruptOutput3
Interrupt/DMA request/trigger output 3.
-
enumerator kRGPIO_InterruptOutput0
-
enum _rgpio_interrupt_config
Configures the interrupt generation condition.
Values:
-
enumerator kRGPIO_InterruptOrDMADisabled
Interrupt/DMA request is disabled.
-
enumerator kRGPIO_DMARisingEdge
DMA request on rising edge.
-
enumerator kRGPIO_DMAFallingEdge
DMA request on falling edge.
-
enumerator kRGPIO_DMAEitherEdge
DMA request on either edge.
-
enumerator kRGPIO_FlagRisingEdge
Flag sets on rising edge.
-
enumerator kRGPIO_FlagFallingEdge
Flag sets on falling edge.
-
enumerator kRGPIO_FlagEitherEdge
Flag sets on either edge.
-
enumerator kRGPIO_InterruptLogicZero
Interrupt when logic zero.
-
enumerator kRGPIO_InterruptRisingEdge
Interrupt on rising edge.
-
enumerator kRGPIO_InterruptFallingEdge
Interrupt on falling edge.
-
enumerator kRGPIO_InterruptEitherEdge
Interrupt on either edge.
-
enumerator kRGPIO_InterruptLogicOne
Interrupt when logic one.
-
enumerator kRGPIO_ActiveHighTriggerOutputEnable
Enable active high-trigger output.
-
enumerator kRGPIO_ActiveLowTriggerOutputEnable
Enable active low-trigger output.
-
enumerator kRGPIO_InterruptOrDMADisabled
-
typedef enum _rgpio_pin_direction rgpio_pin_direction_t
RGPIO direction definition.
-
typedef enum _rgpio_checker_attribute rgpio_checker_attribute_t
RGPIO checker attribute.
-
typedef enum _rgpio_interrupt_sel rgpio_interrupt_sel_t
Configures the interrupt generation condition.
-
typedef enum _rgpio_interrupt_config rgpio_interrupt_config_t
Configures the interrupt generation condition.
-
typedef struct _rgpio_pin_config rgpio_pin_config_t
The RGPIO pin configuration structure.
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().
-
struct _rgpio_pin_config
- #include <fsl_rgpio.h>
The RGPIO pin configuration structure.
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().
Public Members
-
rgpio_pin_direction_t pinDirection
RGPIO direction, input or output
-
uint8_t outputLogic
Set a default output logic, which has no use in input
-
rgpio_pin_direction_t pinDirection
RGPIO Driver
-
void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config)
Initializes a RGPIO pin used by the board.
To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. Then, call the RGPIO_PinInit() function.
This is an example to define an input pin or an output pin configuration.
Define a digital input pin configuration, rgpio_pin_config_t config = { kRGPIO_DigitalInput, 0, } Define a digital output pin configuration, rgpio_pin_config_t config = { kRGPIO_DigitalOutput, 0, }
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
pin – RGPIO port pin number
config – RGPIO pin configuration pointer
-
uint32_t RGPIO_GetInstance(RGPIO_Type *base)
Gets the RGPIO instance according to the RGPIO base.
- Parameters:
base – RGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
- Return values:
RGPIO – instance
-
static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output)
Sets the output level of the multiple RGPIO pins to the logic 1 or 0.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
pin – RGPIO pin number
output – RGPIO pin output logic level.
0: corresponding pin output low-logic level.
1: corresponding pin output high-logic level.
-
static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output)
Sets the output level of the multiple RGPIO pins to the logic 1 or 0.
- Deprecated:
Do not use this function. It has been superceded by RGPIO_PinWrite.
-
static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask)
Sets the output level of the multiple RGPIO pins to the logic 1.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro
-
static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask)
Sets the output level of the multiple RGPIO pins to the logic 1.
- Deprecated:
Do not use this function. It has been superceded by RGPIO_PortSet.
-
static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask)
Sets the output level of the multiple RGPIO pins to the logic 0.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro
-
static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask)
Sets the output level of the multiple RGPIO pins to the logic 0.
- Deprecated:
Do not use this function. It has been superceded by RGPIO_PortClear.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro
-
static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask)
Reverses the current output logic of the multiple RGPIO pins.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro
-
static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask)
Reverses the current output logic of the multiple RGPIO pins.
- Deprecated:
Do not use this function. It has been superceded by RGPIO_PortToggle.
-
static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin)
Reads the current input value of the RGPIO port.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
pin – RGPIO pin number
- Return values:
RGPIO – port input value
0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.
-
static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin)
Reads the current input value of the RGPIO port.
- Deprecated:
Do not use this function. It has been superceded by RGPIO_PinRead.
-
static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable)
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number mask
enable – RGPIO digital input enable/disable flag.
-
void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute)
The RGPIO module supports a device-specific number of data ports, organized as 32-bit words. Each 32-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro
-
static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base, uint32_t pin, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)
Configures the gpio pin interrupt/DMA request.
- Parameters:
base – RGPIO peripheral base pointer.
pin – RGPIO pin number.
sel – RGPIO pin interrupt selection(0-3).
config – RGPIO pin interrupt configuration.
-
static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base, uint32_t mask, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)
Sets the gpio interrupt configuration in ICR register for multiple pins.
- Parameters:
base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
mask – RGPIO pin number macro.
sel – RGPIO pin interrupt selection(0-3).
config – RGPIO pin interrupt configuration.
-
static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel)
Reads the whole gpio status flag.
If a pin is configured to generate the DMA request, the corresponding flag is cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted, the flag is set again immediately.
- Parameters:
base – RGPIO peripheral base pointer.
sel – RGPIO pin interrupt selection(0-3).
- Returns:
Current gpio interrupt status flags, for example, 0x00010001 means the pin 0 and 16 have the interrupt.
-
static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask)
Clears the multiple pin interrupt status flag.
- Parameters:
base – RGPIO peripheral base pointer.
sel – RGPIO pin interrupt selection(0-3).
mask – RGPIO pin number macro.
Romapi
Flash Pad Definitions.
Values:
-
enumerator kSerialFlash_1Pad
1-wire communication
-
enumerator kSerialFlash_2Pads
2-wire communication
-
enumerator kSerialFlash_4Pads
4-wire communication
-
enumerator kSerialFlash_8Pads
8-wire communication
-
enumerator kSerialFlash_1Pad
FLEXSPI clock configuration type.
Values:
-
enumerator kFLEXSPIClk_SDR
Clock configure for SDR mode
-
enumerator kFLEXSPIClk_DDR
Clock configure for DDR mode
-
enumerator kFLEXSPIClk_SDR
-
enum _flexspi_read_sample_clk
FLEXSPI Read Sample Clock Source definition.
Values:
-
enumerator kFLEXSPIReadSampleClk_LoopbackInternally
FLEXSPI Read Sample Clock Source from the Internal loopback
-
enumerator kFLEXSPIReadSampleClk_LoopbackFromDqsPad
FLEXSPI Read Sample Clock Source from the Dqs Pad loopback
-
enumerator kFLEXSPIReadSampleClk_LoopbackFromSckPad
FLEXSPI Read Sample Clock Source from the Sck Pad loopback
-
enumerator kFLEXSPIReadSampleClk_ExternalInputFromDqsPad
FLEXSPI Read Sample Clock Source from the External Input by the Dqs Pad
-
enumerator kFLEXSPIReadSampleClk_LoopbackInternally
Flash Type Definition.
Values:
-
enumerator kFLEXSPIDeviceType_SerialNOR
Flash device is Serial NOR
-
enumerator kFLEXSPIDeviceType_SerialNOR
Flash Configuration Command Type.
Values:
-
enumerator kDeviceConfigCmdType_Generic
Generic command, for example: configure dummy cycles, drive strength, etc.
-
enumerator kDeviceConfigCmdType_QuadEnable
Quad Enable command
-
enumerator kDeviceConfigCmdType_Spi2Xpi
Switch from SPI to DPI/QPI/OPI mode
-
enumerator kDeviceConfigCmdType_Xpi2Spi
Switch from DPI/QPI/OPI to SPI mode
-
enumerator kDeviceConfigCmdType_Spi2NoCmd
Switch to 0-4-4/0-8-8 mode
-
enumerator kDeviceConfigCmdType_Reset
Reset device command
-
enumerator kDeviceConfigCmdType_Generic
-
enum _flexspi_serial_clk_freq
Definitions for FLEXSPI Serial Clock Frequency.
Values:
-
enumerator kFLEXSPISerialClk_NoChange
FlexSPI serial clock no changed
-
enumerator kFLEXSPISerialClk_30MHz
FlexSPI serial clock 30MHz
-
enumerator kFLEXSPISerialClk_50MHz
FlexSPI serial clock 50MHz
-
enumerator kFLEXSPISerialClk_60MHz
FlexSPI serial clock 60MHz
-
enumerator kFLEXSPISerialClk_75MHz
FlexSPI serial clock 75MHz
-
enumerator kFLEXSPISerialClk_80MHz
FlexSPI serial clock 80MHz
-
enumerator kFLEXSPISerialClk_100MHz
FlexSPI serial clock 100MHz
-
enumerator kFLEXSPISerialClk_133MHz
FlexSPI serial clock 133MHz
-
enumerator kFLEXSPISerialClk_166MHz
FlexSPI serial clock 166MHz
-
enumerator kFLEXSPISerialClk_NoChange
Misc feature bit definitions.
Values:
-
enumerator kFLEXSPIMiscOffset_DiffClkEnable
Bit for Differential clock enable
-
enumerator kFLEXSPIMiscOffset_Ck2Enable
Bit for CK2 enable
-
enumerator kFLEXSPIMiscOffset_ParallelEnable
Bit for Parallel mode enable
-
enumerator kFLEXSPIMiscOffset_WordAddressableEnable
Bit for Word Addressable enable
-
enumerator kFLEXSPIMiscOffset_SafeConfigFreqEnable
Bit for Safe Configuration Frequency enable
-
enumerator kFLEXSPIMiscOffset_PadSettingOverrideEnable
Bit for Pad setting override enable
-
enumerator kFLEXSPIMiscOffset_DdrModeEnable
Bit for DDR clock configuration indication.
-
enumerator kFLEXSPIMiscOffset_UseValidTimeForAllFreq
Bit for DLLCR settings under all modes
-
enumerator kFLEXSPIMiscOffset_DiffClkEnable
Manufacturer ID.
Values:
-
enumerator kSerialFlash_ISSI_ManufacturerID
Manufacturer ID of the ISSI serial flash
-
enumerator kSerialFlash_Adesto_ManufacturerID
Manufacturer ID of the Adesto Technologies serial flash
-
enumerator kSerialFlash_Winbond_ManufacturerID
Manufacturer ID of the Winbond serial flash
-
enumerator kSerialFlash_Cypress_ManufacturerID
Manufacturer ID for Cypress
-
enumerator kSerialFlash_ISSI_ManufacturerID
-
enum _flexspi_nor_status
ROM FLEXSPI NOR flash status.
Values:
-
enumerator kStatus_ROM_FLEXSPI_SequenceExecutionTimeout
Status for Sequence Execution timeout
-
enumerator kStatus_ROM_FLEXSPI_InvalidSequence
Status for Invalid Sequence
-
enumerator kStatus_ROM_FLEXSPI_DeviceTimeout
Status for Device timeout
-
enumerator kStatus_ROM_FLEXSPINOR_SFDP_NotFound
Status for SFDP read failure
-
enumerator kStatus_ROM_FLEXSPINOR_Flash_NotFound
Status for Flash detection failure
-
enumerator kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed
Status for DDR Read dummy probe failure
-
enumerator kStatus_ROM_FLEXSPI_SequenceExecutionTimeout
-
enum _flexspi_operation
FLEXSPI Operation Context.
Values:
-
enumerator kFLEXSPIOperation_Command
FLEXSPI operation: Only command, both TX and RX buffer are ignored.
-
enumerator kFLEXSPIOperation_Config
FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT.
-
enumerator kFLEXSPIOperation_Write
FLEXSPI operation: Write, only TX buffer is effective
-
enumerator kFLEXSPIOperation_Read
FLEXSPI operation: Read, only Rx Buffer is effective.
-
enumerator kFLEXSPIOperation_Command
-
typedef struct _flexspi_lut_seq flexspi_lut_seq_t
FLEXSPI LUT Sequence structure.
-
typedef struct _flexspi_mem_config flexspi_mem_config_t
FLEXSPI Memory Configuration Block.
-
typedef struct _flexspi_nor_config flexspi_nor_config_t
Serial NOR configuration block.
-
typedef enum _flexspi_operation flexspi_operation_t
FLEXSPI Operation Context.
-
typedef struct _flexspi_xfer flexspi_xfer_t
FLEXSPI Transfer Context.
-
void ROM_API_Init(void)
ROM API init.
Get the bootloader api entry address.
-
kFLEXSPIOperation_End
-
MISRA_CAST(to_type, to_var, from_type, from_var)
convert the type for MISRA
-
typedef struct _serial_nor_config_option serial_nor_config_option_t
Serial NOR Configuration Option.
-
void ROM_RunBootloader(void *arg)
Enter Bootloader.
- Parameters:
arg – A pointer to the storage for the bootloader param. refer to System Boot Chapter in device reference manual for details.
-
status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option)
Get FLEXSPI NOR Configuration Block based on specified option.
- Parameters:
instance – storage the instance of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
option – A pointer to the storage Serial NOR Configuration Option Context.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
Initialize Serial NOR devices via FLEXSPI.
This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
- Parameters:
instance – storage the instance of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src)
Program data to Serial NOR via FLEXSPI.
This function programs the NOR flash memory with the dest address for a given flash area as determined by the dst address and the length.
Note
It is recommended that use page aligned access; If the dst_addr is not aligned to page, the driver automatically aligns address down with the page address.
- Parameters:
instance – storage the instance of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
dst_addr – A pointer to the desired flash memory to be programmed.
src – A pointer to the source buffer of data that is to be programmed into the NOR flash.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_Read(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes)
Read data from Serial NOR via FLEXSPI.
This function read the NOR flash memory with the start address for a given flash area as determined by the dst address and the length.
Note
It is recommended that use page aligned access; If the dstAddr is not aligned to page, the driver automatically aligns address down with the page address.
- Parameters:
instance – storage the instance of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
dst – A pointer to the dest buffer of data that is to be read from the NOR flash.
start – The start address of the desired NOR flash memory to be read.
lengthInBytes – The length, given in bytes to be read.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
Erase Flash Region specified by address and length.
This function erases the appropriate number of flash sectors based on the desired start address and length.
Note
It is recommended that use sector-aligned access nor device; If dstAddr is not aligned with the sector,the driver automatically aligns address down with the sector address.
Note
It is recommended that use sector-aligned access nor device; If length is not aligned with the sector,the driver automatically aligns up with the sector.
- Parameters:
instance – storage the index of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
start – The start address of the desired NOR flash memory to be erased.
length – The length, given in bytes to be erased.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
Erase one sector specified by address.
This function erases one of NOR flash sectors based on the desired address.
Note
It is recommended that use sector-aligned access nor device; If dstAddr is not aligned with the sector, the driver automatically aligns address down with the sector address.
- Parameters:
instance – storage the index of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
start – The start address of the desired NOR flash memory to be erased.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
Erase one block specified by address.
This function erases one block of NOR flash based on the desired address.
Note
It is recommended that use block-aligned access nor device; If dstAddr is not aligned with the block, the driver automatically aligns address down with the block address.
- Parameters:
instance – storage the index of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
start – The start address of the desired NOR flash memory to be erased.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config)
Erase all the Serial NOR devices connected on FLEXSPI.
- Parameters:
instance – storage the instance of FLEXSPI.
config – A pointer to the storage for the driver runtime state.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_DeviceTimeout – the device timeout
-
status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
FLEXSPI command.
This function is used to perform the command write sequence to the NOR device.
- Parameters:
instance – storage the index of FLEXSPI.
xfer – A pointer to the storage FLEXSPI Transfer Context.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
-
status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber)
Configure FLEXSPI Lookup table.
- Parameters:
instance – storage the index of FLEXSPI.
seqIndex – storage the sequence Id.
lutBase – A pointer to the look-up-table for command sequences.
seqNumber – storage sequence number.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
-
status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address)
Wait until device is idle.
- Parameters:
instance – Indicates the index of FLEXSPI.
config – A pointer to the storage for the driver runtime state
isParallelMode – Indicates whether NOR flash is in parallel mode.
address – Indicates the operation(erase/program/read) address for serial NOR flash.
- Return values:
kStatus_Success – Api was executed successfully.
kStatus_InvalidArgument – A invalid argument is provided.
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout – Sequence Execution timeout.
kStatus_ROM_FLEXSPI_InvalidSequence – A invalid Sequence is provided.
kStatus_ROM_FLEXSPI_DeviceTimeout – Device timeout.
-
void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
Software reset for the FLEXSPI logic.
This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.
- Parameters:
instance – storage the index of FLEXSPI.
-
FSL_ROM_HAS_FLEXSPINOR_API
ROM has FLEXSPI NOR API.
-
FSL_ROM_HAS_RUNBOOTLOADER_API
ROM has run bootloader API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG
ROM has FLEXSPI NOR get config API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT
ROM has flash init API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE
ROM has erase API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
ROM has erase sector API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
ROM has erase block API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL
ROM has erase all API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ
ROM has read API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
ROM has update lut API.
-
FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
ROM has FLEXSPI command API.
-
kROM_StatusGroup_FLEXSPINOR
ROM FLEXSPI NOR status group number.
-
FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
-
FSL_ROM_FLEXSPI_BITMASK(bit_offset)
Generate bit mask.
-
FLEXSPI_CFG_BLK_TAG
FLEXSPI memory config block related definitions.
ascii “FCFB” Big Endian
-
FLEXSPI_CFG_BLK_VERSION
V1.4.0
-
CMD_SDR
-
CMD_DDR
-
RADDR_SDR
-
RADDR_DDR
-
CADDR_SDR
-
CADDR_DDR
-
MODE1_SDR
-
MODE1_DDR
-
MODE2_SDR
-
MODE2_DDR
-
MODE4_SDR
-
MODE4_DDR
-
MODE8_SDR
-
MODE8_DDR
-
WRITE_SDR
-
WRITE_DDR
-
READ_SDR
-
READ_DDR
-
LEARN_SDR
-
LEARN_DDR
-
DATSZ_SDR
-
DATSZ_DDR
-
DUMMY_SDR
-
DUMMY_DDR
-
DUMMY_RWDS_SDR
-
DUMMY_RWDS_DDR
-
JMP_ON_CS
-
STOP
-
FLEXSPI_1PAD
-
FLEXSPI_2PAD
-
FLEXSPI_4PAD
-
FLEXSPI_8PAD
-
NOR_CMD_LUT_SEQ_IDX_READ
NOR LUT sequence index used for default LUT assignment.
Note
It will take effect if the lut sequences are not customized. READ LUT sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_READSTATUS
Read Status LUT sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI
Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_WRITEENABLE
Write Enable sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI
Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_ERASESECTOR
Erase Sector sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_READID
-
NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK
Erase Block sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM
Program sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_CHIPERASE
Chip Erase sequence in lookupTable id stored in config block
-
NOR_CMD_LUT_SEQ_IDX_READ_SFDP
Read SFDP sequence in lookupTable id stored in config block
-
NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD
Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-
NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD
Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-
uint32_t max_freq
Maximum supported Frequency
-
uint32_t misc_mode
miscellaneous mode
-
uint32_t quad_mode_setting
Quad mode setting
-
uint32_t cmd_pads
Command pads
-
uint32_t query_pads
SFDP read pads
-
uint32_t device_type
Device type
-
uint32_t option_size
Option size, in terms of uint32_t, size = (option_size + 1) * 4
-
uint32_t tag
Tag, must be 0x0E
-
struct _serial_nor_config_option B
-
uint32_t U
-
union _serial_nor_config_option option0
-
uint32_t dummy_cycles
Dummy cycles before read
-
uint32_t status_override
Override status register value during device mode configuration
-
uint32_t pinmux_group
The pinmux group selection
-
uint32_t dqs_pinmux_group
The DQS Pinmux Group Selection
-
uint32_t drive_strength
The Drive Strength of FlexSPI Pads
-
uint32_t flash_connection
Flash connection option: 0 - Single Flash connected to port A, 1 - Parallel mode, 2 - Single Flash connected to Port B
-
struct _serial_nor_config_option B
-
uint32_t U
-
union _serial_nor_config_option option1
-
uint8_t seqNum
Sequence Number, valid number: 1-16
-
uint8_t seqId
Sequence Index, valid number: 0-15
-
uint16_t reserved
-
uint8_t time_100ps
Data valid time, in terms of 100ps
-
uint8_t delay_cells
Data valid time, in terms of delay cells
-
uint32_t tag
[0x000-0x003] Tag, fixed value 0x42464346UL
-
uint32_t version
[0x004-0x007] Version,[31:24] -‘V’, [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-
uint32_t reserved0
[0x008-0x00b] Reserved for future use
-
uint8_t readSampleClkSrc
[0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-
uint8_t csHoldTime
[0x00d-0x00d] Data hold time, default value: 3
-
uint8_t csSetupTime
[0x00e-0x00e] Date setup time, default value: 3
-
uint8_t columnAddressWidth
[0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet
-
uint8_t deviceModeCfgEnable
[0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-
uint8_t deviceModeType
[0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.
-
uint16_t waitTimeCfgCommands
[0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command
-
flexspi_lut_seq_t deviceModeSeq
[0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved
-
uint32_t deviceModeArg
[0x018-0x01b] Argument/Parameter for device configuration
-
uint8_t configCmdEnable
[0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-
uint8_t configModeType[3]
[0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-
flexspi_lut_seq_t configCmdSeqs[3]
[0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-
uint32_t reserved1
[0x02c-0x02f] Reserved for future use
-
uint32_t configCmdArgs[3]
[0x030-0x03b] Arguments/Parameters for device Configuration commands
-
uint32_t reserved2
[0x03c-0x03f] Reserved for future use
-
uint32_t controllerMiscOption
[0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details
-
uint8_t deviceType
[0x044-0x044] Device Type: See Flash Type Definition for more details
-
uint8_t sflashPadType
[0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-
uint8_t serialClkFreq
[0x046-0x046] Serial Flash Frequency, device specific definitions. See System Boot Chapter for more details
-
uint8_t lutCustomSeqEnable
[0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-
uint32_t reserved3[2]
[0x048-0x04f] Reserved for future use
-
uint32_t sflashA1Size
[0x050-0x053] Size of Flash connected to A1
-
uint32_t sflashA2Size
[0x054-0x057] Size of Flash connected to A2
-
uint32_t sflashB1Size
[0x058-0x05b] Size of Flash connected to B1
-
uint32_t sflashB2Size
[0x05c-0x05f] Size of Flash connected to B2
-
uint32_t csPadSettingOverride
[0x060-0x063] CS pad setting override value
-
uint32_t sclkPadSettingOverride
[0x064-0x067] SCK pad setting override value
-
uint32_t dataPadSettingOverride
[0x068-0x06b] data pad setting override value
-
uint32_t dqsPadSettingOverride
[0x06c-0x06f] DQS pad setting override value
-
uint32_t timeoutInMs
[0x070-0x073] Timeout threshold for read status command
-
uint32_t commandInterval
[0x074-0x077] CS deselect interval between two commands
-
flexspi_dll_time_t dataValidTime[2]
[0x078-0x07b] CLK edge to data valid time for PORT A and PORT B
-
uint16_t busyOffset
[0x07c-0x07d] Busy offset, valid value: 0-31
-
uint16_t busyBitPolarity
[0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy
-
uint32_t lookupTable[64]
[0x080-0x17f] Lookup table holds Flash command sequences
-
flexspi_lut_seq_t lutCustomSeq[12]
[0x180-0x1af] Customizable LUT Sequences
-
uint32_t reserved4[4]
[0x1b0-0x1bf] Reserved for future use
-
flexspi_mem_config_t memConfig
Common memory configuration info via FLEXSPI
-
uint32_t pageSize
Page size of Serial NOR
-
uint32_t sectorSize
Sector size of Serial NOR
-
uint8_t ipcmdSerialClkFreq
Clock frequency for IP command
-
uint8_t isUniformBlockSize
Sector/Block size is the same
-
uint8_t isDataOrderSwapped
Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)
-
uint8_t reserved0[1]
Reserved for future use
-
uint8_t serialNorType
Serial NOR Flash type: 0/1/2/3
-
uint8_t needExitNoCmdMode
Need to exit NoCmd mode before other IP command
-
uint8_t halfClkForNonReadCmd
Half the Serial Clock for non-read command: true/false
-
uint8_t needRestoreNoCmdMode
Need to Restore NoCmd mode after IP command execution
-
uint32_t blockSize
Block size
-
uint32_t reserve2[11]
Reserved for future use
-
flexspi_operation_t operation
FLEXSPI operation
-
uint32_t baseAddress
FLEXSPI operation base address
-
uint32_t seqId
Sequence Id
-
uint32_t seqNum
Sequence Number
-
bool isParallelModeEnable
Is a parallel transfer
-
uint32_t *txBuffer
Tx buffer
-
uint32_t txSize
Tx size in bytes
-
uint32_t *rxBuffer
Rx buffer
-
uint32_t rxSize
Rx size in bytes
-
FSL_ROM_ROMAPI_VERSION
ROM API version 1.1.2.
-
FSL_ROM_FLEXSPINOR_DRIVER_VERSION
ROM FLEXSPI NOR driver version 1.7.0.
-
struct _serial_nor_config_option
- #include <fsl_romapi.h>
Serial NOR Configuration Option.
-
struct _flexspi_lut_seq
- #include <fsl_romapi.h>
FLEXSPI LUT Sequence structure.
-
struct flexspi_dll_time_t
- #include <fsl_romapi.h>
FLEXSPI DLL time.
-
struct _flexspi_mem_config
- #include <fsl_romapi.h>
FLEXSPI Memory Configuration Block.
-
struct _flexspi_nor_config
- #include <fsl_romapi.h>
Serial NOR configuration block.
-
struct _flexspi_xfer
- #include <fsl_romapi.h>
FLEXSPI Transfer Context.
-
union option0
-
struct B
Public Members
-
uint32_t max_freq
Maximum supported Frequency
-
uint32_t misc_mode
miscellaneous mode
-
uint32_t quad_mode_setting
Quad mode setting
-
uint32_t cmd_pads
Command pads
-
uint32_t query_pads
SFDP read pads
-
uint32_t device_type
Device type
-
uint32_t option_size
Option size, in terms of uint32_t, size = (option_size + 1) * 4
-
uint32_t tag
Tag, must be 0x0E
-
uint32_t max_freq
-
union option1
-
struct B
Public Members
-
uint32_t dummy_cycles
Dummy cycles before read
-
uint32_t status_override
Override status register value during device mode configuration
-
uint32_t pinmux_group
The pinmux group selection
-
uint32_t dqs_pinmux_group
The DQS Pinmux Group Selection
-
uint32_t drive_strength
The Drive Strength of FlexSPI Pads
-
uint32_t flash_connection
Flash connection option: 0 - Single Flash connected to port A, 1 - Parallel mode, 2 - Single Flash connected to Port B
-
uint32_t dummy_cycles
RTWDOG: 32-bit Watchdog Timer
-
void RTWDOG_GetDefaultConfig(rtwdog_config_t *config)
Initializes the RTWDOG configuration structure.
This function initializes the RTWDOG configuration structure to default values. The default values are:
rtwdogConfig->enableRtwdog = true; rtwdogConfig->clockSource = kRTWDOG_ClockSource1; rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; rtwdogConfig->workMode.enableWait = true; rtwdogConfig->workMode.enableStop = false; rtwdogConfig->workMode.enableDebug = false; rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; rtwdogConfig->enableUpdate = true; rtwdogConfig->enableInterrupt = false; rtwdogConfig->enableWindowMode = false; rtwdogConfig->windowValue = 0U; rtwdogConfig->timeoutValue = 0xFFFFU;
See also
rtwdog_config_t
- Parameters:
config – Pointer to the RTWDOG configuration structure.
- AT_QUICKACCESS_SECTION_CODE (void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config))
Initializes the RTWDOG module.
This function initializes the RTWDOG. To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true in the configuration.
Example:
rtwdog_config_t config; RTWDOG_GetDefaultConfig(&config); config.timeoutValue = 0x7ffU; config.enableUpdate = true; RTWDOG_Init(wdog_base,&config);
- Parameters:
base – RTWDOG peripheral base address.
config – The configuration of the RTWDOG.
-
void RTWDOG_Deinit(RTWDOG_Type *base)
De-initializes the RTWDOG module.
This function shuts down the RTWDOG. Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.
- Parameters:
base – RTWDOG peripheral base address.
-
static inline void RTWDOG_Enable(RTWDOG_Type *base)
Enables the RTWDOG module.
This function writes a value into the WDOG_CS register to enable the RTWDOG. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address.
-
static inline void RTWDOG_Disable(RTWDOG_Type *base)
Disables the RTWDOG module.
This function writes a value into the WDOG_CS register to disable the RTWDOG. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address
-
static inline void RTWDOG_EnableInterrupts(RTWDOG_Type *base, uint32_t mask)
Enables the RTWDOG interrupt.
This function writes a value into the WDOG_CS register to enable the RTWDOG interrupt. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address.
mask – The interrupts to enable. The parameter can be a combination of the following source if defined:
kRTWDOG_InterruptEnable
-
static inline void RTWDOG_DisableInterrupts(RTWDOG_Type *base, uint32_t mask)
Disables the RTWDOG interrupt.
This function writes a value into the WDOG_CS register to disable the RTWDOG interrupt. The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address.
mask – The interrupts to disabled. The parameter can be a combination of the following source if defined:
kRTWDOG_InterruptEnable
-
static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base)
Gets the RTWDOG all status flags.
This function gets all status flags.
Example to get the running flag:
uint32_t status; status = RTWDOG_GetStatusFlags(wdog_base) & kRTWDOG_RunningFlag;
See also
_rtwdog_status_flags_t
true: related status flag has been set.
false: related status flag is not set.
- Parameters:
base – RTWDOG peripheral base address
- Returns:
State of the status flag: asserted (true) or not-asserted (false).
-
static inline void RTWDOG_EnableWindowMode(RTWDOG_Type *base, bool enable)
Enables/disables the window mode.
- Parameters:
base – RTWDOG peripheral base address.
enable – Enables(true) or disables(false) the feature.
-
static inline uint32_t RTWDOG_CountToMesec(RTWDOG_Type *base, uint32_t count, uint32_t clockFreqInHz)
Converts raw count value to millisecond.
Note that if the clock frequency is too high the timeout period can be less than 1 ms. In this case this api will return 0 value.
- Parameters:
base – RTWDOG peripheral base address.
count – Raw count value.
clockFreqInHz – The frequency of the clock source RTWDOG uses.
- Returns:
Return converted time. Will return 0 if result is larger than 0xFFFFFFFF.
-
void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask)
Clears the RTWDOG flag.
This function clears the RTWDOG status flag.
Example to clear an interrupt flag:
RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag);
- Parameters:
base – RTWDOG peripheral base address.
mask – The status flags to clear. The parameter can be any combination of the following values:
kRTWDOG_InterruptFlag
-
static inline void RTWDOG_SetTimeoutValue(RTWDOG_Type *base, uint16_t timeoutCount)
Sets the RTWDOG timeout value.
This function writes a timeout value into the WDOG_TOVAL register. The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address
timeoutCount – RTWDOG timeout value, count of RTWDOG clock ticks.
-
static inline void RTWDOG_SetWindowValue(RTWDOG_Type *base, uint16_t windowValue)
Sets the RTWDOG window value.
This function writes a window value into the WDOG_WIN register. The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.
- Parameters:
base – RTWDOG peripheral base address.
windowValue – RTWDOG window value.
- __STATIC_FORCEINLINE void RTWDOG_Unlock (RTWDOG_Type *base)
Unlocks the RTWDOG register written.
This function unlocks the RTWDOG register written.
Before starting the unlock sequence and following the configuration, disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. After the configuration finishes, re-enable the global interrupts.
- Parameters:
base – RTWDOG peripheral base address
-
static inline void RTWDOG_Refresh(RTWDOG_Type *base)
Refreshes the RTWDOG timer.
This function feeds the RTWDOG. This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted.
- Parameters:
base – RTWDOG peripheral base address
-
static inline uint32_t RTWDOG_GetCounterValue(RTWDOG_Type *base)
Gets the RTWDOG counter value.
This function gets the RTWDOG counter value.
- Parameters:
base – RTWDOG peripheral base address.
- Returns:
Current RTWDOG counter value.
-
WDOG_FIRST_WORD_OF_UNLOCK
First word of unlock sequence
-
WDOG_SECOND_WORD_OF_UNLOCK
Second word of unlock sequence
-
WDOG_FIRST_WORD_OF_REFRESH
First word of refresh sequence
-
WDOG_SECOND_WORD_OF_REFRESH
Second word of refresh sequence
-
FSL_RTWDOG_DRIVER_VERSION
RTWDOG driver version.
-
enum _rtwdog_clock_source
Describes RTWDOG clock source.
Values:
-
enumerator kRTWDOG_ClockSource0
Clock source 0
-
enumerator kRTWDOG_ClockSource1
Clock source 1
-
enumerator kRTWDOG_ClockSource2
Clock source 2
-
enumerator kRTWDOG_ClockSource3
Clock source 3
-
enumerator kRTWDOG_ClockSource0
-
enum _rtwdog_clock_prescaler
Describes the selection of the clock prescaler.
Values:
-
enumerator kRTWDOG_ClockPrescalerDivide1
Divided by 1
-
enumerator kRTWDOG_ClockPrescalerDivide256
Divided by 256
-
enumerator kRTWDOG_ClockPrescalerDivide1
-
enum _rtwdog_test_mode
Describes RTWDOG test mode.
Values:
-
enumerator kRTWDOG_TestModeDisabled
Test Mode disabled
-
enumerator kRTWDOG_UserModeEnabled
User Mode enabled
-
enumerator kRTWDOG_LowByteTest
Test Mode enabled, only low byte is used
-
enumerator kRTWDOG_HighByteTest
Test Mode enabled, only high byte is used
-
enumerator kRTWDOG_TestModeDisabled
-
enum _rtwdog_interrupt_enable_t
RTWDOG interrupt configuration structure.
This structure contains the settings for all of the RTWDOG interrupt configurations.
Values:
-
enumerator kRTWDOG_InterruptEnable
Interrupt is generated before forcing a reset
-
enumerator kRTWDOG_InterruptEnable
-
enum _rtwdog_status_flags_t
RTWDOG status flags.
This structure contains the RTWDOG status flags for use in the RTWDOG functions.
Values:
-
enumerator kRTWDOG_RunningFlag
Running flag, set when RTWDOG is enabled
-
enumerator kRTWDOG_InterruptFlag
Interrupt flag, set when interrupt occurs
-
enumerator kRTWDOG_RunningFlag
-
typedef enum _rtwdog_clock_source rtwdog_clock_source_t
Describes RTWDOG clock source.
-
typedef enum _rtwdog_clock_prescaler rtwdog_clock_prescaler_t
Describes the selection of the clock prescaler.
-
typedef struct _rtwdog_work_mode rtwdog_work_mode_t
Defines RTWDOG work mode.
-
typedef enum _rtwdog_test_mode rtwdog_test_mode_t
Describes RTWDOG test mode.
-
typedef struct _rtwdog_config rtwdog_config_t
Describes RTWDOG configuration structure.
-
struct _rtwdog_work_mode
- #include <fsl_rtwdog.h>
Defines RTWDOG work mode.
Public Members
-
bool enableWait
Enables or disables RTWDOG in wait mode
-
bool enableStop
Enables or disables RTWDOG in stop mode
-
bool enableDebug
Enables or disables RTWDOG in debug mode
-
bool enableWait
-
struct _rtwdog_config
- #include <fsl_rtwdog.h>
Describes RTWDOG configuration structure.
Public Members
-
bool enableRtwdog
Enables or disables RTWDOG
-
rtwdog_clock_source_t clockSource
Clock source select
-
rtwdog_clock_prescaler_t prescaler
Clock prescaler value
-
rtwdog_work_mode_t workMode
Configures RTWDOG work mode in debug stop and wait mode
-
rtwdog_test_mode_t testMode
Configures RTWDOG test mode
-
bool enableUpdate
Update write-once register enable
-
bool enableInterrupt
Enables or disables RTWDOG interrupt
-
bool enableWindowMode
Enables or disables RTWDOG window mode
-
uint16_t windowValue
Window value
-
uint16_t timeoutValue
Timeout value
-
bool enableRtwdog
S3MU: Sentinel
-
FSL_S3MU_DRIVER_VERSION
Defines S3MU driver version 2.0.1.
Change log:
Version 2.0.1
Update kStatusGroup_SNT to kStatusGroup_ELEMU
Version 2.0.0
initial version
Values:
-
enumerator kStatus_S3MU_AgumentOutOfRange
S3MU status for out of range access.
-
enumerator kStatus_S3MU_InvalidArgument
S3MU status for invalid argument check.
-
enumerator kStatus_S3MU_RequestTimeout
S3MU status for timeout.
-
enumerator kStatus_S3MU_Busy
S3MU status for reservation by other core.
-
enumerator kStatus_S3MU_AgumentOutOfRange
-
status_t S3MU_SendMessage(S3MU_Type *mu, void *buf, size_t wordCount)
Send message to MU.
This function writes messgae into MU regsters and send message to EdgeLock Enclave.
- Parameters:
base – MU peripheral base address
buf – buffer to store read data
wordCount – size of data in words
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t S3MU_GetResponse(S3MU_Type *mu, void *buf)
Get response from MU.
This function reads response data from EdgeLock Enclave if available.
Note: number of read response word is obtained by header, so user need to prepare buffer with enough space for expected response
- Parameters:
base – MU peripheral base address
buf – buffer to store read data
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t S3MU_WaitForData(S3MU_Type *mu, uint32_t *buf, size_t wordCount, uint32_t wait)
Wait and Read data from MU.
This function waits limited time (ticks) and tests if data are ready to be read. When data are ready, reads them into buffer, timeout otherwise.
- Parameters:
base – MU peripheral base address
buf – buffer to store read data
wordCount – size of data in words
wait – number of iterations to wait
- Returns:
Status kStatus_Success if success, kStatus_S3MU_RequestTimeout if timeout Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
status_t S3MU_ReadMessage(S3MU_Type *mu, uint32_t *buf, size_t *size, uint8_t read_header)
Read message from MU.
This function reads message date from EdgeLock Enclave if available.
- Parameters:
base – MU peripheral base address
buf – buffer to store read data
size – lenght of data in words. If read_header equal MU_READ_HEADER, size is read from response header.
read_header – specifies if size is obtained by response header or provided in parameter.
- Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange
-
void S3MU_Init(S3MU_Type *mu)
Init MU.
This function does nothing. MU is initialized after leaving ROM.
- Parameters:
base – MU peripheral base address
-
uint32_t S3MU_ComputeMsgCrc(uint32_t *msg, uint32_t msg_len)
Computes CRC.
This function computes CRC of input message.
- Parameters:
msg – pointer to message
msg_len – size of message in words
- Returns:
CRC32 checksum value
-
MU_MSG_HEADER_SIZE
-
MESSAGING_TAG_COMMAND
-
MESSAGING_TAG_REPLY
-
struct mu_hdr_t
- #include <fsl_s3mu.h>
-
union __unnamed225__
-
struct hdr_byte
SAI: Serial Audio Interface
SAI Driver
-
void SAI_Init(I2S_Type *base)
Initializes the SAI peripheral.
This API gates the SAI clock. The SAI module can’t operate unless SAI_Init is called to enable the clock.
- Parameters:
base – SAI base pointer.
-
void SAI_Deinit(I2S_Type *base)
De-initializes the SAI peripheral.
This API gates the SAI clock. The SAI module can’t operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.
- Parameters:
base – SAI base pointer.
-
void SAI_TxReset(I2S_Type *base)
Resets the SAI Tx.
This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.
- Parameters:
base – SAI base pointer
-
void SAI_RxReset(I2S_Type *base)
Resets the SAI Rx.
This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.
- Parameters:
base – SAI base pointer
-
void SAI_TxEnable(I2S_Type *base, bool enable)
Enables/disables the SAI Tx.
- Parameters:
base – SAI base pointer.
enable – True means enable SAI Tx, false means disable.
-
void SAI_RxEnable(I2S_Type *base, bool enable)
Enables/disables the SAI Rx.
- Parameters:
base – SAI base pointer.
enable – True means enable SAI Rx, false means disable.
-
static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
Set Rx bit clock direction.
Select bit clock direction, master or slave.
- Parameters:
base – SAI base pointer.
masterSlave – reference sai_master_slave_t.
-
static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
Set Rx bit clock direction.
Select bit clock direction, master or slave.
- Parameters:
base – SAI base pointer.
masterSlave – reference sai_master_slave_t.
-
static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
Set Rx frame sync direction.
Select frame sync direction, master or slave.
- Parameters:
base – SAI base pointer.
masterSlave – reference sai_master_slave_t.
-
static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
Set Tx frame sync direction.
Select frame sync direction, master or slave.
- Parameters:
base – SAI base pointer.
masterSlave – reference sai_master_slave_t.
-
void SAI_TxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
Transmitter bit clock rate configurations.
- Parameters:
base – SAI base pointer.
sourceClockHz – Bit clock source frequency.
sampleRate – Audio data sample rate.
bitWidth – Audio data bitWidth.
channelNumbers – Audio channel numbers.
-
void SAI_RxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
Receiver bit clock rate configurations.
- Parameters:
base – SAI base pointer.
sourceClockHz – Bit clock source frequency.
sampleRate – Audio data sample rate.
bitWidth – Audio data bitWidth.
channelNumbers – Audio channel numbers.
-
void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
Transmitter Bit clock configurations.
- Parameters:
base – SAI base pointer.
masterSlave – master or slave.
config – bit clock other configurations, can be NULL in slave mode.
-
void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
Receiver Bit clock configurations.
- Parameters:
base – SAI base pointer.
masterSlave – master or slave.
config – bit clock other configurations, can be NULL in slave mode.
-
void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)
Master clock configurations.
- Parameters:
base – SAI base pointer.
config – master clock configurations.
-
void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
SAI transmitter fifo configurations.
- Parameters:
base – SAI base pointer.
config – fifo configurations.
-
void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
SAI receiver fifo configurations.
- Parameters:
base – SAI base pointer.
config – fifo configurations.
-
void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
SAI transmitter Frame sync configurations.
- Parameters:
base – SAI base pointer.
masterSlave – master or slave.
config – frame sync configurations, can be NULL in slave mode.
-
void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
SAI receiver Frame sync configurations.
- Parameters:
base – SAI base pointer.
masterSlave – master or slave.
config – frame sync configurations, can be NULL in slave mode.
-
void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
SAI transmitter Serial data configurations.
- Parameters:
base – SAI base pointer.
config – serial data configurations.
-
void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
SAI receiver Serial data configurations.
- Parameters:
base – SAI base pointer.
config – serial data configurations.
-
void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)
SAI transmitter configurations.
- Parameters:
base – SAI base pointer.
config – transmitter configurations.
-
void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)
SAI receiver configurations.
- Parameters:
base – SAI base pointer.
config – receiver configurations.
-
void SAI_GetClassicI2SConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
Get classic I2S mode configurations.
- Parameters:
config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.
-
void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
Get left justified mode configurations.
- Parameters:
config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.
-
void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
Get right justified mode configurations.
- Parameters:
config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.
-
void SAI_GetTDMConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)
Get TDM mode configurations.
- Parameters:
config – transceiver configurations.
frameSyncWidth – length of frame sync.
bitWidth – audio data word width.
dataWordNum – word number in one frame.
saiChannelMask – mask value of the channel to be enable.
-
void SAI_GetDSPConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)
Get DSP mode configurations.
DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) SAI_TxSetConfig(base, config)
Note
DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) config->frameSync.frameSyncEarly = true; SAI_TxSetConfig(base, config)
- Parameters:
config – transceiver configurations.
frameSyncWidth – length of frame sync.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to enable.
-
static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)
Gets the SAI Tx status flag state.
- Parameters:
base – SAI base pointer
- Returns:
SAI Tx status flag value. Use the Status Mask to get the status value needed.
-
static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)
Clears the SAI Tx status flag state.
- Parameters:
base – SAI base pointer
mask – State mask. It can be a combination of the following source if defined:
kSAI_WordStartFlag
kSAI_SyncErrorFlag
kSAI_FIFOErrorFlag
-
static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)
Gets the SAI Tx status flag state.
- Parameters:
base – SAI base pointer
- Returns:
SAI Rx status flag value. Use the Status Mask to get the status value needed.
-
static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
Clears the SAI Rx status flag state.
- Parameters:
base – SAI base pointer
mask – State mask. It can be a combination of the following sources if defined.
kSAI_WordStartFlag
kSAI_SyncErrorFlag
kSAI_FIFOErrorFlag
-
void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
Do software reset or FIFO reset .
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.
- Parameters:
base – SAI base pointer
resetType – Reset type, FIFO reset or software reset
-
void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
Do software reset or FIFO reset .
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.
- Parameters:
base – SAI base pointer
resetType – Reset type, FIFO reset or software reset
-
void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
Set the Tx channel FIFO enable mask.
- Parameters:
base – SAI base pointer
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.
-
void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
Set the Rx channel FIFO enable mask.
- Parameters:
base – SAI base pointer
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.
-
void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)
Set the Tx data order.
- Parameters:
base – SAI base pointer
order – Data order MSB or LSB
-
void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)
Set the Rx data order.
- Parameters:
base – SAI base pointer
order – Data order MSB or LSB
-
void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
Set the Tx data order.
- Parameters:
base – SAI base pointer
polarity –
-
void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
Set the Rx data order.
- Parameters:
base – SAI base pointer
polarity –
-
void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
Set the Tx data order.
- Parameters:
base – SAI base pointer
polarity –
-
void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
Set the Rx data order.
- Parameters:
base – SAI base pointer
polarity –
-
void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
Set Tx FIFO packing feature.
- Parameters:
base – SAI base pointer.
pack – FIFO pack type. It is element of sai_fifo_packing_t.
-
void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
Set Rx FIFO packing feature.
- Parameters:
base – SAI base pointer.
pack – FIFO pack type. It is element of sai_fifo_packing_t.
-
static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
Set Tx FIFO error continue.
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
- Parameters:
base – SAI base pointer.
isEnabled – Is FIFO error continue enabled, true means enable, false means disable.
-
static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
Set Rx FIFO error continue.
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
- Parameters:
base – SAI base pointer.
isEnabled – Is FIFO error continue enabled, true means enable, false means disable.
-
static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)
Enables the SAI Tx interrupt requests.
- Parameters:
base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSAI_WordStartInterruptEnable
kSAI_SyncErrorInterruptEnable
kSAI_FIFOWarningInterruptEnable
kSAI_FIFORequestInterruptEnable
kSAI_FIFOErrorInterruptEnable
-
static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)
Enables the SAI Rx interrupt requests.
- Parameters:
base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSAI_WordStartInterruptEnable
kSAI_SyncErrorInterruptEnable
kSAI_FIFOWarningInterruptEnable
kSAI_FIFORequestInterruptEnable
kSAI_FIFOErrorInterruptEnable
-
static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)
Disables the SAI Tx interrupt requests.
- Parameters:
base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSAI_WordStartInterruptEnable
kSAI_SyncErrorInterruptEnable
kSAI_FIFOWarningInterruptEnable
kSAI_FIFORequestInterruptEnable
kSAI_FIFOErrorInterruptEnable
-
static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)
Disables the SAI Rx interrupt requests.
- Parameters:
base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSAI_WordStartInterruptEnable
kSAI_SyncErrorInterruptEnable
kSAI_FIFOWarningInterruptEnable
kSAI_FIFORequestInterruptEnable
kSAI_FIFOErrorInterruptEnable
-
static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
Enables/disables the SAI Tx DMA requests.
- Parameters:
base – SAI base pointer
mask – DMA source The parameter can be combination of the following sources if defined.
kSAI_FIFOWarningDMAEnable
kSAI_FIFORequestDMAEnable
enable – True means enable DMA, false means disable DMA.
-
static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
Enables/disables the SAI Rx DMA requests.
- Parameters:
base – SAI base pointer
mask – DMA source The parameter can be a combination of the following sources if defined.
kSAI_FIFOWarningDMAEnable
kSAI_FIFORequestDMAEnable
enable – True means enable DMA, false means disable DMA.
-
static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
Gets the SAI Tx data register address.
This API is used to provide a transfer address for the SAI DMA transfer configuration.
- Parameters:
base – SAI base pointer.
channel – Which data channel used.
- Returns:
data register address.
-
static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
Gets the SAI Rx data register address.
This API is used to provide a transfer address for the SAI DMA transfer configuration.
- Parameters:
base – SAI base pointer.
channel – Which data channel used.
- Returns:
data register address.
-
void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
Sends data using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be written.
size – Bytes to be written.
-
void SAI_WriteMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
Sends data to multi channel using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
channelMask – channel mask.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be written.
size – Bytes to be written.
-
static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)
Writes data into SAI FIFO.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
data – Data needs to be written.
-
void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
Receives data using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be read.
size – Bytes to be read.
-
void SAI_ReadMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
Receives multi channel data using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
channelMask – channel mask.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be read.
size – Bytes to be read.
-
static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)
Reads data from the SAI FIFO.
- Parameters:
base – SAI base pointer.
channel – Data channel used.
- Returns:
Data in SAI FIFO.
-
void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
Initializes the SAI Tx handle.
This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – SAI base pointer
handle – SAI handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function
-
void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
Initializes the SAI Rx handle.
This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – SAI base pointer.
handle – SAI handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function.
-
void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
SAI transmitter transfer configurations.
This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.
- Parameters:
base – SAI base pointer.
handle – SAI handle pointer.
config – tranmitter configurations.
-
void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
SAI receiver transfer configurations.
This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.
- Parameters:
base – SAI base pointer.
handle – SAI handle pointer.
config – receiver configurations.
-
status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
Performs an interrupt non-blocking send transfer on SAI.
Note
This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
xfer – Pointer to the sai_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_SAI_TxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.
-
status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
Performs an interrupt non-blocking receive transfer on SAI.
Note
This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.
- Parameters:
base – SAI base pointer
handle – Pointer to the sai_handle_t structure which stores the transfer state.
xfer – Pointer to the sai_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_SAI_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.
-
status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
Gets a set byte count.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
count – Bytes count sent.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
Gets a received byte count.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
count – Bytes count received.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)
Aborts the current send.
Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
-
void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)
Aborts the current IRQ receive.
Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – SAI base pointer
handle – Pointer to the sai_handle_t structure which stores the transfer state.
-
void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)
Terminate all SAI send.
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
-
void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)
Terminate all SAI receive.
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
-
void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
Tx interrupt handler.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure.
-
void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
Tx interrupt handler.
- Parameters:
base – SAI base pointer.
handle – Pointer to the sai_handle_t structure.
-
FSL_SAI_DRIVER_VERSION
Version 2.4.4
_sai_status_t, SAI return status.
Values:
-
enumerator kStatus_SAI_TxBusy
SAI Tx is busy.
-
enumerator kStatus_SAI_RxBusy
SAI Rx is busy.
-
enumerator kStatus_SAI_TxError
SAI Tx FIFO error.
-
enumerator kStatus_SAI_RxError
SAI Rx FIFO error.
-
enumerator kStatus_SAI_QueueFull
SAI transfer queue is full.
-
enumerator kStatus_SAI_TxIdle
SAI Tx is idle
-
enumerator kStatus_SAI_RxIdle
SAI Rx is idle
-
enumerator kStatus_SAI_TxBusy
_sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific
Values:
-
enumerator kSAI_Channel0Mask
channel 0 mask value
-
enumerator kSAI_Channel1Mask
channel 1 mask value
-
enumerator kSAI_Channel2Mask
channel 2 mask value
-
enumerator kSAI_Channel3Mask
channel 3 mask value
-
enumerator kSAI_Channel4Mask
channel 4 mask value
-
enumerator kSAI_Channel5Mask
channel 5 mask value
-
enumerator kSAI_Channel6Mask
channel 6 mask value
-
enumerator kSAI_Channel7Mask
channel 7 mask value
-
enumerator kSAI_Channel0Mask
-
enum _sai_protocol
Define the SAI bus type.
Values:
-
enumerator kSAI_BusLeftJustified
Uses left justified format.
-
enumerator kSAI_BusRightJustified
Uses right justified format.
-
enumerator kSAI_BusI2S
Uses I2S format.
-
enumerator kSAI_BusPCMA
Uses I2S PCM A format.
-
enumerator kSAI_BusPCMB
Uses I2S PCM B format.
-
enumerator kSAI_BusLeftJustified
-
enum _sai_master_slave
Master or slave mode.
Values:
-
enumerator kSAI_Master
Master mode include bclk and frame sync
-
enumerator kSAI_Slave
Slave mode include bclk and frame sync
-
enumerator kSAI_Bclk_Master_FrameSync_Slave
bclk in master mode, frame sync in slave mode
-
enumerator kSAI_Bclk_Slave_FrameSync_Master
bclk in slave mode, frame sync in master mode
-
enumerator kSAI_Master
-
enum _sai_mono_stereo
Mono or stereo audio format.
Values:
-
enumerator kSAI_Stereo
Stereo sound.
-
enumerator kSAI_MonoRight
Only Right channel have sound.
-
enumerator kSAI_MonoLeft
Only left channel have sound.
-
enumerator kSAI_Stereo
-
enum _sai_data_order
SAI data order, MSB or LSB.
Values:
-
enumerator kSAI_DataLSB
LSB bit transferred first
-
enumerator kSAI_DataMSB
MSB bit transferred first
-
enumerator kSAI_DataLSB
-
enum _sai_clock_polarity
SAI clock polarity, active high or low.
Values:
-
enumerator kSAI_PolarityActiveHigh
Drive outputs on rising edge
-
enumerator kSAI_PolarityActiveLow
Drive outputs on falling edge
-
enumerator kSAI_SampleOnFallingEdge
Sample inputs on falling edge
-
enumerator kSAI_SampleOnRisingEdge
Sample inputs on rising edge
-
enumerator kSAI_PolarityActiveHigh
-
enum _sai_sync_mode
Synchronous or asynchronous mode.
Values:
-
enumerator kSAI_ModeAsync
Asynchronous mode
-
enumerator kSAI_ModeSync
Synchronous mode (with receiver or transmit)
-
enumerator kSAI_ModeSyncWithOtherTx
Synchronous with another SAI transmit
-
enumerator kSAI_ModeSyncWithOtherRx
Synchronous with another SAI receiver
-
enumerator kSAI_ModeAsync
-
enum _sai_bclk_source
Bit clock source.
Values:
-
enumerator kSAI_BclkSourceBusclk
Bit clock using bus clock
-
enumerator kSAI_BclkSourceMclkOption1
Bit clock MCLK option 1
-
enumerator kSAI_BclkSourceMclkOption2
Bit clock MCLK option2
-
enumerator kSAI_BclkSourceMclkOption3
Bit clock MCLK option3
-
enumerator kSAI_BclkSourceMclkDiv
Bit clock using master clock divider
-
enumerator kSAI_BclkSourceOtherSai0
Bit clock from other SAI device
-
enumerator kSAI_BclkSourceOtherSai1
Bit clock from other SAI device
-
enumerator kSAI_BclkSourceBusclk
_sai_interrupt_enable_t, The SAI interrupt enable flag
Values:
-
enumerator kSAI_WordStartInterruptEnable
Word start flag, means the first word in a frame detected
-
enumerator kSAI_SyncErrorInterruptEnable
Sync error flag, means the sync error is detected
-
enumerator kSAI_FIFOWarningInterruptEnable
FIFO warning flag, means the FIFO is empty
-
enumerator kSAI_FIFOErrorInterruptEnable
FIFO error flag
-
enumerator kSAI_FIFORequestInterruptEnable
FIFO request, means reached watermark
-
enumerator kSAI_WordStartInterruptEnable
_sai_dma_enable_t, The DMA request sources
Values:
-
enumerator kSAI_FIFOWarningDMAEnable
FIFO warning caused by the DMA request
-
enumerator kSAI_FIFORequestDMAEnable
FIFO request caused by the DMA request
-
enumerator kSAI_FIFOWarningDMAEnable
_sai_flags, The SAI status flag
Values:
-
enumerator kSAI_WordStartFlag
Word start flag, means the first word in a frame detected
-
enumerator kSAI_SyncErrorFlag
Sync error flag, means the sync error is detected
-
enumerator kSAI_FIFOErrorFlag
FIFO error flag
-
enumerator kSAI_FIFORequestFlag
FIFO request flag.
-
enumerator kSAI_FIFOWarningFlag
FIFO warning flag
-
enumerator kSAI_WordStartFlag
-
enum _sai_reset_type
The reset type.
Values:
-
enumerator kSAI_ResetTypeSoftware
Software reset, reset the logic state
-
enumerator kSAI_ResetTypeFIFO
FIFO reset, reset the FIFO read and write pointer
-
enumerator kSAI_ResetAll
All reset.
-
enumerator kSAI_ResetTypeSoftware
-
enum _sai_fifo_packing
The SAI packing mode The mode includes 8 bit and 16 bit packing.
Values:
-
enumerator kSAI_FifoPackingDisabled
Packing disabled
-
enumerator kSAI_FifoPacking8bit
8 bit packing enabled
-
enumerator kSAI_FifoPacking16bit
16bit packing enabled
-
enumerator kSAI_FifoPackingDisabled
-
enum _sai_sample_rate
Audio sample rate.
Values:
-
enumerator kSAI_SampleRate8KHz
Sample rate 8000 Hz
-
enumerator kSAI_SampleRate11025Hz
Sample rate 11025 Hz
-
enumerator kSAI_SampleRate12KHz
Sample rate 12000 Hz
-
enumerator kSAI_SampleRate16KHz
Sample rate 16000 Hz
-
enumerator kSAI_SampleRate22050Hz
Sample rate 22050 Hz
-
enumerator kSAI_SampleRate24KHz
Sample rate 24000 Hz
-
enumerator kSAI_SampleRate32KHz
Sample rate 32000 Hz
-
enumerator kSAI_SampleRate44100Hz
Sample rate 44100 Hz
-
enumerator kSAI_SampleRate48KHz
Sample rate 48000 Hz
-
enumerator kSAI_SampleRate96KHz
Sample rate 96000 Hz
-
enumerator kSAI_SampleRate192KHz
Sample rate 192000 Hz
-
enumerator kSAI_SampleRate384KHz
Sample rate 384000 Hz
-
enumerator kSAI_SampleRate8KHz
-
enum _sai_word_width
Audio word width.
Values:
-
enumerator kSAI_WordWidth8bits
Audio data width 8 bits
-
enumerator kSAI_WordWidth16bits
Audio data width 16 bits
-
enumerator kSAI_WordWidth24bits
Audio data width 24 bits
-
enumerator kSAI_WordWidth32bits
Audio data width 32 bits
-
enumerator kSAI_WordWidth8bits
-
enum _sai_data_pin_state
sai data pin state definition
Values:
-
enumerator kSAI_DataPinStateTriState
transmit data pins are tri-stated when slots are masked or channels are disabled
-
enumerator kSAI_DataPinStateOutputZero
transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled
-
enumerator kSAI_DataPinStateTriState
-
enum _sai_fifo_combine
sai fifo combine mode definition
Values:
-
enumerator kSAI_FifoCombineDisabled
sai TX/RX fifo combine mode disabled
-
enumerator kSAI_FifoCombineModeEnabledOnRead
sai TX fifo combine mode enabled on FIFO reads
-
enumerator kSAI_FifoCombineModeEnabledOnWrite
sai TX fifo combine mode enabled on FIFO write
-
enumerator kSAI_RxFifoCombineModeEnabledOnWrite
sai RX fifo combine mode enabled on FIFO write
-
enumerator kSAI_RXFifoCombineModeEnabledOnRead
sai RX fifo combine mode enabled on FIFO reads
-
enumerator kSAI_FifoCombineModeEnabledOnReadWrite
sai TX/RX fifo combined mode enabled on FIFO read/writes
-
enumerator kSAI_FifoCombineDisabled
-
enum _sai_transceiver_type
sai transceiver type
Values:
-
enumerator kSAI_Transmitter
sai transmitter
-
enumerator kSAI_Receiver
sai receiver
-
enumerator kSAI_Transmitter
-
enum _sai_frame_sync_len
sai frame sync len
Values:
-
enumerator kSAI_FrameSyncLenOneBitClk
1 bit clock frame sync len for DSP mode
-
enumerator kSAI_FrameSyncLenPerWordWidth
Frame sync length decided by word width
-
enumerator kSAI_FrameSyncLenOneBitClk
-
typedef enum _sai_protocol sai_protocol_t
Define the SAI bus type.
-
typedef enum _sai_master_slave sai_master_slave_t
Master or slave mode.
-
typedef enum _sai_mono_stereo sai_mono_stereo_t
Mono or stereo audio format.
-
typedef enum _sai_data_order sai_data_order_t
SAI data order, MSB or LSB.
-
typedef enum _sai_clock_polarity sai_clock_polarity_t
SAI clock polarity, active high or low.
-
typedef enum _sai_sync_mode sai_sync_mode_t
Synchronous or asynchronous mode.
-
typedef enum _sai_bclk_source sai_bclk_source_t
Bit clock source.
-
typedef enum _sai_reset_type sai_reset_type_t
The reset type.
-
typedef enum _sai_fifo_packing sai_fifo_packing_t
The SAI packing mode The mode includes 8 bit and 16 bit packing.
-
typedef struct _sai_config sai_config_t
SAI user configuration structure.
-
typedef enum _sai_sample_rate sai_sample_rate_t
Audio sample rate.
-
typedef enum _sai_word_width sai_word_width_t
Audio word width.
-
typedef enum _sai_data_pin_state sai_data_pin_state_t
sai data pin state definition
-
typedef enum _sai_fifo_combine sai_fifo_combine_t
sai fifo combine mode definition
-
typedef enum _sai_transceiver_type sai_transceiver_type_t
sai transceiver type
-
typedef enum _sai_frame_sync_len sai_frame_sync_len_t
sai frame sync len
-
typedef struct _sai_transfer_format sai_transfer_format_t
sai transfer format
-
typedef struct _sai_master_clock sai_master_clock_t
master clock configurations
-
typedef struct _sai_fifo sai_fifo_t
sai fifo configurations
-
typedef struct _sai_bit_clock sai_bit_clock_t
sai bit clock configurations
-
typedef struct _sai_frame_sync sai_frame_sync_t
sai frame sync configurations
-
typedef struct _sai_serial_data sai_serial_data_t
sai serial data configurations
-
typedef struct _sai_transceiver sai_transceiver_t
sai transceiver configurations
-
typedef struct _sai_transfer sai_transfer_t
SAI transfer structure.
-
typedef struct _sai_handle sai_handle_t
-
typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData)
SAI transfer callback prototype.
-
SAI_XFER_QUEUE_SIZE
SAI transfer queue size, user can refine it according to use case.
-
FSL_SAI_HAS_FIFO_EXTEND_FEATURE
sai fifo feature
-
struct _sai_config
- #include <fsl_sai.h>
SAI user configuration structure.
Public Members
-
sai_protocol_t protocol
Audio bus protocol in SAI
-
sai_sync_mode_t syncMode
SAI sync mode, control Tx/Rx clock sync
-
bool mclkOutputEnable
Master clock output enable, true means master clock divider enabled
-
sai_bclk_source_t bclkSource
Bit Clock source
-
sai_master_slave_t masterSlave
Master or slave
-
sai_protocol_t protocol
-
struct _sai_transfer_format
- #include <fsl_sai.h>
sai transfer format
Public Members
-
uint32_t sampleRate_Hz
Sample rate of audio data
-
uint32_t bitWidth
Data length of audio data, usually 8/16/24/32 bits
-
sai_mono_stereo_t stereo
Mono or stereo
-
uint32_t masterClockHz
Master clock frequency in Hz
-
uint8_t watermark
Watermark value
-
uint8_t channel
Transfer start channel
-
uint8_t channelMask
enabled channel mask value, reference _sai_channel_mask
-
uint8_t endChannel
end channel number
-
uint8_t channelNums
Total enabled channel numbers
-
sai_protocol_t protocol
Which audio protocol used
-
bool isFrameSyncCompact
True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock.
-
uint32_t sampleRate_Hz
-
struct _sai_master_clock
- #include <fsl_sai.h>
master clock configurations
Public Members
-
bool mclkOutputEnable
master clock output enable
-
uint32_t mclkHz
target mclk frequency
-
uint32_t mclkSourceClkHz
mclk source frequency
-
bool mclkOutputEnable
-
struct _sai_fifo
- #include <fsl_sai.h>
sai fifo configurations
Public Members
-
bool fifoContinueOneError
fifo continues when error occur
-
sai_fifo_combine_t fifoCombine
fifo combine mode
-
sai_fifo_packing_t fifoPacking
fifo packing mode
-
uint8_t fifoWatermark
fifo watermark
-
bool fifoContinueOneError
-
struct _sai_bit_clock
- #include <fsl_sai.h>
sai bit clock configurations
Public Members
-
bool bclkSrcSwap
bit clock source swap
-
bool bclkInputDelay
bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time .
-
sai_clock_polarity_t bclkPolarity
bit clock polarity
-
sai_bclk_source_t bclkSource
bit Clock source
-
bool bclkSrcSwap
-
struct _sai_frame_sync
- #include <fsl_sai.h>
sai frame sync configurations
Public Members
-
uint8_t frameSyncWidth
frame sync width in number of bit clocks
-
bool frameSyncEarly
TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame
-
bool frameSyncGenerateOnDemand
internal frame sync is generated when FIFO waring flag is clear
-
sai_clock_polarity_t frameSyncPolarity
frame sync polarity
-
uint8_t frameSyncWidth
-
struct _sai_serial_data
- #include <fsl_sai.h>
sai serial data configurations
Public Members
-
sai_data_pin_state_t dataMode
sai data pin state when slots masked or channel disabled
-
sai_data_order_t dataOrder
configure whether the LSB or MSB is transmitted first
-
uint8_t dataWord0Length
configure the number of bits in the first word in each frame
-
uint8_t dataWordNLength
configure the number of bits in the each word in each frame, except the first word
-
uint8_t dataWordLength
used to record the data length for dma transfer
-
uint8_t dataFirstBitShifted
Configure the bit index for the first bit transmitted for each word in the frame
-
uint8_t dataWordNum
configure the number of words in each frame
-
uint32_t dataMaskedWord
configure whether the transmit word is masked
-
sai_data_pin_state_t dataMode
-
struct _sai_transceiver
- #include <fsl_sai.h>
sai transceiver configurations
Public Members
-
sai_serial_data_t serialData
serial data configurations
-
sai_frame_sync_t frameSync
ws configurations
-
sai_bit_clock_t bitClock
bit clock configurations
-
sai_fifo_t fifo
fifo configurations
-
sai_master_slave_t masterSlave
transceiver is master or slave
-
sai_sync_mode_t syncMode
transceiver sync mode
-
uint8_t startChannel
Transfer start channel
-
uint8_t channelMask
enabled channel mask value, reference _sai_channel_mask
-
uint8_t endChannel
end channel number
-
uint8_t channelNums
Total enabled channel numbers
-
sai_serial_data_t serialData
-
struct _sai_transfer
- #include <fsl_sai.h>
SAI transfer structure.
Public Members
-
uint8_t *data
Data start address to transfer.
-
size_t dataSize
Transfer size.
-
uint8_t *data
-
struct _sai_handle
- #include <fsl_sai.h>
SAI handle structure.
Public Members
-
I2S_Type *base
base address
-
uint32_t state
Transfer status
-
sai_transfer_callback_t callback
Callback function called at transfer event
-
void *userData
Callback parameter passed to callback function
-
uint8_t bitWidth
Bit width for transfer, 8/16/24/32 bits
-
uint8_t channel
Transfer start channel
-
uint8_t channelMask
enabled channel mask value, refernece _sai_channel_mask
-
uint8_t endChannel
end channel number
-
uint8_t channelNums
Total enabled channel numbers
-
sai_transfer_t saiQueue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint8_t watermark
Watermark value
-
I2S_Type *base
SAI EDMA Driver
-
void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle)
Initializes the SAI eDMA handle.
This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
txDmaHandle – eDMA handle pointer, this handle shall be static allocated by users.
-
void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle)
Initializes the SAI Rx eDMA handle.
This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
rxDmaHandle – eDMA handle pointer, this handle shall be static allocated by users.
-
void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType)
Initializes the SAI interleave type.
This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is kSAI_EDMAInterleavePerChannelSample always
- Parameters:
handle – SAI eDMA handle pointer.
interleaveType – Multi channel interleave type.
-
void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)
Configures the SAI Tx.
Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step.
sai_transceiver_t config; SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite; SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config);
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
saiConfig – sai configurations.
-
void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)
Configures the SAI Rx.
Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step.
sai_transceiver_t config; SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead; SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config);
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
saiConfig – sai configurations.
-
status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)
Performs a non-blocking SAI transfer using DMA.
This function support multi channel transfer,
for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.
Note
This interface returns immediately after the transfer initiates. Call SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
xfer – Pointer to the DMA transfer structure.
- Return values:
kStatus_Success – Start a SAI eDMA send successfully.
kStatus_InvalidArgument – The input argument is invalid.
kStatus_TxBusy – SAI is busy sending data.
-
status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)
Performs a non-blocking SAI receive using eDMA.
This function support multi channel transfer,
for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.
Note
This interface returns immediately after the transfer initiates. Call the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.
- Parameters:
base – SAI base pointer
handle – SAI eDMA handle pointer.
xfer – Pointer to DMA transfer structure.
- Return values:
kStatus_Success – Start a SAI eDMA receive successfully.
kStatus_InvalidArgument – The input argument is invalid.
kStatus_RxBusy – SAI is busy receiving data.
-
status_t SAI_TransferSendLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)
Performs a non-blocking SAI loop transfer using eDMA.
Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer.
Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount).
loopTransferCount – the counts of xfer array.
- Return values:
kStatus_Success – Start a SAI eDMA send successfully.
kStatus_InvalidArgument – The input argument is invalid.
-
status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)
Performs a non-blocking SAI loop transfer using eDMA.
Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer.
Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount).
loopTransferCount – the counts of xfer array.
- Return values:
kStatus_Success – Start a SAI eDMA receive successfully.
kStatus_InvalidArgument – The input argument is invalid.
-
void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
Terminate all SAI send.
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSendEDMA.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
-
void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
Terminate all SAI receive.
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceiveEDMA.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
-
void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
Aborts a SAI transfer using eDMA.
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
-
void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
Aborts a SAI receive using eDMA.
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.
- Parameters:
base – SAI base pointer
handle – SAI eDMA handle pointer.
-
status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
Gets byte count sent by SAI.
- Parameters:
base – SAI base pointer.
handle – SAI eDMA handle pointer.
count – Bytes count sent by SAI.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.
-
status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
Gets byte count received by SAI.
- Parameters:
base – SAI base pointer
handle – SAI eDMA handle pointer.
count – Bytes count received by SAI.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.
-
uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle)
Gets valid transfer slot.
This function can be used to query the valid transfer request slot that the application can submit. It should be called in the critical section, that means the application could call it in the corresponding callback function or disable IRQ before calling it in the application, otherwise, the returned value may not correct.
- Parameters:
base – SAI base pointer
handle – SAI eDMA handle pointer.
- Return values:
valid – slot count that application submit.
-
FSL_SAI_EDMA_DRIVER_VERSION
Version 2.7.1
-
enum _sai_edma_interleave
sai interleave type
Values:
-
enumerator kSAI_EDMAInterleavePerChannelSample
-
enumerator kSAI_EDMAInterleavePerChannelBlock
-
enumerator kSAI_EDMAInterleavePerChannelSample
-
typedef struct sai_edma_handle sai_edma_handle_t
-
typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)
SAI eDMA transfer callback function for finish and error.
-
typedef enum _sai_edma_interleave sai_edma_interleave_t
sai interleave type
-
struct sai_edma_handle
- #include <fsl_sai_edma.h>
SAI DMA transfer handle, users should not touch the content of the handle.
Public Members
-
edma_handle_t *dmaHandle
DMA handler for SAI send
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
uint8_t bytesPerFrame
Bytes in a frame
-
uint8_t channelMask
Enabled channel mask value, reference _sai_channel_mask
-
uint8_t channelNums
total enabled channel nums
-
uint8_t channel
Which data channel
-
uint8_t count
The transfer data count in a DMA request
-
uint32_t state
Internal state for SAI eDMA transfer
-
sai_edma_callback_t callback
Callback for users while transfer finish or error occurs
-
void *userData
User callback parameter
-
uint8_t tcd[((4U) + 1U) * sizeof(edma_tcd_t)]
TCD pool for eDMA transfer.
-
sai_transfer_t saiQueue[(4U)]
Transfer queue storing queued transfer.
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
sai_edma_interleave_t interleaveType
Transfer interleave type
-
volatile uint8_t queueUser
Index for user to queue transfer.
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
edma_handle_t *dmaHandle
SEMA42: Hardware Semaphores Driver
-
FSL_SEMA42_DRIVER_VERSION
SEMA42 driver version.
SEMA42 status return codes.
Values:
-
enumerator kStatus_SEMA42_Busy
SEMA42 gate has been locked by other processor.
-
enumerator kStatus_SEMA42_Reseting
SEMA42 gate reseting is ongoing.
-
enumerator kStatus_SEMA42_Busy
-
enum _sema42_gate_status
SEMA42 gate lock status.
Values:
-
enumerator kSEMA42_Unlocked
The gate is unlocked.
-
enumerator kSEMA42_LockedByProc0
The gate is locked by processor 0.
-
enumerator kSEMA42_LockedByProc1
The gate is locked by processor 1.
-
enumerator kSEMA42_LockedByProc2
The gate is locked by processor 2.
-
enumerator kSEMA42_LockedByProc3
The gate is locked by processor 3.
-
enumerator kSEMA42_LockedByProc4
The gate is locked by processor 4.
-
enumerator kSEMA42_LockedByProc5
The gate is locked by processor 5.
-
enumerator kSEMA42_LockedByProc6
The gate is locked by processor 6.
-
enumerator kSEMA42_LockedByProc7
The gate is locked by processor 7.
-
enumerator kSEMA42_LockedByProc8
The gate is locked by processor 8.
-
enumerator kSEMA42_LockedByProc9
The gate is locked by processor 9.
-
enumerator kSEMA42_LockedByProc10
The gate is locked by processor 10.
-
enumerator kSEMA42_LockedByProc11
The gate is locked by processor 11.
-
enumerator kSEMA42_LockedByProc12
The gate is locked by processor 12.
-
enumerator kSEMA42_LockedByProc13
The gate is locked by processor 13.
-
enumerator kSEMA42_LockedByProc14
The gate is locked by processor 14.
-
enumerator kSEMA42_Unlocked
-
typedef enum _sema42_gate_status sema42_gate_status_t
SEMA42 gate lock status.
-
void SEMA42_Init(SEMA42_Type *base)
Initializes the SEMA42 module.
This function initializes the SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA42_ResetGate or SEMA42_ResetAllGates function.
- Parameters:
base – SEMA42 peripheral base address.
-
void SEMA42_Deinit(SEMA42_Type *base)
De-initializes the SEMA42 module.
This function de-initializes the SEMA42 module. It only disables the clock.
- Parameters:
base – SEMA42 peripheral base address.
-
status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)
Tries to lock the SEMA42 gate.
This function tries to lock the specific SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.
- Parameters:
base – SEMA42 peripheral base address.
gateNum – Gate number to lock.
procNum – Current processor number.
- Return values:
kStatus_Success – Lock the sema42 gate successfully.
kStatus_SEMA42_Busy – Sema42 gate has been locked by another processor.
-
void SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)
Locks the SEMA42 gate.
This function locks the specific SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.
- Parameters:
base – SEMA42 peripheral base address.
gateNum – Gate number to lock.
procNum – Current processor number.
-
static inline void SEMA42_Unlock(SEMA42_Type *base, uint8_t gateNum)
Unlocks the SEMA42 gate.
This function unlocks the specific SEMA42 gate. It only writes unlock value to the SEMA42 gate register. However, it does not check whether the SEMA42 gate is locked by the current processor or not. As a result, if the SEMA42 gate is not locked by the current processor, this function has no effect.
- Parameters:
base – SEMA42 peripheral base address.
gateNum – Gate number to unlock.
-
static inline sema42_gate_status_t SEMA42_GetGateStatus(SEMA42_Type *base, uint8_t gateNum)
Gets the status of the SEMA42 gate.
This function checks the lock status of a specific SEMA42 gate.
- Parameters:
base – SEMA42 peripheral base address.
gateNum – Gate number.
- Returns:
status Current status.
-
status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum)
Resets the SEMA42 gate to an unlocked status.
This function resets a SEMA42 gate to an unlocked status.
- Parameters:
base – SEMA42 peripheral base address.
gateNum – Gate number.
- Return values:
kStatus_Success – SEMA42 gate is reset successfully.
kStatus_SEMA42_Reseting – Some other reset process is ongoing.
-
static inline status_t SEMA42_ResetAllGates(SEMA42_Type *base)
Resets all SEMA42 gates to an unlocked status.
This function resets all SEMA42 gate to an unlocked status.
- Parameters:
base – SEMA42 peripheral base address.
- Return values:
kStatus_Success – SEMA42 is reset successfully.
kStatus_SEMA42_Reseting – Some other reset process is ongoing.
-
SEMA42_GATE_NUM_RESET_ALL
The number to reset all SEMA42 gates.
-
SEMA42_GATEn(base, n)
SEMA42 gate n register address.
The SEMA42 gates are sorted in the order 3, 2, 1, 0, 7, 6, 5, 4, … not in the order 0, 1, 2, 3, 4, 5, 6, 7, … The macro SEMA42_GATEn gets the SEMA42 gate based on the gate index.
The input gate index is XOR’ed with 3U: 0 ^ 3 = 3 1 ^ 3 = 2 2 ^ 3 = 1 3 ^ 3 = 0 4 ^ 3 = 7 5 ^ 3 = 6 6 ^ 3 = 5 7 ^ 3 = 4 …
SEMC: Smart External DRAM Controller Driver
-
void SEMC_GetDefaultConfig(semc_config_t *config)
Gets the SEMC default basic configuration structure.
The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example:
semc_config_t config; SEMC_GetDefaultConfig(&config);
- Parameters:
config – The SEMC configuration structure pointer.
-
void SEMC_Init(SEMC_Type *base, semc_config_t *configure)
Initializes SEMC. This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.
- Parameters:
base – SEMC peripheral base address.
configure – The SEMC configuration structure pointer.
-
void SEMC_Deinit(SEMC_Type *base)
Deinitializes the SEMC module and gates the clock.
This function gates the SEMC clock. As a result, the SEMC module doesn’t work after calling this function, for some IDE, calling this API may cause the next downloading operation failed. so, please call this API cautiously. Additional, users can using “#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)” to disable the clock control operation in drivers.
- Parameters:
base – SEMC peripheral base address.
-
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)
Configures SDRAM controller in SEMC.
- Parameters:
base – SEMC peripheral base address.
cs – The chip selection.
config – The sdram configuration.
clkSrc_Hz – The SEMC clock frequency.
-
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
Configures NAND controller in SEMC.
- Parameters:
base – SEMC peripheral base address.
config – The nand configuration.
clkSrc_Hz – The SEMC clock frequency.
-
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
Configures NOR controller in SEMC.
- Parameters:
base – SEMC peripheral base address.
config – The nor configuration.
clkSrc_Hz – The SEMC clock frequency.
-
status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base, semc_sram_cs_t cs, semc_sram_config_t *config, uint32_t clkSrc_Hz)
Configures SRAM controller in SEMC.
- Parameters:
base – SEMC peripheral base address.
cs – The chip selection.
config – The sram configuration.
clkSrc_Hz – The SEMC clock frequency.
-
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)
Configures SRAM controller in SEMC.
- Deprecated:
Do not use this function. It has been superceded by SEMC_ConfigureSRAMWithChipSelection.
- Parameters:
base – SEMC peripheral base address.
config – The sram configuration.
clkSrc_Hz – The SEMC clock frequency.
-
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)
Configures DBI controller in SEMC.
- Parameters:
base – SEMC peripheral base address.
config – The dbi configuration.
clkSrc_Hz – The SEMC clock frequency.
-
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
Enables the SEMC interrupt.
This function enables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to enable the IP command done and error interrupt, do the following.
SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
- Parameters:
base – SEMC peripheral base address.
mask – SEMC interrupts to enable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.
-
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
Disables the SEMC interrupt.
This function disables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to disable the IP command done and error interrupt, do the following.
SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
- Parameters:
base – SEMC peripheral base address.
mask – SEMC interrupts to disable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.
-
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
Gets the SEMC status.
This function gets the SEMC interrupts event status. User can use the a logical OR of enumeration member as a mask. See semc_interrupt_enable_t.
- Parameters:
base – SEMC peripheral base address.
- Returns:
status flag, use status flag in semc_interrupt_enable_t to get the related status.
-
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
Clears the SEMC status flag state.
The following status register flags can be cleared SEMC interrupt status.
- Parameters:
base – SEMC base pointer
mask – The status flag mask, a logical OR of enumeration member semc_interrupt_enable_t.
-
static inline bool SEMC_IsInIdle(SEMC_Type *base)
Check if SEMC is in idle.
- Parameters:
base – SEMC peripheral base address.
- Returns:
True SEMC is in idle, false is not in idle.
-
status_t SEMC_SendIPCommand(SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
SEMC IP command access.
- Parameters:
base – SEMC peripheral base address.
memType – SEMC memory type. refer to “semc_mem_type_t”
address – SEMC device address.
command – SEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to “semc_ipcmd_nor_dbi_t”. For SRAM device, take refer to “semc_ipcmd_sram_t”. For SDRAM device, take refer to “semc_ipcmd_sdram_t”.
write – Data for write access.
read – Data pointer for read data out.
-
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, semc_ipcmd_nand_addrmode_t addrMode, semc_ipcmd_nand_cmdmode_t cmdMode)
Build SEMC IP command for NAND.
This function build SEMC NAND IP command. The command is build of user command code, SEMC address mode and SEMC command mode.
- Parameters:
userCommand – NAND device normal command.
addrMode – NAND address mode. Refer to “semc_ipcmd_nand_addrmode_t”.
cmdMode – NAND command mode. Refer to “semc_ipcmd_nand_cmdmode_t”.
-
static inline bool SEMC_IsNandReady(SEMC_Type *base)
Check if the NAND device is ready.
- Parameters:
base – SEMC peripheral base address.
- Returns:
True NAND is ready, false NAND is not ready.
-
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
SEMC NAND device memory write through IP command.
- Parameters:
base – SEMC peripheral base address.
address – SEMC NAND device address.
data – Data for write access.
size_bytes – Data length.
-
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
SEMC NAND device memory read through IP command.
- Parameters:
base – SEMC peripheral base address.
address – SEMC NAND device address.
data – Data pointer for data read out.
size_bytes – Data length.
-
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
SEMC NOR device memory write through IP command.
- Parameters:
base – SEMC peripheral base address.
address – SEMC NOR device address.
data – Data for write access.
size_bytes – Data length.
-
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
SEMC NOR device memory read through IP command.
- Parameters:
base – SEMC peripheral base address.
address – SEMC NOR device address.
data – Data pointer for data read out.
size_bytes – Data length.
-
FSL_SEMC_DRIVER_VERSION
SEMC driver version.
SEMC status, _semc_status.
Values:
-
enumerator kStatus_SEMC_InvalidDeviceType
Invalid device type.
-
enumerator kStatus_SEMC_IpCommandExecutionError
IP command execution error.
-
enumerator kStatus_SEMC_AxiCommandExecutionError
AXI command execution error.
-
enumerator kStatus_SEMC_InvalidMemorySize
Invalid memory sie.
-
enumerator kStatus_SEMC_InvalidIpcmdDataSize
Invalid IP command data size.
-
enumerator kStatus_SEMC_InvalidAddressPortWidth
Invalid address port width.
-
enumerator kStatus_SEMC_InvalidDataPortWidth
Invalid data port width.
-
enumerator kStatus_SEMC_InvalidSwPinmuxSelection
Invalid SW pinmux selection.
-
enumerator kStatus_SEMC_InvalidBurstLength
Invalid burst length
-
enumerator kStatus_SEMC_InvalidColumnAddressBitWidth
Invalid column address bit width.
-
enumerator kStatus_SEMC_InvalidBaseAddress
Invalid base address.
-
enumerator kStatus_SEMC_InvalidTimerSetting
Invalid timer setting.
-
enumerator kStatus_SEMC_InvalidDeviceType
-
enum _semc_mem_type
SEMC memory device type.
Values:
-
enumerator kSEMC_MemType_SDRAM
SDRAM
-
enumerator kSEMC_MemType_SRAM
SRAM
-
enumerator kSEMC_MemType_NOR
NOR
-
enumerator kSEMC_MemType_NAND
NAND
-
enumerator kSEMC_MemType_8080
-
enumerator kSEMC_MemType_SDRAM
-
enum _semc_waitready_polarity
SEMC WAIT/RDY polarity.
Values:
-
enumerator kSEMC_LowActive
Low active.
-
enumerator kSEMC_HighActive
High active.
-
enumerator kSEMC_LowActive
-
enum _semc_sdram_cs
SEMC SDRAM Chip selection .
Values:
-
enumerator kSEMC_SDRAM_CS0
SEMC SDRAM CS0.
-
enumerator kSEMC_SDRAM_CS1
SEMC SDRAM CS1.
-
enumerator kSEMC_SDRAM_CS2
SEMC SDRAM CS2.
-
enumerator kSEMC_SDRAM_CS3
SEMC SDRAM CS3.
-
enumerator kSEMC_SDRAM_CS0
-
enum _semc_sram_cs
SEMC SRAM Chip selection .
Values:
-
enumerator kSEMC_SRAM_CS0
SEMC SRAM CS0.
-
enumerator kSEMC_SRAM_CS0
-
enum _semc_nand_access_type
SEMC NAND device type.
Values:
-
enumerator kSEMC_NAND_ACCESS_BY_AXI
Access to NAND flash by AXI bus.
-
enumerator kSEMC_NAND_ACCESS_BY_IPCMD
Access to NAND flash by IP bus.
-
enumerator kSEMC_NAND_ACCESS_BY_AXI
-
enum _semc_interrupt_enable
SEMC interrupts .
Values:
-
enumerator kSEMC_IPCmdDoneInterrupt
Ip command done interrupt.
-
enumerator kSEMC_IPCmdErrInterrupt
Ip command error interrupt.
-
enumerator kSEMC_AXICmdErrInterrupt
AXI command error interrupt.
-
enumerator kSEMC_AXIBusErrInterrupt
AXI bus error interrupt.
-
enumerator kSEMC_IPCmdDoneInterrupt
-
enum _semc_ipcmd_datasize
SEMC IP command data size in bytes.
Values:
-
enumerator kSEMC_IPcmdDataSize_1bytes
The IP command data size 1 byte.
-
enumerator kSEMC_IPcmdDataSize_2bytes
The IP command data size 2 byte.
-
enumerator kSEMC_IPcmdDataSize_3bytes
The IP command data size 3 byte.
-
enumerator kSEMC_IPcmdDataSize_4bytes
The IP command data size 4 byte.
-
enumerator kSEMC_IPcmdDataSize_1bytes
-
enum _semc_refresh_time
SEMC auto-refresh timing.
Values:
-
enumerator kSEMC_RefreshThreeClocks
The refresh timing with three bus clocks.
-
enumerator kSEMC_RefreshSixClocks
The refresh timing with six bus clocks.
-
enumerator kSEMC_RefreshNineClocks
The refresh timing with nine bus clocks.
-
enumerator kSEMC_RefreshThreeClocks
-
enum _semc_caslatency
CAS latency.
Values:
-
enumerator kSEMC_LatencyOne
Latency 1.
-
enumerator kSEMC_LatencyTwo
Latency 2.
-
enumerator kSEMC_LatencyThree
Latency 3.
-
enumerator kSEMC_LatencyOne
-
enum _semc_sdram_column_bit_num
SEMC sdram column address bit number.
Values:
-
enumerator kSEMC_SdramColunm_12bit
12 bit.
-
enumerator kSEMC_SdramColunm_11bit
11 bit.
-
enumerator kSEMC_SdramColunm_10bit
10 bit.
-
enumerator kSEMC_SdramColunm_9bit
9 bit.
-
enumerator kSEMC_SdramColunm_8bit
8 bit.
-
enumerator kSEMC_SdramColunm_12bit
-
enum _semc_sdram_burst_len
SEMC sdram burst length.
Values:
-
enumerator kSEMC_Sdram_BurstLen1
According to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller’s burst length is greater than 1. Burst length 1
-
enumerator kSEMC_Sdram_BurstLen1
-
enum _semc_nand_column_bit_num
SEMC nand column address bit number.
Values:
-
enumerator kSEMC_NandColum_16bit
16 bit.
-
enumerator kSEMC_NandColum_15bit
15 bit.
-
enumerator kSEMC_NandColum_14bit
14 bit.
-
enumerator kSEMC_NandColum_13bit
13 bit.
-
enumerator kSEMC_NandColum_12bit
12 bit.
-
enumerator kSEMC_NandColum_11bit
11 bit.
-
enumerator kSEMC_NandColum_10bit
10 bit.
-
enumerator kSEMC_NandColum_9bit
9 bit.
-
enumerator kSEMC_NandColum_16bit
-
enum _semc_nand_burst_len
SEMC nand burst length.
Values:
-
enumerator kSEMC_Nand_BurstLen1
Burst length 1
-
enumerator kSEMC_Nand_BurstLen2
Burst length 2
-
enumerator kSEMC_Nand_BurstLen4
Burst length 4
-
enumerator kSEMC_Nand_BurstLen8
Burst length 8
-
enumerator kSEMC_Nand_BurstLen16
Burst length 16
-
enumerator kSEMC_Nand_BurstLen32
Burst length 32
-
enumerator kSEMC_Nand_BurstLen64
Burst length 64
-
enumerator kSEMC_Nand_BurstLen1
-
enum _semc_norsram_column_bit_num
SEMC nor/sram column address bit number.
Values:
-
enumerator kSEMC_NorColum_12bit
12 bit.
-
enumerator kSEMC_NorColum_11bit
11 bit.
-
enumerator kSEMC_NorColum_10bit
10 bit.
-
enumerator kSEMC_NorColum_9bit
9 bit.
-
enumerator kSEMC_NorColum_8bit
8 bit.
-
enumerator kSEMC_NorColum_7bit
7 bit.
-
enumerator kSEMC_NorColum_6bit
6 bit.
-
enumerator kSEMC_NorColum_5bit
5 bit.
-
enumerator kSEMC_NorColum_4bit
4 bit.
-
enumerator kSEMC_NorColum_3bit
3 bit.
-
enumerator kSEMC_NorColum_2bit
2 bit.
-
enumerator kSEMC_NorColum_12bit
-
enum _semc_norsram_burst_len
SEMC nor/sram burst length.
Values:
-
enumerator kSEMC_Nor_BurstLen1
Burst length 1
-
enumerator kSEMC_Nor_BurstLen2
Burst length 2
-
enumerator kSEMC_Nor_BurstLen4
Burst length 4
-
enumerator kSEMC_Nor_BurstLen8
Burst length 8
-
enumerator kSEMC_Nor_BurstLen16
Burst length 16
-
enumerator kSEMC_Nor_BurstLen32
Burst length 32
-
enumerator kSEMC_Nor_BurstLen64
Burst length 64
-
enumerator kSEMC_Nor_BurstLen1
-
enum _semc_dbi_column_bit_num
SEMC dbi column address bit number.
Values:
-
enumerator kSEMC_Dbi_Colum_12bit
12 bit.
-
enumerator kSEMC_Dbi_Colum_11bit
11 bit.
-
enumerator kSEMC_Dbi_Colum_10bit
10 bit.
-
enumerator kSEMC_Dbi_Colum_9bit
9 bit.
-
enumerator kSEMC_Dbi_Colum_8bit
8 bit.
-
enumerator kSEMC_Dbi_Colum_7bit
7 bit.
-
enumerator kSEMC_Dbi_Colum_6bit
6 bit.
-
enumerator kSEMC_Dbi_Colum_5bit
5 bit.
-
enumerator kSEMC_Dbi_Colum_4bit
4 bit.
-
enumerator kSEMC_Dbi_Colum_3bit
3 bit.
-
enumerator kSEMC_Dbi_Colum_2bit
2 bit.
-
enumerator kSEMC_Dbi_Colum_12bit
-
enum _semc_dbi_burst_len
SEMC dbi burst length.
Values:
-
enumerator kSEMC_Dbi_BurstLen1
Burst length 1
-
enumerator kSEMC_Dbi_BurstLen2
Burst length 2
-
enumerator kSEMC_Dbi_Dbi_BurstLen4
Burst length 4
-
enumerator kSEMC_Dbi_BurstLen8
Burst length 8
-
enumerator kSEMC_Dbi_BurstLen16
Burst length 16
-
enumerator kSEMC_Dbi_BurstLen32
Burst length 32
-
enumerator kSEMC_Dbi_BurstLen64
Burst length 64
-
enumerator kSEMC_Dbi_BurstLen1
-
enum _semc_iomux_pin
SEMC IOMUXC.
Values:
-
enumerator kSEMC_MUXA8
MUX A8 pin.
-
enumerator kSEMC_MUXCSX0
MUX CSX0 pin
-
enumerator kSEMC_MUXCSX1
MUX CSX1 Pin.
-
enumerator kSEMC_MUXCSX2
MUX CSX2 Pin.
-
enumerator kSEMC_MUXCSX3
MUX CSX3 Pin.
-
enumerator kSEMC_MUXRDY
MUX RDY pin.
-
enumerator kSEMC_MUXA8
-
enum _semc_iomux_nora27_pin
SEMC NOR/PSRAM Address bit 27 A27.
Values:
-
enumerator kSEMC_MORA27_NONE
No NOR/SRAM A27 pin.
-
enumerator kSEMC_NORA27_MUXCSX3
MUX CSX3 Pin.
-
enumerator kSEMC_NORA27_MUXRDY
MUX RDY pin.
-
enumerator kSEMC_MORA27_NONE
-
enum _semc_port_size
SEMC port size.
Values:
-
enumerator kSEMC_PortSize8Bit
8-Bit port size.
-
enumerator kSEMC_PortSize16Bit
16-Bit port size.
-
enumerator kSEMC_PortSize8Bit
-
enum _semc_addr_mode
SEMC address mode.
Values:
-
enumerator kSEMC_AddrDataMux
SEMC address/data mux mode.
-
enumerator kSEMC_AdvAddrdataMux
Advanced address/data mux mode.
-
enumerator kSEMC_AddrDataNonMux
Address/data non-mux mode.
-
enumerator kSEMC_AddrDataMux
-
enum _semc_dqs_mode
SEMC DQS read strobe mode.
Values:
-
enumerator kSEMC_Loopbackinternal
Dummy read strobe loopbacked internally.
-
enumerator kSEMC_Loopbackdqspad
Dummy read strobe loopbacked from DQS pad.
-
enumerator kSEMC_Loopbackinternal
-
enum _semc_adv_polarity
SEMC ADV signal active polarity.
Values:
-
enumerator kSEMC_AdvActiveLow
Adv active low.
-
enumerator kSEMC_AdvActiveHigh
Adv active high.
-
enumerator kSEMC_AdvActiveLow
-
enum _semc_sync_mode
SEMC sync mode.
Values:
-
enumerator kSEMC_AsyncMode
Async mode.
-
enumerator kSEMC_SyncMode
Sync mode.
-
enumerator kSEMC_AsyncMode
-
enum _semc_adv_level_control
SEMC ADV signal level control.
Values:
-
enumerator kSEMC_AdvHigh
Adv is high during address hold state.
-
enumerator kSEMC_AdvLow
Adv is low during address hold state.
-
enumerator kSEMC_AdvHigh
-
enum _semc_rdy_polarity
SEMC RDY signal active polarity.
Values:
-
enumerator kSEMC_RdyActiveLow
Adv active low.
-
enumerator kSEMC_RdyActivehigh
Adv active low.
-
enumerator kSEMC_RdyActiveLow
-
enum _semc_ipcmd_nand_addrmode
SEMC IP command for NAND: address mode.
Values:
-
enumerator kSEMC_NANDAM_ColumnRow
Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2).
-
enumerator kSEMC_NANDAM_ColumnCA0
Address mode: column address only(1 Byte-CA0).
-
enumerator kSEMC_NANDAM_ColumnCA0CA1
Address mode: column address only(2 Byte-CA0/CA1).
-
enumerator kSEMC_NANDAM_RawRA0
Address mode: row address only(1 Byte-RA0).
-
enumerator kSEMC_NANDAM_RawRA0RA1
Address mode: row address only(2 Byte-RA0/RA1).
-
enumerator kSEMC_NANDAM_RawRA0RA1RA2
Address mode: row address only(3 Byte-RA0).
-
enumerator kSEMC_NANDAM_ColumnRow
-
enum _semc_ipcmd_nand_cmdmode
SEMC IP command for NAND: command mode.
Values:
-
enumerator kSEMC_NANDCM_Command
command.
-
enumerator kSEMC_NANDCM_CommandHold
Command hold.
-
enumerator kSEMC_NANDCM_CommandAddress
Command address.
-
enumerator kSEMC_NANDCM_CommandAddressHold
Command address hold.
-
enumerator kSEMC_NANDCM_CommandAddressRead
Command address read.
-
enumerator kSEMC_NANDCM_CommandAddressWrite
Command address write.
-
enumerator kSEMC_NANDCM_CommandRead
Command read.
-
enumerator kSEMC_NANDCM_CommandWrite
Command write.
-
enumerator kSEMC_NANDCM_Read
Read.
-
enumerator kSEMC_NANDCM_Write
Write.
-
enumerator kSEMC_NANDCM_Command
-
enum _semc_nand_address_option
SEMC NAND address option.
Values:
-
enumerator kSEMC_NandAddrOption_5byte_CA2RA3
CA0+CA1+RA0+RA1+RA2
-
enumerator kSEMC_NandAddrOption_4byte_CA2RA2
CA0+CA1+RA0+RA1
-
enumerator kSEMC_NandAddrOption_3byte_CA2RA1
CA0+CA1+RA0
-
enumerator kSEMC_NandAddrOption_4byte_CA1RA3
CA0+RA0+RA1+RA2
-
enumerator kSEMC_NandAddrOption_3byte_CA1RA2
CA0+RA0+RA1
-
enumerator kSEMC_NandAddrOption_2byte_CA1RA1
CA0+RA0
-
enumerator kSEMC_NandAddrOption_5byte_CA2RA3
-
enum _semc_ipcmd_nor_dbi
SEMC IP command for NOR.
Values:
-
enumerator kSEMC_NORDBICM_Read
NOR read.
-
enumerator kSEMC_NORDBICM_Write
NOR write.
-
enumerator kSEMC_NORDBICM_Read
-
enum _semc_ipcmd_sram
SEMC IP command for SRAM.
Values:
-
enumerator kSEMC_SRAMCM_ArrayRead
SRAM memory array read.
-
enumerator kSEMC_SRAMCM_ArrayWrite
SRAM memory array write.
-
enumerator kSEMC_SRAMCM_RegRead
SRAM memory register read.
-
enumerator kSEMC_SRAMCM_RegWrite
SRAM memory register write.
-
enumerator kSEMC_SRAMCM_ArrayRead
-
enum _semc_ipcmd_sdram
SEMC IP command for SDARM.
Values:
-
enumerator kSEMC_SDRAMCM_Read
SDRAM memory read.
-
enumerator kSEMC_SDRAMCM_Write
SDRAM memory write.
-
enumerator kSEMC_SDRAMCM_Modeset
SDRAM MODE SET.
-
enumerator kSEMC_SDRAMCM_Active
SDRAM active.
-
enumerator kSEMC_SDRAMCM_AutoRefresh
SDRAM auto-refresh.
-
enumerator kSEMC_SDRAMCM_SelfRefresh
SDRAM self-refresh.
-
enumerator kSEMC_SDRAMCM_Precharge
SDRAM precharge.
-
enumerator kSEMC_SDRAMCM_Prechargeall
SDRAM precharge all.
-
enumerator kSEMC_SDRAMCM_Read
-
typedef enum _semc_mem_type semc_mem_type_t
SEMC memory device type.
-
typedef enum _semc_waitready_polarity semc_waitready_polarity_t
SEMC WAIT/RDY polarity.
-
typedef enum _semc_sdram_cs semc_sdram_cs_t
SEMC SDRAM Chip selection .
-
typedef enum _semc_sram_cs semc_sram_cs_t
SEMC SRAM Chip selection .
-
typedef enum _semc_nand_access_type semc_nand_access_type_t
SEMC NAND device type.
-
typedef enum _semc_interrupt_enable semc_interrupt_enable_t
SEMC interrupts .
-
typedef enum _semc_ipcmd_datasize semc_ipcmd_datasize_t
SEMC IP command data size in bytes.
-
typedef enum _semc_refresh_time semc_refresh_time_t
SEMC auto-refresh timing.
-
typedef enum _semc_caslatency semc_caslatency_t
CAS latency.
-
typedef enum _semc_sdram_column_bit_num semc_sdram_column_bit_num_t
SEMC sdram column address bit number.
-
typedef enum _semc_sdram_burst_len sem_sdram_burst_len_t
SEMC sdram burst length.
-
typedef enum _semc_nand_column_bit_num semc_nand_column_bit_num_t
SEMC nand column address bit number.
-
typedef enum _semc_nand_burst_len sem_nand_burst_len_t
SEMC nand burst length.
-
typedef enum _semc_norsram_column_bit_num semc_norsram_column_bit_num_t
SEMC nor/sram column address bit number.
-
typedef enum _semc_norsram_burst_len sem_norsram_burst_len_t
SEMC nor/sram burst length.
-
typedef enum _semc_dbi_column_bit_num semc_dbi_column_bit_num_t
SEMC dbi column address bit number.
-
typedef enum _semc_dbi_burst_len sem_dbi_burst_len_t
SEMC dbi burst length.
-
typedef enum _semc_iomux_pin semc_iomux_pin
SEMC IOMUXC.
-
typedef enum _semc_iomux_nora27_pin semc_iomux_nora27_pin
SEMC NOR/PSRAM Address bit 27 A27.
-
typedef enum _semc_port_size smec_port_size_t
SEMC port size.
-
typedef enum _semc_addr_mode semc_addr_mode_t
SEMC address mode.
-
typedef enum _semc_dqs_mode semc_dqs_mode_t
SEMC DQS read strobe mode.
-
typedef enum _semc_adv_polarity semc_adv_polarity_t
SEMC ADV signal active polarity.
-
typedef enum _semc_sync_mode semc_sync_mode_t
SEMC sync mode.
-
typedef enum _semc_adv_level_control semc_adv_level_control_t
SEMC ADV signal level control.
-
typedef enum _semc_rdy_polarity semc_rdy_polarity_t
SEMC RDY signal active polarity.
-
typedef enum _semc_ipcmd_nand_addrmode semc_ipcmd_nand_addrmode_t
SEMC IP command for NAND: address mode.
-
typedef enum _semc_ipcmd_nand_cmdmode semc_ipcmd_nand_cmdmode_t
SEMC IP command for NAND: command mode.
-
typedef enum _semc_nand_address_option semc_nand_address_option_t
SEMC NAND address option.
-
typedef enum _semc_ipcmd_nor_dbi semc_ipcmd_nor_dbi_t
SEMC IP command for NOR.
-
typedef enum _semc_ipcmd_sram semc_ipcmd_sram_t
SEMC IP command for SRAM.
-
typedef enum _semc_ipcmd_sdram semc_ipcmd_sdram_t
SEMC IP command for SDARM.
-
typedef struct _semc_sdram_config semc_sdram_config_t
SEMC SDRAM configuration structure.
The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.
-
typedef struct _semc_nand_timing_config semc_nand_timing_config_t
SEMC NAND device timing configuration structure.
-
typedef struct _semc_nand_config semc_nand_config_t
SEMC NAND configuration structure.
-
typedef struct _semc_nor_config semc_nor_config_t
SEMC NOR configuration structure.
-
typedef struct _semc_sram_config semc_sram_config_t
SEMC SRAM configuration structure.
-
typedef struct _semc_dbi_config semc_dbi_config_t
SEMC DBI configuration structure.
-
typedef struct _semc_queuea_weight_struct semc_queuea_weight_struct_t
SEMC AXI queue a weight setting structure.
-
typedef union _semc_queuea_weight semc_queuea_weight_t
SEMC AXI queue a weight setting union.
-
typedef struct _semc_queueb_weight_struct semc_queueb_weight_struct_t
SEMC AXI queue b weight setting structure.
-
typedef union _semc_queueb_weight semc_queueb_weight_t
SEMC AXI queue b weight setting union.
-
typedef struct _semc_axi_queueweight semc_axi_queueweight_t
SEMC AXI queue weight setting.
-
typedef struct _semc_config_t semc_config_t
SEMC configuration structure.
busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it’s similar to the busTimeoutCycles.
-
struct _semc_sdram_config
- #include <fsl_semc.h>
SEMC SDRAM configuration structure.
The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.
Public Members
-
semc_iomux_pin csxPinMux
CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting.
-
uint32_t address
The base address.
-
uint32_t memsize_kbytes
The memory size in unit of kbytes.
-
smec_port_size_t portSize
Port size.
-
sem_sdram_burst_len_t burstLen
Burst length.
-
semc_sdram_column_bit_num_t columnAddrBitNum
Column address bit number.
-
semc_caslatency_t casLatency
CAS latency.
-
uint8_t tPrecharge2Act_Ns
Precharge to active wait time in unit of nanosecond.
-
uint8_t tAct2ReadWrite_Ns
Act to read/write wait time in unit of nanosecond.
-
uint8_t tRefreshRecovery_Ns
Refresh recovery time in unit of nanosecond.
-
uint8_t tWriteRecovery_Ns
write recovery time in unit of nanosecond.
-
uint8_t tCkeOff_Ns
CKE off minimum time in unit of nanosecond.
-
uint8_t tAct2Prechage_Ns
Active to precharge in unit of nanosecond.
-
uint8_t tSelfRefRecovery_Ns
Self refresh recovery time in unit of nanosecond.
-
uint8_t tRefresh2Refresh_Ns
Refresh to refresh wait time in unit of nanosecond.
-
uint8_t tAct2Act_Ns
Active to active wait time in unit of nanosecond.
-
uint32_t tPrescalePeriod_Ns
Prescaler timer period should not be larger than 256 * 16 * clock cycle.
-
uint32_t tIdleTimeout_Ns
Idle timeout in unit of prescale time period.
-
uint32_t refreshPeriod_nsPerRow
Refresh timer period like 64ms * 1000000/8192 .
-
uint32_t refreshUrgThreshold
Refresh urgent threshold.
-
uint8_t refreshBurstLen
Refresh burst length.
-
uint8_t delayChain
Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.
-
uint8_t autofreshTimes
Auto Refresh cycles times.
-
struct _semc_nand_timing_config
- #include <fsl_semc.h>
SEMC NAND device timing configuration structure.
Public Members
-
uint8_t tCeSetup_Ns
CE setup time: tCS.
-
uint8_t tCeHold_Ns
CE hold time: tCH.
-
uint8_t tCeInterval_Ns
CE interval time:tCEITV.
-
uint8_t tWeLow_Ns
WE low time: tWP.
-
uint8_t tWeHigh_Ns
WE high time: tWH.
-
uint8_t tReLow_Ns
RE low time: tRP.
-
uint8_t tReHigh_Ns
RE high time: tREH.
-
uint8_t tTurnAround_Ns
Turnaround time for async mode: tTA.
-
uint8_t tWehigh2Relow_Ns
WE# high to RE# wait time: tWHR.
-
uint8_t tRehigh2Welow_Ns
RE# high to WE# low wait time: tRHW.
-
uint8_t tAle2WriteStart_Ns
ALE to write start wait time: tADL.
-
uint8_t tReady2Relow_Ns
Ready to RE# low min wait time: tRR.
-
uint8_t tWehigh2Busy_Ns
WE# high to busy wait time: tWB.
-
uint8_t tCeSetup_Ns
-
struct _semc_nand_config
- #include <fsl_semc.h>
SEMC NAND configuration structure.
Public Members
-
semc_iomux_pin cePinMux
The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting.
-
uint32_t axiAddress
The base address for AXI nand.
-
uint32_t axiMemsize_kbytes
The memory size in unit of kbytes for AXI nand.
-
uint32_t ipgAddress
The base address for IPG nand .
-
uint32_t ipgMemsize_kbytes
The memory size in unit of kbytes for IPG nand.
-
semc_rdy_polarity_t rdyactivePolarity
Wait ready polarity.
-
bool edoModeEnabled
EDO mode enabled.
-
semc_nand_column_bit_num_t columnAddrBitNum
Column address bit number.
-
semc_nand_address_option_t arrayAddrOption
Address option.
-
sem_nand_burst_len_t burstLen
Burst length.
-
smec_port_size_t portSize
Port size.
-
semc_nand_timing_config_t *timingConfig
SEMC nand timing configuration.
-
semc_iomux_pin cePinMux
-
struct _semc_nor_config
- #include <fsl_semc.h>
SEMC NOR configuration structure.
Public Members
-
semc_iomux_pin cePinMux
The CE# pin mux setting.
-
semc_iomux_nora27_pin addr27
The Addr bit 27 pin mux setting.
-
uint32_t address
The base address.
-
uint32_t memsize_kbytes
The memory size in unit of kbytes.
-
uint8_t addrPortWidth
The address port width.
-
semc_rdy_polarity_t rdyactivePolarity
Wait ready polarity.
-
semc_adv_polarity_t advActivePolarity
ADV# polarity.
-
semc_norsram_column_bit_num_t columnAddrBitNum
Column address bit number.
-
semc_addr_mode_t addrMode
Address mode.
-
sem_norsram_burst_len_t burstLen
Burst length.
-
smec_port_size_t portSize
Port size.
-
uint8_t tCeSetup_Ns
The CE setup time.
-
uint8_t tCeHold_Ns
The CE hold time.
-
uint8_t tCeInterval_Ns
CE interval minimum time.
-
uint8_t tAddrSetup_Ns
The address setup time.
-
uint8_t tAddrHold_Ns
The address hold time.
-
uint8_t tWeLow_Ns
WE low time for async mode.
-
uint8_t tWeHigh_Ns
WE high time for async mode.
-
uint8_t tReLow_Ns
RE low time for async mode.
-
uint8_t tReHigh_Ns
RE high time for async mode.
-
uint8_t tTurnAround_Ns
Turnaround time for async mode.
-
uint8_t tAddr2WriteHold_Ns
Address to write data hold time for async mode.
-
uint8_t tWriteSetup_Ns
Write data setup time for sync mode.
-
uint8_t tWriteHold_Ns
Write hold time for sync mode.
-
uint8_t latencyCount
Latency count for sync mode.
-
uint8_t readCycle
Read cycle time for sync mode.
-
uint8_t delayChain
Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.
-
semc_iomux_pin cePinMux
-
struct _semc_sram_config
- #include <fsl_semc.h>
SEMC SRAM configuration structure.
Public Members
-
semc_iomux_pin cePinMux
The CE# pin mux setting.
-
semc_iomux_nora27_pin addr27
The Addr bit 27 pin mux setting.
-
uint32_t address
The base address.
-
uint32_t memsize_kbytes
The memory size in unit of kbytes.
-
uint8_t addrPortWidth
The address port width.
-
semc_adv_polarity_t advActivePolarity
ADV# polarity 1: active high, 0: active low.
-
semc_addr_mode_t addrMode
Address mode.
-
sem_norsram_burst_len_t burstLen
Burst length.
-
smec_port_size_t portSize
Port size.
-
semc_sync_mode_t syncMode
Sync mode.
-
bool waitEnable
Wait enable.
-
uint8_t waitSample
Wait sample.
-
semc_adv_level_control_t advLevelCtrl
ADV# level control during address hold state, 1: low, 0: high.
-
uint8_t tCeSetup_Ns
The CE setup time.
-
uint8_t tCeHold_Ns
The CE hold time.
-
uint8_t tCeInterval_Ns
CE interval minimum time.
-
uint8_t readHoldTime_Ns
read hold time.
-
uint8_t tAddrSetup_Ns
The address setup time.
-
uint8_t tAddrHold_Ns
The address hold time.
-
uint8_t tWeLow_Ns
WE low time for async mode.
-
uint8_t tWeHigh_Ns
WE high time for async mode.
-
uint8_t tReLow_Ns
RE low time for async mode.
-
uint8_t tReHigh_Ns
RE high time for async mode.
-
uint8_t tTurnAround_Ns
Turnaround time for async mode.
-
uint8_t tAddr2WriteHold_Ns
Address to write data hold time for async mode.
-
uint8_t tWriteSetup_Ns
Write data setup time for sync mode.
-
uint8_t tWriteHold_Ns
Write hold time for sync mode.
-
uint8_t latencyCount
Latency count for sync mode.
-
uint8_t readCycle
Read cycle time for sync mode.
-
uint8_t delayChain
Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than read data.
-
semc_iomux_pin cePinMux
-
struct _semc_dbi_config
- #include <fsl_semc.h>
SEMC DBI configuration structure.
Public Members
-
semc_iomux_pin csxPinMux
The CE# pin mux.
-
uint32_t address
The base address.
-
uint32_t memsize_kbytes
The memory size in unit of 4kbytes.
-
semc_dbi_column_bit_num_t columnAddrBitNum
Column address bit number.
-
sem_dbi_burst_len_t burstLen
Burst length.
-
smec_port_size_t portSize
Port size.
-
uint8_t tCsxSetup_Ns
The CSX setup time.
-
uint8_t tCsxHold_Ns
The CSX hold time.
-
uint8_t tWexLow_Ns
WEX low time.
-
uint8_t tWexHigh_Ns
WEX high time.
-
uint8_t tRdxLow_Ns
RDX low time.
-
uint8_t tRdxHigh_Ns
RDX high time.
-
uint8_t tCsxInterval_Ns
Write data setup time.
-
semc_iomux_pin csxPinMux
-
struct _semc_queuea_weight_struct
- #include <fsl_semc.h>
SEMC AXI queue a weight setting structure.
Public Members
-
uint32_t qos
weight of qos for queue 0 .
-
uint32_t aging
weight of aging for queue 0.
-
uint32_t slaveHitNoswitch
weight of read/write no switch for queue 0 .
-
uint32_t slaveHitSwitch
weight of read/write switch for queue 0.
-
uint32_t qos
-
union _semc_queuea_weight
- #include <fsl_semc.h>
SEMC AXI queue a weight setting union.
Public Members
-
semc_queuea_weight_struct_t queueaConfig
Structure configuration for queueA.
-
uint32_t queueaValue
Configuration value for queueA which could directly write to the reg.
-
semc_queuea_weight_struct_t queueaConfig
-
struct _semc_queueb_weight_struct
- #include <fsl_semc.h>
SEMC AXI queue b weight setting structure.
Public Members
-
uint32_t qos
weight of qos for queue 1.
-
uint32_t aging
weight of aging for queue 1.
-
uint32_t weightPagehit
weight of page hit for queue 1 only .
-
uint32_t slaveHitNoswitch
weight of read/write no switch for queue 1.
-
uint32_t bankRotation
weight of bank rotation for queue 1 only .
-
uint32_t qos
-
union _semc_queueb_weight
- #include <fsl_semc.h>
SEMC AXI queue b weight setting union.
Public Members
-
semc_queueb_weight_struct_t queuebConfig
Structure configuration for queueB.
-
uint32_t queuebValue
Configuration value for queueB which could directly write to the reg.
-
semc_queueb_weight_struct_t queuebConfig
-
struct _semc_axi_queueweight
- #include <fsl_semc.h>
SEMC AXI queue weight setting.
Public Members
-
bool queueaEnable
Enable queue a.
-
semc_queuea_weight_t queueaWeight
Weight settings for queue a.
-
bool queuebEnable
Enable queue b.
-
semc_queueb_weight_t queuebWeight
Weight settings for queue b.
-
bool queueaEnable
-
struct _semc_config_t
- #include <fsl_semc.h>
SEMC configuration structure.
busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it’s similar to the busTimeoutCycles.
Public Members
-
semc_dqs_mode_t dqsMode
Dummy read strobe mode: use enum in “semc_dqs_mode_t”.
-
uint8_t cmdTimeoutCycles
Command execution timeout cycles.
-
uint8_t busTimeoutCycles
Bus timeout cycles.
-
semc_axi_queueweight_t queueWeight
AXI queue weight.
-
semc_dqs_mode_t dqsMode
SINC: SINC Filter
-
void SINC_Init(SINC_Type *base, const sinc_config_t *config)
Initialize selected SINC instance, including clock options and channel options.
- Parameters:
base – SINC peripheral base address.
config – The pointer to sinc_config_t structure.
-
void SINC_Deinit(SINC_Type *base)
De-initialize selected SINC instance.
- Parameters:
base – SINC peripheral base address.
-
void SINC_GetDefaultConfig(sinc_config_t *config)
Get default configuration.
config->clockPreDivider = kSINC_ClkPrescale1; config->modClkDivider = 2UL; config->disableModClk0Output = false; config->disableModClk1Output = false; config->disableModClk2Output = false; config->channelsConfigArray[4] = {NULL, NULL, NULL, NULL}; config->disableDozeMode = false; config->enableMaster = false;
- Parameters:
config – The pointer to sinc_config_t structure, must not be NULL.
-
static inline void SINC_EnableMaster(SINC_Type *base, bool enable)
Enable/disable all function blocks enabled in their respective registers.
- Parameters:
base – SINC peripheral base address.
enable – Used to enable/disable all function blocks:
true Enable all function blocks, please note that clock must be configured previously;
false Disable all function blocks.
-
static inline void SINC_DoSoftwareReset(SINC_Type *base)
Reset all function blocks(except for the clock blocks), interrupt statuses.
- Parameters:
base – SINC peripheral base address.
-
static inline void SINC_DisableDozeMode(SINC_Type *base, bool disable)
Disable/enable SINC module when the chip enters Doze or Stop mode.
- Parameters:
base – SINC peripheral base address.
disable – Used to control if module functional when the chip enters Doze and Stop mode:
true Disable SINC when the chip enters Doze or Stop mode;
false Enable SINC when the chip enters Doze or stop mode.
-
static inline bool SINC_CheckModulatorClockReady(SINC_Type *base, uint32_t modClkMasks)
Check whether selected modulator clocks are ready.
Note
The result of this APIs means all selected modulator clocks are (not) ready.
- Parameters:
base – SINC peripheral base address.
modClkMasks – The mask of modulator clocks, please refer to _sinc_modulator_clock.
- Return values:
true – The input mask of modulator clocks are ready.
false – The input mask of modulator clocks are not ready.
-
static inline void SINC_DisableModulatorClockOutput(SINC_Type *base, uint32_t modClkMasks, bool disable)
Disable/enable modulator clocks’ output.
Note
By default, modulator clock’s output is enabled.
- Parameters:
base – SINC peripheral base address.
modClkMasks – The mask of modulator clocks, please refer to _sinc_modulator_clock.
disable – Used to enable/disable clock output:
true Disable modulator clocks’ output;
false Enable modulator clocks’ output.
-
static inline void SINC_SetClkPrescale(SINC_Type *base, sinc_clock_prescale_t clkPrescale)
Set the clock divider ratio for the modulator clock.
- Parameters:
base – SINC peripheral base address.
clkPrescale – Clock prescale value, please refer to sinc_clock_prescale_t.
-
static inline void SINC_SetModulatorClockDivider(SINC_Type *base, uint32_t modClkDivider)
Set modulator clock divider value.
Note
IMCLK0 = PRE_CLK / modClkDivider, the minimum clock divider ration is 2.
- Parameters:
base – SINC peripheral base address.
modClkDivider – Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output, write an even value to modClkDivider .
-
void SINC_SetChannelConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_config_t *chConfig)
Set channel configurations, including input options, conversion options and protection options.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
chConfig – Pointer to sinc_channel_config_t structure, must not be NULL.
-
void SINC_SetChannelInputOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_input_option_t *chInputOption)
Set channel input options, including input bit format, input bit source, input bit delay, input clock source, input clock edge.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
chInputOption – Pointer to sinc_channel_input_option_t structure, must not be NULL.
-
void SINC_SetChannelConversionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_conv_option_t *chConvOption)
Set channel conversion options, including conversion mode, trigger source, and primary filter settings.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
chConvOption – Pointer to sinc_channel_conv_option_t structure, must not be NULL.
-
void SINC_SetChannelProtectionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_protection_option_t *chProtection)
Set channel protection options, including limit check, short-circuit detector, clock-absence detector, and zero-crossing detector.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
chProtection – Pointer to sinc_channel_protection_option_t, must not be NULL.
-
static inline uint32_t SINC_ReadChannelResultData(SINC_Type *base, sinc_channel_id_t chId)
Read selected channel’s result data.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
- Returns:
Result data of the selected channel, 24 bits width.
-
static inline void SINC_EnableChannelFIFO(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable FIFO transfers for the primary filter.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable channl FIFO:
true Enable channel FIFO.
false Disable channle FIFO.
-
static inline void SINC_SetChannelFifoWatermark(SINC_Type *base, sinc_channel_id_t chId, uint8_t fifoWaterMark)
Set the FIFO watermark.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
fifoWaterMark – Specify the fifo watermark, range from 0 to 15.
-
static inline void SINC_EnableChannel(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable selected channel:
true Enable selected channel;
false Disable selected channel.
-
static inline void SINC_EnableChannelPrimaryDma(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel’s primary DMA transfers when the channel’s FIFO exceeds its watermark.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable primary DMA :
true Enable primary DMA;
false Disable primary DMA.
-
static inline void SINC_SetChannelAltDmaSource(SINC_Type *base, sinc_channel_id_t chId, sinc_alternate_dma_source_t altDmaSource)
Set selected channel’s alternate DMA source selection.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
altDmaSource – Specify the trigger source for alternate DMA, please refer to sinc_alternate_dma_source_t.
-
static inline void SINC_SetChannelResultDataFormat(SINC_Type *base, sinc_channel_id_t chId, sinc_result_data_format_t dataFormat)
Set selected channel’s result data format.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
dataFormat – Specify the result data format, please refer to sinc_result_data_format_t.
-
static inline uint8_t SINC_GetChannelFifoCount(SINC_Type *base, sinc_channel_id_t chId)
Get the number of remaining data entries in the FIFO.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
- Returns:
The number of remaining data entries in the FIFO.
-
static inline bool SINC_CheckChannelResultDataReady(SINC_Type *base, sinc_channel_id_t chId)
Check whether the data in selected channel’s result data register is stable when FIFO is disabled.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Data in selected channel’s result data regiter is stable.
false – Data in selected channel’s result data register is not stable.
-
static inline bool SINC_CheckChannelFifoEmpty(SINC_Type *base, sinc_channel_id_t chId)
Check whether selected channel’s FIFO is empty.
- Parameters:
base – SINC peripheral base address.
chId – The id of sinc channel to check.
- Return values:
true – Selected channel’s FIFO is empty.
false – Selected channel’s FIFO is not empty.
-
static inline void SINC_AffirmChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)
Trigger selected channel’s conversion.
- Parameters:
base – SINC peripheral base address.
chMask – The mask of channels to trigger.
-
static inline void SINC_NegateChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)
Negate the trigger of selected channel.
- Parameters:
base – SINC peripheral base address.
chMask – The mask of channels.
-
static inline void SINC_SetChannelConversionMode(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_mode_t mode)
Set selected channel’s conversion mode.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
mode – The conversion mode to set, please refer to sinc_conv_mode_t.
-
static inline void SINC_SetChannelTriggerSource(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_trigger_source_t triggerSource)
Set selected channel’s trigger source.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
triggerSource – Trigger source to set, please refer to sinc_conv_trigger_source_t.
-
static inline void SINC_SetChannelMultipurposeData(SINC_Type *base, sinc_channel_id_t chId, uint32_t data)
Set multipurpose data to selected channel.
Note
If input bit format is set as ManchesterCode, multipurpose data indicates the Manchester decoder threshold value and is 11 bits width; if input bit format is set as parallel, multipurpose data indicates the parallel 16-bit data and is 16 bits width; if input bit format is set as serial, multipurpose data indicates the serial data and is 32 bits width.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
data – Multipurpose data to set.
-
static inline void SINC_SetChannelPfOrder(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_order_t pfOrder)
Set selected channel’s PF order.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pfOrder – Primary filter order to set, please refer to sinc_primary_filter_order_t
-
static inline void SINC_SetChannelPfOsr(SINC_Type *base, sinc_channel_id_t chId, uint16_t pfOsr)
Set selected channel’s PF over sample rate.
Note
If PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pfOsr – Control the channel’s PF OSR, the minimum permissible value is 3, low value produce unpredictable result, the maximum permissible value depend on PF order and the desired data format.
-
static inline void SINC_SetChannelPfHpfAlphaCoeff(SINC_Type *base, sinc_channel_id_t chId, sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff)
set selected channel’s HPF DC remover Alpha coefficient.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pfHpfAlphaCoeff – Specify the HPF alpha coefficient or disable HPF as described in sin_primary_filter_hpf_alpha_coeff_t.
-
static inline void SINC_SetChannelPfShiftConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_shift_direction_t pfShiftDirection, uint8_t pfShiftBitsNum)
Set the value that shifts the PF data for the correct 24-bit precision.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pfShiftDirection – Specify the PF shift direction, including right and left.
pfShiftBitsNum – Specify the PF shift value, range from 0 to 15.
-
static inline void SINC_SetChannelPfBiasConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_bias_sign_t pfBiasSign, uint32_t pfBiasValue)
Set the bias offset for the selected channel’s PF.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pfBiasSign – Specify the bias sign, please refer to sinc_primary_filter_bias_sign_t for details.
pfBiasValue – The bias value to subtracted from the output of PF shift block, range from 0 to 0x7FFFFFUL.
-
static inline void SINC_EnableChannelPrimaryFilter(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel’s primary filter.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable primary filter:
true Enable channel’s PF;
false Disable channel’s PF.
-
static inline bool SINC_CheckChannelParallelSerialDataReady(SINC_Type *base, sinc_channel_id_t chId)
Check whether selected channel’s multipurpose data is ready to write parallel or serial data.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Selected channel’s multipurpose data is ready to write parallel or serial data.
false – Selected channel’s multipurpose data is not ready to write parallel or serial data.
-
static inline bool SINC_CheckChannelPrimaryCICSaturation(SINC_Type *base, sinc_channel_id_t chId)
Check whether primary CIC filter saturation occurred.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Selected channel’s primary CIC filter saturation occurred.
false – Selected channel’s primary CIC filter saturation did not occurred.
-
static inline bool SINC_CheckChannelHPFSaturation(SINC_Type *base, sinc_channel_id_t chId)
Check whether HPF saturation occurred.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Selected channel’s HPF saturation occurred.
false – Selected channel’s HPF saturation did not occurred.
-
static inline bool SINC_CheckChannelShiftSaturation(SINC_Type *base, sinc_channel_id_t chId)
Check whether Shift saturation occurred.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Selected channel’s shift saturation occurred.
false – Selected channel’s shift saturation did not occurred.
-
static inline bool SINC_CheckChannelBiasSaturation(SINC_Type *base, sinc_channel_id_t chId)
Check whether bias saturation occurred.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Return values:
true – Selected channel’s bias saturation occurred.
false – Selected channel’s bias saturation did not occurred.
-
uint8_t SINC_GetChannelConversionCount(SINC_Type *base, sinc_channel_id_t chId)
Get selected channel’s number of conversions.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, refer to sinc_channel_id_t for details.
- Returns:
uint8_t Selected channel’s number of conversions.
-
static inline bool SINC_CheckChannelConvProgress(SINC_Type *base, sinc_channel_id_t chId)
Check whether the selected channel is in conversion.
- Parameters:
base – SINC peripheral base address.
chId – The id of sinc channel to check.
- Return values:
false – Selected channel conversion not in progress.
true – Selected channel conversion in progress.
-
static inline bool SINC_CheckChannelReadyForConv(SINC_Type *base, sinc_channel_id_t chId)
Check whether the selected channel is ready for conversion.
- Parameters:
base – SINC peripheral base address.
chId – The id of sinc channel to check.
- Return values:
true – Selected channel is ready for conversion.
false – Selected channel is not ready for conversion.
-
static inline void SINC_SetChannelLowLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t lowLimitThreshold)
Set selected channel’s low-limit threshold value.
Note
When the data exceeds the low-limit threshold value, a low-limit event occurs, and the limit threshold format is determines by channel’s result data format sinc_result_data_format_t.
Note
Low limit value must lower than high limit value, otherwise the low-limit threshold does not work.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
lowLimitThreshold – Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL.
-
static inline void SINC_SetChannelHighLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t highLimitThreshold)
Set selected channel’s high-limit threshold value.
Note
When the data exceeds the high-limit threshold value, a high-limit event occurs, and the limit threshold format is determines by channel’s result data format sinc_result_data_format_t.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
highLimitThreshold – Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL.
-
static inline void SINC_SetChannelLimitDetectorMode(SINC_Type *base, sinc_channel_id_t chId, sinc_limit_detector_mode_t mode)
Set selected channel’s limit detector mode.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
mode – Specify the mode of limit detector, please refer to sinc_limit_detector_mode_t.
-
static inline void SINC_EnableChannelHighLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel’s high limit break signal.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable high limit break signal:
true Enable the automatic assertion of the BREAK_HIGH signal when SINC detects a high-limit event on the selected channel.
false Disable high limit break signal.
-
static inline void SINC_EnableChannelWindowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel’s window limit break signal.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable window limit break signal:
true Enable the automatic assertion of the BREAK_WIN signal when SINC detects a window-limit event on the selected channel.
false Disable window limit break signal.
-
static inline void SINC_EnableChannelLowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable selected channel’s low limit break signal.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable low limit break signal:
true Enable the automatic assertion of the BREAK_LOW signal when SINC detects a low-limit event on the selected channel.
false Disable low limit break signal.
-
static inline void SINC_SetChannelScdOperateMode(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_operate_mode_t opMode)
Set selected channel’s short-circuit detector operate mode.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
opMode – Specify the operate mode to set, please refer to sinc_scd_operate_mode_t.
-
static inline void SINC_SetChannelScdLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint8_t u8ScdLimitThreshold)
Set selected channel’s Scd limit threshold.
Note
The SCD counter tracks the number of received bits with the same repeating value(always 0 or always 1, set by
SINC_SetChannelScdOption()), if that number exceeds the scdLimitThreshold, an SCD event occurs on the associated channel.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
u8ScdLimitThreshold – Specify the threshold value for the SCD counter, range from 2 to 255.
-
static inline void SINC_SetChannelScdOption(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_option_t option)
Set selected channel’s SDC option.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
option – Specify which repeating bit value increments the SCD counter.
-
static inline void SINC_EnableChannelScdBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable the automatic assertion of the BREAK_SCD signal when SINC detects an SCD event on the selected channel.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disable SCD break signal:
true Enable SCD break signal.
false Disable SCD break signal.
-
static inline void SINC_SetChannelCadLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, sinc_cad_threshold_t cadLimitThreshold)
Set the threshold value for the CAD counter.
Note
The CAD counter tracks the number of clock cycles during which SINC does not detect a clock, if that number exceeds the threshold value, a CAD event occurs on the selected channel.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
cadLimitThreshold – Specify the threshold value for the CAD counter, please refer to sinc_cad_threshold_t.
-
static inline void SINC_EnableChannelCadBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
Enable/disable the automatic assertion of the BREAK_CAD signal when SINC detects a CAD event on the assoicated channel.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
enable – Used to enable/disble CAD break signal:
true Enable selected channel’s CAD break signal;
false Disable selected channel’s CAD break signal.
-
static inline void SINC_SetChannelZcdOperateMode(SINC_Type *base, sinc_channel_id_t chId, sinc_zero_cross_operate_mode_t opMode)
Set selected channel’s zero-crossing detector operate mode.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
opMode – Specify the operate mode, please refer to sinc_zero_cross_operate_mode_t.
-
static inline void SINC_SetChannelPulseTriggerMux(SINC_Type *base, sinc_channel_id_t chId, sinc_pulse_trigger_mux_t pulseTrigMux)
Set selected channel’s pulse trigger mux.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
pulseTrigMux – Used to selected the signal for pulse-trigger output.
-
static inline void SINC_SetChannelDebugOutput(SINC_Type *base, sinc_channel_id_t chId, sinc_debug_output_t debugOutput)
Set selected channel’s debug output.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
debugOutput – Used to select debug output, please refer to sinc_debug_output_t.
-
static inline void SINC_LatchChannelDebugProceduce(SINC_Type *base, sinc_channel_id_t chId)
Start selected channel’s debug data latch proceduce.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
-
static inline bool SINC_CheckChannelDebugDataValid(SINC_Type *base, sinc_channel_id_t chId)
Check if the selected channel’s debug data is valid.
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
- Return values:
true – Data is valid.
false – Data is invalid.
-
static inline uint32_t SINC_GetChannelDebugData(SINC_Type *base, sinc_channel_id_t chId)
Return selected channel’s the debug data that requested by SINC_SetChannelDebugOutput().
- Parameters:
base – SINC peripheral base address.
chId – Selected channel id, please refer to sinc_channel_id_t.
- Returns:
Selected channel’s debug data.
-
static inline void SINC_EnableInterrupts(SINC_Type *base, uint64_t interruptMasks)
Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on.
- Parameters:
base – SINC peripheral base address.
interruptMasks – Mask of interrupts to enable, should be the OR’ed value of sinc_interrupt_enable_t.
-
static inline void SINC_DisableInterrupts(SINC_Type *base, uint64_t interruptMasks)
Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on.
- Parameters:
base – SINC peripheral base address.
interruptMasks – Mask of interrupts to disable, should be the OR’ed value of sinc_interrupt_enable_t.
-
static inline uint64_t SINC_GetInterruptStatus(SINC_Type *base)
Get interrupt status flags.
- Parameters:
base – SINC peripheral base address.
- Returns:
SINC module’s interrupt status flags, the OR’ed value of sinc_interrupt_status_t.
-
static inline void SINC_ClearInterruptStatus(SINC_Type *base, uint64_t statusMasks)
Clear selected mask of interrupt status flags.
- Parameters:
base – SINC peripheral base address.
statusMasks – The mask of interrupt status flags to clear, should be the OR’ed value of sinc_interrupt_status_t.
-
FSL_SINC_DRIVER_VERSION
lower_component_name driver version 2.1.5.
-
enum _sinc_interrupt_enable
The enumeration of SINC module’s interrupts. .
Values:
-
enumerator kSINC_CH0ConvCompleteIntEnable
-
enumerator kSINC_CH1ConvCompleteIntEnable
-
enumerator kSINC_CH2ConvCompleteIntEnable
-
enumerator kSINC_CH3ConvCompleteIntEnable
-
enumerator kSINC_CH0DataReadyIntEnable
-
enumerator kSINC_CH1DataReadyIntEnable
-
enumerator kSINC_CH2DataReadyIntEnable
-
enumerator kSINC_CH3DataReadyIntEnable
-
enumerator kSINC_CH0ZeroCrossDetectedIntEnable
-
enumerator kSINC_CH1ZeroCrossDetectedIntEnable
-
enumerator kSINC_CH2ZeroCrossDetectedIntEnable
-
enumerator kSINC_CH3ZeroCrossDetectedIntEnable
-
enumerator kSINC_CH0SCDIntEnable
-
enumerator kSINC_CH1SCDIntEnable
-
enumerator kSINC_CH2SCDIntEnable
-
enumerator kSINC_CH3SCDIntEnable
-
enumerator kSINC_CH0WindowLimitIntEnable
-
enumerator kSINC_CH1WindowLimitIntEnable
-
enumerator kSINC_CH2WindowLimitIntEnable
-
enumerator kSINC_CH3WindowLimitIntEnable
-
enumerator kSINC_CH0LowLimitIntEnable
-
enumerator kSINC_CH1LowLimitIntEnable
-
enumerator kSINC_CH2LowLimitIntEnable
-
enumerator kSINC_CH3LowLimitIntEnable
-
enumerator kSINC_CH0HighLimitIntEnable
-
enumerator kSINC_CH1HighLimitIntEnable
-
enumerator kSINC_CH2HighLimitIntEnable
-
enumerator kSINC_CH3HighLimitIntEnable
-
enumerator kSINC_CH0FifoUnderflowIntEnable
-
enumerator kSINC_CH1FifoUnderflowIntEnable
-
enumerator kSINC_CH2FifoUnderflowIntEnable
-
enumerator kSINC_CH3FifoUnderflowIntEnable
-
enumerator kSINC_CH0FifoOverflowIntEnable
-
enumerator kSINC_CH1FifoOverflowIntEnable
-
enumerator kSINC_CH2FifoOverflowIntEnable
-
enumerator kSINC_CH3FifoOverflowIntEnable
-
enumerator kSINC_CH0CADIntEnable
-
enumerator kSINC_CH1CADIntEnable
-
enumerator kSINC_CH2CADIntEnable
-
enumerator kSINC_CH3CADIntEnable
-
enumerator kSINC_CH0SaturationIntEnable
-
enumerator kSINC_CH1SaturationIntEnable
-
enumerator kSINC_CH2SaturationIntEnable
-
enumerator kSINC_CH3SaturationIntEnable
-
enumerator kSINC_CH0ConvCompleteIntEnable
-
enum _sinc_interrupt_status
The enumeration of SINC interrupt status flags. .
Values:
-
enumerator kSINC_CH0ConvCompleteIntStatus
-
enumerator kSINC_CH1ConvCompleteIntStatus
-
enumerator kSINC_CH2ConvCompleteIntStatus
-
enumerator kSINC_CH3ConvCompleteIntStatus
-
enumerator kSINC_CH0DataReadyIntStatus
-
enumerator kSINC_CH1DataReadyIntStatus
-
enumerator kSINC_CH2DataReadyIntStatus
-
enumerator kSINC_CH3DataReadyIntStatus
-
enumerator kSINC_CH0ZeroCrossDetectedIntStatus
-
enumerator kSINC_CH1ZeroCrossDetectedIntStatus
-
enumerator kSINC_CH2ZeroCrossDetectedIntStatus
-
enumerator kSINC_CH3ZeroCrossDetectedIntStatus
-
enumerator kSINC_CH0SCDIntStatus
-
enumerator kSINC_CH1SCDIntStatus
-
enumerator kSINC_CH2SCDIntStatus
-
enumerator kSINC_CH3SCDIntStatus
-
enumerator kSINC_CH0WindowLimitIntStatus
-
enumerator kSINC_CH1WindowLimitIntStatus
-
enumerator kSINC_CH2WindowLimitIntStatus
-
enumerator kSINC_CH3WindowLimitIntStatus
-
enumerator kSINC_CH0LowLimitIntStatus
-
enumerator kSINC_CH1LowLimitIntStatus
-
enumerator kSINC_CH2LowLimitIntStatus
-
enumerator kSINC_CH3LowLimitIntStatus
-
enumerator kSINC_CH0HighLimitIntStatus
-
enumerator kSINC_CH1HighLimitIntStatus
-
enumerator kSINC_CH2HighLimitIntStatus
-
enumerator kSINC_CH3HighLimitIntStatus
-
enumerator kSINC_CH0FifoUnderflowIntStatus
-
enumerator kSINC_CH1FifoUnderflowIntStatus
-
enumerator kSINC_CH2FifoUnderflowIntStatus
-
enumerator kSINC_CH3FifoUnderflowIntStatus
-
enumerator kSINC_CH0FifoOverflowIntStatus
-
enumerator kSINC_CH1FifoOverflowIntStatus
-
enumerator kSINC_CH2FifoOverflowIntStatus
-
enumerator kSINC_CH3FifoOverflowIntStatus
-
enumerator kSINC_CH0CADIntStatus
-
enumerator kSINC_CH1CADIntStatus
-
enumerator kSINC_CH2CADIntStatus
-
enumerator kSINC_CH3CADIntStatus
-
enumerator kSINC_CH0SaturationIntStatus
-
enumerator kSINC_CH1SaturationIntStatus
-
enumerator kSINC_CH2SaturationIntStatus
-
enumerator kSINC_CH3SaturationIntStatus
-
enumerator kSINC_CH0ConvCompleteIntStatus
-
enum _sinc_channel_id
The enumeration of channel id, the sinc module contains 4 channels.
Values:
-
enumerator kSINC_Channel0
Channel 0.
-
enumerator kSINC_Channel1
Channel 1.
-
enumerator kSINC_Channel2
Channel 2.
-
enumerator kSINC_Channel3
Channel 3.
-
enumerator kSINC_Channel0
-
enum _sinc_modulator_clock
The enumeration of modulator clock name. .
Values:
-
enumerator kSINC_ModClk0
Modulator Clock 0 output.
-
enumerator kSINC_ModClk1
Modulator Clock 1 output.
-
enumerator kSINC_ModClk2
Modulator Clock 2 output.
-
enumerator kSINC_ModClk0
-
enum _sinc_inputClk_source
The enumeration of input clock.
Values:
-
enumerator kSINC_InputClk_SourceMclkOut0
MCLK_OUT0 with internal routeback.
-
enumerator kSINC_InputClk_SourceMclkOut1
MCLK_OUT1 with internal routeback.
-
enumerator kSINC_InputClk_SourceMclkOut2
MCLK_OUT2 with internal routeback.
-
enumerator kSINC_InputClk_SourceExternalModulatorClk
External modulator clock dedicated to the selected channel.
-
enumerator kSINC_InputClk_SourceAdjacentChannelClk
Grouped clock shared with an adjacent channel.
-
enumerator kSINC_InputClk_SourceMclkOut0
-
enum _sinc_inputClk_edge
The enumeration of clock edge.
Values:
-
enumerator kSINC_InputClk_EdgePositive
Positive edge.
-
enumerator kSINC_InputClk_EdgeNegative
Negative edge.
-
enumerator kSINC_InputClk_EdgeBoth
Both edges.
-
enumerator kSINC_InputClk_EdgeOddPositive
Every other odd positive edge.
-
enumerator kSINC_InputClk_EdgeEvenPositive
Every other even positive edge.
-
enumerator kSINC_InputClk_EdgeOddNegative
Every other odd negative edge.
-
enumerator kSINC_InputClk_EdgeEvenNegative
Every other even negative edge.
-
enumerator kSINC_InputClk_EdgePositive
-
enum _sinc_inputBit_format
The enumeration of input bit format.
Values:
-
enumerator kSINC_InputBit_FormatExternalBitstream
External bitstream from the MBIT[n] signal.
-
enumerator kSINC_InputBit_FormatExternalManchesterCode
External Manchester code.
-
enumerator kSINC_InputBit_FormatInternal16bitParallelData
Internal 16-bit parallel data from MPDATA register.
-
enumerator kSINC_InputBit_FormatInternal32bitSerialData
Internal 32-bit serial data from MPDATA.
-
enumerator kSINC_InputBit_FormatExternalBitstream
-
enum _sinc_inputBit_source
The enumeration of input bit source.
Values:
-
enumerator kSINC_InputBit_SourceExternalBitstream
External bitstream from the MBIT[n] signal.
-
enumerator kSINC_InputBit_SourceInternalBitstream
Alternate internal bitstream from the INP[n] signal.
-
enumerator kSINC_InputBit_SourceAdjacentChannel
Grouped bitstream shared with an adjacent chanel.
-
enumerator kSINC_InputBit_SourceExternalBitstream
-
enum _sinc_conv_trigger_source
The enumeration of trigger source.
Values:
-
enumerator kSINC_ConvTrig_SoftPosEdge
Positive edge software trigger.
-
enumerator kSINC_ConvTrig_SoftHighLevel
High level software trigger.
-
enumerator kSINC_ConvTrig_HardPosEdge
Positive edge hardware trigger.
-
enumerator kSINC_ConvTrig_HardHighLevel
High level hardware trigger.
-
enumerator kSINC_ConvTrig_AdjacentChannel
Grouped hardware trigger shared with an adjacent channel.
-
enumerator kSINC_ConvTrig_SoftPosEdge
-
enum _sinc_conv_mode
The enumeration of conversion mode.
Values:
-
enumerator kSINC_ConvMode_Single
One conversion that follows an edge or level trigger event.
-
enumerator kSINC_ConvMode_Continuous
Multiple conversions that follow a triggering event, a new triggering event cancels and restarts conversion.
-
enumerator kSINC_ConvMode_Always
Multiple conversions that follow the first triggering event, SINC ignores the next triggering event.
-
enumerator kSINC_ConvMode_FixedNumber
Fixed number conversions that follow the first triggering event, a new triggering event cancels and restarts conversion.
-
enumerator kSINC_ConvMode_Single
-
enum _sinc_pulse_trigger_mux
The enumeration of pulse trigger mux.
Values:
-
enumerator kSINC_PulseTrigger_Disabled
Disable pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxHighLimitLevelSignal
Select high limit level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxLowLimitLevelSignal
Select low limit level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxHighLowLimitLevelSignal
Select low or high limit level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxWindowLimitLevelSignal
Select window limit level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxZeroCrossRisingLevelSignal
Select zero cross rising level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxZeroCrossFallingLevelSignal
Select zero cross falling level signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxRsLimHighLevelSignal
Select level signal that indicates a high level from an RS flip-flop or a schmitt trigger for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxRsLimLowLevelSignal
Select level signal that indicates a low level from an RS flip-flop or a schmitt trigger for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxChannelRawInputModBitStream
Select channel raw input modulator bitstream for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxChannelRawInputModClock
Select channel raw input modulator clock for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxChannelRecoveredModBitStream
Select channel output recovered modulator bitstream for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxChannelRecoveredModClock
Select channel output recovered modulator clock for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxHighLimitPulseSignal
Select high limit pulse signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxLowLimitPulseSignal
Select low limit pulse signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxLimitPulseSignal
Select the pulse signal that indicates a high/low/window limit for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxWindowLimitPulseSignal
Select window limit pulse signal for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxHighLowLimitPulseSignal
Select the pulse signal that indicates a high or low limit for pulse trigger output.
-
enumerator kSINC_PulseTrigger_MuxZeroCrossRisePulseSignal
Select zero cross rise pulse signal for trigger output.
-
enumerator kSINC_PulseTrigger_MuxZeroCrossFallPulseSignal
Select zero cross fall pulse signal for trigger output.
-
enumerator kSINC_PulseTrigger_MuxZeroCrossRiseFallPulseSignal
Select zero cross rise/fall pulse signal for trigger output.
-
enumerator kSINC_PulseTrigger_MuxFifoWatermarkOkPulseSignal
Select FIFO watermark OK pulse signal for trigger output.
-
enumerator kSINC_PulseTrigger_MuxFifoOverflowPulseSignal
Select FIFO overflow pulse signal.
-
enumerator kSINC_PulseTrigger_MuxFifoUnderflowPulseSignal
Select FIFO underflow pulse signal.
-
enumerator kSINC_PulseTrigger_MuxFifoEmptyPulseSignal
Select FIFO empty pulse signal.
-
enumerator kSINC_PulseTrigger_MuxClockMonitorAssertPulseSignal
Select clock monitor assert pulse signal.
-
enumerator kSINC_PulseTrigger_MuxShortCircuitAssertPulseSignal
Select short circuit assert pulse signal.
-
enumerator kSINC_PulseTrigger_MuxSaturationPulseSignal
Select saturation pulse signal.
-
enumerator kSINC_PulseTrigger_MuxConversionCompletePulseSignal
Select conversion complete pulse signal.
-
enumerator kSINC_PulseTrigger_Disabled
-
enum _sinc_zero_cross_operate_mode
The enumeration of zero cross detector operate mode.
Values:
-
enumerator kSINC_ZCD_BothRiseAndFall
Zero cross detector operate on both rise and fall.
-
enumerator kSINC_ZCD_OnlyFall
Zero cross detector operate on fall edge.
-
enumerator kSINC_ZCD_OnlyRise
Zero cross detector operate on rise edge.
-
enumerator kSINC_ZCD_Disabled
Zero cross detector disabled.
-
enumerator kSINC_ZCD_BothRiseAndFall
-
enum _sinc_primary_filter_order
The enumeration of primary filter order.
Values:
-
enumerator kSINC_PF_FastSinc
Fast sinc filter, ORD is 4.
-
enumerator kSINC_PF_FirstOrder
First order filter, ORD is 1.
-
enumerator kSINC_PF_SecondOrder
Second order filter, ORD is 2.
-
enumerator kSINC_PF_ThirdOrder
Third order filter, ORD is 3.
-
enumerator kSINC_PF_FastSinc
-
enum _sinc_clock_prescale
The enumeration of clock prescale that specify the clock divider ratio for the modulator clock.
Values:
-
enumerator kSINC_ClkPrescale1
No prescale.
-
enumerator kSINC_ClkPrescale2
Modulator clock divider ratio is 2.
-
enumerator kSINC_ClkPrescale4
Modulator clock divider ratio is 4.
-
enumerator kSINC_ClkPrescale8
Modulator clock divider ratio is 8.
-
enumerator kSINC_ClkPrescale1
-
enum _sinc_primary_filter_shift_direction
The enumeration of primary filter shift direction.
Values:
-
enumerator kSINC_PF_ShiftRight
Right shift the raw data.
-
enumerator kSINC_PF_ShiftLeft
Left shift the raw data.
-
enumerator kSINC_PF_ShiftRight
-
enum _sinc_primary_filter_bias_sign
The enumeration of primary filer bias sign.
Values:
-
enumerator kSINC_PF_BiasPositive
The bias sign is positive.
-
enumerator kSINC_PF_BiasNegative
The bias sign is negative.
-
enumerator kSINC_PF_BiasPositive
-
enum _sinc_primary_filter_hpf_alpha_coeff
The enumeration of HPF DC remover Alpha coefficient.
Values:
-
enumerator kSINC_PF_HPFAlphaCoeff0
Disabled HPF.
-
enumerator kSINC_PF_HPFAlphaCoeff1
Alpha coefficient = 1 - (2^-5)
-
enumerator kSINC_PF_HPFAlphaCoeff2
Alpha coefficient = 1 - (2^-6)
-
enumerator kSINC_PF_HPFAlphaCoeff3
Alpha coefficient = 1 - (2^-7)
-
enumerator kSINC_PF_HPFAlphaCoeff4
Alpha coefficient = 1 - (2^-8)
-
enumerator kSINC_PF_HPFAlphaCoeff5
Alpha coefficient = 1 - (2^-9)
-
enumerator kSINC_PF_HPFAlphaCoeff6
Alpha coefficient = 1 - (2^-10)
-
enumerator kSINC_PF_HPFAlphaCoeff7
Alpha coefficient = 1 - (2^-11)
-
enumerator kSINC_PF_HPFAlphaCoeff8
Alpha coefficient = 1 - (2^-12)
-
enumerator kSINC_PF_HPFAlphaCoeff9
Alpha coefficient = 1 - (2^-13)
-
enumerator kSINC_PF_HPFAlphaCoeff10
Alpha coefficient = 1 - (2^-14)
-
enumerator kSINC_PF_HPFAlphaCoeff11
Alpha coefficient = 1 - (2^-15)
-
enumerator kSINC_PF_HPFAlphaCoeff12
Alpha coefficient = 1 - (2^-16)
-
enumerator kSINC_PF_HPFAlphaCoeff13
Alpha coefficient = 1 - (2^-17)
-
enumerator kSINC_PF_HPFAlphaCoeff14
Alpha coefficient = 1 - (2^-18)
-
enumerator kSINC_PF_HPFAlphaCoeff15
Alpha coefficient = 1 - (2^-19)
-
enumerator kSINC_PF_HPFAlphaCoeff0
-
enum _sinc_inputBit_delay
The enumeration of input bit delay.
Values:
-
enumerator kSINC_InputBit_DelayDisabled
Input modulator bitstream delay disabled.
-
enumerator kSINC_InputBit_Delay1ClkCycle
Input modulator bitstream delay 1 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay2ClkCycle
Input modulator bitstream delay 2 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay3ClkCycle
Input modulator bitstream delay 3 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay4ClkCycle
Input modulator bitstream delay 4 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay5ClkCycle
Input modulator bitstream delay 5 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay6ClkCycle
Input modulator bitstream delay 6 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay7ClkCycle
Input modulator bitstream delay 7 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay8ClkCycle
Input modulator bitstream delay 8 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay9ClkCycle
Input modulator bitstream delay 9 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay10ClkCycle
Input modulator bitstream delay 10 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay11ClkCycle
Input modulator bitstream delay 11 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay12ClkCycle
Input modulator bitstream delay 12 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay13ClkCycle
Input modulator bitstream delay 13 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay14ClkCycle
Input modulator bitstream delay 14 PRE_CLK cycle.
-
enumerator kSINC_InputBit_Delay15ClkCycle
Input modulator bitstream delay 15 PRE_CLK cycle.
-
enumerator kSINC_InputBit_DelayDisabled
-
enum _sinc_scd_operate_mode
The enumeration of short-circuit detector operate mode.
Values:
-
enumerator kSINC_Scd_OperateAtChannelEnabled
SCD operates when the channel is enabled.
-
enumerator kSINC_Scd_OperateAtConversion
SCD operates when the PF is performing a conversion.
-
enumerator kSINC_Scd_OperateDisabled
Short circuit detect is disabled.
-
enumerator kSINC_Scd_OperateAtChannelEnabled
-
enum _sinc_scd_option
The enumeration of short-circuit detector option.
Values:
-
enumerator kSINC_Scd_DetectRepeating0And1
Both repeating 0 and 1 increment the SCD counter.
-
enumerator kSINC_Scd_DetectRepeatingOnly1
Only repeating 1 increment the SCD counter.
-
enumerator kSINC_Scd_DetectRepeatingOnly0
Only repeating 1 increment the SCD counter.
-
enumerator kSINC_Scd_DetectRepeating0And1
-
enum _sinc_limit_detector_mode
The mode of limit detector.
Note
The value of each limit detector contains lot of information: bit[1:0]: limit detection options, bit[2]: low limit break signal. bit[3]: window limit break signal. bit[4]: High limit break signal. bit[7]: Enable/disable limit detector.
Values:
-
enumerator kSINC_Lmt_BothHighAndLowLimit
Limit detector is enabled, and compare the filter sample value to high and low limit, if the value larger than high limit will trigger interrupt or break, and if the value lower than low limit will trigger interrupt or break.
-
enumerator kSINC_Lmt_OnlyHighLimit
Limit detector is enabled, and compare the filter sample value to high limit, if the value larger than high limit will trigger interrupt or break.
-
enumerator kSINC_Lmt_OnlyLowLimit
Limit detector is enabled, and compare the filter sample value to low limit, if the value lower than low limit will trigger interrupt or break.
-
enumerator kSINC_Lmt_WindowedValue
Limit detector is enabled, and compare the filter sample value to high and low limit, if the value higher than low limit and lower than high limit will trigger interrupt or break.
-
enumerator kSINC_Lmt_Disabled
Limit detector is disabled.
-
enumerator kSINC_Lmt_BothHighAndLowLimit
-
enum _sinc_cad_threshold
The enumeration of clock-absence threshold.
Values:
-
enumerator kSINC_Cad_Disabled
Clock absence detector is disabled.
-
enumerator kSINC_Cad_Count1ClkCycle
Clock absence detector threshold is 1 clock cycle.
-
enumerator kSINC_Cad_Count2ClkCycle
Clock absence detector threshold is 2 clock cycle.
-
enumerator kSINC_Cad_Count3ClkCycle
Clock absence detector threshold is 3 clock cycle.
-
enumerator kSINC_Cad_Count4ClkCycle
Clock absence detector threshold is 4 clock cycle.
-
enumerator kSINC_Cad_Count5ClkCycle
Clock absence detector threshold is 5 clock cycle.
-
enumerator kSINC_Cad_Count6ClkCycle
Clock absence detector threshold is 6 clock cycle.
-
enumerator kSINC_Cad_Count7ClkCycle
Clock absence detector threshold is 7 clock cycle.
-
enumerator kSINC_Cad_Count8ClkCycle
Clock absence detector threshold is 8 clock cycle.
-
enumerator kSINC_Cad_Count9ClkCycle
Clock absence detector threshold is 9 clock cycle.
-
enumerator kSINC_Cad_Count10ClkCycle
Clock absence detector threshold is 10 clock cycle.
-
enumerator kSINC_Cad_Count11ClkCycle
Clock absence detector threshold is 11 clock cycle.
-
enumerator kSINC_Cad_Count12ClkCycle
Clock absence detector threshold is 12 clock cycle.
-
enumerator kSINC_Cad_Count13ClkCycle
Clock absence detector threshold is 13 clock cycle.
-
enumerator kSINC_Cad_Count14ClkCycle
Clock absence detector threshold is 14 clock cycle.
-
enumerator kSINC_Cad_Count15ClkCycle
Clock absence detector threshold is 15 clock cycle.
-
enumerator kSINC_Cad_Disabled
-
enum _sinc_alternate_dma_source
The enumeration of alternate DMA source.
Values:
-
enumerator kSINC_AltDma_Disabled
Alternate DMA disabled.
-
enumerator kSINC_AltDma_PfConvComplete
Select PF conversion complete for alternate DMA.
-
enumerator kSINC_AltDma_PfDataOutputReady
Select PF data output ready for alternate DMA.
-
enumerator kSINC_AltDma_ZeroCrossDetected
Select zero crossing detected for alternate DMA.
-
enumerator kSINC_AltDma_ShortCircuitDetected
Select short circuit detected for alternate DMA.
-
enumerator kSINC_AltDma_WindowLimitDetected
Select window limit detected for alternate DMA.
-
enumerator kSINC_AltDma_LowLimitDetected
Select low limit detected for alternate DMA.
-
enumerator kSINC_AltDma_HighLimitDetected
Select high limit detected for alternate DMA.
-
enumerator kSINC_AltDma_FifoUnderflow
Select FIFO underflow detected for alternate DMA.
-
enumerator kSINC_AltDma_FifoOverflow
Select FIFO overflow detected for alternate DMA.
-
enumerator kSINC_AltDma_ClockAbsence
Select clock absence detected for alternate DMA.
-
enumerator kSINC_AltDma_Saturation
Select channel saturation for alternate DMA.
-
enumerator kSINC_AltDma_Disabled
-
enum _sinc_result_data_format
The enumeration of result data format.
Values:
-
enumerator kSINC_LeftJustifiedSigned
Left justified, signed.
-
enumerator kSINC_LeftJustifiedUnsigned
Left justified, unsigned.
-
enumerator kSINC_LeftJustifiedSigned
-
enum _sinc_debug_output
The enumeration of debug output.
Values:
-
enumerator kSINC_Debug_PfFinalData
Final data from PF(24 bits).
-
enumerator kSINC_Debug_OffsetData
Offset data(24 bits).
-
enumerator kSINC_Debug_PfShiftedData
Shifted data from the PF(24 bits).
-
enumerator kSINC_Debug_HpfData
DC remover(HPF) data(32 bits).
-
enumerator kSINC_Debug_CicRawData
Raw data from the PF’s CIC filter.
-
enumerator kSINC_Debug_ScdHistoricalData
Historical data from SCD.
-
enumerator kSINC_Debug_ManchesterDecoderData
Data from the Manchester decoder.
-
enumerator kSINC_Debug_CadData
Data from CAD.
-
enumerator kSINC_Debug_FifoEntriesNum
Number of available entries in the FIFO.
-
enumerator kSINC_Debug_ParallelSerialConverterStatus
Status of the parallel or serial data converter.
-
enumerator kSINC_Debug_PfFinalData
-
typedef enum _sinc_channel_id sinc_channel_id_t
The enumeration of channel id, the sinc module contains 4 channels.
-
typedef enum _sinc_inputClk_source sinc_inputClk_source_t
The enumeration of input clock.
-
typedef enum _sinc_inputClk_edge sinc_inputClk_edge_t
The enumeration of clock edge.
-
typedef enum _sinc_inputBit_format sinc_inputBit_format_t
The enumeration of input bit format.
-
typedef enum _sinc_inputBit_source sinc_inputBit_source_t
The enumeration of input bit source.
-
typedef enum _sinc_conv_trigger_source sinc_conv_trigger_source_t
The enumeration of trigger source.
-
typedef enum _sinc_conv_mode sinc_conv_mode_t
The enumeration of conversion mode.
-
typedef enum _sinc_pulse_trigger_mux sinc_pulse_trigger_mux_t
The enumeration of pulse trigger mux.
-
typedef enum _sinc_zero_cross_operate_mode sinc_zero_cross_operate_mode_t
The enumeration of zero cross detector operate mode.
-
typedef enum _sinc_primary_filter_order sinc_primary_filter_order_t
The enumeration of primary filter order.
-
typedef enum _sinc_clock_prescale sinc_clock_prescale_t
The enumeration of clock prescale that specify the clock divider ratio for the modulator clock.
-
typedef enum _sinc_primary_filter_shift_direction sinc_primary_filter_shift_direction_t
The enumeration of primary filter shift direction.
-
typedef enum _sinc_primary_filter_bias_sign sinc_primary_filter_bias_sign_t
The enumeration of primary filer bias sign.
-
typedef enum _sinc_primary_filter_hpf_alpha_coeff sin_primary_filter_hpf_alpha_coeff_t
The enumeration of HPF DC remover Alpha coefficient.
-
typedef enum _sinc_inputBit_delay sinc_inputBit_delay_t
The enumeration of input bit delay.
-
typedef enum _sinc_scd_operate_mode sinc_scd_operate_mode_t
The enumeration of short-circuit detector operate mode.
-
typedef enum _sinc_scd_option sinc_scd_option_t
The enumeration of short-circuit detector option.
-
typedef enum _sinc_limit_detector_mode sinc_limit_detector_mode_t
The mode of limit detector.
Note
The value of each limit detector contains lot of information: bit[1:0]: limit detection options, bit[2]: low limit break signal. bit[3]: window limit break signal. bit[4]: High limit break signal. bit[7]: Enable/disable limit detector.
-
typedef enum _sinc_cad_threshold sinc_cad_threshold_t
The enumeration of clock-absence threshold.
-
typedef enum _sinc_alternate_dma_source sinc_alternate_dma_source_t
The enumeration of alternate DMA source.
-
typedef enum _sinc_result_data_format sinc_result_data_format_t
The enumeration of result data format.
-
typedef enum _sinc_debug_output sinc_debug_output_t
The enumeration of debug output.
-
typedef struct _sinc_channel_input_option sinc_channel_input_option_t
The structure of channel input options, including input bit settings and input clock settings.
-
typedef struct _sinc_channel_conv_option sinc_channel_conv_option_t
The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings, bias settings and so on.
-
typedef struct _sinc_channel_protection_option sinc_channel_protection_option_t
The structure of channel protection options, including limit check settings, short-circuit settings, clock-absence settings, and zero-crossing settings.
-
typedef struct _sinc_channel_config sinc_channel_config_t
The structure of channel configurations, including channel input option, channel conversion options, channel protection options, and so on.
-
typedef struct _sinc_config sinc_config_t
The structure of sinc configurations, including clock settings anc channels’ settings.
-
SINC_CHANNEL_COUNT
-
SINC_NORMAL_INT_REG_ID
-
SINC_NORMAL_INT_NAME_COCIE
-
SINC_NORMAL_INT_NAME_CHFIE
-
SINC_NORMAL_INT_NAME_ZCDIE
-
SINC_ERROR_INT_REG_ID
-
SINC_ERROR_INT_NAME_SCDIE
-
SINC_ERROR_INT_NAME_WLMTIE
-
SINC_ERROR_INT_NAME_LLMTIE
-
SINC_ERROR_INT_NAME_HLMTIE
-
SINC_FIFO_CAD_INT_REG_ID
-
SINC_FIFO_CAD_INT_FUNFIE
-
SINC_FIFO_CAD_INT_FOVFIE
-
SINC_FIFO_CAD_INT_CADIE
-
SINC_FIFO_CAD_INT_SATIE
-
SINC_ENCODE_INTERRUPT(regId, name, channelId)
-
SINC_DECODE_INTERRUPT(interruptMask)
-
SINC_FIND_INT_FIELD_VALUE(mask, name)
-
SINC_FIND_STATUS_FIELD_VALUE(statusValue, name)
-
struct _sinc_channel_input_option
- #include <fsl_sinc.h>
The structure of channel input options, including input bit settings and input clock settings.
Public Members
-
sinc_inputBit_format_t inputBitFormat
Specify input bit format, please refer to sinc_inputBit_format_t.
-
sinc_inputBit_source_t inputBitSource
Specify input bit source, please refer to sinc_inputBit_source_t.
-
sinc_inputBit_delay_t inputBitDelay
Specify input bit delay, please refer to sinc_inputBit_delay_t.
-
sinc_inputClk_source_t inputClkSource
Specify input clock source, please refer to sinc_inputClk_source_t.
-
sinc_inputClk_edge_t inputClkEdge
Specify input clock edge, please refer to sinc_inputClk_edge_t.
-
sinc_inputBit_format_t inputBitFormat
-
struct _sinc_channel_conv_option
- #include <fsl_sinc.h>
The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings, bias settings and so on.
Public Members
-
sinc_conv_mode_t convMode
Specify conversion mode, please refer to sinc_conv_mode_t.
-
sinc_conv_trigger_source_t convTriggerSource
Specify conversion trigger source, please refer to sinc_conv_trigger_source_t.
-
bool enableChPrimaryFilter
Enable/disable channel’s primary filter.
-
sinc_primary_filter_order_t pfOrder
Specify the order of primary filter, please refer to sinc_primary_filter_order_t.
-
uint16_t u16pfOverSampleRatio
Control primary filter’s OSR, the minimum permissible value is 3, low value produce unpredictable result, the maximum permissible value depend on PF order and the desired data format, if PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047. Please note that the OSR for equation is u16pfOverSampleRatio + 1
-
sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff
Specify HPF’s alpha coeff, please refer to sin_primary_filter_hpf_alpha_coeff_t.
-
sinc_primary_filter_shift_direction_t pfShiftDirection
Select shift direction, right or left.
-
uint8_t u8pfShiftBitsNum
Specify the number of bits to shift the data, ranges from 0 to 15.
-
sinc_primary_filter_bias_sign_t pfBiasSign
Select bias sign, please refer to sinc_primary_filter_bias_sign_t.
-
uint32_t u32pfBiasValue
Range from 0 to 0x7FFFFFUL.
-
sinc_conv_mode_t convMode
-
struct _sinc_channel_protection_option
- #include <fsl_sinc.h>
The structure of channel protection options, including limit check settings, short-circuit settings, clock-absence settings, and zero-crossing settings.
Public Members
-
sinc_limit_detector_mode_t limitDetectorMode
Specify limit detector mode, please refer to sinc_limit_detector_mode_t.
-
bool bEnableLmtBreakSignal
Enable/disable limit break signal, the details of break signal is depended on detector mode.
-
uint32_t u32LowLimitThreshold
Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL.
-
uint32_t u32HighLimitThreshold
Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL.
-
sinc_scd_operate_mode_t scdOperateMode
Enable/disable scd, and set SCD operate timming.
-
uint8_t u8ScdLimitThreshold
Range from 2 to 255, 0 and 1 are prohibited.
-
sinc_scd_option_t scdOption
Specify SCD options, please refer to sinc_scd_option_t.
-
bool bEnableScdBreakSignal
Enable/disable SCD break signal.
-
sinc_cad_threshold_t cadLimitThreshold
Specify the threshold value for the CAD counter.
-
bool bEnableCadBreakSignal
Enable/disable CAD break signal.
-
sinc_zero_cross_operate_mode_t zcdOperateMode
Specify zero cross detector operate mode.
-
sinc_limit_detector_mode_t limitDetectorMode
-
struct _sinc_channel_config
- #include <fsl_sinc.h>
The structure of channel configurations, including channel input option, channel conversion options, channel protection options, and so on.
Public Members
-
bool bEnableChannel
Enable/disable channel.
-
bool bEnableFifo
Enable/disable channel’s FIFO.
-
uint8_t u8FifoWaterMark
Specify the fifo watermark, range from 0 to 15.
-
bool bEnablePrimaryDma
Used to enable/disable primary DMA.
-
sinc_alternate_dma_source_t altDmaSource
Set channel’s alternate DMA source, please refer to sinc_alternate_dma_source_t.
-
sinc_result_data_format_t dataFormat
Set channel’s result data format, please refer to sinc_result_data_format_t.
-
sinc_channel_input_option_t *chInputOption
The pointer to sinc_channel_input_option_t that contains channel input options.
-
sinc_channel_conv_option_t *chConvOption
The pointer to sinc_channel_conv_option_t that contains channel conversion options.
-
sinc_channel_protection_option_t *chProtectionOption
The pointer to sinc_channel_protection_option_t that contains channel protection options.
-
bool bEnableChannel
-
struct _sinc_config
- #include <fsl_sinc.h>
The structure of sinc configurations, including clock settings anc channels’ settings.
Public Members
-
sinc_clock_prescale_t clockPreDivider
Specify modulator clock pre divider, please refer to sinc_clock_prescale_t.
-
uint32_t modClkDivider
Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output, write an even value to
-
bool disableModClk0Output
Disable/enable modulator clock0 output.
-
bool disableModClk1Output
Disable/enable modulator clock1 output.
-
bool disableModClk2Output
Disable/enable modulator clock2 output.
-
sinc_channel_config_t *channelsConfigArray[(1)]
The array that contains 4 elements, and the type of each element is sinc_channel_config_t *, channelsConfigArray[0] corresponding to channel0, channelsConfigArray[1] corresponding to channel1, channelsConfigArray[2] corresponding to channel2, channelsConfigArray[3] corresponding to channel3, if some channels are not used, the corresponding elements should be set as NULL.
-
bool disableDozeMode
Disable/enable SINC module when the chip enters Doze or stop mode.
-
bool enableMaster
Enable/disable all function blocks of SINC module.
-
sinc_clock_prescale_t clockPreDivider
SOC_SRC Driver
-
enum _src_core_name
System core.
Values:
-
enumerator kSRC_CM33Core
System Core CM33.
-
enumerator kSRC_CM7Core
System Core CM7.
-
enumerator kSRC_CM33Core
-
enum _src_boot_fuse_selection
The enumeration of the boot fuse selection.
Values:
-
enumerator kSRC_SerialDownloaderBootFlow
The Boot flow jumps directly to the serial downloader.
-
enumerator kSRC_NormalBootFlow
The Boot flow follows the Normal Boot flow.
-
enumerator kSRC_SerialDownloaderBootFlow
-
enum _src_reset_source
The enumeration of global system reset sources.
Values:
-
enumerator kSRC_Wdog1Reset
WDOG1 triggers the global system reset.
-
enumerator kSRC_Wdog2Reset
WDOG2 triggers the global system reset.
-
enumerator kSRC_Wdog3Reset
WDOG3 triggers the global system reset.
-
enumerator kSRC_Wdog4Reset
WODG4 triggers the global system reset.
-
enumerator kSRC_Wdog5Reset
WDOG5 triggers the global system reset.
-
enumerator kSRC_TempsenseReset
Tempsense trigggers the global system reset.
-
enumerator kSRC_SentinelReset
Sentiel trigggers the global system reset.
-
enumerator kSRC_JtagSoftwareReset
JTAG software triggers the global system reset.
-
enumerator kSRC_CM33LockUpReset
CM33 lockup triggers the global system reset.
-
enumerator kSRC_CM33RequestReset
CM33 request triggers the global system reset.
-
enumerator kSRC_CM7LockUpReset
CM7 lockup triggers the global system reset.
-
enumerator kSRC_CM7RequestReset
CM7 request triggers the global system reset.
-
enumerator kSRC_DcdcOverVoltageReset
DCDC over voltage triggers the global system reset.
-
enumerator kSRC_EcatResetOutputReset
EtherCAT reset output triggers the global system reset.
-
enumerator kSRC_Wdog1Reset
-
enum _src_reset_status_flags
The enumeration of reset status flags.
Values:
-
enumerator kSRC_PORResetFlag
Reset is the result of POR.
-
enumerator kSRC_Wdog1ResetFlag
Reset is the result of watchdog1 time-out event.
-
enumerator kSRC_Wdog2ResetFlag
Reset is the result of watchdog2 time-out event.
-
enumerator kSRC_Wdog3ResetFlag
Reset is the result of watchdog3 time-out event.
-
enumerator kSRC_Wdog4ResetFlag
Reset is the result of watchdog4 time-out event.
-
enumerator kSRC_Wdog5ResetFlag
Reset is the result of watchdog5 time-out event.
-
enumerator kSRC_TempsenseResetFlag
Reset is the result of software reset from temperature sensor.
-
enumerator kSRC_SentinelResetFlag
Reset is the result of the Sentinel’s reset event.
-
enumerator kSRC_JtagSoftwareResetFlag
Reset is the result of software reset from JTAG.
-
enumerator kSRC_CM33RequestResetFlag
Reset is the result of CM33 reset request.
-
enumerator kSRC_CM33LockUpResetFlag
Reset is the result of CM33 CPU lockup.
-
enumerator kSRC_CM7RequestResetFlag
Reset is the result of CM7 reset request.
-
enumerator kSRC_CM7LockUpResetFlag
Reset is the result of CM7 CPU lockup.
-
enumerator kSRC_DcdcOverVoltageResetFlag
Reset is the result of DCDC over voltage.
-
enumerator kSRC_EcatResetOutputResetFlag
Reset is the result of ECAT reset output.
-
enumerator kSRC_IppResetFlag
Reset is the result of chip PAD POR_B.
-
enumerator kSRC_PORResetFlag
-
enum _src_reset_mode
The enumeration of global system reset mode.
Values:
-
enumerator kSRC_ResetSystem
Generate the global system reset.
-
enumerator kSRC_DoNotResetSystem
Do not generate the global system reset.
-
enumerator kSRC_ResetSystem
-
enum _src_general_purpose_register_index
The index of each general purpose register.
Values:
-
enumerator kSRC_GeneralPurposeRegister0
The index of General Purpose Register0.
-
enumerator kSRC_GeneralPurposeRegister1
The index of General Purpose Register1.
-
enumerator kSRC_GeneralPurposeRegister2
The index of General Purpose Register2.
-
enumerator kSRC_GeneralPurposeRegister3
The index of General Purpose Register3.
-
enumerator kSRC_GeneralPurposeRegister4
The index of General Purpose Register4.
-
enumerator kSRC_GeneralPurposeRegister5
The index of General Purpose Register5.
-
enumerator kSRC_GeneralPurposeRegister6
The index of General Purpose Register6.
-
enumerator kSRC_GeneralPurposeRegister7
The index of General Purpose Register7.
-
enumerator kSRC_GeneralPurposeRegister8
The index of General Purpose Register8.
-
enumerator kSRC_GeneralPurposeRegister9
The index of General Purpose Register9.
-
enumerator kSRC_GeneralPurposeRegister10
The index of General Purpose Register10.
-
enumerator kSRC_GeneralPurposeRegister11
The index of General Purpose Register11.
-
enumerator kSRC_GeneralPurposeRegister12
The index of General Purpose Register12.
-
enumerator kSRC_GeneralPurposeRegister13
The index of General Purpose Register13.
-
enumerator kSRC_GeneralPurposeRegister14
The index of General Purpose Register14.
-
enumerator kSRC_GeneralPurposeRegister15
The index of General Purpose Register15.
-
enumerator kSRC_GeneralPurposeRegister16
The index of General Purpose Register16.
-
enumerator kSRC_GeneralPurposeRegister17
The index of General Purpose Register17.
-
enumerator kSRC_GeneralPurposeRegister18
The index of General Purpose Register18.
-
enumerator kSRC_GeneralPurposeRegister19
The index of General Purpose Register19.
-
enumerator kSRC_GeneralPurposeRegister0
-
enum _src_power_ctrl_step
software power control step in power on/off sequence.
Values:
-
enumerator kSRC_PDN_EdgelockHandshake
Power down Edgelock handshake step.
-
enumerator kSRC_PDN_IsolationOn
Power down isolation on step.
-
enumerator kSRC_PDN_ResetAssert
Power down reset assert step.
-
enumerator kSRC_PDN_PowerSwitchOff
Power down power switch off step.
-
enumerator kSRC_PUP_PowerSwitchOn
Power up power switch on step.
-
enumerator kSRC_PUP_ResetRelease
Power up reset release step.
-
enumerator kSRC_PUP_IsolationOff
Power up isolation off step.
-
enumerator kSRC_PUP_EdgeLockHandshake
Power up Edgelock handshake step.
-
enumerator kSRC_PDN_EdgelockHandshake
-
enum _src_power_level
The power level of low power mode setting.
Values:
-
enumerator kSRC_PowerLevel1
-
enumerator kSRC_PowerLevel2
power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
-
enumerator kSRC_PowerLevel3
power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
-
enumerator kSRC_PowerLevel4
power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
-
enumerator kSRC_PowerLevel1
-
typedef enum _src_core_name src_core_name_t
System core.
-
typedef enum _src_boot_fuse_selection src_boot_fuse_selection_t
The enumeration of the boot fuse selection.
-
typedef enum _src_reset_source src_reset_source_t
The enumeration of global system reset sources.
-
typedef enum _src_reset_mode src_reset_mode_t
The enumeration of global system reset mode.
-
typedef enum _src_general_purpose_register_index src_general_purpose_register_index_t
The index of each general purpose register.
-
typedef enum _src_power_ctrl_step src_power_ctrl_step_t
software power control step in power on/off sequence.
-
typedef enum _src_power_level src_power_level_t
The power level of low power mode setting.
-
FSL_SRC_DRIVER_VERSION
SRC driver version 2.0.1.
-
void SRC_ReleaseCM7(SRC_GENERAL_Type *base)
Releases related core reset operation.
The core reset will be held until the boot core to release it.
- Parameters:
base – SRC peripheral base address.
-
static inline uint32_t SRC_GetBootConfig(SRC_GENERAL_Type *base)
Gets Boot configuration.
- Parameters:
base – SRC peripheral base address.
- Returns:
Boot configuration. Please refer to fusemap.
-
static inline uint8_t SRC_GetBootMode(SRC_GENERAL_Type *base)
Gets the latched state of the BOOT_MODE1 and BOOT_MODE0 signals.
- Parameters:
base – SRC peripheral base address.
- Returns:
Boot mode. Please refer to the Boot mode pin setting section of System Boot.
-
void SRC_SetGlobalSystemResetMode(SRC_GENERAL_Type *base, src_reset_source_t resetSource, src_reset_mode_t resetMode)
Sets the reset mode of global system reset source.
This function sets the selected mode of the input global system reset sources.
- Parameters:
base – SRC peripheral base address.
resetSource – The global system reset source. See src_reset_source_t for more details.
resetMode – The reset mode of each reset source. See src_reset_mode_t for more details.
-
static inline uint32_t SRC_GetResetStatusFlags(SRC_GENERAL_Type *base)
Gets global system reset status flags.
- Parameters:
base – SRC peripheral base address.
- Returns:
The status of global system reset status. See _src_reset_status_flags for more details.
-
static inline void SRC_ClearGlobalSystemResetStatus(SRC_GENERAL_Type *base, uint32_t mask)
Clears the status of global reset.
- Parameters:
base – SRC peripheral base address.
mask – The reset status flag to be cleared. See _src_reset_status_flags for more details.
-
static inline void SRC_SetGeneralPurposeRegister(SRC_GENERAL_Type *base, src_general_purpose_register_index_t index, uint32_t value)
Sets value to general purpose registers.
- Parameters:
base – SRC peripheral base address.
index – The index of GPRx register array. Please refer to src_general_purpose_register_index_t.
value – Setting value for GPRx register.
-
static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_GENERAL_Type *base, src_general_purpose_register_index_t index)
Gets the value from general purpose registers.
- Parameters:
base – SRC peripheral base address.
index – The index of GPRx register array. Please refer to src_general_purpose_register_index_t.
- Returns:
The setting value for GPRx register.
-
static inline void SRC_SLICE_AllowUserModeAccess(SRC_MIX_SLICE_Type *base, bool enable)
Allows/disallows user mode access.
- Parameters:
base – SRC peripheral base address.
enable – Used to control user mode access.
true Allow user mode access.
false Disallow user mode access.
-
static inline void SRC_SLICE_AllowNonSecureModeAccess(SRC_MIX_SLICE_Type *base, bool enable)
Allows/disallows non secure mode access.
- Parameters:
base – SRC peripheral base address.
enable – Used to control non secure mode access.
true Allow non secure mode access.
false Disallow non secure mode access.
-
static inline void SRC_SLICE_LockAccessSetting(SRC_MIX_SLICE_Type *base)
Locks the setting of user mode access and non secure mode access.
Note
Once locked only reset can unlock related settings.
- Parameters:
base – SRC peripheral base address.
-
static inline void SRC_SLICE_SetWhiteList(SRC_MIX_SLICE_Type *base, uint8_t domainId)
Sets the domain ID white list for the selected slice.
- Parameters:
base – SRC peripheral base address.
domainId – The core to access registers, should be the OR’ed value of src_core_name_t.
-
static inline void SRC_SLICE_LockWhiteList(SRC_MIX_SLICE_Type *base)
Locks the value of white list.
Note
Once locked only reset can unlock related settings.
- Parameters:
base – SRC peripheral base address.
-
void SRC_SLICE_SoftwareControl(SRC_MIX_SLICE_Type *base, src_power_ctrl_step_t step)
brief Set software control step for slice power on/off sequence.
param base SRC peripheral base address. param step Slice power on/off sequence step. See src_power_ctrl_step_t for more details.
-
void SRC_SLICE_PowerDown(SRC_MIX_SLICE_Type *base, bool powerOff)
brief Power on/off slice.
param base SRC peripheral base address. param powerOff Used to trigger slice power on/off sequence.
true Trigger a power off sequence.
false Trigger a power on sequence.
-
void SRC_SLICE_ControlByCpuLowPowerMode(SRC_MIX_SLICE_Type *base, uint32_t domainMap, src_power_level_t level)
SPDIF: Sony/Philips Digital Interface
-
void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config)
Initializes the SPDIF peripheral.
Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. The configuration structure can be custom filled or set with default values by SPDIF_GetDefaultConfig().
Note
This API should be called at the beginning of the application to use the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault because the clock is not enabled.
- Parameters:
base – SPDIF base pointer
config – SPDIF configuration structure.
-
void SPDIF_GetDefaultConfig(spdif_config_t *config)
Sets the SPDIF configuration structure to default values.
This API initializes the configuration structure for use in SPDIF_Init. The initialized structure can remain unchanged in SPDIF_Init, or it can be modified before calling SPDIF_Init. This is an example.
spdif_config_t config; SPDIF_GetDefaultConfig(&config);
- Parameters:
config – pointer to master configuration structure
-
void SPDIF_Deinit(SPDIF_Type *base)
De-initializes the SPDIF peripheral.
This API gates the SPDIF clock. The SPDIF module can’t operate unless SPDIF_Init is called to enable the clock.
- Parameters:
base – SPDIF base pointer
-
uint32_t SPDIF_GetInstance(SPDIF_Type *base)
Get the instance number for SPDIF.
- Parameters:
base – SPDIF base pointer.
-
static inline void SPDIF_TxFIFOReset(SPDIF_Type *base)
Resets the SPDIF Tx.
This function makes Tx FIFO in reset mode.
- Parameters:
base – SPDIF base pointer
-
static inline void SPDIF_RxFIFOReset(SPDIF_Type *base)
Resets the SPDIF Rx.
This function enables the software reset and FIFO reset of SPDIF Rx. After reset, clear the reset bit.
- Parameters:
base – SPDIF base pointer
-
void SPDIF_TxEnable(SPDIF_Type *base, bool enable)
Enables/disables the SPDIF Tx.
- Parameters:
base – SPDIF base pointer
enable – True means enable SPDIF Tx, false means disable.
-
static inline void SPDIF_RxEnable(SPDIF_Type *base, bool enable)
Enables/disables the SPDIF Rx.
- Parameters:
base – SPDIF base pointer
enable – True means enable SPDIF Rx, false means disable.
-
static inline uint32_t SPDIF_GetStatusFlag(SPDIF_Type *base)
Gets the SPDIF status flag state.
- Parameters:
base – SPDIF base pointer
- Returns:
SPDIF status flag value. Use the _spdif_interrupt_enable_t to get the status value needed.
-
static inline void SPDIF_ClearStatusFlags(SPDIF_Type *base, uint32_t mask)
Clears the SPDIF status flag state.
- Parameters:
base – SPDIF base pointer
mask – State mask. It can be a combination of the _spdif_interrupt_enable_t member. Notice these members cannot be included, as these flags cannot be cleared by writing 1 to these bits:
kSPDIF_UChannelReceiveRegisterFull
kSPDIF_QChannelReceiveRegisterFull
kSPDIF_TxFIFOEmpty
kSPDIF_RxFIFOFull
-
static inline void SPDIF_EnableInterrupts(SPDIF_Type *base, uint32_t mask)
Enables the SPDIF Tx interrupt requests.
- Parameters:
base – SPDIF base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSPDIF_WordStartInterruptEnable
kSPDIF_SyncErrorInterruptEnable
kSPDIF_FIFOWarningInterruptEnable
kSPDIF_FIFORequestInterruptEnable
kSPDIF_FIFOErrorInterruptEnable
-
static inline void SPDIF_DisableInterrupts(SPDIF_Type *base, uint32_t mask)
Disables the SPDIF Tx interrupt requests.
- Parameters:
base – SPDIF base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
kSPDIF_WordStartInterruptEnable
kSPDIF_SyncErrorInterruptEnable
kSPDIF_FIFOWarningInterruptEnable
kSPDIF_FIFORequestInterruptEnable
kSPDIF_FIFOErrorInterruptEnable
-
static inline void SPDIF_EnableDMA(SPDIF_Type *base, uint32_t mask, bool enable)
Enables/disables the SPDIF DMA requests.
- Parameters:
base – SPDIF base pointer
mask – SPDIF DMA enable mask, The parameter can be a combination of the following sources if defined
kSPDIF_RxDMAEnable
kSPDIF_TxDMAEnable
enable – True means enable DMA, false means disable DMA.
-
static inline uint32_t SPDIF_TxGetLeftDataRegisterAddress(SPDIF_Type *base)
Gets the SPDIF Tx left data register address.
This API is used to provide a transfer address for the SPDIF DMA transfer configuration.
- Parameters:
base – SPDIF base pointer.
- Returns:
data register address.
-
static inline uint32_t SPDIF_TxGetRightDataRegisterAddress(SPDIF_Type *base)
Gets the SPDIF Tx right data register address.
This API is used to provide a transfer address for the SPDIF DMA transfer configuration.
- Parameters:
base – SPDIF base pointer.
- Returns:
data register address.
-
static inline uint32_t SPDIF_RxGetLeftDataRegisterAddress(SPDIF_Type *base)
Gets the SPDIF Rx left data register address.
This API is used to provide a transfer address for the SPDIF DMA transfer configuration.
- Parameters:
base – SPDIF base pointer.
- Returns:
data register address.
-
static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base)
Gets the SPDIF Rx right data register address.
This API is used to provide a transfer address for the SPDIF DMA transfer configuration.
- Parameters:
base – SPDIF base pointer.
- Returns:
data register address.
-
void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz)
Configures the SPDIF Tx sample rate.
The audio format can be changed at run-time. This function configures the sample rate.
- Parameters:
base – SPDIF base pointer.
sampleRate_Hz – SPDIF sample rate frequency in Hz.
sourceClockFreq_Hz – SPDIF tx clock source frequency in Hz.
-
uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz)
Configures the SPDIF Rx audio format.
The audio format can be changed at run-time. This function configures the sample rate and audio data format to be transferred.
- Parameters:
base – SPDIF base pointer.
clockSourceFreq_Hz – SPDIF system clock frequency in hz.
-
void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
Sends data using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SPDIF base pointer.
buffer – Pointer to the data to be written.
size – Bytes to be written.
-
static inline void SPDIF_WriteLeftData(SPDIF_Type *base, uint32_t data)
Writes data into SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
data – Data needs to be written.
-
static inline void SPDIF_WriteRightData(SPDIF_Type *base, uint32_t data)
Writes data into SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
data – Data needs to be written.
-
static inline void SPDIF_WriteChannelStatusHigh(SPDIF_Type *base, uint32_t data)
Writes data into SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
data – Data needs to be written.
-
static inline void SPDIF_WriteChannelStatusLow(SPDIF_Type *base, uint32_t data)
Writes data into SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
data – Data needs to be written.
-
void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
Receives data using a blocking method.
Note
This function blocks by polling until data is ready to be sent.
- Parameters:
base – SPDIF base pointer.
buffer – Pointer to the data to be read.
size – Bytes to be read.
-
static inline uint32_t SPDIF_ReadLeftData(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
static inline uint32_t SPDIF_ReadRightData(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
static inline uint32_t SPDIF_ReadChannelStatusHigh(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
static inline uint32_t SPDIF_ReadChannelStatusLow(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
static inline uint32_t SPDIF_ReadQChannel(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
static inline uint32_t SPDIF_ReadUChannel(SPDIF_Type *base)
Reads data from the SPDIF FIFO.
- Parameters:
base – SPDIF base pointer.
- Returns:
Data in SPDIF FIFO.
-
void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, void *userData)
Initializes the SPDIF Tx handle.
This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – SPDIF base pointer
handle – SPDIF handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function
-
void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_callback_t callback, void *userData)
Initializes the SPDIF Rx handle.
This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call this function once to get the handle initialized.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function.
-
status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
Performs an interrupt non-blocking send transfer on SPDIF.
Note
This API returns immediately after the transfer initiates. Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer is finished.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
xfer – Pointer to the spdif_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_SPDIF_TxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.
-
status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
Performs an interrupt non-blocking receive transfer on SPDIF.
Note
This API returns immediately after the transfer initiates. Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer is finished.
- Parameters:
base – SPDIF base pointer
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
xfer – Pointer to the spdif_transfer_t structure.
- Return values:
kStatus_Success – Successfully started the data receive.
kStatus_SPDIF_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.
-
status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
Gets a set byte count.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
count – Bytes count sent.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
Gets a received byte count.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
count – Bytes count received.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
-
void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle)
Aborts the current send.
Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
-
void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle)
Aborts the current IRQ receive.
Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.
- Parameters:
base – SPDIF base pointer
handle – Pointer to the spdif_handle_t structure which stores the transfer state.
-
void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
Tx interrupt handler.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure.
-
void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
Tx interrupt handler.
- Parameters:
base – SPDIF base pointer.
handle – Pointer to the spdif_handle_t structure.
-
FSL_SPDIF_DRIVER_VERSION
Version 2.0.7
SPDIF return status.
Values:
-
enumerator kStatus_SPDIF_RxDPLLLocked
SPDIF Rx PLL locked.
-
enumerator kStatus_SPDIF_TxFIFOError
SPDIF Tx FIFO error.
-
enumerator kStatus_SPDIF_TxFIFOResync
SPDIF Tx left and right FIFO resync.
-
enumerator kStatus_SPDIF_RxCnew
SPDIF Rx status channel value updated.
-
enumerator kStatus_SPDIF_ValidatyNoGood
SPDIF validaty flag not good.
-
enumerator kStatus_SPDIF_RxIllegalSymbol
SPDIF Rx receive illegal symbol.
-
enumerator kStatus_SPDIF_RxParityBitError
SPDIF Rx parity bit error.
-
enumerator kStatus_SPDIF_UChannelOverrun
SPDIF receive U channel overrun.
-
enumerator kStatus_SPDIF_QChannelOverrun
SPDIF receive Q channel overrun.
-
enumerator kStatus_SPDIF_UQChannelSync
SPDIF U/Q channel sync found.
-
enumerator kStatus_SPDIF_UQChannelFrameError
SPDIF U/Q channel frame error.
-
enumerator kStatus_SPDIF_RxFIFOError
SPDIF Rx FIFO error.
-
enumerator kStatus_SPDIF_RxFIFOResync
SPDIF Rx left and right FIFO resync.
-
enumerator kStatus_SPDIF_LockLoss
SPDIF Rx PLL clock lock loss.
-
enumerator kStatus_SPDIF_TxIdle
SPDIF Tx is idle
-
enumerator kStatus_SPDIF_RxIdle
SPDIF Rx is idle
-
enumerator kStatus_SPDIF_QueueFull
SPDIF queue full
-
enumerator kStatus_SPDIF_RxDPLLLocked
-
enum _spdif_rxfull_select
SPDIF Rx FIFO full falg select, it decides when assert the rx full flag.
Values:
-
enumerator kSPDIF_RxFull1Sample
Rx full at least 1 sample in left and right FIFO
-
enumerator kSPDIF_RxFull4Samples
Rx full at least 4 sample in left and right FIFO
-
enumerator kSPDIF_RxFull8Samples
Rx full at least 8 sample in left and right FIFO
-
enumerator kSPDIF_RxFull16Samples
Rx full at least 16 sample in left and right FIFO
-
enumerator kSPDIF_RxFull1Sample
-
enum _spdif_txempty_select
SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag.
Values:
-
enumerator kSPDIF_TxEmpty0Sample
Tx empty at most 0 sample in left and right FIFO
-
enumerator kSPDIF_TxEmpty4Samples
Tx empty at most 4 sample in left and right FIFO
-
enumerator kSPDIF_TxEmpty8Samples
Tx empty at most 8 sample in left and right FIFO
-
enumerator kSPDIF_TxEmpty12Samples
Tx empty at most 12 sample in left and right FIFO
-
enumerator kSPDIF_TxEmpty0Sample
-
enum _spdif_uchannel_source
SPDIF U channel source.
Values:
-
enumerator kSPDIF_NoUChannel
No embedded U channel
-
enumerator kSPDIF_UChannelFromRx
U channel from receiver, it is CD mode
-
enumerator kSPDIF_UChannelFromTx
U channel from on chip tx
-
enumerator kSPDIF_NoUChannel
-
enum _spdif_gain_select
SPDIF clock gain.
Values:
-
enumerator kSPDIF_GAIN_24
Gain select is 24
-
enumerator kSPDIF_GAIN_16
Gain select is 16
-
enumerator kSPDIF_GAIN_12
Gain select is 12
-
enumerator kSPDIF_GAIN_8
Gain select is 8
-
enumerator kSPDIF_GAIN_6
Gain select is 6
-
enumerator kSPDIF_GAIN_4
Gain select is 4
-
enumerator kSPDIF_GAIN_3
Gain select is 3
-
enumerator kSPDIF_GAIN_24
-
enum _spdif_tx_source
SPDIF tx data source.
Values:
-
enumerator kSPDIF_txFromReceiver
Tx data directly through SPDIF receiver
-
enumerator kSPDIF_txNormal
Normal operation, data from processor
-
enumerator kSPDIF_txFromReceiver
-
enum _spdif_validity_config
SPDIF tx data source.
Values:
-
enumerator kSPDIF_validityFlagAlwaysSet
Outgoing validity flags always set
-
enumerator kSPDIF_validityFlagAlwaysClear
Outgoing validity flags always clear
-
enumerator kSPDIF_validityFlagAlwaysSet
The SPDIF interrupt enable flag.
Values:
-
enumerator kSPDIF_RxDPLLLocked
SPDIF DPLL locked
-
enumerator kSPDIF_TxFIFOError
Tx FIFO underrun or overrun
-
enumerator kSPDIF_TxFIFOResync
Tx FIFO left and right channel resync
-
enumerator kSPDIF_RxControlChannelChange
SPDIF Rx control channel value changed
-
enumerator kSPDIF_ValidityFlagNoGood
SPDIF validity flag no good
-
enumerator kSPDIF_RxIllegalSymbol
SPDIF receiver found illegal symbol
-
enumerator kSPDIF_RxParityBitError
SPDIF receiver found parity bit error
-
enumerator kSPDIF_UChannelReceiveRegisterFull
SPDIF U channel revceive register full
-
enumerator kSPDIF_UChannelReceiveRegisterOverrun
SPDIF U channel receive register overrun
-
enumerator kSPDIF_QChannelReceiveRegisterFull
SPDIF Q channel receive reigster full
-
enumerator kSPDIF_QChannelReceiveRegisterOverrun
SPDIF Q channel receive register overrun
-
enumerator kSPDIF_UQChannelSync
SPDIF U/Q channel sync found
-
enumerator kSPDIF_UQChannelFrameError
SPDIF U/Q channel frame error
-
enumerator kSPDIF_RxFIFOError
SPDIF Rx FIFO underrun/overrun
-
enumerator kSPDIF_RxFIFOResync
SPDIF Rx left and right FIFO resync
-
enumerator kSPDIF_LockLoss
SPDIF receiver loss of lock
-
enumerator kSPDIF_TxFIFOEmpty
SPDIF Tx FIFO empty
-
enumerator kSPDIF_RxFIFOFull
SPDIF Rx FIFO full
-
enumerator kSPDIF_AllInterrupt
all interrupt
-
enumerator kSPDIF_RxDPLLLocked
The DMA request sources.
Values:
-
enumerator kSPDIF_RxDMAEnable
Rx FIFO full
-
enumerator kSPDIF_TxDMAEnable
Tx FIFO empty
-
enumerator kSPDIF_RxDMAEnable
-
typedef enum _spdif_rxfull_select spdif_rxfull_select_t
SPDIF Rx FIFO full falg select, it decides when assert the rx full flag.
-
typedef enum _spdif_txempty_select spdif_txempty_select_t
SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag.
-
typedef enum _spdif_uchannel_source spdif_uchannel_source_t
SPDIF U channel source.
-
typedef enum _spdif_gain_select spdif_gain_select_t
SPDIF clock gain.
-
typedef enum _spdif_tx_source spdif_tx_source_t
SPDIF tx data source.
-
typedef enum _spdif_validity_config spdif_validity_config_t
SPDIF tx data source.
-
typedef struct _spdif_config spdif_config_t
SPDIF user configuration structure.
-
typedef struct _spdif_transfer spdif_transfer_t
SPDIF transfer structure.
-
typedef struct _spdif_handle spdif_handle_t
-
typedef void (*spdif_transfer_callback_t)(SPDIF_Type *base, spdif_handle_t *handle, status_t status, void *userData)
SPDIF transfer callback prototype.
-
SPDIF_XFER_QUEUE_SIZE
SPDIF transfer queue size, user can refine it according to use case.
-
struct _spdif_config
- #include <fsl_spdif.h>
SPDIF user configuration structure.
Public Members
-
bool isTxAutoSync
If auto sync mechanism open
-
bool isRxAutoSync
If auto sync mechanism open
-
uint8_t DPLLClkSource
SPDIF DPLL clock source, range from 0~15, meaning is chip-specific
-
uint8_t txClkSource
SPDIF tx clock source, range from 0~7, meaning is chip-specific
-
spdif_rxfull_select_t rxFullSelect
SPDIF rx buffer full select
-
spdif_txempty_select_t txFullSelect
SPDIF tx buffer empty select
-
spdif_uchannel_source_t uChannelSrc
U channel source
-
spdif_tx_source_t txSource
SPDIF tx data source
-
spdif_validity_config_t validityConfig
Validity flag config
-
spdif_gain_select_t gain
Rx receive clock measure gain parameter.
-
bool isTxAutoSync
-
struct _spdif_transfer
- #include <fsl_spdif.h>
SPDIF transfer structure.
Public Members
-
uint8_t *data
Data start address to transfer.
-
uint8_t *qdata
Data buffer for Q channel
-
uint8_t *udata
Data buffer for C channel
-
size_t dataSize
Transfer size.
-
uint8_t *data
-
struct _spdif_handle
- #include <fsl_spdif.h>
SPDIF handle structure.
Public Members
-
uint32_t state
Transfer status
-
spdif_transfer_callback_t callback
Callback function called at transfer event
-
void *userData
Callback parameter passed to callback function
-
spdif_transfer_t spdifQueue[(4U)]
Transfer queue storing queued transfer
-
size_t transferSize[(4U)]
Data bytes need to transfer
-
volatile uint8_t queueUser
Index for user to queue transfer
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
uint8_t watermark
Watermark value
-
uint32_t state
SPDIF eDMA Driver
-
void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, void *userData, edma_handle_t *dmaLeftHandle, edma_handle_t *dmaRightHandle)
Initializes the SPDIF eDMA handle.
This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. Usually, for a specified SPDIF instance, call this API once to get the initialized handle.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF eDMA handle pointer.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
dmaLeftHandle – eDMA handle pointer for left channel, this handle shall be static allocated by users.
dmaRightHandle – eDMA handle pointer for right channel, this handle shall be static allocated by users.
-
void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_callback_t callback, void *userData, edma_handle_t *dmaLeftHandle, edma_handle_t *dmaRightHandle)
Initializes the SPDIF Rx eDMA handle.
This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. Usually, for a specified SPDIF instance, call this API once to get the initialized handle.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF eDMA handle pointer.
callback – Pointer to user callback function.
userData – User parameter passed to the callback function.
dmaLeftHandle – eDMA handle pointer for left channel, this handle shall be static allocated by users.
dmaRightHandle – eDMA handle pointer for right channel, this handle shall be static allocated by users.
-
status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)
Performs a non-blocking SPDIF transfer using DMA.
Note
This interface returns immediately after the transfer initiates. Call SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF eDMA handle pointer.
xfer – Pointer to the DMA transfer structure.
- Return values:
kStatus_Success – Start a SPDIF eDMA send successfully.
kStatus_InvalidArgument – The input argument is invalid.
kStatus_TxBusy – SPDIF is busy sending data.
-
status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)
Performs a non-blocking SPDIF receive using eDMA.
Note
This interface returns immediately after the transfer initiates. Call the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished.
- Parameters:
base – SPDIF base pointer
handle – SPDIF eDMA handle pointer.
xfer – Pointer to DMA transfer structure.
- Return values:
kStatus_Success – Start a SPDIF eDMA receive successfully.
kStatus_InvalidArgument – The input argument is invalid.
kStatus_RxBusy – SPDIF is busy receiving data.
-
void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)
Aborts a SPDIF transfer using eDMA.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF eDMA handle pointer.
-
void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)
Aborts a SPDIF receive using eDMA.
- Parameters:
base – SPDIF base pointer
handle – SPDIF eDMA handle pointer.
-
status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
Gets byte count sent by SPDIF.
- Parameters:
base – SPDIF base pointer.
handle – SPDIF eDMA handle pointer.
count – Bytes count sent by SPDIF.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.
-
status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
Gets byte count received by SPDIF.
- Parameters:
base – SPDIF base pointer
handle – SPDIF eDMA handle pointer.
count – Bytes count received by SPDIF.
- Return values:
kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress.
-
FSL_SPDIF_EDMA_DRIVER_VERSION
Version 2.0.8
-
typedef struct _spdif_edma_handle spdif_edma_handle_t
-
typedef void (*spdif_edma_callback_t)(SPDIF_Type *base, spdif_edma_handle_t *handle, status_t status, void *userData)
SPDIF eDMA transfer callback function for finish and error.
-
typedef struct _spdif_edma_transfer spdif_edma_transfer_t
SPDIF transfer structure.
-
struct _spdif_edma_transfer
- #include <fsl_spdif_edma.h>
SPDIF transfer structure.
Public Members
-
uint8_t *leftData
Data start address to transfer.
-
uint8_t *rightData
Data start address to transfer.
-
size_t dataSize
Transfer size.
-
uint8_t *leftData
-
struct _spdif_edma_handle
- #include <fsl_spdif_edma.h>
SPDIF DMA transfer handle, users should not touch the content of the handle.
Public Members
-
edma_handle_t *dmaLeftHandle
DMA handler for SPDIF left channel
-
edma_handle_t *dmaRightHandle
DMA handler for SPDIF right channel
-
uint8_t nbytes
eDMA minor byte transfer count initially configured.
-
uint8_t count
The transfer data count in a DMA request
-
uint32_t state
Internal state for SPDIF eDMA transfer
-
spdif_edma_callback_t callback
Callback for users while transfer finish or error occurs
-
void *userData
User callback parameter
-
edma_tcd_t leftTcd[(4U) + 1U]
TCD pool for eDMA transfer.
-
edma_tcd_t rightTcd[(4U) + 1U]
TCD pool for eDMA transfer.
-
spdif_edma_transfer_t spdifQueue[(4U)]
Transfer queue storing queued transfer.
-
size_t transferSize[(4U)]
Data bytes need to transfer, left and right are the same, so use one
-
volatile uint8_t queueUser
Index for user to queue transfer.
-
volatile uint8_t queueDriver
Index for driver to get the transfer data and size
-
edma_handle_t *dmaLeftHandle
Sysctr
-
enum _sysctr_clock_source
System Counter clock source selection.
Values:
-
enumerator kSYSCTR_BaseFrequency
24MHz base clock from crystal oscillator is used as the clock.
-
enumerator kSYSCTR_AlternateFrequency
32kHz alternate slow clock from crystal oscillator is used as the clock.
-
enumerator kSYSCTR_BaseFrequency
-
enum _sysctr_compare_frame
System Counter compare frame selection.
Values:
-
enumerator kSYSCTR_CompareFrame_0
Select compare frame 0.
-
enumerator kSYSCTR_CompareFrame_1
Select compare frame 1.
-
enumerator kSYSCTR_CompareFrame_0
-
enum _sysctr_frequency_modes_table
System Counter frequency modes table selection.
Values:
-
enumerator kSYSCTR_FrequencyModesTable_0
Select frequency modes table 0.
-
enumerator kSYSCTR_FrequencyModesTable_1
Select frequency modes table 1.
-
enumerator kSYSCTR_FrequencyModesTable_2
Select frequency modes table 2.
-
enumerator kSYSCTR_FrequencyModesTable_0
-
enum _sysctr_interrupt_enable
List of System Counter interrupt options.
Values:
-
enumerator kSYSCTR_Compare0InterruptEnable
Compare frame 0 interrupt.
-
enumerator kSYSCTR_Compare1InterruptEnable
Compare frame 1 interrupt.
-
enumerator kSYSCTR_Compare0InterruptEnable
-
enum _sysctr_status_flags
List of System Counter status flags.
Values:
-
enumerator kSYSCTR_Compare0Flag
Compare frame 0 compare flag.
-
enumerator kSYSCTR_Compare1Flag
Compare frame 1 compare flag.
-
enumerator kSYSCTR_Compare0Flag
-
enum _sysctr_flags
System Counter status flags.
This provides constants for the System Counter status flags for use in the System Counter functions. The system counter status flags provide information concerning the clock frequency and debug state.
Values:
-
enumerator kSYSCTR_DebugHalt
-
enumerator kSYSCTR_FrequencyChangeAck_0
-
enumerator kSYSCTR_FrequencyChangeAck_1
-
enumerator kSYSCTR_DebugHalt
-
typedef enum _sysctr_clock_source sysctr_clock_source_t
System Counter clock source selection.
-
typedef enum _sysctr_compare_frame sysctr_compare_frame_t
System Counter compare frame selection.
-
typedef enum _sysctr_frequency_modes_table sysctr_frequency_modes_table_t
System Counter frequency modes table selection.
-
typedef enum _sysctr_interrupt_enable sysctr_interrupt_enable_t
List of System Counter interrupt options.
-
typedef enum _sysctr_status_flags sysctr_status_flags_t
List of System Counter status flags.
-
typedef struct _sysctr_config sysctr_config_t
System Counter config structure.
This structure holds the configuration settings for the System Counter peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
-
FSL_SYSCTR_DRIVER_VERSION
System Counter driver version.
-
void SYSCTR_Init(SYS_CTR_CONTROL_Type *ctrlBase, SYS_CTR_COMPARE_Type *cmpBase, const sysctr_config_t *pConfig)
Initializes a System Counter instance.
This function initializes the System Counter module with user-defined settings. This example shows how to set up the sysctr_config_t parameters and how to call the SYSCTR_Init function by passing in these parameters. Default clock source is 24MHz base clock from crystal oscillator.
sysctr_config_t sysctrConfig; sysctrConfig.enableDebugHalt = false; sysctrConfig.enableHardwareFrequencyChange = false; SYSCTR_Init(SYS_CTR_CONTROL, SYS_CTR_COMPARE, &sysctr_config_t);
- Parameters:
ctrlBase – System Counter peripheral control model base address.
cmpBase – System Counter peripheral compare model base address.
pConfig – Configuration pointer to user’s System Counter config structure.
-
void SYSCTR_Deinit(SYS_CTR_CONTROL_Type *ctrlBase, SYS_CTR_COMPARE_Type *cmpBase)
De-initializes a System Counter instance.
This function disables the System Counter module clock and sets all register values to the reset value.
- Parameters:
ctrlBase – System Counter peripheral control model base address.
cmpBase – System Counter peripheral compare model base address.
-
void SYSCTR_GetDefaultConfig(sysctr_config_t *pConfig)
Fill in the System Counter config struct with the default settings.
The default values are:
config->enableDebugHalt = false; config->enableHardwareFrequencyChange = false;
- Parameters:
pConfig – Configuration pointer to user’s System Counter config structure.
-
static inline void SYSCTR_EnableInterrupts(SYS_CTR_COMPARE_Type *base, uint32_t mask)
Enables the selected System Counter interrupts.
- Parameters:
base – System Counter peripheral compare model base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration sysctr_interrupt_enable_t.
-
static inline void SYSCTR_DisableInterrupts(SYS_CTR_COMPARE_Type *base, uint32_t mask)
Disable the selected System Counter interrupts.
- Parameters:
base – System Counter peripheral compare model base address.
mask – The interrupts to disable. This is a logical OR of members of the enumeration sysctr_interrupt_enable_t.
-
static inline uint32_t SYSCTR_GetStatusFlags(SYS_CTR_COMPARE_Type *base)
Get System Counter status flags.
- Parameters:
base – System Counter peripheral compare model base address.
- Returns:
The status flags. This is the logical OR of members of the enumeration sysctr_status_flags_t.
-
static inline void SYSCTR_StartCounter(SYS_CTR_CONTROL_Type *base)
Enables the System Counter counting.
- Parameters:
base – System Counter peripheral control model base address.
-
static inline void SYSCTR_StopCounter(SYS_CTR_CONTROL_Type *base)
Disables the System Counter counting.
- Parameters:
base – System Counter peripheral control model base address.
-
bool enableDebugHalt
true: Debug input causes the System Counter to halt; false: Debug input is ignored
-
bool enableHardwareFrequencyChange
true: Hardware changes frequency automatically when entering or exiting low power mode; false: Frequency changes are fully under software control
-
static inline void SYSCTR_SetCounterlValue(SYS_CTR_CONTROL_Type *base, uint64_t value)
Set System Counter count value.
User can set System Counter initial count value before starting counter. Be cautious that user must set count value while operating on the base frequency only. Set count value while running on the alternate frequency may have unpredictable results.
- Parameters:
base – System Counter peripheral control model base address.
value – System Counter count value.
-
static inline uint64_t SYSCTR_GetCounterlValue(SYS_CTR_READ_Type *base)
Get System Counter current count value.
- Parameters:
base – System Counter peripheral read model base address.
- Returns:
System Counter current count value.
-
void SYSCTR_SetCounterClockSource(SYS_CTR_CONTROL_Type *base, sysctr_clock_source_t clockSource)
Set System Counter clock source.
- Parameters:
base – System Counter peripheral control model base address.
sysctr_clock_source_t – System Counter clock source.
-
void SYSCTR_EnableCompare(SYS_CTR_COMPARE_Type *base, sysctr_compare_frame_t cmpFrame, bool enable)
Enable or disable compare function of specific compare frame.
- Parameters:
base – System Counter peripheral control model base address.
cmpFrame – System Counter compare frame selection.
enable – true: Enable compare function; false: Disable compare function
-
void SYSCTR_SetCompareValue(SYS_CTR_CONTROL_Type *ctrlBase, SYS_CTR_COMPARE_Type *cmpBase, sysctr_compare_frame_t cmpFrame, uint64_t value)
Set System Counter compare value of specific compare frame.
Be cautious that user must set compare value while operating on the base frequency only. Set compare value while running on the alternate frequency may have unpredictable results.
- Parameters:
ctrlBase – System Counter peripheral control model base address.
cmpBase – System Counter peripheral compare model base address.
cmpFrame – System Counter compare frame selection.
value – System Counter compare value.
-
uint32_t SYSCTR_GetFrequencyModesTableValue(SYS_CTR_CONTROL_Type *base, sysctr_frequency_modes_table_t index)
Get specific Frequency Modes Table value.
- Parameters:
base – System Counter peripheral control model base address.
index – Frequency Modes Table index.
- Returns:
Frequency modes table value.
-
struct _sysctr_config
- #include <fsl_sysctr.h>
System Counter config structure.
This structure holds the configuration settings for the System Counter peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
SYSCTR: System Counter Driver
SYSPM: System Performance Monitor
-
FSL_SYSPM_DRIVER_VERSION
SYSPM driver version.
-
enum _syspm_monitor
syspm select control monitor
Values:
-
enumerator kSYSPM_Monitor0
Monitor 0
-
enumerator kSYSPM_Monitor0
-
enum _syspm_event
syspm select event
Values:
-
enumerator kSYSPM_Event1
Event 1
-
enumerator kSYSPM_Event2
Event 2
-
enumerator kSYSPM_Event3
Event 3
-
enumerator kSYSPM_Event1
-
enum _syspm_mode
syspm set count mode
Values:
-
enumerator kSYSPM_BothMode
count in both modes
-
enumerator kSYSPM_UserMode
count only in user mode
-
enumerator kSYSPM_PrivilegedMode
count only in privileged mode
-
enumerator kSYSPM_BothMode
-
enum _syspm_startstop_control
syspm start/stop control
Values:
-
enumerator kSYSPM_Idle
idle >
-
enumerator kSYSPM_LocalStop
local stop
-
enumerator kSYSPM_LocalStart
local start
-
enumerator KSYSPM_EnableTraceControl
enable global TSTART/TSTOP
-
enumerator kSYSPM_GlobalStart
global stop
-
enumerator kSYSPM_GlobalStop
global start
-
enumerator kSYSPM_Idle
-
typedef enum _syspm_monitor syspm_monitor_t
syspm select control monitor
-
typedef enum _syspm_event syspm_event_t
syspm select event
-
typedef enum _syspm_mode syspm_mode_t
syspm set count mode
-
typedef enum _syspm_startstop_control syspm_startstop_control_t
syspm start/stop control
-
void SYSPM_Init(SYSPM_Type *base)
Initializes the SYSPM.
This function enables the SYSPM clock.
- Parameters:
base – SYSPM peripheral base address.
-
void SYSPM_Deinit(SYSPM_Type *base)
Deinitializes the SYSPM.
This function disables the SYSPM clock.
- Parameters:
base – SYSPM peripheral base address.
-
void SYSPM_SelectEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event, uint8_t eventCode)
Select event counters.
- Parameters:
base – SYSPM peripheral base address.
event – syspm select event, see to syspm_event_t.
eventCode – select which event to be counted in PMECTRx., see to table Events.
-
void SYSPM_ResetEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event)
Reset event counters.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
-
void SYSPM_ResetInstructionEvent(SYSPM_Type *base, syspm_monitor_t monitor)
Reset Instruction Counter.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
-
void SYSPM_SetCountMode(SYSPM_Type *base, syspm_monitor_t monitor, syspm_mode_t mode)
Set count mode.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
mode – syspm select counter mode, see to syspm_mode_t.
-
void SYSPM_SetStartStopControl(SYSPM_Type *base, syspm_monitor_t monitor, syspm_startstop_control_t ssc)
Set Start/Stop Control.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
ssc – This 3-bit field provides a three-phase mechanism to start/stop the counters. It includes a prioritized scheme with local start > local stop > global start > global stop > conditional TSTART > TSTOP. The global and conditional start/stop affect all configured PM/PSAM module concurrently so counters are “coherent”. see to syspm_startstop_control_t
-
void SYSPM_DisableCounter(SYSPM_Type *base, syspm_monitor_t monitor)
Disable Counters if Stopped or Halted.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
-
uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event)
This is the the 40-bits of eventx counter. The value in this register increments each time the event selected in PMCRx[SELEVTx] occurs.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
event – syspm select event, see to syspm_event_t.
- Returns:
get the the 40 bits of eventx counter.
-
uint64_t SYSPM_GetInstructionCounter(SYSPM_Type *base, syspm_monitor_t monitor)
This is the the 40-bits of instructionx counter. The value in this register increments each time the CPU count signals occurs.
- Parameters:
base – SYSPM peripheral base address.
monitor – syspm control monitor, see to syspm_monitor_t.
- Returns:
get the the 40 bits of instruction counter.
TEMPSENSOR: Temperature Sensor Module
-
FSL_TMPSNS_DRIVER_VERSION
TMPSNS interrupt status enable type, tmpsns_interrupt_status_enable_t.
Values:
-
enumerator kTEMPSENSOR_HighTempInterruptStatusEnable
High temperature interrupt status enable.
-
enumerator kTEMPSENSOR_LowTempInterruptStatusEnable
Low temperature interrupt status enable.
-
enumerator kTEMPSENSOR_PanicTempInterruptStatusEnable
Panic temperature interrupt status enable.
-
enumerator kTEMPSENSOR_FinishInterruptStatusEnable
Finish interrupt enable.
-
enumerator kTEMPSENSOR_HighTempInterruptStatusEnable
TMPSNS interrupt status type, tmpsns_interrupt_status_t.
Values:
-
enumerator kTEMPSENSOR_HighTempInterruptStatus
High temperature interrupt status.
-
enumerator kTEMPSENSOR_LowTempInterruptStatus
Low temperature interrupt status.
-
enumerator kTEMPSENSOR_PanicTempInterruptStatus
Panic temperature interrupt status.
-
enumerator kTEMPSENSOR_HighTempInterruptStatus
-
enum tmpsns_measure_mode_t
TMPSNS measure mode, tempsensor_measure_mode.
Values:
-
enumerator kTEMPSENSOR_SingleMode
Single measurement mode.
-
enumerator kTEMPSENSOR_ContinuousMode
Continuous measurement mode.
-
enumerator kTEMPSENSOR_SingleMode
-
enum _tmpsns_alarm_mode
TMPSNS alarm mode.
Values:
-
enumerator kTEMPMON_HighAlarmMode
The high alarm temperature interrupt mode.
-
enumerator kTEMPMON_PanicAlarmMode
The panic alarm temperature interrupt mode.
-
enumerator kTEMPMON_LowAlarmMode
The low alarm temperature interrupt mode.
-
enumerator kTEMPMON_HighAlarmMode
-
typedef struct _tmpsns_config tmpsns_config_t
TMPSNS temperature structure.
-
typedef enum _tmpsns_alarm_mode tmpsns_alarm_mode_t
TMPSNS alarm mode.
-
void TMPSNS_Init(TMPSNS_Type *base, const tmpsns_config_t *config)
Initializes the TMPSNS module.
- Parameters:
base – TMPSNS base pointer
config – Pointer to configuration structure.
-
void TMPSNS_Deinit(TMPSNS_Type *base)
Deinitializes the TMPSNS module.
- Parameters:
base – TMPSNS base pointer
-
void TMPSNS_GetDefaultConfig(tmpsns_config_t *config)
Gets the default configuration structure.
This function initializes the TMPSNS configuration structure to a default value. The default values are: tempmonConfig->frequency = 0x02U; tempmonConfig->highAlarmTemp = 44U; tempmonConfig->panicAlarmTemp = 90U; tempmonConfig->lowAlarmTemp = 39U;
- Parameters:
config – Pointer to a configuration structure.
-
void TMPSNS_StartMeasure(TMPSNS_Type *base)
start the temperature measurement process.
- Parameters:
base – TMPSNS base pointer.
-
void TMPSNS_StopMeasure(TMPSNS_Type *base)
stop the measurement process.
- Parameters:
base – TMPSNS base pointer
-
float TMPSNS_GetCurrentTemperature(TMPSNS_Type *base)
Get current temperature with the fused temperature calibration data.
- Parameters:
base – TMPSNS base pointer
- Returns:
current temperature with degrees Celsius.
-
void TMPSNS_SetTempAlarm(TMPSNS_Type *base, int32_t tempVal, tmpsns_alarm_mode_t alarmMode)
Set the temperature count (raw sensor output) that will generate an alarm interrupt.
- Parameters:
base – TMPSNS base pointer
tempVal – The alarm temperature with degrees Celsius
alarmMode – The alarm mode.
-
void TMPSNS_EnableInterrupt(TMPSNS_Type *base, uint32_t mask)
Enable interrupt status.
- Parameters:
base – TMPSNS base pointer
mask – The interrupts to enable from tmpsns_interrupt_status_enable_t.
-
void TMPSNS_DisableInterrupt(TMPSNS_Type *base, uint32_t mask)
Disable interrupt status.
- Parameters:
base – TMPSNS base pointer
mask – The interrupts to disable from tmpsns_interrupt_status_enable_t.
-
static inline uint32_t TMPSNS_GetInterruptFlags(TMPSNS_Type *base)
Get interrupt status flag.
- Parameters:
base – TMPSNS base pointer
-
static inline void TMPSNS_ClearInterruptFlags(TMPSNS_Type *base, uint32_t mask)
Clear interrupt status flag.
- Parameters:
base – TMPSNS base pointer
mask – The interrupts to disable from tmpsns_interrupt_status_t.
-
struct _tmpsns_config
- #include <fsl_tempsensor.h>
TMPSNS temperature structure.
Public Members
-
tmpsns_measure_mode_t measureMode
The temperature measure mode.
-
uint16_t frequency
The temperature measure frequency.
-
int32_t highAlarmTemp
The high alarm temperature.
-
int32_t panicAlarmTemp
The panic alarm temperature.
-
int32_t lowAlarmTemp
The low alarm temperature.
-
tmpsns_measure_mode_t measureMode
TPM: Timer PWM Module
-
uint32_t TPM_GetInstance(TPM_Type *base)
Gets the instance from the base address.
- Parameters:
base – TPM peripheral base address
- Returns:
The TPM instance
-
void TPM_Init(TPM_Type *base, const tpm_config_t *config)
Ungates the TPM clock and configures the peripheral for basic operation.
Note
This API should be called at the beginning of the application using the TPM driver.
- Parameters:
base – TPM peripheral base address
config – Pointer to user’s TPM config structure.
-
void TPM_Deinit(TPM_Type *base)
Stops the counter and gates the TPM clock.
- Parameters:
base – TPM peripheral base address
-
void TPM_GetDefaultConfig(tpm_config_t *config)
Fill in the TPM config struct with the default settings.
The default values are:
config->prescale = kTPM_Prescale_Divide_1; config->useGlobalTimeBase = false; config->syncGlobalTimeBase = false; config->dozeEnable = false; config->dbgMode = false; config->enableReloadOnTrigger = false; config->enableStopOnOverflow = false; config->enableStartOnTrigger = false; #if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER config->enablePauseOnTrigger = false; #endif config->triggerSelect = kTPM_Trigger_Select_0; #if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION config->triggerSource = kTPM_TriggerSource_External; config->extTriggerPolarity = kTPM_ExtTrigger_Active_High; #endif #if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL config->chnlPolarity = 0U; #endif
- Parameters:
config – Pointer to user’s TPM config structure.
-
tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)
Calculates the counter clock prescaler.
This function calculates the values for SC[PS].
return Calculated clock prescaler value.
- Parameters:
base – TPM peripheral base address
counterPeriod_Hz – The desired frequency in Hz which corresponding to the time when the counter reaches the mod value
srcClock_Hz – TPM counter clock in Hz
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status_t TPM_SetupPwm(TPM_Type *base, const tpm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, tpm_pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)
Configures the PWM signal parameters.
User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this function to configure all the TPM channels that will be used to output a PWM signal
- Parameters:
base – TPM peripheral base address
chnlParams – Array of PWM channel parameters to configure the channel(s)
numOfChnls – Number of channels to configure, this should be the size of the array passed in
mode – PWM operation mode, options available in enumeration tpm_pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – TPM counter clock in Hz
- Returns:
kStatus_Success if the PWM setup was successful, kStatus_Error on failure
-
status_t TPM_UpdatePwmDutycycle(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_pwm_mode_t currentPwmMode, uint8_t dutyCyclePercent)
Update the duty cycle of an active PWM signal.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number. In combined mode, this represents the channel pair number
currentPwmMode – The current PWM mode set during PWM setup
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)
- Returns:
kStatus_Success if the PWM setup was successful, kStatus_Error on failure
-
void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level)
Update the edge level selection for a channel.
Note
When the TPM has PWM pause level select feature (FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT = 1), the PWM output cannot be turned off by selecting the output level. In this case, must use TPM_DisableChannel API to close the PWM output.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
level – The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. See the appropriate SoC reference manual for details about this field.
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static inline uint8_t TPM_GetChannelContorlBits(TPM_Type *base, tpm_chnl_t chnlNumber)
Get the channel control bits value (mode, edge and level bit fileds).
This function disable the channel by clear all mode and level control bits.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
- Returns:
The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t.
-
static inline void TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber)
Dsiable the channel.
This function disable the channel by clear all mode and level control bits.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
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static inline void TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control)
Enable the channel according to mode and level configs.
This function enable the channel output according to input mode/level config parameters.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
control – The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t.
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void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode)
Enables capturing an input signal on the channel using the function parameters.
When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into the CnV register. The user has to read the CnV register separately to get this value.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
captureMode – Specifies which edge to capture
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void TPM_SetupOutputCompare(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_output_compare_mode_t compareMode, uint32_t compareValue)
Configures the TPM to generate timed pulses.
When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel output is changed based on what is specified in the compareMode argument.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
compareMode – Action to take on the channel output when the compare condition is met
compareValue – Value to be programmed in the CnV register.
-
void TPM_SetupDualEdgeCapture(TPM_Type *base, tpm_chnl_t chnlPairNumber, const tpm_dual_edge_capture_param_t *edgeParam, uint32_t filterValue)
Configures the dual edge capture mode of the TPM.
This function allows to measure a pulse width of the signal on the input of channel of a channel pair. The filter function is disabled if the filterVal argument passed is zero.
- Parameters:
base – TPM peripheral base address
chnlPairNumber – The TPM channel pair number; options are 0, 1, 2, 3
edgeParam – Sets up the dual edge capture function
filterValue – Filter value, specify 0 to disable filter.
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void TPM_SetupQuadDecode(TPM_Type *base, const tpm_phase_params_t *phaseAParams, const tpm_phase_params_t *phaseBParams, tpm_quad_decode_mode_t quadMode)
Configures the parameters and activates the quadrature decode mode.
- Parameters:
base – TPM peripheral base address
phaseAParams – Phase A configuration parameters
phaseBParams – Phase B configuration parameters
quadMode – Selects encoding mode used in quadrature decoder mode
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static inline void TPM_SetChannelPolarity(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)
Set the input and output polarity of each of the channels.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
enable – true: Set the channel polarity to active high; false: Set the channel polarity to active low;
-
static inline void TPM_EnableChannelExtTrigger(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)
Enable external trigger input to be used by channel.
In input capture mode, configures the trigger input that is used by the channel to capture the counter value. In output compare or PWM mode, configures the trigger input used to modulate the channel output. When modulating the output, the output is forced to the channel initial value whenever the trigger is not asserted.
Note
No matter how many external trigger sources there are, only input trigger 0 and 1 are used. The even numbered channels share the input trigger 0 and the odd numbered channels share the second input trigger 1.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
enable – true: Configures trigger input 0 or 1 to be used by channel; false: Trigger input has no effect on the channel
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void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask)
Enables the selected TPM interrupts.
- Parameters:
base – TPM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t
-
void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask)
Disables the selected TPM interrupts.
- Parameters:
base – TPM peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t
-
uint32_t TPM_GetEnabledInterrupts(TPM_Type *base)
Gets the enabled TPM interrupts.
- Parameters:
base – TPM peripheral base address
- Returns:
The enabled interrupts. This is the logical OR of members of the enumeration tpm_interrupt_enable_t
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void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback)
Register callback.
If channel or overflow interrupt is enabled by the user, then a callback can be registered which will be invoked when the interrupt is triggered.
- Parameters:
base – TPM peripheral base address
callback – Callback function
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static inline uint32_t TPM_GetChannelValue(TPM_Type *base, tpm_chnl_t chnlNumber)
Gets the TPM channel value.
Note
The TPM channel value contain the captured TPM counter value for the input modes or the match value for the output modes.
- Parameters:
base – TPM peripheral base address
chnlNumber – The channel number
- Returns:
The channle CnV regisyer value.
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static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
Gets the TPM status flags.
- Parameters:
base – TPM peripheral base address
- Returns:
The status flags. This is the logical OR of members of the enumeration tpm_status_flags_t
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static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
Clears the TPM status flags.
- Parameters:
base – TPM peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration tpm_status_flags_t
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static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)
Sets the timer period in units of ticks.
Timers counts from 0 until it equals the count value set here. The count value is written to the MOD register.
Note
This API allows the user to use the TPM module as a timer. Do not mix usage of this API with TPM’s PWM setup API’s.
Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
- Parameters:
base – TPM peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.
-
static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)
Reads the current timer counting value.
This function returns the real-time timer counting value in a range from 0 to a timer period.
Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
- Parameters:
base – TPM peripheral base address
- Returns:
The current counter value in ticks
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static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
Starts the TPM counter.
- Parameters:
base – TPM peripheral base address
clockSource – TPM clock source; once clock source is set the counter will start running
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static inline void TPM_StopTimer(TPM_Type *base)
Stops the TPM counter.
- Parameters:
base – TPM peripheral base address
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FSL_TPM_DRIVER_VERSION
TPM driver version 2.3.2.
-
enum _tpm_chnl
List of TPM channels.
Note
Actual number of available channels is SoC dependent
Values:
-
enumerator kTPM_Chnl_0
TPM channel number 0
-
enumerator kTPM_Chnl_1
TPM channel number 1
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enumerator kTPM_Chnl_2
TPM channel number 2
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enumerator kTPM_Chnl_3
TPM channel number 3
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enumerator kTPM_Chnl_4
TPM channel number 4
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enumerator kTPM_Chnl_5
TPM channel number 5
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enumerator kTPM_Chnl_6
TPM channel number 6
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enumerator kTPM_Chnl_7
TPM channel number 7
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enumerator kTPM_Chnl_0
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enum _tpm_pwm_mode
TPM PWM operation modes.
Values:
-
enumerator kTPM_EdgeAlignedPwm
Edge aligned PWM
-
enumerator kTPM_CenterAlignedPwm
Center aligned PWM
-
enumerator kTPM_CombinedPwm
Combined PWM (Edge-aligned, center-aligned, or asymmetrical PWMs can be obtained in combined mode using different software configurations)
-
enumerator kTPM_EdgeAlignedPwm
-
enum _tpm_pwm_level_select
TPM PWM output pulse mode: high-true, low-true or no output.
Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output.
Values:
-
enumerator kTPM_HighTrue
High true pulses
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enumerator kTPM_LowTrue
Low true pulses
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enumerator kTPM_HighTrue
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enum _tpm_pwm_pause_level_select
TPM PWM output when first enabled or paused: set or clear.
Values:
-
enumerator kTPM_ClearOnPause
Clear Output when counter first enabled or paused.
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enumerator kTPM_SetOnPause
Set Output when counter first enabled or paused.
-
enumerator kTPM_ClearOnPause
-
enum _tpm_chnl_control_bit_mask
List of TPM channel modes and level control bit mask.
Values:
-
enumerator kTPM_ChnlELSnAMask
Channel ELSA bit mask.
-
enumerator kTPM_ChnlELSnBMask
Channel ELSB bit mask.
-
enumerator kTPM_ChnlMSAMask
Channel MSA bit mask.
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enumerator kTPM_ChnlMSBMask
Channel MSB bit mask.
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enumerator kTPM_ChnlELSnAMask
-
enum _tpm_trigger_select
Trigger sources available.
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)
Note
The actual trigger sources available is SoC-specific.
Values:
-
enumerator kTPM_Trigger_Select_0
-
enumerator kTPM_Trigger_Select_1
-
enumerator kTPM_Trigger_Select_2
-
enumerator kTPM_Trigger_Select_3
-
enumerator kTPM_Trigger_Select_4
-
enumerator kTPM_Trigger_Select_5
-
enumerator kTPM_Trigger_Select_6
-
enumerator kTPM_Trigger_Select_7
-
enumerator kTPM_Trigger_Select_8
-
enumerator kTPM_Trigger_Select_9
-
enumerator kTPM_Trigger_Select_10
-
enumerator kTPM_Trigger_Select_11
-
enumerator kTPM_Trigger_Select_12
-
enumerator kTPM_Trigger_Select_13
-
enumerator kTPM_Trigger_Select_14
-
enumerator kTPM_Trigger_Select_15
-
enumerator kTPM_Trigger_Select_0
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enum _tpm_trigger_source
Trigger source options available.
Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger.
Values:
-
enumerator kTPM_TriggerSource_External
Use external trigger input
-
enumerator kTPM_TriggerSource_Internal
Use internal trigger (channel pin input capture)
-
enumerator kTPM_TriggerSource_External
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enum _tpm_ext_trigger_polarity
External trigger source polarity.
Note
Selects the polarity of the external trigger source.
Values:
-
enumerator kTPM_ExtTrigger_Active_High
External trigger input is active high
-
enumerator kTPM_ExtTrigger_Active_Low
External trigger input is active low
-
enumerator kTPM_ExtTrigger_Active_High
-
enum _tpm_output_compare_mode
TPM output compare modes.
Values:
-
enumerator kTPM_NoOutputSignal
No channel output when counter reaches CnV
-
enumerator kTPM_ToggleOnMatch
Toggle output
-
enumerator kTPM_ClearOnMatch
Clear output
-
enumerator kTPM_SetOnMatch
Set output
-
enumerator kTPM_HighPulseOutput
Pulse output high
-
enumerator kTPM_LowPulseOutput
Pulse output low
-
enumerator kTPM_NoOutputSignal
-
enum _tpm_input_capture_edge
TPM input capture edge.
Values:
-
enumerator kTPM_RisingEdge
Capture on rising edge only
-
enumerator kTPM_FallingEdge
Capture on falling edge only
-
enumerator kTPM_RiseAndFallEdge
Capture on rising or falling edge
-
enumerator kTPM_RisingEdge
-
enum _tpm_quad_decode_mode
TPM quadrature decode modes.
Note
This mode is available only on some SoC’s.
Values:
-
enumerator kTPM_QuadPhaseEncode
Phase A and Phase B encoding mode
-
enumerator kTPM_QuadCountAndDir
Count and direction encoding mode
-
enumerator kTPM_QuadPhaseEncode
-
enum _tpm_phase_polarity
TPM quadrature phase polarities.
Values:
-
enumerator kTPM_QuadPhaseNormal
Phase input signal is not inverted
-
enumerator kTPM_QuadPhaseInvert
Phase input signal is inverted
-
enumerator kTPM_QuadPhaseNormal
-
enum _tpm_clock_source
TPM clock source selection.
Values:
-
enumerator kTPM_SystemClock
System clock
-
enumerator kTPM_ExternalClock
External TPM_EXTCLK pin clock
-
enumerator kTPM_ExternalInputTriggerClock
Selected external input trigger clock
-
enumerator kTPM_SystemClock
-
enum _tpm_clock_prescale
TPM prescale value selection for the clock source.
Values:
-
enumerator kTPM_Prescale_Divide_1
Divide by 1
-
enumerator kTPM_Prescale_Divide_2
Divide by 2
-
enumerator kTPM_Prescale_Divide_4
Divide by 4
-
enumerator kTPM_Prescale_Divide_8
Divide by 8
-
enumerator kTPM_Prescale_Divide_16
Divide by 16
-
enumerator kTPM_Prescale_Divide_32
Divide by 32
-
enumerator kTPM_Prescale_Divide_64
Divide by 64
-
enumerator kTPM_Prescale_Divide_128
Divide by 128
-
enumerator kTPM_Prescale_Divide_1
-
enum _tpm_interrupt_enable
List of TPM interrupts.
Values:
-
enumerator kTPM_Chnl0InterruptEnable
Channel 0 interrupt.
-
enumerator kTPM_Chnl1InterruptEnable
Channel 1 interrupt.
-
enumerator kTPM_Chnl2InterruptEnable
Channel 2 interrupt.
-
enumerator kTPM_Chnl3InterruptEnable
Channel 3 interrupt.
-
enumerator kTPM_Chnl4InterruptEnable
Channel 4 interrupt.
-
enumerator kTPM_Chnl5InterruptEnable
Channel 5 interrupt.
-
enumerator kTPM_Chnl6InterruptEnable
Channel 6 interrupt.
-
enumerator kTPM_Chnl7InterruptEnable
Channel 7 interrupt.
-
enumerator kTPM_TimeOverflowInterruptEnable
Time overflow interrupt.
-
enumerator kTPM_Chnl0InterruptEnable
-
enum _tpm_status_flags
List of TPM flags.
Values:
-
enumerator kTPM_Chnl0Flag
Channel 0 flag
-
enumerator kTPM_Chnl1Flag
Channel 1 flag
-
enumerator kTPM_Chnl2Flag
Channel 2 flag
-
enumerator kTPM_Chnl3Flag
Channel 3 flag
-
enumerator kTPM_Chnl4Flag
Channel 4 flag
-
enumerator kTPM_Chnl5Flag
Channel 5 flag
-
enumerator kTPM_Chnl6Flag
Channel 6 flag
-
enumerator kTPM_Chnl7Flag
Channel 7 flag
-
enumerator kTPM_TimeOverflowFlag
Time overflow flag
-
enumerator kTPM_Chnl0Flag
-
typedef enum _tpm_chnl tpm_chnl_t
List of TPM channels.
Note
Actual number of available channels is SoC dependent
-
typedef enum _tpm_pwm_mode tpm_pwm_mode_t
TPM PWM operation modes.
-
typedef enum _tpm_pwm_level_select tpm_pwm_level_select_t
TPM PWM output pulse mode: high-true, low-true or no output.
Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output.
-
typedef enum _tpm_pwm_pause_level_select tpm_pwm_pause_level_select_t
TPM PWM output when first enabled or paused: set or clear.
-
typedef enum _tpm_chnl_control_bit_mask tpm_chnl_control_bit_mask_t
List of TPM channel modes and level control bit mask.
-
typedef struct _tpm_chnl_pwm_signal_param tpm_chnl_pwm_signal_param_t
Options to configure a TPM channel’s PWM signal.
-
typedef enum _tpm_trigger_select tpm_trigger_select_t
Trigger sources available.
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)
Note
The actual trigger sources available is SoC-specific.
-
typedef enum _tpm_trigger_source tpm_trigger_source_t
Trigger source options available.
Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger.
-
typedef enum _tpm_ext_trigger_polarity tpm_ext_trigger_polarity_t
External trigger source polarity.
Note
Selects the polarity of the external trigger source.
-
typedef enum _tpm_output_compare_mode tpm_output_compare_mode_t
TPM output compare modes.
-
typedef enum _tpm_input_capture_edge tpm_input_capture_edge_t
TPM input capture edge.
-
typedef struct _tpm_dual_edge_capture_param tpm_dual_edge_capture_param_t
TPM dual edge capture parameters.
Note
This mode is available only on some SoC’s.
-
typedef enum _tpm_quad_decode_mode tpm_quad_decode_mode_t
TPM quadrature decode modes.
Note
This mode is available only on some SoC’s.
-
typedef enum _tpm_phase_polarity tpm_phase_polarity_t
TPM quadrature phase polarities.
-
typedef struct _tpm_phase_param tpm_phase_params_t
TPM quadrature decode phase parameters.
-
typedef enum _tpm_clock_source tpm_clock_source_t
TPM clock source selection.
-
typedef enum _tpm_clock_prescale tpm_clock_prescale_t
TPM prescale value selection for the clock source.
-
typedef struct _tpm_config tpm_config_t
TPM config structure.
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
-
typedef enum _tpm_interrupt_enable tpm_interrupt_enable_t
List of TPM interrupts.
-
typedef enum _tpm_status_flags tpm_status_flags_t
List of TPM flags.
-
typedef void (*tpm_callback_t)(TPM_Type *base)
TPM callback function pointer.
- Param base:
TPM peripheral base address.
-
static inline void TPM_Reset(TPM_Type *base)
Performs a software reset on the TPM module.
Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.
Note
TPM software reset is available on certain SoC’s only
- Parameters:
base – TPM peripheral base address
-
TPM_MAX_COUNTER_VALUE(x)
Help macro to get the max counter value.
-
struct _tpm_chnl_pwm_signal_param
- #include <fsl_tpm.h>
Options to configure a TPM channel’s PWM signal.
Public Members
-
tpm_chnl_t chnlNumber
TPM channel to configure. In combined mode (available in some SoC’s), this represents the channel pair number
-
tpm_pwm_pause_level_select_t pauseLevel
PWM output level when counter first enabled or paused
-
tpm_pwm_level_select_t level
PWM output active level select
-
uint8_t dutyCyclePercent
PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle)
-
uint8_t firstEdgeDelayPercent
Used only in combined PWM mode to generate asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure, leave as 0. Should be specified as percentage of the PWM period, (dutyCyclePercent + firstEdgeDelayPercent) value should be not greate than 100.
-
bool enableComplementary
Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;
-
tpm_pwm_pause_level_select_t secPauseLevel
Used only in combined PWM mode. Define the second channel output level when counter first enabled or paused
-
uint8_t deadTimeValue[2]
The dead time value for channel n and n+1 in combined complementary PWM mode. Deadtime insertion is disabled when this value is zero, otherwise deadtime insertion for channel n/n+1 is configured as (deadTimeValue * 4) clock cycles. deadTimeValue’s available range is 0 ~ 15.
-
tpm_chnl_t chnlNumber
-
struct _tpm_dual_edge_capture_param
- #include <fsl_tpm.h>
TPM dual edge capture parameters.
Note
This mode is available only on some SoC’s.
Public Members
-
bool enableSwap
true: Use channel n+1 input, channel n input is ignored; false: Use channel n input, channel n+1 input is ignored
-
tpm_input_capture_edge_t currChanEdgeMode
Input capture edge select for channel n
-
tpm_input_capture_edge_t nextChanEdgeMode
Input capture edge select for channel n+1
-
bool enableSwap
-
struct _tpm_phase_param
- #include <fsl_tpm.h>
TPM quadrature decode phase parameters.
Public Members
-
uint32_t phaseFilterVal
Filter value, filter is disabled when the value is zero
-
tpm_phase_polarity_t phasePolarity
Phase polarity
-
uint32_t phaseFilterVal
-
struct _tpm_config
- #include <fsl_tpm.h>
TPM config structure.
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash
Public Members
-
tpm_clock_prescale_t prescale
Select TPM clock prescale value
-
bool useGlobalTimeBase
true: The TPM channels use an external global time base (the local counter still use for generate overflow interrupt and DMA request); false: All TPM channels use the local counter as their timebase
-
bool syncGlobalTimeBase
true: The TPM counter is synchronized to the global time base; false: disabled
-
tpm_trigger_select_t triggerSelect
Input trigger to use for controlling the counter operation
-
tpm_trigger_source_t triggerSource
Decides if we use external or internal trigger.
-
tpm_ext_trigger_polarity_t extTriggerPolarity
when using external trigger source, need selects the polarity of it.
-
bool enableDoze
true: TPM counter is paused in doze mode; false: TPM counter continues in doze mode
-
bool enableDebugMode
true: TPM counter continues in debug mode; false: TPM counter is paused in debug mode
-
bool enableReloadOnTrigger
true: TPM counter is reloaded on trigger; false: TPM counter not reloaded
-
bool enableStopOnOverflow
true: TPM counter stops after overflow; false: TPM counter continues running after overflow
-
bool enableStartOnTrigger
true: TPM counter only starts when a trigger is detected; false: TPM counter starts immediately
-
bool enablePauseOnTrigger
true: TPM counter will pause while trigger remains asserted; false: TPM counter continues running
-
uint8_t chnlPolarity
Defines the input/output polarity of the channels in POL register
-
tpm_clock_prescale_t prescale
TRDC: Trusted Resource Domain Controller
-
void TRDC_Init(TRDC_Type *base)
Initializes the TRDC module.
This function enables the TRDC clock.
- Parameters:
base – TRDC peripheral base address.
-
void TRDC_Deinit(TRDC_Type *base)
De-initializes the TRDC module.
This function disables the TRDC clock.
- Parameters:
base – TRDC peripheral base address.
-
static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)
Gets the domain ID of the current bus master.
- Parameters:
base – TRDC peripheral base address.
- Returns:
Domain ID of current bus master.
-
void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config)
Gets the TRDC hardware configuration.
This function gets the TRDC hardware configurations, including number of bus masters, number of domains, number of MRCs and number of PACs.
- Parameters:
base – TRDC peripheral base address.
config – Pointer to the structure to get the configuration.
-
static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)
Sets the TRDC DAC(Domain Assignment Controllers) global valid.
Once enabled, it will remain enabled until next reset.
- Parameters:
base – TRDC peripheral base address.
-
static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master)
Locks the bus master domain assignment register.
This function locks the master domain assignment. After it is locked, the register can’t be changed until next reset.
- Parameters:
base – TRDC peripheral base address.
master – Which master to configure.
-
static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, bool valid)
Sets the master domain assignment as valid or invalid.
This function sets the master domain assignment as valid or invalid.
- Parameters:
base – TRDC peripheral base address.
master – Which master to configure.
valid – True to set valid, false to set invalid.
-
void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment)
Gets the default master domain assignment for the processor bus master.
This function gets the default master domain assignment for the processor bus master. It should only be used for the processor bus masters, such as CORE0. This function sets the assignment as follows:
assignment->domainId = 0U; assignment->domainIdSelect = kTRDC_DidMda; assignment->lock = 0U;
- Parameters:
domainAssignment – Pointer to the assignment structure.
-
void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment)
Gets the default master domain assignment for non-processor bus master.
This function gets the default master domain assignment for non-processor bus master. It should only be used for the non-processor bus masters, such as DMA. This function sets the assignment as follows:
assignment->domainId = 0U; assignment->privilegeAttr = kTRDC_ForceUser; assignment->secureAttr = kTRDC_ForceSecure; assignment->bypassDomainId = 0U; assignment->lock = 0U;
- Parameters:
domainAssignment – Pointer to the assignment structure.
-
void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, const trdc_processor_domain_assignment_t *domainAssignment)
Sets the processor bus master domain assignment.
This function sets the processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter
assignIndex
specifies which assignment register to set.Example: Set domain assignment for core 0.
trdc_processor_domain_assignment_t processorAssignment; TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); processorAssignment.domainId = 0; processorAssignment.xxx = xxx; TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);
- Parameters:
base – TRDC peripheral base address.
domainAssignment – Pointer to the assignment structure.
-
static inline void TRDC_EnableProcessorDomainAssignment(TRDC_Type *base, bool enable)
Enables the processor bus master domain assignment.
- Parameters:
base – TRDC peripheral base address.
enable – True to enable, false to disable.
-
void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, uint8_t master, const trdc_non_processor_domain_assignment_t *domainAssignment)
Sets the non-processor bus master domain assignment.
This function sets the non-processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter
assignIndex
specifies which assignment register to set.Example: Set domain assignment for DMA0.
trdc_non_processor_domain_assignment_t nonProcessorAssignment; TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); nonProcessorAssignment.domainId = 1; nonProcessorAssignment.xxx = xxx; TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);
- Parameters:
base – TRDC peripheral base address.
master – Which master to configure, refer to trdc_master_t in processor header file.
domainAssignment – Pointer to the assignment structure.
-
void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration)
Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.
config->lockSecureVTOR = false; config->lockNonsecureVTOR = false; config->lockSecureMPU = false; config->lockNonsecureMPU = false; config->lockSAU = false;
- Parameters:
idauConfiguration – Pointer to the configuration structure.
-
void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration)
Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.
Example: Lock the secure and non-secure MPU registers.
trdc_idau_config_t idauConfiguration; TRDC_GetDefaultIDAUConfig(&idauConfiguration); idauConfiguration.lockSecureMPU = true; idauConfiguration.lockNonsecureMPU = true; TRDC_SetIDAU(TRDC, &idauConfiguration);
- Parameters:
base – TRDC peripheral base address.
idauConfiguration – Pointer to the configuration structure.
-
static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)
Enables/disables the FLW(flash logical window) function.
- Parameters:
base – TRDC peripheral base address.
enable – True to enable, false to disable.
-
static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)
Locks FLW registers. Once locked the registers can noy be updated until next reset.
- Parameters:
base – TRDC peripheral base address.
-
static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)
Gets the FLW physical base address.
- Parameters:
base – TRDC peripheral base address.
- Returns:
Physical address of the FLW function.
-
static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)
Sets the FLW size.
- Parameters:
base – TRDC peripheral base address.
size – Size of the FLW in unit of 32k bytes.
-
void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration)
Gets the default FLW(Flsh Logical Window) configuration.
config->blockCount = false; config->arrayBaseAddr = false; config->lock = false; config->enable = false;
- Parameters:
flwConfiguration – Pointer to the configuration structure.
-
void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration)
Sets the FLW function’s configuration.
trdc_flw_config_t flwConfiguration; TRDC_GetDefaultIDAUConfig(&flwConfiguration); flwConfiguration.blockCount = 32U; flwConfiguration.arrayBaseAddr = 0xXXXXXXXX; TRDC_SetIDAU(TRDC, &flwConfiguration);
- Parameters:
base – TRDC peripheral base address.
flwConfiguration – Pointer to the configuration structure.
-
status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error)
Gets and clears the first domain error of the current domain.
This function gets the first access violation information for the current domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.
- Parameters:
base – TRDC peripheral base address.
error – Pointer to the error information.
- Returns:
If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData.
-
status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId)
Gets and clears the first domain error of the specific domain.
This function gets the first access violation information for the specific domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.
- Parameters:
base – TRDC peripheral base address.
error – Pointer to the error information.
domainId – The error of which domain to get and clear.
- Returns:
If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData.
-
static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)
Sets the TRDC MRC(Memory Region Checkers) global valid.
Once enabled, it will remain enabled until next reset.
- Parameters:
base – TRDC peripheral base address.
-
static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)
Gets the TRDC MRC(Memory Region Checkers) region number valid.
- Parameters:
base – TRDC peripheral base address.
mrcIdx – MRC index.
- Returns:
the region number of the given MRC instance
-
void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mrcIdx, uint8_t regIdx)
Sets the memory access configuration for one of the access control register of one MRC.
Example: Enable the secure operations and lock the configuration for MRC0 region 1.
trdc_memory_access_control_config_t config; config.securePrivX = true; config.securePrivW = true; config.securePrivR = true; config.lock = true; TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);
- Parameters:
base – TRDC peripheral base address.
config – Pointer to the configuration structure.
mrcIdx – MRC index.
regIdx – Register number.
-
void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable)
Enables the update of the selected domians.
After the domians’ update are enabled, their regions’ NSE bits can be set or clear.
- Parameters:
base – TRDC peripheral base address.
mrcIdx – MRC index.
domianMask – Bit mask of the domains to be enabled.
enable – True to enable, false to disable.
-
void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)
Sets the NSE bits of the selected regions for domains.
This function sets the NSE bits for the selected regions for the domains whose update are enabled.
- Parameters:
base – TRDC peripheral base address.
mrcIdx – MRC index.
regionMask – Bit mask of the regions whose NSE bits to set.
-
void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)
Clears the NSE bits of the selected regions for domains.
This function clears the NSE bits for the selected regions for the domains whose update are enabled.
- Parameters:
base – TRDC peripheral base address.
mrcIdx – MRC index.
regionMask – Bit mask of the regions whose NSE bits to clear.
-
void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask)
Clears the NSE bits for all the regions of the selected domains.
This function clears the NSE bits for all regions of selected domains whose update are enabled.
- Parameters:
base – TRDC peripheral base address.
mrcIdx – MRC index.
domainMask – Bit mask of the domians whose NSE bits to clear.
-
void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config)
Sets the configuration for one of the region descriptor per domain per MRC instnce.
This function sets the configuration for one of the region descriptor, including the start and end address of the region, memory access control policy and valid.
- Parameters:
base – TRDC peripheral base address.
config – Pointer to region descriptor configuration structure.
-
static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)
Sets the TRDC MBC(Memory Block Checkers) global valid.
Once enabled, it will remain enabled until next reset.
- Parameters:
base – TRDC peripheral base address.
-
void TRDC_GetMbcHardwareConfig(TRDC_Type *base, trdc_slave_memory_hardware_config_t *config, uint8_t mbcIdx, uint8_t slvIdx)
Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).
- Parameters:
base – TRDC peripheral base address.
config – Pointer to the structure to get the configuration.
mbcIdx – MBC number.
slvIdx – Slave number.
-
void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx)
Sets the NSR update configuration for one of the MBC instance.
After set the NSE configuration, the configured memory area can be updateby NSE set/clear.
- Parameters:
base – TRDC peripheral base address.
config – Pointer to NSE update configuration structure.
mbcIdx – MBC index.
-
void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)
Sets the NSE bits of the selected configuration words according to NSE update configuration.
This function sets the NSE bits of the word for the configured regio, memory.
- Parameters:
base – TRDC peripheral base address.
mbcIdx – MBC index.
bitMask – Mask of the bits whose NSE bits to set.
-
void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)
Clears the NSE bits of the selected configuration words according to NSE update configuration.
This function sets the NSE bits of the word for the configured regio, memory.
- Parameters:
base – TRDC peripheral base address.
mbcIdx – MBC index.
bitMask – Mask of the bits whose NSE bits to clear.
-
void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slaveMask)
Clears all configuration words’ NSE bits of the selected domain and memory.
- Parameters:
base – TRDC peripheral base address.
mbcIdx – MBC index.
domainMask – Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
slaveMask – Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1’s NSE bits.
-
void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mbcIdx, uint8_t rgdIdx)
Sets the memory access configuration for one of the region descriptor of one MBC.
Example: Enable the secure operations and lock the configuration for MRC0 region 1.
trdc_memory_access_control_config_t config; config.securePrivX = true; config.securePrivW = true; config.securePrivR = true; config.lock = true; TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);
- Parameters:
base – TRDC peripheral base address.
config – Pointer to the configuration structure.
mbcIdx – MBC index.
rgdIdx – Region descriptor number.
-
void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config)
Sets the configuration for one of the memory block per domain per MBC instnce.
This function sets the configuration for one of the memory block, including the memory access control policy and nse enable.
- Parameters:
base – TRDC peripheral base address.
config – Pointer to memory block configuration structure.
-
enum _trdc_did_sel
TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.
Values:
-
enumerator kTRDC_DidMda
Use MDAn[2:0] as DID.
-
enumerator kTRDC_DidInput
Use the input DID (DID_in) as DID.
-
enumerator kTRDC_DidMdaAndInput
Use MDAn[2] concatenated with DID_in[1:0] as DID.
-
enumerator kTRDC_DidReserved
Reserved.
-
enumerator kTRDC_DidMda
-
enum _trdc_secure_attr
TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.
Values:
-
enumerator kTRDC_ForceSecure
Force the bus attribute for this master to secure.
-
enumerator kTRDC_ForceNonSecure
Force the bus attribute for this master to non-secure.
-
enumerator kTRDC_MasterSecure
Use the bus master’s secure/nonsecure attribute directly.
-
enumerator kTRDC_MasterSecure1
Use the bus master’s secure/nonsecure attribute directly.
-
enumerator kTRDC_ForceSecure
-
enum _trdc_privilege_attr
TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.
Values:
-
enumerator kTRDC_ForceUser
Force the bus attribute for this master to user.
-
enumerator kTRDC_ForcePrivilege
Force the bus attribute for this master to privileged.
-
enumerator kTRDC_MasterPrivilege
Use the bus master’s attribute directly.
-
enumerator kTRDC_MasterPrivilege1
Use the bus master’s attribute directly.
-
enumerator kTRDC_ForceUser
-
enum _trdc_controller
TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.
Values:
-
enumerator kTRDC_MemBlockController0
Memory block checker 0.
-
enumerator kTRDC_MemBlockController1
Memory block checker 1.
-
enumerator kTRDC_MemBlockController2
Memory block checker 2.
-
enumerator kTRDC_MemBlockController3
Memory block checker 3.
-
enumerator kTRDC_MemRegionChecker0
Memory region checker 0.
-
enumerator kTRDC_MemRegionChecker1
Memory region checker 1.
-
enumerator kTRDC_MemRegionChecker2
Memory region checker 2.
-
enumerator kTRDC_MemRegionChecker3
Memory region checker 3.
-
enumerator kTRDC_MemRegionChecker4
Memory region checker 4.
-
enumerator kTRDC_MemRegionChecker5
Memory region checker 5.
-
enumerator kTRDC_MemRegionChecker6
Memory region checker 6.
-
enumerator kTRDC_MemBlockController0
-
enum _trdc_error_state
TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].
Values:
-
enumerator kTRDC_ErrorStateNone
No access violation detected.
-
enumerator kTRDC_ErrorStateNone1
No access violation detected.
-
enumerator kTRDC_ErrorStateSingle
Single access violation detected.
-
enumerator kTRDC_ErrorStateMulti
Multiple access violation detected.
-
enumerator kTRDC_ErrorStateNone
-
enum _trdc_error_attr
TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].
Values:
-
enumerator kTRDC_ErrorSecureUserInst
Secure user mode, instruction fetch access.
-
enumerator kTRDC_ErrorSecureUserData
Secure user mode, data access.
-
enumerator kTRDC_ErrorSecurePrivilegeInst
Secure privileged mode, instruction fetch access.
-
enumerator kTRDC_ErrorSecurePrivilegeData
Secure privileged mode, data access.
-
enumerator kTRDC_ErrorNonSecureUserInst
NonSecure user mode, instruction fetch access.
-
enumerator kTRDC_ErrorNonSecureUserData
NonSecure user mode, data access.
-
enumerator kTRDC_ErrorNonSecurePrivilegeInst
NonSecure privileged mode, instruction fetch access.
-
enumerator kTRDC_ErrorNonSecurePrivilegeData
NonSecure privileged mode, data access.
-
enumerator kTRDC_ErrorSecureUserInst
-
enum _trdc_error_type
TRDC domain error access type definition TRDC_DERR_W1_n[ERW].
Values:
-
enumerator kTRDC_ErrorTypeRead
Error occurs on read reference.
-
enumerator kTRDC_ErrorTypeWrite
Error occurs on write reference.
-
enumerator kTRDC_ErrorTypeRead
-
enum _trdc_region_descriptor
The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.
Values:
-
enumerator kTRDC_RegionDescriptor0
Region descriptor 0.
-
enumerator kTRDC_RegionDescriptor1
Region descriptor 1.
-
enumerator kTRDC_RegionDescriptor2
Region descriptor 2.
-
enumerator kTRDC_RegionDescriptor3
Region descriptor 3.
-
enumerator kTRDC_RegionDescriptor4
Region descriptor 4.
-
enumerator kTRDC_RegionDescriptor5
Region descriptor 5.
-
enumerator kTRDC_RegionDescriptor6
Region descriptor 6.
-
enumerator kTRDC_RegionDescriptor7
Region descriptor 7.
-
enumerator kTRDC_RegionDescriptor8
Region descriptor 8.
-
enumerator kTRDC_RegionDescriptor9
Region descriptor 9.
-
enumerator kTRDC_RegionDescriptor10
Region descriptor 10.
-
enumerator kTRDC_RegionDescriptor11
Region descriptor 11.
-
enumerator kTRDC_RegionDescriptor12
Region descriptor 12.
-
enumerator kTRDC_RegionDescriptor13
Region descriptor 13.
-
enumerator kTRDC_RegionDescriptor14
Region descriptor 14.
-
enumerator kTRDC_RegionDescriptor15
Region descriptor 15.
-
enumerator kTRDC_RegionDescriptor0
-
enum _trdc_MRC_domain
The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or several domains.
Values:
-
enumerator kTRDC_MrcDomain0
Domain 0.
-
enumerator kTRDC_MrcDomain1
Domain 1.
-
enumerator kTRDC_MrcDomain2
Domain 2.
-
enumerator kTRDC_MrcDomain3
Domain 3.
-
enumerator kTRDC_MrcDomain4
Domain 4.
-
enumerator kTRDC_MrcDomain5
Domain 5.
-
enumerator kTRDC_MrcDomain6
Domain 6.
-
enumerator kTRDC_MrcDomain7
Domain 7.
-
enumerator kTRDC_MrcDomain8
Domain 8.
-
enumerator kTRDC_MrcDomain9
Domain 9.
-
enumerator kTRDC_MrcDomain10
Domain 10.
-
enumerator kTRDC_MrcDomain11
Domain 11.
-
enumerator kTRDC_MrcDomain12
Domain 12.
-
enumerator kTRDC_MrcDomain13
Domain 13.
-
enumerator kTRDC_MrcDomain14
Domain 14.
-
enumerator kTRDC_MrcDomain15
Domain 15.
-
enumerator kTRDC_MrcDomain0
-
enum _trdc_MBC_domain
The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several domains.
Values:
-
enumerator kTRDC_MbcDomain0
Domain 0.
-
enumerator kTRDC_MbcDomain1
Domain 1.
-
enumerator kTRDC_MbcDomain2
Domain 2.
-
enumerator kTRDC_MbcDomain3
Domain 3.
-
enumerator kTRDC_MbcDomain4
Domain 4.
-
enumerator kTRDC_MbcDomain5
Domain 5.
-
enumerator kTRDC_MbcDomain6
Domain 6.
-
enumerator kTRDC_MbcDomain7
Domain 7.
-
enumerator kTRDC_MbcDomain0
-
enum _trdc_MBC_memory
The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several memory block.
Values:
-
enumerator kTRDC_MbcSlaveMemory0
Memory 0.
-
enumerator kTRDC_MbcSlaveMemory1
Memory 1.
-
enumerator kTRDC_MbcSlaveMemory2
Memory 2.
-
enumerator kTRDC_MbcSlaveMemory3
Memory 3.
-
enumerator kTRDC_MbcSlaveMemory0
-
enum _trdc_MBC_bit
The MBC bit enumeration, used to form a mask to set/clear configured words’ NSE.
Values:
-
enumerator kTRDC_MbcBit0
Bit 0.
-
enumerator kTRDC_MbcBit1
Bit 1.
-
enumerator kTRDC_MbcBit2
Bit 2.
-
enumerator kTRDC_MbcBit3
Bit 3.
-
enumerator kTRDC_MbcBit4
Bit 4.
-
enumerator kTRDC_MbcBit5
Bit 5.
-
enumerator kTRDC_MbcBit6
Bit 6.
-
enumerator kTRDC_MbcBit7
Bit 7.
-
enumerator kTRDC_MbcBit8
Bit 8.
-
enumerator kTRDC_MbcBit9
Bit 9.
-
enumerator kTRDC_MbcBit10
Bit 10.
-
enumerator kTRDC_MbcBit11
Bit 11.
-
enumerator kTRDC_MbcBit12
Bit 12.
-
enumerator kTRDC_MbcBit13
Bit 13.
-
enumerator kTRDC_MbcBit14
Bit 14.
-
enumerator kTRDC_MbcBit15
Bit 15.
-
enumerator kTRDC_MbcBit16
Bit 16.
-
enumerator kTRDC_MbcBit17
Bit 17.
-
enumerator kTRDC_MbcBit18
Bit 18.
-
enumerator kTRDC_MbcBit19
Bit 19.
-
enumerator kTRDC_MbcBit20
Bit 20.
-
enumerator kTRDC_MbcBit21
Bit 21.
-
enumerator kTRDC_MbcBit22
Bit 22.
-
enumerator kTRDC_MbcBit23
Bit 23.
-
enumerator kTRDC_MbcBit24
Bit 24.
-
enumerator kTRDC_MbcBit25
Bit 25.
-
enumerator kTRDC_MbcBit26
Bit 26.
-
enumerator kTRDC_MbcBit27
Bit 27.
-
enumerator kTRDC_MbcBit28
Bit 28.
-
enumerator kTRDC_MbcBit29
Bit 29.
-
enumerator kTRDC_MbcBit30
Bit 30.
-
enumerator kTRDC_MbcBit31
Bit 31.
-
enumerator kTRDC_MbcBit0
-
typedef struct _trdc_hardware_config trdc_hardware_config_t
TRDC hardware configuration.
-
typedef struct _trdc_slave_memory_hardware_config trdc_slave_memory_hardware_config_t
Hardware configuration of the two slave memories within each MBC(memory block checker).
-
typedef enum _trdc_did_sel trdc_did_sel_t
TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.
-
typedef enum _trdc_secure_attr trdc_secure_attr_t
TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.
-
typedef struct _trdc_processor_domain_assignment trdc_processor_domain_assignment_t
Domain assignment for the processor bus master.
-
typedef enum _trdc_privilege_attr trdc_privilege_attr_t
TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.
-
typedef struct _trdc_non_processor_domain_assignment trdc_non_processor_domain_assignment_t
Domain assignment for the non-processor bus master.
-
typedef struct _trdc_idau_config trdc_idau_config_t
IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.
-
typedef struct _trdc_flw_config trdc_flw_config_t
FLW(Flash Logical Window) configuration.
-
typedef enum _trdc_controller trdc_controller_t
TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.
-
typedef enum _trdc_error_state trdc_error_state_t
TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].
-
typedef enum _trdc_error_attr trdc_error_attr_t
TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].
-
typedef enum _trdc_error_type trdc_error_type_t
TRDC domain error access type definition TRDC_DERR_W1_n[ERW].
-
typedef struct _trdc_domain_error trdc_domain_error_t
TRDC domain error definition.
-
typedef struct _trdc_memory_access_control_config trdc_memory_access_control_config_t
Memory access control configuration for MBC/MRC.
-
typedef struct _trdc_mrc_region_descriptor_config trdc_mrc_region_descriptor_config_t
The configuration of each region descriptor per domain per MRC instance.
-
typedef struct _trdc_mbc_nse_update_config trdc_mbc_nse_update_config_t
The configuration of MBC NSE update.
-
typedef struct _trdc_mbc_memory_block_config trdc_mbc_memory_block_config_t
The configuration of each memory block per domain per MBC instance.
-
FSL_TRDC_DRIVER_VERSION
-
struct _trdc_hardware_config
- #include <fsl_trdc.h>
TRDC hardware configuration.
Public Members
-
uint8_t masterNumber
Number of bus masters.
-
uint8_t domainNumber
Number of domains.
-
uint8_t mbcNumber
Number of MBCs.
-
uint8_t mrcNumber
Number of MRCs.
-
uint8_t masterNumber
-
struct _trdc_slave_memory_hardware_config
- #include <fsl_trdc.h>
Hardware configuration of the two slave memories within each MBC(memory block checker).
Public Members
-
uint32_t blockNum
Number of blocks.
-
uint32_t blockSize
Block size.
-
uint32_t blockNum
-
struct _trdc_processor_domain_assignment
- #include <fsl_trdc.h>
Domain assignment for the processor bus master.
Public Members
-
uint32_t domainId
Domain ID.
-
uint32_t domainIdSelect
Domain ID select method, see trdc_did_sel_t.
-
uint32_t __pad0__
Reserved.
-
uint32_t secureAttr
Secure attribute, see trdc_secure_attr_t.
-
uint32_t __pad1__
Reserved.
-
uint32_t lock
Lock the register.
-
uint32_t __pad2__
Reserved.
-
uint32_t domainId
-
struct _trdc_non_processor_domain_assignment
- #include <fsl_trdc.h>
Domain assignment for the non-processor bus master.
Public Members
-
uint32_t domainId
Domain ID.
-
uint32_t privilegeAttr
Privileged attribute, see trdc_privilege_attr_t.
-
uint32_t secureAttr
Secure attribute, see trdc_secure_attr_t.
-
uint32_t bypassDomainId
Bypass domain ID.
-
uint32_t __pad0__
Reserved.
-
uint32_t lock
Lock the register.
-
uint32_t __pad1__
Reserved.
-
uint32_t domainId
-
struct _trdc_idau_config
- #include <fsl_trdc.h>
IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.
Public Members
-
uint32_t __pad0__
Reserved.
-
uint32_t lockSecureVTOR
Disable writes to secure VTOR(Vector Table Offset Register).
-
uint32_t lockNonsecureVTOR
Disable writes to non-secure VTOR, Application interrupt and Reset Control Registers.
-
uint32_t lockSecureMPU
Disable writes to secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor in Secure state.
-
uint32_t lockNonsecureMPU
Disable writes to non-secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor.
-
uint32_t lockSAU
Disable writes to SAU(Security Attribution Unit) registers.
-
uint32_t __pad1__
Reserved.
-
uint32_t __pad0__
-
struct _trdc_flw_config
- #include <fsl_trdc.h>
FLW(Flash Logical Window) configuration.
Public Members
-
uint16_t blockCount
Block count of the Flash Logic Window in 32KByte blocks.
-
uint32_t arrayBaseAddr
Flash array base address of the Flash Logical Window.
-
bool lock
Disable writes to FLW registers.
-
bool enable
Enable FLW function.
-
uint16_t blockCount
-
struct _trdc_domain_error
- #include <fsl_trdc.h>
TRDC domain error definition.
Public Members
-
trdc_controller_t controller
Which controller captured access violation.
-
uint32_t address
Access address that generated access violation.
-
trdc_error_state_t errorState
Error state.
-
trdc_error_attr_t errorAttr
Error attribute.
-
trdc_error_type_t errorType
Error type.
-
uint8_t errorPort
Error port.
-
uint8_t domainId
Domain ID.
-
uint8_t slaveMemoryIdx
The slave memory index. Only apply when violation in MBC.
-
trdc_controller_t controller
-
struct _trdc_memory_access_control_config
- #include <fsl_trdc.h>
Memory access control configuration for MBC/MRC.
Public Members
-
uint32_t nonsecureUsrX
Allow nonsecure user execute access.
-
uint32_t nonsecureUsrW
Allow nonsecure user write access.
-
uint32_t nonsecureUsrR
Allow nonsecure user read access.
-
uint32_t __pad0__
Reserved.
-
uint32_t nonsecurePrivX
Allow nonsecure privilege execute access.
-
uint32_t nonsecurePrivW
Allow nonsecure privilege write access.
-
uint32_t nonsecurePrivR
Allow nonsecure privilege read access.
-
uint32_t __pad1__
Reserved.
-
uint32_t secureUsrX
Allow secure user execute access.
-
uint32_t secureUsrW
Allow secure user write access.
-
uint32_t secureUsrR
Allow secure user read access.
-
uint32_t __pad2__
Reserved.
-
uint32_t securePrivX
Allownsecure privilege execute access.
-
uint32_t securePrivW
Allownsecure privilege write access.
-
uint32_t securePrivR
Allownsecure privilege read access.
-
uint32_t __pad3__
Reserved.
-
uint32_t lock
Lock the configuration until next reset, only apply to access control register 0.
-
uint32_t nonsecureUsrX
-
struct _trdc_mrc_region_descriptor_config
- #include <fsl_trdc.h>
The configuration of each region descriptor per domain per MRC instance.
Public Members
-
uint8_t memoryAccessControlSelect
Select one of the 8 access control policies for this region, for access cotrol policies see trdc_memory_access_control_config_t.
-
uint32_t startAddr
Physical start address.
-
bool valid
Lock the register.
-
bool nseEnable
Enable non-secure accesses and disable secure accesses.
-
uint32_t endAddr
Physical start address.
-
uint8_t mrcIdx
The index of the MRC for this configuration to take effect.
-
uint8_t domainIdx
The index of the domain for this configuration to take effect.
-
uint8_t regionIdx
The index of the region for this configuration to take effect.
-
uint8_t memoryAccessControlSelect
-
struct _trdc_mbc_nse_update_config
- #include <fsl_trdc.h>
The configuration of MBC NSE update.
Public Members
-
uint32_t __pad0__
Reserved.
-
uint32_t wordIdx
MBC configuration word index to be updated.
-
uint32_t __pad1__
Reserved.
-
uint32_t memorySelect
Bit mask of the selected memory to be updated. _trdc_MBC_memory.
-
uint32_t __pad2__
Reserved.
-
uint32_t domianSelect
Bit mask of the selected domain to be updated. _trdc_MBC_domain.
-
uint32_t __pad3__
Reserved.
-
uint32_t autoIncrement
Whether to increment the word index after current word is updated using this configuration.
-
uint32_t __pad0__
-
struct _trdc_mbc_memory_block_config
- #include <fsl_trdc.h>
The configuration of each memory block per domain per MBC instance.
Public Members
-
uint32_t memoryAccessControlSelect
Select one of the 8 access control policies for this memory block, for access cotrol policies see trdc_memory_access_control_config_t.
-
uint32_t nseEnable
Enable non-secure accesses and disable secure accesses.
-
uint32_t mbcIdx
The index of the MBC for this configuration to take effect.
-
uint32_t domainIdx
The index of the domain for this configuration to take effect.
-
uint32_t slaveMemoryIdx
The index of the slave memory for this configuration to take effect.
-
uint32_t memoryBlockIdx
The index of the memory block for this configuration to take effect.
-
uint32_t memoryAccessControlSelect
TSTMR: Timestamp Timer Driver
-
FSL_TSTMR_DRIVER_VERSION
Version 2.0.2
-
static inline uint64_t TSTMR_ReadTimeStamp(TSTMR_Type *base)
Reads the time stamp.
This function reads the low and high registers and returns the 56-bit free running counter value. This can be read by software at any time to determine the software ticks. TSTMR registers can be read with 32-bit accesses only. The TSTMR LOW read should occur first, followed by the TSTMR HIGH read.
- Parameters:
base – TSTMR peripheral base address.
- Returns:
The 56-bit time stamp value.
-
static inline void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs)
Delays for a specified number of microseconds.
This function repeatedly reads the timestamp register and waits for the user-specified delay value.
- Parameters:
base – TSTMR peripheral base address.
delayInUs – Delay value in microseconds.
-
FSL_COMPONENT_ID
USDHC: Ultra Secured Digital Host Controller Driver
-
void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)
USDHC module initialization function.
Configures the USDHC according to the user configuration.
Example:
usdhc_config_t config; config.cardDetectDat3 = false; config.endianMode = kUSDHC_EndianModeLittle; config.dmaMode = kUSDHC_DmaModeAdma2; config.readWatermarkLevel = 128U; config.writeWatermarkLevel = 128U; USDHC_Init(USDHC, &config);
- Parameters:
base – USDHC peripheral base address.
config – USDHC configuration information.
- Return values:
kStatus_Success – Operate successfully.
-
void USDHC_Deinit(USDHC_Type *base)
Deinitializes the USDHC.
- Parameters:
base – USDHC peripheral base address.
-
bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout)
Resets the USDHC.
- Parameters:
base – USDHC peripheral base address.
mask – The reset type mask(_usdhc_reset).
timeout – Timeout for reset.
- Return values:
true – Reset successfully.
false – Reset failed.
-
status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_data_t *dataConfig, uint32_t flags)
Sets the DMA descriptor table configuration. A high level DMA descriptor configuration function.
- Parameters:
base – USDHC peripheral base address.
dmaConfig – ADMA configuration
dataConfig – Data descriptor
flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.
- Return values:
kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.
kStatus_Success – Operate successfully.
-
status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, const uint32_t *dataAddr, bool enAutoCmd23)
Internal DMA configuration. This function is used to config the USDHC DMA related registers.
- Parameters:
base – USDHC peripheral base address.
dmaConfig – ADMA configuration.
dataAddr – Transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.
enAutoCmd23 – Flag to indicate Auto CMD23 is enable or not, a simple DMA parameter, if ADMA is used, leave it to false.
- Return values:
kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.
kStatus_Success – Operate successfully.
-
status_t USDHC_SetADMA2Descriptor(uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)
Sets the ADMA2 descriptor table configuration.
- Parameters:
admaTable – ADMA table address.
admaTableWords – ADMA table length.
dataBufferAddr – Data buffer address.
dataBytes – Data Data length.
flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.
- Return values:
kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.
kStatus_Success – Operate successfully.
-
status_t USDHC_SetADMA1Descriptor(uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)
Sets the ADMA1 descriptor table configuration.
- Parameters:
admaTable – ADMA table address.
admaTableWords – ADMA table length.
dataBufferAddr – Data buffer address.
dataBytes – Data length.
flags – ADAM descriptor flag, used to indicate to create multiple or single descriptor, please refer to enum _usdhc_adma_flag.
- Return values:
kStatus_OutOfRange – ADMA descriptor table length isn’t enough to describe data.
kStatus_Success – Operate successfully.
-
static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable)
Enables internal DMA.
- Parameters:
base – USDHC peripheral base address.
enable – enable or disable flag
-
static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask)
Enables the interrupt status.
- Parameters:
base – USDHC peripheral base address.
mask – Interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask)
Disables the interrupt status.
- Parameters:
base – USDHC peripheral base address.
mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask)
Enables the interrupt signal corresponding to the interrupt status flag.
- Parameters:
base – USDHC peripheral base address.
mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask)
Disables the interrupt signal corresponding to the interrupt status flag.
- Parameters:
base – USDHC peripheral base address.
mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base)
Gets the enabled interrupt status.
- Parameters:
base – USDHC peripheral base address.
- Returns:
Current interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base)
Gets the current interrupt status.
- Parameters:
base – USDHC peripheral base address.
- Returns:
Current interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask)
Clears a specified interrupt status. write 1 clears.
- Parameters:
base – USDHC peripheral base address.
mask – The interrupt status flags mask(_usdhc_interrupt_status_flag).
-
static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base)
Gets the status of auto command 12 error.
- Parameters:
base – USDHC peripheral base address.
- Returns:
Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag).
-
static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base)
Gets the status of the ADMA error.
- Parameters:
base – USDHC peripheral base address.
- Returns:
ADMA error status flags mask(_usdhc_adma_error_status_flag).
-
static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base)
Gets a present status.
This function gets the present USDHC’s status except for an interrupt status and an error status.
- Parameters:
base – USDHC peripheral base address.
- Returns:
Present USDHC’s status flags mask(_usdhc_present_status_flag).
-
void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability)
Gets the capability information.
- Parameters:
base – USDHC peripheral base address.
capability – Structure to save capability information.
-
static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable)
Forces the card clock on.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
-
uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz)
Sets the SD bus clock frequency.
- Parameters:
base – USDHC peripheral base address.
srcClock_Hz – USDHC source clock frequency united in Hz.
busClock_Hz – SD bus clock frequency united in Hz.
- Returns:
The nearest frequency of busClock_Hz configured for SD bus.
-
bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout)
Sends 80 clocks to the card to set it to the active state.
This function must be called each time the card is inserted to ensure that the card can receive the command correctly.
- Parameters:
base – USDHC peripheral base address.
timeout – Timeout to initialize card.
- Return values:
true – Set card active successfully.
false – Set card active failed.
-
static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high)
Triggers a hardware reset.
- Parameters:
base – USDHC peripheral base address.
high – 1 or 0 level
-
static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width)
Sets the data transfer width.
- Parameters:
base – USDHC peripheral base address.
width – Data transfer width.
-
static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data)
Fills the data port.
This function is used to implement the data transfer by Data Port instead of DMA.
- Parameters:
base – USDHC peripheral base address.
data – The data about to be sent.
-
static inline uint32_t USDHC_ReadData(USDHC_Type *base)
Retrieves the data from the data port.
This function is used to implement the data transfer by Data Port instead of DMA.
- Parameters:
base – USDHC peripheral base address.
- Returns:
The data has been read.
-
void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command)
Sends command function.
- Parameters:
base – USDHC peripheral base address.
command – configuration
-
static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable)
Enables or disables a wakeup event in low-power mode.
- Parameters:
base – USDHC peripheral base address.
mask – Wakeup events mask(_usdhc_wakeup_event).
enable – True to enable, false to disable.
-
static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable)
Detects card insert status.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
-
static inline bool USDHC_DetectCardInsert(USDHC_Type *base)
Detects card insert status.
- Parameters:
base – USDHC peripheral base address.
-
static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable)
Enables or disables the SDIO card control.
- Parameters:
base – USDHC peripheral base address.
mask – SDIO card control flags mask(_usdhc_sdio_control_flag).
enable – True to enable, false to disable.
-
static inline void USDHC_SetContinueRequest(USDHC_Type *base)
Restarts a transaction which has stopped at the block GAP for the SDIO card.
- Parameters:
base – USDHC peripheral base address.
-
static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable)
Request stop at block gap function.
- Parameters:
base – USDHC peripheral base address.
enable – True to stop at block gap, false to normal transfer.
-
void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config)
Configures the MMC boot feature.
Example:
usdhc_boot_config_t config; config.ackTimeoutCount = 4; config.bootMode = kUSDHC_BootModeNormal; config.blockCount = 5; config.enableBootAck = true; config.enableBoot = true; config.enableAutoStopAtBlockGap = true; USDHC_SetMmcBootConfig(USDHC, &config);
- Parameters:
base – USDHC peripheral base address.
config – The MMC boot configuration information.
-
static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable)
Enables or disables the mmc boot mode.
- Parameters:
base – USDHC peripheral base address.
enable – True to enable, false to disable.
-
static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask)
Forces generating events according to the given mask.
- Parameters:
base – USDHC peripheral base address.
mask – The force events bit posistion (_usdhc_force_event).
-
static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base)
Checks the SDR50 mode request tuning bit. When this bit set, application shall perform tuning for SDR50 mode.
- Parameters:
base – USDHC peripheral base address.
-
static inline bool USDHC_RequestReTuning(USDHC_Type *base)
Checks the request re-tuning bit. When this bit is set, user should do manual tuning or standard tuning function.
- Parameters:
base – USDHC peripheral base address.
-
static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable)
The SDR104 mode auto tuning enable and disable. This function should be called after tuning function execute pass, auto tuning will handle by hardware.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
-
void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base)
The auto tuning enbale for CMD/DATA line.
- Parameters:
base – USDHC peripheral base address.
-
void USDHC_EnableManualTuning(USDHC_Type *base, bool enable)
Manual tuning trigger or abort. User should handle the tuning cmd and find the boundary of the delay then calucate a average value which will be configured to the CLK_TUNE_CTRL_STATUS This function should be called before function USDHC_AdjustDelayForManualTuning.
- Parameters:
base – USDHC peripheral base address.
enable – tuning enable flag
-
static inline uint32_t USDHC_GetTuningDelayStatus(USDHC_Type *base)
Get the tuning delay cell setting.
- Parameters:
base – USDHC peripheral base address.
- Return values:
CLK – Tuning Control and Status register value.
-
status_t USDHC_SetTuningDelay(USDHC_Type *base, uint32_t preDelay, uint32_t outDelay, uint32_t postDelay)
The tuning delay cell setting.
- Parameters:
base – USDHC peripheral base address.
preDelay – Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE.
outDelay – Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT.
postDelay – Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST.
- Return values:
kStatus_Fail – config the delay setting fail
kStatus_Success – config the delay setting success
-
status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay)
Adjusts delay for mannual tuning.
- Deprecated:
Do not use this function. It has been superceded by USDHC_SetTuingDelay
- Parameters:
base – USDHC peripheral base address.
delay – setting configuration
- Return values:
kStatus_Fail – config the delay setting fail
kStatus_Success – config the delay setting success
-
static inline void USDHC_SetStandardTuningCounter(USDHC_Type *base, uint8_t counter)
set tuning counter tuning.
- Parameters:
base – USDHC peripheral base address.
counter – tuning counter
- Return values:
kStatus_Fail – config the delay setting fail
kStatus_Success – config the delay setting success
-
void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable)
The enable standard tuning function. The standard tuning window and tuning counter using the default config tuning cmd is sent by the software, user need to check whether the tuning result can be used for SDR50, SDR104, and HS200 mode tuning.
- Parameters:
base – USDHC peripheral base address.
tuningStartTap – start tap
step – tuning step
enable – enable/disable flag
-
static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base)
Gets execute STD tuning status.
- Parameters:
base – USDHC peripheral base address.
-
static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base)
Checks STD tuning result.
- Parameters:
base – USDHC peripheral base address.
-
static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base)
Checks tuning error.
- Parameters:
base – USDHC peripheral base address.
-
void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos)
The enable/disable DDR mode.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
nibblePos – nibble position
-
static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable)
The enable/disable HS400 mode.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
-
static inline void USDHC_ResetStrobeDLL(USDHC_Type *base)
Resets the strobe DLL.
- Parameters:
base – USDHC peripheral base address.
-
static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable)
Enables/disables the strobe DLL.
- Parameters:
base – USDHC peripheral base address.
enable – enable/disable flag
-
void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval)
Configs the strobe DLL delay target and update interval.
- Parameters:
base – USDHC peripheral base address.
delayTarget – delay target
updateInterval – update interval
-
static inline void USDHC_SetStrobeDllOverride(USDHC_Type *base, uint32_t delayTaps)
Enables manual override for slave delay chain using STROBE_SLV_OVERRIDE_VAL.
- Parameters:
base – USDHC peripheral base address.
delayTaps – Valid delay taps range from 1 - 128 taps. A value of 0 selects tap 1, and a value of 0x7F selects tap 128.
-
static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base)
Gets the strobe DLL status.
- Parameters:
base – USDHC peripheral base address.
-
void USDHC_SetDataConfig(USDHC_Type *base, usdhc_transfer_direction_t dataDirection, uint32_t blockCount, uint32_t blockSize)
USDHC data configuration.
- Parameters:
base – USDHC peripheral base address.
dataDirection – Data direction, tx or rx.
blockCount – Data block count.
blockSize – Data block size.
-
void USDHC_TransferCreateHandle(USDHC_Type *base, usdhc_handle_t *handle, const usdhc_transfer_callback_t *callback, void *userData)
Creates the USDHC handle.
- Parameters:
base – USDHC peripheral base address.
handle – USDHC handle pointer.
callback – Structure pointer to contain all callback functions.
userData – Callback function parameter.
-
status_t USDHC_TransferNonBlocking(USDHC_Type *base, usdhc_handle_t *handle, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer)
Transfers the command/data using an interrupt and an asynchronous method.
This function sends a command and data and returns immediately. It doesn’t wait for the transfer to complete or to encounter an error. The application must not call this API in multiple threads at the same time. Because of that this API doesn’t support the re-entry mechanism.
Note
Call API USDHC_TransferCreateHandle when calling this API.
- Parameters:
base – USDHC peripheral base address.
handle – USDHC handle.
dmaConfig – ADMA configuration.
transfer – Transfer content.
- Return values:
kStatus_InvalidArgument – Argument is invalid.
kStatus_USDHC_BusyTransferring – Busy transferring.
kStatus_USDHC_PrepareAdmaDescriptorFailed – Prepare ADMA descriptor failed.
kStatus_Success – Operate successfully.
-
status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer)
Transfers the command/data using a blocking method.
This function waits until the command response/data is received or the USDHC encounters an error by polling the status flag.
The application must not call this API in multiple threads at the same time. Because this API doesn’t support the re-entry mechanism.
Note
There is no need to call API USDHC_TransferCreateHandle when calling this API.
- Parameters:
base – USDHC peripheral base address.
dmaConfig – adma configuration
transfer – Transfer content.
- Return values:
kStatus_InvalidArgument – Argument is invalid.
kStatus_USDHC_PrepareAdmaDescriptorFailed – Prepare ADMA descriptor failed.
kStatus_USDHC_SendCommandFailed – Send command failed.
kStatus_USDHC_TransferDataFailed – Transfer data failed.
kStatus_Success – Operate successfully.
-
void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle)
IRQ handler for the USDHC.
This function deals with the IRQs on the given host controller.
- Parameters:
base – USDHC peripheral base address.
handle – USDHC handle.
-
FSL_USDHC_DRIVER_VERSION
Driver version 2.8.4.
Enum _usdhc_status. USDHC status.
Values:
-
enumerator kStatus_USDHC_BusyTransferring
Transfer is on-going.
-
enumerator kStatus_USDHC_PrepareAdmaDescriptorFailed
Set DMA descriptor failed.
-
enumerator kStatus_USDHC_SendCommandFailed
Send command failed.
-
enumerator kStatus_USDHC_TransferDataFailed
Transfer data failed.
-
enumerator kStatus_USDHC_DMADataAddrNotAlign
Data address not aligned.
-
enumerator kStatus_USDHC_ReTuningRequest
Re-tuning request.
-
enumerator kStatus_USDHC_TuningError
Tuning error.
-
enumerator kStatus_USDHC_NotSupport
Not support.
-
enumerator kStatus_USDHC_TransferDataComplete
Transfer data complete.
-
enumerator kStatus_USDHC_SendCommandSuccess
Transfer command complete.
-
enumerator kStatus_USDHC_TransferDMAComplete
Transfer DMA complete.
-
enumerator kStatus_USDHC_BusyTransferring
Enum _usdhc_capability_flag. Host controller capabilities flag mask. .
Values:
-
enumerator kUSDHC_SupportAdmaFlag
Support ADMA.
-
enumerator kUSDHC_SupportHighSpeedFlag
Support high-speed.
-
enumerator kUSDHC_SupportDmaFlag
Support DMA.
-
enumerator kUSDHC_SupportSuspendResumeFlag
Support suspend/resume.
-
enumerator kUSDHC_SupportV330Flag
Support voltage 3.3V.
-
enumerator kUSDHC_SupportV300Flag
Support voltage 3.0V.
-
enumerator kUSDHC_Support4BitFlag
Flag in HTCAPBLT_MBL’s position, supporting 4-bit mode.
-
enumerator kUSDHC_Support8BitFlag
Flag in HTCAPBLT_MBL’s position, supporting 8-bit mode.
-
enumerator kUSDHC_SupportDDR50Flag
SD version 3.0 new feature, supporting DDR50 mode.
-
enumerator kUSDHC_SupportSDR104Flag
Support SDR104 mode.
-
enumerator kUSDHC_SupportSDR50Flag
Support SDR50 mode.
-
enumerator kUSDHC_SupportAdmaFlag
Enum _usdhc_wakeup_event. Wakeup event mask. .
Values:
-
enumerator kUSDHC_WakeupEventOnCardInt
Wakeup on card interrupt.
-
enumerator kUSDHC_WakeupEventOnCardInsert
Wakeup on card insertion.
-
enumerator kUSDHC_WakeupEventOnCardRemove
Wakeup on card removal.
-
enumerator kUSDHC_WakeupEventsAll
All wakeup events
-
enumerator kUSDHC_WakeupEventOnCardInt
Enum _usdhc_reset. Reset type mask. .
Values:
-
enumerator kUSDHC_ResetAll
Reset all except card detection.
-
enumerator kUSDHC_ResetCommand
Reset command line.
-
enumerator kUSDHC_ResetData
Reset data line.
-
enumerator kUSDHC_ResetTuning
Reset tuning circuit.
-
enumerator kUSDHC_ResetsAll
All reset types
-
enumerator kUSDHC_ResetAll
Enum _usdhc_transfer_flag. Transfer flag mask.
Values:
-
enumerator kUSDHC_EnableDmaFlag
Enable DMA.
-
enumerator kUSDHC_CommandTypeSuspendFlag
Suspend command.
-
enumerator kUSDHC_CommandTypeResumeFlag
Resume command.
-
enumerator kUSDHC_CommandTypeAbortFlag
Abort command.
-
enumerator kUSDHC_EnableBlockCountFlag
Enable block count.
-
enumerator kUSDHC_EnableAutoCommand12Flag
Enable auto CMD12.
-
enumerator kUSDHC_DataReadFlag
Enable data read.
-
enumerator kUSDHC_MultipleBlockFlag
Multiple block data read/write.
-
enumerator kUSDHC_EnableAutoCommand23Flag
Enable auto CMD23.
-
enumerator kUSDHC_ResponseLength136Flag
136-bit response length.
-
enumerator kUSDHC_ResponseLength48Flag
48-bit response length.
-
enumerator kUSDHC_ResponseLength48BusyFlag
48-bit response length with busy status.
-
enumerator kUSDHC_EnableCrcCheckFlag
Enable CRC check.
-
enumerator kUSDHC_EnableIndexCheckFlag
Enable index check.
-
enumerator kUSDHC_DataPresentFlag
Data present flag.
-
enumerator kUSDHC_EnableDmaFlag
Enum _usdhc_present_status_flag. Present status flag mask. .
Values:
-
enumerator kUSDHC_CommandInhibitFlag
Command inhibit.
-
enumerator kUSDHC_DataInhibitFlag
Data inhibit.
-
enumerator kUSDHC_DataLineActiveFlag
Data line active.
-
enumerator kUSDHC_SdClockStableFlag
SD bus clock stable.
-
enumerator kUSDHC_WriteTransferActiveFlag
Write transfer active.
-
enumerator kUSDHC_ReadTransferActiveFlag
Read transfer active.
-
enumerator kUSDHC_BufferWriteEnableFlag
Buffer write enable.
-
enumerator kUSDHC_BufferReadEnableFlag
Buffer read enable.
-
enumerator kUSDHC_ReTuningRequestFlag
Re-tuning request flag, only used for SDR104 mode.
-
enumerator kUSDHC_DelaySettingFinishedFlag
Delay setting finished flag.
-
enumerator kUSDHC_CardInsertedFlag
Card inserted.
-
enumerator kUSDHC_CommandLineLevelFlag
Command line signal level.
-
enumerator kUSDHC_Data0LineLevelFlag
Data0 line signal level.
-
enumerator kUSDHC_Data1LineLevelFlag
Data1 line signal level.
-
enumerator kUSDHC_Data2LineLevelFlag
Data2 line signal level.
-
enumerator kUSDHC_Data3LineLevelFlag
Data3 line signal level.
-
enumerator kUSDHC_Data4LineLevelFlag
Data4 line signal level.
-
enumerator kUSDHC_Data5LineLevelFlag
Data5 line signal level.
-
enumerator kUSDHC_Data6LineLevelFlag
Data6 line signal level.
-
enumerator kUSDHC_Data7LineLevelFlag
Data7 line signal level.
-
enumerator kUSDHC_CommandInhibitFlag
Enum _usdhc_interrupt_status_flag. Interrupt status flag mask. .
Values:
-
enumerator kUSDHC_CommandCompleteFlag
Command complete.
-
enumerator kUSDHC_DataCompleteFlag
Data complete.
-
enumerator kUSDHC_BlockGapEventFlag
Block gap event.
-
enumerator kUSDHC_DmaCompleteFlag
DMA interrupt.
-
enumerator kUSDHC_BufferWriteReadyFlag
Buffer write ready.
-
enumerator kUSDHC_BufferReadReadyFlag
Buffer read ready.
-
enumerator kUSDHC_CardInsertionFlag
Card inserted.
-
enumerator kUSDHC_CardRemovalFlag
Card removed.
-
enumerator kUSDHC_CardInterruptFlag
Card interrupt.
-
enumerator kUSDHC_ReTuningEventFlag
Re-Tuning event, only for SD3.0 SDR104 mode.
-
enumerator kUSDHC_TuningPassFlag
SDR104 mode tuning pass flag.
-
enumerator kUSDHC_TuningErrorFlag
SDR104 tuning error flag.
-
enumerator kUSDHC_CommandTimeoutFlag
Command timeout error.
-
enumerator kUSDHC_CommandCrcErrorFlag
Command CRC error.
-
enumerator kUSDHC_CommandEndBitErrorFlag
Command end bit error.
-
enumerator kUSDHC_CommandIndexErrorFlag
Command index error.
-
enumerator kUSDHC_DataTimeoutFlag
Data timeout error.
-
enumerator kUSDHC_DataCrcErrorFlag
Data CRC error.
-
enumerator kUSDHC_DataEndBitErrorFlag
Data end bit error.
-
enumerator kUSDHC_AutoCommand12ErrorFlag
Auto CMD12 error.
-
enumerator kUSDHC_DmaErrorFlag
DMA error.
-
enumerator kUSDHC_CommandErrorFlag
Command error
-
enumerator kUSDHC_DataErrorFlag
Data error
-
enumerator kUSDHC_ErrorFlag
All error
-
enumerator kUSDHC_DataFlag
Data interrupts
-
enumerator kUSDHC_DataDMAFlag
Data interrupts
-
enumerator kUSDHC_CommandFlag
Command interrupts
-
enumerator kUSDHC_CardDetectFlag
Card detection interrupts
-
enumerator kUSDHC_SDR104TuningFlag
SDR104 tuning flag.
-
enumerator kUSDHC_AllInterruptFlags
All flags mask
-
enumerator kUSDHC_CommandCompleteFlag
Enum _usdhc_auto_command12_error_status_flag. Auto CMD12 error status flag mask. .
Values:
-
enumerator kUSDHC_AutoCommand12NotExecutedFlag
Not executed error.
-
enumerator kUSDHC_AutoCommand12TimeoutFlag
Timeout error.
-
enumerator kUSDHC_AutoCommand12EndBitErrorFlag
End bit error.
-
enumerator kUSDHC_AutoCommand12CrcErrorFlag
CRC error.
-
enumerator kUSDHC_AutoCommand12IndexErrorFlag
Index error.
-
enumerator kUSDHC_AutoCommand12NotIssuedFlag
Not issued error.
-
enumerator kUSDHC_AutoCommand12NotExecutedFlag
Enum _usdhc_standard_tuning. Standard tuning flag.
Values:
-
enumerator kUSDHC_ExecuteTuning
Used to start tuning procedure.
-
enumerator kUSDHC_TuningSampleClockSel
When std_tuning_en bit is set, this bit is used to select sampleing clock.
-
enumerator kUSDHC_ExecuteTuning
Enum _usdhc_adma_error_status_flag. ADMA error status flag mask. .
Values:
-
enumerator kUSDHC_AdmaLenghMismatchFlag
Length mismatch error.
-
enumerator kUSDHC_AdmaDescriptorErrorFlag
Descriptor error.
-
enumerator kUSDHC_AdmaLenghMismatchFlag
Enum _usdhc_adma_error_state. ADMA error state.
This state is the detail state when ADMA error has occurred.
Values:
-
enumerator kUSDHC_AdmaErrorStateStopDma
Stop DMA, previous location set in the ADMA system address is errored address.
-
enumerator kUSDHC_AdmaErrorStateFetchDescriptor
Fetch descriptor, current location set in the ADMA system address is errored address.
-
enumerator kUSDHC_AdmaErrorStateChangeAddress
Change address, no DMA error has occurred.
-
enumerator kUSDHC_AdmaErrorStateTransferData
Transfer data, previous location set in the ADMA system address is errored address.
-
enumerator kUSDHC_AdmaErrorStateInvalidLength
Invalid length in ADMA descriptor.
-
enumerator kUSDHC_AdmaErrorStateInvalidDescriptor
Invalid descriptor fetched by ADMA.
-
enumerator kUSDHC_AdmaErrorState
ADMA error state
-
enumerator kUSDHC_AdmaErrorStateStopDma
Enum _usdhc_force_event. Force event bit position. .
Values:
-
enumerator kUSDHC_ForceEventAutoCommand12NotExecuted
Auto CMD12 not executed error.
-
enumerator kUSDHC_ForceEventAutoCommand12Timeout
Auto CMD12 timeout error.
-
enumerator kUSDHC_ForceEventAutoCommand12CrcError
Auto CMD12 CRC error.
-
enumerator kUSDHC_ForceEventEndBitError
Auto CMD12 end bit error.
-
enumerator kUSDHC_ForceEventAutoCommand12IndexError
Auto CMD12 index error.
-
enumerator kUSDHC_ForceEventAutoCommand12NotIssued
Auto CMD12 not issued error.
-
enumerator kUSDHC_ForceEventCommandTimeout
Command timeout error.
-
enumerator kUSDHC_ForceEventCommandCrcError
Command CRC error.
-
enumerator kUSDHC_ForceEventCommandEndBitError
Command end bit error.
-
enumerator kUSDHC_ForceEventCommandIndexError
Command index error.
-
enumerator kUSDHC_ForceEventDataTimeout
Data timeout error.
-
enumerator kUSDHC_ForceEventDataCrcError
Data CRC error.
-
enumerator kUSDHC_ForceEventDataEndBitError
Data end bit error.
-
enumerator kUSDHC_ForceEventAutoCommand12Error
Auto CMD12 error.
-
enumerator kUSDHC_ForceEventCardInt
Card interrupt.
-
enumerator kUSDHC_ForceEventDmaError
Dma error.
-
enumerator kUSDHC_ForceEventTuningError
Tuning error.
-
enumerator kUSDHC_ForceEventsAll
All force event flags mask.
-
enumerator kUSDHC_ForceEventAutoCommand12NotExecuted
-
enum _usdhc_transfer_direction
Data transfer direction.
Values:
-
enumerator kUSDHC_TransferDirectionReceive
USDHC transfer direction receive.
-
enumerator kUSDHC_TransferDirectionSend
USDHC transfer direction send.
-
enumerator kUSDHC_TransferDirectionReceive
-
enum _usdhc_data_bus_width
Data transfer width.
Values:
-
enumerator kUSDHC_DataBusWidth1Bit
1-bit mode
-
enumerator kUSDHC_DataBusWidth4Bit
4-bit mode
-
enumerator kUSDHC_DataBusWidth8Bit
8-bit mode
-
enumerator kUSDHC_DataBusWidth1Bit
-
enum _usdhc_endian_mode
Endian mode.
Values:
-
enumerator kUSDHC_EndianModeBig
Big endian mode.
-
enumerator kUSDHC_EndianModeHalfWordBig
Half word big endian mode.
-
enumerator kUSDHC_EndianModeLittle
Little endian mode.
-
enumerator kUSDHC_EndianModeBig
-
enum _usdhc_dma_mode
DMA mode.
Values:
-
enumerator kUSDHC_DmaModeSimple
External DMA.
-
enumerator kUSDHC_DmaModeAdma1
ADMA1 is selected.
-
enumerator kUSDHC_DmaModeAdma2
ADMA2 is selected.
-
enumerator kUSDHC_ExternalDMA
External DMA mode selected.
-
enumerator kUSDHC_DmaModeSimple
Enum _usdhc_sdio_control_flag. SDIO control flag mask. .
Values:
-
enumerator kUSDHC_StopAtBlockGapFlag
Stop at block gap.
-
enumerator kUSDHC_ReadWaitControlFlag
Read wait control.
-
enumerator kUSDHC_InterruptAtBlockGapFlag
Interrupt at block gap.
-
enumerator kUSDHC_ReadDoneNo8CLK
Read done without 8 clk for block gap.
-
enumerator kUSDHC_ExactBlockNumberReadFlag
Exact block number read.
-
enumerator kUSDHC_StopAtBlockGapFlag
-
enum _usdhc_boot_mode
MMC card boot mode.
Values:
-
enumerator kUSDHC_BootModeNormal
Normal boot
-
enumerator kUSDHC_BootModeAlternative
Alternative boot
-
enumerator kUSDHC_BootModeNormal
-
enum _usdhc_card_command_type
The command type.
Values:
-
enumerator kCARD_CommandTypeNormal
Normal command
-
enumerator kCARD_CommandTypeSuspend
Suspend command
-
enumerator kCARD_CommandTypeResume
Resume command
-
enumerator kCARD_CommandTypeAbort
Abort command
-
enumerator kCARD_CommandTypeEmpty
Empty command
-
enumerator kCARD_CommandTypeNormal
-
enum _usdhc_card_response_type
The command response type.
Defines the command response type from card to host controller.
Values:
-
enumerator kCARD_ResponseTypeNone
Response type: none
-
enumerator kCARD_ResponseTypeR1
Response type: R1
-
enumerator kCARD_ResponseTypeR1b
Response type: R1b
-
enumerator kCARD_ResponseTypeR2
Response type: R2
-
enumerator kCARD_ResponseTypeR3
Response type: R3
-
enumerator kCARD_ResponseTypeR4
Response type: R4
-
enumerator kCARD_ResponseTypeR5
Response type: R5
-
enumerator kCARD_ResponseTypeR5b
Response type: R5b
-
enumerator kCARD_ResponseTypeR6
Response type: R6
-
enumerator kCARD_ResponseTypeR7
Response type: R7
-
enumerator kCARD_ResponseTypeNone
Enum _usdhc_adma1_descriptor_flag. The mask for the control/status field in ADMA1 descriptor.
Values:
-
enumerator kUSDHC_Adma1DescriptorValidFlag
Valid flag.
-
enumerator kUSDHC_Adma1DescriptorEndFlag
End flag.
-
enumerator kUSDHC_Adma1DescriptorInterrupFlag
Interrupt flag.
-
enumerator kUSDHC_Adma1DescriptorActivity1Flag
Activity 1 flag.
-
enumerator kUSDHC_Adma1DescriptorActivity2Flag
Activity 2 flag.
-
enumerator kUSDHC_Adma1DescriptorTypeNop
No operation.
-
enumerator kUSDHC_Adma1DescriptorTypeTransfer
Transfer data.
-
enumerator kUSDHC_Adma1DescriptorTypeLink
Link descriptor.
-
enumerator kUSDHC_Adma1DescriptorTypeSetLength
Set data length.
-
enumerator kUSDHC_Adma1DescriptorValidFlag
Enum _usdhc_adma2_descriptor_flag. ADMA1 descriptor control and status mask.
Values:
-
enumerator kUSDHC_Adma2DescriptorValidFlag
Valid flag.
-
enumerator kUSDHC_Adma2DescriptorEndFlag
End flag.
-
enumerator kUSDHC_Adma2DescriptorInterruptFlag
Interrupt flag.
-
enumerator kUSDHC_Adma2DescriptorActivity1Flag
Activity 1 mask.
-
enumerator kUSDHC_Adma2DescriptorActivity2Flag
Activity 2 mask.
-
enumerator kUSDHC_Adma2DescriptorTypeNop
No operation.
-
enumerator kUSDHC_Adma2DescriptorTypeReserved
Reserved.
-
enumerator kUSDHC_Adma2DescriptorTypeTransfer
Transfer type.
-
enumerator kUSDHC_Adma2DescriptorTypeLink
Link type.
-
enumerator kUSDHC_Adma2DescriptorValidFlag
Enum _usdhc_adma_flag. ADMA descriptor configuration flag. .
Values:
-
enumerator kUSDHC_AdmaDescriptorSingleFlag
Try to finish the transfer in a single ADMA descriptor. If transfer size is bigger than one ADMA descriptor’s ability, new another descriptor for data transfer.
-
enumerator kUSDHC_AdmaDescriptorMultipleFlag
Create multiple ADMA descriptors within the ADMA table, this is used for mmc boot mode specifically, which need to modify the ADMA descriptor on the fly, so the flag should be used combining with stop at block gap feature.
-
enumerator kUSDHC_AdmaDescriptorSingleFlag
-
enum _usdhc_burst_len
DMA transfer burst len config.
Values:
-
enumerator kUSDHC_EnBurstLenForINCR
Enable burst len for INCR.
-
enumerator kUSDHC_EnBurstLenForINCR4816
Enable burst len for INCR4/INCR8/INCR16.
-
enumerator kUSDHC_EnBurstLenForINCR4816WRAP
Enable burst len for INCR4/8/16 WRAP.
-
enumerator kUSDHC_EnBurstLenForINCR
Enum _usdhc_transfer_data_type. Tansfer data type definition.
Values:
-
enumerator kUSDHC_TransferDataNormal
Transfer normal read/write data.
-
enumerator kUSDHC_TransferDataTuning
Transfer tuning data.
-
enumerator kUSDHC_TransferDataBoot
Transfer boot data.
-
enumerator kUSDHC_TransferDataBootcontinous
Transfer boot data continuously.
-
enumerator kUSDHC_TransferDataNormal
-
typedef enum _usdhc_transfer_direction usdhc_transfer_direction_t
Data transfer direction.
-
typedef enum _usdhc_data_bus_width usdhc_data_bus_width_t
Data transfer width.
-
typedef enum _usdhc_endian_mode usdhc_endian_mode_t
Endian mode.
-
typedef enum _usdhc_dma_mode usdhc_dma_mode_t
DMA mode.
-
typedef enum _usdhc_boot_mode usdhc_boot_mode_t
MMC card boot mode.
-
typedef enum _usdhc_card_command_type usdhc_card_command_type_t
The command type.
-
typedef enum _usdhc_card_response_type usdhc_card_response_type_t
The command response type.
Defines the command response type from card to host controller.
-
typedef enum _usdhc_burst_len usdhc_burst_len_t
DMA transfer burst len config.
-
typedef uint32_t usdhc_adma1_descriptor_t
Defines the ADMA1 descriptor structure.
-
typedef struct _usdhc_adma2_descriptor usdhc_adma2_descriptor_t
Defines the ADMA2 descriptor structure.
-
typedef struct _usdhc_capability usdhc_capability_t
USDHC capability information.
Defines a structure to save the capability information of USDHC.
-
typedef struct _usdhc_boot_config usdhc_boot_config_t
Data structure to configure the MMC boot feature.
-
typedef struct _usdhc_config usdhc_config_t
Data structure to initialize the USDHC.
-
typedef struct _usdhc_command usdhc_command_t
Card command descriptor.
Defines card command-related attribute.
-
typedef struct _usdhc_adma_config usdhc_adma_config_t
ADMA configuration.
-
typedef struct _usdhc_scatter_gather_data_list usdhc_scatter_gather_data_list_t
Card scatter gather data list.
Allow application register uncontinuous data buffer for data transfer.
-
typedef struct _usdhc_scatter_gather_data usdhc_scatter_gather_data_t
Card scatter gather data descriptor.
Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.
-
typedef struct _usdhc_scatter_gather_transfer usdhc_scatter_gather_transfer_t
usdhc scatter gather transfer.
-
typedef struct _usdhc_data usdhc_data_t
Card data descriptor.
Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.
-
typedef struct _usdhc_transfer usdhc_transfer_t
Transfer state.
-
typedef struct _usdhc_handle usdhc_handle_t
USDHC handle typedef.
-
typedef struct _usdhc_transfer_callback usdhc_transfer_callback_t
USDHC callback functions.
-
typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content)
USDHC transfer function.
-
typedef struct _usdhc_host usdhc_host_t
USDHC host descriptor.
-
USDHC_MAX_BLOCK_COUNT
Maximum block count can be set one time.
-
FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
USDHC scatter gather feature control macro.
-
USDHC_ADMA1_ADDRESS_ALIGN
The alignment size for ADDRESS filed in ADMA1’s descriptor.
-
USDHC_ADMA1_LENGTH_ALIGN
The alignment size for LENGTH field in ADMA1’s descriptor.
-
USDHC_ADMA2_ADDRESS_ALIGN
The alignment size for ADDRESS field in ADMA2’s descriptor.
-
USDHC_ADMA2_LENGTH_ALIGN
The alignment size for LENGTH filed in ADMA2’s descriptor.
-
USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT
The bit shift for ADDRESS filed in ADMA1’s descriptor.
Address/page field
Reserved
Attribute
31 12
11 6
05
04
03
02
01
00
address or data length
000000
Act2
Act1
0
Int
End
Valid
Act2
Act1
Comment
31-28
27-12
0
0
No op
Don’t care
0
1
Set data length
0000
Data Length
1
0
Transfer data
Data address
1
1
Link descriptor
Descriptor address
-
USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK
The bit mask for ADDRESS field in ADMA1’s descriptor.
-
USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT
The bit shift for LENGTH filed in ADMA1’s descriptor.
-
USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK
The mask for LENGTH field in ADMA1’s descriptor.
-
USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY
The maximum value of LENGTH filed in ADMA1’s descriptor. Since the max transfer size ADMA1 support is 65535 which is indivisible by 4096, so to make sure a large data load transfer (>64KB) continuously (require the data address be always align with 4096), software will set the maximum data length for ADMA1 to (64 - 4)KB.
-
USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT
The bit shift for LENGTH field in ADMA2’s descriptor.
Address field
Length
Reserved
Attribute
63 32
31 16
15 06
05
04
03
02
01
00
32-bit address
16-bit length
0000000000
Act2
Act1
0
Int
End
Valid
Act2
Act1
Comment
Operation
0
0
No op
Don’t care
0
1
Reserved
Read this line and go to next one
1
0
Transfer data
Transfer data with address and length set in this descriptor line
1
1
Link descriptor
Link to another descriptor
-
USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK
The bit mask for LENGTH field in ADMA2’s descriptor.
-
USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY
The maximum value of LENGTH field in ADMA2’s descriptor.
-
struct _usdhc_adma2_descriptor
- #include <fsl_usdhc.h>
Defines the ADMA2 descriptor structure.
Public Members
-
uint32_t attribute
The control and status field.
-
const uint32_t *address
The address field.
-
uint32_t attribute
-
struct _usdhc_capability
- #include <fsl_usdhc.h>
USDHC capability information.
Defines a structure to save the capability information of USDHC.
Public Members
-
uint32_t sdVersion
Support SD card/sdio version.
-
uint32_t mmcVersion
Support EMMC card version.
-
uint32_t maxBlockLength
Maximum block length united as byte.
-
uint32_t maxBlockCount
Maximum block count can be set one time.
-
uint32_t flags
Capability flags to indicate the support information(_usdhc_capability_flag).
-
uint32_t sdVersion
-
struct _usdhc_boot_config
- #include <fsl_usdhc.h>
Data structure to configure the MMC boot feature.
Public Members
-
uint32_t ackTimeoutCount
Timeout value for the boot ACK. The available range is 0 ~ 15.
-
usdhc_boot_mode_t bootMode
Boot mode selection.
-
uint32_t blockCount
Stop at block gap value of automatic mode. Available range is 0 ~ 65535.
-
size_t blockSize
Block size.
-
bool enableBootAck
Enable or disable boot ACK.
-
bool enableAutoStopAtBlockGap
Enable or disable auto stop at block gap function in boot period.
-
uint32_t ackTimeoutCount
-
struct _usdhc_config
- #include <fsl_usdhc.h>
Data structure to initialize the USDHC.
Public Members
-
uint32_t dataTimeout
Data timeout value.
-
usdhc_endian_mode_t endianMode
Endian mode.
-
uint8_t readWatermarkLevel
Watermark level for DMA read operation. Available range is 1 ~ 128.
-
uint8_t writeWatermarkLevel
Watermark level for DMA write operation. Available range is 1 ~ 128.
-
uint32_t dataTimeout
-
struct _usdhc_command
- #include <fsl_usdhc.h>
Card command descriptor.
Defines card command-related attribute.
Public Members
-
uint32_t index
Command index.
-
uint32_t argument
Command argument.
-
usdhc_card_command_type_t type
Command type.
-
usdhc_card_response_type_t responseType
Command response type.
-
uint32_t response[4U]
Response for this command.
-
uint32_t responseErrorFlags
Response error flag, which need to check the command reponse.
-
uint32_t flags
Cmd flags.
-
uint32_t index
-
struct _usdhc_adma_config
- #include <fsl_usdhc.h>
ADMA configuration.
Public Members
-
usdhc_dma_mode_t dmaMode
DMA mode.
-
uint32_t *admaTable
ADMA table address, can’t be null if transfer way is ADMA1/ADMA2.
-
uint32_t admaTableWords
ADMA table length united as words, can’t be 0 if transfer way is ADMA1/ADMA2.
-
usdhc_dma_mode_t dmaMode
-
struct _usdhc_scatter_gather_data_list
- #include <fsl_usdhc.h>
Card scatter gather data list.
Allow application register uncontinuous data buffer for data transfer.
-
struct _usdhc_scatter_gather_data
- #include <fsl_usdhc.h>
Card scatter gather data descriptor.
Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.
Public Members
-
bool enableAutoCommand12
Enable auto CMD12.
-
bool enableAutoCommand23
Enable auto CMD23.
-
bool enableIgnoreError
Enable to ignore error event to read/write all the data.
-
usdhc_transfer_direction_t dataDirection
data direction
-
uint8_t dataType
this is used to distinguish the normal/tuning/boot data.
-
size_t blockSize
Block size.
-
usdhc_scatter_gather_data_list_t sgData
scatter gather data
-
bool enableAutoCommand12
-
struct _usdhc_scatter_gather_transfer
- #include <fsl_usdhc.h>
usdhc scatter gather transfer.
Public Members
-
usdhc_scatter_gather_data_t *data
Data to transfer.
-
usdhc_command_t *command
Command to send.
-
usdhc_scatter_gather_data_t *data
-
struct _usdhc_data
- #include <fsl_usdhc.h>
Card data descriptor.
Defines a structure to contain data-related attribute. The ‘enableIgnoreError’ is used when upper card driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an error event happens. For example, bus testing procedure for MMC card.
Public Members
-
bool enableAutoCommand12
Enable auto CMD12.
-
bool enableAutoCommand23
Enable auto CMD23.
-
bool enableIgnoreError
Enable to ignore error event to read/write all the data.
-
uint8_t dataType
this is used to distinguish the normal/tuning/boot data.
-
size_t blockSize
Block size.
-
uint32_t blockCount
Block count.
-
uint32_t *rxData
Buffer to save data read.
-
const uint32_t *txData
Data buffer to write.
-
bool enableAutoCommand12
-
struct _usdhc_transfer
- #include <fsl_usdhc.h>
Transfer state.
-
struct _usdhc_transfer_callback
- #include <fsl_usdhc.h>
USDHC callback functions.
Public Members
-
void (*CardInserted)(USDHC_Type *base, void *userData)
Card inserted occurs when DAT3/CD pin is for card detect
-
void (*CardRemoved)(USDHC_Type *base, void *userData)
Card removed occurs
-
void (*SdioInterrupt)(USDHC_Type *base, void *userData)
SDIO card interrupt occurs
-
void (*BlockGap)(USDHC_Type *base, void *userData)
stopped at block gap event
-
void (*TransferComplete)(USDHC_Type *base, usdhc_handle_t *handle, status_t status, void *userData)
Transfer complete callback.
-
void (*ReTuning)(USDHC_Type *base, void *userData)
Handle the re-tuning.
-
void (*CardInserted)(USDHC_Type *base, void *userData)
-
struct _usdhc_handle
- #include <fsl_usdhc.h>
USDHC handle.
Defines the structure to save the USDHC state information and callback function.
Note
All the fields except interruptFlags and transferredWords must be allocated by the user.
Public Members
-
usdhc_data_t *volatile data
Transfer parameter. Data to transfer.
-
usdhc_command_t *volatile command
Transfer parameter. Command to send.
-
volatile uint32_t transferredWords
Transfer status. Words transferred by DATAPORT way.
-
usdhc_transfer_callback_t callback
Callback function.
-
void *userData
Parameter for transfer complete callback.
-
usdhc_data_t *volatile data
-
struct _usdhc_host
- #include <fsl_usdhc.h>
USDHC host descriptor.
Public Members
-
USDHC_Type *base
USDHC peripheral base address.
-
uint32_t sourceClock_Hz
USDHC source clock frequency united in Hz.
-
usdhc_config_t config
USDHC configuration.
-
usdhc_capability_t capability
USDHC capability information.
-
usdhc_transfer_function_t transfer
USDHC transfer function.
-
USDHC_Type *base
Xbar
-
void XBAR_Init(xbar_instance_t xbarInstance)
Initializes the XBAR modules.
This function un-gates the XBAR clock.
- Parameters:
xbarInstance – XBAR peripheral address.
-
void XBAR_Deinit(xbar_instance_t xbarInstance)
Shutdown the XBAR modules.
This function disables XBAR clock.
- Parameters:
xbarInstance – XBAR peripheral address.
-
status_t XBAR_SetSignalsConnection(xbar_input_signal_t input, xbar_output_signal_t output)
Set connection between the selected XBAR_IN[*] input and the XBAR_OUT[*] output signal.
This function connects the XBAR input to the selected XBAR output. If more than one XBAR module is available, only the inputs and outputs from the same module can be connected.
Example:
XBAR_SetSignalsConnection(kXBAR_DSC1_InputLogicLow, kXBAR_DSC1_OutputTriggerSyncIn0);
- Parameters:
input – XBAR input signal.
output – XBAR output signal.
- Return values:
kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.
-
status_t XBAR_ClearOutputStatusFlag(xbar_output_signal_t output)
Clears the edge detection status flags.
- Parameters:
output – XBAR output signal.
- Return values:
kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.
-
status_t XBAR_GetOutputStatusFlag(xbar_output_signal_t output, bool *flag)
Gets the active edge detection status.
This function gets the active edge detect status of all XBAR_OUTs. If the active edge occurs, the return value is asserted. When the interrupt or the DMA functionality is enabled for the XBAR_OUTx, this field is 1 when the interrupt or DMA request is asserted and 0 when the interrupt or DMA request has been cleared.
- Parameters:
output – XBAR output signal.
flag – get XBAR output status flag.
- Return values:
kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.
-
status_t XBAR_SetOutputSignalConfig(xbar_output_signal_t output, const xbar_control_config_t *controlConfig)
Configures the XBAR control register.
This function configures an XBAR control register. The active edge detection and the DMA/IRQ function on the corresponding XBAR output can be set.
Example:
xbar_control_config_t userConfig; userConfig.activeEdge = kXBAR_EdgeRising; userConfig.requestType = kXBAR_RequestInterruptEnable; XBAR_SetOutputSignalConfig(kXBARA_OutputDMAMUX18, &userConfig);
- Parameters:
output – XBAR output signal.
controlConfig – Pointer to structure that keeps configuration of control register.
- Return values:
kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.
-
enum _xbar_active_edge
XBAR active edge for detection.
Values:
-
enumerator kXBAR_EdgeNone
Edge detection status bit never asserts.
-
enumerator kXBAR_EdgeRising
Edge detection status bit asserts on rising edges.
-
enumerator kXBAR_EdgeFalling
Edge detection status bit asserts on falling edges.
-
enumerator kXBAR_EdgeRisingAndFalling
Edge detection status bit asserts on rising and falling edges.
-
enumerator kXBAR_EdgeNone
-
enum _xbar_request
Defines the XBAR DMA and interrupt configurations.
Values:
-
enumerator kXBAR_RequestDisable
Interrupt and DMA are disabled.
-
enumerator kXBAR_RequestDMAEnable
DMA enabled, interrupt disabled.
-
enumerator kXBAR_RequestInterruptEnable
Interrupt enabled, DMA disabled.
-
enumerator kXBAR_RequestDisable
-
typedef uint16_t xbar_reg_t
-
typedef enum _xbar_active_edge xbar_active_edge_t
XBAR active edge for detection.
-
typedef enum _xbar_request xbar_request_t
Defines the XBAR DMA and interrupt configurations.
-
typedef struct _xbar_control_config xbar_control_config_t
Defines the configuration structure of the XBAR control register.
This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers.
-
FSL_XBAR_DRIVER_VERSION
-
struct xbar_info_t
- #include <fsl_xbar.h>
Find the instance index from base address and register offset mappings.
-
struct _xbar_control_config
- #include <fsl_xbar.h>
Defines the configuration structure of the XBAR control register.
This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers.
Public Members
-
xbar_active_edge_t activeEdge
Active edge to be detected.
-
xbar_request_t requestType
Selects DMA/Interrupt request.
-
xbar_active_edge_t activeEdge
CACHE: CACHE Memory Controller
-
uint32_t XCACHE_GetInstanceByAddr(uint32_t address)
brief Returns an instance number given physical memory address.
param address The physical memory address.
- Returns:
XCACHE instance number starting from 0.
-
void XCACHE_EnableCache(XCACHE_Type *base)
Enables the cache.
- Parameters:
base – XCACHE peripheral base address.
-
void XCACHE_DisableCache(XCACHE_Type *base)
Disables the cache.
- Parameters:
base – XCACHE peripheral base address.
-
void XCACHE_InvalidateCache(XCACHE_Type *base)
Invalidates the cache.
- Parameters:
base – XCACHE peripheral base address.
-
void XCACHE_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
Invalidates cache by range.
Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address of cache.
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
-
void XCACHE_CleanCache(XCACHE_Type *base)
Cleans the cache.
- Parameters:
base – XCACHE peripheral base address.
-
void XCACHE_CleanCacheByRange(uint32_t address, uint32_t size_byte)
Cleans cache by range.
Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address of cache.
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size.
-
void XCACHE_CleanInvalidateCache(XCACHE_Type *base)
Cleans and invalidates the cache.
- Parameters:
base – XCACHE peripheral base address.
-
void XCACHE_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
Cleans and invalidate cache by range.
Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address of cache.
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size.
-
static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates instruction cache by range.
Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
-
static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
Invalidates data cache by range.
Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size.
-
static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
Clean data cache by range.
Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size.
-
static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
Cleans and Invalidates data cache by range.
Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.
- Parameters:
address – The physical address.
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size.
-
FSL_CACHE_DRIVER_VERSION
cache driver version.
-
XCACHE_LINESIZE_BYTE
cache line size.