MIMXRT1189

ACMP: Analog Comparator Driver

void ACMP_Init(CMP_Type *base, const acmp_config_t *config)

Initializes the ACMP.

The default configuration can be got by calling ACMP_GetDefaultConfig().

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to ACMP configuration structure.

void ACMP_Deinit(CMP_Type *base)

Deinitializes the ACMP.

Parameters:

• base – ACMP peripheral base address.

void ACMP_GetDefaultConfig(acmp_config_t *config)

Gets the default configuration for ACMP.

This function initializes the user configuration structure to default value. The default value are:

Example:

config->enableHighSpeed = false;
config->enableInvertOutput = false;
config->useUnfilteredOutput = false;
config->enablePinOut = false;
config->enableHysteresisBothDirections = false;
config->hysteresisMode = kACMP_hysteresisMode0;

Parameters:

• config – Pointer to ACMP configuration structure.

void ACMP_Enable(CMP_Type *base, bool enable)

Enables or disables the ACMP.

Parameters:

• base – ACMP peripheral base address.

• enable – True to enable the ACMP.

void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable)

Enables the link from CMP to DAC enable.

When this bit is set, the DAC enable/disable is controlled by the bit CMP_C0[EN] instead of CMP_C1[DACEN].

Parameters:

• base – ACMP peripheral base address.

• enable – Enable the feature or not.

void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config)

Sets the channel configuration.

Note that the plus/minus mux’s setting is only valid when the positive/negative port’s input isn’t from DAC but from channel mux.

Example:

acmp_channel_config_t configStruct = {0};
configStruct.positivePortInput = kACMP_PortInputFromDAC;
configStruct.negativePortInput = kACMP_PortInputFromMux;
configStruct.minusMuxInput = 1U;
ACMP_SetChannelConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to channel configuration structure.

void ACMP_EnableDMA(CMP_Type *base, bool enable)

Enables or disables DMA.

Parameters:

• base – ACMP peripheral base address.

• enable – True to enable DMA.

void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config)

Configures the filter.

The filter can be enabled when the filter count is bigger than 1, the filter period is greater than 0 and the sample clock is from divided bus clock or the filter is bigger than 1 and the sample clock is from external clock. Detailed usage can be got from the reference manual.

Example:

acmp_filter_config_t configStruct = {0};
configStruct.filterCount = 5U;
configStruct.filterPeriod = 200U;
configStruct.enableSample = false;
ACMP_SetFilterConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to filter configuration structure.

void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config)

Configures the internal DAC.

Example:

acmp_dac_config_t configStruct = {0};
configStruct.referenceVoltageSource = kACMP_VrefSourceVin1;
configStruct.DACValue = 20U;
configStruct.enableOutput = false;
configStruct.workMode = kACMP_DACWorkLowSpeedMode;
ACMP_SetDACConfig(CMP0, &configStruct);

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to DAC configuration structure. “NULL” is for disabling the feature.

void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask)

Enables interrupts.

Parameters:

• base – ACMP peripheral base address.

• mask – Interrupts mask. See “_acmp_interrupt_enable”.

void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask)

Disables interrupts.

Parameters:

• base – ACMP peripheral base address.

• mask – Interrupts mask. See “_acmp_interrupt_enable”.

uint32_t ACMP_GetStatusFlags(CMP_Type *base)

Gets status flags.

Parameters:

• base – ACMP peripheral base address.

Returns:

Status flags asserted mask. See “_acmp_status_flags”.

void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)

Clears status flags.

Parameters:

• base – ACMP peripheral base address.

• mask – Status flags mask. See “_acmp_status_flags”.

void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config)

Configure the discrete mode.

Configure the discrete mode when supporting 3V domain with 1.8V core.

Parameters:

• base – ACMP peripheral base address.

• config – Pointer to configuration structure. See “acmp_discrete_mode_config_t”.

void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config)

Get the default configuration for discrete mode setting.

Parameters:

• config – Pointer to configuration structure to be restored with the setting values.

FSL_ACMP_DRIVER_VERSION

ACMP driver version 2.4.0.

enum _acmp_interrupt_enable

Interrupt enable/disable mask.

Values:

enumerator kACMP_OutputRisingInterruptEnable

Enable the interrupt when comparator outputs rising.

enumerator kACMP_OutputFallingInterruptEnable

Enable the interrupt when comparator outputs falling.

enum _acmp_status_flags

Status flag mask.

Values:

enumerator kACMP_OutputRisingEventFlag

Rising-edge on compare output has occurred.

enumerator kACMP_OutputFallingEventFlag

Falling-edge on compare output has occurred.

enumerator kACMP_OutputAssertEventFlag

Return the current value of the analog comparator output.

enum _acmp_offset_mode

Comparator hard block offset control.

If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.

Values:

enumerator kACMP_OffsetLevel0

The comparator hard block output has level 0 offset internally.

enumerator kACMP_OffsetLevel1

The comparator hard block output has level 1 offset internally.

enum _acmp_hysteresis_mode

Comparator hard block hysteresis control.

See chip data sheet to get the actual hysteresis value with each level.

Values:

enumerator kACMP_HysteresisLevel0

Offset is level 0 and Hysteresis is level 0.

enumerator kACMP_HysteresisLevel1

Offset is level 0 and Hysteresis is level 1.

enumerator kACMP_HysteresisLevel2

Offset is level 0 and Hysteresis is level 2.

enumerator kACMP_HysteresisLevel3

Offset is level 0 and Hysteresis is level 3.

enum _acmp_reference_voltage_source

CMP Voltage Reference source.

Values:

enumerator kACMP_VrefSourceVin1

Vin1 is selected as resistor ladder network supply reference Vin.

enumerator kACMP_VrefSourceVin2

Vin2 is selected as resistor ladder network supply reference Vin.

enum _acmp_port_input

Port input source.

Values:

enumerator kACMP_PortInputFromDAC

Port input from the 8-bit DAC output.

enumerator kACMP_PortInputFromMux

Port input from the analog 8-1 mux.

enum _acmp_dac_work_mode

Internal DAC’s work mode.

Values:

enumerator kACMP_DACWorkLowSpeedMode

DAC is selected to work in low speed and low power mode.

enumerator kACMP_DACWorkHighSpeedMode

DAC is selected to work in high speed high power mode.

typedef enum _acmp_offset_mode acmp_offset_mode_t

Comparator hard block offset control.

If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port input in the positive direction (or negative port input crossing positive port input in the negative direction). Hysteresis still exists for positive port input crossing negative port input in the falling direction. If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.

typedef enum _acmp_hysteresis_mode acmp_hysteresis_mode_t

Comparator hard block hysteresis control.

See chip data sheet to get the actual hysteresis value with each level.

typedef enum _acmp_reference_voltage_source acmp_reference_voltage_source_t

CMP Voltage Reference source.

typedef enum _acmp_port_input acmp_port_input_t

Port input source.

typedef enum _acmp_dac_work_mode acmp_dac_work_mode_t

Internal DAC’s work mode.

typedef struct _acmp_config acmp_config_t

Configuration for ACMP.

typedef struct _acmp_channel_config acmp_channel_config_t

Configuration for channel.

The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.

typedef struct _acmp_filter_config acmp_filter_config_t

Configuration for filter.

typedef struct _acmp_dac_config acmp_dac_config_t

Configuration for DAC.

typedef struct _acmp_discrete_mode_config acmp_discrete_mode_config_t

Configuration for discrete mode.

CMP_C0_CFx_MASK

The mask of status flags cleared by writing 1.

struct _acmp_config

#include <fsl_acmp.h>

Configuration for ACMP.

Public Members

acmp_offset_mode_t offsetMode

Offset mode.

acmp_hysteresis_mode_t hysteresisMode

Hysteresis mode.

bool enableHighSpeed

Enable High Speed (HS) comparison mode.

bool enableInvertOutput

Enable inverted comparator output.

bool useUnfilteredOutput

Set compare output(COUT) to equal COUTA(true) or COUT(false).

bool enablePinOut

The comparator output is available on the associated pin.

struct _acmp_channel_config

#include <fsl_acmp.h>

Configuration for channel.

The comparator’s port can be input from channel mux or DAC. If port input is from channel mux, detailed channel number for the mux should be configured.

Public Members

acmp_port_input_t positivePortInput

Input source of the comparator’s positive port.

uint32_t plusMuxInput

Plus mux input channel(0~7).

acmp_port_input_t negativePortInput

Input source of the comparator’s negative port.

uint32_t minusMuxInput

Minus mux input channel(0~7).

struct _acmp_filter_config

#include <fsl_acmp.h>

Configuration for filter.

Public Members

uint32_t filterCount

Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.

uint32_t filterPeriod

Filter Sample Period. The divider to bus clock. Available range is 0-255.

struct _acmp_dac_config

#include <fsl_acmp.h>

Configuration for DAC.

Public Members

acmp_reference_voltage_source_t referenceVoltageSource

Supply voltage reference source.

uint32_t DACValue

Value for DAC Output Voltage. Available range is 0-255.

bool enableOutput

Enable the DAC output.

struct _acmp_discrete_mode_config

#include <fsl_acmp.h>

Configuration for discrete mode.

Public Members

bool enablePositiveChannelDiscreteMode

Positive Channel Continuous Mode Enable. By default, the continuous mode is used.

bool enableNegativeChannelDiscreteMode

Negative Channel Continuous Mode Enable. By default, the continuous mode is used.

AOI: Crossbar AND/OR/INVERT Driver

void AOI_Init(AOI_Type *base)

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

• base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

• base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Index of the event which will be set of type aoi_event_t.

• config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Event which will be configured of type aoi_event_t.

• eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION

Version 2.0.2.

enum _aoi_input_config

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero

Forces the input to logical zero.

enumerator kAOI_InputSignal

Passes the input signal.

enumerator kAOI_InvInputSignal

Inverts the input signal.

enumerator kAOI_LogicOne

Forces the input to logical one.

enum _aoi_event

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0

Event 0 index

enumerator kAOI_Event1

Event 1 index

enumerator kAOI_Event2

Event 2 index

enumerator kAOI_Event3

Event 3 index

typedef enum _aoi_input_config aoi_input_config_t

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI

AOI peripheral address

struct _aoi_event_config

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC

Product term 0 input A

aoi_input_config_t PT0BC

Product term 0 input B

aoi_input_config_t PT0CC

Product term 0 input C

aoi_input_config_t PT0DC

Product term 0 input D

aoi_input_config_t PT1AC

Product term 1 input A

aoi_input_config_t PT1BC

Product term 1 input B

aoi_input_config_t PT1CC

Product term 1 input C

aoi_input_config_t PT1DC

Product term 1 input D

aoi_input_config_t PT2AC

Product term 2 input A

aoi_input_config_t PT2BC

Product term 2 input B

aoi_input_config_t PT2CC

Product term 2 input C

aoi_input_config_t PT2DC

Product term 2 input D

aoi_input_config_t PT3AC

Product term 3 input A

aoi_input_config_t PT3BC

Product term 3 input B

aoi_input_config_t PT3CC

Product term 3 input C

aoi_input_config_t PT3DC

Product term 3 input D

ASRC: Asynchronous sample rate converter

ASRC Driver

uint32_t ASRC_GetInstance(ASRC_Type *base)

Get instance number of the ASRC peripheral.

Parameters:

• base – ASRC base pointer.

void ASRC_Init(ASRC_Type *base, uint32_t asrcPeripheralClock_Hz)

brief Initializes the asrc peripheral.

This API gates the asrc clock. The asrc module can’t operate unless ASRC_Init is called to enable the clock.

param base asrc base pointer. param asrcPeripheralClock_Hz peripheral clock of ASRC.

void ASRC_Deinit(ASRC_Type *base)

De-initializes the ASRC peripheral.

This API gates the ASRC clock and disable ASRC module. The ASRC module can’t operate unless ASRC_Init

Parameters:

• base – ASRC base pointer.

void ASRC_SoftwareReset(ASRC_Type *base)

Do software reset .

This software reset bit is self-clear bit, it will generate a software reset signal inside ASRC. After 9 cycles of the ASRC processing clock, this reset process will stop and this bit will cleared automatically.

Parameters:

• base – ASRC base pointer

status_t ASRC_SetChannelPairConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure channel pair.

Parameters:

• base – ASRC base pointer.

• channelPair – index of channel pair, reference _asrc_channel_pair.

• config – ASRC channel pair configuration pointer.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

uint32_t ASRC_GetOutSamplesSize(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)

Get output sample buffer size.

Note

This API is depends on the ASRC output configuration, should be called after the ASRC_SetChannelPairConfig.

Parameters:

• base – asrc base pointer.

• channelPair – ASRC channel pair number.

• inSampleRate – input sample rate.

• outSampleRate – output sample rate.

• inSamplesize – input sampleS size.

Return values:

output – buffer size in byte.

uint32_t ASRC_MapSamplesWidth(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *inWidth, uint32_t *outWidth)

Map register sample width to real sample width.

Note

This API is depends on the ASRC configuration, should be called after the ASRC_SetChannelPairConfig.

Parameters:

• base – asrc base pointer.

• channelPair – asrc channel pair index.

• inWidth – ASRC channel pair number.

• outWidth – input sample rate.

Return values:

input – sample mask value.

uint32_t ASRC_GetRemainFifoSamples(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t *buffer, uint32_t outSampleWidth, uint32_t remainSamples)

Get left samples in fifo.

Parameters:

• base – asrc base pointer.

• channelPair – ASRC channel pair number.

• buffer – input sample numbers.

• outSampleWidth – output sample width.

• remainSamples – output sample rate.

Return values:

remain – samples number.

static inline void ASRC_ModuleEnable(ASRC_Type *base, bool enable)

ASRC module enable.

Parameters:

• base – ASRC base pointer.

• enable – true is enable, false is disable

static inline void ASRC_ChannelPairEnable(ASRC_Type *base, asrc_channel_pair_t channelPair, bool enable)

ASRC enable channel pair.

Parameters:

• base – ASRC base pointer.

• channelPair – channel pair mask value, reference _asrc_channel_pair_mask.

• enable – true is enable, false is disable.

static inline void ASRC_EnableInterrupt(ASRC_Type *base, uint32_t mask)

ASRC interrupt enable This function enable the ASRC interrupt with the provided mask.

Parameters:

• base – ASRC peripheral base address.

• mask – The interrupts to enable. Logical OR of _asrc_interrupt_mask.

static inline void ASRC_DisableInterrupt(ASRC_Type *base, uint32_t mask)

ASRC interrupt disable This function disable the ASRC interrupt with the provided mask.

Parameters:

• base – ASRC peripheral base address.

• mask – The interrupts to disable. Logical OR of _asrc_interrupt_mask.

static inline uint32_t ASRC_GetStatus(ASRC_Type *base)

Gets the ASRC status flag state.

Parameters:

• base – ASRC base pointer

Returns:

ASRC Tx status flag value. Use the Status Mask to get the status value needed.

static inline bool ASRC_GetChannelPairInitialStatus(ASRC_Type *base, asrc_channel_pair_t channel)

Gets the ASRC channel pair initialization state.

Parameters:

• base – ASRC base pointer

• channel – ASRC channel pair.

Returns:

ASRC Tx status flag value. Use the Status Mask to get the status value needed.

static inline uint32_t ASRC_GetChannelPairFifoStatus(ASRC_Type *base, asrc_channel_pair_t channelPair)

Gets the ASRC channel A fifo a status flag state.

Parameters:

• base – ASRC base pointer

• channelPair – ASRC channel pair.

Returns:

ASRC channel pair a fifo status flag value. Use the Status Mask to get the status value needed.

static inline void ASRC_ChannelPairWriteData(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t data)

Writes data into ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

• data – Data needs to be written.

static inline uint32_t ASRC_ChannelPairReadData(ASRC_Type *base, asrc_channel_pair_t channelPair)

Read data from ASRC channel pair FIFO. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

Return values:

value – read from fifo.

static inline uint32_t ASRC_GetInputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)

Get input data fifo address. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

static inline uint32_t ASRC_GetOutputDataRegisterAddress(ASRC_Type *base, asrc_channel_pair_t channelPair)

Get output data fifo address. Note: ASRC fifo width is 24bit.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

status_t ASRC_SetIdealRatioConfig(ASRC_Type *base, asrc_channel_pair_t channelPair, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure ideal ratio. The ideal ratio should be used when input clock source is not avalible.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

status_t ASRC_TransferSetChannelPairConfig(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_config_t *config, uint32_t inputSampleRate, uint32_t outputSampleRate)

ASRC configure channel pair.

Parameters:

• base – ASRC base pointer.

• handle – ASRC transactional handle pointer.

• config – ASRC channel pair configuration pointer.

• inputSampleRate – input audio data sample rate.

• outputSampleRate – output audio data sample rate.

void ASRC_TransferCreateHandle(ASRC_Type *base, asrc_handle_t *handle, asrc_channel_pair_t channelPair, asrc_transfer_callback_t inCallback, asrc_transfer_callback_t outCallback, void *userData)

Initializes the ASRC handle.

This function initializes the handle for the ASRC transactional APIs. Call this function once to get the handle initialized.

Parameters:

• base – ASRC base pointer

• handle – ASRC handle pointer.

• channelPair – ASRC channel pair.

• inCallback – Pointer to the user callback function.

• outCallback – Pointer to the user callback function.

• userData – User parameter passed to the callback function

status_t ASRC_TransferNonBlocking(ASRC_Type *base, asrc_handle_t *handle, asrc_transfer_t *xfer)

Performs an interrupt non-blocking convert on asrc.

Note

This API returns immediately after the transfer initiates, application should check the wait and check the callback status.

Parameters:

• base – asrc base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

• xfer – Pointer to the ASRC_transfer_t structure.

Return values:

• kStatus_Success – Successfully started the data receive.

• kStatus_ASRCBusy – Previous receive still not finished.

status_t ASRC_TransferBlocking(ASRC_Type *base, asrc_channel_pair_t channelPair, asrc_transfer_t *xfer)

Performs an blocking convert on asrc.

Note

This API returns immediately after the convert finished.

Parameters:

• base – asrc base pointer.

• channelPair – channel pair index.

• xfer – Pointer to the ASRC_transfer_t structure.

Return values:

kStatus_Success – Successfully started the data receive.

status_t ASRC_TransferGetConvertedCount(ASRC_Type *base, asrc_handle_t *handle, size_t *count)

Get converted byte count.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

• count – Bytes count sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_ASRCIdle – There is not a non-blocking transaction currently in progress.

void ASRC_TransferAbortConvert(ASRC_Type *base, asrc_handle_t *handle)

Aborts the current convert.

Note

This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure which stores the transfer state.

void ASRC_TransferTerminateConvert(ASRC_Type *base, asrc_handle_t *handle)

Terminate all ASRC convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortConvert.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferHandleIRQ(ASRC_Type *base, asrc_handle_t *handle)

ASRC convert interrupt handler.

Parameters:

• base – ASRC base pointer.

• handle – Pointer to the asrc_handle_t structure.

FSL_ASRC_DRIVER_VERSION

Version 2.1.3

ASRC return status .

Values:

enumerator kStatus_ASRCIdle

ASRC is idle.

enumerator kStatus_ASRCInIdle

ASRC in is idle.

enumerator kStatus_ASRCOutIdle

ASRC out is idle.

enumerator kStatus_ASRCBusy

ASRC is busy.

enumerator kStatus_ASRCInvalidArgument

ASRC invalid argument.

enumerator kStatus_ASRCClockConfigureFailed

ASRC clock configure failed

enumerator kStatus_ASRCChannelPairConfigureFailed

ASRC clock configure failed

enumerator kStatus_ASRCConvertError

ASRC clock configure failed

enumerator kStatus_ASRCNotSupport

ASRC not support

enumerator kStatus_ASRCQueueFull

ASRC queue is full

enumerator kStatus_ASRCOutQueueIdle

ASRC out queue is idle

enumerator kStatus_ASRCInQueueIdle

ASRC in queue is idle

enum _asrc_channel_pair

ASRC channel pair mask.

Values:

enumerator kASRC_ChannelPairA

channel pair A value

enumerator kASRC_ChannelPairB

channel pair B value

enumerator kASRC_ChannelPairC

channel pair C value

ASRC support sample rate .

Values:

enumerator kASRC_SampleRate_8000HZ

asrc sample rate 8KHZ

enumerator kASRC_SampleRate_11025HZ

asrc sample rate 11.025KHZ

enumerator kASRC_SampleRate_12000HZ

asrc sample rate 12KHZ

enumerator kASRC_SampleRate_16000HZ

asrc sample rate 16KHZ

enumerator kASRC_SampleRate_22050HZ

asrc sample rate 22.05KHZ

enumerator kASRC_SampleRate_24000HZ

asrc sample rate 24KHZ

enumerator kASRC_SampleRate_30000HZ

asrc sample rate 30KHZ

enumerator kASRC_SampleRate_32000HZ

asrc sample rate 32KHZ

enumerator kASRC_SampleRate_44100HZ

asrc sample rate 44.1KHZ

enumerator kASRC_SampleRate_48000HZ

asrc sample rate 48KHZ

enumerator kASRC_SampleRate_64000HZ

asrc sample rate 64KHZ

enumerator kASRC_SampleRate_88200HZ

asrc sample rate 88.2KHZ

enumerator kASRC_SampleRate_96000HZ

asrc sample rate 96KHZ

enumerator kASRC_SampleRate_128000HZ

asrc sample rate 128KHZ

enumerator kASRC_SampleRate_176400HZ

asrc sample rate 176.4KHZ

enumerator kASRC_SampleRate_192000HZ

asrc sample rate 192KHZ

The ASRC interrupt enable flag .

Values:

enumerator kASRC_FPInWaitStateInterruptEnable

FP in wait state mask

enumerator kASRC_OverLoadInterruptMask

overload interrupt mask

enumerator kASRC_DataOutputCInterruptMask

data output c interrupt mask

enumerator kASRC_DataOutputBInterruptMask

data output b interrupt mask

enumerator kASRC_DataOutputAInterruptMask

data output a interrupt mask

enumerator kASRC_DataInputCInterruptMask

data input c interrupt mask

enumerator kASRC_DataInputBInterruptMask

data input b interrupt mask

enumerator kASRC_DataInputAInterruptMask

data input a interrupt mask

The ASRC interrupt status .

Values:

enumerator kASRC_StatusDSLCounterReady

DSL counter

enumerator kASRC_StatusTaskQueueOverLoad

task queue overload

enumerator kASRC_StatusPairCOutputOverLoad

pair c output overload

enumerator kASRC_StatusPairBOutputOverLoad

pair b output overload

enumerator kASRC_StatusPairAOutputOverLoad

pair a output overload

enumerator kASRC_StatusPairCInputOverLoad

pair c input overload

enumerator kASRC_StatusPairBInputOverLoad

pair b input overload

enumerator kASRC_StatusPairAInputOverLoad

pair a input overload

enumerator kASRC_StatusPairCOutputOverflow

pair c output overflow

enumerator kASRC_StatusPairBOutputOverflow

pair b output overflow

enumerator kASRC_StatusPairAOutputOverflow

pair a output overflow

enumerator kASRC_StatusPairCInputUnderflow

pair c input underflow

enumerator kASRC_StatusPairBInputUnderflow

pair b input under flow

enumerator kASRC_StatusPairAInputUnderflow

pair a input underflow

enumerator kASRC_StatusFPInWaitState

FP in wait state

enumerator kASRC_StatusOverloadError

overload error

enumerator kASRC_StatusInputError

input error status

enumerator kASRC_StatusOutputError

output error status

enumerator kASRC_StatusPairCOutputReady

pair c output ready

enumerator kASRC_StatusPairBOutputReady

pair b output ready

enumerator kASRC_StatusPairAOutputReady

pair a output ready

enumerator kASRC_StatusPairCInputReady

pair c input ready

enumerator kASRC_StatusPairBInputReady

pair b input ready

enumerator kASRC_StatusPairAInputReady

pair a input ready

enumerator kASRC_StatusPairAInterrupt

pair A interrupt

enumerator kASRC_StatusPairBInterrupt

pair B interrupt

enumerator kASRC_StatusPairCInterrupt

pair C interrupt

ASRC channel pair status .

Values:

enumerator kASRC_OutputFifoNearFull

channel pair output fifo near full

enumerator kASRC_InputFifoNearEmpty

channel pair input fifo near empty

enum _asrc_ratio

ASRC ideal ratio.

Values:

enumerator kASRC_RatioNotUsed

ideal ratio not used

enumerator kASRC_RatioUseInternalMeasured

ideal ratio use internal measure ratio, can be used for real time streaming audio

enumerator kASRC_RatioUseIdealRatio

ideal ratio use manual configure ratio, can be used for the non-real time streaming audio

enum _asrc_audio_channel

Number of channels in audio data.

Values:

enumerator kASRC_ChannelsNumber1

channel number is 1

enumerator kASRC_ChannelsNumber2

channel number is 2

enumerator kASRC_ChannelsNumber3

channel number is 3

enumerator kASRC_ChannelsNumber4

channel number is 4

enumerator kASRC_ChannelsNumber5

channel number is 5

enumerator kASRC_ChannelsNumber6

channel number is 6

enumerator kASRC_ChannelsNumber7

channel number is 7

enumerator kASRC_ChannelsNumber8

channel number is 8

enumerator kASRC_ChannelsNumber9

channel number is 9

enumerator kASRC_ChannelsNumber10

channel number is 10

enum _asrc_data_width

data width

Values:

enumerator kASRC_DataWidth24Bit

data width 24bit

enumerator kASRC_DataWidth16Bit

data width 16bit

enumerator kASRC_DataWidth8Bit

data width 8bit

enum _asrc_data_align

data alignment

Values:

enumerator kASRC_DataAlignMSB

data alignment MSB

enumerator kASRC_DataAlignLSB

data alignment LSB

enum _asrc_sign_extension

sign extension

Values:

enumerator kASRC_NoSignExtension

no sign extension

enumerator kASRC_SignExtension

sign extension

typedef enum _asrc_channel_pair asrc_channel_pair_t

ASRC channel pair mask.

typedef enum _asrc_ratio asrc_ratio_t

ASRC ideal ratio.

typedef enum _asrc_audio_channel asrc_audio_channel_t

Number of channels in audio data.

typedef enum _asrc_data_width asrc_data_width_t

data width

typedef enum _asrc_data_align asrc_data_align_t

data alignment

typedef enum _asrc_sign_extension asrc_sign_extension_t

sign extension

typedef struct _asrc_channel_pair_config asrc_channel_pair_config_t

asrc channel pair configuation

typedef struct _asrc_transfer asrc_transfer_t

SAI transfer structure.

typedef struct _asrc_handle asrc_handle_t

asrc handler

typedef void (*asrc_transfer_callback_t)(ASRC_Type *base, asrc_handle_t *handle, status_t status, void *userData)

ASRC transfer callback prototype.

typedef struct _asrc_in_handle asrc_in_handle_t

asrc in handler

typedef struct _asrc_out_handle asrc_out_handle_t

output handler

ASRC_XFER_QUEUE_SIZE

ASRC transfer queue size, user can refine it according to use case.

FSL_ASRC_CHANNEL_PAIR_COUNT

ASRC channel pair count.

FSL_ASRC_CHANNEL_PAIR_FIFO_DEPTH

ASRC FIFO depth.

ASRC_ASRCTR_AT_MASK(index)

ASRC register access macro.

ASRC_ASRCTR_RATIO_MASK(index)

ASRC_ASRCTR_RATIO(ratio, index)

ASRC_ASRIER_INPUT_INTERRUPT_MASK(index)

ASRC_ASRIER_OUTPUTPUT_INTERRUPT_MASK(index)

ASRC_ASRCNCR_CHANNEL_COUNTER_MASK(index)

ASRC_ASRCNCR_CHANNEL_COUNTER(counter, index)

ASRC_ASRCFG_PRE_MODE_MASK(index)

ASRC_ASRCFG_PRE_MODE(mode, index)

ASRC_ASRCFG_POST_MODE_MASK(index)

ASRC_ASRCFG_POST_MODE(mode, index)

ASRC_ASRCFG_INIT_DONE_MASK(index)

ASRC_ASRCSR_INPUT_CLOCK_SOURCE_MASK(index)

ASRC_ASRCSR_INPUT_CLOCK_SOURCE(source, index)

ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE_MASK(index)

ASRC_ASRCSR_OUTPUT_CLOCK_SOURCE(source, index)

ASRC_ASRCDR_INPUT_PRESCALER_MASK(index)

ASRC_ASRCDR_INPUT_PRESCALER(prescaler, index)

ASRC_ASRCDR_INPUT_DIVIDER_MASK(index)

ASRC_ASRCDR_INPUT_DIVIDER(divider, index)

ASRC_ASRCDR_OUTPUT_PRESCALER_MASK(index)

ASRC_ASRCDR_OUTPUT_PRESCALER(prescaler, index)

ASRC_ASRCDR_OUTPUT_DIVIDER_MASK(index)

ASRC_ASRCDR_OUTPUT_DIVIDER(divider, index)

ASCR_ASRCDR_OUTPUT_CLOCK_DIVIDER_PRESCALER(value, index)

ASCR_ASRCDR_INPUT_CLOCK_DIVIDER_PRESCALER(value, index)

ASRC_IDEAL_RATIO_HIGH(base, index)

ASRC_IDEAL_RATIO_LOW(base, index)

ASRC_ASRMCR(base, index)

ASRC_ASRMCR1(base, index)

ASRC_ASRDI(base, index)

ASRC_ASRDO(base, index)

ASRC_ASRDI_ADDR(base, index)

ASRC_ASRDO_ADDR(base, index)

ASRC_ASRFST_ADDR(base, index)

ASRC_GET_CHANNEL_COUNTER(base, index)

struct _asrc_channel_pair_config

#include <fsl_asrc.h>

asrc channel pair configuation

Public Members

asrc_audio_channel_t audioDataChannels

audio data channel numbers

asrc_clock_source_t inClockSource

input clock source, reference the clock source definition in SOC header file

uint32_t inSourceClock_Hz

input source clock frequency

asrc_clock_source_t outClockSource

output clock source, reference the clock source definition in SOC header file

uint32_t outSourceClock_Hz

output source clock frequency

asrc_ratio_t sampleRateRatio

sample rate ratio type

asrc_data_width_t inDataWidth

input data width

asrc_data_align_t inDataAlign

input data alignment

asrc_data_width_t outDataWidth

output data width

asrc_data_align_t outDataAlign

output data alignment

asrc_sign_extension_t outSignExtension

output extension

uint8_t outFifoThreshold

output fifo threshold

uint8_t inFifoThreshold

input fifo threshold

bool bufStallWhenFifoEmptyFull

stall Pair A conversion in case of Buffer near empty full condition

struct _asrc_transfer

#include <fsl_asrc.h>

SAI transfer structure.

Public Members

void *inData

Data address to convert.

size_t inDataSize

input data size.

void *outData

Data address to store converted data

size_t outDataSize

output data size.

struct _asrc_in_handle

#include <fsl_asrc.h>

asrc in handler

Public Members

asrc_transfer_callback_t callback

Callback function called at convert complete

uint32_t sampleWidth

data width

uint32_t sampleMask

data mask

uint32_t fifoThreshold

fifo threshold

uint8_t *asrcQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSamples[(4U)]

Data bytes need to convert

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

struct _asrc_out_handle

#include <fsl_asrc.h>

output handler

Public Members

asrc_transfer_callback_t callback

Callback function called at convert complete

uint32_t sampleWidth

data width

uint32_t fifoThreshold

fifo threshold

uint8_t *asrcQueue[(4U)]

Transfer queue storing queued transfer

size_t transferSamples[(4U)]

Data bytes need to convert

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

struct _asrc_handle

#include <fsl_asrc.h>

ASRC handle structure.

Public Members

ASRC_Type *base

base address

uint32_t state

Transfer status

void *userData

Callback parameter passed to callback function

asrc_audio_channel_t audioDataChannels

audio channel number

asrc_channel_pair_t channelPair

channel pair mask

asrc_in_handle_t in

asrc input handler

asrc_out_handle_t out

asrc output handler

ASRC EDMA Driver

void ASRC_TransferInCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *inDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)

Initializes the ASRC IN eDMA handle.

This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair

• handle – ASRC eDMA handle pointer.

• callback – Pointer to user callback function.

• inDmaHandle – DMA handler for ASRC in.

• periphConfig – peripheral configuration.

• userData – User parameter passed to the callback function.

void ASRC_TransferOutCreateHandleEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_t channelPair, asrc_edma_callback_t callback, edma_handle_t *outDmaHandle, const asrc_p2p_edma_config_t *periphConfig, void *userData)

Initializes the ASRC OUT eDMA handle.

This function initializes the ASRC DMA handle, which can be used for other ASRC transactional APIs. Usually, for a specified ASRC channel pair, call this API once to get the initialized handle.

Parameters:

• base – ASRC base pointer.

• channelPair – ASRC channel pair

• handle – ASRC eDMA handle pointer.

• callback – Pointer to user callback function.

• outDmaHandle – DMA handler for ASRC out.

• periphConfig – peripheral configuration.

• userData – User parameter passed to the callback function.

status_t ASRC_TransferSetChannelPairConfigEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_channel_pair_config_t *asrcConfig, uint32_t inSampleRate, uint32_t outSampleRate)

Configures the ASRC P2P channel pair.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

• asrcConfig – asrc configurations.

• inSampleRate – ASRC input sample rate.

• outSampleRate – ASRC output sample rate.

uint32_t ASRC_GetOutSamplesSizeEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, uint32_t inSampleRate, uint32_t outSampleRate, uint32_t inSamplesize)

Get output sample buffer size can be transferred by edma.

Note

This API is depends on the ASRC output configuration, should be called after the ASRC_TransferSetChannelPairConfigEDMA.

Parameters:

• base – asrc base pointer.

• handle – ASRC channel pair edma handle.

• inSampleRate – input sample rate.

• outSampleRate – output sample rate.

• inSamplesize – input sampleS size.

Return values:

output – buffer size in byte.

status_t ASRC_TransferEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_transfer_t *xfer)

Performs a non-blocking ASRC m2m convert using EDMA.

Note

This interface returns immediately after the transfer initiates.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

• xfer – Pointer to the DMA transfer structure.

Return values:

• kStatus_Success – Start a ASRC eDMA send successfully.

• kStatus_InvalidArgument – The input argument is invalid.

• kStatus_ASRCQueueFull – ASRC EDMA driver queue is full.

void ASRC_TransferInAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Aborts a ASRC IN transfer using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferOutAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Aborts a ASRC OUT transfer using eDMA.

This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call ASRC_TransferTerminalP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferInTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Terminate In ASRC Convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

void ASRC_TransferOutTerminalEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)

Terminate Out ASRC Convert.

This function will clear all transfer slots buffered in the asrc queue. If users only want to abort the current transfer slot, please call ASRC_TransferAbortPP2PEDMA.

Parameters:

• base – ASRC base pointer.

• handle – ASRC eDMA handle pointer.

FSL_ASRC_EDMA_DRIVER_VERSION

Version 2.2.0

typedef struct _asrc_edma_handle asrc_edma_handle_t

typedef void (*asrc_edma_callback_t)(ASRC_Type *base, asrc_edma_handle_t *handle, status_t status, void *userData)

ASRC eDMA transfer callback function for finish and error.

typedef void (*asrc_start_peripheral_t)(bool start)

ASRC trigger peripheral function pointer.

typedef struct _asrc_p2p_edma_config asrc_p2p_edma_config_t

destination peripheral configuration

typedef struct _asrc_in_edma_handle asrc_in_edma_handle_t

@ brief asrc in edma handler

typedef struct _asrc_out_edma_handle asrc_out_edma_handle_t

@ brief asrc out edma handler

ASRC_XFER_IN_QUEUE_SIZE

ASRC IN edma QUEUE size.

<

ASRC_XFER_OUT_QUEUE_SIZE

struct _asrc_p2p_edma_config

#include <fsl_asrc_edma.h>

destination peripheral configuration

Public Members

asrc_start_peripheral_t startPeripheral

trigger peripheral start

struct _asrc_in_edma_handle

#include <fsl_asrc_edma.h>

@ brief asrc in edma handler

Public Members

edma_handle_t *inDmaHandle

DMA handler for ASRC in

uint8_t tcd[(4U + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA send.

uint32_t sampleWidth

input data width

uint32_t fifoThreshold

ASRC input fifo threshold

uint32_t *asrcQueue[4U]

Transfer queue storing queued transfer.

size_t transferSize[4U]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint32_t state

Internal state for ASRC eDMA transfer

const asrc_p2p_edma_config_t *peripheralConfig

peripheral configuration pointer

struct _asrc_out_edma_handle

#include <fsl_asrc_edma.h>

@ brief asrc out edma handler

Public Members

edma_handle_t *outDmaHandle

DMA handler for ASRC out

uint8_t tcd[(((4U) * 2U) + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA send.

uint32_t sampleWidth

output data width

uint32_t fifoThreshold

ASRC output fifo threshold

uint32_t *asrcQueue[((4U) * 2U)]

Transfer queue storing queued transfer.

size_t transferSize[((4U) * 2U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

uint32_t state

Internal state for ASRC eDMA transfer

const asrc_p2p_edma_config_t *peripheralConfig

peripheral configuration pointer

struct _asrc_edma_handle

#include <fsl_asrc_edma.h>

ASRC DMA transfer handle.

Public Members

asrc_in_edma_handle_t in

asrc in handler

asrc_out_edma_handle_t out

asrc out handler

asrc_channel_pair_t channelPair

channel pair

void *userData

User callback parameter

asrc_edma_callback_t callback

Callback for users while transfer finish or error occurs

Battery-Backed Non-Secure Module

void BBNSM_Init(BBNSM_Type *base)

Init the BBNSM section.

Parameters:

• base – BBNSM peripheral base address

void BBNSM_Deinit(BBNSM_Type *base)

Deinit the BBNSM section.

Parameters:

• base – BBNSM peripheral base address

FSL_BBNSM_DRIVER_VERSION

Version 2.0.0

enum _bbnsm_interrupts

List of BBNSM interrupts.

Values:

enumerator kBBNSM_RTC_AlarmInterrupt

RTC time alarm interrupt

enumerator kBBNSM_RTC_RolloverInterrupt

RTC rollover interrupt

enum _bbnsm_status_flags

List of BBNSM flags.

Values:

enumerator kBBNSM_RTC_AlarmInterruptFlag

RTC time alarm interrupt flag

enumerator kBBNSM_RTC_RolloverInterruptFlag

RTC rollover interrupt flag

enumerator kBBNSM_PWR_ON_InterruptFlag

power on interrupt flag

enumerator kBBNSM_PWR_OFF_InterruptFlag

power off interrupt flag

enumerator kBBNSM_EMG_OFF_InterruptFlag

emergency power off interrupt flag

typedef enum _bbnsm_interrupts bbnsm_interrupts_t

List of BBNSM interrupts.

typedef enum _bbnsm_status_flags bbnsm_status_flags_t

List of BBNSM flags.

typedef struct _bbnsm_rtc_config bbnsm_rtc_config_t

BBNSM config structure.

This structure holds the configuration settings for the BBNSM peripheral. To initialize this structure to reasonable defaults, call the BBNSM_RTC_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

void BBNSM_RTC_Init(BBNSM_Type *base, const bbnsm_rtc_config_t *config)

Ungates the BBNSM clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the BBNSM driver.

Parameters:

• base – BBNSM peripheral base address

• config – Pointer to the user’s BBNSM rtc configuration structure.

void BBNSM_RTC_Deinit(BBNSM_Type *base)

Stops the RTC timer.

Parameters:

• base – BBNSM peripheral base address

void BBNSM_RTC_GetDefaultConfig(bbnsm_rtc_config_t *config)

Fills in the BBNSM RTC config struct with the default settings.

The default values are as follows.

config->rtccalenable = false;
config->rtccalvalue = 0U;

Parameters:

• config – Pointer to the user’s BBNSM configuration structure.

status_t BBNSM_RTC_SetAlarm(BBNSM_Type *base, uint32_t alarmSeconds)

Sets the BBNSM RTC alarm time.

The function sets the RTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error. Please note, that RTC alarm has limited resolution because only 32 most significant bits of RTC counter are compared to RTC Alarm register. If the alarm time is beyond RTC resolution, the function does not set the alarm and returns an error.

Parameters:

• base – BBNSM peripheral base address

• alarmSeconds –

Returns:

kStatus_Success: success in setting the BBNSM RTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed or is beyond resolution

uint32_t BBNSM_RTC_GetAlarm(BBNSM_Type *base)

Returns the BBNSM RTC alarm time.

Parameters:

• base – BBNSM peripheral base address

struct _bbnsm_rtc_config

#include <fsl_bbnsm.h>

BBNSM config structure.

This structure holds the configuration settings for the BBNSM peripheral. To initialize this structure to reasonable defaults, call the BBNSM_RTC_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

bool rtcCalEnable

true: RTC calibration mechanism is enabled; false: No calibration is used

uint32_t rtcCalValue

Defines signed calibration value for RTC; This is a 5-bit 2’s complement value, range from -16 to +15

CACHE: ARMV7-M7 CACHE Memory Controller

static inline void L1CACHE_EnableICache(void)

Enables cortex-m7 L1 instruction cache.

static inline void L1CACHE_DisableICache(void)

Disables cortex-m7 L1 instruction cache.

static inline void L1CACHE_InvalidateICache(void)

Invalidate cortex-m7 L1 instruction cache.

void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)

Invalidate cortex-m7 L1 instruction cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

static inline void L1CACHE_EnableDCache(void)

Enables cortex-m7 L1 data cache.

static inline void L1CACHE_DisableDCache(void)

Disables cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCache(void)

Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_CleanDCache(void)

Cleans cortex-m7 L1 data cache.

static inline void L1CACHE_CleanInvalidateDCache(void)

Cleans and Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be invalidated.

• size_byte – The memory size.

static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be cleaned.

• size_byte – The memory size.

static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The start address of the memory to be clean and invalidated.

• size_byte – The memory size.

void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be invalidated.

void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be cleaned.

void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

• address – The physical address.

• size_byte – size of the memory to be cleaned and invalidated.

FSL_CACHE_DRIVER_VERSION

cache driver version 2.0.4.

Clock Driver

enum _clock_lpcg

Clock LPCG index.

Values:

enumerator kCLOCK_M7

Clock LPCG M7

enumerator kCLOCK_M33

Clock LPCG M33

enumerator kCLOCK_Edgelock

Clock LPCG Edgelock

enumerator kCLOCK_Sim_Aon

Clock LPCG Sim_Aon

enumerator kCLOCK_Sim_Wakeup

Clock LPCG Sim_Wakeup

enumerator kCLOCK_Sim_Mega

Clock LPCG Sim_Mega

enumerator kCLOCK_Sim_R

Clock LPCG Sim_R

enumerator kCLOCK_Anadig

Clock LPCG Anadig

enumerator kCLOCK_Dcdc

Clock LPCG Dcdc

enumerator kCLOCK_Src

Clock LPCG Src

enumerator kCLOCK_Ccm

Clock LPCG Ccm

enumerator kCLOCK_Gpc

Clock LPCG Gpc

enumerator kCLOCK_Adc1

Clock LPCG Adc1

enumerator kCLOCK_Adc2

Clock LPCG Adc2

enumerator kCLOCK_Dac

Clock LPCG Dac

enumerator kCLOCK_Acmp1

Clock LPCG Acmp1

enumerator kCLOCK_Acmp2

Clock LPCG Acmp2

enumerator kCLOCK_Acmp3

Clock LPCG Acmp3

enumerator kCLOCK_Acmp4

Clock LPCG Acmp4

enumerator kCLOCK_Wdog1

Clock LPCG Wdog1

enumerator kCLOCK_Wdog2

Clock LPCG Wdog2

enumerator kCLOCK_Wdog3

Clock LPCG Wdog3

enumerator kCLOCK_Wdog4

Clock LPCG Wdog4

enumerator kCLOCK_Wdog5

Clock LPCG Wdog5

enumerator kCLOCK_Ewm0

Clock LPCG Ewm0

enumerator kCLOCK_Sema1

Clock LPCG Sema1

enumerator kCLOCK_Sema2

Clock LPCG Sema2

enumerator kCLOCK_Mu_A

Clock LPCG Mu_A

enumerator kCLOCK_Mu_B

Clock LPCG Mu_B

enumerator kCLOCK_Edma3

Clock LPCG Edma3

enumerator kCLOCK_Edma4

Clock LPCG Edma4

enumerator kCLOCK_Romcp

Clock LPCG Romcp

enumerator kCLOCK_Ocram1

Clock LPCG Ocram1

enumerator kCLOCK_Ocram2

Clock LPCG Ocram2

enumerator kCLOCK_Flexspi1

Clock LPCG Flexspi1

enumerator kCLOCK_Flexspi2

Clock LPCG Flexspi2

enumerator kCLOCK_Flexspi_Slv

Clock LPCG Flexspi_Slv

enumerator kCLOCK_Trdc

Clock LPCG Trdc

enumerator kCLOCK_Ocotp

Clock LPCG Ocotp

enumerator kCLOCK_Semc

Clock LPCG Semc

enumerator kCLOCK_Iee

Clock LPCG Iee

enumerator kCLOCK_Cstrace

Clock LPCG Cstrace

enumerator kCLOCK_Csswo

Clock LPCG Csswo

enumerator kCLOCK_Iomuxc1

Clock LPCG Iomuxc1

enumerator kCLOCK_Iomuxc2

Clock LPCG Iomuxc2

enumerator kCLOCK_Gpio1

Clock LPCG Gpio1

enumerator kCLOCK_Gpio2

Clock LPCG Gpio2

enumerator kCLOCK_Gpio3

Clock LPCG Gpio3

enumerator kCLOCK_Gpio4

Clock LPCG Gpio4

enumerator kCLOCK_Gpio5

Clock LPCG Gpio5

enumerator kCLOCK_Gpio6

Clock LPCG Gpio6

enumerator kCLOCK_Flexio1

Clock LPCG Flexio1

enumerator kCLOCK_Flexio2

Clock LPCG Flexio2

enumerator kCLOCK_Lpit1

Clock LPCG Lpit1

enumerator kCLOCK_Lpit2

Clock LPCG Lpit2

enumerator kCLOCK_Lpit3

Clock LPCG Lpit3

enumerator kCLOCK_Lptmr1

Clock LPCG Lptmr1

enumerator kCLOCK_Lptmr2

Clock LPCG Lptmr2

enumerator kCLOCK_Lptmr3

Clock LPCG Lptmr3

enumerator kCLOCK_Tpm1

Clock LPCG Tpm1

enumerator kCLOCK_Tpm2

Clock LPCG Tpm2

enumerator kCLOCK_Tpm3

Clock LPCG Tpm3

enumerator kCLOCK_Tpm4

Clock LPCG Tpm4

enumerator kCLOCK_Tpm5

Clock LPCG Tpm5

enumerator kCLOCK_Tpm6

Clock LPCG Tpm6

enumerator kCLOCK_Qtimer1

Clock LPCG Qtimer1

enumerator kCLOCK_Qtimer2

Clock LPCG Qtimer2

enumerator kCLOCK_Qtimer3

Clock LPCG Qtimer3

enumerator kCLOCK_Qtimer4

Clock LPCG Qtimer4

enumerator kCLOCK_Qtimer5

Clock LPCG Qtimer5

enumerator kCLOCK_Qtimer6

Clock LPCG Qtimer6

enumerator kCLOCK_Qtimer7

Clock LPCG Qtimer7

enumerator kCLOCK_Qtimer8

Clock LPCG Qtimer8

enumerator kCLOCK_Gpt1

Clock LPCG Gpt1

enumerator kCLOCK_Gpt2

Clock LPCG Gpt2

enumerator kCLOCK_Syscount

Clock LPCG Syscount

enumerator kCLOCK_Can1

Clock LPCG Can1

enumerator kCLOCK_Can2

Clock LPCG Can2

enumerator kCLOCK_Can3

Clock LPCG Can3

enumerator kCLOCK_Lpuart1

Clock LPCG Lpuart1

enumerator kCLOCK_Lpuart2

Clock LPCG Lpuart2

enumerator kCLOCK_Lpuart3

Clock LPCG Lpuart3

enumerator kCLOCK_Lpuart4

Clock LPCG Lpuart4

enumerator kCLOCK_Lpuart5

Clock LPCG Lpuart5

enumerator kCLOCK_Lpuart6

Clock LPCG Lpuart6

enumerator kCLOCK_Lpuart7

Clock LPCG Lpuart7

enumerator kCLOCK_Lpuart8

Clock LPCG Lpuart8

enumerator kCLOCK_Lpuart9

Clock LPCG Lpuart9

enumerator kCLOCK_Lpuart10

Clock LPCG Lpuart10

enumerator kCLOCK_Lpuart11

Clock LPCG Lpuart11

enumerator kCLOCK_Lpuart12

Clock LPCG Lpuart12

enumerator kCLOCK_Lpi2c1

Clock LPCG Lpi2c1

enumerator kCLOCK_Lpi2c2

Clock LPCG Lpi2c2

enumerator kCLOCK_Lpi2c3

Clock LPCG Lpi2c3

enumerator kCLOCK_Lpi2c4

Clock LPCG Lpi2c4

enumerator kCLOCK_Lpi2c5

Clock LPCG Lpi2c5

enumerator kCLOCK_Lpi2c6

Clock LPCG Lpi2c6

enumerator kCLOCK_Lpspi1

Clock LPCG Lpspi1

enumerator kCLOCK_Lpspi2

Clock LPCG Lpspi2

enumerator kCLOCK_Lpspi3

Clock LPCG Lpspi3

enumerator kCLOCK_Lpspi4

Clock LPCG Lpspi4

enumerator kCLOCK_Lpspi5

Clock LPCG Lpspi5

enumerator kCLOCK_Lpspi6

Clock LPCG Lpspi6

enumerator kCLOCK_I3c1

Clock LPCG I3c1

enumerator kCLOCK_I3c2

Clock LPCG I3c2

enumerator kCLOCK_Usdhc1

Clock LPCG Usdhc1

enumerator kCLOCK_Usdhc2

Clock LPCG Usdhc2

enumerator kCLOCK_Usb

Clock LPCG Usb

enumerator kCLOCK_Sinc1

Clock LPCG Sinc1

enumerator kCLOCK_Sinc2

Clock LPCG Sinc2

enumerator kCLOCK_Sinc3

Clock LPCG Sinc3

enumerator kCLOCK_Xbar1

Clock LPCG Xbar1

enumerator kCLOCK_Xbar2

Clock LPCG Xbar2

enumerator kCLOCK_Xbar3

Clock LPCG Xbar3

enumerator kCLOCK_Aoi1

Clock LPCG Aoi1

enumerator kCLOCK_Aoi2

Clock LPCG Aoi2

enumerator kCLOCK_Aoi3

Clock LPCG Aoi3

enumerator kCLOCK_Aoi4

Clock LPCG Aoi4

enumerator kCLOCK_Enc1

Clock LPCG Enc1

enumerator kCLOCK_Enc2

Clock LPCG Enc2

enumerator kCLOCK_Enc3

Clock LPCG Enc3

enumerator kCLOCK_Enc4

Clock LPCG Enc4

enumerator kCLOCK_Kpp

Clock LPCG Kpp

enumerator kCLOCK_Pwm1

Clock LPCG Pwm1

enumerator kCLOCK_Pwm2

Clock LPCG Pwm2

enumerator kCLOCK_Pwm3

Clock LPCG Pwm3

enumerator kCLOCK_Pwm4

Clock LPCG Pwm4

enumerator kCLOCK_Ecat

Clock LPCG Ecat

enumerator kCLOCK_Netc

Clock LPCG Netc

enumerator kCLOCK_Serdes1

Clock LPCG Serdes1

enumerator kCLOCK_Serdes2

Clock LPCG Serdes2

enumerator kCLOCK_Serdes3

Clock LPCG Serdes3

enumerator kCLOCK_Xcelbusx

Clock LPCG Xcelbusx

enumerator kCLOCK_Xriocu4

Clock LPCG Xriocu4

enumerator kCLOCK_Sptp

Clock LPCG Sptp

enumerator kCLOCK_Mctrl

Clock LPCG Mctrl

enumerator kCLOCK_Sai1

Clock LPCG Sai1

enumerator kCLOCK_Sai2

Clock LPCG Sai2

enumerator kCLOCK_Sai3

Clock LPCG Sai3

enumerator kCLOCK_Sai4

Clock LPCG Sai4

enumerator kCLOCK_Spdif

Clock LPCG Spdif

enumerator kCLOCK_Asrc

Clock LPCG Asrc

enumerator kCLOCK_Pdm

Clock LPCG Mic

enumerator kCLOCK_Vref

Clock LPCG Vref

enumerator kCLOCK_Bist

Clock LPCG Bist

enumerator kCLOCK_Ssi_W2M7

Clock LPCG Ssi_W2M7

enumerator kCLOCK_Ssi_M72W

Clock LPCG Ssi_M72W

enumerator kCLOCK_Ssi_W2Ao

Clock LPCG Ssi_W2Ao

enumerator kCLOCK_Ssi_Ao2W

Clock LPCG Ssi_Ao2W

enumerator kCLOCK_IpInvalid

Invalid value.

enum _clock_name

Clock name.

Values:

enumerator kCLOCK_OscRc24M

24MHz RC Oscillator.

enumerator kCLOCK_OscRc400M

400MHz RC Oscillator.

enumerator kCLOCK_Osc24M

24MHz Oscillator.

enumerator kCLOCK_Osc24MOut

24MHz Oscillator Out.

enumerator kCLOCK_ArmPll

ARM PLL.

enumerator kCLOCK_ArmPllOut

ARM PLL Out.

enumerator kCLOCK_SysPll2

SYS PLL2.

enumerator kCLOCK_SysPll2Out

SYS PLL2 OUT.

enumerator kCLOCK_SysPll2Pfd0

SYS PLL2 PFD0.

enumerator kCLOCK_SysPll2Pfd1

SYS PLL2 PFD1.

enumerator kCLOCK_SysPll2Pfd2

SYS PLL2 PFD2.

enumerator kCLOCK_SysPll2Pfd3

SYS PLL2 PFD3.

enumerator kCLOCK_SysPll3

SYS PLL3.

enumerator kCLOCK_SysPll3Out

SYS PLL3 OUT.

enumerator kCLOCK_SysPll3Div2

SYS PLL3 DIV2

enumerator kCLOCK_SysPll3Pfd0

SYS PLL3 PFD0.

enumerator kCLOCK_SysPll3Pfd1

SYS PLL3 PFD1

enumerator kCLOCK_SysPll3Pfd2

SYS PLL3 PFD2

enumerator kCLOCK_SysPll3Pfd3

SYS PLL3 PFD3

enumerator kCLOCK_SysPll1

SYS PLL1.

enumerator kCLOCK_SysPll1Out

SYS PLL1 OUT.

enumerator kCLOCK_SysPll1Div2

SYS PLL1 DIV2.

enumerator kCLOCK_SysPll1Div5

SYS PLL1 DIV5.

enumerator kCLOCK_AudioPll

SYS AUDIO PLL.

enumerator kCLOCK_AudioPllOut

SYS AUDIO PLL OUT.

enumerator kCLOCK_CpuClk

SYS CPU CLK.

enumerator kCLOCK_CoreSysClk

SYS CORE SYS CLK.

enum _clock_root

Root clock index.

Values:

enumerator kCLOCK_Root_M7

CLOCK Root M7

enumerator kCLOCK_Root_M33

CLOCK Root M33

enumerator kCLOCK_Root_Edgelock

CLOCK Root Edgelock

enumerator kCLOCK_Root_Bus_Aon

CLOCK Root Bus_Aon

enumerator kCLOCK_Root_Bus_Wakeup

CLOCK Root Bus_Wakeup

enumerator kCLOCK_Root_Wakeup_Axi

CLOCK Root Wakeup_Axi

enumerator kCLOCK_Root_Swo_Trace

CLOCK Root Swo_Trace

enumerator kCLOCK_Root_M33_Systick

CLOCK Root M33_Systick

enumerator kCLOCK_Root_M7_Systick

CLOCK Root M7_Systick

enumerator kCLOCK_Root_Flexio1

CLOCK Root Flexio1

enumerator kCLOCK_Root_Flexio2

CLOCK Root Flexio2

enumerator kCLOCK_Root_Lpit3

CLOCK Root Lpit3

enumerator kCLOCK_Root_Lptimer1

CLOCK Root Lptimer1

enumerator kCLOCK_Root_Lptimer2

CLOCK Root Lptimer2

enumerator kCLOCK_Root_Lptimer3

CLOCK Root Lptimer3

enumerator kCLOCK_Root_Tpm2

CLOCK Root Tpm2

enumerator kCLOCK_Root_Tpm4

CLOCK Root Tpm4

enumerator kCLOCK_Root_Tpm5

CLOCK Root Tpm5

enumerator kCLOCK_Root_Tpm6

CLOCK Root Tpm6

enumerator kCLOCK_Root_Gpt1

CLOCK Root Gpt1

enumerator kCLOCK_Root_Gpt2

CLOCK Root Gpt2

enumerator kCLOCK_Root_Flexspi1

CLOCK Root Flexspi1

enumerator kCLOCK_Root_Flexspi2

CLOCK Root Flexspi2

enumerator kCLOCK_Root_Flexspi_Slv

CLOCK Root Flexspi_Slv

enumerator kCLOCK_Root_Can1

CLOCK Root Can1

enumerator kCLOCK_Root_Can2

CLOCK Root Can2

enumerator kCLOCK_Root_Can3

CLOCK Root Can3

enumerator kCLOCK_Root_Lpuart0102

CLOCK Root Lpuart0102

enumerator kCLOCK_Root_Lpuart0304

CLOCK Root Lpuart0304

enumerator kCLOCK_Root_Lpuart0506

CLOCK Root Lpuart0506

enumerator kCLOCK_Root_Lpuart0708

CLOCK Root Lpuart0708

enumerator kCLOCK_Root_Lpuart0910

CLOCK Root Lpuart0910

enumerator kCLOCK_Root_Lpuart1112

CLOCK Root Lpuart1112

enumerator kCLOCK_Root_Lpi2c0102

CLOCK Root Lpi2c0102

enumerator kCLOCK_Root_Lpi2c0304

CLOCK Root Lpi2c0304

enumerator kCLOCK_Root_Lpi2c0506

CLOCK Root Lpi2c0506

enumerator kCLOCK_Root_Lpspi0102

CLOCK Root Lpspi0102

enumerator kCLOCK_Root_Lpspi0304

CLOCK Root Lpspi0304

enumerator kCLOCK_Root_Lpspi0506

CLOCK Root Lpspi0506

enumerator kCLOCK_Root_I3c1

CLOCK Root I3c1

enumerator kCLOCK_Root_I3c2

CLOCK Root I3c2

enumerator kCLOCK_Root_Usdhc1

CLOCK Root Usdhc1

enumerator kCLOCK_Root_Usdhc2

CLOCK Root Usdhc2

enumerator kCLOCK_Root_Semc

CLOCK Root Semc

enumerator kCLOCK_Root_Adc1

CLOCK Root Adc1

enumerator kCLOCK_Root_Adc2

CLOCK Root Adc2

enumerator kCLOCK_Root_Acmp

CLOCK Root Acmp

enumerator kCLOCK_Root_Ecat

CLOCK Root Ecat

enumerator kCLOCK_Root_Enet

CLOCK Root Enet

enumerator kCLOCK_Root_Tmr_1588

CLOCK Root Tmr_1588

enumerator kCLOCK_Root_Netc

CLOCK Root Netc

enumerator kCLOCK_Root_Mac0

CLOCK Root Mac0

enumerator kCLOCK_Root_Mac1

CLOCK Root Mac1

enumerator kCLOCK_Root_Mac2

CLOCK Root Mac2

enumerator kCLOCK_Root_Mac3

CLOCK Root Mac3

enumerator kCLOCK_Root_Mac4

CLOCK Root Mac4

enumerator kCLOCK_Root_Serdes0

CLOCK Root Serdes0

enumerator kCLOCK_Root_Serdes1

CLOCK Root Serdes1

enumerator kCLOCK_Root_Serdes2

CLOCK Root Serdes2

enumerator kCLOCK_Root_Serdes0_1G

CLOCK Root Serdes0_1G

enumerator kCLOCK_Root_Serdes1_1G

CLOCK Root Serdes1_1G

enumerator kCLOCK_Root_Serdes2_1G

CLOCK Root Serdes2_1G

enumerator kCLOCK_Root_Xcelbusx

CLOCK Root Xcelbusx

enumerator kCLOCK_Root_Xriocu4

CLOCK Root Xriocu4

enumerator kCLOCK_Root_Mctrl

CLOCK Root Mctrl

enumerator kCLOCK_Root_Sai1

CLOCK Root Sai1

enumerator kCLOCK_Root_Sai2

CLOCK Root Sai2

enumerator kCLOCK_Root_Sai3

CLOCK Root Sai3

enumerator kCLOCK_Root_Sai4

CLOCK Root Sai4

enumerator kCLOCK_Root_Spdif

CLOCK Root Spdif

enumerator kCLOCK_Root_Asrc

CLOCK Root Asrc

enumerator kCLOCK_Root_Mic

CLOCK Root Mic

enumerator kCLOCK_Root_Cko1

CLOCK Root Cko1

enumerator kCLOCK_Root_Cko2

CLOCK Root Cko2

enum _clock_root_mux_source

The enumerator of clock roots’ clock source mux value.

Values:

enumerator kCLOCK_M7_ClockRoot_MuxOscRc24M

M7 mux from OscRc24M.

enumerator kCLOCK_M7_ClockRoot_MuxOscRc400M

M7 mux from OscRc400M.

enumerator kCLOCK_M7_ClockRoot_MuxArmPllOut

M7 mux from ArmPllOut.

enumerator kCLOCK_M7_ClockRoot_MuxSysPll3Out

M7 mux from SysPll3Out.

enumerator kCLOCK_M33_ClockRoot_MuxOscRc24M

M33 mux from OscRc24M.

enumerator kCLOCK_M33_ClockRoot_MuxOscRc400M

M33 mux from OscRc400M.

enumerator kCLOCK_M33_ClockRoot_MuxSysPll3Out

M33 mux from SysPll3Out.

enumerator kCLOCK_M33_ClockRoot_MuxArmPllOut

M33 mux from ArmPllOut.

enumerator kCLOCK_EDGELOCK_ClockRoot_MuxOscRc24M

EDGELOCK mux from OscRc24M.

enumerator kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M

EDGELOCK mux from OscRc400M.

enumerator kCLOCK_EDGELOCK_ClockRoot_MuxSysPll1Out

EDGELOCK mux from SysPll1Out.

enumerator kCLOCK_EDGELOCK_ClockRoot_MuxSysPll2Pfd1

EDGELOCK mux from SysPll2Pfd1.

enumerator kCLOCK_BUS_AON_ClockRoot_MuxOscRc24M

BUS_AON mux from OscRc24M.

enumerator kCLOCK_BUS_AON_ClockRoot_MuxOscRc400M

BUS_AON mux from OscRc400M.

enumerator kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out

BUS_AON mux from SysPll2Out.

enumerator kCLOCK_BUS_AON_ClockRoot_MuxSysPll3Pfd2

BUS_AON mux from SysPll3Pfd2.

enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc24M

BUS_WAKEUP mux from OscRc24M.

enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxOscRc400M

BUS_WAKEUP mux from OscRc400M.

enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out

BUS_WAKEUP mux from SysPll2Out.

enumerator kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll3Pfd1

BUS_WAKEUP mux from SysPll3Pfd1.

enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc24M

WAKEUP_AXI mux from OscRc24M.

enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxOscRc400M

WAKEUP_AXI mux from OscRc400M.

enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out

WAKEUP_AXI mux from SysPll3Out.

enumerator kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll2Pfd1

WAKEUP_AXI mux from SysPll2Pfd1.

enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc24M

SWO_TRACE mux from OscRc24M.

enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxOscRc400M

SWO_TRACE mux from OscRc400M.

enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2

SWO_TRACE mux from SysPll3Div2.

enumerator kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll1Div5

SWO_TRACE mux from SysPll1Div5.

enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc24M

M33_SYSTICK mux from OscRc24M.

enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOscRc400M

M33_SYSTICK mux from OscRc400M.

enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut

M33_SYSTICK mux from Osc24MOut.

enumerator kCLOCK_M33_SYSTICK_ClockRoot_MuxSysPll3Div2

M33_SYSTICK mux from SysPll3Div2.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M

M7_SYSTICK mux from OscRc24M.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M

M7_SYSTICK mux from OscRc400M.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut

M7_SYSTICK mux from Osc24MOut.

enumerator kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2

M7_SYSTICK mux from SysPll3Div2.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc24M

FLEXIO1 mux from OscRc24M.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M

FLEXIO1 mux from OscRc400M.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2

FLEXIO1 mux from SysPll3Div2.

enumerator kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5

FLEXIO1 mux from SysPll1Div5.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc24M

FLEXIO2 mux from OscRc24M.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M

FLEXIO2 mux from OscRc400M.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2

FLEXIO2 mux from SysPll3Div2.

enumerator kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5

FLEXIO2 mux from SysPll1Div5.

enumerator kCLOCK_LPIT3_ClockRoot_MuxOscRc24M

LPIT3 mux from OscRc24M.

enumerator kCLOCK_LPIT3_ClockRoot_MuxOscRc400M

LPIT3 mux from OscRc400M.

enumerator kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2

LPIT3 mux from SysPll3Div2.

enumerator kCLOCK_LPIT3_ClockRoot_MuxSysPll2Pfd3

LPIT3 mux from SysPll2Pfd3.

enumerator kCLOCK_LPTIMER1_ClockRoot_MuxOscRc24M

LPTIMER1 mux from OscRc24M.

enumerator kCLOCK_LPTIMER1_ClockRoot_MuxOscRc400M

LPTIMER1 mux from OscRc400M.

enumerator kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2

LPTIMER1 mux from SysPll3Div2.

enumerator kCLOCK_LPTIMER1_ClockRoot_MuxSysPll2Pfd3

LPTIMER1 mux from SysPll2Pfd3.

enumerator kCLOCK_LPTIMER2_ClockRoot_MuxOscRc24M

LPTIMER2 mux from OscRc24M.

enumerator kCLOCK_LPTIMER2_ClockRoot_MuxOscRc400M

LPTIMER2 mux from OscRc400M.

enumerator kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2

LPTIMER2 mux from SysPll3Div2.

enumerator kCLOCK_LPTIMER2_ClockRoot_MuxSysPll2Pfd3

LPTIMER2 mux from SysPll2Pfd3.

enumerator kCLOCK_LPTIMER3_ClockRoot_MuxOscRc24M

LPTIMER3 mux from OscRc24M.

enumerator kCLOCK_LPTIMER3_ClockRoot_MuxOscRc400M

LPTIMER3 mux from OscRc400M.

enumerator kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2

LPTIMER3 mux from SysPll3Div2.

enumerator kCLOCK_LPTIMER3_ClockRoot_MuxSysPll2Pfd3

LPTIMER3 mux from SysPll2Pfd3.

enumerator kCLOCK_TPM2_ClockRoot_MuxOscRc24M

TPM2 mux from OscRc24M.

enumerator kCLOCK_TPM2_ClockRoot_MuxOscRc400M

TPM2 mux from OscRc400M.

enumerator kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2

TPM2 mux from SysPll3Div2.

enumerator kCLOCK_TPM2_ClockRoot_MuxSysPll2Pfd3

TPM2 mux from SysPll2Pfd3.

enumerator kCLOCK_TPM4_ClockRoot_MuxOscRc24M

TPM4 mux from OscRc24M.

enumerator kCLOCK_TPM4_ClockRoot_MuxOscRc400M

TPM4 mux from OscRc400M.

enumerator kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2

TPM4 mux from SysPll3Div2.

enumerator kCLOCK_TPM4_ClockRoot_MuxSysPll2Pfd3

TPM4 mux from SysPll2Pfd3.

enumerator kCLOCK_TPM5_ClockRoot_MuxOscRc24M

TPM5 mux from OscRc24M.

enumerator kCLOCK_TPM5_ClockRoot_MuxOscRc400M

TPM5 mux from OscRc400M.

enumerator kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2

TPM5 mux from SysPll3Div2.

enumerator kCLOCK_TPM5_ClockRoot_MuxSysPll2Pfd3

TPM5 mux from SysPll2Pfd3.

enumerator kCLOCK_TPM6_ClockRoot_MuxOscRc24M

TPM6 mux from OscRc24M.

enumerator kCLOCK_TPM6_ClockRoot_MuxOscRc400M

TPM6 mux from OscRc400M.

enumerator kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2

TPM6 mux from SysPll3Div2.

enumerator kCLOCK_TPM6_ClockRoot_MuxSysPll2Pfd3

TPM6 mux from SysPll2Pfd3.

enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc24M

GPT1 mux from OscRc24M.

enumerator kCLOCK_GPT1_ClockRoot_MuxOscRc400M

GPT1 mux from OscRc400M.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2

GPT1 mux from SysPll3Div2.

enumerator kCLOCK_GPT1_ClockRoot_MuxSysPll2Pfd3

GPT1 mux from SysPll2Pfd3.

enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc24M

GPT2 mux from OscRc24M.

enumerator kCLOCK_GPT2_ClockRoot_MuxOscRc400M

GPT2 mux from OscRc400M.

enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2

GPT2 mux from SysPll3Div2.

enumerator kCLOCK_GPT2_ClockRoot_MuxSysPll2Pfd3

GPT2 mux from SysPll2Pfd3.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M

FLEXSPI1 mux from OscRc24M.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M

FLEXSPI1 mux from OscRc400M.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0

FLEXSPI1 mux from SysPll3Pfd0.

enumerator kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd0

FLEXSPI1 mux from SysPll2Pfd0.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc24M

FLEXSPI2 mux from OscRc24M.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M

FLEXSPI2 mux from OscRc400M.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2

FLEXSPI2 mux from SysPll3Pfd2.

enumerator kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd1

FLEXSPI2 mux from SysPll2Pfd1.

enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc24M

FLEXSPI_SLV mux from OscRc24M.

enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxOscRc400M

FLEXSPI_SLV mux from OscRc400M.

enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out

FLEXSPI_SLV mux from SysPll2Out.

enumerator kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll1Out

FLEXSPI_SLV mux from SysPll1Out.

enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc24M

CAN1 mux from OscRc24M.

enumerator kCLOCK_CAN1_ClockRoot_MuxOscRc400M

CAN1 mux from OscRc400M.

enumerator kCLOCK_CAN1_ClockRoot_MuxSysPll3Out

CAN1 mux from SysPll3Out.

enumerator kCLOCK_CAN1_ClockRoot_MuxOsc24MOut

CAN1 mux from Osc24MOut.

enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc24M

CAN2 mux from OscRc24M.

enumerator kCLOCK_CAN2_ClockRoot_MuxOscRc400M

CAN2 mux from OscRc400M.

enumerator kCLOCK_CAN2_ClockRoot_MuxSysPll3Out

CAN2 mux from SysPll3Out.

enumerator kCLOCK_CAN2_ClockRoot_MuxOsc24MOut

CAN2 mux from Osc24MOut.

enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc24M

CAN3 mux from OscRc24M.

enumerator kCLOCK_CAN3_ClockRoot_MuxOscRc400M

CAN3 mux from OscRc400M.

enumerator kCLOCK_CAN3_ClockRoot_MuxSysPll3Out

CAN3 mux from SysPll3Out.

enumerator kCLOCK_CAN3_ClockRoot_MuxOsc24MOut

CAN3 mux from Osc24MOut.

enumerator kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M

LPUART0102 mux from OscRc24M.

enumerator kCLOCK_LPUART0102_ClockRoot_MuxOscRc400M

LPUART0102 mux from OscRc400M.

enumerator kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2

LPUART0102 mux from SysPll3Div2.

enumerator kCLOCK_LPUART0102_ClockRoot_MuxSysPll2Pfd3

LPUART0102 mux from SysPll2Pfd3.

enumerator kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M

LPUART0304 mux from OscRc24M.

enumerator kCLOCK_LPUART0304_ClockRoot_MuxOscRc400M

LPUART0304 mux from OscRc400M.

enumerator kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2

LPUART0304 mux from SysPll3Div2.

enumerator kCLOCK_LPUART0304_ClockRoot_MuxSysPll2Pfd3

LPUART0304 mux from SysPll2Pfd3.

enumerator kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M

LPUART0506 mux from OscRc24M.

enumerator kCLOCK_LPUART0506_ClockRoot_MuxOscRc400M

LPUART0506 mux from OscRc400M.

enumerator kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2

LPUART0506 mux from SysPll3Div2.

enumerator kCLOCK_LPUART0506_ClockRoot_MuxSysPll2Pfd3

LPUART0506 mux from SysPll2Pfd3.

enumerator kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M

LPUART0708 mux from OscRc24M.

enumerator kCLOCK_LPUART0708_ClockRoot_MuxOscRc400M

LPUART0708 mux from OscRc400M.

enumerator kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2

LPUART0708 mux from SysPll3Div2.

enumerator kCLOCK_LPUART0708_ClockRoot_MuxSysPll2Pfd3

LPUART0708 mux from SysPll2Pfd3.

enumerator kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M

LPUART0910 mux from OscRc24M.

enumerator kCLOCK_LPUART0910_ClockRoot_MuxOscRc400M

LPUART0910 mux from OscRc400M.

enumerator kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2

LPUART0910 mux from SysPll3Div2.

enumerator kCLOCK_LPUART0910_ClockRoot_MuxSysPll2Pfd3

LPUART0910 mux from SysPll2Pfd3.

enumerator kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M

LPUART1112 mux from OscRc24M.

enumerator kCLOCK_LPUART1112_ClockRoot_MuxOscRc400M

LPUART1112 mux from OscRc400M.

enumerator kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2

LPUART1112 mux from SysPll3Div2.

enumerator kCLOCK_LPUART1112_ClockRoot_MuxSysPll2Pfd3

LPUART1112 mux from SysPll2Pfd3.

enumerator kCLOCK_LPI2C0102_ClockRoot_MuxOscRc24M

LPI2C0102 mux from OscRc24M.

enumerator kCLOCK_LPI2C0102_ClockRoot_MuxOscRc400M

LPI2C0102 mux from OscRc400M.

enumerator kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2

LPI2C0102 mux from SysPll3Div2.

enumerator kCLOCK_LPI2C0102_ClockRoot_MuxSysPll2Pfd3

LPI2C0102 mux from SysPll2Pfd3.

enumerator kCLOCK_LPI2C0304_ClockRoot_MuxOscRc24M

LPI2C0304 mux from OscRc24M.

enumerator kCLOCK_LPI2C0304_ClockRoot_MuxOscRc400M

LPI2C0304 mux from OscRc400M.

enumerator kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2

LPI2C0304 mux from SysPll3Div2.

enumerator kCLOCK_LPI2C0304_ClockRoot_MuxSysPll2Pfd3

LPI2C0304 mux from SysPll2Pfd3.

enumerator kCLOCK_LPI2C0506_ClockRoot_MuxOscRc24M

LPI2C0506 mux from OscRc24M.

enumerator kCLOCK_LPI2C0506_ClockRoot_MuxOscRc400M

LPI2C0506 mux from OscRc400M.

enumerator kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2

LPI2C0506 mux from SysPll3Div2.

enumerator kCLOCK_LPI2C0506_ClockRoot_MuxSysPll2Pfd3

LPI2C0506 mux from SysPll2Pfd3.

enumerator kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M

LPSPI0102 mux from OscRc24M.

enumerator kCLOCK_LPSPI0102_ClockRoot_MuxOscRc400M

LPSPI0102 mux from OscRc400M.

enumerator kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1

LPSPI0102 mux from SysPll3Pfd1.

enumerator kCLOCK_LPSPI0102_ClockRoot_MuxSysPll2Out

LPSPI0102 mux from SysPll2Out.

enumerator kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M

LPSPI0304 mux from OscRc24M.

enumerator kCLOCK_LPSPI0304_ClockRoot_MuxOscRc400M

LPSPI0304 mux from OscRc400M.

enumerator kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1

LPSPI0304 mux from SysPll3Pfd1.

enumerator kCLOCK_LPSPI0304_ClockRoot_MuxSysPll2Out

LPSPI0304 mux from SysPll2Out.

enumerator kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M

LPSPI0506 mux from OscRc24M.

enumerator kCLOCK_LPSPI0506_ClockRoot_MuxOscRc400M

LPSPI0506 mux from OscRc400M.

enumerator kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1

LPSPI0506 mux from SysPll3Pfd1.

enumerator kCLOCK_LPSPI0506_ClockRoot_MuxSysPll2Out

LPSPI0506 mux from SysPll2Out.

enumerator kCLOCK_I3C1_ClockRoot_MuxOscRc24M

I3C1 mux from OscRc24M.

enumerator kCLOCK_I3C1_ClockRoot_MuxOscRc400M

I3C1 mux from OscRc400M.

enumerator kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2

I3C1 mux from SysPll3Div2.

enumerator kCLOCK_I3C1_ClockRoot_MuxSysPll2Pfd3

I3C1 mux from SysPll2Pfd3.

enumerator kCLOCK_I3C2_ClockRoot_MuxOscRc24M

I3C2 mux from OscRc24M.

enumerator kCLOCK_I3C2_ClockRoot_MuxOscRc400M

I3C2 mux from OscRc400M.

enumerator kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2

I3C2 mux from SysPll3Div2.

enumerator kCLOCK_I3C2_ClockRoot_MuxSysPll2Pfd3

I3C2 mux from SysPll2Pfd3.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc24M

USDHC1 mux from OscRc24M.

enumerator kCLOCK_USDHC1_ClockRoot_MuxOscRc400M

USDHC1 mux from OscRc400M.

enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2

USDHC1 mux from SysPll2Pfd2.

enumerator kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5

USDHC1 mux from SysPll1Div5.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc24M

USDHC2 mux from OscRc24M.

enumerator kCLOCK_USDHC2_ClockRoot_MuxOscRc400M

USDHC2 mux from OscRc400M.

enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2

USDHC2 mux from SysPll2Pfd2.

enumerator kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5

USDHC2 mux from SysPll1Div5.

enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc24M

SEMC mux from OscRc24M.

enumerator kCLOCK_SEMC_ClockRoot_MuxOscRc400M

SEMC mux from OscRc400M.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll1Out

SEMC mux from SysPll1Out.

enumerator kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd0

SEMC mux from SysPll2Pfd0.

enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc24M

ADC1 mux from OscRc24M.

enumerator kCLOCK_ADC1_ClockRoot_MuxOscRc400M

ADC1 mux from OscRc400M.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2

ADC1 mux from SysPll3Div2.

enumerator kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3

ADC1 mux from SysPll2Pfd3.

enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc24M

ADC2 mux from OscRc24M.

enumerator kCLOCK_ADC2_ClockRoot_MuxOscRc400M

ADC2 mux from OscRc400M.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2

ADC2 mux from SysPll3Div2.

enumerator kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3

ADC2 mux from SysPll2Pfd3.

enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc24M

ACMP mux from OscRc24M.

enumerator kCLOCK_ACMP_ClockRoot_MuxOscRc400M

ACMP mux from OscRc400M.

enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll3Out

ACMP mux from SysPll3Out.

enumerator kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3

ACMP mux from SysPll2Pfd3.

enumerator kCLOCK_ECAT_ClockRoot_MuxOscRc24M

ECAT mux from OscRc24M.

enumerator kCLOCK_ECAT_ClockRoot_MuxOscRc400M

ECAT mux from OscRc400M.

enumerator kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2

ECAT mux from SysPll1Div2.

enumerator kCLOCK_ECAT_ClockRoot_MuxSysPll1Div5

ECAT mux from SysPll1Div5.

enumerator kCLOCK_ENET_ClockRoot_MuxOscRc24M

ENET mux from OscRc24M.

enumerator kCLOCK_ENET_ClockRoot_MuxOscRc400M

ENET mux from OscRc400M.

enumerator kCLOCK_ENET_ClockRoot_MuxSysPll1Div2

ENET mux from SysPll1Div2.

enumerator kCLOCK_ENET_ClockRoot_MuxSysPll1Div5

ENET mux from SysPll1Div5.

enumerator kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M

TMR_1588 mux from OscRc24M.

enumerator kCLOCK_TMR_1588_ClockRoot_MuxOscRc400M

TMR_1588 mux from OscRc400M.

enumerator kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out

TMR_1588 mux from SysPll3Out.

enumerator kCLOCK_TMR_1588_ClockRoot_MuxSysPll2Pfd3

TMR_1588 mux from SysPll2Pfd3.

enumerator kCLOCK_NETC_ClockRoot_MuxOscRc24M

NETC mux from OscRc24M.

enumerator kCLOCK_NETC_ClockRoot_MuxOscRc400M

NETC mux from OscRc400M.

enumerator kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3

NETC mux from SysPll3Pfd3.

enumerator kCLOCK_NETC_ClockRoot_MuxSysPll2Pfd1

NETC mux from SysPll2Pfd1.

enumerator kCLOCK_MAC0_ClockRoot_MuxOscRc24M

MAC0 mux from OscRc24M.

enumerator kCLOCK_MAC0_ClockRoot_MuxOscRc400M

MAC0 mux from OscRc400M.

enumerator kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2

MAC0 mux from SysPll1Div2.

enumerator kCLOCK_MAC0_ClockRoot_MuxSysPll1Div5

MAC0 mux from SysPll1Div5.

enumerator kCLOCK_MAC1_ClockRoot_MuxOscRc24M

MAC1 mux from OscRc24M.

enumerator kCLOCK_MAC1_ClockRoot_MuxOscRc400M

MAC1 mux from OscRc400M.

enumerator kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2

MAC1 mux from SysPll1Div2.

enumerator kCLOCK_MAC1_ClockRoot_MuxSysPll1Div5

MAC1 mux from SysPll1Div5.

enumerator kCLOCK_MAC2_ClockRoot_MuxOscRc24M

MAC2 mux from OscRc24M.

enumerator kCLOCK_MAC2_ClockRoot_MuxOscRc400M

MAC2 mux from OscRc400M.

enumerator kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2

MAC2 mux from SysPll1Div2.

enumerator kCLOCK_MAC2_ClockRoot_MuxSysPll1Div5

MAC2 mux from SysPll1Div5.

enumerator kCLOCK_MAC3_ClockRoot_MuxOscRc24M

MAC3 mux from OscRc24M.

enumerator kCLOCK_MAC3_ClockRoot_MuxOscRc400M

MAC3 mux from OscRc400M.

enumerator kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2

MAC3 mux from SysPll1Div2.

enumerator kCLOCK_MAC3_ClockRoot_MuxSysPll1Div5

MAC3 mux from SysPll1Div5.

enumerator kCLOCK_MAC4_ClockRoot_MuxOscRc24M

MAC4 mux from OscRc24M.

enumerator kCLOCK_MAC4_ClockRoot_MuxOscRc400M

MAC4 mux from OscRc400M.

enumerator kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2

MAC4 mux from SysPll1Div2.

enumerator kCLOCK_MAC4_ClockRoot_MuxSysPll1Div5

MAC4 mux from SysPll1Div5.

enumerator kCLOCK_SERDES0_ClockRoot_MuxOscRc24M

SERDES0 mux from OscRc24M.

enumerator kCLOCK_SERDES0_ClockRoot_MuxOscRc400M

SERDES0 mux from OscRc400M.

enumerator kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div2

SERDES0 mux from SysPll1Div2.

enumerator kCLOCK_SERDES0_ClockRoot_MuxSysPll1Div5

SERDES0 mux from SysPll1Div5.

enumerator kCLOCK_SERDES1_ClockRoot_MuxOscRc24M

SERDES1 mux from OscRc24M.

enumerator kCLOCK_SERDES1_ClockRoot_MuxOscRc400M

SERDES1 mux from OscRc400M.

enumerator kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div2

SERDES1 mux from SysPll1Div2.

enumerator kCLOCK_SERDES1_ClockRoot_MuxSysPll1Div5

SERDES1 mux from SysPll1Div5.

enumerator kCLOCK_SERDES2_ClockRoot_MuxOscRc24M

SERDES2 mux from OscRc24M.

enumerator kCLOCK_SERDES2_ClockRoot_MuxOscRc400M

SERDES2 mux from OscRc400M.

enumerator kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div2

SERDES2 mux from SysPll1Div2.

enumerator kCLOCK_SERDES2_ClockRoot_MuxSysPll1Div5

SERDES2 mux from SysPll1Div5.

enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc24M

SERDES0_1G mux from OscRc24M.

enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxOscRc400M

SERDES0_1G mux from OscRc400M.

enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxSysPll1Out

SERDES0_1G mux from SysPll1Out.

enumerator kCLOCK_SERDES0_1G_ClockRoot_MuxAudioPllOut

SERDES0_1G mux from AudioPllOut.

enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc24M

SERDES1_1G mux from OscRc24M.

enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxOscRc400M

SERDES1_1G mux from OscRc400M.

enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxSysPll1Out

SERDES1_1G mux from SysPll1Out.

enumerator kCLOCK_SERDES1_1G_ClockRoot_MuxAudioPllOut

SERDES1_1G mux from AudioPllOut.

enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc24M

SERDES2_1G mux from OscRc24M.

enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxOscRc400M

SERDES2_1G mux from OscRc400M.

enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxSysPll1Out

SERDES2_1G mux from SysPll1Out.

enumerator kCLOCK_SERDES2_1G_ClockRoot_MuxAudioPllOut

SERDES2_1G mux from AudioPllOut.

enumerator kCLOCK_XCELBUSX_ClockRoot_MuxOscRc24M

XCELBUSX mux from OscRc24M.

enumerator kCLOCK_XCELBUSX_ClockRoot_MuxOscRc400M

XCELBUSX mux from OscRc400M.

enumerator kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Out

XCELBUSX mux from SysPll3Out.

enumerator kCLOCK_XCELBUSX_ClockRoot_MuxSysPll3Pfd1

XCELBUSX mux from SysPll3Pfd1.

enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOscRc24M

XRIOCU4 mux from OscRc24M.

enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOscRc400M

XRIOCU4 mux from OscRc400M.

enumerator kCLOCK_XRIOCU4_ClockRoot_MuxOsc24MOut

XRIOCU4 mux from Osc24MOut.

enumerator kCLOCK_XRIOCU4_ClockRoot_MuxSysPll3Div2

XRIOCU4 mux from SysPll3Div2.

enumerator kCLOCK_MCTRL_ClockRoot_MuxOscRc24M

MCTRL mux from OscRc24M.

enumerator kCLOCK_MCTRL_ClockRoot_MuxOscRc400M

MCTRL mux from OscRc400M.

enumerator kCLOCK_MCTRL_ClockRoot_MuxSysPll1Div5

MCTRL mux from SysPll1Div5.

enumerator kCLOCK_MCTRL_ClockRoot_MuxAudioPllOut

MCTRL mux from AudioPllOut.

enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc24M

SAI1 mux from OscRc24M.

enumerator kCLOCK_SAI1_ClockRoot_MuxOscRc400M

SAI1 mux from OscRc400M.

enumerator kCLOCK_SAI1_ClockRoot_MuxAudioPllOut

SAI1 mux from AudioPllOut.

enumerator kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2

SAI1 mux from SysPll3Pfd2.

enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc24M

SAI2 mux from OscRc24M.

enumerator kCLOCK_SAI2_ClockRoot_MuxOscRc400M

SAI2 mux from OscRc400M.

enumerator kCLOCK_SAI2_ClockRoot_MuxAudioPllOut

SAI2 mux from AudioPllOut.

enumerator kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2

SAI2 mux from SysPll3Pfd2.

enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc24M

SAI3 mux from OscRc24M.

enumerator kCLOCK_SAI3_ClockRoot_MuxOscRc400M

SAI3 mux from OscRc400M.

enumerator kCLOCK_SAI3_ClockRoot_MuxAudioPllOut

SAI3 mux from AudioPllOut.

enumerator kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2

SAI3 mux from SysPll3Pfd2.

enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc24M

SAI4 mux from OscRc24M.

enumerator kCLOCK_SAI4_ClockRoot_MuxOscRc400M

SAI4 mux from OscRc400M.

enumerator kCLOCK_SAI4_ClockRoot_MuxAudioPllOut

SAI4 mux from AudioPllOut.

enumerator kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd2

SAI4 mux from SysPll3Pfd2.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc24M

SPDIF mux from OscRc24M.

enumerator kCLOCK_SPDIF_ClockRoot_MuxOscRc400M

SPDIF mux from OscRc400M.

enumerator kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut

SPDIF mux from AudioPllOut.

enumerator kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2

SPDIF mux from SysPll3Pfd2.

enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc24M

ASRC mux from OscRc24M.

enumerator kCLOCK_ASRC_ClockRoot_MuxOscRc400M

ASRC mux from OscRc400M.

enumerator kCLOCK_ASRC_ClockRoot_MuxSysPll3Out

ASRC mux from SysPll3Out.

enumerator kCLOCK_ASRC_ClockRoot_MuxAudioPllOut

ASRC mux from AudioPllOut.

enumerator kCLOCK_MIC_ClockRoot_MuxOscRc24M

MIC mux from OscRc24M.

enumerator kCLOCK_MIC_ClockRoot_MuxOscRc400M

MIC mux from OscRc400M.

enumerator kCLOCK_MIC_ClockRoot_MuxSysPll3Div2

MIC mux from SysPll3Div2.

enumerator kCLOCK_MIC_ClockRoot_MuxAudioPllOut

MIC mux from AudioPllOut.

enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc24M

CKO1 mux from OscRc24M.

enumerator kCLOCK_CKO1_ClockRoot_MuxOscRc400M

CKO1 mux from OscRc400M.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2

CKO1 mux from SysPll3Div2.

enumerator kCLOCK_CKO1_ClockRoot_MuxSysPll1Div2

CKO1 mux from SysPll1Div2.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc24M

CKO2 mux from OscRc24M.

enumerator kCLOCK_CKO2_ClockRoot_MuxOscRc400M

CKO2 mux from OscRc400M.

enumerator kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5

CKO2 mux from SysPll1Div5.

enumerator kCLOCK_CKO2_ClockRoot_MuxArmPllOut

CKO2 mux from ArmPllOut.

enum _clock_osc

OSC 24M sorce select.

Values:

enumerator kCLOCK_RcOsc

On chip OSC.

enumerator kCLOCK_XtalOsc

24M Xtal OSC

enum _clock_gate_value

Clock gate value.

Values:

enumerator kCLOCK_Off

Clock is off.

enumerator kCLOCK_On

Clock is on

enum _clock_mode_t

System clock mode.

Values:

enumerator kCLOCK_ModeRun

Remain in run mode.

enumerator kCLOCK_ModeWait

Transfer to wait mode.

enumerator kCLOCK_ModeStop

Transfer to stop mode.

enum _clock_usb_src

USB clock source definition.

Values:

enumerator kCLOCK_Usb480M

Use 480M.

enumerator kCLOCK_UsbSrcUnused

Used when the function does not care the clock source.

enum _clock_usb_phy_src

Source of the USB HS PHY.

Values:

enumerator kCLOCK_Usbphy480M

Use 480M.

enum _clock_pll_clk_src

PLL clock source, bypass cloco source also.

Values:

enumerator kCLOCK_PllClkSrc24M

Pll clock source 24M

enumerator kCLOCK_PllSrcClkPN

Pll clock source CLK1_P and CLK1_N

enum _clock_pll_post_div

PLL post divider enumeration.

Values:

enumerator kCLOCK_PllPostDiv2

Divide by 2.

enumerator kCLOCK_PllPostDiv4

Divide by 4.

enumerator kCLOCK_PllPostDiv8

Divide by 8.

enumerator kCLOCK_PllPostDiv1

Divide by 1.

enum _clock_output1_selection

The enumerater of clock output1’s clock source.

Values:

enumerator kCLOCK_CKO1OutputMuxOscRc24M

CKO1 mux from OscRc24M.

enumerator kCLOCK_CKO1OutputMuxOscRc400M

CKO1 mux from OscRc400M.

enumerator kCLOCK_CKO1OutputMuxSysPll3Div2

CKO1 mux from SysPll3Div2.

enumerator kCLOCK_CKO1OutputMuxSysPll1Div2

CKO1 mux from SysPll1Div2.

enum _clock_output2_selection

The enumerater of clock output2’s clock source.

Values:

enumerator kCLOCK_CKO2OutputMuxOscRc24M

CKO2 mux from OscRc24M.

enumerator kCLOCK_CKO2OutputMuxOscRc400M

CKO2 mux from OscRc400M.

enumerator kCLOCK_CKO2OutputMuxSysPll1Div5

CKO2 mux from SysPll1Div5.

enumerator kCLOCK_CKO2OutputMuxArmPllOut

CKO2 mux from ArmPllOut.

enum _clock_pll

PLL name.

Values:

enumerator kCLOCK_PllArm

ARM PLL.

enumerator kCLOCK_PllSys1

SYS1 PLL, it has a dedicated frequency of 1GHz.

enumerator kCLOCK_PllSys2

SYS2 PLL, it has a dedicated frequency of 528MHz.

enumerator kCLOCK_PllSys3

SYS3 PLL, it has a dedicated frequency of 480MHz.

enumerator kCLOCK_PllAudio

Audio PLL.

enumerator kCLOCK_PllInvalid

Invalid value.

enum _clock_pfd

PLL PFD name.

Values:

enumerator kCLOCK_Pfd0

PLL PFD0

enumerator kCLOCK_Pfd1

PLL PFD1

enumerator kCLOCK_Pfd2

PLL PFD2

enumerator kCLOCK_Pfd3

PLL PFD3

enum _clock_control_mode

The enumeration of control mode.

Values:

enumerator kCLOCK_SoftwareMode

Software control mode.

enumerator kCLOCK_GpcMode

GPC control mode.

enum _clock_24MOsc_mode

The enumeration of 24MHz crystal oscillator mode.

Values:

enumerator kCLOCK_24MOscHighGainMode

24MHz crystal oscillator work as high gain mode.

enumerator kCLOCK_24MOscBypassMode

24MHz crystal oscillator work as bypass mode.

enumerator kCLOCK_24MOscLowPowerMode

24MHz crystal oscillator work as low power mode.

enum _clock_1MHzOut_behavior

The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

Values:

enumerator kCLOCK_1MHzOutDisable

Disable 1MHz output clock.

enumerator kCLOCK_1MHzOutEnableLocked1Mhz

Enable 1MHz output clock, and select locked 1MHz to output.

enumerator kCLOCK_1MHzOutEnableFreeRunning1Mhz

Enable 1MHZ output clock, and select free-running 1MHz to output.

enum _clock_level

The clock dependence level.

Values:

enumerator kCLOCK_Level0

Not needed in any mode.

enumerator kCLOCK_Level1

Needed in RUN mode.

enumerator kCLOCK_Level2

Needed in RUN and WAIT mode.

enumerator kCLOCK_Level3

Needed in RUN, WAIT and STOP mode.

enumerator kCLOCK_Level4

Always on in any mode.

typedef enum _clock_lpcg clock_lpcg_t

Clock LPCG index.

typedef enum _clock_name clock_name_t

Clock name.

typedef enum _clock_root clock_root_t

Root clock index.

typedef enum _clock_root_mux_source clock_root_mux_source_t

The enumerator of clock roots’ clock source mux value.

typedef enum _clock_osc clock_osc_t

OSC 24M sorce select.

typedef enum _clock_gate_value clock_gate_value_t

Clock gate value.

typedef enum _clock_mode_t clock_mode_t

System clock mode.

typedef enum _clock_usb_src clock_usb_src_t

USB clock source definition.

typedef enum _clock_usb_phy_src clock_usb_phy_src_t

Source of the USB HS PHY.

typedef enum _clock_pll_post_div clock_pll_post_div_t

PLL post divider enumeration.

typedef enum _clock_output1_selection clock_output1_selection_t

The enumerater of clock output1’s clock source.

typedef enum _clock_output2_selection clock_output2_selection_t

The enumerater of clock output2’s clock source.

typedef struct _clock_arm_pll_config clock_arm_pll_config_t

PLL configuration for ARM.

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

typedef struct _clock_usb_pll_config clock_usb_pll_config_t

PLL configuration for USB.

typedef struct _clock_pll_ss_config clock_pll_ss_config_t

Spread specturm configure Pll.

typedef struct _clock_sys_pll2_config clock_sys_pll2_config_t

PLL configure for Sys Pll2.

typedef struct _clock_sys_pll1_config clock_sys_pll1_config_t

PLL configure for Sys Pll1.

typedef struct _clock_audio_pll_config clock_audio_pll_config_t

PLL configuration for AUDIO.

typedef struct _clock_root_config_t clock_root_config_t

Clock root configuration.

typedef enum _clock_pll clock_pll_t

PLL name.

typedef enum _clock_pfd clock_pfd_t

PLL PFD name.

typedef enum _clock_control_mode clock_control_mode_t

The enumeration of control mode.

typedef enum _clock_24MOsc_mode clock_24MOsc_mode_t

The enumeration of 24MHz crystal oscillator mode.

typedef enum _clock_1MHzOut_behavior clock_1MHzOut_behavior_t

The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

typedef enum _clock_level clock_level_t

The clock dependence level.

const clock_name_t s_clockSourceName[][4]

static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)

Set CCM Root Clock MUX node to certain value.

Parameters:

• root – Which root clock node to set, see clock_root_t.

• src – Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.

static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)

Get CCM Root Clock MUX value.

Parameters:

• root – Which root clock node to get, see clock_root_t.

Returns:

Clock mux value.

static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)

Get CCM Root Clock Source.

Parameters:

• root – Which root clock node to get, see clock_root_t.

• src – Clock mux value to get, see clock_root_mux_source_t.

Returns:

Clock source

static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div)

Set CCM Root Clock DIV certain value.

Parameters:

• root – Which root clock to set, see clock_root_t.

• div – Clock div value to set, different divider has different value range.

static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)

Get CCM DIV node value.

Parameters:

• root – Which root clock node to get, see clock_root_t.

Returns:

divider set for this root

static inline void CLOCK_PowerOffRootClock(clock_root_t root)

Power Off Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

static inline void CLOCK_PowerOnRootClock(clock_root_t root)

Power On Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)

Configure Root Clock.

Parameters:

• root – Which root clock node to set, see clock_root_t.

• config – root clock config, see clock_root_config_t

static inline void CLOCK_ControlGate(clock_lpcg_t name, clock_gate_value_t value)

Control the clock gate for specific IP.

Note

This API will not have any effect when this clock is in CPULPM or SetPoint Mode

Parameters:

• name – Which clock to enable, see clock_lpcg_t.

• value – Clock gate value to set, see clock_gate_value_t.

static inline void CLOCK_EnableClock(clock_lpcg_t name)

Enable the clock for specific IP.

Parameters:

• name – Which clock to enable, see clock_lpcg_t.

static inline void CLOCK_DisableClock(clock_lpcg_t name)

Disable the clock for specific IP.

Parameters:

• name – Which clock to disable, see clock_lpcg_t.

uint32_t CLOCK_GetFreq(clock_name_t name)

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters:

• name – Clock names defined in clock_name_t

Returns:

Clock frequency value in hertz

static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)

Gets the clock frequency for a specific root clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.

Parameters:

• root – Clock names defined in clock_root_t

Returns:

Clock frequency value in hertz

uint32_t CLOCK_GetM7Freq(void)

Get the CCM CPU/core/system frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetM33Freq(void)

Get the CCM CPU/core/system frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)

Check if PLL is bypassed.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

Returns:

PLL bypass status.

• true: The PLL is bypassed.

• false: The PLL is not bypassed.

static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)

Check if PLL is enabled.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

Returns:

PLL bypass status.

• true: The PLL is enabled.

• false: The PLL is not enabled.

FSL_CLOCK_DRIVER_VERSION

CLOCK driver version.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

CCSR_OFFSET

CCM registers offset.

CBCDR_OFFSET

CBCMR_OFFSET

CSCMR1_OFFSET

CSCMR2_OFFSET

CSCDR1_OFFSET

CDCDR_OFFSET

CSCDR2_OFFSET

CSCDR3_OFFSET

CACRR_OFFSET

CS1CDR_OFFSET

CS2CDR_OFFSET

ARM_PLL_OFFSET

CCM Analog registers offset.

PLL_SYS_OFFSET

PLL_USB1_OFFSET

PLL_AUDIO_OFFSET

PLL_VIDEO_OFFSET

PLL_ENET_OFFSET

PLL_USB2_OFFSET

CCM_TUPLE(reg, shift, mask, busyShift)

CCM_TUPLE_REG(base, tuple)

CCM_TUPLE_SHIFT(tuple)

CCM_TUPLE_MASK(tuple)

CCM_TUPLE_BUSY_SHIFT(tuple)

CCM_BUSY_WAIT

CCM_ANALOG_TUPLE(reg, shift)

CCM ANALOG tuple macros to map corresponding registers and bit fields.

CCM_ANALOG_TUPLE_SHIFT(tuple)

CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)

CCM_ANALOG_TUPLE_REG(base, tuple)

PLL_SYS1_1G_FREQ

SYS_PLL_FREQ frequency in Hz.

PLL_SYS2_528_MFI

PLL_SYS2_528_FREQ

PLL_SYS3_480_MFI

PLL_SYS3_480_FREQ

XTAL_FREQ

VREF_CLOCKS

Clock gate name array for VREF.

LPADC_CLOCKS

Clock gate name array for LPADC.

AOI_CLOCKS

Clock gate name array for AOI.

ASRC_CLOCKS

Clock ip name array for ASRC.

CMP_CLOCKS

Clock ip name array for CMP.

DAC_CLOCKS

Clock ip name array for DAC.

DCDC_CLOCKS

Clock gate name array for DCDC.

ECAT_CLOCKS

Clock ip name array for ECAT.

EDMA_CLOCKS

Clock gate name array for EDMA.

ENC_CLOCKS

Clock ip name array for ENC.

EWM_CLOCKS

Clock gate name array for EWM.

FLEXCAN_CLOCKS

Clock ip name array for FLEXCAN.

FLEXIO_CLOCKS

Clock ip name array for FLEXIO.

FLEXSPI_CLOCKS

Clock gate name array for FLEXSPI.

FLEXSPI_SLV_CLOCKS

Clock gate name array for FLEXSPI_SLV.

GPC_CLOCKS

Clock gate name array for GPC.

GPIO_CLOCKS

Clock ip name array for GPIO.

GPT_CLOCKS

Clock ip name array for GPT.

I3C_CLOCKS

Clock ip name array for I3C.

IEE_CLOCKS

Clock ip name array for IEE.

KPP_CLOCKS

Clock ip name array for KPP.

LPI2C_CLOCKS

Clock ip name array for LPI2C.

LPIT_CLOCKS

Clock ip name array for LPIT.

LPSPI_CLOCKS

Clock ip name array for LPSPI.

LPTMR_CLOCKS

Clock ip name array for LPTMR.

LPUART_CLOCKS

Clock ip name array for LPUART.

PDM_CLOCKS

Clock ip name array for MIC.

MU_CLOCKS

Clock gate name array for MU.

NETC_CLOCKS

Clock ip name array for NETC.

OCOTP_CLOCKS

Clock ip name array for OCOTP.

PWM_CLOCKS

Clock ip name array for PWM.

SAI_CLOCKS

Clock ip name array for SAI.

SEMA42_CLOCKS

Clock gate name array for Sema.

SEMC_CLOCKS

Clock ip name array for SEMC.

SERDES_CLOCKS

Clock ip name array for SERDES.

SINC_CLOCKS

Clock ip name array for SINC.

SPDIF_CLOCKS

Clock ip name array for SPDIF.

SRC_CLOCKS

Clock gate name array for SRC.

TMR_CLOCKS

Clock ip name array for QTIMER.

TPM_CLOCKS

Clock ip name array for TPM.

USB_CLOCKS

Clock ip name array for USB.

USDHC_CLOCKS

Clock ip name array for USDHC.

WDOG_CLOCKS

Clock gate name array for WDOG.

XBAR_CLOCKS

Clock ip name array for XBAR.

CCM_OBS_OSC_RC_24M

CCM_OBS_OSC_RC_400M

CCM_OBS_OSC_24M_OUT

CCM_OBS_PLL_ARM_OUT

CCM_OBS_PLL_528_OUT

CCM_OBS_PLL_528_PFD0

CCM_OBS_PLL_528_PFD1

CCM_OBS_PLL_528_PFD2

CCM_OBS_PLL_528_PFD3

CCM_OBS_PLL_480_OUT

CCM_OBS_PLL_480_DIV2

CCM_OBS_PLL_480_PFD0

CCM_OBS_PLL_480_PFD1

CCM_OBS_PLL_480_PFD2

CCM_OBS_PLL_480_PFD3

CCM_OBS_PLL_1G_OUT

CCM_OBS_PLL_1G_DIV2

CCM_OBS_PLL_1G_DIV5

CCM_OBS_PLL_AUDIO_OUT

CCM_OBS_M7_CLK_ROOT

CCM_OBS_M33_CLK_ROOT

CCM_OBS_EDGELOCK_CLK_ROOT

CCM_OBS_BUS_AON_CLK_ROOT

CCM_OBS_BUS_WAKEUP_CLK_ROOT

CCM_OBS_WAKEUP_AXI_CLK_ROOT

CCM_OBS_SWO_TRACE_CLK_ROOT

CCM_OBS_M33_SYSTICK_CLK_ROOT

CCM_OBS_M7_SYSTICK_CLK_ROOT

CCM_OBS_FLEXIO1_CLK_ROOT

CCM_OBS_FLEXIO2_CLK_ROOT

CCM_OBS_LPIT3_CLK_ROOT

CCM_OBS_LPTMR1_CLK_ROOT

CCM_OBS_LPTMR2_CLK_ROOT

CCM_OBS_LPTMR3_CLK_ROOT

CCM_OBS_TPM2_CLK_ROOT

CCM_OBS_TPM4_CLK_ROOT

CCM_OBS_TPM5_CLK_ROOT

CCM_OBS_TPM6_CLK_ROOT

CCM_OBS_GPT1_CLK_ROOT

CCM_OBS_GPT2_CLK_ROOT

CCM_OBS_FLEXSPI1_CLK_ROOT

CCM_OBS_FLEXSPI2_CLK_ROOT

CCM_OBS_FLEXSPI_SLV_CLK_ROOT

CCM_OBS_CAN1_CLK_ROOT

CCM_OBS_CAN2_CLK_ROOT

CCM_OBS_CAN3_CLK_ROOT

CCM_OBS_LPUART0102_CLK_ROOT

CCM_OBS_LPUART0304_CLK_ROOT

CCM_OBS_LPUART0506_CLK_ROOT

CCM_OBS_LPUART0708_CLK_ROOT

CCM_OBS_LPUART0910_CLK_ROOT

CCM_OBS_LPUART1112_CLK_ROOT

CCM_OBS_LPI2C0102_CLK_ROOT

CCM_OBS_LPI2C0304_CLK_ROOT

CCM_OBS_LPI2C0506_CLK_ROOT

CCM_OBS_LPSPI0102_CLK_ROOT

CCM_OBS_LPSPI0304_CLK_ROOT

CCM_OBS_LPSPI0506_CLK_ROOT

CCM_OBS_I3C1_CLK_ROOT

CCM_OBS_I3C2_CLK_ROOT

CCM_OBS_USDHC1_CLK_ROOT

CCM_OBS_USDHC2_CLK_ROOT

CCM_OBS_SEMC_CLK_ROOT

CCM_OBS_ADC1_CLK_ROOT

CCM_OBS_ADC2_CLK_ROOT

CCM_OBS_ACMP_CLK_ROOT

CCM_OBS_ECAT_CLK_ROOT

CCM_OBS_ENET_REFCLK_ROOT

CCM_OBS_TMR_1588_CLK_ROOT

CCM_OBS_NETC_CLK_ROOT

CCM_OBS_MAC0_CLK_ROOT

CCM_OBS_MAC1_CLK_ROOT

CCM_OBS_MAC2_CLK_ROOT

CCM_OBS_MAC3_CLK_ROOT

CCM_OBS_MAC4_CLK_ROOT

CCM_OBS_SERDES0_CLK_ROOT

CCM_OBS_SERDES1_CLK_ROOT

CCM_OBS_SERDES2_CLK_ROOT

CCM_OBS_SERDES0_1G_CLK_ROOT

CCM_OBS_SERDES1_1G_CLK_ROOT

CCM_OBS_SERDES2_1G_CLK_ROOT

CCM_OBS_XCELBUSX_CLK_ROOT

CCM_OBS_XRIOCU4_CLK_ROOT

CCM_OBS_MOTORCTRL_CLK_ROOT

CCM_OBS_SAI1_CLK_ROOT

CCM_OBS_SAI2_CLK_ROOT

CCM_OBS_SAI3_CLK_ROOT

CCM_OBS_SAI4_CLK_ROOT

CCM_OBS_SPDIF_CLK_ROOT

CCM_OBS_ASRC_CLK_ROOT

CCM_OBS_MIC_CLK_ROOT

CCM_OBS_CCM_CKO1_CLK_ROOT

CCM_OBS_CCM_CKO2_CLK_ROOT

CCM_OBS_DIV

clock_ip_name_t

CLOCK_GetCpuClkFreq

CLOCK_GetCoreSysClkFreq

For compatible with other platforms without CCM.

PLL_PFD_COUNT

static inline uint32_t CLOCK_GetRtcFreq(void)

Gets the RTC clock frequency.

Returns:

Clock frequency; If the clock is invalid, returns 0.

void CLOCK_SetClockSourceControlMode(clock_name_t name, clock_control_mode_t controlMode)

Set the control mode of a specifed clock.

Parameters:

• name – Clock names defined in clock_name_t

• controlMode – The control mode to be set, please refer to clock_control_mode_t.

static inline void CLOCK_OSC_EnableOscRc24M(bool enable)

Enable/disable 24MHz RC oscillator.

Parameters:

• enable – Used to enable or disable the 24MHz RC oscillator.

  • true Enable the 24MHz RC oscillator.

  • false Dissable the 24MHz RC oscillator.

void CLOCK_OSC_EnableOsc24M(void)

Enable OSC 24Mhz.

This function enables OSC 24Mhz.

static inline void CLOCK_OSC_GateOsc24M(bool enableGate)

Gate/ungate the 24MHz crystal oscillator output.

Note

Gating the 24MHz crystal oscillator can save power.

Parameters:

• enableGate – Used to gate/ungate the 24MHz crystal oscillator.

  • true Gate the 24MHz crystal oscillator to save power.

  • false Ungate the 24MHz crystal oscillator.

void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode)

Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.

Parameters:

• workMode – The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

void CLOCK_OSC_EnableOscRc400M(void)

Enable OSC RC 400Mhz.

This function enables OSC RC 400Mhz.

void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim)

Trims OSC RC 400MHz.

Parameters:

• enable – Used to enable trim function.

• bypass – Bypass the trim function.

• trim – Trim value.

void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue)

Set the divide value for ref_clk to generate slow clock.

Note

slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters:

• divValue – The divide value to be set, the available range is 0~63.

void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount)

Set the target count for the fast clock.

Parameters:

• targetCount – The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis)

Set the negative and positive hysteresis value for the tuned clock.

Note

The hysteresis value should be set after the clock is tuned.

Parameters:

• negHysteresis – The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

• posHysteresis – The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass)

Bypass/un-bypass the tune logic.

Parameters:

• enableBypass – Used to control whether to bypass the turn logic.

  • true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.

  • false Use the output of tune logic to run the oscillator.

void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable)

Start/Stop the tune logic.

Parameters:

• enable – Used to start or stop the tune logic.

  • true Start tuning

  • false Stop tuning and reset the tuning logic.

void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze)

Freeze/Unfreeze the tuning value.

Parameters:

• enableFreeze – Used to control whether to freeze the tune value.

  • true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.

  • false Unfreezes and continues the tune operation.

void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue)

Set the 400MHz RC oscillator tune value when the tune logic is disabled.

Parameters:

• tuneValue – The tune value to determine the frequency of Oscillator.

void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior)

Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.

Note

The 1MHz clock is divided from 400M RC Oscillator.

Parameters:

• behavior – The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

void CLOCK_OSC_SetLocked1MHzCount(uint16_t count)

Set the count for the locked 1MHz clock out.

Parameters:

• count – Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void)

Check the error flag for locked 1MHz clock out.

Returns:

The error flag for locked 1MHz clock out.

• true The count value has been reached within one diviced ref clock period

• false No effect.

void CLOCK_OSC_ClearLocked1MHzErrorFlag(void)

Clear the error flag for locked 1MHz clock out.

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void)

Get current count for the fast clock during the tune process.

Returns:

The current count for the fast clock.

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void)

Get current tune value used by oscillator during tune process.

Returns:

The current tune value.

void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)

Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

Parameters:

• config – configuration to set to PLL.

status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Arm PLL

Parameters:

• config – pll config structure

• freqInMhz – target frequency

status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz)

Initializes the Arm PLL with Specific Frequency (in Mhz).

This function initializes the Arm PLL with specific frequency

Parameters:

• freqInMhz – target frequency

void CLOCK_DeinitArmPll(void)

De-initialize the ARM PLL.

void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)

Calculate spread spectrum step and stop.

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/syspll1), the factor is denominator.

Parameters:

• factor – factor to calculate step/stop

• range – spread spectrum range

• mod – spread spectrum modulation frequency

• ss – calculated spread spectrum values

void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config)

Initialize the System PLL1.

This function initializes the System PLL1 with specific settings

Parameters:

• config – Configuration to set to PLL1.

void CLOCK_DeinitSysPll1(void)

De-initialize the System PLL1.

void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config)

Initialize the System PLL2.

This function initializes the System PLL2 with specific settings

Parameters:

• config – Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

void CLOCK_DeinitSysPll2(void)

De-initialize the System PLL2.

bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd)

Check if Sys PLL2 PFD is enabled.

Note

Only useful in software control mode.

Parameters:

• pfd – PFD control name

Returns:

PFD bypass status.

• true: power on.

• false: power off.

void CLOCK_InitSysPll3(void)

Initialize the System PLL3.

This function initializes the System PLL3 with specific settings

void CLOCK_DeinitSysPll3(void)

De-initialize the System PLL3.

bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd)

Check if Sys PLL3 PFD is enabled.

Note

Only useful in software control mode.

Parameters:

• pfd – PFD control name

Returns:

PFD bypass status.

• true: power on.

• false: power off.

void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass)

PLL bypass setting.

Parameters:

• pll – PLL control name (see clock_pll_t enumeration)

• bypass – Bypass the PLL.

  • true: Bypass the PLL.

  • false:Not bypass the PLL.

status_t CLOCK_CalcAudioPllFreq(clock_audio_pll_config_t *config, uint32_t freqInMhz)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Audio PLL.

Parameters:

• config – pll config structure

• freqInMhz – target frequency

status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)

Initializes the Audio PLL with Specific Frequency (in Mhz).

This function initializes the Audio PLL with specific frequency

Parameters:

• freqInMhz – target frequency

• ssEnable – enable spread spectrum or not

• ssRange – range spread spectrum range

• ssMod – spread spectrum modulation frequency

void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)

Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

Parameters:

• config – Configuration to set to PLL.

void CLOCK_DeinitAudioPll(void)

De-initialize the Audio PLL.

uint32_t CLOCK_GetPllFreq(clock_pll_t pll)

Get current PLL output frequency.

This function get current output frequency of specific PLL

Parameters:

• pll – pll name to get frequency.

Returns:

The PLL output frequency in hertz.

void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)

Initialize PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Note

It is recommended that PFD settings are kept between 13-35.

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – Which PFD clock to enable.

• frac – The PFD FRAC value.

void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)

De-initialize selected PLL PFD.

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – Which PFD clock to enable.

uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd)

Get current PFD output frequency.

This function get current output frequency of specific System PLL PFD

Parameters:

• pll – Which PLL of targeting PFD to be operated.

• pfd – pfd name to get frequency.

Returns:

The PFD output frequency in hertz.

uint32_t CLOCK_GetFreqFromObs(uint8_t obsIndex, uint32_t obsSigIndex)

bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters:

• src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.

• freq – USB HS does not care about the clock source, so this parameter is ignored.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters:

• src – USB HS PHY PLL clock source.

• freq – The frequency specified by src.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs0PhyPllClock(void)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters:

• src – USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.

• freq – USB HS does not care about the clock source, so this parameter is ignored.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters:

• src – USB HS PHY PLL clock source.

• freq – The frequency specified by src.

Return values:

• true – The clock is set successfully.

• false – The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs1PhyPllClock(void)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• domainId – Domains that on the whitelist can change this clock.

void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, uint32_t domainMap, clock_level_t level)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock source name, see clock_name_t.

• domainMap – Domains that on the whitelist can change this clock.

• level – Depend level of this clock.

static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock root name, see clock_root_t.

• domainId – Domains that on the whitelist can change this clock.

static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)

Lock the value of Domain ID white list for this clock.

Note

Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)

Set domain ID that can change this clock.

Note

If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• domainId – Domains that on the whitelist can change this clock.

void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, uint32_t domainMap, clock_level_t level)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters:

• name – Clock gate name, see clock_lpcg_t.

• domainMap – Domains that on the whitelist can change this clock.

• level – Depend level of this clock.

static inline void CLOCK_SetClockOutput1(clock_output1_selection_t selection, uint32_t divider)

Set the clock source and the divider of the clock output1.

param selection The clock source to be output, please refer to clock_output1_selection_t. param divider The divider of the output clock signal.

static inline void CLOCK_SetClockOutput2(clock_output2_selection_t selection, uint32_t divider)

Set the clock source and the divider of the clock output2.

param selection The clock source to be output, please refer to clock_output2_selection_t. param divider The divider of the output clock signal.

static inline uint32_t CLOCK_GetClockOutCLKO1Freq(void)

Get the frequency of clock output1 clock signal.

Returns:

The frequency of clock output1 clock signal.

static inline uint32_t CLOCK_GetClockOutClkO2Freq(void)

Get the frequency of clock output2 clock signal.

Returns:

The frequency of clock output2 clock signal.

clock_pll_post_div_t postDivider

Post divider.

uint32_t loopDivider

PLL loop divider. Valid range: 104-208.

uint8_t loopDivider

PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22

uint8_t src

Pll clock source, reference _clock_pll_clk_src

uint16_t stop

Spread spectrum stop value to get frequency change.

uint16_t step

Spread spectrum step value to get frequency change step.

uint32_t mfd

Denominator of spread spectrum

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

bool pllDiv2En

Enable Sys Pll1 divide-by-2 clock or not.

bool pllDiv5En

Enable Sys Pll1 divide-by-5 clock or not.

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

uint8_t loopDivider

PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

uint8_t postDivider

Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.

uint32_t numerator

30 bit numerator of fractional loop divider.

uint32_t denominator

30 bit denominator of fractional loop divider

clock_pll_ss_config_t *ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

bool ssEnable

Enable spread spectrum flag

bool clockOff

uint8_t mux

See clock_root_mux_source_t for details.

uint8_t div

it’s the actual divider

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

struct _clock_arm_pll_config

#include <fsl_clock.h>

PLL configuration for ARM.

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

struct _clock_usb_pll_config

#include <fsl_clock.h>

PLL configuration for USB.

struct _clock_pll_ss_config

#include <fsl_clock.h>

Spread specturm configure Pll.

struct _clock_sys_pll2_config

#include <fsl_clock.h>

PLL configure for Sys Pll2.

struct _clock_sys_pll1_config

#include <fsl_clock.h>

PLL configure for Sys Pll1.

struct _clock_audio_pll_config

#include <fsl_clock.h>

PLL configuration for AUDIO.

struct _clock_root_config_t

#include <fsl_clock.h>

Clock root configuration.

DAC12: 12-bit Digital-to-Analog Converter Driver

void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info)

Get hardware information about this module.

Parameters:

• base – DAC12 peripheral base address.

• info – Pointer to info structure, see to dac12_hardware_info_t.

void DAC12_Init(DAC_Type *base, const dac12_config_t *config)

Initialize the DAC12 module.

Parameters:

• base – DAC12 peripheral base address.

• config – Pointer to configuration structure, see to dac12_config_t.

void DAC12_GetDefaultConfig(dac12_config_t *config)

Initializes the DAC12 user configuration structure.

This function initializes the user configuration structure to a default value. The default values are:

config->fifoWatermarkLevel = 0U;
config->fifoWorkMode = kDAC12_FIFODisabled;
config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1;
config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode;
config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0;
config->speedMode = kDAC12_SpeedLowMode;
config->speedMode = false;
config->currentReferenceInternalTrimValue = 0x4;

Parameters:

• config – Pointer to the configuration structure. See “dac12_config_t”.

void DAC12_Deinit(DAC_Type *base)

De-initialize the DAC12 module.

Parameters:

• base – DAC12 peripheral base address.

static inline void DAC12_Enable(DAC_Type *base, bool enable)

Enable the DAC12’s converter or not.

Parameters:

• base – DAC12 peripheral base address.

• enable – Enable the DAC12’s converter or not.

static inline void DAC12_ResetConfig(DAC_Type *base)

Reset all internal logic and registers.

Parameters:

• base – DAC12 peripheral base address.

static inline void DAC12_ResetFIFO(DAC_Type *base)

Reset the FIFO pointers.

FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers to the same address to reset the FIFO as empty.

Parameters:

• base – DAC12 peripheral base address.

static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base)

Get status flags.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Mask of current status flags. See to _dac12_status_flags.

static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags)

Clear status flags.

Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to target chip’s reference manual document.

Parameters:

• base – DAC12 peripheral base address.

• flags – Mask of status flags to be cleared. See to _dac12_status_flags.

static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – DAC12 peripheral base address.

• mask – Mask value of interrupts to be enabled. See to _dac12_interrupt_enable.

static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – DAC12 peripheral base address.

• mask – Mask value of interrupts to be disabled. See to _dac12_interrupt_enable.

static inline void DAC12_EnableDMA(DAC_Type *base, bool enable)

Enable DMA or not.

When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.

static inline void DAC12_SetData(DAC_Type *base, uint32_t value)

Set data into the entry of FIFO buffer.

When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion without trigger support. When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored into the FIFO buffer.

Parameters:

• base – DAC12 peripheral base address.

• value – Setting value into FIFO buffer.

static inline void DAC12_DoSoftwareTrigger(DAC_Type *base)

Do trigger the FIFO by software.

When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the data in the entry pointed by read pointer would be converted as new output.

Parameters:

• base – DAC12 peripheral base address.

static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base)

Get the current read pointer of FIFO.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Read pointer index of FIFO buffer.

static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base)

Get the current write pointer of FIFO.

Parameters:

• base – DAC12 peripheral base address.

Returns:

Write pointer index of FIFO buffer

FSL_DAC12_DRIVER_VERSION

DAC12 driver version 2.1.2.

enum _dac12_status_flags

DAC12 flags.

Values:

enumerator kDAC12_OverflowFlag

FIFO overflow status flag, which indicates that more data has been written into FIFO than it can hold.

enumerator kDAC12_UnderflowFlag

FIFO underflow status flag, which means that there is a new trigger after the FIFO is nearly empty.

enumerator kDAC12_WatermarkFlag

FIFO wartermark status flag, which indicates the remaining FIFO data is less than the watermark setting.

enumerator kDAC12_NearlyEmptyFlag

FIFO nearly empty flag, which means there is only one data remaining in FIFO.

enumerator kDAC12_FullFlag

FIFO full status flag, which means that the FIFO read pointer equals the write pointer, as the write pointer increase.

enum _dac12_interrupt_enable

DAC12 interrupts.

Values:

enumerator kDAC12_UnderOrOverflowInterruptEnable

Underflow and overflow interrupt enable.

enumerator kDAC12_WatermarkInterruptEnable

Watermark interrupt enable.

enumerator kDAC12_NearlyEmptyInterruptEnable

Nearly empty interrupt enable.

enumerator kDAC12_FullInterruptEnable

Full interrupt enable.

enum _dac12_fifo_size_info

DAC12 FIFO size information provided by hardware.

Values:

enumerator kDAC12_FIFOSize2

FIFO depth is 2.

enumerator kDAC12_FIFOSize4

FIFO depth is 4.

enumerator kDAC12_FIFOSize8

FIFO depth is 8.

enumerator kDAC12_FIFOSize16

FIFO depth is 16.

enumerator kDAC12_FIFOSize32

FIFO depth is 32.

enumerator kDAC12_FIFOSize64

FIFO depth is 64.

enumerator kDAC12_FIFOSize128

FIFO depth is 128.

enumerator kDAC12_FIFOSize256

FIFO depth is 256.

enum _dac12_fifo_work_mode

DAC12 FIFO work mode.

Values:

enumerator kDAC12_FIFODisabled

FIFO disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.

enumerator kDAC12_FIFOWorkAsNormalMode

Data will first read from FIFO to buffer then go to conversion.

enumerator kDAC12_FIFOWorkAsSwingMode

In Swing mode, the FIFO must be set up to be full. In Swing back mode, a trigger changes the read pointer to make it swing between the FIFO Full and Nearly Empty state. That is, the trigger increases the read pointer till FIFO is nearly empty and decreases the read pointer till the FIFO is full.

enum _dac12_reference_voltage_source

DAC12 reference voltage source.

Values:

enumerator kDAC12_ReferenceVoltageSourceAlt1

The DAC selects DACREF_1 as the reference voltage.

enumerator kDAC12_ReferenceVoltageSourceAlt2

The DAC selects DACREF_2 as the reference voltage.

enum _dac12_fifo_trigger_mode

DAC12 FIFO trigger mode.

Values:

enumerator kDAC12_FIFOTriggerByHardwareMode

Buffer would be triggered by hardware.

enumerator kDAC12_FIFOTriggerBySoftwareMode

Buffer would be triggered by software.

enum _dac12_reference_current_source

DAC internal reference current source.

Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.

Values:

enumerator kDAC12_ReferenceCurrentSourceDisabled

None of reference current source is enabled.

enumerator kDAC12_ReferenceCurrentSourceAlt0

Use the internal reference current generated by the module itself.

enumerator kDAC12_ReferenceCurrentSourceAlt1

Use the ZTC(Zero Temperature Coefficient) reference current generated by on-chip power management module.

enumerator kDAC12_ReferenceCurrentSourceAlt2

Use the PTAT(Proportional To Absolution Temperature) reference current generated by power management module.

enum _dac12_speed_mode

DAC analog buffer speed mode for conversion.

Values:

enumerator kDAC12_SpeedLowMode

Low speed mode.

enumerator kDAC12_SpeedMiddleMode

Middle speed mode.

enumerator kDAC12_SpeedHighMode

High speed mode.

typedef enum _dac12_fifo_size_info dac12_fifo_size_info_t

DAC12 FIFO size information provided by hardware.

typedef enum _dac12_fifo_work_mode dac12_fifo_work_mode_t

DAC12 FIFO work mode.

typedef enum _dac12_reference_voltage_source dac12_reference_voltage_source_t

DAC12 reference voltage source.

typedef enum _dac12_fifo_trigger_mode dac12_fifo_trigger_mode_t

DAC12 FIFO trigger mode.

typedef enum _dac12_reference_current_source dac12_reference_current_source_t

DAC internal reference current source.

Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by on-chip PMC’s “reference part”. If no current reference be selected, analog module can’t working normally ,even when other register can still be assigned, DAC would waste current but no function. To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.

typedef enum _dac12_speed_mode dac12_speed_mode_t

DAC analog buffer speed mode for conversion.

typedef struct _dac12_hardware_info dac12_hardware_info_t

DAC12 hardware information.

DAC12_CR_W1C_FLAGS_MASK

Define “write 1 to clear” flags.

DAC12_CR_ALL_FLAGS_MASK

Define all the flag bits in DACx_CR register.

struct _dac12_hardware_info

#include <fsl_dac12.h>

DAC12 hardware information.

Public Members

dac12_fifo_size_info_t fifoSizeInfo

The number of words in this device’s DAC buffer.

struct dac12_config_t

#include <fsl_dac12.h>

DAC12 module configuration.

Actually, the most fields are for FIFO buffer.

Public Members

uint32_t fifoWatermarkLevel

FIFO’s watermark, the max value can be the hardware FIFO size.

dac12_fifo_work_mode_t fifoWorkMode

FIFI’s work mode about pointers.

dac12_reference_voltage_source_t referenceVoltageSource

Select the reference voltage source.

dac12_reference_current_source_t referenceCurrentSource

Select the trigger mode for FIFO. Select the reference current source.

dac12_speed_mode_t speedMode

Select the speed mode for conversion.

bool enableAnalogBuffer

Enable analog buffer for high drive.

Dcdc_soc

void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)

Initializes the basic resource of DCDC module, such as control mode, etc.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to the dcdc_config_t structure.

void DCDC_Deinit(DCDC_Type *base)

De-initializes the DCDC module.

Parameters:

• base – DCDC peripheral base address.

void DCDC_GetDefaultConfig(dcdc_config_t *config)

Gets the default setting for DCDC, such as control mode, etc.

This function initializes the user configuration structure to a default value. The default values are:

config->controlMode                    = kDCDC_StaticControl;
config->trimInputMode                  = kDCDC_SampleTrimInput;
config->enableDcdcTimeout              = false;
config->enableSwitchingConverterOutput = false;

Parameters:

• config – Pointer to configuration structure. See to dcdc_config_t.

static inline void DCDC_SetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)

static inline uint16_t DCDC_GetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P0 in low power mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P0’s voltage value in low power mode and the unit is “mV”.

static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enable)

static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)

Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• core – Core for DCDC to control.

• targetVoltage – The target value of VDD1P0 in buck mode, see dcdc_1P0_target_vol_t.

static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P0 in buck mode, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P0’s voltage value in buck mode and the unit is “mV”.

static inline void DCDC_GPC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)

static inline void DCDC_GPC_SetVDD1P0LowPowerModeTargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P0_target_vol_t targetVoltage)

Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in low power mode, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• core – Core for DCDC to control.

• targetVoltage – The target value of VDD1P0 in low power mode, see dcdc_1P0_target_vol_t.

static inline void DCDC_GPC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enable)

Enable VDD1P0 in low power mode.

Parameters:

• base – DCDC peripheral base address.

• core – Core for DCDC to control.

• enable – Enable the output or not.

static inline void DCDC_SetVDD1P8TargetVoltage(DCDC_Type *base, dcdc_core_slice_t core, dcdc_1P8_target_vol_t targetVoltage)

Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8, 25mV each step.

Parameters:

• base – DCDC peripheral base address.

• core – Core for DCDC to control.

• targetVoltage – The target value of VDD1P8, see dcdc_1P8_target_vol_t.

static inline uint16_t DCDC_GetVDD1P8TargetVoltage(DCDC_Type *base)

Gets the target value of VDD1P8, the result takes “mV” as the unit.

Parameters:

• base – DCDC peripheral base address.

Returns:

The VDD1P8’s voltage value and the unit is “mV”.

static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)

Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be disabled.

Parameters:

• base – DCDC peripheral base address.

• enable – Used to control the behavior.

  • true Enables stepping for VDD1P0.

  • false Disables stepping for VDD1P0.

void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)

Gets the default setting for detection configuration.

The default configuration are set according to responding registers’ setting when powered on. They are:

config->enableXtalokDetection = false;
config->powerDownOverVoltageVdd1P8Detection = true;
config->powerDownOverVoltageVdd1P0Detection = true;
config->powerDownLowVoltageDetection  = false;
config->powerDownOverCurrentDetection = true;
config->powerDownPeakCurrentDetection = true;
config->powerDownZeroCrossDetection   = true;
config->OverCurrentThreshold          = kDCDC_OverCurrentThresholdAlt0;
config->PeakCurrentThreshold          = kDCDC_PeakCurrentThresholdAlt0;

Parameters:

• config – Pointer to configuration structure. See to dcdc_detection_config_t.

void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)

Configures the DCDC detection.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_detection_config_t.

void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)

Configures the DCDC clock source.

Parameters:

• base – DCDC peripheral base address.

• clockSource – Clock source for DCDC. See to dcdc_clock_source_t.

static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)

Sets the bangap trim value(0~31) to trim bandgap voltage.

Parameters:

• base – DCDC peripheral base address.

• trimValue – The bangap trim value. Available range is 0U-31U.

void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)

Gets the default setting for loop control configuration.

The default configuration are set according to responding registers’ setting when powered on. They are:

config->enableCommonHysteresis = false;
config->enableCommonThresholdDetection = false;
config->enableInvertHysteresisSign = false;
config->enableRCThresholdDetection = false;
config->enableRCScaleCircuit = 0U;
config->complementFeedForwardStep = 0U;
config->controlParameterMagnitude = 2U;
config->integralProportionalRatio = 2U;

Parameters:

• config – Pointer to configuration structure. See to dcdc_loop_control_config_t.

void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)

Configures the DCDC loop control.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_loop_control_config_t.

void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)

Configures the DCDC internal regulator.

Parameters:

• base – DCDC peripheral base address.

• config – Pointer to configuration structure. See to dcdc_internal_regulator_config_t.

static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)

Adjusts delay to reduce ground noise.

Parameters:

• base – DCDC peripheral base address.

• enable – Enable the feature or not.

static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)

Get DCDC status flags.

Parameters:

• base – peripheral base address.

Returns:

Mask of asserted status flags. See to _dcdc_status_flags.

void DCDC_BootIntoCCM(DCDC_Type *base)

Boots DCDC into CCM(continous conduction mode).

pwd_zcd=0x1;
pwd_cmp_offset=0x0;
dcdc_loopctrl_en_rcscale=0x3;

Parameters:

• base – DCDC peripheral base address.

enum _dcdc_status_flags

The enumeration of DCDC status flags.

Values:

enumerator kDCDC_AlreadySettledStatusFlag

Indicate DCDC status. 1’b1: DCDC already settled 1’b0: DCDC is settling.

enum _dcdc_core_slice

CORE slice.

Values:

enumerator kDCDC_CORE0

CORE slice 0.

enumerator kDCDC_CORE1

CORE slice 1.

enum _dcdc_control_mode

DCDC control mode, including software control mode and GPC control mode.

Values:

enumerator kDCDC_SoftwareControl

Controlled by software.

enumerator kDCDC_GPCControl

Controlled by GPC.

enum _dcdc_trim_input_mode

DCDC trim input mode, including sample trim input and hold trim input.

Values:

enumerator kDCDC_SampleTrimInput

Sample trim input.

enumerator kDCDC_HoldTrimInput

Hold trim input.

enum _dcdc_1P0_target_vol

The enumeration VDD1P0’s target voltage value.

Values:

enumerator kDCDC_1P0Target0P6V

The target voltage value of VDD1P0 is 0.6V.

enumerator kDCDC_1P0Target0P625V

The target voltage value of VDD1P0 is 0.625V.

enumerator kDCDC_1P0Target0P65V

The target voltage value of VDD1P0 is 0.65V.

enumerator kDCDC_1P0Target0P675V

The target voltage value of VDD1P0 is 0.675V.

enumerator kDCDC_1P0Target0P7V

The target voltage value of VDD1P0 is 0.7V.

enumerator kDCDC_1P0Target0P725V

The target voltage value of VDD1P0 is 0.725V.

enumerator kDCDC_1P0Target0P75V

The target voltage value of VDD1P0 is 0.75V.

enumerator kDCDC_1P0Target0P775V

The target voltage value of VDD1P0 is 0.775V.

enumerator kDCDC_1P0Target0P8V

The target voltage value of VDD1P0 is 0.8V.

enumerator kDCDC_1P0Target0P825V

The target voltage value of VDD1P0 is 0.825V.

enumerator kDCDC_1P0Target0P85V

The target voltage value of VDD1P0 is 0.85V.

enumerator kDCDC_1P0Target0P875V

The target voltage value of VDD1P0 is 0.875V.

enumerator kDCDC_1P0Target0P9V

The target voltage value of VDD1P0 is 0.9V.

enumerator kDCDC_1P0Target0P925V

The target voltage value of VDD1P0 is 0.925V.

enumerator kDCDC_1P0Target0P95V

The target voltage value of VDD1P0 is 0.95V.

enumerator kDCDC_1P0Target0P975V

The target voltage value of VDD1P0 is 0.975V.

enumerator kDCDC_1P0Target1P0V

The target voltage value of VDD1P0 is 1.0V.

enumerator kDCDC_1P0Target1P025V

The target voltage value of VDD1P0 is 1.025V.

enumerator kDCDC_1P0Target1P05V

The target voltage value of VDD1P0 is 1.05V.

enumerator kDCDC_1P0Target1P075V

The target voltage value of VDD1P0 is 1.075V.

enumerator kDCDC_1P0Target1P1V

The target voltage value of VDD1P0 is 1.1V.

enumerator kDCDC_1P0Target1P125V

The target voltage value of VDD1P0 is 1.125V.

enumerator kDCDC_1P0Target1P15V

The target voltage value of VDD1P0 is 1.15V.

enumerator kDCDC_1P0Target1P175V

The target voltage value of VDD1P0 is 1.175V.

enumerator kDCDC_1P0Target1P2V

The target voltage value of VDD1P0 is 1.2V.

enumerator kDCDC_1P0Target1P225V

The target voltage value of VDD1P0 is 1.225V.

enumerator kDCDC_1P0Target1P25V

The target voltage value of VDD1P0 is 1.25V.

enumerator kDCDC_1P0Target1P275V

The target voltage value of VDD1P0 is 1.275V.

enumerator kDCDC_1P0Target1P3V

The target voltage value of VDD1P0 is 1.3V.

enumerator kDCDC_1P0Target1P325V

The target voltage value of VDD1P0 is 1.325V.

enumerator kDCDC_1P0Target1P35V

The target voltage value of VDD1P0 is 1.35V.

enumerator kDCDC_1P0Target1P375V

The target voltage value of VDD1P0 is 1.375V.

enum _dcdc_1P8_target_vol

The enumeration VDD1P8’s target voltage value.

Values:

enumerator kDCDC_1P8Target1P5V

The target voltage value of VDD1P8 is 1.5V.

enumerator kDCDC_1P8Target1P525V

The target voltage value of VDD1P8 is 1.525V.

enumerator kDCDC_1P8Target1P55V

The target voltage value of VDD1P8 is 1.55V.

enumerator kDCDC_1P8Target1P575V

The target voltage value of VDD1P8 is 1.575V.

enumerator kDCDC_1P8Target1P6V

The target voltage value of VDD1P8 is 1.6V.

enumerator kDCDC_1P8Target1P625V

The target voltage value of VDD1P8 is 1.625V.

enumerator kDCDC_1P8Target1P65V

The target voltage value of VDD1P8 is 1.65V.

enumerator kDCDC_1P8Target1P675V

The target voltage value of VDD1P8 is 1.675V.

enumerator kDCDC_1P8Target1P7V

The target voltage value of VDD1P8 is 1.7V.

enumerator kDCDC_1P8Target1P725V

The target voltage value of VDD1P8 is 1.725V.

enumerator kDCDC_1P8Target1P75V

The target voltage value of VDD1P8 is 1.75V.

enumerator kDCDC_1P8Target1P775V

The target voltage value of VDD1P8 is 1.775V.

enumerator kDCDC_1P8Target1P8V

The target voltage value of VDD1P8 is 1.8V.

enumerator kDCDC_1P8Target1P825V

The target voltage value of VDD1P8 is 1.825V.

enumerator kDCDC_1P8Target1P85V

The target voltage value of VDD1P8 is 1.85V.

enumerator kDCDC_1P8Target1P875V

The target voltage value of VDD1P8 is 1.875V.

enumerator kDCDC_1P8Target1P9V

The target voltage value of VDD1P8 is 1.9V.

enumerator kDCDC_1P8Target1P925V

The target voltage value of VDD1P8 is 1.925V.

enumerator kDCDC_1P8Target1P95V

The target voltage value of VDD1P8 is 1.95V.

enumerator kDCDC_1P8Target1P975V

The target voltage value of VDD1P8 is 1.975V.

enumerator kDCDC_1P8Target2P0V

The target voltage value of VDD1P8 is 2.0V.

enumerator kDCDC_1P8Target2P025V

The target voltage value of VDD1P8 is 2.025V.

enumerator kDCDC_1P8Target2P05V

The target voltage value of VDD1P8 is 2.05V.

enumerator kDCDC_1P8Target2P075V

The target voltage value of VDD1P8 is 2.075V.

enumerator kDCDC_1P8Target2P1V

The target voltage value of VDD1P8 is 2.1V.

enumerator kDCDC_1P8Target2P125V

The target voltage value of VDD1P8 is 2.125V.

enumerator kDCDC_1P8Target2P15V

The target voltage value of VDD1P8 is 2.15V.

enumerator kDCDC_1P8Target2P175V

The target voltage value of VDD1P8 is 2.175V.

enumerator kDCDC_1P8Target2P2V

The target voltage value of VDD1P8 is 2.2V.

enumerator kDCDC_1P8Target2P225V

The target voltage value of VDD1P8 is 2.225V.

enumerator kDCDC_1P8Target2P25V

The target voltage value of VDD1P8 is 2.25V.

enumerator kDCDC_1P8Target2P275V

The target voltage value of VDD1P8 is 2.275V.

enum _dcdc_comparator_current_bias

The current bias of low power comparator.

Values:

enumerator kDCDC_ComparatorCurrentBias50nA

The current bias of low power comparator is 50nA.

enumerator kDCDC_ComparatorCurrentBias100nA

The current bias of low power comparator is 100nA.

enumerator kDCDC_ComparatorCurrentBias200nA

The current bias of low power comparator is 200nA.

enumerator kDCDC_ComparatorCurrentBias400nA

The current bias of low power comparator is 400nA.

enum _dcdc_peak_current_threshold

The threshold if peak current detection.

Values:

enumerator kDCDC_PeakCurrentRunMode250mALPMode1P5A

Over peak current threshold in low power mode is 250mA, in run mode is 1.5A

enumerator kDCDC_PeakCurrentRunMode200mALPMode1P5A

Over peak current threshold in low power mode is 200mA, in run mode is 1.5A

enumerator kDCDC_PeakCurrentRunMode250mALPMode2A

Over peak current threshold in low power mode is 250mA, in run mode is 2A

enumerator kDCDC_PeakCurrentRunMode200mALPMode2A

Over peak current threshold in low power mode is 200mA, in run mode is 2A

enum _dcdc_clock_source

Oscillator clock option.

Values:

enumerator kDCDC_ClockAutoSwitch

Automatic clock switch from internal oscillator to external clock.

enumerator kDCDC_ClockInternalOsc

Use internal oscillator.

enumerator kDCDC_ClockExternalOsc

Use external 24M crystal oscillator.

enum _dcdc_voltage_output_sel

Voltage output option.

Values:

enumerator kDCDC_VoltageOutput1P8

1.8V output.

enumerator kDCDC_VoltageOutput1P0

1.0V output.

typedef enum _dcdc_core_slice dcdc_core_slice_t

CORE slice.

typedef enum _dcdc_control_mode dcdc_control_mode_t

DCDC control mode, including software control mode and GPC control mode.

typedef enum _dcdc_trim_input_mode dcdc_trim_input_mode_t

DCDC trim input mode, including sample trim input and hold trim input.

typedef enum _dcdc_1P0_target_vol dcdc_1P0_target_vol_t

The enumeration VDD1P0’s target voltage value.

typedef enum _dcdc_1P8_target_vol dcdc_1P8_target_vol_t

The enumeration VDD1P8’s target voltage value.

typedef enum _dcdc_comparator_current_bias dcdc_comparator_current_bias_t

The current bias of low power comparator.

typedef enum _dcdc_peak_current_threshold dcdc_peak_current_threshold_t

The threshold if peak current detection.

typedef enum _dcdc_clock_source dcdc_clock_source_t

Oscillator clock option.

typedef enum _dcdc_voltage_output_sel dcdc_voltage_output_sel_t

Voltage output option.

typedef struct _dcdc_config dcdc_config_t

Configuration for DCDC.

typedef struct _dcdc_min_power_config dcdc_min_power_config_t

Configuration for min power setting.

typedef struct _dcdc_detection_config dcdc_detection_config_t

Configuration for DCDC detection.

typedef struct _dcdc_loop_control_config dcdc_loop_control_config_t

Configuration for the loop control.

typedef struct _dcdc_internal_regulator_config dcdc_internal_regulator_config_t

Configuration for DCDC internal regulator.

FSL_DCDC_DRIVER_VERSION

DCDC driver version.

Version 2.0.1.

VDD1P0_TARGET_VOLTAGE

The array of VDD1P0 target voltage.

VDD1P8_TARGET_VOLTAGE

The array of VDD1P8 target voltage.

struct _dcdc_config

#include <fsl_dcdc.h>

Configuration for DCDC.

Public Members

dcdc_control_mode_t controlMode

DCDC control mode.

dcdc_trim_input_mode_t trimInputMode

Hold trim input.

struct _dcdc_min_power_config

#include <fsl_dcdc.h>

Configuration for min power setting.

Public Members

bool enableUseHalfFreqForContinuous

Set DCDC clock to half frequency for the continuous mode.

struct _dcdc_detection_config

#include <fsl_dcdc.h>

Configuration for DCDC detection.

Public Members

bool enableXtalokDetection

Enable xtalok detection circuit.

bool powerDownOverVoltageVdd1P8Detection

Power down over-voltage detection comparator for VDD1P8.

bool powerDownOverVoltageVdd1P0Detection

Power down over-voltage detection comparator for VDD1P0.

bool powerDownLowVoltageDetection

Power down low-voltage detection comparator.

bool powerDownOverCurrentDetection

Power down over-current detection.

struct _dcdc_loop_control_config

#include <fsl_dcdc.h>

Configuration for the loop control.

Public Members

bool enableCommonHysteresis

Enable hysteresis in switching converter common mode analog comparators. This feature will improve transient supply ripple and efficiency.

bool enableCommonThresholdDetection

Increase the threshold detection for common mode analog comparator.

bool enableDifferentialHysteresis

Enable hysteresis in switching converter differential mode analog comparators. This feature will improve transient supply ripple and efficiency.

bool enableDifferentialThresholdDetection

Increase the threshold detection for differential mode analog comparators.

bool enableInvertHysteresisSign

Invert the sign of the hysteresis in DC-DC analog comparators.

bool enableRCThresholdDetection

Increase the threshold detection for RC scale circuit.

uint32_t enableRCScaleCircuit

Available range is 0~7. Enable analog circuit of DC-DC converter to respond faster under transient load conditions.

uint32_t complementFeedForwardStep

Available range is 0~7. Two’s complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional to the change. This can be used to force a certain control loop behavior, such as improving response under known heavy load transients.

uint32_t controlParameterMagnitude

Available range is 0~15. Magnitude of proportional control parameter in the switching DC-DC converter control loop.

uint32_t integralProportionalRatio

Available range is 0~3.Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response.

struct _dcdc_internal_regulator_config

#include <fsl_dcdc.h>

Configuration for DCDC internal regulator.

Public Members

uint32_t feedbackPoint

Available range is 0~3. Select the feedback point of the internal regulator.

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

• base – eDMA peripheral base address.

• config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

• base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

• base – EDMA peripheral base address.

• channel – EDMA channel number.

• tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

• config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)

EDMA Channel initialization.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)

Set channel memory attribute.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• writeAttribute – Attributes associated with a write transaction.

• readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)

Set channel sign extension.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)

Set channel swap size.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)

Set channel access type.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)

Set channel request source.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)

Gets the channel identification and attribute information on the system bus interface.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)

Set channel master ID replication.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)

Set channel security level.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number

• config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• type – A channel link type, which can be one of the following:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an async request for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• base – eDMA peripheral base address.

• channel – edma channel number.

• sourceOffset – source address offset will be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

• For the platform has cache, the software TCD should be put in non cache section

• The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

• tcd – Pointer to the TCD structure.

• transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

• tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

• tcd – Pointer to the TCD structure.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

• tcd – A point to the TCD structure.

• config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• tcd – Point to the TCD structure.

• type – Channel link type, it can be one of:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• tcd – A pointer to the TCD structure.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• tcd – A pointer to the TCD structure.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• tcd – A pointer to the TCD structure.

• enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• tcd – A point to the TCD structure.

• sourceOffset – source address offset wiil be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

• For the platform has cache, the software TCD should be put in non cache section

• The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

• transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

• base – eDMA peripheral base address.

• tcd – A point to the TCD structure.

• config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• type – Channel link type, it can be one of:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• base – eDMA peripheral base address.

• tcd – A point to the TCD structure.

• sourceOffset – source address offset wiil be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

1. The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

• base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

• handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Return values:

• kStatus_Success –

• kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

• handle – eDMA handle pointer.

• tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.

• tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

• handle – eDMA handle pointer.

• callback – eDMA callback function pointer.

• userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• srcOffset – source address offset.

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• destOffset – destination address offset.

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

• type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• handle – eDMA handle pointer.

• tcd – Pointer to eDMA transfer content descriptor structure.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• srcOffset – source address offset.

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• destOffset – destination address offset.

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

• nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

1. submit single transfer

   edma_tcd_t tcd;
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_StartTransfer(handle)
   

2. submit static link transfer,

   edma_tcd_t tcd[2];
   EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
   EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
   EDMA_SubmitTransferTCD(handle, &tcd[0])
   EDMA_StartTransfer(handle)
   

3. submit dynamic link transfer

   edma_tcd_t tcdpool[2];
   EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
   edma_tcd_t tcd;
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_StartTransfer(handle)
   

4. submit loop transfer

   edma_tcd_t tcd[2];
   EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
   EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
   EDMA_SubmitTransferTCD(handle, &tcd[0])
   EDMA_StartTransfer(handle)
   

Parameters:

• handle – eDMA handle pointer.

• tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

• kStatus_EDMA_Success – It means submit transfer request succeed.

• kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.

• kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

• handle – eDMA handle pointer.

• config – Pointer to eDMA transfer configuration structure.

Return values:

• kStatus_EDMA_Success – It means submit transfer request succeed.

• kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.

• kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

• handle – eDMA handle pointer

• transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail

• transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

• kStatus_Success – It means submit transfer request succeed

• kStatus_EDMA_Busy – channel is in busy status

• kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

• handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

• handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

• handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

• handle – eDMA handle pointer.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.10.7.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull

TCD queue is full.

enumerator kStatus_EDMA_Busy

Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes

Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes

Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes

Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes

Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable

Disable modulo

enumerator kEDMA_Modulo2bytes

Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes

Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes

Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes

Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes

Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes

Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes

Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes

Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes

Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes

Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes

Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes

Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes

Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes

Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes

Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes

Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes

Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes

Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes

Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes

Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes

Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes

Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes

Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes

Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes

Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes

Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes

Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes

Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes

Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes

Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes

Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone

No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle

eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle

eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone

No channel link

enumerator kEDMA_MinorLink

Channel link after each minor loop

enumerator kEDMA_MajorLink

Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag

DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag

eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag

eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag

Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag

Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag

Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag

NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag

Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag

Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag

Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag

Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag

Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag

Transfer cancelled

enumerator kEDMA_ValidFlag

No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable

Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable

Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable

Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory

Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory

Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral

Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral

Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer

No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable

No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer

No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable

No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer

No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable

No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer

No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable

No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer

write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable

write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer

write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable

write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer

write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable

write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer

write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable

write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled

Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap

Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap

Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap

Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap

Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap

Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap

Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel

Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId

DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess

Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess

Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser

user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged

Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t

eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t

eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t

Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t

Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t

eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t

eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t

eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t

eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t

eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t

eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t

eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t

eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0

2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width

3. the totalBytes should align with the bytesEachRequest

4. the srcAddr should align with the srcWidthOfEachTransfer

5. the dstAddr should align with the dstWidthOfEachTransfer

6. the srcAddr should align with srcAddrModulo if modulo feature is enabled

7. the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

typedef struct _edma_config edma_config_t

eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:

EDMA handle pointer, users shall not touch the values inside.

Param userData:

The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.

Param transferDone:

If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.

Param tcds:

How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t

eDMA transfer handle structure

FSL_EDMA_DRIVER_EDMA4

eDMA driver name

EDMA_ALLOCATE_TCD(name, number)

Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel)

Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption

If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility

If true: a channel can suspend other channel with low priority

uint8_t channelPriority

Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset

Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset

Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset

Offset for a minor loop mapping.

struct _edma_channel_config

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig

channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute

channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute

channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize

channel swap size configuration

edma_channel_access_type_t channelAccessType

channel access type configuration

uint8_t channelDataSignExtensionBitPosition

channel data sign extension bit psition configuration

uint32_t channelRequestSource

hardware service request source for the channel

bool enableMasterIDReplication

enable master ID replication

edma_channel_protection_level_t protectionLevel

protection level

struct _edma_transfer_config

#include <fsl_edma.h>

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0

2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width

3. the totalBytes should align with the bytesEachRequest

4. the srcAddr should align with the srcWidthOfEachTransfer

5. the dstAddr should align with the dstWidthOfEachTransfer

6. the srcAddr should align with srcAddrModulo if modulo feature is enabled

7. the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

Public Members

uint32_t srcAddr

Source data address.

uint32_t destAddr

Destination data address.

edma_transfer_size_t srcTransferSize

Source data transfer size.

edma_transfer_size_t destTransferSize

Destination data transfer size.

int16_t srcOffset

Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset

Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes

bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts

minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask

channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo

source circular data queue range

int32_t srcMajorLoopOffset

source major loop offset

edma_modulo_t dstAddrModulo

destination circular data queue range

int32_t dstMajorLoopOffset

destination major loop offset

bool enableSrcMinorLoopOffset

enable source minor loop offset

bool enableDstMinorLoopOffset

enable dest minor loop offset

int32_t minorLoopOffset

burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink

channel link when major loop complete

uint32_t majorLoopLinkChannel

major loop link channel number

bool enableChannelMinorLoopLink

channel link when minor loop complete

uint32_t minorLoopLinkChannel

minor loop link channel number

edma_tcd_t *linkTCD

pointer to the link transfer control descriptor

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableContinuousLinkMode

Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.

bool enableMasterIdReplication

Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink

Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError

Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode

Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration

Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]

channel preemption configuration

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback

Callback function for major count exhausted.

void *userData

Callback function parameter.

EDMA_ChannelType *channelBase

eDMA peripheral channel base address.

EDMA_Type *base

eDMA peripheral base address

EDMA_TCDType *tcdBase

eDMA peripheral tcd base address.

edma_tcd_t *tcdPool

Pointer to memory stored TCDs.

uint32_t channel

eDMA channel number.

volatile int8_t header

The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail

The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed

The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize

The total number of TCD slots in the queue.

eDMA core Driver

enum _edma_tcd_type

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag

Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag

Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t

edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t

edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t

eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t

edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t

edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t

edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType

EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType

typedef void EDMA_Type

DMA_CORE_MP_CSR_EDBG_MASK

DMA_CORE_MP_CSR_ERCA_MASK

DMA_CORE_MP_CSR_HAE_MASK

DMA_CORE_MP_CSR_HALT_MASK

DMA_CORE_MP_CSR_GCLC_MASK

DMA_CORE_MP_CSR_GMRC_MASK

DMA_CORE_MP_CSR_EDBG(x)

DMA_CORE_MP_CSR_ERCA(x)

DMA_CORE_MP_CSR_HAE(x)

DMA_CORE_MP_CSR_HALT(x)

DMA_CORE_MP_CSR_GCLC(x)

DMA_CORE_MP_CSR_GMRC(x)

DMA_CSR_INTMAJOR_MASK

DMA_CSR_INTHALF_MASK

DMA_CSR_DREQ_MASK

DMA_CSR_ESG_MASK

DMA_CSR_BWC_MASK

DMA_CSR_BWC(x)

DMA_CSR_START_MASK

DMA_CITER_ELINKNO_CITER_MASK

DMA_BITER_ELINKNO_BITER_MASK

DMA_CITER_ELINKNO_CITER_SHIFT

DMA_CITER_ELINKYES_CITER_MASK

DMA_CITER_ELINKYES_CITER_SHIFT

DMA_ATTR_SMOD_MASK

DMA_ATTR_DMOD_MASK

DMA_CITER_ELINKNO_ELINK_MASK

DMA_CSR_MAJORELINK_MASK

DMA_BITER_ELINKYES_ELINK_MASK

DMA_CITER_ELINKYES_ELINK_MASK

DMA_CSR_MAJORLINKCH_MASK

DMA_BITER_ELINKYES_LINKCH_MASK

DMA_CITER_ELINKYES_LINKCH_MASK

DMA_NBYTES_MLOFFYES_MLOFF_MASK

DMA_NBYTES_MLOFFYES_DMLOE_MASK

DMA_NBYTES_MLOFFYES_SMLOE_MASK

DMA_NBYTES_MLOFFNO_NBYTES_MASK

DMA_ATTR_DMOD(x)

DMA_ATTR_SMOD(x)

DMA_BITER_ELINKYES_LINKCH(x)

DMA_CITER_ELINKYES_LINKCH(x)

DMA_NBYTES_MLOFFYES_MLOFF(x)

DMA_NBYTES_MLOFFYES_DMLOE(x)

DMA_NBYTES_MLOFFYES_SMLOE(x)

DMA_NBYTES_MLOFFNO_NBYTES(x)

DMA_NBYTES_MLOFFYES_NBYTES(x)

DMA_ATTR_DSIZE(x)

DMA_ATTR_SSIZE(x)

DMA_CSR_DREQ(x)

DMA_CSR_MAJORLINKCH(x)

DMA_CH_MATTR_WCACHE(x)

DMA_CH_MATTR_RCACHE(x)

DMA_CH_CSR_SIGNEXT_MASK

DMA_CH_CSR_SIGNEXT_SHIFT

DMA_CH_CSR_SWAP_MASK

DMA_CH_CSR_SWAP_SHIFT

DMA_CH_SBR_INSTR_MASK

DMA_CH_SBR_INSTR_SHIFT

DMA_CH_SBR_EMI_MASK

DMA_CH_SBR_EMI_SHIFT

DMA_CH_MUX_SOURCE(x)

DMA_ERR_DBE_FLAG

DMA error flag.

DMA_ERR_SBE_FLAG

DMA_ERR_SGE_FLAG

DMA_ERR_NCE_FLAG

DMA_ERR_DOE_FLAG

DMA_ERR_DAE_FLAG

DMA_ERR_SOE_FLAG

DMA_ERR_SAE_FLAG

DMA_ERR_ERRCHAN_FLAG

DMA_ERR_ECX_FLAG

DMA_ERR_FLAG

DMA_CLEAR_DONE_STATUS(base, channel)

get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)

DMA_ENABLE_ERROR_INT(base, channel)

enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)

DMA_CLEAR_ERROR_STATUS(base, channel)

get/clear error status

DMA_GET_ERROR_STATUS(base, channel)

DMA_CLEAR_INT_STATUS(base, channel)

get/clear INT status

DMA_GET_INT_STATUS(base, channel)

DMA_ENABLE_MAJOR_INT(base, channel)

enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)

DMA_DISABLE_MAJOR_INT(base, channel)

DMA_DISABLE_HALF_INT(base, channel)

EDMA_TCD_ALIGN_SIZE

EDMA tcd align size.

EDMA_CORE_BASE(base)

EDMA base address convert macro.

EDMA_MP_BASE(base)

EDMA_CHANNEL_BASE(base, channel)

EDMA_TCD_BASE(base, channel)

EDMA_TCD_TYPE(x)

EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag)

EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)

EDMA_TCD_ATTR(tcd, flag)

EDMA_TCD_NBYTES(tcd, flag)

EDMA_TCD_SLAST(tcd, flag)

EDMA_TCD_DADDR(tcd, flag)

EDMA_TCD_DOFF(tcd, flag)

EDMA_TCD_CITER(tcd, flag)

EDMA_TCD_DLAST_SGA(tcd, flag)

EDMA_TCD_CSR(tcd, flag)

EDMA_TCD_BITER(tcd, flag)

struct _edma_core_mp

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT

Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR

Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI

Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR

SADDR register, used to save source address

__IO uint32_t SADDR_HIGH

SADDR HIGH register, used to save source address

__IO uint16_t SOFF

SOFF register, save offset bytes every transfer

__IO uint16_t ATTR

ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES

Nbytes register, minor loop length in bytes

__IO uint32_t SLAST

SLAST register

__IO uint32_t SLAST_SDA_HIGH

SLAST SDA HIGH register

__IO uint32_t DADDR

DADDR register, used for destination address

__IO uint32_t DADDR_HIGH

DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH

DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF

DOFF register, used for destination offset

__IO uint16_t CITER

CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR

CSR register, for TCD control status

__IO uint16_t BITER

BITER register, begin minor loop count.

uint8_t RESERVED[16]

Aligned 64 bytes

struct _edma4_core_tcd

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR

SADDR register, used to save source address

__IO uint16_t SOFF

SOFF register, save offset bytes every transfer

__IO uint16_t ATTR

ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES

Nbytes register, minor loop length in bytes

__IO uint32_t SLAST

SLAST register

__IO uint32_t DADDR

DADDR register, used for destination address

__IO uint16_t DOFF

DOFF register, used for destination offset

__IO uint16_t CITER

CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR

CSR register, for TCD control status

__IO uint16_t BITER

BITER register, begin minor loop count.

struct _edma_core_tcd

#include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS

Public Members

struct _edma_core_mp EDMA5_REG

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW

Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH

Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW

Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH

Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH

Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW

Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH

Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]

Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]

Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]

Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS

Public Members

struct _edma_core_channel EDMA5_REG

struct _edma_core_channel EDMA4_REG

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX

Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS

Public Members

edma4_core_tcd_t edma4_tcd

eDMA soc Driver

FSL_EDMA_SOC_DRIVER_VERSION

Driver version 2.1.0.

FSL_EDMA_SOC_IP_DMA3

DMA IP version.

FSL_EDMA_SOC_IP_DMA4

EDMA_BASE_PTRS

DMA base table.

EDMA_CHN_IRQS

Verify dma base and request source

EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source)

EDMA_CHANNEL_OFFSET

EDMA base address convert macro.

EDMA_CHANNEL_ARRAY_STEP(base)

Ele_base_api

status_t ELE_BaseAPI_Ping(S3MU_Type *mu)

Ping ELE.

This function Ping EdgeLock Enclave, can be sent at any time to verify ELE is alive. Additionally, this command reloads the fuse shadow registers and kick the Sentinel active bit. This active bit must be kicked at least once every day (24 hours).

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_GetFwVersion(S3MU_Type *mu, uint32_t *EleFwVersion)

Get ELE FW Version.

This function is used to retrieve the Sentinel FW version.

Parameters:

• mu – MU peripheral base address

• EleFwVersion – Pointer where ElE firmware version will be stored

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_GetFwStatus(S3MU_Type *mu, uint32_t *EleFwStatus)

Get ELE FW Status.

This function is used to retrieve the Sentinel FW status.

Parameters:

• mu – MU peripheral base address

• EleFwStatus – Pointer where ElE firmware status will be stored

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_EnableAPC(S3MU_Type *mu)

Enable APC (Application core)

This function is used by RTC (real time core) to release APC (Application core) when needed.

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_ForwardLifecycle(S3MU_Type *mu, uint32_t Lifecycle)

Forward Lifecycle update.

This function is to change chip lifecycle 0x01U for NXP provisoned 0x02U for OEM Open 0x08U for OEM Closed 0x80U for OEM Locked

Parameters:

• mu – MU peripheral base address

• Lifecycle – to switch

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_ReleaseRDC(S3MU_Type *mu, uint32_t RdcID, uint32_t CoreID)

Release RDC.

This function is used to release specifed RDC to the core identified in this function. The RDC will be released only if the FW of the core to which is the RDC ownership is going to be transferred has been properly authenticated and verified.

Parameters:

• mu – MU peripheral base address

• RdcID – Resource Domain Control identifier

• CoreID – Core identifier

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_StartRng(S3MU_Type *mu)

Start the initialization of the RNG context.

The RNG must be started before using some of the ELE services.

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_EnableOtfad(S3MU_Type *mu, uint8_t OtfadID)

Enable an instance of OTFAD.

Parameters:

• mu – MU peripheral base address

• OtfadID – ID of the OTFAD instance to enable - used only if there are multiple instances on the SoC

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_ClockChangeStart(S3MU_Type *mu)

Start the clock change process.

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_ClockChangeFinish(S3MU_Type *mu, uint8_t NewClockRateELE, uint8_t NewClockRateCM33)

Change ELE and/or CM33 clock.

It is valid to pass both parameters at the same time if the SoC supports both.

Parameters:

• mu – MU peripheral base address

• NewClockRateELE – the new clock rate for ELE

• NewClockRateCM33 – the new clock rate for the CM33 core

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_VoltageChangeStart(S3MU_Type *mu)

Start the voltage change process.

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

status_t ELE_BaseAPI_VoltageChangeFinish(S3MU_Type *mu)

Finish the voltage change process.

Parameters:

• mu – MU peripheral base address

Returns:

Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange

FSL_ELE_BASE_API_DRIVER_VERSION

Defines ELE Base API version 1.0.0.

Change log:

• Version 1.0.0

  • initial version

RESPONSE_SUCCESS

SHIFT_16

SHIFT_8

MSG_RESPONSE_MAX

MSG_TAG_CMD

MSG_TAG_RESP

PING

PING_SIZE

PING_RESPONSE_HDR

GET_FW_VERSION

GET_FW_VERSION_SIZE

GET_FW_VERSION_RESPONSE_HDR

CLOCK_CHANGE_START

CLOCK_CHANGE_START_SIZE

CLOCK_CHANGE_START_RESPONSE_HDR

CLOCK_CHANGE_FINISH

CLOCK_CHANGE_FINISH_SIZE

CLOCK_CHANGE_FINISH_RESPONSE_HDR

VOLTAGE_CHANGE_START

VOLTAGE_CHANGE_START_SIZE

VOLTAGE_CHANGE_START_RESPONSE_HDR

VOLTAGE_CHANGE_FINISH

VOLTAGE_CHANGE_FINISH_SIZE

VOLTAGE_CHANGE_FINISH_RESPONSE_HDR

GET_FW_STATUS

GET_FW_STATUS_SIZE

GET_FW_STATUS_RESPONSE_HDR

ENABLE_APC

ENABLE_APC_SIZE

ENABLE_APC_RESPONSE_HDR

START_RNG

START_RNG_SIZE

START_RNG_RESPONSE_HDR

FORWARD_LIFECYCLE

FORWARD_LIFECYCLE_SIZE

FORWARD_LIFECYCLE_RESPONSE_HDR

ENABLE_OTFAD

ENABLE_OTFAD_SIZE

ENABLE_OTFAD_RESPONSE_HDR

RELEASE_RDC

RELEASE_RDC_SIZE

RELEASE_RDC_RESPONSE_HDR

EQDC: Enhanced Quadrature Encoder/Decoder

void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)

Initializes the EQDC module.

This function initializes the EQDC by enabling the IP bus clock (optional).

Parameters:

• base – EQDC peripheral base address.

• psConfig – Pointer to configuration structure.

void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)

Gets an available pre-defined configuration.

The default value are:

psConfig->enableReverseDirection              = false;
psConfig->countOnce                           = false;
psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
psConfig->countMode                           = kEQDC_QuadratureX4;
psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
psConfig->enableIndexInitPositionCounter      = false;
psConfig->enableDma                           = false;
psConfig->bufferedRegisterLoadMode            = false;
psConfig->enableTriggerInitPositionCounter    = false;
psConfig->enableTriggerClearPositionRegisters = false;
psConfig->enableTriggerHoldPositionRegisters  = false;
psConfig->enableWatchdog                      = false;
psConfig->watchdogTimeoutValue                = 0xFFFFU;
psConfig->filterPhaseA                        = 0U;
psConfig->filterPhaseB                        = 0U;
psConfig->filterIndPre                        = 0U;
psConfig->filterHomEna                        = 0U;
psConfig->filterClockSourceselection          = false;
psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
psConfig->filterSamplePeriod                  = 0U;
psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
psConfig->positionCompareValue[0]                = 0xFFFFFFFFU;
psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
psConfig->positionModulusValue                = 0U;
psConfig->positionInitialValue                = 0U;
psConfig->positionCounterValue                = 0U;
psConfig->enablePeriodMeasurement             = false;
psConfig->prescaler                           = kEQDC_Prescaler1;
psConfig->enabledInterruptsMask               = 0U;

Parameters:

• psConfig – Pointer to configuration structure.

void EQDC_Deinit(EQDC_Type *base)

De-initializes the EQDC module.

This function deinitializes the EQDC by disabling the IP bus clock (optional).

Parameters:

• base – EQDC peripheral base address.

void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)

Initializes the mode of operation.

This function initializes mode of operation by enabling the IP bus clock (optional).

Parameters:

• base – EQDC peripheral base address.

• operateMode – Select operation mode.

static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode)

Initializes the mode of count.

These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved

Parameters:

• base – EQDC peripheral base address.

• countMode – Select count mode.

static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable)

Enable watchdog for EQDC module.

Parameters:

• base – EQDC peripheral base address

• bEnable – Enables or disables the watchdog

static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout)

Set watchdog timeout value.

Parameters:

• base – EQDC peripheral base address

• u16Timeout – Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out

static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable)

Enable DMA for EQDC module.

Parameters:

• base – EQDC peripheral base address

• bEnable – Enables or disables the DMA

static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Set Buffered Register Load (Update) Mode.

This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Clear Buffered Register Load (Update) Mode.

Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

static inline void EQDC_SetEqdcLdok(EQDC_Type *base)

Set load okay.

Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.

Parameters:

• base – EQDC peripheral base address.

static inline uint8_t EQDC_GetEqdcLdok(EQDC_Type *base)

Get load okay.

Parameters:

• base – EQDC peripheral base address.

static inline void EQDC_ClearEqdcLdok(EQDC_Type *base)

Clear load okay.

Parameters:

• base – EQDC peripheral base address.

static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base)

Get the status flags.

Parameters:

• base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the status flags, _eqdc_status_flags.

static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags)

Clear the status flags.

Parameters:

• base – EQDC peripheral base address.

• u32Flags – Logical OR’ed value of the flags to clear, _eqdc_status_flags.

static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base)

Get the signals’ real-time status.

Parameters:

• base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the real-time signal status, _eqdc_signal_status.

static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base)

Get the direction of the last count.

Parameters:

• base – EQDC peripheral base address.

Returns:

Direction of the last count.

static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Enable the interrupts.

Parameters:

• base – EQDC peripheral base address.

• u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Disable the interrupts.

Parameters:

• base – EQDC peripheral base address.

• u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base)

Load the initial position value to position counter.

Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters:

• base – EQDC peripheral base address.

static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue)

Set initial position value for EQDC module.

Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• u32PositionInitValue – Position initial value

static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue)

Set position counter value.

Set the position counter value (POS or UPOS, LPOS).

Parameters:

• base – EQDC peripheral base address

• positionCounterValue – Position counter value

static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue)

Set position counter modulus value.

Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• positionModulusValue – Position modulus value

static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value)

Set position counter compare 0 value.

Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• u32PositionComp0Value – Position modulus value

static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value)

Set position counter compare 1 value.

Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• u32PositionComp1Value – Position modulus value

static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value)

Set position counter compare 2 value.

Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• u32PositionComp2Value – Position modulus value

static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value)

Set position counter compare 3 value.

Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

1. If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

2. If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

• base – EQDC peripheral base address

• u32PositionComp3Value – Position modulus value

static inline uint32_t EQDC_GetPosition(EQDC_Type *base)

Get the current position counter’s value.

Parameters:

• base – EQDC peripheral base address.

Returns:

Current position counter’s value.

static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base)

Get the hold position counter’s value.

The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:

1. Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.

2. TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position counter’s value.

static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base)

Get the hold position counter1’s value.

The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position counter1’s value.

static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base)

Get the hold position counter2’s value.

The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position counter2’s value.

static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base)

Get the hold position counter3’s value.

The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position counter3’s value.

static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base)

Get the position difference counter’s value.

Parameters:

• base – EQDC peripheral base address.

Returns:

The position difference counter’s value.

static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base)

Get the hold position difference counter’s value.

The position difference (POSD) value is loaded to hold position difference (POSDH) when:

1. Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.

2. TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position difference counter’s value.

static inline uint16_t EQDC_GetRevolution(EQDC_Type *base)

Get the revolution counter’s value.

Get the revolution counter (REV) value.

Parameters:

• base – EQDC peripheral base address.

Returns:

The revolution counter’s value.

static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base)

Get the hold revolution counter’s value.

The revolution counter (REV) value is loaded to hold revolution (REVH) when:

1. Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.

2. TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold position revolution counter’s value.

static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base)

Get the last edge time.

Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

• base – EQDC peripheral base address.

Returns:

The last edge time.

static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base)

Get the hold last edge time.

The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.

Parameters:

• base – EQDC peripheral base address.

Returns:

Hold of last edge time.

static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base)

Get the Position Difference Period counter value.

The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

• base – EQDC peripheral base address.

Returns:

The position difference period counter value.

static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base)

Get buffered Position Difference Period counter value.

The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.

Parameters:

• base – EQDC peripheral base address.

Returns:

The buffered position difference period counter value.

static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)

Get Hold Position Difference Period counter value.

The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.

Parameters:

• base – EQDC peripheral base address.

Returns:

The hold position difference period counter value.

enum _eqdc_status_flags

EQDC status flags, these flags indicate the counter’s events. .

Values:

enumerator kEQDC_HomeEnableTransitionFlag

HOME/ENABLE signal transition occured.

enumerator kEQDC_IndexPresetPulseFlag

INDEX/PRESET pulse occured.

enumerator kEQDC_WatchdogTimeoutFlag

Watchdog timeout occured.

enumerator kEQDC_SimultPhaseChangeFlag

Simultaneous change of PHASEA and PHASEB occured.

enumerator kEQDC_CountDirectionChangeFlag

Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverFlag

Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.

enumerator kEQDC_PositionRollUnderFlag

Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.

enumerator kEQDC_PositionCompare0Flag

Position counter match the COMP0 value.

enumerator kEQDC_PositionCompare1Flag

Position counter match the COMP1 value.

enumerator kEQDC_PositionCompare2Flag

Position counter match the COMP2 value.

enumerator kEQDC_PositionCompare3Flag

Position counter match the COMP3 value.

enumerator kEQDC_StatusAllFlags

enum _eqdc_signal_status

Signal status, these flags indicate the raw and filtered input signal status. .

Values:

enumerator kEQDC_SignalStatusRawHomeEnable

Raw HOME/ENABLE input.

enumerator kEQDC_SignalStatusRawIndexPreset

Raw INDEX/PRESET input.

enumerator kEQDC_SignalStatusRawPhaseB

Raw PHASEB input.

enumerator kEQDC_SignalStatusRawPhaseA

Raw PHASEA input.

enumerator kEQDC_SignalStatusFilteredHomeEnable

The filtered HOME/ENABLE input.

enumerator kEQDC_SignalStatusFilteredIndexPreset

The filtered INDEX/PRESET input.

enumerator kEQDC_SignalStatusFilteredPhaseB

The filtered PHASEB input.

enumerator kEQDC_SignalStatusFilteredPhaseA

The filtered PHASEA input.

enumerator kEQDC_SignalStatusPositionCompare0Flag

Position Compare 0 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare1Flag

Position Compare 1 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare2Flag

Position Compare 2 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare3Flag

Position Compare 3 Flag Output.

enumerator kEQDC_SignalStatusCountDirectionFlagHold

Count Direction Flag Hold.

enumerator kEQDC_SignalStatusCountDirectionFlag

Count Direction Flag Output.

enumerator kEQDC_SignalStatusAllFlags

enum _eqdc_interrupt_enable

Interrupt enable/disable mask. .

Values:

enumerator kEQDC_HomeEnableTransitionInterruptEnable

HOME/ENABLE signal transition interrupt enable.

enumerator kEQDC_IndexPresetPulseInterruptEnable

INDEX/PRESET pulse interrupt enable.

enumerator kEQDC_WatchdogTimeoutInterruptEnable

Watchdog timeout interrupt enable.

enumerator kEQDC_SimultPhaseChangeInterruptEnable

Simultaneous PHASEA and PHASEB change interrupt enable.

enumerator kEQDC_CountDirectionChangeInterruptEnable

Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverInterruptEnable

Roll-over interrupt enable.

enumerator kEQDC_PositionRollUnderInterruptEnable

Roll-under interrupt enable.

enumerator kEQDC_AllInterruptEnable

enum _eqdc_home_enable_init_pos_counter_mode

Define HOME/ENABLE signal’s trigger mode.

Values:

enumerator kEQDC_HomeInitPosCounterDisabled

Don’t use HOME/ENABLE signal to initialize the position counter.

enumerator kEQDC_HomeInitPosCounterOnRisingEdge

Use positive going edge to trigger initialization of position counters.

enumerator kEQDC_HomeInitPosCounterOnFallingEdge

Use negative going edge to trigger initialization of position counters.

enum _eqdc_index_preset_init_pos_counter_mode

Define INDEX/PRESET signal’s trigger mode.

Values:

enumerator kEQDC_IndexInitPosCounterDisabled

INDEX/PRESET pulse does not initialize the position counter.

enumerator kEQDC_IndexInitPosCounterOnRisingEdge

Use INDEX/PRESET pulse rising edge to initialize position counter.

enumerator kEQDC_IndexInitPosCounterOnFallingEdge

Use INDEX/PRESET pulse falling edge to initialize position counter.

enum _eqdc_operate_mode

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

Values:

enumerator kEQDC_QuadratureDecodeOperationMode

Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_QuadratureCountOperationMode

Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.

enumerator kEQDC_SinglePhaseDecodeOperationMode

Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_SinglePhaseCountOperationMode

Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.

enum _eqdc_count_mode

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

• If PHASEA leads PHASEB, then motion is in the positive direction.

• If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:

• In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.

• In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).

• In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

Values:

enumerator kEQDC_QuadratureX4

Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX2

Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX1

Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_UpDownPulseCount

Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountDoubleEdge

Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountSingleEdge

Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enum _eqdc_output_pulse_mode

Define type for the condition of POSMATCH pulses.

Values:

enumerator kEQDC_OutputPulseOnCounterEqualCompare

POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).

enumerator kEQDC_OutputPulseOnReadingPositionCounter

POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).

enum _eqdc_revolution_count_condition

Define type for determining how the revolution counter (REV) is incremented/decremented.

Values:

enumerator kEQDC_RevolutionCountOnIndexPulse

Use INDEX pulse to increment/decrement revolution counter.

enumerator kEQDC_RevolutionCountOnRollOverModulus

Use modulus counting roll-over/under to increment/decrement revolution counter.

enum _eqdc_filter_sample_count

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

Values:

enumerator kEQDC_Filter3Samples

3 samples.

enumerator kEQDC_Filter4Samples

4 samples.

enumerator kEQDC_Filter5Samples

5 samples.

enumerator kEQDC_Filter6Samples

6 samples.

enumerator kEQDC_Filter7Samples

7 samples.

enumerator kEQDC_Filter8Samples

8 samples.

enumerator kEQDC_Filter9Samples

9 samples.

enumerator kEQDC_Filter10Samples

10 samples.

enum _eqdc_count_direction_flag

Count direction.

Values:

enumerator kEQDC_CountDirectionDown

Last count was in down direction.

enumerator kEQDC_CountDirectionUp

Last count was in up direction.

enum _eqdc_prescaler

Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

Values:

enumerator kEQDC_Prescaler1

Prescaler value 1.

enumerator kEQDC_Prescaler2

Prescaler value 2.

enumerator kEQDC_Prescaler4

Prescaler value 4.

enumerator kEQDC_Prescaler8

Prescaler value 8.

enumerator kEQDC_Prescaler16

Prescaler value 16.

enumerator kEQDC_Prescaler32

Prescaler value 32.

enumerator kEQDC_Prescaler64

Prescaler value 64.

enumerator kEQDC_Prescaler128

Prescaler value 128.

enumerator kEQDC_Prescaler256

Prescaler value 256.

enumerator kEQDC_Prescaler512

Prescaler value 512.

enumerator kEQDC_Prescaler1024

Prescaler value 1024.

enumerator kEQDC_Prescaler2048

Prescaler value 2048.

enumerator kEQDC_Prescaler4096

Prescaler value 4096.

enumerator kEQDC_Prescaler8192

Prescaler value 8192.

enumerator kEQDC_Prescaler16384

Prescaler value 16384.

enumerator kEQDC_Prescaler32768

Prescaler value 32768.

typedef enum _eqdc_home_enable_init_pos_counter_mode eqdc_home_enable_init_pos_counter_mode_t

Define HOME/ENABLE signal’s trigger mode.

typedef enum _eqdc_index_preset_init_pos_counter_mode eqdc_index_preset_init_pos_counter_mode_t

Define INDEX/PRESET signal’s trigger mode.

typedef enum _eqdc_operate_mode eqdc_operate_mode_t

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

typedef enum _eqdc_count_mode eqdc_count_mode_t

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

• If PHASEA leads PHASEB, then motion is in the positive direction.

• If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:

• In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.

• In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).

• In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

typedef enum _eqdc_output_pulse_mode eqdc_output_pulse_mode_t

Define type for the condition of POSMATCH pulses.

typedef enum _eqdc_revolution_count_condition eqdc_revolution_count_condition_t

Define type for determining how the revolution counter (REV) is incremented/decremented.

typedef enum _eqdc_filter_sample_count eqdc_filter_sample_count_t

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

typedef enum _eqdc_count_direction_flag eqdc_count_direction_flag_t

Count direction.

typedef enum _eqdc_prescaler eqdc_prescaler_t

Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

typedef struct _eqdc_config eqdc_config_t

Define user configuration structure for EQDC module.

FSL_EQDC_DRIVER_VERSION

EQDC_CTRL_W1C_FLAGS

W1C bits in EQDC CTRL registers.

EQDC_INTCTRL_W1C_FLAGS

W1C bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_EN

Interrupt enable bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_EN

Interrupt enable bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_FLAGS

Interrupt flag bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_FLAGS

Interrupt flag bits in EQDC INTCTRL registers.

struct _eqdc_config

#include <fsl_eqdc.h>

Define user configuration structure for EQDC module.

Public Members

bool enableReverseDirection

Enable reverse direction counting.

bool countOnce

Selects modulo loop or one shot counting mode.

bool enableDma

Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)

bool bufferedRegisterLoadMode

selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD).

bool enableTriggerInitPositionCounter

Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER’s rising edge.

bool enableIndexInitPositionCounter

Enables the feature that the position counter to be initialized by Index Event Edge Mark.

This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:

When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.

When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.

bool enableTriggerClearPositionRegisters

Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER’s rising edge.

bool enableTriggerHoldPositionRegisters

Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER’s rising edge.

bool filterPhaseA

Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed.

bool filterPhaseB

Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed.

bool filterIndPre

Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed.

bool filterHomEna

Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed.

bool enableWatchdog

Enable the watchdog to detect if the target is moving or not.

uint16_t watchdogTimeoutValue

Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer.

eqdc_prescaler_t prescaler

Prescaler.

bool filterClockSourceselection

Filter Clock Source selection.

eqdc_filter_sample_count_t filterSampleCount

Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.

uint8_t filterSamplePeriod

Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

eqdc_operate_mode_t operateMode

Selects operation mode.

eqdc_count_mode_t countMode

Selects count mode.

eqdc_home_enable_init_pos_counter_mode_t homeEnableInitPosCounterMode

Select how HOME/Enable signal used to initialize position counters.

eqdc_index_preset_init_pos_counter_mode_t indexPresetInitPosCounterMode

Select how INDEX/Preset signal used to initialize position counters.

eqdc_output_pulse_mode_t outputPulseMode

The condition of POSMATCH pulses.

uint32_t positionCompareValue[4]

Position compare 0 ~ 3 value. The available value is a 32-bit number.

eqdc_revolution_count_condition_t revolutionCountCondition

Revolution Counter Modulus Enable.

uint32_t positionModulusValue

Position modulus value. The available value is a 32-bit number.

uint32_t positionInitialValue

Position initial value. The available value is a 32-bit number.

uint32_t positionCounterValue

Position counter value. When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.

bool enablePeriodMeasurement

Enable period measurement. When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.

uint16_t enabledInterruptsMask

Mask of interrupts to be enabled, should be OR’ed value of _eqdc_interrupt_enable.

EWM: External Watchdog Monitor Driver

void EWM_Init(EWM_Type *base, const ewm_config_t *config)

Initializes the EWM peripheral.

This function is used to initialize the EWM. After calling, the EWM runs immediately according to the configuration. Note that, except for the interrupt enable control bit, other control bits and registers are write once after a CPU reset. Modifying them more than once generates a bus transfer error.

This is an example.

ewm_config_t config;
EWM_GetDefaultConfig(&config);
config.compareHighValue = 0xAAU;
EWM_Init(ewm_base,&config);

Parameters:

• base – EWM peripheral base address

• config – The configuration of the EWM

void EWM_Deinit(EWM_Type *base)

Deinitializes the EWM peripheral.

This function is used to shut down the EWM.

Parameters:

• base – EWM peripheral base address

void EWM_GetDefaultConfig(ewm_config_t *config)

Initializes the EWM configuration structure.

This function initializes the EWM configuration structure to default values. The default values are as follows.

ewmConfig->enableEwm = true;
ewmConfig->enableEwmInput = false;
ewmConfig->setInputAssertLogic = false;
ewmConfig->enableInterrupt = false;
ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
ewmConfig->prescaler = 0;
ewmConfig->compareLowValue = 0;
ewmConfig->compareHighValue = 0xFEU;

See also

ewm_config_t

Parameters:

• config – Pointer to the EWM configuration structure.

static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)

Enables the EWM interrupt.

This function enables the EWM interrupt.

Parameters:

• base – EWM peripheral base address

• mask – The interrupts to enable The parameter can be combination of the following source if defined

  • kEWM_InterruptEnable

static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)

Disables the EWM interrupt.

This function enables the EWM interrupt.

Parameters:

• base – EWM peripheral base address

• mask – The interrupts to disable The parameter can be combination of the following source if defined

  • kEWM_InterruptEnable

static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)

Gets all status flags.

This function gets all status flags.

This is an example for getting the running flag.

uint32_t status;
status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;

See also

_ewm_status_flags_t

• True: a related status flag has been set.

• False: a related status flag is not set.

Parameters:

• base – EWM peripheral base address

Returns:

State of the status flag: asserted (true) or not-asserted (false).

void EWM_Refresh(EWM_Type *base)

Services the EWM.

This function resets the EWM counter to zero.

Parameters:

• base – EWM peripheral base address

FSL_EWM_DRIVER_VERSION

EWM driver version 2.0.4.

enum _ewm_lpo_clock_source

Describes EWM clock source.

Values:

enumerator kEWM_LpoClockSource0

EWM clock sourced from lpo_clk[0]

enumerator kEWM_LpoClockSource1

EWM clock sourced from lpo_clk[1]

enumerator kEWM_LpoClockSource2

EWM clock sourced from lpo_clk[2]

enumerator kEWM_LpoClockSource3

EWM clock sourced from lpo_clk[3]

enum _ewm_interrupt_enable_t

EWM interrupt configuration structure with default settings all disabled.

This structure contains the settings for all of EWM interrupt configurations.

Values:

enumerator kEWM_InterruptEnable

Enable the EWM to generate an interrupt

enum _ewm_status_flags_t

EWM status flags.

This structure contains the constants for the EWM status flags for use in the EWM functions.

Values:

enumerator kEWM_RunningFlag

Running flag, set when EWM is enabled

typedef enum _ewm_lpo_clock_source ewm_lpo_clock_source_t

Describes EWM clock source.

typedef struct _ewm_config ewm_config_t

Data structure for EWM configuration.

This structure is used to configure the EWM.

struct _ewm_config

#include <fsl_ewm.h>

Data structure for EWM configuration.

This structure is used to configure the EWM.

Public Members

bool enableEwm

Enable EWM module

bool enableEwmInput

Enable EWM_in input

bool setInputAssertLogic

EWM_in signal assertion state

bool enableInterrupt

Enable EWM interrupt

ewm_lpo_clock_source_t clockSource

Clock source select

uint8_t prescaler

Clock prescaler value

uint8_t compareLowValue

Compare low-register value

uint8_t compareHighValue

Compare high-register value

FGPIO Driver

FlexCAN: Flex Controller Area Network Driver

FlexCAN Driver

bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)

Determine whether the FlexCAN instance support CAN FD mode at run time.

Note

Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.

uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)

Get Mailbox offset number by dword.

This function gets the offset number of the specified mailbox. Mailbox is not consecutive between memory regions when payload is not 8 bytes so need to calculate the specified mailbox address. For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword after the 0x4002_4080, which is actually the address of mailbox MB[1].CS.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – Mailbox index.

Returns:

Mailbox address offset in word.

status_t FLEXCAN_EnterFreezeMode(CAN_Type *base)

Enter FlexCAN Freeze Mode.

This function makes the FlexCAN work under Freeze Mode.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

status_t FLEXCAN_ExitFreezeMode(CAN_Type *base)

Exit FlexCAN Freeze Mode.

This function makes the FlexCAN leave Freeze Mode.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

uint32_t FLEXCAN_GetInstance(CAN_Type *base)

Get the FlexCAN instance from peripheral base address.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN instance.

bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit Rates for classical CAN.

This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.

Parameters:

• base – FlexCAN peripheral base address.

• bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.

• sourceClock_Hz – The Source clock frequency in Hz.

• pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration.

void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the user-defined configuration structure.

• sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit rates for CANFD.

This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.

Parameters:

• base – FlexCAN peripheral base address.

• bitRate – The CANFD bus control speed in bps defined by user.

• bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.

• sourceClock_Hz – The Source clock frequency in Hz.

• pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration

void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.bitRateFD            = 2000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the user-defined configuration structure.

• sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

• dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.

• brs – True if bit rate switch is enabled in FD mode.

void FLEXCAN_Deinit(CAN_Type *base)

De-initializes a FlexCAN instance.

This function disables the FlexCAN module clock and sets all register values to the reset value.

Parameters:

• base – FlexCAN peripheral base address.

void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)

Gets the default configuration structure.

This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;

Parameters:

• pConfig – Pointer to the FlexCAN configuration structure.

void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN classical CAN protocol timing characteristic.

This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.

Note

Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)

Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.

This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.

Note

Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().

Parameters:

• base – FlexCAN peripheral base address.

• sourceClock_Hz – Source Clock in Hz.

• bitRate_Bps – Bit rate in Bps.

Returns:

kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.

void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN CANFD data phase timing characteristic.

This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.

Note

Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)

Set bit rate of FlexCAN FD frame.

This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.

Parameters:

• base – FlexCAN peripheral base address.

• sourceClock_Hz – Source Clock in Hz.

• bitRateN_Bps – Nominal bit Rate in Bps.

• bitRateD_Bps – Data bit Rate in Bps.

Returns:

kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.

void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive message buffer global mask.

This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().

Parameters:

• base – FlexCAN peripheral base address.

• mask – Rx Message Buffer Global Mask value.

void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive FIFO global mask.

This function sets the global mask for FlexCAN FIFO in a matching process.

Parameters:

• base – FlexCAN peripheral base address.

• mask – Rx Fifo Global Mask value.

void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)

Sets the FlexCAN receive individual mask.

This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.

Parameters:

• base – FlexCAN peripheral base address.

• maskIdx – The Index of individual Mask.

• mask – Rx Individual Mask value.

void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• enable – Enable/disable Tx Message Buffer.

  • true: Enable Tx Message Buffer.

  • false: Disable Tx Message Buffer.

void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.

• enable – Enable/disable Rx Message Buffer.

  • true: Enable Rx Message Buffer.

  • false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• enable – Enable/disable Tx Message Buffer.

  • true: Enable Tx Message Buffer.

  • false: Disable Tx Message Buffer.

void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.

• enable – Enable/disable Rx Message Buffer.

  • true: Enable Rx Message Buffer.

  • false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetFDMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)

Configures a FlexCAN Remote Response Message Buffer.

User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The Message Buffer index.

• pFrame – Pointer to CAN message frame structure for response.

void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)

Configures the FlexCAN Legacy Rx FIFO.

This function configures the FlexCAN Rx FIFO with given configuration.

Note

Legacy Rx FIFO only can receive classic CAN message.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.

• enable – Enable/disable Legacy Rx FIFO.

  • true: Enable Legacy Rx FIFO.

  • false: Disable Legacy Rx FIFO.

void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable)

Configures the FlexCAN Enhanced Rx FIFO.

This function configures the Enhanced Rx FIFO with given configuration.

Note

Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time.

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter is false.

• enable – Enable/disable Enhanced Rx FIFO.

  • true: Enable Enhanced Rx FIFO.

  • false: Disable Enhanced Rx FIFO.

void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)

Configures the FlexCAN Pretended Networking mode.

This function configures the FlexCAN Pretended Networking mode with given configuration.

Parameters:

• base – FlexCAN peripheral base address.

• pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.

static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)

Gets the FlexCAN module interrupt flags.

This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.

static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)

Clears status flags with the provided mask.

This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.

static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)

Gets the FlexCAN Bus Error Counter value.

This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.

Parameters:

• base – FlexCAN peripheral base address.

• txErrBuf – Buffer to store Tx Error Counter value.

• rxErrBuf – Buffer to store Rx Error Counter value.

static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN low 64 Message Buffer interrupt flags.

This function gets the interrupt flags of a given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN low 64 Message Buffer interrupt flags.

This function clears the interrupt flags of a given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)

Gets the FlexCAN Memory Error Report registers status.

This function gets the FlexCAN Memory Error Report registers status.

Parameters:

• base – FlexCAN peripheral base address.

• errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.

static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)

Gets the FlexCAN Number of Matches when in Pretended Networking.

This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

The number of received wake up msessages.

static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)

Gets the number of FlexCAN Enhanced Rx FIFO available frames.

This function gets the number of CAN messages stored in the Enhanced Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

The number of available CAN messages stored in the Enhanced Rx FIFO.

static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN interrupts according to the provided mask.

This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN interrupts according to the provided mask.

This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN low 64 Message Buffer interrupts.

This function enables the interrupts of given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN low 64 Message Buffer interrupts.

This function disables the interrupts of given Message Buffers.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

• base – FlexCAN peripheral base address.

• mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)

Enables or disables the FlexCAN Rx FIFO DMA request.

This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• enable – true to enable, false to disable.

static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)

Gets the Rx FIFO Head address.

This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.

Parameters:

• base – FlexCAN peripheral base address.

Returns:

FlexCAN Rx FIFO Head address.

static inline status_t FLEXCAN_Enable(CAN_Type *base, bool enable)

Enables or disables the FlexCAN module operation.

This function enables or disables the FlexCAN module.

Parameters:

• base – FlexCAN base pointer.

• enable – true to enable, false to disable.

Returns:

kStatus_Success Enable FlexCAN module successful kStatus_Timeout Timeout when wait for Low-Power Mode Acknowledge

status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)

Writes a FlexCAN Message to the Transmit Message Buffer.

This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN Message Buffer index.

• pTxFrame – Pointer to CAN message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Receive Message Buffer.

This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN Message Buffer index.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)

Writes a FlexCAN FD Message to the Transmit Message Buffer.

This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN FD Message Buffer index.

• pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN FD Message from Receive Message Buffer.

This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

• base – FlexCAN peripheral base address.

• mbIdx – The FlexCAN FD Message Buffer index.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Legacy Rx FIFO.

This function reads a CAN message from the FlexCAN Legacy Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN Message from Enhanced Rx FIFO.

This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Wake Up MB.

This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.

Parameters:

• base – FlexCAN peripheral base address.

• pRxFrame – Pointer to CAN message frame structure for reception.

• mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.

Return values:

• kStatus_Success – - Read Message from Wake up Message Buffer successfully.

• kStatus_Fail – - Wake up Message Buffer has no valid content.

status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

• pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

• kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

• kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – Start Tx Message Buffer sending process successfully.

• kStatus_Fail – Write Tx Message Buffer failed.

• kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – - Start Rx Message Buffer receiving process successfully.

• kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN FD Message Buffer index.

status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN Message Buffer index.

• pTxFrame – Pointer to CAN message frame to be sent.

Return values:

• kStatus_Success – - Write Tx Message Buffer Successfully.

• kStatus_Fail – - Tx Message Buffer is currently in use.

• kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• mbIdx – The FlexCAN Message Buffer index.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Rx Message Buffer is full and has been read successfully.

• kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.

• kStatus_Fail – - Rx Message Buffer is empty.

• kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

• kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

• base – FlexCAN peripheral base pointer.

• pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

• kStatus_Success – - Read Message from Rx FIFO successfully.

• kStatus_Fail – - Rx FIFO is not enabled.

• kStatus_Timeout – - Failed to receive frames within specific time.

void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)

Initializes the FlexCAN handle.

This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• callback – The callback function.

• userData – The parameter of the callback function.

status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – Start Tx Message Buffer sending process successfully.

• kStatus_Fail – Write Tx Message Buffer failed.

• kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

• kStatus_Success – - Start Rx Message Buffer receiving process successfully.

• kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.

Return values:

• kStatus_Success – - Start Rx FIFO receiving process successfully.

• kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Enhanced Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• pFifoXfer – FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@

Return values:

• kStatus_Success – - Start Rx FIFO receiving process successfully.

• kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)

Gets the detail index of Mailbox’s Timestamp by handle.

Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking

Parameters:

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

Return values:

the – index of mailbox ‘s timestamp stored in the handle.

void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Rx FIFO process.

This function aborts the interrupt driven message receive from Rx FIFO process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Enhanced Rx FIFO process.

This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN IRQ handle function.

This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_MbHandleIRQ(CAN_Type *base, flexcan_handle_t *handle, uint32_t startMbIdx, uint32_t endMbIdx)

FlexCAN Message Buffer IRQ handle function.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• startMbIdx – First Message Buffer to handle.

• endMbIdx – Last Message Buffer to handle.

void FLEXCAN_EhancedRxFifoHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Ehanced Rx FIFO IRQ handle function.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_BusoffErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Bus Off, Error and Warning IRQ handle function.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_PNWakeUpHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Pretended Networking Wake-up IRQ handle function.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

void FLEXCAN_MemoryErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Memory Error IRQ handle function.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

FSL_FLEXCAN_DRIVER_VERSION

FlexCAN driver version.

FlexCAN transfer status.

Values:

enumerator kStatus_FLEXCAN_TxBusy

Tx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_TxIdle

Tx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_TxSwitchToRx

Remote Message is send out and Message buffer changed to Receive one.

enumerator kStatus_FLEXCAN_RxBusy

Rx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_RxIdle

Rx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_RxOverflow

Rx Message Buffer is Overflowed.

enumerator kStatus_FLEXCAN_RxFifoBusy

Rx Message FIFO is Busy.

enumerator kStatus_FLEXCAN_RxFifoIdle

Rx Message FIFO is Idle.

enumerator kStatus_FLEXCAN_RxFifoOverflow

Rx Message FIFO is overflowed.

enumerator kStatus_FLEXCAN_RxFifoWarning

Rx Message FIFO is almost overflowed.

enumerator kStatus_FLEXCAN_RxFifoDisabled

Rx Message FIFO is disabled during reading.

enumerator kStatus_FLEXCAN_ErrorStatus

FlexCAN Module Error and Status.

enumerator kStatus_FLEXCAN_WakeUp

FlexCAN is waken up from STOP mode.

enumerator kStatus_FLEXCAN_UnHandled

UnHadled Interrupt asserted.

enumerator kStatus_FLEXCAN_RxRemote

Rx Remote Message Received in Mail box.

enumerator kStatus_FLEXCAN_RxFifoUnderflow

Enhanced Rx Message FIFO is underflow.

enumerator kStatus_FLEXCAN_MemoryError

FlexCAN Memory Error.

enum _flexcan_frame_format

FlexCAN frame format.

Values:

enumerator kFLEXCAN_FrameFormatStandard

Standard frame format attribute.

enumerator kFLEXCAN_FrameFormatExtend

Extend frame format attribute.

enum _flexcan_frame_type

FlexCAN frame type.

Values:

enumerator kFLEXCAN_FrameTypeData

Data frame type attribute.

enumerator kFLEXCAN_FrameTypeRemote

Remote frame type attribute.

enum _flexcan_clock_source

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

Values:

enumerator kFLEXCAN_ClkSrcOsc

FlexCAN Protocol Engine clock from Oscillator.

enumerator kFLEXCAN_ClkSrcPeri

FlexCAN Protocol Engine clock from Peripheral Clock.

enumerator kFLEXCAN_ClkSrc0

FlexCAN Protocol Engine clock selected by user as SRC == 0.

enumerator kFLEXCAN_ClkSrc1

FlexCAN Protocol Engine clock selected by user as SRC == 1.

enum _flexcan_wake_up_source

FlexCAN wake up source.

Values:

enumerator kFLEXCAN_WakeupSrcUnfiltered

FlexCAN uses unfiltered Rx input to detect edge.

enumerator kFLEXCAN_WakeupSrcFiltered

FlexCAN uses filtered Rx input to detect edge.

enum _flexcan_rx_fifo_filter_type

FlexCAN Rx Fifo Filter type.

Values:

enumerator kFLEXCAN_RxFifoFilterTypeA

One full ID (standard and extended) per ID Filter element.

enumerator kFLEXCAN_RxFifoFilterTypeB

Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeC

Four partial 8-bit Standard or extended ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeD

All frames rejected.

enum _flexcan_mb_size

FlexCAN Message Buffer Payload size.

Values:

enumerator kFLEXCAN_8BperMB

Selects 8 bytes per Message Buffer.

enumerator kFLEXCAN_16BperMB

Selects 16 bytes per Message Buffer.

enumerator kFLEXCAN_32BperMB

Selects 32 bytes per Message Buffer.

enumerator kFLEXCAN_64BperMB

Selects 64 bytes per Message Buffer.

enum _flexcan_fd_frame_length

FlexCAN CAN FD frame supporting data length (available DLC values).

For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.

Values:

enumerator kFLEXCAN_0BperFrame

Frame contains 0 valid data bytes.

enumerator kFLEXCAN_1BperFrame

Frame contains 1 valid data bytes.

enumerator kFLEXCAN_2BperFrame

Frame contains 2 valid data bytes.

enumerator kFLEXCAN_3BperFrame

Frame contains 3 valid data bytes.

enumerator kFLEXCAN_4BperFrame

Frame contains 4 valid data bytes.

enumerator kFLEXCAN_5BperFrame

Frame contains 5 valid data bytes.

enumerator kFLEXCAN_6BperFrame

Frame contains 6 valid data bytes.

enumerator kFLEXCAN_7BperFrame

Frame contains 7 valid data bytes.

enumerator kFLEXCAN_8BperFrame

Frame contains 8 valid data bytes.

enumerator kFLEXCAN_12BperFrame

Frame contains 12 valid data bytes.

enumerator kFLEXCAN_16BperFrame

Frame contains 16 valid data bytes.

enumerator kFLEXCAN_20BperFrame

Frame contains 20 valid data bytes.

enumerator kFLEXCAN_24BperFrame

Frame contains 24 valid data bytes.

enumerator kFLEXCAN_32BperFrame

Frame contains 32 valid data bytes.

enumerator kFLEXCAN_48BperFrame

Frame contains 48 valid data bytes.

enumerator kFLEXCAN_64BperFrame

Frame contains 64 valid data bytes.

enum _flexcan_efifo_dma_per_read_length

FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

Values:

enumerator kFLEXCAN_1WordPerRead

Transfer 1 32-bit words (CS).

enumerator kFLEXCAN_2WordPerRead

Transfer 2 32-bit words (CS + ID).

enumerator kFLEXCAN_3WordPerRead

Transfer 3 32-bit words (CS + ID + 1~4 bytes data).

enumerator kFLEXCAN_4WordPerRead

Transfer 4 32-bit words (CS + ID + 5~8 bytes data).

enumerator kFLEXCAN_5WordPerRead

Transfer 5 32-bit words (CS + ID + 9~12 bytes data).

enumerator kFLEXCAN_6WordPerRead

Transfer 6 32-bit words (CS + ID + 13~16 bytes data).

enumerator kFLEXCAN_7WordPerRead

Transfer 7 32-bit words (CS + ID + 17~20 bytes data).

enumerator kFLEXCAN_8WordPerRead

Transfer 8 32-bit words (CS + ID + 21~24 bytes data).

enumerator kFLEXCAN_9WordPerRead

Transfer 9 32-bit words (CS + ID + 25~28 bytes data).

enumerator kFLEXCAN_10WordPerRead

Transfer 10 32-bit words (CS + ID + 29~32 bytes data).

enumerator kFLEXCAN_11WordPerRead

Transfer 11 32-bit words (CS + ID + 33~36 bytes data).

enumerator kFLEXCAN_12WordPerRead

Transfer 12 32-bit words (CS + ID + 37~40 bytes data).

enumerator kFLEXCAN_13WordPerRead

Transfer 13 32-bit words (CS + ID + 41~44 bytes data).

enumerator kFLEXCAN_14WordPerRead

Transfer 14 32-bit words (CS + ID + 45~48 bytes data).

enumerator kFLEXCAN_15WordPerRead

Transfer 15 32-bit words (CS + ID + 49~52 bytes data).

enumerator kFLEXCAN_16WordPerRead

Transfer 16 32-bit words (CS + ID + 53~56 bytes data).

enumerator kFLEXCAN_17WordPerRead

Transfer 17 32-bit words (CS + ID + 57~60 bytes data).

enumerator kFLEXCAN_18WordPerRead

Transfer 18 32-bit words (CS + ID + 61~64 bytes data).

enumerator kFLEXCAN_19WordPerRead

Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).

enum _flexcan_rx_fifo_priority

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

Values:

enumerator kFLEXCAN_RxFifoPrioLow

Matching process start from Rx Message Buffer first.

enumerator kFLEXCAN_RxFifoPrioHigh

Matching process start from Enhanced/Legacy Rx FIFO first.

enum _flexcan_interrupt_enable

FlexCAN interrupt enable enumerations.

This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.

Note

FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.

Values:

enumerator kFLEXCAN_BusOffInterruptEnable

Bus Off interrupt, use bit 15.

enumerator kFLEXCAN_ErrorInterruptEnable

CAN Error interrupt, use bit 14.

enumerator kFLEXCAN_TxWarningInterruptEnable

Tx Warning interrupt, use bit 11.

enumerator kFLEXCAN_RxWarningInterruptEnable

Rx Warning interrupt, use bit 10.

enumerator kFLEXCAN_WakeUpInterruptEnable

Self Wake Up interrupt, use bit 26.

enumerator kFLEXCAN_FDErrorInterruptEnable

CAN FD Error interrupt, use bit 31.

enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable

PN Match Wake Up interrupt, use high word bit 17.

enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable

PN Timeout Wake Up interrupt, use high word bit 16. Enhanced Rx FIFO Underflow interrupt, use high word bit 31.

enumerator kFLEXCAN_ERxFifoUnderflowInterruptEnable

Enhanced Rx FIFO Overflow interrupt, use high word bit 30.

enumerator kFLEXCAN_ERxFifoOverflowInterruptEnable

Enhanced Rx FIFO Watermark interrupt, use high word bit 29.

enumerator kFLEXCAN_ERxFifoWatermarkInterruptEnable

Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28.

enumerator kFLEXCAN_ERxFifoDataAvlInterruptEnable

enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable

Host Access With Non-Correctable Errors interrupt, use high word bit 0.

enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable

FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.

enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable

Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.

enum _flexcan_flags

FlexCAN status flags.

This provides constants for the FlexCAN status flags for use in the FlexCAN functions.

Note

The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.

Values:

enumerator kFLEXCAN_ErrorOverrunFlag

Error Overrun Status.

enumerator kFLEXCAN_FDErrorIntFlag

CAN FD Error Interrupt Flag.

enumerator kFLEXCAN_BusoffDoneIntFlag

Bus Off process completed Interrupt Flag.

enumerator kFLEXCAN_SynchFlag

CAN Synchronization Status.

enumerator kFLEXCAN_TxWarningIntFlag

Tx Warning Interrupt Flag.

enumerator kFLEXCAN_RxWarningIntFlag

Rx Warning Interrupt Flag.

enumerator kFLEXCAN_IdleFlag

FlexCAN In IDLE Status.

enumerator kFLEXCAN_FaultConfinementFlag

FlexCAN Fault Confinement State.

enumerator kFLEXCAN_TransmittingFlag

FlexCAN In Transmission Status.

enumerator kFLEXCAN_ReceivingFlag

FlexCAN In Reception Status.

enumerator kFLEXCAN_BusOffIntFlag

Bus Off Interrupt Flag.

enumerator kFLEXCAN_ErrorIntFlag

CAN Error Interrupt Flag.

enumerator kFLEXCAN_WakeUpIntFlag

Self Wake-Up Interrupt Flag.

enumerator kFLEXCAN_ErrorFlag

enumerator kFLEXCAN_PNMatchIntFlag

PN Matching Event Interrupt Flag.

enumerator kFLEXCAN_PNTimeoutIntFlag

PN Timeout Event Interrupt Flag.

enumerator kFLEXCAN_ERxFifoUnderflowIntFlag

Enhanced Rx FIFO underflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoOverflowIntFlag

Enhanced Rx FIFO overflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoWatermarkIntFlag

Enhanced Rx FIFO watermark Interrupt Flag.

enumerator kFLEXCAN_ERxFifoDataAvlIntFlag

Enhanced Rx FIFO data available Interrupt Flag.

enumerator kFLEXCAN_ERxFifoEmptyFlag

Enhanced Rx FIFO empty status.

enumerator kFLEXCAN_ERxFifoFullFlag

Enhanced Rx FIFO full status.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag

Host Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag

FlexCAN Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_CorrectableErrorIntFlag

Correctable Error Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag

Host Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag

FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_CorrectableErrorOverrunFlag

Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_AllMemoryErrorIntFlag

All Memory Error Interrupt Flags.

enumerator kFLEXCAN_AllMemoryErrorFlag

All Memory Error Flags.

enum _flexcan_error_flags

FlexCAN error status flags.

The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.

Values:

enumerator kFLEXCAN_FDStuffingError

Stuffing Error.

enumerator kFLEXCAN_FDFormError

Form Error.

enumerator kFLEXCAN_FDCrcError

Cyclic Redundancy Check Error.

enumerator kFLEXCAN_FDBit0Error

Unable to send dominant bit.

enumerator kFLEXCAN_FDBit1Error

Unable to send recessive bit.

enumerator kFLEXCAN_TxErrorWarningFlag

Tx Error Warning Status.

enumerator kFLEXCAN_RxErrorWarningFlag

Rx Error Warning Status.

enumerator kFLEXCAN_StuffingError

Stuffing Error.

enumerator kFLEXCAN_FormError

Form Error.

enumerator kFLEXCAN_CrcError

Cyclic Redundancy Check Error.

enumerator kFLEXCAN_AckError

Received no ACK on transmission.

enumerator kFLEXCAN_Bit0Error

Unable to send dominant bit.

enumerator kFLEXCAN_Bit1Error

Unable to send recessive bit.

FlexCAN Legacy Rx FIFO status flags.

The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.

Values:

enumerator kFLEXCAN_RxFifoOverflowFlag

Rx FIFO overflow flag.

enumerator kFLEXCAN_RxFifoWarningFlag

Rx FIFO almost full flag.

enumerator kFLEXCAN_RxFifoFrameAvlFlag

Frames available in Rx FIFO flag.

enum _flexcan_memory_error_type

FlexCAN Memory Error Type.

Values:

enumerator kFLEXCAN_CorrectableError

The memory error is correctable which means on bit error.

enumerator kFLEXCAN_NonCorrectableError

The memory error is non-correctable which means two bit errors.

enum _flexcan_memory_access_type

FlexCAN Memory Access Type.

Values:

enumerator kFLEXCAN_MoveOutFlexCanAccess

The memory error was detected during move-out FlexCAN access.

enumerator kFLEXCAN_MoveInAccess

The memory error was detected during move-in FlexCAN access.

enumerator kFLEXCAN_TxArbitrationAccess

The memory error was detected during Tx Arbitration FlexCAN access.

enumerator kFLEXCAN_RxMatchingAccess

The memory error was detected during Rx Matching FlexCAN access.

enumerator kFLEXCAN_MoveOutHostAccess

The memory error was detected during Rx Matching Host (CPU) access.

enum _flexcan_byte_error_syndrome

FlexCAN Memory Error Byte Syndrome.

Values:

enumerator kFLEXCAN_NoError

No bit error in this byte.

enumerator kFLEXCAN_ParityBits0Error

Parity bit 0 error in this byte.

enumerator kFLEXCAN_ParityBits1Error

Parity bit 1 error in this byte.

enumerator kFLEXCAN_ParityBits2Error

Parity bit 2 error in this byte.

enumerator kFLEXCAN_ParityBits3Error

Parity bit 3 error in this byte.

enumerator kFLEXCAN_ParityBits4Error

Parity bit 4 error in this byte.

enumerator kFLEXCAN_DataBits0Error

Data bit 0 error in this byte.

enumerator kFLEXCAN_DataBits1Error

Data bit 1 error in this byte.

enumerator kFLEXCAN_DataBits2Error

Data bit 2 error in this byte.

enumerator kFLEXCAN_DataBits3Error

Data bit 3 error in this byte.

enumerator kFLEXCAN_DataBits4Error

Data bit 4 error in this byte.

enumerator kFLEXCAN_DataBits5Error

Data bit 5 error in this byte.

enumerator kFLEXCAN_DataBits6Error

Data bit 6 error in this byte.

enumerator kFLEXCAN_DataBits7Error

Data bit 7 error in this byte.

enumerator kFLEXCAN_AllZeroError

All-zeros non-correctable error in this byte.

enumerator kFLEXCAN_AllOneError

All-ones non-correctable error in this byte.

enumerator kFLEXCAN_NonCorrectableErrors

Non-correctable error in this byte.

enum _flexcan_pn_match_source

FlexCAN Pretended Networking match source selection.

Values:

enumerator kFLEXCAN_PNMatSrcID

Message match with ID filtering.

enumerator kFLEXCAN_PNMatSrcIDAndData

Message match with ID filtering and payload filtering.

enum _flexcan_pn_match_mode

FlexCAN Pretended Networking mode match type.

Values:

enumerator kFLEXCAN_PNMatModeEqual

Match upon ID/Payload contents against an exact target value.

enumerator kFLEXCAN_PNMatModeGreater

Match upon an ID/Payload value greater than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeSmaller

Match upon an ID/Payload value smaller than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeRange

Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit

typedef enum _flexcan_frame_format flexcan_frame_format_t

FlexCAN frame format.

typedef enum _flexcan_frame_type flexcan_frame_type_t

FlexCAN frame type.

typedef enum _flexcan_clock_source flexcan_clock_source_t

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t

FlexCAN wake up source.

typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t

FlexCAN Rx Fifo Filter type.

typedef enum _flexcan_mb_size flexcan_mb_size_t

FlexCAN Message Buffer Payload size.

typedef enum _flexcan_efifo_dma_per_read_length flexcan_efifo_dma_per_read_length_t

FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t

FlexCAN Memory Error Type.

typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t

FlexCAN Memory Access Type.

typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t

FlexCAN Memory Error Byte Syndrome.

typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

typedef struct _flexcan_frame flexcan_frame_t

FlexCAN message frame structure.

typedef struct _flexcan_fd_frame flexcan_fd_frame_t

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

typedef struct _flexcan_timing_config flexcan_timing_config_t

FlexCAN protocol timing characteristic configuration structure.

typedef struct _flexcan_config flexcan_config_t

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t

FlexCAN Pretended Networking match source selection.

typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t

FlexCAN Pretended Networking mode match type.

typedef struct _flexcan_pn_config flexcan_pn_config_t

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t

FlexCAN Legacy Rx FIFO configuration structure.

typedef struct _flexcan_enhanced_rx_fifo_std_id_filter flexcan_enhanced_rx_fifo_std_id_filter_t

FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter flexcan_enhanced_rx_fifo_ext_id_filter_t

FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_config flexcan_enhanced_rx_fifo_config_t

FlexCAN Enhanced Rx FIFO configuration structure.

typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t

FlexCAN Message Buffer transfer.

typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t

FlexCAN Rx FIFO transfer.

typedef struct _flexcan_handle flexcan_handle_t

FlexCAN handle structure definition.

typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)

FLEXCAN_WAIT_TIMEOUT

FLEXCAN_POLLING_TIMEOUT

Max loops to wait for polling transfer.

FLEXCAN_MODULE_TIMEOUT

Max loops to wait for FlexCAN register access complete.

DLC_LENGTH_DECODE(dlc)

FlexCAN frame length helper macro.

FLEXCAN_ID_STD(id)

FlexCAN Frame ID helper macro.

Standard Frame ID helper macro.

FLEXCAN_ID_EXT(id)

Extend Frame ID helper macro.

FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)

FlexCAN Rx Message Buffer Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide)

Extend Rx Message Buffer Mask helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)

FlexCAN Legacy Rx FIFO Mask helper macro.

Standard Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)

Standard Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)

Standard Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id)

Standard Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)

Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id)

Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id)

Standard Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)

Extend Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id)

Extend Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id)

Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id)

Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id)

Extend Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)

FlexCAN Rx FIFO Filter helper macro.

Standard Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide)

Standard Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide)

Standard Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id)

Standard Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id)

Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id)

Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)

Standard Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide)

Extend Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)

Extend Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id)

Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id)

Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id)

Extend Rx FIFO Filter helper macro Type C lower part helper macro.

ENHANCED_RX_FIFO_FSCH(x)

FlexCAN Enhanced Rx FIFO Filter and Mask helper macro.

RTR_STD_HIGH(x)

RTR_STD_LOW(x)

RTR_EXT(x)

ID_STD_LOW(id)

ID_STD_HIGH(id)

ID_EXT(id)

FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask)

Standard ID filter element with filter + mask scheme.

FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask)

Standard ID filter element with filter range.

FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2)

Standard ID filter element with two filters without masks.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr)

Extended ID filter element with filter + mask scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask)

Extended ID filter element with filter + mask scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr)

Extended ID filter element with range scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask)

Extended ID filter element with range scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2)

Extended ID filter element with two filters without masks low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1)

Extended ID filter element with two filters without masks high word.

FLEXCAN_PN_STD_MASK(id, rtr)

FlexCAN Pretended Networking ID Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_PN_EXT_MASK(id, rtr)

Extend Rx Message Buffer Mask helper macro.

FLEXCAN_PN_INT_MASK(x)

FlexCAN interrupt/status flag helper macro.

FLEXCAN_PN_INT_UNMASK(x)

FLEXCAN_PN_STATUS_MASK(x)

FLEXCAN_PN_STATUS_UNMASK(x)

FLEXCAN_EFIFO_INT_MASK(x)

FLEXCAN_EFIFO_INT_UNMASK(x)

FLEXCAN_EFIFO_STATUS_MASK(x)

FLEXCAN_EFIFO_STATUS_UNMASK(x)

FLEXCAN_MECR_INT_MASK(x)

FLEXCAN_MECR_INT_UNMASK(x)

FLEXCAN_MECR_STATUS_MASK(x)

FLEXCAN_MECR_STATUS_UNMASK(x)

FLEXCAN_ERROR_AND_STATUS_INT_FLAG

FLEXCAN_PNWAKE_UP_FLAG

FLEXCAN_WAKE_UP_FLAG

FLEXCAN_MEMORY_ERROR_INT_FLAG

FLEXCAN_ENHANCED_RX_FIFO_INT_FLAG

FlexCAN Enhanced Rx FIFO base address helper macro.

E_RX_FIFO(base)

FLEXCAN_CALLBACK(x)

FlexCAN transfer callback function.

The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.

struct _flexcan_memory_error_report_status

#include <fsl_flexcan.h>

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

Public Members

flexcan_memory_error_type_t errorType

The type of memory error that giving rise to the report.

flexcan_memory_access_type_t accessType

The type of memory access that giving rise to the memory error.

uint16_t accessAddress

The address where memory error detected.

uint32_t errorData

The raw data word read from memory with error.

struct _flexcan_frame

#include <fsl_flexcan.h>

FlexCAN message frame structure.

struct _flexcan_fd_frame

#include <fsl_flexcan.h>

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

Public Members

uint32_t idhit

Note

ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is correct. CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive mode).

struct _flexcan_timing_config

#include <fsl_flexcan.h>

FlexCAN protocol timing characteristic configuration structure.

Public Members

uint32_t preDivider

Classic CAN or CAN FD nominal phase bit rate prescaler.

uint32_t rJumpwidth

Classic CAN or CAN FD nominal phase Re-sync Jump Width.

uint32_t phaseSeg1

Classic CAN or CAN FD nominal phase Segment 1.

uint32_t phaseSeg2

Classic CAN or CAN FD nominal phase Segment 2.

uint32_t propSeg

Classic CAN or CAN FD nominal phase Propagation Segment.

uint32_t fpreDivider

CAN FD data phase bit rate prescaler.

uint32_t frJumpwidth

CAN FD data phase Re-sync Jump Width.

uint32_t fphaseSeg1

CAN FD data phase Phase Segment 1.

uint32_t fphaseSeg2

CAN FD data phase Phase Segment 2.

uint32_t fpropSeg

CAN FD data phase Propagation Segment.

struct _flexcan_config

#include <fsl_flexcan.h>

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

Public Members

flexcan_clock_source_t clkSrc

Clock source for FlexCAN Protocol Engine.

flexcan_wake_up_source_t wakeupSrc

Wake up source selection.

uint8_t maxMbNum

The maximum number of Message Buffers used by user.

bool enableLoopBack

Enable or Disable Loop Back Self Test Mode.

bool enableTimerSync

Enable or Disable Timer Synchronization.

bool enableSelfWakeup

Enable or Disable Self Wakeup Mode.

bool enableIndividMask

Enable or Disable Rx Individual Mask and Queue feature.

bool disableSelfReception

Enable or Disable Self Reflection.

bool enableListenOnlyMode

Enable or Disable Listen Only Mode.

bool enableDoze

Enable or Disable Doze Mode.

bool enablePretendedeNetworking

Enable or Disable the Pretended Networking mode.

bool enableMemoryErrorControl

Enable or Disable the memory errors detection and correction mechanism.

bool enableNonCorrectableErrorEnterFreeze

Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.

bool enableTransceiverDelayMeasure

Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.

bool enableRemoteRequestFrameStored

true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.

struct _flexcan_rx_mb_config

#include <fsl_flexcan.h>

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

Public Members

uint32_t id

CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

flexcan_frame_format_t format

CAN Frame Identifier format(Standard of Extend).

flexcan_frame_type_t type

CAN Frame Type(Data or Remote for classical CAN only).

struct _flexcan_pn_config

#include <fsl_flexcan.h>

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

Public Members

bool enableTimeout

Enable or Disable timeout event trigger wakeup.

uint16_t timeoutValue

The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.

bool enableMatch

Enable or Disable match event trigger wakeup.

flexcan_pn_match_source_t matchSrc

Selects the match source (ID and/or data match) to trigger wakeup.

uint8_t matchNum

The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.

flexcan_pn_match_mode_t idMatchMode

The ID match type.

flexcan_pn_match_mode_t dataMatchMode

The data match type.

uint32_t idLower

The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.

uint32_t idUpper

The ID target values 2 which used only as the upper limit value in ID match “range

detection” or used to store the ID mask in “equal to”.

uint8_t lengthLower

The lower limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

uint8_t lengthUpper

The upper limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

struct _flexcan_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Legacy Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable

Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.

uint8_t idFilterNum

The FlexCAN Legacy Rx FIFO Filter elements quantity.

flexcan_rx_fifo_filter_type_t idFilterType

The FlexCAN Legacy Rx FIFO Filter type.

flexcan_rx_fifo_priority_t priority

The FlexCAN Legacy Rx FIFO receive priority.

struct _flexcan_enhanced_rx_fifo_std_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

Public Members

uint32_t filterType

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1

CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1

CAN Frame Type(DATA or REMOTE).

uint32_t rtr2

CAN Frame Identifier(STD or EXT format).

uint32_t std2

Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_ext_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

Public Members

uint32_t filterType

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1

CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1

CAN Frame Type(DATA or REMOTE).

uint32_t rtr2

CAN Frame Identifier(STD or EXT format).

uint32_t std2

Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable

Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member occupies 32 bit word, table size should be equal to idFilterNum. There are two types of Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table members), the extended-ID filter element needs to be placed in front of the table.

uint8_t idFilterPairNum

idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two standard ID filter elements.

uint8_t extendIdFilterNum

The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO identifier filter table, each extended-ID filter element occupies 2 words, extendIdFilterNum need less than or equal to idFilterPairNum.

uint8_t fifoWatermark

(fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO which can trigger FIFO watermark interrupt or a DMA request.

flexcan_efifo_dma_per_read_length_t dmaPerReadLength

Define the length of each read of the Enhanced RX FIFO element by the DAM, see _flexcan_fd_frame_length.

flexcan_rx_fifo_priority_t priority

The FlexCAN Enhanced Rx FIFO receive priority.

struct _flexcan_mb_transfer

#include <fsl_flexcan.h>

FlexCAN Message Buffer transfer.

Public Members

flexcan_frame_t *frame

The buffer of CAN Message to be transfer.

uint8_t mbIdx

The index of Message buffer used to transfer Message.

struct _flexcan_fifo_transfer

#include <fsl_flexcan.h>

FlexCAN Rx FIFO transfer.

Public Members

flexcan_fd_frame_t *framefd

The buffer of CAN Message to be received from Enhanced Rx FIFO.

flexcan_frame_t *frame

The buffer of CAN Message to be received from Legacy Rx FIFO.

size_t frameNum

Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO.

struct _flexcan_handle

#include <fsl_flexcan.h>

FlexCAN handle structure.

Public Members

flexcan_transfer_callback_t callback

Callback function.

void *userData

FlexCAN callback function parameter.

flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]

The buffer for received CAN data from Message Buffers.

flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]

The buffer for received CAN FD data from Message Buffers.

flexcan_frame_t *volatile rxFifoFrameBuf

The buffer for received CAN data from Legacy Rx FIFO.

flexcan_fd_frame_t *volatile rxFifoFDFrameBuf

The buffer for received CAN FD data from Ehanced Rx FIFO.

size_t rxFifoFrameNum

The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO.

size_t rxFifoTransferTotalNum

Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO.

volatile uint8_t mbState[CAN_WORD1_COUNT]

Message Buffer transfer state.

volatile uint8_t rxFifoState

Rx FIFO transfer state.

volatile uint32_t timestamp[CAN_WORD1_COUNT]

Mailbox transfer timestamp.

struct byteStatus

Public Members

bool byteIsRead

The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.

struct __unnamed34__

Public Members

uint32_t timestamp

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length

CAN frame data length in bytes (Range: 0~8).

uint32_t type

CAN Frame Type(DATA or REMOTE).

uint32_t format

CAN Frame Identifier(STD or EXT format).

uint32_t __pad0__

Reserved.

uint32_t idhit

CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).

struct __unnamed36__

Public Members

uint32_t id

CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__

Reserved.

union __unnamed38__

Public Members

struct _flexcan_frame

struct _flexcan_frame

struct __unnamed40__

Public Members

uint32_t dataWord0

CAN Frame payload word0.

uint32_t dataWord1

CAN Frame payload word1.

struct __unnamed42__

Public Members

uint8_t dataByte3

CAN Frame payload byte3.

uint8_t dataByte2

CAN Frame payload byte2.

uint8_t dataByte1

CAN Frame payload byte1.

uint8_t dataByte0

CAN Frame payload byte0.

uint8_t dataByte7

CAN Frame payload byte7.

uint8_t dataByte6

CAN Frame payload byte6.

uint8_t dataByte5

CAN Frame payload byte5.

uint8_t dataByte4

CAN Frame payload byte4.

struct __unnamed44__

Public Members

uint32_t timestamp

FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length

CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t type

CAN Frame Type(DATA only).

uint32_t format

CAN Frame Identifier(STD or EXT format).

uint32_t srr

Substitute Remote request.

uint32_t esi

Error State Indicator.

uint32_t brs

Bit Rate Switch.

uint32_t edl

Extended Data Length.

struct __unnamed46__

Public Members

uint32_t id

CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__

Reserved.

union __unnamed48__

Public Members

struct _flexcan_fd_frame

struct _flexcan_fd_frame

struct __unnamed50__

Public Members

uint32_t dataWord[16]

CAN FD Frame payload, 16 double word maximum.

struct __unnamed52__

Public Members

uint8_t dataByte3

CAN Frame payload byte3.

uint8_t dataByte2

CAN Frame payload byte2.

uint8_t dataByte1

CAN Frame payload byte1.

uint8_t dataByte0

CAN Frame payload byte0.

uint8_t dataByte7

CAN Frame payload byte7.

uint8_t dataByte6

CAN Frame payload byte6.

uint8_t dataByte5

CAN Frame payload byte5.

uint8_t dataByte4

CAN Frame payload byte4.

union __unnamed54__

Public Members

struct _flexcan_config

struct _flexcan_config

struct __unnamed56__

Public Members

uint32_t baudRate

FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t baudRateFD

FlexCAN FD bit rate in bps, for CANFD data phase.

struct __unnamed58__

Public Members

uint32_t bitRate

FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t bitRateFD

FlexCAN FD bit rate in bps, for CANFD data phase.

union __unnamed60__

Public Members

struct _flexcan_pn_config

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

struct _flexcan_pn_config

struct __unnamed64__

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

Public Members

uint32_t lowerWord0

CAN Frame payload word0.

uint32_t lowerWord1

CAN Frame payload word1.

struct __unnamed66__

Public Members

uint8_t lowerByte3

CAN Frame payload byte3.

uint8_t lowerByte2

CAN Frame payload byte2.

uint8_t lowerByte1

CAN Frame payload byte1.

uint8_t lowerByte0

CAN Frame payload byte0.

uint8_t lowerByte7

CAN Frame payload byte7.

uint8_t lowerByte6

CAN Frame payload byte6.

uint8_t lowerByte5

CAN Frame payload byte5.

uint8_t lowerByte4

CAN Frame payload byte4.

union __unnamed62__

Public Members

struct _flexcan_pn_config

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

struct _flexcan_pn_config

struct __unnamed68__

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

Public Members

uint32_t upperWord0

CAN Frame payload word0.

uint32_t upperWord1

CAN Frame payload word1.

struct __unnamed70__

Public Members

uint8_t upperByte3

CAN Frame payload byte3.

uint8_t upperByte2

CAN Frame payload byte2.

uint8_t upperByte1

CAN Frame payload byte1.

uint8_t upperByte0

CAN Frame payload byte0.

uint8_t upperByte7

CAN Frame payload byte7.

uint8_t upperByte6

CAN Frame payload byte6.

uint8_t upperByte5

CAN Frame payload byte5.

uint8_t upperByte4

CAN Frame payload byte4.

FlexCAN eDMA Driver

void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)

Initializes the FlexCAN handle, which is used in transactional functions.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• callback – The callback function.

• userData – The parameter of the callback function.

• rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.

void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)

Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.

This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.

Parameters:

• base – FlexCAN peripheral base address.

• pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

• pEdmaConfig – The user configuration structure of type edma_transfer_t.

status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)

Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.

This function to Update edma transfer confiugration and Start eDMA transfer

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• pEdmaConfig – The user configuration structure of type edma_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN Message from the Legacy Rx FIFO using eDMA.

This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)

Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.

This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

• base – FlexCAN peripheral base address.

• handle – Pointer to flexcan_edma_handle_t structure.

• pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

• base – FlexCAN peripheral base address.

• handle – FlexCAN handle pointer.

• count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

FSL_FLEXCAN_EDMA_DRIVER_VERSION

FlexCAN EDMA driver version.

typedef struct _flexcan_edma_handle flexcan_edma_handle_t

typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData)

FlexCAN transfer callback function.

struct _flexcan_edma_handle

#include <fsl_flexcan_edma.h>

FlexCAN eDMA handle.

Public Members

flexcan_edma_transfer_callback_t callback

Callback function.

void *userData

FlexCAN callback function parameter.

edma_handle_t *rxFifoEdmaHandle

The EDMA handler for Rx FIFO.

volatile uint8_t rxFifoState

Rx FIFO transfer state.

size_t frameNum

The number of messages that need to be received.

flexcan_fd_frame_t *framefd

Point to the buffer of CAN Message to be received from Enhanced Rx FIFO.

FlexIO: FlexIO Driver

FlexIO Driver

void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)

Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().

Example:

flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);

Parameters:

• userConfig – pointer to flexio_config_t structure

void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)

Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().

Example

flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);

Parameters:

• base – FlexIO peripheral base address

• userConfig – pointer to flexio_config_t structure

void FLEXIO_Deinit(FLEXIO_Type *base)

Gates the FlexIO clock. Call this API to stop the FlexIO clock.

Note

After calling this API, call the FLEXO_Init to use the FlexIO module.

Parameters:

• base – FlexIO peripheral base address

uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)

Get instance number for FLEXIO module.

Parameters:

• base – FLEXIO peripheral base address.

void FLEXIO_Reset(FLEXIO_Type *base)

Resets the FlexIO module.

Parameters:

• base – FlexIO peripheral base address

static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)

Enables the FlexIO module operation.

Parameters:

• base – FlexIO peripheral base address

• enable – true to enable, false to disable.

static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)

Reads the input data on each of the FlexIO pins.

Parameters:

• base – FlexIO peripheral base address

Returns:

FlexIO pin input data

static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)

Gets the current state pointer for state mode use.

Parameters:

• base – FlexIO peripheral base address

Returns:

current State pointer

void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)

Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.

Example

flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);

Parameters:

• base – FlexIO peripheral base address

• index – Shifter index

• shifterConfig – Pointer to flexio_shifter_config_t structure

void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)

Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.

Example

flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);

Parameters:

• base – FlexIO peripheral base address

• index – Timer index

• timerConfig – Pointer to the flexio_timer_config_t structure

static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)

This function set the value of the prescaler on flexio channels.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

• index – Timer index

• clocksource – Set clock value

static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)

Gets the shifter status flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Shifter status flags

static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter status flags.

Note

For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)

Gets the shifter error flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Shifter error flags

static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter error flags.

Note

For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)

Gets the timer status flags.

Parameters:

• base – FlexIO peripheral base address

Returns:

Timer status flags

static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the timer status flags.

Note

For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)

Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.

Note

For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

• base – FlexIO peripheral base address

• mask – The shifter status mask which can be calculated by (1 << shifter index)

• enable – True to enable, false to disable.

uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)

Gets the shifter buffer address for the DMA transfer usage.

Parameters:

• base – FlexIO peripheral base address

• type – Shifter type of flexio_shifter_buffer_type_t

• index – Shifter index

Returns:

Corresponding shifter buffer index

status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)

Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

• handle – Pointer to the handler for FlexIO simulated peripheral.

• isr – FlexIO simulated peripheral interrupt handler.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_UnregisterHandleIRQ(void *base)

Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

• base – Pointer to the FlexIO simulated peripheral type.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 0.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 1.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple FLEXIO pins.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the FLEXIO pins to the logic 1 or 0.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

• output – FLEXIO pin output logic level.

  • 0: corresponding pin output low-logic level.

  • 1: corresponding pin output high-logic level.

static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)

Enables the FLEXIO output pin function.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)

Reads the current input value of the FLEXIO pin.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

Return values:

FLEXIO – port input value

• 0: corresponding pin input low-logic level.

• 1: corresponding pin input high-logic level.

static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)

Gets the FLEXIO input pin status.

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

Return values:

FLEXIO – port input status

• 0: corresponding pin input capture no status.

• 1: corresponding pin input capture rising or falling edge.

static inline void FLEXIO_SetPinLevel(FLEXIO_Type *base, uint8_t pin, bool level)

Sets the FLEXIO output pin level.

Parameters:

• base – FlexIO peripheral base address

• pin – FlexIO pin number.

• level – FlexIO output pin level to set, can be either 0 or 1.

static inline bool FLEXIO_GetPinOverride(const FLEXIO_Type *const base, uint8_t pin)

Gets the enabled status of a FLEXIO output pin.

Parameters:

• base – FlexIO peripheral base address

• pin – FlexIO pin number.

Return values:

FlexIO – port enabled status

• 0: corresponding output pin is in disabled state.

• 1: corresponding output pin is in enabled state.

static inline void FLEXIO_ConfigPinOverride(FLEXIO_Type *base, uint8_t pin, bool enabled)

Enables or disables a FLEXIO output pin.

Parameters:

• base – FlexIO peripheral base address

• pin – Flexio pin number.

• enabled – Enable or disable the FlexIO pin.

static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)

Clears the multiple FLEXIO input pins status.

Parameters:

• base – FlexIO peripheral base address

• mask – FLEXIO pin number mask

FSL_FLEXIO_DRIVER_VERSION

FlexIO driver version.

enum _flexio_timer_trigger_polarity

Define time of timer trigger polarity.

Values:

enumerator kFLEXIO_TimerTriggerPolarityActiveHigh

Active high.

enumerator kFLEXIO_TimerTriggerPolarityActiveLow

Active low.

enum _flexio_timer_trigger_source

Define type of timer trigger source.

Values:

enumerator kFLEXIO_TimerTriggerSourceExternal

External trigger selected.

enumerator kFLEXIO_TimerTriggerSourceInternal

Internal trigger selected.

enum _flexio_pin_config

Define type of timer/shifter pin configuration.

Values:

enumerator kFLEXIO_PinConfigOutputDisabled

Pin output disabled.

enumerator kFLEXIO_PinConfigOpenDrainOrBidirection

Pin open drain or bidirectional output enable.

enumerator kFLEXIO_PinConfigBidirectionOutputData

Pin bidirectional output data.

enumerator kFLEXIO_PinConfigOutput

Pin output.

enum _flexio_pin_polarity

Definition of pin polarity.

Values:

enumerator kFLEXIO_PinActiveHigh

Active high.

enumerator kFLEXIO_PinActiveLow

Active low.

enum _flexio_timer_mode

Define type of timer work mode.

Values:

enumerator kFLEXIO_TimerModeDisabled

Timer Disabled.

enumerator kFLEXIO_TimerModeDual8BitBaudBit

Dual 8-bit counters baud/bit mode.

enumerator kFLEXIO_TimerModeDual8BitPWM

Dual 8-bit counters PWM mode.

enumerator kFLEXIO_TimerModeSingle16Bit

Single 16-bit counter mode.

enumerator kFLEXIO_TimerModeDual8BitPWMLow

Dual 8-bit counters PWM Low mode.

enum _flexio_timer_output

Define type of timer initial output or timer reset condition.

Values:

enumerator kFLEXIO_TimerOutputOneNotAffectedByReset

Logic one when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset

Logic zero when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputOneAffectedByReset

Logic one when enabled and on timer reset.

enumerator kFLEXIO_TimerOutputZeroAffectedByReset

Logic zero when enabled and on timer reset.

enum _flexio_timer_decrement_source

Define type of timer decrement.

Values:

enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput

Decrement counter on FlexIO clock, Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

enum _flexio_timer_reset_condition

Define type of timer reset condition.

Values:

enumerator kFLEXIO_TimerResetNever

Timer never reset.

enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput

Timer reset on Timer Pin equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput

Timer reset on Timer Trigger equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge

Timer reset on Timer Pin rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge

Timer reset on Trigger rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge

Timer reset on Trigger rising or falling edge.

enum _flexio_timer_disable_condition

Define type of timer disable condition.

Values:

enumerator kFLEXIO_TimerDisableNever

Timer never disabled.

enumerator kFLEXIO_TimerDisableOnPreTimerDisable

Timer disabled on Timer N-1 disable.

enumerator kFLEXIO_TimerDisableOnTimerCompare

Timer disabled on Timer compare.

enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow

Timer disabled on Timer compare and Trigger Low.

enumerator kFLEXIO_TimerDisableOnPinBothEdge

Timer disabled on Pin rising or falling edge.

enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh

Timer disabled on Pin rising or falling edge provided Trigger is high.

enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge

Timer disabled on Trigger falling edge.

enum _flexio_timer_enable_condition

Define type of timer enable condition.

Values:

enumerator kFLEXIO_TimerEnabledAlways

Timer always enabled.

enumerator kFLEXIO_TimerEnableOnPrevTimerEnable

Timer enabled on Timer N-1 enable.

enumerator kFLEXIO_TimerEnableOnTriggerHigh

Timer enabled on Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh

Timer enabled on Trigger high and Pin high.

enumerator kFLEXIO_TimerEnableOnPinRisingEdge

Timer enabled on Pin rising edge.

enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh

Timer enabled on Pin rising edge and Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge

Timer enabled on Trigger rising edge.

enumerator kFLEXIO_TimerEnableOnTriggerBothEdge

Timer enabled on Trigger rising or falling edge.

enum _flexio_timer_stop_bit_condition

Define type of timer stop bit generate condition.

Values:

enumerator kFLEXIO_TimerStopBitDisabled

Stop bit disabled.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare

Stop bit is enabled on timer compare.

enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable

Stop bit is enabled on timer disable.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable

Stop bit is enabled on timer compare and timer disable.

enum _flexio_timer_start_bit_condition

Define type of timer start bit generate condition.

Values:

enumerator kFLEXIO_TimerStartBitDisabled

Start bit disabled.

enumerator kFLEXIO_TimerStartBitEnabled

Start bit enabled.

enum _flexio_timer_output_state

FlexIO as PWM channel output state.

Values:

enumerator kFLEXIO_PwmLow

The output state of PWM channel is low

enumerator kFLEXIO_PwmHigh

The output state of PWM channel is high

enum _flexio_shifter_timer_polarity

Define type of timer polarity for shifter control.

Values:

enumerator kFLEXIO_ShifterTimerPolarityOnPositive

Shift on positive edge of shift clock.

enumerator kFLEXIO_ShifterTimerPolarityOnNegitive

Shift on negative edge of shift clock.

enum _flexio_shifter_mode

Define type of shifter working mode.

Values:

enumerator kFLEXIO_ShifterDisabled

Shifter is disabled.

enumerator kFLEXIO_ShifterModeReceive

Receive mode.

enumerator kFLEXIO_ShifterModeTransmit

Transmit mode.

enumerator kFLEXIO_ShifterModeMatchStore

Match store mode.

enumerator kFLEXIO_ShifterModeMatchContinuous

Match continuous mode.

enumerator kFLEXIO_ShifterModeState

SHIFTBUF contents are used for storing programmable state attributes.

enumerator kFLEXIO_ShifterModeLogic

SHIFTBUF contents are used for implementing programmable logic look up table.

enum _flexio_shifter_input_source

Define type of shifter input source.

Values:

enumerator kFLEXIO_ShifterInputFromPin

Shifter input from pin.

enumerator kFLEXIO_ShifterInputFromNextShifterOutput

Shifter input from Shifter N+1.

enum _flexio_shifter_stop_bit

Define of STOP bit configuration.

Values:

enumerator kFLEXIO_ShifterStopBitDisable

Disable shifter stop bit.

enumerator kFLEXIO_ShifterStopBitLow

Set shifter stop bit to logic low level.

enumerator kFLEXIO_ShifterStopBitHigh

Set shifter stop bit to logic high level.

enum _flexio_shifter_start_bit

Define type of START bit configuration.

Values:

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable

Disable shifter start bit, transmitter loads data on enable.

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift

Disable shifter start bit, transmitter loads data on first shift.

enumerator kFLEXIO_ShifterStartBitLow

Set shifter start bit to logic low level.

enumerator kFLEXIO_ShifterStartBitHigh

Set shifter start bit to logic high level.

enum _flexio_shifter_buffer_type

Define FlexIO shifter buffer type.

Values:

enumerator kFLEXIO_ShifterBuffer

Shifter Buffer N Register.

enumerator kFLEXIO_ShifterBufferBitSwapped

Shifter Buffer N Bit Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferByteSwapped

Shifter Buffer N Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferBitByteSwapped

Shifter Buffer N Bit Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleByteSwapped

Shifter Buffer N Nibble Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferHalfWordSwapped

Shifter Buffer N Half Word Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleSwapped

Shifter Buffer N Nibble Swapped Register.

enum _flexio_gpio_direction

FLEXIO gpio direction definition.

Values:

enumerator kFLEXIO_DigitalInput

Set current pin as digital input

enumerator kFLEXIO_DigitalOutput

Set current pin as digital output

enum _flexio_pin_input_config

FLEXIO gpio input config.

Values:

enumerator kFLEXIO_InputInterruptDisabled

Interrupt request is disabled.

enumerator kFLEXIO_InputInterruptEnable

Interrupt request is enable.

enumerator kFLEXIO_FlagRisingEdgeEnable

Input pin flag on rising edge.

enumerator kFLEXIO_FlagFallingEdgeEnable

Input pin flag on falling edge.

typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t

Define time of timer trigger polarity.

typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t

Define type of timer trigger source.

typedef enum _flexio_pin_config flexio_pin_config_t

Define type of timer/shifter pin configuration.

typedef enum _flexio_pin_polarity flexio_pin_polarity_t

Definition of pin polarity.

typedef enum _flexio_timer_mode flexio_timer_mode_t

Define type of timer work mode.

typedef enum _flexio_timer_output flexio_timer_output_t

Define type of timer initial output or timer reset condition.

typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t

Define type of timer decrement.

typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t

Define type of timer reset condition.

typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t

Define type of timer disable condition.

typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t

Define type of timer enable condition.

typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t

Define type of timer stop bit generate condition.

typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t

Define type of timer start bit generate condition.

typedef enum _flexio_timer_output_state flexio_timer_output_state_t

FlexIO as PWM channel output state.

typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t

Define type of timer polarity for shifter control.

typedef enum _flexio_shifter_mode flexio_shifter_mode_t

Define type of shifter working mode.

typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t

Define type of shifter input source.

typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t

Define of STOP bit configuration.

typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t

Define type of START bit configuration.

typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t

Define FlexIO shifter buffer type.

typedef struct _flexio_config_ flexio_config_t

Define FlexIO user configuration structure.

typedef struct _flexio_timer_config flexio_timer_config_t

Define FlexIO timer configuration structure.

typedef struct _flexio_shifter_config flexio_shifter_config_t

Define FlexIO shifter configuration structure.

typedef enum _flexio_gpio_direction flexio_gpio_direction_t

FLEXIO gpio direction definition.

typedef enum _flexio_pin_input_config flexio_pin_input_config_t

FLEXIO gpio input config.

typedef struct _flexio_gpio_config flexio_gpio_config_t

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

typedef void (*flexio_isr_t)(void *base, void *handle)

typedef for FlexIO simulated driver interrupt handler.

FLEXIO_Type *const s_flexioBases[]

Pointers to flexio bases for each instance.

const clock_ip_name_t s_flexioClocks[]

Pointers to flexio clocks for each instance.

void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)

Configure a FLEXIO pin used by the board.

To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
}
Define a digital output pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalOutput,
  0U,
  0U
}

Parameters:

• base – FlexIO peripheral base address

• pin – FLEXIO pin number.

• config – FLEXIO pin configuration pointer.

FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)

Calculate FlexIO timer trigger.

FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)

FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)

struct _flexio_config_

#include <fsl_flexio.h>

Define FlexIO user configuration structure.

Public Members

bool enableFlexio

Enable/disable FlexIO module

bool enableInDoze

Enable/disable FlexIO operation in doze mode

bool enableInDebug

Enable/disable FlexIO operation in debug mode

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_timer_config

#include <fsl_flexio.h>

Define FlexIO timer configuration structure.

Public Members

uint32_t triggerSelect

The internal trigger selection number using MACROs.

flexio_timer_trigger_polarity_t triggerPolarity

Trigger Polarity.

flexio_timer_trigger_source_t triggerSource

Trigger Source, internal (see ‘trgsel’) or external.

flexio_pin_config_t pinConfig

Timer Pin Configuration.

uint32_t pinSelect

Timer Pin number Select.

flexio_pin_polarity_t pinPolarity

Timer Pin Polarity.

flexio_timer_mode_t timerMode

Timer work Mode.

flexio_timer_output_t timerOutput

Configures the initial state of the Timer Output and whether it is affected by the Timer reset.

flexio_timer_decrement_source_t timerDecrement

Configures the source of the Timer decrement and the source of the Shift clock.

flexio_timer_reset_condition_t timerReset

Configures the condition that causes the timer counter (and optionally the timer output) to be reset.

flexio_timer_disable_condition_t timerDisable

Configures the condition that causes the Timer to be disabled and stop decrementing.

flexio_timer_enable_condition_t timerEnable

Configures the condition that causes the Timer to be enabled and start decrementing.

flexio_timer_stop_bit_condition_t timerStop

Timer STOP Bit generation.

flexio_timer_start_bit_condition_t timerStart

Timer STRAT Bit generation.

uint32_t timerCompare

Value for Timer Compare N Register.

struct _flexio_shifter_config

#include <fsl_flexio.h>

Define FlexIO shifter configuration structure.

Public Members

uint32_t timerSelect

Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.

flexio_shifter_timer_polarity_t timerPolarity

Timer Polarity.

flexio_pin_config_t pinConfig

Shifter Pin Configuration.

uint32_t pinSelect

Shifter Pin number Select.

flexio_pin_polarity_t pinPolarity

Shifter Pin Polarity.

flexio_shifter_mode_t shifterMode

Configures the mode of the Shifter.

uint32_t parallelWidth

Configures the parallel width when using parallel mode.

flexio_shifter_input_source_t inputSource

Selects the input source for the shifter.

flexio_shifter_stop_bit_t shifterStop

Shifter STOP bit.

flexio_shifter_start_bit_t shifterStart

Shifter START bit.

struct _flexio_gpio_config

#include <fsl_flexio.h>

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

Public Members

flexio_gpio_direction_t pinDirection

FLEXIO pin direction, input or output

uint8_t outputLogic

Set a default output logic, which has no use in input

uint8_t inputConfig

Set an input config

FlexIO eDMA I2S Driver

void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S eDMA handle.

This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer.

• callback – FlexIO I2S eDMA callback function called while finished a block.

• userData – User parameter for callback.

• dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S Rx eDMA handle.

This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer.

• callback – FlexIO I2S eDMA callback function called while finished a block.

• userData – User parameter for callback.

• dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S Tx audio format.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S eDMA handle pointer

• format – Pointer to FlexIO I2S audio data format structure.

• srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.

status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S transfer using DMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a FlexIO I2S eDMA send successfully.

• kStatus_InvalidArgument – The input arguments is invalid.

• kStatus_TxBusy – FlexIO I2S is busy sending data.

status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S receive using eDMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• xfer – Pointer to DMA transfer structure.

Return values:

• kStatus_Success – Start a FlexIO I2S eDMA receive successfully.

• kStatus_InvalidArgument – The input arguments is invalid.

• kStatus_RxBusy – FlexIO I2S is busy receiving data.

void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S transfer using eDMA.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S receive using eDMA.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• count – Bytes sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Get the remaining bytes to be received.

Parameters:

• base – FlexIO I2S peripheral base address.

• handle – FlexIO I2S DMA handle pointer.

• count – Bytes received.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION

FlexIO I2S EDMA driver version 2.1.9.

typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t

typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData)

FlexIO I2S eDMA transfer callback function for finish and error.

struct _flexio_i2s_edma_handle

#include <fsl_flexio_i2s_edma.h>

FlexIO I2S DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle

DMA handler for FlexIO I2S send

uint8_t bytesPerFrame

Bytes in a frame

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint32_t state

Internal state for FlexIO I2S eDMA transfer

flexio_i2s_edma_callback_t callback

Callback for users while transfer finish or error occurred

void *userData

User callback parameter

edma_tcd_t tcd[(4U) + 1U]

TCD pool for eDMA transfer.

flexio_i2s_transfer_t queue[(4U)]

Transfer queue storing queued transfer.

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer.

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

FlexIO eDMA SPI Driver

status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI master eDMA handle.

This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.

• callback – SPI callback, NULL means no callback.

• userData – callback function parameter.

• txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

• rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.

• xfer – Pointer to FlexIO SPI transfer structure.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI master eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

• count – Number of bytes transferred so far by the non-blocking transaction.

static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI slave eDMA handle.

This function initializes the FlexIO SPI slave eDMA handle.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

• callback – SPI callback, NULL means no callback.

• userData – callback function parameter.

• txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

• rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

• xfer – Pointer to FlexIO SPI transfer structure.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.

Parameters:

• base – Pointer to FLEXIO_SPI_Type structure.

• handle – FlexIO SPI eDMA handle pointer.

• count – Number of bytes transferred so far by the non-blocking transaction.

FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION

FlexIO SPI EDMA driver version.

typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t

typedef for flexio_spi_master_edma_handle_t in advance.

typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t

Slave handle is the same with master handle.

typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData)

FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData)

FlexIO SPI slave callback for finished transmit.

struct _flexio_spi_master_edma_handle

#include <fsl_flexio_spi_edma.h>

FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.

Public Members

size_t transferSize

Total bytes to be transferred.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

bool txInProgress

Send transfer in progress

bool rxInProgress

Receive transfer in progress

edma_handle_t *txHandle

DMA handler for SPI send

edma_handle_t *rxHandle

DMA handler for SPI receive

flexio_spi_master_edma_transfer_callback_t callback

Callback for SPI DMA transfer

void *userData

User Data for SPI DMA callback

FlexIO eDMA UART Driver

status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the UART handle which is used in transactional functions.

Parameters:

• base – Pointer to FLEXIO_UART_Type.

• handle – Pointer to flexio_uart_edma_handle_t structure.

• callback – The callback function.

• userData – The parameter of the callback function.

• rxEdmaHandle – User requested DMA handle for RX DMA transfer.

• txEdmaHandle – User requested DMA handle for TX DMA transfer.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – UART handle pointer.

• xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.

status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_UART_RxBusy – Previous transfer on going.

void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the sent data which using eDMA.

This function aborts sent data which using eDMA.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the receive data which using eDMA.

This function aborts the receive data which using eDMA.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes sent out.

This function gets the number of bytes sent out.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• count – Number of bytes sent so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received.

Parameters:

• base – Pointer to FLEXIO_UART_Type

• handle – Pointer to flexio_uart_edma_handle_t structure

• count – Number of bytes received so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

FSL_FLEXIO_UART_EDMA_DRIVER_VERSION

FlexIO UART EDMA driver version.

typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t

typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData)

UART transfer callback function.

struct _flexio_uart_edma_handle

#include <fsl_flexio_uart_edma.h>

UART eDMA handle.

Public Members

flexio_uart_edma_transfer_callback_t callback

Callback function.

void *userData

UART callback function parameter.

size_t txDataSizeAll

Total bytes to be sent.

size_t rxDataSizeAll

Total bytes to be received.

edma_handle_t *txEdmaHandle

The eDMA TX channel used.

edma_handle_t *rxEdmaHandle

The eDMA RX channel used.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

FlexIO I2C Master Driver

status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)

Make sure the bus isn’t already pulled down.

Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure..

Return values:

• kStatus_Success –

• kStatus_FLEXIO_I2C_Busy –

status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.

Example

FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• masterConfig – Pointer to flexio_i2c_master_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

Return values:

• kStatus_Success – Initialization successful

• kStatus_InvalidArgument – The source clock exceed upper range limitation

void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)

De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.

Parameters:

• base – pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().

Example:

flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);

Parameters:

• masterConfig – Pointer to flexio_i2c_master_config_t structure.

static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)

Enables/disables the FlexIO module operation.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• enable – Pass true to enable module, false does not have any effect.

uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)

Gets the FlexIO I2C master status flags.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

Returns:

Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.

void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)

Clears the FlexIO I2C master status flags.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Status flag. The parameter can be any combination of the following values:

  • kFLEXIO_I2C_RxFullFlag

  • kFLEXIO_I2C_ReceiveNakFlag

void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Enables the FlexIO i2c master interrupt requests.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Interrupt source. Currently only one interrupt request source:

  • kFLEXIO_I2C_TransferCompleteInterruptEnable

void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Disables the FlexIO I2C master interrupt requests.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• mask – Interrupt source.

void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the FlexIO I2C master transfer baudrate.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• baudRate_Bps – the baud rate value in HZ

• srcClock_Hz – source clock in HZ

void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)

Sends START + 7-bit address to the bus.

Note

This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• address – 7-bit address.

• direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:

  • kFLEXIO_I2C_Write: Transmit

  • kFLEXIO_I2C_Read: Receive

void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)

Sends the stop signal on the bus.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)

Sends the repeated start signal on the bus.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)

Sends the stop signal when transfer is still on-going.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)

Configures the sent ACK/NAK for the following byte.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• enable – True to configure send ACK, false configure to send NAK.

status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)

Sets the number of bytes to be transferred from a start signal to a stop signal.

Note

Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• count – Number of bytes need to be transferred from a start signal to a re-start/stop signal

Return values:

• kStatus_Success – Successfully configured the count.

• kStatus_InvalidArgument – Input argument is invalid.

static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)

Writes one byte of data to the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• data – a byte of data.

static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)

Reads one byte of data from the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

Returns:

data byte read.

status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)

Sends a buffer of data in bytes.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• txBuff – The data bytes to send.

• txSize – The number of data bytes to send.

Return values:

• kStatus_Success – Successfully write data.

• kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• rxBuff – The buffer to store the received bytes.

• rxSize – The number of data bytes to be received.

Return values:

• kStatus_Success – Successfully read data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to receiving NAK.

Parameters:

• base – pointer to FLEXIO_I2C_Type structure.

• xfer – pointer to flexio_i2c_master_transfer_t structure.

Returns:

status of status_t.

status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.

• callback – Pointer to user callback function.

• userData – User param passed to the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.

status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

• xfer – pointer to flexio_i2c_master_transfer_t structure

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.

status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure.

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

• kStatus_Success – Successfully return the count.

void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – Pointer to FLEXIO_I2C_Type structure

• handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)

Master interrupt handler.

Parameters:

• i2cType – Pointer to FLEXIO_I2C_Type structure

• i2cHandle – Pointer to flexio_i2c_master_transfer_t structure

FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION

FlexIO I2C transfer status.

Values:

enumerator kStatus_FLEXIO_I2C_Busy

I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Idle

I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Nak

NAK received during transfer.

enumerator kStatus_FLEXIO_I2C_Timeout

Timeout polling status flags.

enum _flexio_i2c_master_interrupt

Define FlexIO I2C master interrupt mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyInterruptEnable

Tx buffer empty interrupt enable.

enumerator kFLEXIO_I2C_RxFullInterruptEnable

Rx buffer full interrupt enable.

enum _flexio_i2c_master_status_flags

Define FlexIO I2C master status mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyFlag

Tx shifter empty flag.

enumerator kFLEXIO_I2C_RxFullFlag

Rx shifter full/Transfer complete flag.

enumerator kFLEXIO_I2C_ReceiveNakFlag

Receive NAK flag.

enum _flexio_i2c_direction

Direction of master transfer.

Values:

enumerator kFLEXIO_I2C_Write

Master send to slave.

enumerator kFLEXIO_I2C_Read

Master receive from slave.

typedef enum _flexio_i2c_direction flexio_i2c_direction_t

Direction of master transfer.

typedef struct _flexio_i2c_type FLEXIO_I2C_Type

Define FlexIO I2C master access structure typedef.

typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t

Define FlexIO I2C master user configuration structure.

typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t

Define FlexIO I2C master transfer structure.

typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t

FlexIO I2C master handle typedef.

typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData)

FlexIO I2C master transfer callback typedef.

I2C_RETRY_TIMES

Retry times for waiting flag.

struct _flexio_i2c_type

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t SDAPinIndex

Pin select for I2C SDA.

uint8_t SCLPinIndex

Pin select for I2C SCL.

uint8_t shifterIndex[2]

Shifter index used in FlexIO I2C.

uint8_t timerIndex[3]

Timer index used in FlexIO I2C.

uint32_t baudrate

Master transfer baudrate, used to calculate delay time.

struct _flexio_i2c_master_config

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master user configuration structure.

Public Members

bool enableMaster

Enables the FlexIO I2C peripheral at initialization time.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

struct _flexio_i2c_master_transfer

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master transfer structure.

Public Members

uint32_t flags

Transfer flag which controls the transfer, reserved for FlexIO I2C.

uint8_t slaveAddress

7-bit slave address.

flexio_i2c_direction_t direction

Transfer direction, read or write.

uint32_t subaddress

Sub address. Transferred MSB first.

uint8_t subaddressSize

Size of sub address.

uint8_t volatile *data

Transfer buffer.

volatile size_t dataSize

Transfer size.

struct _flexio_i2c_master_handle

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master handle structure.

Public Members

flexio_i2c_master_transfer_t transfer

FlexIO I2C master transfer copy.

size_t transferSize

Total bytes to be transferred.

uint8_t state

Transfer state maintained during transfer.

flexio_i2c_master_transfer_callback_t completionCallback

Callback function called at transfer event. Callback function called at transfer event.

void *userData

Callback parameter passed to callback function.

bool needRestart

Whether master needs to send re-start signal.

FlexIO I2S Driver

void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)

Initializes the FlexIO I2S.

This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.

Parameters:

• base – FlexIO I2S base pointer

• config – FlexIO I2S configure structure.

void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)

Sets the FlexIO I2S configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().

Parameters:

• config – pointer to master configuration structure

void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)

De-initializes the FlexIO I2S.

Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.

Parameters:

• base – FlexIO I2S base pointer

static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S module operation.

Parameters:

• base – Pointer to FLEXIO_I2S_Type

• enable – True to enable, false dose not have any effect.

uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S status flags.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.

void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Enables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• mask – interrupt source

void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Disables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – pointer to FLEXIO_I2S_Type structure

• mask – interrupt source

static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Tx DMA requests.

Parameters:

• base – FlexIO I2S base pointer

• enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Rx DMA requests.

Parameters:

• base – FlexIO I2S base pointer

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S send data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s send data register address.

static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S receive data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s receive data register address.

void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format in master mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• format – Pointer to FlexIO I2S audio data format structure.

• srcClock_Hz – I2S master clock source frequency in Hz.

void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)

Configures the FlexIO I2S audio format in slave mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• format – Pointer to FlexIO I2S audio data format structure.

status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)

Sends data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

• base – FlexIO I2S base pointer.

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• txData – Pointer to the data to be written.

• size – Bytes to be written.

Return values:

• kStatus_Success – Successfully write data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)

Writes data into a data register.

Parameters:

• base – FlexIO I2S base pointer.

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• data – Data to be written.

status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)

Receives a piece of data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

• base – FlexIO I2S base pointer

• bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.

• rxData – Pointer to the data to be read.

• size – Bytes to be read.

Return values:

• kStatus_Success – Successfully read data.

• kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)

Reads a data from the data register.

Parameters:

• base – FlexIO I2S base pointer

Returns:

Data read from data register.

void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure

• handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.

• callback – FlexIO I2S callback function, which is called while finished a block.

• userData – User parameter for the FlexIO I2S callback.

void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format.

Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – FlexIO I2S handle pointer.

• format – Pointer to audio data format structure.

• srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.

void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S receive handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.

• callback – FlexIO I2S callback function, which is called while finished a block.

• userData – User parameter for the FlexIO I2S callback.

status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.

• kStatus_InvalidArgument – The input parameter is invalid.

status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

• kStatus_Success – Successfully start the data receive.

• kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.

• kStatus_InvalidArgument – The input parameter is invalid.

void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current send.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current receive.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• count – Bytes sent.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be received.

Parameters:

• base – Pointer to FLEXIO_I2S_Type structure.

• handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

• count – Bytes recieved.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

Returns:

count Bytes received.

void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)

Tx interrupt handler.

Parameters:

• i2sBase – Pointer to FLEXIO_I2S_Type structure.

• i2sHandle – Pointer to flexio_i2s_handle_t structure

void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)

Rx interrupt handler.

Parameters:

• i2sBase – Pointer to FLEXIO_I2S_Type structure.

• i2sHandle – Pointer to flexio_i2s_handle_t structure.

FSL_FLEXIO_I2S_DRIVER_VERSION

FlexIO I2S driver version 2.2.2.

FlexIO I2S transfer status.

Values:

enumerator kStatus_FLEXIO_I2S_Idle

FlexIO I2S is in idle state

enumerator kStatus_FLEXIO_I2S_TxBusy

FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_RxBusy

FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_Error

FlexIO I2S error occurred

enumerator kStatus_FLEXIO_I2S_QueueFull

FlexIO I2S transfer queue is full.

enumerator kStatus_FLEXIO_I2S_Timeout

FlexIO I2S timeout polling status flags.

enum _flexio_i2s_master_slave

Master or slave mode.

Values:

enumerator kFLEXIO_I2S_Master

Master mode

enumerator kFLEXIO_I2S_Slave

Slave mode

_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable

Receive buffer full interrupt enable.

_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_I2S_RxDataRegFullFlag

Receive buffer full flag.

enum _flexio_i2s_sample_rate

Audio sample rate.

Values:

enumerator kFLEXIO_I2S_SampleRate8KHz

Sample rate 8000Hz

enumerator kFLEXIO_I2S_SampleRate11025Hz

Sample rate 11025Hz

enumerator kFLEXIO_I2S_SampleRate12KHz

Sample rate 12000Hz

enumerator kFLEXIO_I2S_SampleRate16KHz

Sample rate 16000Hz

enumerator kFLEXIO_I2S_SampleRate22050Hz

Sample rate 22050Hz

enumerator kFLEXIO_I2S_SampleRate24KHz

Sample rate 24000Hz

enumerator kFLEXIO_I2S_SampleRate32KHz

Sample rate 32000Hz

enumerator kFLEXIO_I2S_SampleRate44100Hz

Sample rate 44100Hz

enumerator kFLEXIO_I2S_SampleRate48KHz

Sample rate 48000Hz

enumerator kFLEXIO_I2S_SampleRate96KHz

Sample rate 96000Hz

enum _flexio_i2s_word_width

Audio word width.

Values:

enumerator kFLEXIO_I2S_WordWidth8bits

Audio data width 8 bits

enumerator kFLEXIO_I2S_WordWidth16bits

Audio data width 16 bits

enumerator kFLEXIO_I2S_WordWidth24bits

Audio data width 24 bits

enumerator kFLEXIO_I2S_WordWidth32bits

Audio data width 32 bits

typedef struct _flexio_i2s_type FLEXIO_I2S_Type

Define FlexIO I2S access structure typedef.

typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t

Master or slave mode.

typedef struct _flexio_i2s_config flexio_i2s_config_t

FlexIO I2S configure structure.

typedef struct _flexio_i2s_format flexio_i2s_format_t

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t

Audio sample rate.

typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t

Audio word width.

typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t

Define FlexIO I2S transfer structure.

typedef struct _flexio_i2s_handle flexio_i2s_handle_t

typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData)

FlexIO I2S xfer callback prototype.

I2S_RETRY_TIMES

Retry times for waiting flag.

FLEXIO_I2S_XFER_QUEUE_SIZE

FlexIO I2S transfer queue size, user can refine it according to use case.

struct _flexio_i2s_type

#include <fsl_flexio_i2s.h>

Define FlexIO I2S access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer

uint8_t txPinIndex

Tx data pin index in FlexIO pins

uint8_t rxPinIndex

Rx data pin index

uint8_t bclkPinIndex

Bit clock pin index

uint8_t fsPinIndex

Frame sync pin index

uint8_t txShifterIndex

Tx data shifter index

uint8_t rxShifterIndex

Rx data shifter index

uint8_t bclkTimerIndex

Bit clock timer index

uint8_t fsTimerIndex

Frame sync timer index

struct _flexio_i2s_config

#include <fsl_flexio_i2s.h>

FlexIO I2S configure structure.

Public Members

bool enableI2S

Enable FlexIO I2S

flexio_i2s_master_slave_t masterSlave

Master or slave

flexio_pin_polarity_t txPinPolarity

Tx data pin polarity, active high or low

flexio_pin_polarity_t rxPinPolarity

Rx data pin polarity

flexio_pin_polarity_t bclkPinPolarity

Bit clock pin polarity

flexio_pin_polarity_t fsPinPolarity

Frame sync pin polarity

flexio_shifter_timer_polarity_t txTimerPolarity

Tx data valid on bclk rising or falling edge

flexio_shifter_timer_polarity_t rxTimerPolarity

Rx data valid on bclk rising or falling edge

struct _flexio_i2s_format

#include <fsl_flexio_i2s.h>

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

Public Members

uint8_t bitWidth

Bit width of audio data, always 8/16/24/32 bits

uint32_t sampleRate_Hz

Sample rate of the audio data

struct _flexio_i2s_transfer

#include <fsl_flexio_i2s.h>

Define FlexIO I2S transfer structure.

Public Members

uint8_t *data

Data buffer start pointer

size_t dataSize

Bytes to be transferred.

struct _flexio_i2s_handle

#include <fsl_flexio_i2s.h>

Define FlexIO I2S handle structure.

Public Members

uint32_t state

Internal state

flexio_i2s_callback_t callback

Callback function called at transfer event

void *userData

Callback parameter passed to callback function

uint8_t bitWidth

Bit width for transfer, 8/16/24/32bits

flexio_i2s_transfer_t queue[(4U)]

Transfer queue storing queued transfer

size_t transferSize[(4U)]

Data bytes need to transfer

volatile uint8_t queueUser

Index for user to queue transfer

volatile uint8_t queueDriver

Index for driver to get the transfer data and size

FlexIO SPI Driver

void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().

Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);

Note

1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• masterConfig – Pointer to the flexio_spi_master_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)

Resets the FlexIO SPI timer and shifter config.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:

flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

• masterConfig – Pointer to the flexio_spi_master_config_t structure.

void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().

Note

1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)

Gates the FlexIO clock.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)

Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:

flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

• slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)

Gets FlexIO SPI status flags.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

Returns:

status flag; Use the status flag to AND the following flag mask and get the status.

• kFLEXIO_SPI_TxEmptyFlag

• kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)

Clears FlexIO SPI status flags.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – status flag The parameter can be any combination of the following values:

  • kFLEXIO_SPI_TxEmptyFlag

  • kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Enables the FlexIO SPI interrupt.

This function enables the FlexIO SPI interrupt.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – interrupt source. The parameter can be any combination of the following values:

  • kFLEXIO_SPI_RxFullInterruptEnable

  • kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Disables the FlexIO SPI interrupt.

This function disables the FlexIO SPI interrupt.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – interrupt source The parameter can be any combination of the following values:

  • kFLEXIO_SPI_RxFullInterruptEnable

  • kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)

Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• mask – SPI DMA source.

• enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI transmit data register address for MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI transmit data register address.

static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI receive data register address for the MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI receive data register address.

static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)

Enables/disables the FlexIO SPI module operation.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type.

• enable – True to enable, false does not have any effect.

void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)

Sets baud rate for the FlexIO SPI transfer, which is only used for the master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• baudRate_Bps – Baud Rate needed in Hz.

• srcClockHz – SPI source clock frequency in Hz.

static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)

Writes one byte of data, which is sent using the MSB method.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• data – 8/16/32 bit data.

static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Reads 8 bit/16 bit data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

Returns:

8 bit/16 bit data received.

status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• buffer – The data bytes to send.

• size – The number of data bytes to send.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• direction – Shift direction of MSB first or LSB first.

• buffer – The buffer to store the received bytes.

• size – The number of data bytes to be received.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

• base – pointer to FLEXIO_SPI_Type structure

• xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)

Flush tx/rx shifters.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Master handle, which is used in transactional functions.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)

Master transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)

Aborts the master data transfer, which used IRQ.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI master IRQ handler function.

Parameters:

• spiType – Pointer to the FLEXIO_SPI_Type structure.

• spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Slave handle, which is used in transactional functions.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)

Slave transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• base – Pointer to the FLEXIO_SPI_Type structure.

• xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

• kStatus_Success – Successfully start a transfer.

• kStatus_InvalidArgument – Input argument is invalid.

• kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)

Aborts the slave data transfer which used IRQ, share same API with master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ, share same API with master.

Parameters:

• base – Pointer to the FLEXIO_SPI_Type structure.

• handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI slave IRQ handler function.

Parameters:

• spiType – Pointer to the FLEXIO_SPI_Type structure.

• spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

FSL_FLEXIO_SPI_DRIVER_VERSION

FlexIO SPI driver version.

Error codes for the FlexIO SPI driver.

Values:

enumerator kStatus_FLEXIO_SPI_Busy

FlexIO SPI is busy.

enumerator kStatus_FLEXIO_SPI_Idle

SPI is idle

enumerator kStatus_FLEXIO_SPI_Error

FlexIO SPI error.

enumerator kStatus_FLEXIO_SPI_Timeout

FlexIO SPI timeout polling status flags.

enum _flexio_spi_clock_phase

FlexIO SPI clock phase configuration.

Values:

enumerator kFLEXIO_SPI_ClockPhaseFirstEdge

First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kFLEXIO_SPI_ClockPhaseSecondEdge

First edge on SPSCK occurs at the start of the first cycle of a data transfer.

enum _flexio_spi_shift_direction

FlexIO SPI data shifter direction options.

Values:

enumerator kFLEXIO_SPI_MsbFirst

Data transfers start with most significant bit.

enumerator kFLEXIO_SPI_LsbFirst

Data transfers start with least significant bit.

enum _flexio_spi_data_bitcount_mode

FlexIO SPI data length mode options.

Values:

enumerator kFLEXIO_SPI_8BitMode

8-bit data transmission mode.

enumerator kFLEXIO_SPI_16BitMode

16-bit data transmission mode.

enumerator kFLEXIO_SPI_32BitMode

32-bit data transmission mode.

enum _flexio_spi_interrupt_enable

Define FlexIO SPI interrupt mask.

Values:

enumerator kFLEXIO_SPI_TxEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_SPI_RxFullInterruptEnable

Receive buffer full interrupt enable.

enum _flexio_spi_status_flags

Define FlexIO SPI status mask.

Values:

enumerator kFLEXIO_SPI_TxBufferEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_SPI_RxBufferFullFlag

Receive buffer full flag.

enum _flexio_spi_dma_enable

Define FlexIO SPI DMA mask.

Values:

enumerator kFLEXIO_SPI_TxDmaEnable

Tx DMA request source

enumerator kFLEXIO_SPI_RxDmaEnable

Rx DMA request source

enumerator kFLEXIO_SPI_DmaAllEnable

All DMA request source

enum _flexio_spi_transfer_flags

Define FlexIO SPI transfer flags.

Note

Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.

Values:

enumerator kFLEXIO_SPI_8bitMsb

FlexIO SPI 8-bit MSB first

enumerator kFLEXIO_SPI_8bitLsb

FlexIO SPI 8-bit LSB first

enumerator kFLEXIO_SPI_16bitMsb

FlexIO SPI 16-bit MSB first

enumerator kFLEXIO_SPI_16bitLsb

FlexIO SPI 16-bit LSB first

enumerator kFLEXIO_SPI_32bitMsb

FlexIO SPI 32-bit MSB first

enumerator kFLEXIO_SPI_32bitLsb

FlexIO SPI 32-bit LSB first

enumerator kFLEXIO_SPI_csContinuous

Enable the CS signal continuous mode

typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t

FlexIO SPI clock phase configuration.

typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t

FlexIO SPI data shifter direction options.

typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t

FlexIO SPI data length mode options.

typedef struct _flexio_spi_type FLEXIO_SPI_Type

Define FlexIO SPI access structure typedef.

typedef struct _flexio_spi_master_config flexio_spi_master_config_t

Define FlexIO SPI master configuration structure.

typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t

Define FlexIO SPI slave configuration structure.

typedef struct _flexio_spi_transfer flexio_spi_transfer_t

Define FlexIO SPI transfer structure.

typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t

typedef for flexio_spi_master_handle_t in advance.

typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t

Slave handle is the same with master handle.

typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData)

FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData)

FlexIO SPI slave callback for finished transmit.

FLEXIO_SPI_DUMMYDATA

FlexIO SPI dummy transfer data, the data is sent while txData is NULL.

SPI_RETRY_TIMES

Retry times for waiting flag.

FLEXIO_SPI_XFER_DATA_FORMAT(flag)

Get the transfer data format of width and bit order.

struct _flexio_spi_type

#include <fsl_flexio_spi.h>

Define FlexIO SPI access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t SDOPinIndex

Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.

uint8_t SDIPinIndex

Pin select for data input.

uint8_t SCKPinIndex

Pin select for clock.

uint8_t CSnPinIndex

Pin select for enable.

uint8_t shifterIndex[2]

Shifter index used in FlexIO SPI.

uint8_t timerIndex[2]

Timer index used in FlexIO SPI.

struct _flexio_spi_master_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI master configuration structure.

Public Members

bool enableMaster

Enable/disable FlexIO SPI master after configuration.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

flexio_spi_clock_phase_t phase

Clock phase.

flexio_spi_data_bitcount_mode_t dataMode

8bit or 16bit mode.

struct _flexio_spi_slave_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI slave configuration structure.

Public Members

bool enableSlave

Enable/disable FlexIO SPI slave after configuration.

bool enableInDoze

Enable/disable FlexIO operation in doze mode.

bool enableInDebug

Enable/disable FlexIO operation in debug mode.

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_spi_clock_phase_t phase

Clock phase.

flexio_spi_data_bitcount_mode_t dataMode

8bit or 16bit mode.

struct _flexio_spi_transfer

#include <fsl_flexio_spi.h>

Define FlexIO SPI transfer structure.

Public Members

const uint8_t *txData

Send buffer.

uint8_t *rxData

Receive buffer.

size_t dataSize

Transfer bytes.

uint8_t flags

FlexIO SPI control flag, MSB first or LSB first.

struct _flexio_spi_master_handle

#include <fsl_flexio_spi.h>

Define FlexIO SPI handle structure.

Public Members

const uint8_t *txData

Transfer buffer.

uint8_t *rxData

Receive buffer.

size_t transferSize

Total bytes to be transferred.

volatile size_t txRemainingBytes

Send data remaining in bytes.

volatile size_t rxRemainingBytes

Receive data remaining in bytes.

volatile uint32_t state

FlexIO SPI internal state.

uint8_t bytePerFrame

SPI mode, 2bytes or 1byte in a frame

flexio_spi_shift_direction_t direction

Shift direction.

flexio_spi_master_transfer_callback_t callback

FlexIO SPI callback.

void *userData

Callback parameter.

bool isCsContinuous

Is current transfer using CS continuous mode.

uint32_t timer1Cfg

TIMER1 TIMCFG regiser value backup.

FlexIO UART Driver

status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().

Example

FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• userConfig – Pointer to the flexio_uart_config_t structure.

• srcClock_Hz – FlexIO source clock in Hz.

Return values:

• kStatus_Success – Configuration success.

• kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)

Resets the FlexIO UART shifter and timer config.

Note

After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.

Parameters:

• base – Pointer to FLEXIO_UART_Type structure

void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)

Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:

flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);

Parameters:

• userConfig – Pointer to the flexio_uart_config_t structure.

uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)

Gets the FlexIO UART status flags.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART status flags.

void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)

Gets the FlexIO UART status flags.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Status flag. The parameter can be any combination of the following values:

  • kFLEXIO_UART_TxDataRegEmptyFlag

  • kFLEXIO_UART_RxEmptyFlag

  • kFLEXIO_UART_RxOverRunFlag

void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Enables the FlexIO UART interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Interrupt source.

void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Disables the FlexIO UART interrupt.

This function disables the FlexIO UART interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• mask – Interrupt source.

static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UARt transmit data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART transmit data register address.

static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UART receive data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART receive data register address.

static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• enable – True to enable, false to disable.

static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• enable – True to enable, false to disable.

static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART module operation.

Parameters:

• base – Pointer to the FLEXIO_UART_Type.

• enable – True to enable, false does not have any effect.

static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• buffer – The data bytes to send.

static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• buffer – The buffer to store the received bytes.

status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• txData – The data bytes to send.

• txSize – The number of data bytes to send.

Return values:

• kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• rxData – The buffer to store the received bytes.

• rxSize – The number of data bytes to be received.

Return values:

• kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)

Initializes the UART handle.

This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.

The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

• base – to FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• callback – The callback function.

• userData – The parameter of the callback function.

Return values:

• kStatus_Success – Successfully create the handle.

• kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.

• ringBufferSize – Size of the ring buffer.

void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.

Note

The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.

Return values:

• kStatus_Success – Successfully starts the data transmission.

• kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• count – Number of bytes sent so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• xfer – UART transfer structure. See flexio_uart_transfer_t.

• receivedBytes – Bytes received from the ring buffer directly.

Return values:

• kStatus_Success – Successfully queue the transfer into the transmit queue.

• kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.

void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

• handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

• count – Number of bytes received so far by the non-blocking transaction.

Return values:

• kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.

• kStatus_Success – Successfully return the count.

void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)

FlexIO UART IRQ handler function.

This function processes the FlexIO UART transmit and receives the IRQ request.

Parameters:

• uartType – Pointer to the FLEXIO_UART_Type structure.

• uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)

Flush tx/rx shifters.

Parameters:

• base – Pointer to the FLEXIO_UART_Type structure.

FSL_FLEXIO_UART_DRIVER_VERSION

FlexIO UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_FLEXIO_UART_TxBusy

Transmitter is busy.

enumerator kStatus_FLEXIO_UART_RxBusy

Receiver is busy.

enumerator kStatus_FLEXIO_UART_TxIdle

UART transmitter is idle.

enumerator kStatus_FLEXIO_UART_RxIdle

UART receiver is idle.

enumerator kStatus_FLEXIO_UART_ERROR

ERROR happens on UART.

enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun

UART RX software ring buffer overrun.

enumerator kStatus_FLEXIO_UART_RxHardwareOverrun

UART RX receiver overrun.

enumerator kStatus_FLEXIO_UART_Timeout

UART times out.

enumerator kStatus_FLEXIO_UART_BaudrateNotSupport

Baudrate is not supported in current clock source

enum _flexio_uart_bit_count_per_char

FlexIO UART bit count per char.

Values:

enumerator kFLEXIO_UART_7BitsPerChar

7-bit data characters

enumerator kFLEXIO_UART_8BitsPerChar

8-bit data characters

enumerator kFLEXIO_UART_9BitsPerChar

9-bit data characters

enum _flexio_uart_interrupt_enable

Define FlexIO UART interrupt mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable

Transmit buffer empty interrupt enable.

enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable

Receive buffer full interrupt enable.

enum _flexio_uart_status_flags

Define FlexIO UART status mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyFlag

Transmit buffer empty flag.

enumerator kFLEXIO_UART_RxDataRegFullFlag

Receive buffer full flag.

enumerator kFLEXIO_UART_RxOverRunFlag

Receive buffer over run flag.

typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t

FlexIO UART bit count per char.

typedef struct _flexio_uart_type FLEXIO_UART_Type

Define FlexIO UART access structure typedef.

typedef struct _flexio_uart_config flexio_uart_config_t

Define FlexIO UART user configuration structure.

typedef struct _flexio_uart_transfer flexio_uart_transfer_t

Define FlexIO UART transfer structure.

typedef struct _flexio_uart_handle flexio_uart_handle_t

typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData)

FlexIO UART transfer callback function.

UART_RETRY_TIMES

Retry times for waiting flag.

struct _flexio_uart_type

#include <fsl_flexio_uart.h>

Define FlexIO UART access structure typedef.

Public Members

FLEXIO_Type *flexioBase

FlexIO base pointer.

uint8_t TxPinIndex

Pin select for UART_Tx.

uint8_t RxPinIndex

Pin select for UART_Rx.

uint8_t shifterIndex[2]

Shifter index used in FlexIO UART.

uint8_t timerIndex[2]

Timer index used in FlexIO UART.

struct _flexio_uart_config

#include <fsl_flexio_uart.h>

Define FlexIO UART user configuration structure.

Public Members

bool enableUart

Enable/disable FlexIO UART TX & RX.

bool enableInDoze

Enable/disable FlexIO operation in doze mode

bool enableInDebug

Enable/disable FlexIO operation in debug mode

bool enableFastAccess

Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps

Baud rate in Bps.

flexio_uart_bit_count_per_char_t bitCountPerChar

number of bits, 7/8/9 -bit

struct _flexio_uart_transfer

#include <fsl_flexio_uart.h>

Define FlexIO UART transfer structure.

Public Members

size_t dataSize

Transfer size

struct _flexio_uart_handle

#include <fsl_flexio_uart.h>

Define FLEXIO UART handle structure.

Public Members

const uint8_t *volatile txData

Address of remaining data to send.

volatile size_t txDataSize

Size of the remaining data to send.

uint8_t *volatile rxData

Address of remaining data to receive.

volatile size_t rxDataSize

Size of the remaining data to receive.

size_t txDataSizeAll

Total bytes to be sent.

size_t rxDataSizeAll

Total bytes to be received.

uint8_t *rxRingBuffer

Start address of the receiver ring buffer.

size_t rxRingBufferSize

Size of the ring buffer.

volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer.

flexio_uart_transfer_callback_t callback

Callback function.

void *userData

UART callback function parameter.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

union __unnamed262__

Public Members

uint8_t *data

The buffer of data to be transfer.

uint8_t *rxData

The buffer to receive data.

const uint8_t *txData

The buffer of data to be sent.

FLEXSPI: Flexible Serial Peripheral Interface Driver

uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)

Get the instance number for FLEXSPI.

Parameters:

• base – FLEXSPI base pointer.

status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)

Check and clear IP command execution errors.

Parameters:

• base – FLEXSPI base pointer.

• status – interrupt status.

void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)

Initializes the FLEXSPI module and internal state.

This function enables the clock for FLEXSPI and also configures the FLEXSPI with the input configure parameters. Users should call this function before any FLEXSPI operations.

Parameters:

• base – FLEXSPI peripheral base address.

• config – FLEXSPI configure structure.

void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)

Gets default settings for FLEXSPI.

Parameters:

• config – FLEXSPI configuration structure.

void FLEXSPI_Deinit(FLEXSPI_Type *base)

Deinitializes the FLEXSPI module.

Clears the FLEXSPI state and FLEXSPI module registers.

Parameters:

• base – FLEXSPI peripheral base address.

void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Update FLEXSPI DLL value depending on currently flexspi root clock.

Parameters:

• base – FLEXSPI peripheral base address.

• config – Flash configuration parameters.

• port – FLEXSPI Operation port.

void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Configures the connected device parameter.

This function configures the connected device relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the connected device.

Parameters:

• base – FLEXSPI peripheral base address.

• config – Flash configuration parameters.

• port – FLEXSPI Operation port.

void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)

Software reset for the FLEXSPI logic.

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

Parameters:

• base – FLEXSPI peripheral base address.

static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)

Enables or disables the FLEXSPI module.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – True means enable FLEXSPI, false means disable.

void FLEXSPI_UpdateAhbBuffersSettings(FLEXSPI_Type *base, flexspi_ahbBuffers_ctrl_t *ptrAhbBufferCtrl)

Update all AHB buffers’ settings, including buffer size, master ID.

Parameters:

• base – FLEXSPI peripheral base address.

• ptrAhbBufferCtrl – Pointer to structure flexspi_ahbBuffers_ctrl_t which store all AHB buffers’ settings.

static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Enables the FLEXSPI interrupts.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Disable the FLEXSPI interrupts.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Tx FIFO DMA requests.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – Enable flag for transmit DMA request. Pass true for enable, false for disable.

static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Rx FIFO DMA requests.

Parameters:

• base – FLEXSPI peripheral base address.

• enable – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP tx fifo address for DMA transfer.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

The – tx fifo address.

static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP rx fifo address for DMA transfer.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

The – rx fifo address.

static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)

Clears the FLEXSPI IP FIFO logic.

Parameters:

• base – FLEXSPI peripheral base address.

• txFifo – Pass true to reset TX FIFO.

• rxFifo – Pass true to reset RX FIFO.

static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)

Gets the valid data entries in the FLEXSPI FIFOs.

Parameters:

• base – FLEXSPI peripheral base address.

• txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)

Get the FLEXSPI interrupt status flags.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

interrupt – status flag, use status flag to AND flexspi_flags_t could get the related status.

static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)

Get the FLEXSPI interrupt status flags.

Parameters:

• base – FLEXSPI peripheral base address.

• mask – FLEXSPI interrupt source.

static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)

Gets the trigger source of current command sequence granted by arbitrator.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

trigger – source of current command sequence.

static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when IP command error detected.

Parameters:

• base – FLEXSPI peripheral base address.

• index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when IP command error detected.

static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when AHB command error detected.

Parameters:

• base – FLEXSPI peripheral base address.

• index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when AHB command error detected.

static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)

Returns whether the bus is idle.

Parameters:

• base – FLEXSPI peripheral base address.

Return values:

• true – Bus is idle.

• false – Bus is busy.

void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)

Update read sample clock source.

Parameters:

• base – FLEXSPI peripheral base address.

• clockSource – clockSource of type flexspi_read_sample_clock_t

void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)

Updates the LUT table.

Parameters:

• base – FLEXSPI peripheral base address.

• index – From which index start to update. It could be any index of the LUT table, which also allows user to update command content inside a command. Each command consists of up to 8 instructions and occupy 4*32-bit memory.

• cmd – Command sequence array.

• count – Number of sequences.

static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)

Writes data into FIFO.

Parameters:

• base – FLEXSPI peripheral base address

• data – The data bytes to send

• fifoIndex – Destination fifo index.

static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)

Receives data from data FIFO.

Parameters:

• base – FLEXSPI peripheral base address

• fifoIndex – Source fifo index.

Returns:

The data in the FIFO.

status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Sends a buffer of data bytes using blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – FLEXSPI peripheral base address

• buffer – The data bytes to send

• size – The number of data bytes to send

Return values:

• kStatus_Success – write success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

• base – FLEXSPI peripheral base address

• buffer – The data bytes to send

• size – The number of data bytes to receive

Return values:

• kStatus_Success – read success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequencen error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)

Execute command to transfer a buffer data bytes using a blocking method.

Parameters:

• base – FLEXSPI peripheral base address

• xfer – pointer to the transfer structure.

Return values:

• kStatus_Success – command transfer success without error

• kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout

• kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected

• kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData)

Initializes the FLEXSPI handle which is used in transactional functions.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure to store the transfer state.

• callback – pointer to user callback function.

• userData – user parameter passed to the callback function.

status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)

Performs a interrupt non-blocking transfer on the FLEXSPI bus.

Note

Calling the API returns immediately after transfer initiates. The user needs to call FLEXSPI_GetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or FLEXSPI could not read data properly.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state.

• xfer – pointer to flexspi_transfer_t structure.

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_FLEXSPI_Busy – Previous transmission still not finished.

status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_InvalidArgument – count is Invalid.

• kStatus_Success – Successfully return the count.

void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure which stores the transfer state

void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)

Master interrupt handler.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – pointer to flexspi_handle_t structure.

FSL_FLEXSPI_DRIVER_VERSION

FLEXSPI driver version.

Status structure of FLEXSPI.

Values:

enumerator kStatus_FLEXSPI_Busy

FLEXSPI is busy

enumerator kStatus_FLEXSPI_SequenceExecutionTimeout

Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandSequenceError

IP command Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandGrantTimeout

IP command grant timeout error occurred during FLEXSPI transfer.

CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command.

Values:

enumerator kFLEXSPI_Command_STOP

Stop execution, deassert CS.

enumerator kFLEXSPI_Command_SDR

Transmit Command code to Flash, using SDR mode.

enumerator kFLEXSPI_Command_RADDR_SDR

Transmit Row Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_CADDR_SDR

Transmit Column Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE1_SDR

Transmit 1-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE2_SDR

Transmit 2-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE4_SDR

Transmit 4-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE8_SDR

Transmit 8-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_WRITE_SDR

Transmit Programming Data to Flash, using SDR mode.

enumerator kFLEXSPI_Command_READ_SDR

Receive Read Data from Flash, using SDR mode.

enumerator kFLEXSPI_Command_LEARN_SDR

Receive Read Data or Preamble bit from Flash, SDR mode.

enumerator kFLEXSPI_Command_DATSZ_SDR

Transmit Read/Program Data size (byte) to Flash, SDR mode.

enumerator kFLEXSPI_Command_DUMMY_SDR

Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_SDR

Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_DDR

Transmit Command code to Flash, using DDR mode.

enumerator kFLEXSPI_Command_RADDR_DDR

Transmit Row Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_CADDR_DDR

Transmit Column Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE1_DDR

Transmit 1-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE2_DDR

Transmit 2-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE4_DDR

Transmit 4-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE8_DDR

Transmit 8-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_WRITE_DDR

Transmit Programming Data to Flash, using DDR mode.

enumerator kFLEXSPI_Command_READ_DDR

Receive Read Data from Flash, using DDR mode.

enumerator kFLEXSPI_Command_LEARN_DDR

Receive Read Data or Preamble bit from Flash, DDR mode.

enumerator kFLEXSPI_Command_DATSZ_DDR

Transmit Read/Program Data size (byte) to Flash, DDR mode.

enumerator kFLEXSPI_Command_DUMMY_DDR

Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_DDR

Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_JUMP_ON_CS

Stop execution, deassert CS and save operand[7:0] as the instruction start pointer for next sequence

enum _flexspi_pad

pad definition of FLEXSPI, use to form LUT instruction.

Values:

enumerator kFLEXSPI_1PAD

Transmit command/address and transmit/receive data only through DATA0/DATA1.

enumerator kFLEXSPI_2PAD

Transmit command/address and transmit/receive data only through DATA[1:0].

enumerator kFLEXSPI_4PAD

Transmit command/address and transmit/receive data only through DATA[3:0].

enumerator kFLEXSPI_8PAD

Transmit command/address and transmit/receive data only through DATA[7:0].

enum _flexspi_flags

FLEXSPI interrupt status flags.

Values:

enumerator kFLEXSPI_SequenceExecutionTimeoutFlag

Sequence execution timeout.

enumerator kFLEXSPI_AhbBusErrorFlag

AHB Bus error flag.

enumerator kFLEXSPI_SckStoppedBecauseTxEmptyFlag

SCK is stopped during command sequence because Async TX FIFO empty.

enumerator kFLEXSPI_SckStoppedBecauseRxFullFlag

SCK is stopped during command sequence because Async RX FIFO full.

enumerator kFLEXSPI_IpTxFifoWatermarkEmptyFlag

IP TX FIFO WaterMark empty.

enumerator kFLEXSPI_IpRxFifoWatermarkAvailableFlag

IP RX FIFO WaterMark available.

enumerator kFLEXSPI_AhbCommandSequenceErrorFlag

AHB triggered Command Sequences Error.

enumerator kFLEXSPI_IpCommandSequenceErrorFlag

IP triggered Command Sequences Error.

enumerator kFLEXSPI_AhbCommandGrantTimeoutFlag

AHB triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandGrantTimeoutFlag

IP triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandExecutionDoneFlag

IP triggered Command Sequences Execution finished.

enumerator kFLEXSPI_AllInterruptFlags

All flags.

enum _flexspi_read_sample_clock

FLEXSPI sample clock source selection for Flash Reading.

Values:

enumerator kFLEXSPI_ReadSampleClkLoopbackInternally

Dummy Read strobe generated by FlexSPI Controller and loopback internally.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromDqsPad

Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromSckPad

SCK output clock and loopback from SCK pad.

enumerator kFLEXSPI_ReadSampleClkExternalInputFromDqsPad

Flash provided Read strobe and input from DQS pad.

enum _flexspi_cs_interval_cycle_unit

FLEXSPI interval unit for flash device select.

Values:

enumerator kFLEXSPI_CsIntervalUnit1SckCycle

Chip selection interval: CSINTERVAL * 1 serial clock cycle.

enumerator kFLEXSPI_CsIntervalUnit256SckCycle

Chip selection interval: CSINTERVAL * 256 serial clock cycle.

enum _flexspi_ahb_write_wait_unit

FLEXSPI AHB wait interval unit for writing.

Values:

enumerator kFLEXSPI_AhbWriteWaitUnit2AhbCycle

AWRWAIT unit is 2 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8AhbCycle

AWRWAIT unit is 8 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32AhbCycle

AWRWAIT unit is 32 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit128AhbCycle

AWRWAIT unit is 128 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit512AhbCycle

AWRWAIT unit is 512 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit2048AhbCycle

AWRWAIT unit is 2048 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8192AhbCycle

AWRWAIT unit is 8192 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32768AhbCycle

AWRWAIT unit is 32768 ahb clock cycle.

enum _flexspi_ip_error_code

Error Code when IP command Error detected.

Values:

enumerator kFLEXSPI_IpCmdErrorNoError

No error.

enumerator kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd

IP command with JMP_ON_CS instruction used.

enumerator kFLEXSPI_IpCmdErrorUnknownOpCode

Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence

Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence

Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_IpCmdErrorInvalidAddress

Flash access start address exceed the whole flash address range (A1/A2/B1/B2).

enumerator kFLEXSPI_IpCmdErrorSequenceExecutionTimeout

Sequence execution timeout.

enumerator kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss

Flash boundary crossed.

enum _flexspi_ahb_error_code

Error Code when AHB command Error detected.

Values:

enumerator kFLEXSPI_AhbCmdErrorNoError

No error.

enumerator kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd

AHB Write command with JMP_ON_CS instruction used in the sequence.

enumerator kFLEXSPI_AhbCmdErrorUnknownOpCode

Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence

Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence

Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_AhbCmdSequenceExecutionTimeout

Sequence execution timeout.

enum _flexspi_port

FLEXSPI operation port select.

Values:

enumerator kFLEXSPI_PortA1

Access flash on A1 port.

enumerator kFLEXSPI_PortA2

Access flash on A2 port.

enumerator kFLEXSPI_PortB1

Access flash on B1 port.

enumerator kFLEXSPI_PortB2

Access flash on B2 port.

enumerator kFLEXSPI_PortCount

enum _flexspi_arb_command_source

Trigger source of current command sequence granted by arbitrator.

Values:

enumerator kFLEXSPI_AhbReadCommand

enumerator kFLEXSPI_AhbWriteCommand

enumerator kFLEXSPI_IpCommand

enumerator kFLEXSPI_SuspendedCommand

enum _flexspi_command_type

Command type.

Values:

enumerator kFLEXSPI_Command

FlexSPI operation: Only command, both TX and Rx buffer are ignored.

enumerator kFLEXSPI_Config

FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT.

enumerator kFLEXSPI_Read

enumerator kFLEXSPI_Write

typedef enum _flexspi_pad flexspi_pad_t

pad definition of FLEXSPI, use to form LUT instruction.

typedef enum _flexspi_flags flexspi_flags_t

FLEXSPI interrupt status flags.

typedef enum _flexspi_read_sample_clock flexspi_read_sample_clock_t

FLEXSPI sample clock source selection for Flash Reading.

typedef enum _flexspi_cs_interval_cycle_unit flexspi_cs_interval_cycle_unit_t

FLEXSPI interval unit for flash device select.

typedef enum _flexspi_ahb_write_wait_unit flexspi_ahb_write_wait_unit_t

FLEXSPI AHB wait interval unit for writing.

typedef enum _flexspi_ip_error_code flexspi_ip_error_code_t

Error Code when IP command Error detected.

typedef enum _flexspi_ahb_error_code flexspi_ahb_error_code_t

Error Code when AHB command Error detected.

typedef enum _flexspi_port flexspi_port_t

FLEXSPI operation port select.

typedef enum _flexspi_arb_command_source flexspi_arb_command_source_t

Trigger source of current command sequence granted by arbitrator.

typedef enum _flexspi_command_type flexspi_command_type_t

Command type.

typedef struct _flexspi_ahbBuffer_config flexspi_ahbBuffer_config_t

typedef struct _flexspi_ahbBuffers_ctrl flexspi_ahbBuffers_ctrl_t

Structure to control all AHB buffers.

typedef struct _flexspi_config flexspi_config_t

FLEXSPI configuration structure.

typedef struct _flexspi_device_config flexspi_device_config_t

External device configuration items.

typedef struct _flexspi_transfer flexspi_transfer_t

Transfer structure for FLEXSPI.

typedef struct _flexspi_handle flexspi_handle_t

typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, flexspi_handle_t *handle, status_t status, void *userData)

FLEXSPI transfer callback function.

typedef struct _flexspi_addr_map_config flexspi_addr_map_config_t

Address mapping configuration structure.

FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT

FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)

Formula to form FLEXSPI instructions in LUT table.

struct _flexspi_ahbBuffer_config

#include <fsl_flexspi.h>

Public Members

uint8_t priority

This priority for AHB Master Read which this AHB RX Buffer is assigned.

uint8_t masterIndex

AHB Master ID the AHB RX Buffer is assigned.

uint16_t bufferSize

AHB buffer size in byte.

bool enablePrefetch

AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows prefetch disable/enable separately for each master.

struct _flexspi_ahbBuffers_ctrl

#include <fsl_flexspi.h>

Structure to control all AHB buffers.

Public Members

flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]

Configurations of all AHB buffers.

struct _flexspi_config

#include <fsl_flexspi.h>

FLEXSPI configuration structure.

Public Members

flexspi_read_sample_clock_t rxSampleClock

Sample Clock source selection for Flash Reading.

bool enableSckFreeRunning

Enable/disable SCK output free-running.

bool enableDoze

Enable/disable doze mode support.

bool enableHalfSpeedAccess

Enable/disable divide by 2 of the clock for half speed commands.

bool enableSameConfigForAll

Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all.

uint16_t seqTimeoutCycle

Timeout wait cycle for command sequence execution, timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles.

uint8_t ipGrantTimeoutCycle

Timeout wait cycle for IP command grant, timeout after ipGrantTimeoutCycle*1024 AHB clock cycles.

uint8_t txWatermark

FLEXSPI IP transmit watermark value.

uint8_t rxWatermark

FLEXSPI receive watermark value.

struct _flexspi_device_config

#include <fsl_flexspi.h>

External device configuration items.

Public Members

uint32_t flexspiRootClk

FLEXSPI serial root clock.

bool isSck2Enabled

FLEXSPI use SCK2.

uint32_t flashSize

Flash size in KByte.

bool addressShift

Address shift.

flexspi_cs_interval_cycle_unit_t CSIntervalUnit

CS interval unit, 1 or 256 cycle.

uint16_t CSInterval

CS line assert interval, multiply CS interval unit to get the CS line assert interval cycles.

uint8_t CSHoldTime

CS line hold time.

uint8_t CSSetupTime

CS line setup time.

uint8_t dataValidTime

Data valid time for external device.

uint8_t columnspace

Column space size.

bool enableWordAddress

If enable word address.

uint8_t AWRSeqIndex

Sequence ID for AHB write command.

uint8_t AWRSeqNumber

Sequence number for AHB write command.

uint8_t ARDSeqIndex

Sequence ID for AHB read command.

uint8_t ARDSeqNumber

Sequence number for AHB read command.

flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit

AHB write wait unit.

uint16_t AHBWriteWaitInterval

AHB write wait interval, multiply AHB write interval unit to get the AHB write wait cycles.

bool enableWriteMask

Enable/Disable FLEXSPI drive DQS pin as write mask when writing to external device.

struct _flexspi_transfer

#include <fsl_flexspi.h>

Transfer structure for FLEXSPI.

Public Members

uint32_t deviceAddress

Operation device address.

flexspi_port_t port

Operation port.

flexspi_command_type_t cmdType

Execution command type.

uint8_t seqIndex

Sequence ID for command.

uint8_t SeqNumber

Sequence number for command.

uint32_t *data

Data buffer.

size_t dataSize

Data size in bytes.

struct _flexspi_handle

#include <fsl_flexspi.h>

Transfer handle structure for FLEXSPI.

Public Members

uint32_t state

Internal state for FLEXSPI transfer

uint8_t *data

Data buffer.

size_t dataSize

Remaining Data size in bytes.

size_t transferTotalSize

Total Data size in bytes.

flexspi_transfer_callback_t completionCallback

Callback for users while transfer finish or error occurred

void *userData

FLEXSPI callback function parameter.

struct _flexspi_addr_map_config

#include <fsl_flexspi.h>

Address mapping configuration structure.

Public Members

uint32_t addrStart

Remapping start address.

uint32_t addrEnd

Remapping end address.

uint32_t addrOffset

Address offset.

bool remapEnable

Enable address remapping.

struct ahbConfig

Public Members

uint8_t ahbGrantTimeoutCycle

Timeout wait cycle for AHB command grant, timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles.

uint16_t ahbBusTimeoutCycle

Timeout wait cycle for AHB read/write access, timeout after ahbBusTimeoutCycle*1024 AHB clock cycles.

uint8_t resumeWaitCycle

Wait cycle for idle state before suspended command sequence resume, timeout after ahbBusTimeoutCycle AHB clock cycles.

flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]

AHB buffer size.

bool enableClearAHBBufferOpt

Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK.

bool enableReadAddressOpt

Enable/disable remove AHB read burst start address alignment limitation. when enable, there is no AHB read burst start address alignment limitation.

bool enableAHBPrefetch

Enable/disable AHB read prefetch feature, when enabled, FLEXSPI will fetch more data than current AHB burst.

bool enableAHBBufferable

Enable/disable AHB bufferable write access support, when enabled, FLEXSPI return before waiting for command execution finished.

bool enableAHBCachable

Enable AHB bus cachable read access support.

FLEXSPI eDMA Driver

void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)

Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.

Parameters:

• base – FLEXSPI peripheral base address

• handle – Pointer to flexspi_edma_handle_t structure

• callback – FLEXSPI callback, NULL means no callback.

• userData – User callback function data.

• txDmaHandle – User requested DMA handle for TX DMA transfer.

• rxDmaHandle – User requested DMA handle for RX DMA transfer.

void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_transfer_nsize_t nsize)

Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).

See also

flexspi_edma_transfer_nsize_t .

Parameters:

• base – FLEXSPI peripheral base address

• handle – Pointer to flexspi_edma_handle_t structure

• nsize – FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is kFLEXPSI_EDMAnSize1Bytes(one byte).

status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_transfer_t *xfer)

Transfers FLEXSPI data using an eDMA non-blocking method.

This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure

• xfer – FLEXSPI transfer structure.

Return values:

• kStatus_FLEXSPI_Busy – FLEXSPI is busy transfer.

• kStatus_InvalidArgument – The watermark configuration is invalid, the watermark should be power of 2 to do successfully EDMA transfer.

• kStatus_Success – FLEXSPI successfully start edma transfer.

void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle)

Aborts the transfer data using eDMA.

This function aborts the transfer data using eDMA.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure

status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count)

Gets the transferred counts of transfer.

Parameters:

• base – FLEXSPI peripheral base address.

• handle – Pointer to flexspi_edma_handle_t structure.

• count – Bytes transfer.

Return values:

• kStatus_Success – Succeed get the transfer count.

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXSPI_EDMA_DRIVER_VERSION

FLEXSPI EDMA driver version.

FLEXSPI EDMA driver.

FSL_FLEXSPI_EDMA_DRIVER_VERSION

FLEXSPI EDMA driver.

enum _flexspi_edma_ntransfer_size

eDMA transfer configuration

Values:

enumerator kFLEXPSI_EDMAnSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kFLEXPSI_EDMAnSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kFLEXPSI_EDMAnSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kFLEXPSI_EDMAnSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kFLEXPSI_EDMAnSize32Bytes

Source/Destination data transfer size is 32 bytes every time

enum _flexspi_edma_ntransfer_size

eDMA transfer configuration

Values:

enumerator kFLEXPSI_EDMAnSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kFLEXPSI_EDMAnSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kFLEXPSI_EDMAnSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kFLEXPSI_EDMAnSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kFLEXPSI_EDMAnSize32Bytes

Source/Destination data transfer size is 32 bytes every time

typedef struct _flexspi_edma_handle flexspi_edma_handle_t

typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)

FLEXSPI eDMA transfer callback function for finish and error.

typedef enum _flexspi_edma_ntransfer_size flexspi_edma_transfer_nsize_t

eDMA transfer configuration

typedef struct _flexspi_edma_handle flexspi_edma_handle_t

typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)

FLEXSPI eDMA transfer callback function for finish and error.

typedef enum _flexspi_edma_ntransfer_size flexspi_edma_transfer_nsize_t

eDMA transfer configuration

struct _flexspi_edma_handle

#include <fsl_flexspi_edma.h>

FLEXSPI DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *txDmaHandle

eDMA handler for FLEXSPI Tx.

edma_handle_t *rxDmaHandle

eDMA handler for FLEXSPI Rx.

size_t transferSize

Bytes need to transfer.

flexspi_edma_transfer_nsize_t nsize

eDMA SSIZE/DSIZE in each transfer.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint8_t count

The transfer data count in a DMA request.

uint32_t state

Internal state for FLEXSPI eDMA transfer.

flexspi_edma_callback_t completionCallback

A callback function called after the eDMA transfer is finished.

void *userData

User callback parameter

FLEXSPI_FLR: Flexible Serial Peripheral Interface Follower Driver

IO mode enumeration of FLEXSPI FOLLOWER.

Values:

enumerator kFLEXSPI_SLV_IOMODE_SDRx4

enumerator kFLEXSPI_SLV_IOMODE_SDRx8

enumerator kFLEXSPI_SLV_IOMODE_DDRx4

enumerator kFLEXSPI_SLV_IOMODE_DDRx8

The read fetch size enumeration of FLEXSPI FOLLOWER.

Values:

enumerator kFLEXSPI_SLV_Read_Fetch_256Bytes

enumerator kFLEXSPI_SLV_Read_Fetch_512Bytes

enumerator kFLEXSPI_SLV_Read_Fetch_1KBytes

enumerator kFLEXSPI_SLV_Read_Fetch_2KBytes

The write watermark enumeration of FLEXSPI FOLLOWER.

Values:

enumerator kFLEXSPI_SLV_Write_Watermark_32Bytes

enumerator kFLEXSPI_SLV_Write_Watermark_64Bytes

enumerator kFLEXSPI_SLV_Write_Watermark_128Bytes

enumerator kFLEXSPI_SLV_Write_Watermark_256Bytes

Interrupt status flags of FLEXSPI FOLLOWER.

Values:

enumerator kFLEXSPI_SLV_WriteOverflowFlag

An IO RX FIFO overflow occurred during command/address/write data phase.

enumerator kFLEXSPI_SLV_ReadUnderflowFlag

IO TX FIFO underflow has occurred during a read command.

enumerator kFLEXSPI_SLV_ErrorCommandFlag

An unknown command has been received from the SPI bus.

enumerator kFLEXSPI_SLV_MailInterruptFlag

Mailbox interrupt.

enumerator kFLEXSPI_SLV_AllInterruptFlags

All flags.

typedef struct _flexspi_slv_config flexspi_slv_config_t

FLEXSPI FOLLOWER configuration structure.

typedef struct _flexspi_slv_handle flexspi_slv_handle_t

typedef void (*flexspi_slv_callback_t)(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle)

FLEXSPI FOLLOWER interrupt callback function.

FSL_FLEXSPI_SLV_DRIVER_VERSION

FLEXSPI FOLLOWER driver version.

FLEXSPI_SLV_CMD_DDR(x)

uint32_t FLEXSPI_SLV_GetInstance(FLEXSPI_SLV_Type *base)

Get the instance number for FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER base pointer.

void FLEXSPI_SLV_Init(FLEXSPI_SLV_Type *base, const flexspi_slv_config_t *config)

Initializes the FLEXSPI FOLLOWER module and internal state.

This function enables the clock for FLEXSPI FOLLOWER and also configures the FLEXSPI FOLLOWER with the input configure parameters. Users should call this function before any FLEXSPI FOLLOWER operations.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• config – FLEXSPI FOLLOWER configure structure.

void FLEXSPI_SLV_GetDefaultConfig(flexspi_slv_config_t *config)

Gets default settings for FLEXSPI FOLLOWER.

Parameters:

• config – FLEXSPI FOLLOWER configuration structure.

void FLEXSPI_SLV_Deinit(FLEXSPI_SLV_Type *base)

Deinitializes the FLEXSPI FOLLOWER module.

Clears the FLEXSPI FOLLOWER state and FLEXSPI FOLLOWER module registers.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline void FLEXSPI_SLV_SoftwareReset(FLEXSPI_SLV_Type *base)

Software reset for the FLEXSPI FOLLOWER logic.

This function does software reset for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline void FLEXSPI_SLV_SetIOMode(FLEXSPI_SLV_Type *base, uint32_t ioMode)

Set IO mode for the FLEXSPI FOLLOWER module.

This function sets the IO mode flags for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• ioMode – Set IO Mode for FLEXSPI FOLLOWER

static inline void FLEXSPI_SLV_UpdateRWCmdBaseRange(FLEXSPI_SLV_Type *base)

Update RW CMD base address and range value for the FLEXSPI FOLLOWER module.

This function updates RW CMD base address and range value for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline void FLEXSPI_SLV_SetRWCmdBaseAddr(FLEXSPI_SLV_Type *base, uint32_t addr1, uint32_t addr2)

Set RW command base address1 for the FLEXSPI FOLLOWER module.

This function sets the RW command base address1 for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• addr1 – The high 16-bit base address of the RW command0.

• addr2 – The high 16-bit base address of the RW command1.

static inline void FLEXSPI_SLV_SetAddrRange(FLEXSPI_SLV_Type *base, uint32_t index, uint32_t val)

Set address1/2 range for the FLEXSPI FOLLOWER module.

This function sets the address1/2 range for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• index – The index of RW command, 0 or 1.

• val – The size of the memory range in 1KB units.

static inline void FLEXSPI_SLV_SetReadWatermark(FLEXSPI_SLV_Type *base, uint32_t rxWatermark, bool enable)

Set read water mark level for the FLEXSPI FOLLOWER module.

This function sets read water mark level for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• val – Read watermark level in bytes

static inline void FLEXSPI_SLV_SetReadFetchSize(FLEXSPI_SLV_Type *base, uint32_t rxFetchSize)

Sets the maximum read size triggered by a single read command.

This function sets the maximum read size for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• rxFetchSize – The maximum read size triggered by a single read command.

static inline void FLEXSPI_SLV_SetWriteWatermark(FLEXSPI_SLV_Type *base, uint32_t txWatermark)

Set write water mark level for the FLEXSPI FOLLOWER module.

This function sets write water mark level for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• txWatermark – Write watermark level

static inline void FLEXSPI_SLV_MaskChipSelect(FLEXSPI_SLV_Type *base, uint32_t mask)

Set CS mask value for the FLEXSPI FOLLOWER module.

This function sets CS mask value for the FLEXSPI FOLLOWER.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• mask – 0 - Not masked, 1 - Masked.

static inline void FLEXSPI_SLV_EnableInterrupts(FLEXSPI_SLV_Type *base, uint32_t mask)

Enables the FLEXSPI FOLLOWER interrupts.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• mask – FLEXSPI FOLLOWER interrupt source.

static inline void FLEXSPI_SLV_DisableInterrupts(FLEXSPI_SLV_Type *base, uint32_t mask)

Disable the FLEXSPI FOLLOWER interrupts.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• mask – FLEXSPI FOLLOWER interrupt source.

static inline uint32_t FLEXSPI_SLV_GetEnabledInterrupts(FLEXSPI_SLV_Type *base)

Get the FLEXSPI FOLLOWER enabled interrupts.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline void FLEXSPI_SLV_EnableMailInterrupt(FLEXSPI_SLV_Type *base, bool enable)

Enable the FLEXSPI FOLLOWER mailbox interrupts.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• enable – Whether enable the mailbox interrupt.

static inline bool FLEXSPI_SLV_GetEnabledMailInterrupt(FLEXSPI_SLV_Type *base)

Return whether the FLEXSPI FOLLOWER enables the mailbox interrupt.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline void FLEXSPI_SLV_GetOutOfRangeCounts(FLEXSPI_SLV_Type *base, size_t *rdCount, size_t *wrCount)

Gets the SPI leader read/write out-of-allowed-range count.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• rdCount – [out] Pointer through which the current number in the read out-of-allowed-range counter is returned. Pass NULL if this value is not required.

• wrCount – [out] Pointer through which the current number in the write out-of-allowed-range counter is returned Pass NULL if this value is not required.

static inline uint32_t FLEXSPI_SLV_GetInterruptStatusFlags(FLEXSPI_SLV_Type *base)

Get the FLEXSPI FOLLOWER interrupt status flags.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

Interrupt – status flag, use status flag to AND the bit mask could get the related status.

static inline uint32_t FLEXSPI_SLV_GetMailboxData(FLEXSPI_SLV_Type *base, uint32_t index)

Get the FLEXSPI FOLLOWER mailbox data.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• index – The index of the mail interrupt register

Returns:

Return the FLEXSPI FOLLOWER mailbox data

static inline void FLEXSPI_SLV_ClearInterruptStatusFlags(FLEXSPI_SLV_Type *base, uint32_t mask)

Clear the FLEXSPI FOLLOWER interrupt status flags.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• mask – FLEXSPI FOLLOWER interrupt source.

static inline void FLEXSPI_SLV_ClearMailInterruptFlag(FLEXSPI_SLV_Type *base)

Clear the FLEXSPI FOLLOWER mailbox interrupt flag.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

static inline bool FLEXSPI_SLV_GetAXIWriteBusyStatus(FLEXSPI_SLV_Type *base)

Returns whether the current AXI write leader is busy with a write command.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

• true – The current AXI write leader is busy.

• false – The current AXI write leader is not busy.

static inline bool FLEXSPI_SLV_GetAXIReadIdleStatus(FLEXSPI_SLV_Type *base)

Returns whether the AXI read leader is busy with a read request or else idle with no pending AXI read request.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

• true – The current AXI read leader is idle.

• false – The current AXI read leader is busy.

static inline bool FLEXSPI_SLV_GetRegReadWriteIdleStatus(FLEXSPI_SLV_Type *base)

Returns whether the SPI to read/write register queue is idle.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

• true – The SPI to read/write register queue is idle.

• false – The SPI to read/write register queue is busy.

static inline bool FLEXSPI_SLV_GetSEQIdleStatus(FLEXSPI_SLV_Type *base)

Returns whether the SEQ control logic is idle or else busy with an ongoing SPI request.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

• true – The SEQ control logic is idle.

• false – The SEQ control logic is busy.

static inline bool FLEXSPI_SLV_GetModuleBusyStatus(FLEXSPI_SLV_Type *base)

Returns whether the FLEXSPI FOLLOWER module is busy.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

Return values:

• true – The SEQ control logic is busy.

• false – The SEQ control logic is idle.

static inline void FLEXSPI_SLV_SetReadMemCommand(FLEXSPI_SLV_Type *base, uint32_t index, uint16_t command, uint16_t dummyCycle)

Sets the read memory command.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• index – The read command setting register index.

• command – The read command value.

• dummyCycle – The dummy cycle value of the read command.

static inline void FLEXSPI_SLV_SetWriteMemCommand(FLEXSPI_SLV_Type *base, uint32_t index, uint32_t command)

Sets the write memory command.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• index – The write command setting register index.

• command – The write command value.

static inline void FLEXSPI_SLV_SetReadRegCommand(FLEXSPI_SLV_Type *base, uint16_t command, uint16_t dummyCycle)

Sets the read register command.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address

• command – The read command value.

• dummyCycle – The dummy cycle value of the read command.

static inline void FLEXSPI_SLV_SetWriteRegCommand(FLEXSPI_SLV_Type *base, uint32_t command)

Sets the write register command.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• command – The write register command value.

void FLEXSPI_SLV_InterruptCreateHandle(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle, flexspi_slv_callback_t callback, uint32_t interruptMask)

Initializes the FLEXSPI FOLLOWER handle which is used in transactional functions.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• handle – Pointer to flexspi_slv_handle_t structure to store the interrupt state.

• callback – Pointer to user callback function.

• interruptMask – Interrupt mask to enable during handle creation. Use enumeration values ORed.

void FLEXSPI_SLV_HandleIRQ(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle)

Master interrupt handler.

Parameters:

• base – FLEXSPI FOLLOWER peripheral base address.

• handle – Pointer to flexspi_slv_handle_t structure.

uint32_t baseAddr1

Read/Write CMD1 Base Address.

uint32_t baseAddr2

Read/Write CMD2 Base Address.

uint32_t addrRange1

Read/Write CMD1 Addr Range.

uint32_t addrRange2

Read/Write CMD2 Addr Range.

uint8_t ioMode

IO mode control - SDRx4, SDRx8, DDRx4, DDRx8.

uint8_t rxFetchSize

Specifies the maximum read size triggered by a single read command.

uint8_t rxWatermark

Triggers a new AXI read to fetch more data through the IP AXI header.

uint8_t txWatermark

Specifies the watermark value. During the write command, if pending write data equals or exceeds the watermark level, it triggers a new AXI write.

uint16_t readRegCmd

Read register command.

uint16_t readRegDummyCycle

Read register dymmy cycle.

uint16_t writeRegCmd

Write register command.

uint16_t readMemCmd1

Read memory command1.

uint16_t readMemDummyCycle1

Read memory dymmy cycle1.

uint16_t readMemCmd2

Read memory command2.

uint16_t readMemDummyCycle2

Read memory dymmy cycle2.

uint16_t writeMemCmd1

Write memory command1.

uint16_t writeMemCmd2

Write memory command2.

uint32_t intrMask

Interrupt state for FLEXSPI FOLLOWER.

flexspi_slv_callback_t callback

Callback for users while mailbox received or error occurred.

struct _flexspi_slv_config

#include <fsl_flexspi_flr.h>

FLEXSPI FOLLOWER configuration structure.

struct _flexspi_slv_handle

#include <fsl_flexspi_flr.h>

Interrupt handle structure for FLEXSPI FOLLOWER.

Gpc

void GPC_AssignCpuDomain(gpc_cpu_slice_t cpu, uint32_t domainMap)

static inline void GPC_CM_EnableCpuSleepHold(gpc_cpu_slice_t slice, bool enable)

static inline void GPC_CM_SetNextCpuMode(gpc_cpu_slice_t slice, gpc_cpu_mode_t mode)

Set the CPU mode on the next sleep event.

This function configures the CPU mode that the CPU core will transmit to on next sleep event.

Note

This API must be called each time before entering sleep.

Parameters:

• slice – GPC CPU slice number.

• mode – The CPU mode that the core will transmit to, refer to “gpc_cpu_mode_t”.

static inline gpc_cpu_mode_t GPC_CM_GetCurrentCpuMode(gpc_cpu_slice_t slice)

Get current CPU mode.

Parameters:

• slice – GPC CPU slice number.

Returns:

The current CPU mode, in type of gpc_cpu_mode_t.

static inline gpc_cpu_mode_t GPC_CM_GetPreviousCpuMode(gpc_cpu_slice_t slice)

Get previous CPU mode.

Parameters:

• slice – GPC CPU slice number.

Returns:

The previous CPU mode, in type of gpc_cpu_mode_t.

void GPC_CM_EnableIrqWakeup(gpc_cpu_slice_t slice, uint32_t irqId, bool enable)

Enable IRQ wakeup request.

This function enables the IRQ request which can wakeup the CPU platform.

Parameters:

• slice – GPC CPU slice number.

• irqId – ID of the IRQ, accessible range is 0-255.

• enable – Enable the IRQ request or not.

static inline void GPC_CM_EnableNonIrqWakeup(gpc_cpu_slice_t slice, uint32_t mask, bool enable)

Enable Non-IRQ wakeup request.

This function enables the non-IRQ request which can wakeup the CPU platform.

Parameters:

• slice – GPC CPU slice number.

• mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.

• enable – Enable the Non-IRQ request or not.

bool GPC_CM_GetIrqWakeupStatus(gpc_cpu_slice_t slice, uint32_t irqId)

Get the status of the IRQ wakeup request.

Parameters:

• slice – GPC CPU slice number.

• irqId – ID of the IRQ, accessible range is 0-255.

Returns:

Indicate the IRQ request is asserted or not.

static inline bool GPC_CM_GetNonIrqWakeupStatus(gpc_cpu_slice_t slice, uint32_t mask)

Get the status of the Non-IRQ wakeup request.

Parameters:

• slice – GPC CPU slice number.

• mask – Non-IRQ type, refer to “_gpc_cm_non_irq_wakeup_request”.

Returns:

Indicate the Non-IRQ request is asserted or not.

void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable)

brief Config the cpu mode transition step.

param slice GPC CPU slice number. param step step type, refer to “gpc_cm_tran_step_t”. param enable Used to control the transition step.

• true This step is enabled.

• false This step is disabled, GPC will skip this step and not send any request.

void GPC_CM_RequestSystemSleepMode(gpc_cpu_slice_t slice, const gpc_cpu_mode_t mode)

Request the chip into system sleep mode.

Parameters:

• slice – GPC CPU slice number.

• mode – CPU mode. Refer to “gpc_cpu_mode_t”.

void GPC_CM_ClearSystemSleepModeRequest(gpc_cpu_slice_t slice, const gpc_cpu_mode_t mode)

Clear the system sleep mode request.

Parameters:

• slice – GPC CPU slice number.

• mode – CPU mode. Refer to “gpc_cpu_mode_t”.

static inline bool GPC_CM_GetSystemSleepModeStatus(gpc_cpu_slice_t slice, uint32_t mask)

Get the status of the CPU system sleep mode transition.

Parameters:

• slice – GPC CPU slice number.

• mask – System sleep mode transition status mask, refer to “gpc_cm_system sleep_mode_status_t”.

Returns:

Indicate the CPU’s system sleep transition status.

void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step, bool enable)

brief Config the system sleep transition step.

param base GPC system sleep controller base address. param step step type, refer to “gpc_ss_tran_step_t”. param enable Used to control the transition step.

• true This step is enabled.

• false This step is disabled, GPC will skip this step and not send any request.

static inline void GPC_SS_SoftwareTriggerPMICStandby(GPC_SYS_SLEEP_CTRL_Type *base, bool enable)

Trigger PMIC standby ON/OFF by software.

Parameters:

• base – PMIC module base address.

• enable – Trigger on/off PMIC standby.

  • true Trigger PMIC standby ON.

  • false Trigger PMIC standby OFF.

static inline void GPC_SS_SystemSleepTriggerPMICStandby(GPC_SYS_SLEEP_CTRL_Type *base, bool enable)

brief Assert the PMIC standby request when system sleep.

Parameters:

• base – PMIC module base address.

• enable – Assert PMIC standby request or not.

  • true Assert PMIC_STBY_REQ when system sleep is entered.

  • false Do not assert PMIC_STBY_REQ when system sleep is entered.

FSL_GPC_RIVER_VERSION

GPC driver version 2.1.0.

_gpc_cm_non_irq_wakeup_request GPC Non-IRQ wakeup request.

Values:

enumerator kGPC_CM_DebugWakeupRequest

Debug wakeup request.

Values:

enumerator kGPC_Domain0

GPC domain 0.

enumerator kGPC_Domain1

GPC domain 1.

enumerator kGPC_Domain2

GPC domain 2.

enumerator kGPC_Domain3

GPC domain 3.

enumerator kGPC_Domain4

GPC domain 4.

enumerator kGPC_Domain5

GPC domain 5.

enumerator kGPC_Domain6

GPC domain 6.

enumerator kGPC_Domain7

GPC domain 7.

enumerator kGPC_Domain8

GPC domain 8.

enumerator kGPC_Domain9

GPC domain 9.

enumerator kGPC_Domain10

GPC domain 10.

enumerator kGPC_Domain11

GPC domain 11.

enumerator kGPC_Domain12

GPC domain 12.

enumerator kGPC_Domain13

GPC domain 13.

enumerator kGPC_Domain14

GPC domain 14.

enumerator kGPC_Domain15

GPC domain 15.

enum _gpc_cpu_slice

CPU slice.

Values:

enumerator kGPC_CPU0

CPU slice 0.

enumerator kGPC_CPU1

CPU slice 1.

enum _gpc_cm_tran_step

CPU mode transition step in sleep/wakeup sequence.

Values:

enumerator kGPC_CM_SleepSsar

SSAR (State Save And Restore) sleep step.

enumerator kGPC_CM_SleepLpcg

LPCG (Low Power Clock Gating) sleep step.

enumerator kGPC_CM_SleepPll

PLL sleep step.

enumerator kGPC_CM_SleepIso

ISO (Isolation) sleep step.

enumerator kGPC_CM_SleepReset

Reset sleep step.

enumerator kGPC_CM_SleepPower

Power sleep step.

enumerator kGPC_CM_SleepSYS

System sleep sleep step. Note that this step is controlled by system sleep controller.

enumerator kGPC_CM_WakeupSYS

System sleep wakeup step. Note that this step is controlled by system sleep controller.

enumerator kGPC_CM_WakeupPower

Power wakeup step.

enumerator kGPC_CM_WakeupReset

Reset wakeup step.

enumerator kGPC_CM_WakeupIso

ISO wakeup step.

enumerator kGPC_CM_WakeupPll

PLL wakeup step.

enumerator kGPC_CM_WakeupLpcg

LPCG wakeup step.

enumerator kGPC_CM_WakeupSsar

SSAR wakeup step.

enum _gpc_cpu_mode

CPU mode.

Values:

enumerator kGPC_RunMode

Stay in RUN mode.

enumerator kGPC_WaitMode

Transit to WAIT mode.

enumerator kGPC_StopMode

Transit to STOP mode.

enumerator kGPC_SuspendMode

Transit to SUSPEND mode.

enum _gpc_ss_tran_step

GPC system sleep mode transition steps.

Values:

enumerator kGPC_SS_Step0In

Bias in step.

enumerator kGPC_SS_Step1In

PLDO in step.

enumerator kGPC_SS_Step2In

Bandgap in step.

enumerator kGPC_SS_Step3In

LDO in step.

enumerator kGPC_SS_DcdcIn

DCDC in step.

enumerator kGPC_SS_PmicIn

PMIC in step.

enumerator kGPC_SS_PmicOut

PMIC out step.

enumerator kGPC_SS_DcdcOut

DCDC out step.

enumerator kGPC_SS_Step3Out

LDO out step.

enumerator kGPC_SS_Step2Out

Bandgap out step.

enumerator kGPC_SS_Step1Out

PLDO out step.

enumerator kGPC_SS_Step0Out

Bias out step.

typedef enum _gpc_cpu_slice gpc_cpu_slice_t

CPU slice.

typedef enum _gpc_cm_tran_step gpc_cm_tran_step_t

CPU mode transition step in sleep/wakeup sequence.

typedef enum _gpc_cpu_mode gpc_cpu_mode_t

CPU mode.

typedef enum _gpc_ss_tran_step gpc_ss_tran_step_t

GPC system sleep mode transition steps.

GPC_RESERVED_USE_MACRO

GPC_CM_SLEEP_SSAR_CTRL_OFFSET

GPC_CM_SLEEP_LPCG_CTRL_OFFSET

GPC_CM_SLEEP_PLL_CTRL_OFFSET

GPC_CM_SLEEP_ISO_CTRL_OFFSET

GPC_CM_SLEEP_RESET_CTRL_OFFSET

GPC_CM_SLEEP_POWER_CTRL_OFFSET

GPC_CM_WAKEUP_POWER_CTRL_OFFSET

GPC_CM_WAKEUP_RESET_CTRL_OFFSET

GPC_CM_WAKEUP_ISO_CTRL_OFFSET

GPC_CM_WAKEUP_PLL_CTRL_OFFSET

GPC_CM_WAKEUP_LPCG_CTRL_OFFSET

GPC_CM_WAKEUP_SSAR_CTRL_OFFSET

GPC_SS_STEP0_IN_CTRL_OFFSET

GPC_SS_STEP1_IN_CTRL_OFFSET

GPC_SS_STEP2_IN_CTRL_OFFSET

GPC_SS_STEP3_IN_CTRL_OFFSET

GPC_SS_DCDC_IN_CTRL_OFFSET

GPC_SS_PMIC_IN_CTRL_OFFSET

GPC_SS_PMIC_OUT_CTRL_OFFSET

GPC_SS_DCDC_OUT_CTRL_OFFSET

GPC_SS_STEP3_OUT_CTRL_OFFSET

GPC_SS_STEP2_OUT_CTRL_OFFSET

GPC_SS_STEP1_OUT_CTRL_OFFSET

GPC_SS_STEP0_OUT_CTRL_OFFSET

GPC_CM_STEP_REG_OFFSET

GPC_SS_STEP_REG_OFFSET

GPC_STAT(mask, shift)

GPT: General Purpose Timer

void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)

Initialize GPT to reset state and initialize running mode.

Parameters:

• base – GPT peripheral base address.

• initConfig – GPT mode setting configuration.

void GPT_Deinit(GPT_Type *base)

Disables the module and gates the GPT clock.

Parameters:

• base – GPT peripheral base address.

void GPT_GetDefaultConfig(gpt_config_t *config)

Fills in the GPT configuration structure with default settings.

The default values are:

config->clockSource = kGPT_ClockSource_Periph;
config->divider = 1U;
config->enableRunInStop = true;
config->enableRunInWait = true;
config->enableRunInDoze = false;
config->enableRunInDbg = false;
config->enableFreeRun = false;
config->enableMode  = true;

Parameters:

• config – Pointer to the user configuration structure.

static inline void GPT_SoftwareReset(GPT_Type *base)

Software reset of GPT module.

Parameters:

• base – GPT peripheral base address.

static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)

Set clock source of GPT.

Parameters:

• base – GPT peripheral base address.

• gptClkSource – Clock source (see gpt_clock_source_t typedef enumeration).

static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)

Get clock source of GPT.

Parameters:

• base – GPT peripheral base address.

Returns:

clock source (see gpt_clock_source_t typedef enumeration).

static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)

Set pre scaler of GPT.

Parameters:

• base – GPT peripheral base address.

• divider – Divider of GPT (1-4096).

static inline uint32_t GPT_GetClockDivider(GPT_Type *base)

Get clock divider in GPT module.

Parameters:

• base – GPT peripheral base address.

Returns:

clock divider in GPT module (1-4096).

static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)

OSC 24M pre-scaler before selected by clock source.

Parameters:

• base – GPT peripheral base address.

• divider – OSC Divider(1-16).

static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)

Get OSC 24M clock divider in GPT module.

Parameters:

• base – GPT peripheral base address.

Returns:

OSC clock divider in GPT module (1-16).

static inline void GPT_StartTimer(GPT_Type *base)

Start GPT timer.

Parameters:

• base – GPT peripheral base address.

static inline void GPT_StopTimer(GPT_Type *base)

Stop GPT timer.

Parameters:

• base – GPT peripheral base address.

static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)

Reads the current GPT counting value.

Parameters:

• base – GPT peripheral base address.

Returns:

Current GPT counter value.

static inline void GPT_SetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)

Set GPT operation mode of input capture channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

• mode – GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT operation mode of input capture channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT input capture value of certain channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture value.

static inline void GPT_SetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)

Set GPT operation mode of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

• mode – GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT operation mode of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)

Set GPT output compare value of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

• value – GPT output compare value.

static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT output compare value of output compare channel.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output compare value.

static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)

Force GPT output action on output compare channel, ignoring comparator.

Parameters:

• base – GPT peripheral base address.

• channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)

Enables the selected GPT interrupts.

Parameters:

• base – GPT peripheral base address.

• mask – The interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)

Disables the selected GPT interrupts.

Parameters:

• base – GPT peripheral base address

• mask – The interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)

Gets the enabled GPT interrupts.

Parameters:

• base – GPT peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Get GPT status flags.

Parameters:

• base – GPT peripheral base address.

• flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

Returns:

GPT status, each bit represents one status flag.

static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Clears the GPT status flags.

Parameters:

• base – GPT peripheral base address.

• flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

FSL_GPT_DRIVER_VERSION

enum _gpt_clock_source

List of clock sources.

Note

Actual number of clock sources is SoC dependent

Values:

enumerator kGPT_ClockSource_Off

GPT Clock Source Off.

enumerator kGPT_ClockSource_Periph

GPT Clock Source from Peripheral Clock.

enumerator kGPT_ClockSource_HighFreq

GPT Clock Source from High Frequency Reference Clock.

enumerator kGPT_ClockSource_Ext

GPT Clock Source from external pin.

enumerator kGPT_ClockSource_LowFreq

GPT Clock Source from Low Frequency Reference Clock.

enumerator kGPT_ClockSource_Osc

GPT Clock Source from Crystal oscillator.

enum _gpt_input_capture_channel

List of input capture channel number.

Values:

enumerator kGPT_InputCapture_Channel1

GPT Input Capture Channel1.

enumerator kGPT_InputCapture_Channel2

GPT Input Capture Channel2.

enum _gpt_input_operation_mode

List of input capture operation mode.

Values:

enumerator kGPT_InputOperation_Disabled

Don’t capture.

enumerator kGPT_InputOperation_RiseEdge

Capture on rising edge of input pin.

enumerator kGPT_InputOperation_FallEdge

Capture on falling edge of input pin.

enumerator kGPT_InputOperation_BothEdge

Capture on both edges of input pin.

enum _gpt_output_compare_channel

List of output compare channel number.

Values:

enumerator kGPT_OutputCompare_Channel1

Output Compare Channel1.

enumerator kGPT_OutputCompare_Channel2

Output Compare Channel2.

enumerator kGPT_OutputCompare_Channel3

Output Compare Channel3.

enum _gpt_output_operation_mode

List of output compare operation mode.

Values:

enumerator kGPT_OutputOperation_Disconnected

Don’t change output pin.

enumerator kGPT_OutputOperation_Toggle

Toggle output pin.

enumerator kGPT_OutputOperation_Clear

Set output pin low.

enumerator kGPT_OutputOperation_Set

Set output pin high.

enumerator kGPT_OutputOperation_Activelow

Generate a active low pulse on output pin.

enum _gpt_interrupt_enable

List of GPT interrupts.

Values:

enumerator kGPT_OutputCompare1InterruptEnable

Output Compare Channel1 interrupt enable

enumerator kGPT_OutputCompare2InterruptEnable

Output Compare Channel2 interrupt enable

enumerator kGPT_OutputCompare3InterruptEnable

Output Compare Channel3 interrupt enable

enumerator kGPT_InputCapture1InterruptEnable

Input Capture Channel1 interrupt enable

enumerator kGPT_InputCapture2InterruptEnable

Input Capture Channel1 interrupt enable

enumerator kGPT_RollOverFlagInterruptEnable

Counter rolled over interrupt enable

enum _gpt_status_flag

Status flag.

Values:

enumerator kGPT_OutputCompare1Flag

Output compare channel 1 event.

enumerator kGPT_OutputCompare2Flag

Output compare channel 2 event.

enumerator kGPT_OutputCompare3Flag

Output compare channel 3 event.

enumerator kGPT_InputCapture1Flag

Input Capture channel 1 event.

enumerator kGPT_InputCapture2Flag

Input Capture channel 2 event.

enumerator kGPT_RollOverFlag

Counter reaches maximum value and rolled over to 0 event.

typedef enum _gpt_clock_source gpt_clock_source_t

List of clock sources.

Note

Actual number of clock sources is SoC dependent

typedef enum _gpt_input_capture_channel gpt_input_capture_channel_t

List of input capture channel number.

typedef enum _gpt_input_operation_mode gpt_input_operation_mode_t

List of input capture operation mode.

typedef enum _gpt_output_compare_channel gpt_output_compare_channel_t

List of output compare channel number.

typedef enum _gpt_output_operation_mode gpt_output_operation_mode_t

List of output compare operation mode.

typedef enum _gpt_interrupt_enable gpt_interrupt_enable_t

List of GPT interrupts.

typedef enum _gpt_status_flag gpt_status_flag_t

Status flag.

typedef struct _gpt_init_config gpt_config_t

Structure to configure the running mode.

struct _gpt_init_config

#include <fsl_gpt.h>

Structure to configure the running mode.

Public Members

gpt_clock_source_t clockSource

clock source for GPT module.

uint32_t divider

clock divider (prescaler+1) from clock source to counter.

bool enableFreeRun

true: FreeRun mode, false: Restart mode.

bool enableRunInWait

GPT enabled in wait mode.

bool enableRunInStop

GPT enabled in stop mode.

bool enableRunInDoze

GPT enabled in doze mode.

bool enableRunInDbg

GPT enabled in debug mode.

bool enableMode

true: counter reset to 0 when enabled; false: counter retain its value when enabled.

I3C: I3C Driver

FSL_I3C_DRIVER_VERSION

I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy

The master is already performing a transfer.

enumerator kStatus_I3C_Idle

The slave driver is idle.

enumerator kStatus_I3C_Nak

The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort

The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term

The master terminates slave read.

enumerator kStatus_I3C_HdrParityError

Parity error from DDR read.

enumerator kStatus_I3C_CrcError

CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError

Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError

Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError

Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq

Invalid use of request.

enumerator kStatus_I3C_Timeout

The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed

The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon

The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError

Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError

Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak

Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart

Slave invalid start flag

enumerator kStatus_I3C_SdrParityError

SDR parity error

enumerator kStatus_I3C_S0S1Error

S0 or S1 error

enum _i3c_hdr_mode

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone

enumerator kI3C_HDRModeDDR

enumerator kI3C_HDRModeTSP

enumerator kI3C_HDRModeTSL

typedef enum _i3c_hdr_mode i3c_hdr_mode_t

I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t

I3C device information.

I3C_RETRY_TIMES

Max loops to wait for I3C operation status complete.

This is the maximum number of loops to wait for I3C operation status complete. If set to 0, it will wait indefinitely.

I3C_MAX_DEVCNT

I3C_IBI_BUFF_SIZE

struct _i3c_device_info

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr

Device dynamic address.

uint8_t staticAddr

Static address.

uint8_t dcr

Device characteristics register information.

uint8_t bcr

Bus characteristics register information.

uint16_t vendorID

Device vendor ID(manufacture ID).

uint32_t partNumber

Device part number info

uint16_t maxReadLength

Maximum read length.

uint16_t maxWriteLength

Maximum write length.

uint8_t hdrMode

Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver

typedef struct _i3c_config i3c_config_t

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)

Get which instance current I3C is used.

Parameters:

• base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->enableMaster                 = kI3C_MasterCapable;
config->disableTimeout               = false;
config->hKeep                        = kI3C_MasterHighKeeperNone;
config->enableOpenDrainStop          = true;
config->enableOpenDrainHigh          = true;
config->baudRate_Hz.i2cBaud          = 400000U;
config->baudRate_Hz.i3cPushPullBaud  = 12500000U;
config->baudRate_Hz.i3cOpenDrainBaud = 2500000U;
config->masterDynamicAddress         = 0x0AU;
config->slowClock_Hz                 = 1000000U;
config->enableSlave                  = true;
config->vendorID                     = 0x11BU;
config->enableRandomPart             = false;
config->partNumber                   = 0;
config->dcr                          = 0;
config->bcr = 0;
config->hdrMode             = (uint8_t)kI3C_HDRModeDDR;
config->nakAllRequest       = false;
config->ignoreS0S1Error     = false;
config->offline             = false;
config->matchSlaveStartStop = false;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

• config – [out] User provided configuration structure for default values. Refer to i3c_config_t.

void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration.

Parameters:

• base – The I3C peripheral base address.

• config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

struct _i3c_config

#include <fsl_i3c.h>

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

i3c_master_enable_t enableMaster

Enable master mode.

bool disableTimeout

Whether to disable timeout to prevent the ERRWARN.

i3c_master_hkeep_t hKeep

High keeper mode setting.

bool enableOpenDrainStop

Whether to emit open-drain speed STOP.

bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD.

i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings.

uint8_t masterDynamicAddress

Main master dynamic address configuration.

uint32_t maxWriteLength

Maximum write length.

uint32_t maxReadLength

Maximum read length.

bool enableSlave

Whether to enable slave.

uint8_t staticAddr

Static address.

uint16_t vendorID

Device vendor ID(manufacture ID).

uint32_t partNumber

Device part number info

uint8_t dcr

Device characteristics register information.

uint8_t bcr

Bus characteristics register information.

uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t.

bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC.

bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode.

bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely.

bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed.

I3C Master Driver

void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)

Provides a default configuration for the I3C master peripheral.

This function provides the following default configuration for the I3C master peripheral:

masterConfig->enableMaster            = kI3C_MasterOn;
masterConfig->disableTimeout          = false;
masterConfig->hKeep                   = kI3C_MasterHighKeeperNone;
masterConfig->enableOpenDrainStop     = true;
masterConfig->enableOpenDrainHigh     = true;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busType                 = kI3C_TypeI2C;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I3C_MasterInit().

Parameters:

• masterConfig – [out] User provided configuration structure for default values. Refer to i3c_master_config_t.

void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the I3C master peripheral.

This function enables the peripheral clock and initializes the I3C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

• base – The I3C peripheral base address.

• masterConfig – User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void I3C_MasterDeinit(I3C_Type *base)

Deinitializes the I3C master peripheral.

This function disables the I3C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The I3C peripheral base address.

status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)

status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)

status_t I3C_CheckForBusyBus(I3C_Type *base)

static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)

Set I3C module master mode.

Parameters:

• base – The I3C peripheral base address.

• enable – Enable master mode.

void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral.

This function provides the following default configuration for the I3C slave peripheral:

slaveConfig->enableslave             = true;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

• slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t.

void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral.

This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

• base – The I3C peripheral base address.

• slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override.

• slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.

void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral.

This function disables the I3C slave peripheral and gates the clock.

Parameters:

• base – The I3C peripheral base address.

static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave.

Parameters:

• base – The I3C peripheral base address.

• isEnable – Enable or disable.

static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)

Gets the I3C master status flags.

A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_master_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master status flag state.

The following status register flags can be cleared:

• kI3C_MasterSlaveStartFlag

• kI3C_MasterControlDoneFlag

• kI3C_MasterCompleteFlag

• kI3C_MasterArbitrationWonFlag

• kI3C_MasterSlave2MasterFlag

Attempts to clear other flags has no effect.

See also

_i3c_master_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_master_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags().

static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)

Gets the I3C master error status flags.

A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_master_error_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the error status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master error status flag state.

See also

_i3c_master_error_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_master_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags().

i3c_master_state_t I3C_MasterGetState(I3C_Type *base)

Gets the I3C master state.

Parameters:

• base – The I3C peripheral base address.

Returns:

I3C master state.

static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags.

A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_slave_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state.

The following status register flags can be cleared:

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

Attempts to clear other flags has no effect.

See also

_i3c_slave_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags().

static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags.

A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_slave_error_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the error status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state.

See also

_i3c_slave_error_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags().

i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state.

Parameters:

• base – The I3C peripheral base address.

Returns:

I3C slave activity state, refer i3c_slave_activity_state_t.

status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)

static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C master interrupt requests.

All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C master interrupt requests.

All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C master interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C master interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of pending interrupts.

static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests.

Only below flags can be enabled as interrupts.

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

• kI3C_SlaveRxReadyFlag

• kI3C_SlaveTxReadyFlag

• kI3C_SlaveDynamicAddrChangedFlag

• kI3C_SlaveReceivedCCCFlag

• kI3C_SlaveErrorFlag

• kI3C_SlaveHDRCommandMatchFlag

• kI3C_SlaveCCCHandledFlag

• kI3C_SlaveEventSentFlag

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests.

Only below flags can be disabled as interrupts.

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

• kI3C_SlaveRxReadyFlag

• kI3C_SlaveTxReadyFlag

• kI3C_SlaveDynamicAddrChangedFlag

• kI3C_SlaveReceivedCCCFlag

• kI3C_SlaveErrorFlag

• kI3C_SlaveHDRCommandMatchFlag

• kI3C_SlaveCCCHandledFlag

• kI3C_SlaveEventSentFlag

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts.

static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C master DMA requests.

Parameters:

• base – The I3C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

• width – DMA read/write unit in bytes.

static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master transmit data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Master Transmit Data Register address.

static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master receive data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Master Receive Data Register address.

static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests.

Parameters:

• base – The I3C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

• width – DMA read/write unit in bytes.

static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Slave Transmit Data Register address.

static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Slave Receive Data Register address.

static inline void I3C_MasterSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C master FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txLvl – Transmit FIFO watermark level. The kI3C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.

• rxLvl – Receive FIFO watermark level. The kI3C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.

• flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.

• flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.

static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C master FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.

• rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.

• flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.

• flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.

static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz)

Sets the I3C bus frequency for master transactions.

The I3C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Parameters:

• base – The I3C peripheral base address.

• baudRate_Hz – Pointer to structure of requested bus frequency in Hertz.

• sourceClock_Hz – I3C functional clock frequency in Hertz.

static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)

Returns whether the bus is idle.

Requires the master mode to be enabled.

Parameters:

• base – The I3C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

status_t I3C_MasterStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified in the call.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the a address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

• base – The I3C peripheral base address.

• type – The bus type to use in this transaction.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

• rxSize – Read terminate size for the followed read transfer, limit to 255 bytes.

Return values:

• kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a START signal and slave address on the I2C/I3C bus.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

• base – The I3C peripheral base address.

• type – The bus type to use in this transaction.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

status_t I3C_MasterRepeatedStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified in the call.

This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize configuration.

Note

This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

• base – The I3C peripheral base address.

• type – The bus type to use in this transaction.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

• rxSize – Read terminate size for the followed read transfer, limit to 255 bytes.

Return values:

kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.

static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a repeated START signal and slave address on the I2C/I3C bus.

This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address.

Note

This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

• base – The I3C peripheral base address.

• type – The bus type to use in this transaction.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.

status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)

Performs a polling send transfer on the I2C/I3C bus.

Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_I3C_Nak.

Parameters:

• base – The I3C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

• flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options.

Return values:

• kStatus_Success – Data was sent successfully.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

• kStatus_I3C_Timeout – The module has stalled too long in a frame.

• kStatus_I3C_Nak – The slave device sent a NAK in response to an address.

• kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write.

• kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.

• kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full.

• kStatus_I3C_InvalidReq – Invalid use of request.

status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)

Performs a polling receive transfer on the I2C/I3C bus.

Parameters:

• base – The I3C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

• flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

• kStatus_I3C_Timeout – The module has stalled too long in a frame.

• kStatus_I3C_Term – The master terminates slave read.

• kStatus_I3C_HdrParityError – Parity error from DDR read.

• kStatus_I3C_CrcError – CRC error from DDR read.

• kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.

• kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty.

• kStatus_I3C_InvalidReq – Invalid use of request.

status_t I3C_MasterStop(I3C_Type *base)

Sends a STOP signal on the I2C/I3C bus.

This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

• base – The I3C peripheral base address.

Return values:

• kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

• kStatus_I3C_Timeout – The module has stalled too long in a frame.

• kStatus_I3C_InvalidReq – Invalid use of request.

void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq)

I3C master emit request.

Parameters:

• base – The I3C peripheral base address.

• masterReq – I3C master request of type i3c_bus_request_t

static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)

I3C master emit request.

Parameters:

• base – The I3C peripheral base address.

• ibiResponse – I3C master emit IBI response of type i3c_ibi_response_t

void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master register IBI rule.

Parameters:

• base – The I3C peripheral base address.

• ibiRule – Pointer to ibi rule description of type i3c_register_ibi_addr_t

void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master get IBI rule.

Parameters:

• base – The I3C peripheral base address.

• ibiRule – Pointer to store the read out ibi rule description.

i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base)

I3C master get IBI Type.

Parameters:

• base – The I3C peripheral base address.

Return values:

i3c_ibi_type_t – Type of i3c_ibi_type_t.

static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)

I3C master get IBI Address.

Parameters:

• base – The I3C peripheral base address.

Return values:

The – 8-bit IBI address.

status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint8_t *addressList, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate)

Performs a DAA in the i3c bus with specified temporary baud rate.

Parameters:

• base – The I3C peripheral base address.

• addressList – The pointer for address list which is used to do DAA.

• count – The address count in the address list.

• daaBaudRate – The temporary baud rate in DAA process, NULL for using initial setting. The initial setting is set back between the completion of the DAA and the return of this function.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

• kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)

Performs a DAA in the i3c bus.

Parameters:

• base – The I3C peripheral base address.

• addressList – The pointer for address list which is used to do DAA.

• count – The address count in the address list. The initial setting is set back between the completion of the DAA and the return of this function.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

• kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count)

Get device information list after DAA process is done.

Parameters:

• base – The I3C peripheral base address.

• count – [out] The pointer to store the available device count.

Returns:

Pointer to the i3c_device_info_t array.

void I3C_MasterClearDeviceCount(I3C_Type *base)

Clear the global device count which represents current devices number on the bus. When user resets all dynamic addresses on the bus, should call this API.

Parameters:

• base – The I3C peripheral base address.

status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C/I3C bus.

Note

The API does not return until the transfer succeeds or fails due to error happens during transfer.

Parameters:

• base – The I3C peripheral base address.

• transfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_I3C_Busy – Another master is currently utilizing the bus.

• kStatus_I3C_IBIWon – The I3C slave event IBI or MR or HJ won the arbitration on a header address.

• kStatus_I3C_Timeout – The module has stalled too long in a frame.

• kStatus_I3C_Nak – The slave device sent a NAK in response to an address.

• kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write.

• kStatus_I3C_Term – The master terminates slave read.

• kStatus_I3C_HdrParityError – Parity error from DDR read.

• kStatus_I3C_CrcError – CRC error from DDR read.

• kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state.

• kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty.

• kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full.

• kStatus_I3C_InvalidReq – Invalid use of request.

status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus.

Parameters:

• base – The I3C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

Returns:

Error or success status returned by API.

status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus.

Parameters:

• base – The I3C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

Returns:

Error or success status returned by API.

void I3C_MasterTransferCreateHandle(I3C_Type *base, i3c_master_handle_t *handle, const i3c_master_transfer_callback_t *callback, void *userData)

Creates a new handle for the I3C master non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The I3C peripheral base address.

• handle – [out] Pointer to the I3C master driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C/I3C bus.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)

Terminates a non-blocking I3C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the I3C peripheral’s IRQ priority.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The I3C peripheral base address.

• intHandle – Pointer to the I3C master driver handle.

enum _i3c_master_flags

I3C master peripheral flags.

The following status register flags can be cleared:

• kI3C_MasterSlaveStartFlag

• kI3C_MasterControlDoneFlag

• kI3C_MasterCompleteFlag

• kI3C_MasterArbitrationWonFlag

• kI3C_MasterSlave2MasterFlag

All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kI3C_MasterBetweenFlag

Between messages/DAAs flag

enumerator kI3C_MasterNackDetectFlag

NACK detected flag

enumerator kI3C_MasterSlaveStartFlag

Slave request start flag

enumerator kI3C_MasterControlDoneFlag

Master request complete flag

enumerator kI3C_MasterCompleteFlag

Transfer complete flag

enumerator kI3C_MasterRxReadyFlag

Rx data ready in Rx buffer flag

enumerator kI3C_MasterTxReadyFlag

Tx buffer ready for Tx data flag

enumerator kI3C_MasterArbitrationWonFlag

Header address won arbitration flag

enumerator kI3C_MasterErrorFlag

Error occurred flag

enumerator kI3C_MasterSlave2MasterFlag

Switch from slave to master flag

enumerator kI3C_MasterClearFlags

enum _i3c_master_error_flags

I3C master error flags to indicate the causes.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kI3C_MasterErrorNackFlag

Slave NACKed the last address

enumerator kI3C_MasterErrorWriteAbortFlag

Slave NACKed the write data

enumerator kI3C_MasterErrorParityFlag

Parity error from DDR read

enumerator kI3C_MasterErrorCrcFlag

CRC error from DDR read

enumerator kI3C_MasterErrorReadFlag

Read from MRDATAB register when FIFO empty

enumerator kI3C_MasterErrorWriteFlag

Write to MWDATAB register when FIFO full

enumerator kI3C_MasterErrorMsgFlag

Message SDR/DDR mismatch or read/write message in wrong state

enumerator kI3C_MasterErrorInvalidReqFlag

Invalid use of request

enumerator kI3C_MasterErrorTimeoutFlag

The module has stalled too long in a frame

enumerator kI3C_MasterAllErrorFlags

All error flags

enum _i3c_master_state

I3C working master state.

Values:

enumerator kI3C_MasterStateIdle

Bus stopped.

enumerator kI3C_MasterStateSlvReq

Bus stopped but slave holding SDA low.

enumerator kI3C_MasterStateMsgSdr

In SDR Message mode from using MWMSG_SDR.

enumerator kI3C_MasterStateNormAct

In normal active SDR mode.

enumerator kI3C_MasterStateDdr

In DDR Message mode.

enumerator kI3C_MasterStateDaa

In ENTDAA mode.

enumerator kI3C_MasterStateIbiAck

Waiting on IBI ACK/NACK decision.

enumerator kI3C_MasterStateIbiRcv

Receiving IBI.

enum _i3c_master_enable

I3C master enable configuration.

Values:

enumerator kI3C_MasterOff

Master off.

enumerator kI3C_MasterOn

Master on.

enumerator kI3C_MasterCapable

Master capable.

enum _i3c_master_hkeep

I3C high keeper configuration.

Values:

enumerator kI3C_MasterHighKeeperNone

Use PUR to hold SCL high.

enumerator kI3C_MasterHighKeeperWiredIn

Use pin_HK controls.

enumerator kI3C_MasterPassiveSDA

Hi-Z for Bus Free and hold SDA.

enumerator kI3C_MasterPassiveSDASCL

Hi-Z both for Bus Free, and can Hi-Z SDA for hold.

enum _i3c_bus_request

Emits the requested operation when doing in pieces vs. by message.

Values:

enumerator kI3C_RequestNone

No request.

enumerator kI3C_RequestEmitStartAddr

Request to emit start and address on bus.

enumerator kI3C_RequestEmitStop

Request to emit stop on bus.

enumerator kI3C_RequestIbiAckNack

Manual IBI ACK or NACK.

enumerator kI3C_RequestProcessDAA

Process DAA.

enumerator kI3C_RequestForceExit

Request to force exit.

enumerator kI3C_RequestAutoIbi

Hold in stopped state, but Auto-emit START,7E.

enum _i3c_bus_type

Bus type with EmitStartAddr.

Values:

enumerator kI3C_TypeI3CSdr

SDR mode of I3C.

enumerator kI3C_TypeI2C

Standard i2c protocol.

enumerator kI3C_TypeI3CDdr

HDR-DDR mode of I3C.

enum _i3c_ibi_response

IBI response.

Values:

enumerator kI3C_IbiRespAck

ACK with no mandatory byte.

enumerator kI3C_IbiRespNack

NACK.

enumerator kI3C_IbiRespAckMandatory

ACK with mandatory byte.

enumerator kI3C_IbiRespManual

Reserved.

enum _i3c_ibi_type

IBI type.

Values:

enumerator kI3C_IbiNormal

In-band interrupt.

enumerator kI3C_IbiHotJoin

slave hot join.

enumerator kI3C_IbiMasterRequest

slave master ship request.

enum _i3c_ibi_state

IBI state.

Values:

enumerator kI3C_IbiReady

In-band interrupt ready state, ready for user to handle.

enumerator kI3C_IbiDataBuffNeed

In-band interrupt need data buffer for data receive.

enumerator kI3C_IbiAckNackPending

In-band interrupt Ack/Nack pending for decision.

enum _i3c_direction

Direction of master and slave transfers.

Values:

enumerator kI3C_Write

Master transmit.

enumerator kI3C_Read

Master receive.

enum _i3c_tx_trigger_level

Watermark of TX int/dma trigger level.

Values:

enumerator kI3C_TxTriggerOnEmpty

Trigger on empty.

enumerator kI3C_TxTriggerUntilOneQuarterOrLess

Trigger on 1/4 full or less.

enumerator kI3C_TxTriggerUntilOneHalfOrLess

Trigger on 1/2 full or less.

enumerator kI3C_TxTriggerUntilOneLessThanFull

Trigger on 1 less than full or less.

enum _i3c_rx_trigger_level

Watermark of RX int/dma trigger level.

Values:

enumerator kI3C_RxTriggerOnNotEmpty

Trigger on not empty.

enumerator kI3C_RxTriggerUntilOneQuarterOrMore

Trigger on 1/4 full or more.

enumerator kI3C_RxTriggerUntilOneHalfOrMore

Trigger on 1/2 full or more.

enumerator kI3C_RxTriggerUntilThreeQuarterOrMore

Trigger on 3/4 full or more.

enum _i3c_rx_term_ops

I3C master read termination operations.

Values:

enumerator kI3C_RxTermDisable

Master doesn’t terminate read, used for CCC transfer.

enumerator kI3C_RxAutoTerm

Master auto terminate read after receiving specified bytes(<=255).

enumerator kI3C_RxTermLastByte

Master terminates read at any time after START, no length limitation.

enum _i3c_start_scl_delay

I3C start SCL delay options.

Values:

enumerator kI3C_NoDelay

No delay.

enumerator kI3C_IncreaseSclHalfPeriod

Increases SCL clock period by 1/2.

enumerator kI3C_IncreaseSclOnePeriod

Increases SCL clock period by 1.

enumerator kI3C_IncreaseSclOneAndHalfPeriod

Increases SCL clock period by 1 1/2

enum _i3c_master_transfer_flags

Transfer option flags.

Note

These enumerations are intended to be OR’d together to form a bit mask of options for the _i3c_master_transfer::flags field.

Values:

enumerator kI3C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal.

enumerator kI3C_TransferNoStartFlag

Don’t send a start condition, address, and sub address

enumerator kI3C_TransferRepeatedStartFlag

Send a repeated start condition

enumerator kI3C_TransferNoStopFlag

Don’t send a stop condition.

enumerator kI3C_TransferWordsFlag

Transfer in words, else transfer in bytes.

enumerator kI3C_TransferDisableRxTermFlag

Disable Rx termination. Note: It’s for I3C CCC transfer.

enumerator kI3C_TransferRxAutoTermFlag

Set Rx auto-termination. Note: It’s adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive.

enumerator kI3C_TransferStartWithBroadcastAddr

Start transfer with 0x7E, then read/write data with device address.

typedef enum _i3c_master_state i3c_master_state_t

I3C working master state.

typedef enum _i3c_master_enable i3c_master_enable_t

I3C master enable configuration.

typedef enum _i3c_master_hkeep i3c_master_hkeep_t

I3C high keeper configuration.

typedef enum _i3c_bus_request i3c_bus_request_t

Emits the requested operation when doing in pieces vs. by message.

typedef enum _i3c_bus_type i3c_bus_type_t

Bus type with EmitStartAddr.

typedef enum _i3c_ibi_response i3c_ibi_response_t

IBI response.

typedef enum _i3c_ibi_type i3c_ibi_type_t

IBI type.

typedef enum _i3c_ibi_state i3c_ibi_state_t

IBI state.

typedef enum _i3c_direction i3c_direction_t

Direction of master and slave transfers.

typedef enum _i3c_tx_trigger_level i3c_tx_trigger_level_t

Watermark of TX int/dma trigger level.

typedef enum _i3c_rx_trigger_level i3c_rx_trigger_level_t

Watermark of RX int/dma trigger level.

typedef enum _i3c_rx_term_ops i3c_rx_term_ops_t

I3C master read termination operations.

typedef enum _i3c_start_scl_delay i3c_start_scl_delay_t

I3C start SCL delay options.

typedef struct _i3c_register_ibi_addr i3c_register_ibi_addr_t

Structure with setting master IBI rules and slave registry.

typedef struct _i3c_baudrate i3c_baudrate_hz_t

Structure with I3C baudrate settings.

typedef struct _i3c_master_daa_baudrate i3c_master_daa_baudrate_t

I3C DAA baud rate configuration.

typedef struct _i3c_master_config i3c_master_config_t

Structure with settings to initialize the I3C master module.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef struct _i3c_master_transfer i3c_master_transfer_t

typedef struct _i3c_master_handle i3c_master_handle_t

typedef struct _i3c_master_transfer_callback i3c_master_transfer_callback_t

i3c master callback functions.

typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle)

Typedef for master interrupt handler.

struct _i3c_register_ibi_addr

#include <fsl_i3c.h>

Structure with setting master IBI rules and slave registry.

Public Members

uint8_t address[5]

Address array for registry.

bool i3cFastStart

Allow the START header to run as push-pull speed if all dynamic addresses take MSB 0.

bool ibiHasPayload

Whether the address array has mandatory IBI byte.

struct _i3c_baudrate

#include <fsl_i3c.h>

Structure with I3C baudrate settings.

Public Members

uint32_t i2cBaud

Desired I2C baud rate in Hertz.

uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz.

uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz.

struct _i3c_master_daa_baudrate

#include <fsl_i3c.h>

I3C DAA baud rate configuration.

Public Members

uint32_t sourceClock_Hz

FCLK, function clock in Hertz.

uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz.

uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz.

struct _i3c_master_config

#include <fsl_i3c.h>

Structure with settings to initialize the I3C master module.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

i3c_master_enable_t enableMaster

Enable master mode.

bool disableTimeout

Whether to disable timeout to prevent the ERRWARN.

i3c_master_hkeep_t hKeep

High keeper mode setting.

bool enableOpenDrainStop

Whether to emit open-drain speed STOP.

bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD.

i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings.

struct _i3c_master_transfer_callback

#include <fsl_i3c.h>

i3c master callback functions.

Public Members

void (*slave2Master)(I3C_Type *base, void *userData)

Transfer complete callback

void (*ibiCallback)(I3C_Type *base, i3c_master_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback

void (*transferComplete)(I3C_Type *base, i3c_master_handle_t *handle, status_t completionStatus, void *userData)

Transfer complete callback

struct _i3c_master_transfer

#include <fsl_i3c.h>

Non-blocking transfer descriptor structure.

This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API.

Public Members

uint32_t flags

Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. Set to 0 or kI3C_TransferDefaultFlag for normal transfers.

uint8_t slaveAddress

The 7-bit slave address.

i3c_direction_t direction

Either kI3C_Read or kI3C_Write.

uint32_t subaddress

Sub address. Transferred MSB first.

size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes.

void *data

Pointer to data to transfer.

size_t dataSize

Number of bytes to transfer.

i3c_bus_type_t busType

bus type.

i3c_ibi_response_t ibiResponse

ibi response during transfer.

struct _i3c_master_handle

#include <fsl_i3c.h>

Driver handle for master non-blocking APIs.

Note

The contents of this structure are private and subject to change.

Public Members

uint8_t state

Transfer state machine current state.

uint32_t remainingBytes

Remaining byte count in current state.

i3c_rx_term_ops_t rxTermOps

Read termination operation.

i3c_master_transfer_t transfer

Copy of the current transfer info.

uint8_t ibiAddress

Slave address which request IBI.

uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes.

size_t ibiPayloadSize

IBI payload size.

i3c_ibi_type_t ibiType

IBI type.

i3c_master_transfer_callback_t callback

Callback functions pointer.

void *userData

Application data passed to callback.

I3C Master DMA Driver

void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, const i3c_master_edma_callback_t *callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C master DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.

For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

• rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function.

• txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function.

status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I3C bus.

The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.

void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)

Terminates a non-blocking I3C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the DMA peripheral’s IRQ priority.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C master driver handle.

void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The I3C peripheral base address.

• i3cHandle – Pointer to the I3C master DMA driver handle.

typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t

typedef struct _i3c_master_edma_callback i3c_master_edma_callback_t

i3c master callback functions.

struct _i3c_master_edma_callback

#include <fsl_i3c_edma.h>

i3c master callback functions.

Public Members

void (*slave2Master)(I3C_Type *base, void *userData)

Target asks for controller request.

void (*ibiCallback)(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback.

void (*transferComplete)(I3C_Type *base, i3c_master_edma_handle_t *handle, status_t status, void *userData)

Transfer complete callback.

struct _i3c_master_edma_handle

#include <fsl_i3c_edma.h>

Driver handle for master EDMA APIs.

Note

The contents of this structure are private and subject to change.

Public Members

I3C_Type *base

I3C base pointer.

uint8_t state

Transfer state machine current state.

uint32_t transferCount

Indicates progress of the transfer

uint8_t subaddressBuffer[4]

Saving subaddress command.

uint8_t subaddressCount

Saving command count.

i3c_master_transfer_t transfer

Copy of the current transfer info.

i3c_master_edma_callback_t callback

Callback function pointer.

void *userData

Application data passed to callback.

edma_handle_t *rxDmaHandle

Handle for receive DMA channel.

edma_handle_t *txDmaHandle

Handle for transmit DMA channel.

bool ibiFlag

IBIWON flag.

uint8_t ibiAddress

Slave address which request IBI.

uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes.

size_t ibiPayloadSize

IBI payload size.

i3c_ibi_type_t ibiType

IBI type.

status_t result

Transfer result.

I3C Slave Driver

void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral.

This function provides the following default configuration for the I3C slave peripheral:

slaveConfig->enableslave             = true;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

• slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t.

void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral.

This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

• base – The I3C peripheral base address.

• slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override.

• slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.

void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral.

This function disables the I3C slave peripheral and gates the clock.

Parameters:

• base – The I3C peripheral base address.

static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave.

Parameters:

• base – The I3C peripheral base address.

• isEnable – Enable or disable.

static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags.

A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_slave_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state.

The following status register flags can be cleared:

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

Attempts to clear other flags has no effect.

See also

_i3c_slave_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags().

static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags.

A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_i3c_slave_error_flags

Parameters:

• base – The I3C peripheral base address.

Returns:

State of the error status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state.

See also

_i3c_slave_error_flags.

Parameters:

• base – The I3C peripheral base address.

• statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags().

i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state.

Parameters:

• base – The I3C peripheral base address.

Returns:

I3C slave activity state, refer i3c_slave_activity_state_t.

status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)

static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests.

Only below flags can be enabled as interrupts.

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

• kI3C_SlaveRxReadyFlag

• kI3C_SlaveTxReadyFlag

• kI3C_SlaveDynamicAddrChangedFlag

• kI3C_SlaveReceivedCCCFlag

• kI3C_SlaveErrorFlag

• kI3C_SlaveHDRCommandMatchFlag

• kI3C_SlaveCCCHandledFlag

• kI3C_SlaveEventSentFlag

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests.

Only below flags can be disabled as interrupts.

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

• kI3C_SlaveRxReadyFlag

• kI3C_SlaveTxReadyFlag

• kI3C_SlaveDynamicAddrChangedFlag

• kI3C_SlaveReceivedCCCFlag

• kI3C_SlaveErrorFlag

• kI3C_SlaveHDRCommandMatchFlag

• kI3C_SlaveCCCHandledFlag

• kI3C_SlaveEventSentFlag

Parameters:

• base – The I3C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests.

Parameters:

• base – The I3C peripheral base address.

Returns:

A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts.

static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests.

Parameters:

• base – The I3C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

• width – DMA read/write unit in bytes.

static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Slave Transmit Data Register address.

static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer.

Parameters:

• base – The I3C peripheral base address.

• width – DMA read/write unit in bytes.

Returns:

The I3C Slave Receive Data Register address.

static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl.

• rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl.

• flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.

• flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.

static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs.

Parameters:

• base – The I3C peripheral base address.

• txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus.

Parameters:

• base – The I3C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

Returns:

Error or success status returned by API.

status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus.

Parameters:

• base – The I3C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

Returns:

Error or success status returned by API.

void I3C_SlaveTransferCreateHandle(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the I3C slave non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The I3C peripheral base address.

• handle – [out] Pointer to the I3C slave driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers.

Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i3c_slave_transfer_event_t enumerators for the events you wish to receive. The kI3C_SlaveTransmitEvent and kI3C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI3C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.

• eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI3C_SlaveAllEvents to enable all events.

Return values:

• kStatus_Success – Slave transfers were successfully started.

• kStatus_I3C_Busy – Slave transfers have already been started on this handle.

status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to i2c_slave_handle_t structure.

• count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress –

void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle)

Aborts the slave non-blocking transfers.

Note

This API could be called at any time to stop slave for handling the bus events.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.

void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The I3C peripheral base address.

• intHandle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state.

enum _i3c_slave_flags

I3C slave peripheral flags.

The following status register flags can be cleared:

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

Only below flags can be enabled as interrupts.

• kI3C_SlaveBusStartFlag

• kI3C_SlaveMatchedFlag

• kI3C_SlaveBusStopFlag

• kI3C_SlaveRxReadyFlag

• kI3C_SlaveTxReadyFlag

• kI3C_SlaveDynamicAddrChangedFlag

• kI3C_SlaveReceivedCCCFlag

• kI3C_SlaveErrorFlag

• kI3C_SlaveHDRCommandMatchFlag

• kI3C_SlaveCCCHandledFlag

• kI3C_SlaveEventSentFlag

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kI3C_SlaveNotStopFlag

Slave status not stop flag

enumerator kI3C_SlaveMessageFlag

Slave status message, indicating slave is listening to the bus traffic or responding

enumerator kI3C_SlaveRequiredReadFlag

Slave status required, either is master doing SDR read from slave, or is IBI pushing out.

enumerator kI3C_SlaveRequiredWriteFlag

Slave status request write, master is doing SDR write to slave, except slave in ENTDAA mode

enumerator kI3C_SlaveBusDAAFlag

I3C bus is in ENTDAA mode

enumerator kI3C_SlaveBusHDRModeFlag

I3C bus is in HDR mode

enumerator kI3C_SlaveBusStartFlag

Start/Re-start event is seen since the bus was last cleared

enumerator kI3C_SlaveMatchedFlag

Slave address(dynamic/static) matched since last cleared

enumerator kI3C_SlaveBusStopFlag

Stop event is seen since the bus was last cleared

enumerator kI3C_SlaveRxReadyFlag

Rx data ready in rx buffer flag

enumerator kI3C_SlaveTxReadyFlag

Tx buffer ready for Tx data flag

enumerator kI3C_SlaveDynamicAddrChangedFlag

Slave dynamic address has been assigned, re-assigned, or lost

enumerator kI3C_SlaveReceivedCCCFlag

Slave received Common command code

enumerator kI3C_SlaveErrorFlag

Error occurred flag

enumerator kI3C_SlaveHDRCommandMatchFlag

High data rate command match

enumerator kI3C_SlaveCCCHandledFlag

Slave received Common command code is handled by I3C module

enumerator kI3C_SlaveEventSentFlag

Slave IBI/P2P/MR/HJ event has been sent

enumerator kI3C_SlaveIbiDisableFlag

Slave in band interrupt is disabled.

enumerator kI3C_SlaveMasterRequestDisabledFlag

Slave master request is disabled.

enumerator kI3C_SlaveHotJoinDisabledFlag

Slave Hot-Join is disabled.

enumerator kI3C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kI3C_SlaveAllIrqFlags

enum _i3c_slave_error_flags

I3C slave error flags to indicate the causes.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kI3C_SlaveErrorOverrunFlag

Slave internal from-bus buffer/FIFO overrun.

enumerator kI3C_SlaveErrorUnderrunFlag

Slave internal to-bus buffer/FIFO underrun

enumerator kI3C_SlaveErrorUnderrunNakFlag

Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kI3C_SlaveErrorTermFlag

Terminate error from master

enumerator kI3C_SlaveErrorInvalidStartFlag

Slave invalid start flag

enumerator kI3C_SlaveErrorSdrParityFlag

SDR parity error

enumerator kI3C_SlaveErrorHdrParityFlag

HDR parity error

enumerator kI3C_SlaveErrorHdrCRCFlag

HDR-DDR CRC error

enumerator kI3C_SlaveErrorS0S1Flag

S0 or S1 error

enumerator kI3C_SlaveErrorOverreadFlag

Over-read error

enumerator kI3C_SlaveErrorOverwriteFlag

Over-write error

enum _i3c_slave_event

I3C slave.event.

Values:

enumerator kI3C_SlaveEventNormal

Normal mode.

enumerator kI3C_SlaveEventIBI

In band interrupt event.

enumerator kI3C_SlaveEventMasterReq

Master request event.

enumerator kI3C_SlaveEventHotJoinReq

Hot-join event.

enum _i3c_slave_activity_state

I3C slave.activity state.

Values:

enumerator kI3C_SlaveNoLatency

Normal bus operation

enumerator kI3C_SlaveLatency1Ms

1ms of latency.

enumerator kI3C_SlaveLatency100Ms

100ms of latency.

enumerator kI3C_SlaveLatency10S

10s latency.

enum _i3c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kI3C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start.

enumerator kI3C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role).

enumerator kI3C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kI3C_SlaveRequiredTransmitEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kI3C_SlaveStartEvent

A start/repeated start was detected.

enumerator kI3C_SlaveHDRCommandMatchEvent

Slave Match HDR Command.

enumerator kI3C_SlaveCompletionEvent

A stop was detected, completing the transfer.

enumerator kI3C_SlaveRequestSentEvent

Slave request event sent.

enumerator kI3C_SlaveReceivedCCCEvent

Slave received CCC event, need to handle by application.

enumerator kI3C_SlaveAllEvents

Bit mask of all available events.

typedef enum _i3c_slave_event i3c_slave_event_t

I3C slave.event.

typedef enum _i3c_slave_activity_state i3c_slave_activity_state_t

I3C slave.activity state.

typedef struct _i3c_slave_config i3c_slave_config_t

Structure with settings to initialize the I3C slave module.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _i3c_slave_transfer_event i3c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _i3c_slave_transfer i3c_slave_transfer_t

I3C slave transfer structure.

typedef struct _i3c_slave_handle i3c_slave_handle_t

typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type.

This callback is used only for the slave non-blocking transfer API. To install a callback, use the I3C_SlaveSetCallback() function after you have created a handle.

Param base:

Base address for the I3C instance on which the event occurred.

Param transfer:

Pointer to transfer descriptor containing values passed to and/or from the callback.

Param userData:

Arbitrary pointer-sized value passed from the application.

typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle)

Typedef for slave interrupt handler.

struct _i3c_slave_config

#include <fsl_i3c.h>

Structure with settings to initialize the I3C slave module.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableSlave

Whether to enable slave.

uint8_t staticAddr

Static address.

uint16_t vendorID

Device vendor ID(manufacture ID).

uint32_t partNumber

Device part number info

uint8_t dcr

Device characteristics register information.

uint8_t bcr

Bus characteristics register information.

uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t.

bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC.

bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode.

bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely.

bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed.

uint32_t maxWriteLength

Maximum write length.

uint32_t maxReadLength

Maximum read length.

struct _i3c_slave_transfer

#include <fsl_i3c.h>

I3C slave transfer structure.

Public Members

uint32_t event

Reason the callback is being invoked.

uint8_t *txData

Transfer buffer

size_t txDataSize

Transfer size

uint8_t *rxData

Transfer buffer

size_t rxDataSize

Transfer size

status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent.

size_t transferredCount

Number of bytes actually transferred since start or last repeated start.

struct _i3c_slave_handle

#include <fsl_i3c.h>

I3C slave handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

i3c_slave_transfer_t transfer

I3C slave transfer copy.

bool isBusy

Whether transfer is busy.

bool wasTransmit

Whether the last transfer was a transmit.

uint32_t eventMask

Mask of enabled events.

uint32_t transferredCount

Count of bytes transferred.

i3c_slave_transfer_callback_t callback

Callback function called at transfer event.

void *userData

Callback parameter passed to callback.

size_t txFifoSize

Tx Fifo size

I3C Slave DMA Driver

void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C slave DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.

For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C slave driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

• rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function.

• txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function.

status_t I3C_SlaveTransferEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_transfer_t *transfer, uint32_t eventMask)

Prepares for a non-blocking DMA-based transaction on the I3C bus.

The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when there’s bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned with master application to ensure the transfer is executed as expected. Callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

• base – The I3C peripheral base address.

• handle – Pointer to the I3C slave driver handle.

• transfer – The pointer to the transfer descriptor.

• eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. The transmit and receive events is not allowed to be enabled.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

• kStatus_Fail – The transaction can’t be set.

void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)

Abort a slave edma non-blocking transfer in a early time.

Parameters:

• base – I3C peripheral base address

• handle – pointer to i3c_slave_edma_handle_t structure

void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The I3C peripheral base address.

• i3cHandle – Pointer to the I3C slave DMA driver handle.

typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t

typedef struct _i3c_slave_edma_transfer i3c_slave_edma_transfer_t

I3C slave transfer structure.

typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData)

Slave event callback function pointer type.

This callback is used only for the slave DMA transfer API.

Param base:

Base address for the I3C instance on which the event occurred.

Param handle:

Pointer to slave DMA transfer handle.

Param transfer:

Pointer to transfer descriptor containing values passed to and/or from the callback.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _i3c_slave_edma_transfer

#include <fsl_i3c_edma.h>

I3C slave transfer structure.

Public Members

uint32_t event

Reason the callback is being invoked.

uint8_t *txData

Transfer buffer

size_t txDataSize

Transfer size

uint8_t *rxData

Transfer buffer

size_t rxDataSize

Transfer size

status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent.

struct _i3c_slave_edma_handle

#include <fsl_i3c_edma.h>

I3C slave edma handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

I3C_Type *base

I3C base pointer.

i3c_slave_edma_transfer_t transfer

I3C slave transfer copy.

bool isBusy

Whether transfer is busy.

bool wasTransmit

Whether the last transfer was a transmit.

bool isDdrMode

Whether this is HDR-DDR transfer.

uint32_t eventMask

Mask of enabled events.

i3c_slave_edma_callback_t callback

Callback function called at transfer event.

edma_handle_t *rxDmaHandle

Handle for receive DMA channel.

edma_handle_t *txDmaHandle

Handle for transmit DMA channel.

void *userData

Callback parameter passed to callback.

IEE: Inline Encryption Engine

FSL_IEE_DRIVER_VERSION

IEE driver version. Version 2.1.1.

Current version: 2.1.1

Change log:

• Version 2.0.0

  • Initial version

• Version 2.1.0

  • Add region lock function IEE_LockRegionConfig() and driver clock control

• Version 2.1.1

  • Fixed MISRA issues.

• Version 2.2.0

  • Add ELE (EdgeLock Enclave) key provisioning feature.

enum _iee_region

IEE region.

Values:

enumerator kIEE_Region0

IEE region 0

enumerator kIEE_Region1

IEE region 1

enumerator kIEE_Region2

IEE region 2

enumerator kIEE_Region3

IEE region 3

enumerator kIEE_Region4

IEE region 4

enumerator kIEE_Region5

IEE region 5

enumerator kIEE_Region6

IEE region 6

enumerator kIEE_Region7

IEE region 7

enum _iee_aes_bypass

IEE AES enablement/bypass.

Values:

enumerator kIEE_AesUseMdField

AES encryption/decryption enabled

enumerator kIEE_AesBypass

AES encryption/decryption bypass

enum _iee_aes_mode

IEE AES mode.

Values:

enumerator kIEE_ModeNone

AES NONE mode

enumerator kIEE_ModeAesXTS

AES XTS mode

enumerator kIEE_ModeAesCTRWAddress

AES CTR w address binding mode

enumerator kIEE_ModeAesCTRWOAddress

AES CTR w/o address binding mode

enumerator kIEE_ModeAesCTRkeystream

AES CTR keystream only

enum _iee_aes_key_size

IEE AES key size.

Values:

enumerator kIEE_AesCTR128XTS256

AES 128 bits (CTR), 256 bits (XTS)

enumerator kIEE_AesCTR256XTS512

AES 256 bits (CTR), 512 bits (XTS)

enum _iee_aes_key_num

IEE AES key number.

Values:

enumerator kIEE_AesKey1

AES Key 1

enumerator kIEE_AesKey2

AES Key 2

typedef enum _iee_region iee_region_t

IEE region.

typedef enum _iee_aes_bypass iee_aes_bypass_t

IEE AES enablement/bypass.

typedef enum _iee_aes_mode iee_aes_mode_t

IEE AES mode.

typedef enum _iee_aes_key_size iee_aes_key_size_t

IEE AES key size.

typedef enum _iee_aes_key_num iee_aes_key_num_t

IEE AES key number.

typedef struct _iee_config iee_config_t

IEE configuration structure.

void IEE_Init(IEE_Type *base)

Resets IEE module to factory default values.

This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared.

Parameters:

• base – IEER peripheral address.

void IEE_GetDefaultConfig(iee_config_t *config)

Loads default values to the IEE configuration structure.

Loads default values to the IEE region configuration structure. The default values are as follows.

config->bypass = kIEE_AesUseMdField;
config->mode = kIEE_ModeNone;
config->keySize = kIEE_AesCTR128XTS256;
config->pageOffset = 0U;

Parameters:

• config – Configuration for the selected IEE region.

void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config)

Sets the IEE module according to the configuration structure.

This function configures IEE region according to configuration structure.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be configured.

• config – Configuration for the selected IEE region.

status_t IEE_SetRegionKey(IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize)

Sets the IEE module key.

This function sets specified AES key for the given region.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be configured.

• keyNum – Selection of AES KEY1 or KEY2.

• key – AES key.

• keySize – Size of AES key.

static inline uint32_t IEE_GetOffset(uint32_t addressIee, uint32_t addressMemory)

Computes IEE offset to be set for specifed memory location.

This function calculates offset that must be set for IEE region to access physical memory location.

Parameters:

• addressIee – Address of IEE peripheral.

• addressMemory – Address of physical memory location.

void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region)

Lock the IEE region configuration.

This function locks IEE region registers for Key, Offset and Attribute. Only system reset can clear the Lock bit.

Parameters:

• base – IEE peripheral address.

• region – Selection of the IEE region to be locked.

struct _iee_config

#include <fsl_iee.h>

IEE configuration structure.

Public Members

iee_aes_bypass_t bypass

AES encryption/decryption bypass

iee_aes_mode_t mode

AES mode

iee_aes_key_size_t keySize

size of AES key

uint32_t pageOffset

Offset to physical memory location from IEE start address

Ieer

FSL_IEE_APC_DRIVER_VERSION

IEE_APC driver version. Version 2.0.2.

Current version: 2.0.2

Change log:

• Version 2.0.0

  • Initial version

• Version 2.0.1

  • Fixed MISRA issues.

• Version 2.0.2

  • Update to newer version of implementation in HW.

enum _iee_apc_region

APC IEE regions.

Values:

enumerator kIEE_APC_Region0

APC IEE region 0

enumerator kIEE_APC_Region1

APC IEE region 1

enumerator kIEE_APC_Region2

APC IEE region 2

enumerator kIEE_APC_Region3

APC IEE region 3

enumerator kIEE_APC_Region4

APC IEE region 4

enumerator kIEE_APC_Region5

APC IEE region 5

enumerator kIEE_APC_Region6

APC IEE region 6

enumerator kIEE_APC_Region7

APC IEE region 7

enum _apc_iee_domain

APC IEE domains.

Values:

enumerator kIEE_APC_Domain0

APC IEE region 0

enumerator kIEE_APC_Domain1

APC IEE region 1

typedef enum _iee_apc_region iee_apc_region_t

APC IEE regions.

typedef enum _apc_iee_domain iee_apc_domain_t

APC IEE domains.

void IEE_APC_GlobalEnable(IEE_APC_Type *base)

Enable the APC IEE Region setting.

This function enables IOMUXC LPSR GPR and APC IEE for setting the region.

Parameters:

• base – APC IEE peripheral address.

void IEE_APC_GlobalDisable(IEE_APC_Type *base)

Disables the APC IEE Region setting.

This function disables IOMUXC LPSR GPR and APC IEE for setting the region.

Parameters:

• base – APC IEE peripheral address.

status_t IEE_APC_SetRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, uint32_t startAddr, uint32_t endAddr)

Sets the APC IEE Memory Region Descriptors.

This function configures APC IEE Memory Region Descriptor according to region configuration structure.

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be configured.

• startAddr – Start encryption adress for the selected APC IEE region.

• endAddr – End encryption adress for the selected APC IEE region.

status_t IEE_APC_LockRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, iee_apc_domain_t domain)

Lock the LPSR GPR and APC IEE configuration.

This function locks writting to IOMUXC LPSR GPR and APC IEE encryption region setting registers. Only system reset can clear the LPSR GPR and APC IEE-RDC_D0/1 Lock bit

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be locked.

• domain – Core domain ID

void IEE_APC_RegionEnable(IEE_APC_Type *base, iee_apc_region_t region)

Enable the IEE encryption/decryption and can lock this setting.

This function enables encryption/decryption by writting to IOMUXC LPSR GPR.

Parameters:

• base – APC IEE peripheral address.

• region – Selection of the APC IEE region to be enabled.

IOMUXC: IOMUX Controller

enum _iomuxc_mqs_pwm_oversample_rate

Values:

enumerator kIOMUXC_MqsPwmOverSampleRate32

enumerator kIOMUXC_MqsPwmOverSampleRate64

typedef enum _iomuxc_mqs_pwm_oversample_rate iomuxc_mqs_pwm_oversample_rate_t

IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00

IOMUXC_GPIO_EMC_B1_00_XBAR1_XBAR_INOUT04

IOMUXC_GPIO_EMC_B1_00_SINC3_MOD_CLK0

IOMUXC_GPIO_EMC_B1_00_LPUART3_CTS_B

IOMUXC_GPIO_EMC_B1_00_NETC_PINMUX_ETH3_TXD03

IOMUXC_GPIO_EMC_B1_00_GPIO2_IO00

IOMUXC_GPIO_EMC_B1_00_KPP_ROW03

IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00

IOMUXC_GPIO_EMC_B1_00_NETC_PINMUX_ETH4_TXD03

IOMUXC_GPIO_EMC_B1_00_ECAT_TX_DATA3_0

IOMUXC_GPIO_EMC_B1_00_AHB_SRAMC_DATA00

IOMUXC_GPIO_EMC_B1_01_ECAT_TX_DATA2_0

IOMUXC_GPIO_EMC_B1_01_AHB_SRAMC_DATA01

IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01

IOMUXC_GPIO_EMC_B1_01_XBAR1_XBAR_INOUT05

IOMUXC_GPIO_EMC_B1_01_SINC3_MOD_CLK1

IOMUXC_GPIO_EMC_B1_01_LPUART3_RTS_B

IOMUXC_GPIO_EMC_B1_01_NETC_PINMUX_ETH3_TXD02

IOMUXC_GPIO_EMC_B1_01_GPIO2_IO01

IOMUXC_GPIO_EMC_B1_01_KPP_COL03

IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01

IOMUXC_GPIO_EMC_B1_01_NETC_PINMUX_ETH4_TXD02

IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02

IOMUXC_GPIO_EMC_B1_02_XBAR1_XBAR_INOUT06

IOMUXC_GPIO_EMC_B1_02_SINC3_MOD_CLK2

IOMUXC_GPIO_EMC_B1_02_LPUART3_RX

IOMUXC_GPIO_EMC_B1_02_NETC_PINMUX_ETH3_RX_CLK

IOMUXC_GPIO_EMC_B1_02_GPIO2_IO02

IOMUXC_GPIO_EMC_B1_02_KPP_ROW02

IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02

IOMUXC_GPIO_EMC_B1_02_NETC_PINMUX_ETH4_RX_CLK

IOMUXC_GPIO_EMC_B1_02_ECAT_RX_CLK_0

IOMUXC_GPIO_EMC_B1_02_AHB_SRAMC_DATA02

IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03

IOMUXC_GPIO_EMC_B1_03_XBAR1_XBAR_INOUT07

IOMUXC_GPIO_EMC_B1_03_SINC3_EMCLK00

IOMUXC_GPIO_EMC_B1_03_LPUART3_TX

IOMUXC_GPIO_EMC_B1_03_NETC_PINMUX_ETH3_RXD03

IOMUXC_GPIO_EMC_B1_03_GPIO2_IO03

IOMUXC_GPIO_EMC_B1_03_KPP_COL02

IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03

IOMUXC_GPIO_EMC_B1_03_NETC_PINMUX_ETH4_RXD03

IOMUXC_GPIO_EMC_B1_03_ECAT_RX_DATA3_0

IOMUXC_GPIO_EMC_B1_03_AHB_SRAMC_DATA03

IOMUXC_GPIO_EMC_B1_04_ECAT_RX_DATA2_0

IOMUXC_GPIO_EMC_B1_04_AHB_SRAMC_DATA04

IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04

IOMUXC_GPIO_EMC_B1_04_XBAR1_XBAR_INOUT08

IOMUXC_GPIO_EMC_B1_04_SINC3_EMBIT00

IOMUXC_GPIO_EMC_B1_04_LPUART3_DSR_B

IOMUXC_GPIO_EMC_B1_04_NETC_PINMUX_ETH3_RXD02

IOMUXC_GPIO_EMC_B1_04_GPIO2_IO04

IOMUXC_GPIO_EMC_B1_04_KPP_ROW01

IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04

IOMUXC_GPIO_EMC_B1_04_NETC_PINMUX_ETH4_RXD02

IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05

IOMUXC_GPIO_EMC_B1_05_XBAR1_XBAR_INOUT09

IOMUXC_GPIO_EMC_B1_05_SINC3_EMCLK01

IOMUXC_GPIO_EMC_B1_05_LPUART3_DCD_B

IOMUXC_GPIO_EMC_B1_05_NETC_PINMUX_ETH3_TXD00

IOMUXC_GPIO_EMC_B1_05_GPIO2_IO05

IOMUXC_GPIO_EMC_B1_05_KPP_ROW07

IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05

IOMUXC_GPIO_EMC_B1_05_NETC_PINMUX_ETH4_TXD00

IOMUXC_GPIO_EMC_B1_05_ECAT_TX_DATA0_0

IOMUXC_GPIO_EMC_B1_05_AHB_SRAMC_DATA05

IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06

IOMUXC_GPIO_EMC_B1_06_FLEXPWM4_PWMB03

IOMUXC_GPIO_EMC_B1_06_SINC3_EMBIT01

IOMUXC_GPIO_EMC_B1_06_LPUART3_RI_B

IOMUXC_GPIO_EMC_B1_06_NETC_PINMUX_ETH3_TXD01

IOMUXC_GPIO_EMC_B1_06_GPIO2_IO06

IOMUXC_GPIO_EMC_B1_06_KPP_COL07

IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06

IOMUXC_GPIO_EMC_B1_06_NETC_PINMUX_ETH4_TXD01

IOMUXC_GPIO_EMC_B1_06_ECAT_TX_DATA1_0

IOMUXC_GPIO_EMC_B1_06_AHB_SRAMC_DATA06

IOMUXC_GPIO_EMC_B1_07_ECAT_TX_EN_0

IOMUXC_GPIO_EMC_B1_07_AHB_SRAMC_DATA07

IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07

IOMUXC_GPIO_EMC_B1_07_FLEXPWM4_PWMA03

IOMUXC_GPIO_EMC_B1_07_SINC3_EMCLK02

IOMUXC_GPIO_EMC_B1_07_LPUART3_DTR_B

IOMUXC_GPIO_EMC_B1_07_NETC_PINMUX_ETH3_TX_EN

IOMUXC_GPIO_EMC_B1_07_GPIO2_IO07

IOMUXC_GPIO_EMC_B1_07_KPP_ROW06

IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07

IOMUXC_GPIO_EMC_B1_07_NETC_PINMUX_ETH4_TX_EN

IOMUXC_GPIO_EMC_B1_08_SEMC_DM00

IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWMB03

IOMUXC_GPIO_EMC_B1_08_SINC3_EMBIT02

IOMUXC_GPIO_EMC_B1_08_LPUART4_DSR_B

IOMUXC_GPIO_EMC_B1_08_NETC_PINMUX_ETH3_TX_CLK

IOMUXC_GPIO_EMC_B1_08_GPIO2_IO08

IOMUXC_GPIO_EMC_B1_08_KPP_COL06

IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08

IOMUXC_GPIO_EMC_B1_08_NETC_PINMUX_ETH4_TX_CLK

IOMUXC_GPIO_EMC_B1_08_ECAT_TX_CLK_0

IOMUXC_GPIO_EMC_B1_08_AHB_SRAMC_LBB

IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00

IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWMA03

IOMUXC_GPIO_EMC_B1_09_SINC3_EMCLK03

IOMUXC_GPIO_EMC_B1_09_LPUART4_DCD_B

IOMUXC_GPIO_EMC_B1_09_NETC_PINMUX_ETH3_RXD00

IOMUXC_GPIO_EMC_B1_09_GPIO2_IO09

IOMUXC_GPIO_EMC_B1_09_KPP_ROW05

IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09

IOMUXC_GPIO_EMC_B1_09_NETC_PINMUX_ETH4_RXD00

IOMUXC_GPIO_EMC_B1_09_ECAT_RX_DATA0_0

IOMUXC_GPIO_EMC_B1_09_AHB_SRAMC_ADDR00

IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01

IOMUXC_GPIO_EMC_B1_10_FLEXPWM3_PWMB03

IOMUXC_GPIO_EMC_B1_10_SINC3_EMBIT03

IOMUXC_GPIO_EMC_B1_10_LPUART4_RI_B

IOMUXC_GPIO_EMC_B1_10_NETC_PINMUX_ETH3_RXD01

IOMUXC_GPIO_EMC_B1_10_GPIO2_IO10

IOMUXC_GPIO_EMC_B1_10_KPP_COL05

IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10

IOMUXC_GPIO_EMC_B1_10_NETC_PINMUX_ETH4_RXD01

IOMUXC_GPIO_EMC_B1_10_ECAT_RX_DATA1_0

IOMUXC_GPIO_EMC_B1_10_AHB_SRAMC_ADDR01

IOMUXC_GPIO_EMC_B1_11_ECAT_RX_DV_0

IOMUXC_GPIO_EMC_B1_11_AHB_SRAMC_ADDR02

IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02

IOMUXC_GPIO_EMC_B1_11_FLEXPWM3_PWMA03

IOMUXC_GPIO_EMC_B1_11_SINC_FILTER_GLUE3_BREAK

IOMUXC_GPIO_EMC_B1_11_LPUART4_DTR_B

IOMUXC_GPIO_EMC_B1_11_NETC_PINMUX_ETH3_RX_DV

IOMUXC_GPIO_EMC_B1_11_GPIO2_IO11

IOMUXC_GPIO_EMC_B1_11_KPP_ROW04

IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11

IOMUXC_GPIO_EMC_B1_11_NETC_PINMUX_ETH4_RX_DV

IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03

IOMUXC_GPIO_EMC_B1_12_FLEXPWM4_PWMA00

IOMUXC_GPIO_EMC_B1_12_LPUART4_TX

IOMUXC_GPIO_EMC_B1_12_NETC_PINMUX_ETH3_RX_ER

IOMUXC_GPIO_EMC_B1_12_GPIO2_IO12

IOMUXC_GPIO_EMC_B1_12_KPP_COL04

IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12

IOMUXC_GPIO_EMC_B1_12_NETC_PINMUX_ETH4_RX_ER

IOMUXC_GPIO_EMC_B1_12_ECAT_PT0_RX_ER

IOMUXC_GPIO_EMC_B1_12_AHB_SRAMC_ADDR03

IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04

IOMUXC_GPIO_EMC_B1_13_FLEXPWM4_PWMB00

IOMUXC_GPIO_EMC_B1_13_LPUART4_RX

IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH2_RX_DV

IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH3_TX_ER

IOMUXC_GPIO_EMC_B1_13_GPIO2_IO13

IOMUXC_GPIO_EMC_B1_13_KPP_COL01

IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13

IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH4_TX_ER

IOMUXC_GPIO_EMC_B1_13_QTIMER1_TIMER1

IOMUXC_GPIO_EMC_B1_13_AHB_SRAMC_ADDR04

IOMUXC_GPIO_EMC_B1_14_LPUART4_CTS_B

IOMUXC_GPIO_EMC_B1_14_AHB_SRAMC_ADDR05

IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05

IOMUXC_GPIO_EMC_B1_14_FLEXPWM4_PWMA01

IOMUXC_GPIO_EMC_B1_14_LPUART5_TX

IOMUXC_GPIO_EMC_B1_14_NETC_PINMUX_ETH2_TX_EN

IOMUXC_GPIO_EMC_B1_14_NETC_ETH3_CRS

IOMUXC_GPIO_EMC_B1_14_GPIO2_IO14

IOMUXC_GPIO_EMC_B1_14_KPP_ROW00

IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14

IOMUXC_GPIO_EMC_B1_14_NETC_ETH4_CRS

IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06

IOMUXC_GPIO_EMC_B1_15_FLEXPWM4_PWMB01

IOMUXC_GPIO_EMC_B1_15_LPUART5_RX

IOMUXC_GPIO_EMC_B1_15_NETC_PINMUX_ETH2_TX_CLK

IOMUXC_GPIO_EMC_B1_15_NETC_ETH3_COL

IOMUXC_GPIO_EMC_B1_15_GPIO2_IO15

IOMUXC_GPIO_EMC_B1_15_KPP_COL00

IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15

IOMUXC_GPIO_EMC_B1_15_NETC_ETH4_COL

IOMUXC_GPIO_EMC_B1_15_LPUART4_RTS_B

IOMUXC_GPIO_EMC_B1_15_AHB_SRAMC_ADDR06

IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07

IOMUXC_GPIO_EMC_B1_16_FLEXPWM4_PWMB02

IOMUXC_GPIO_EMC_B1_16_LPUART9_TX

IOMUXC_GPIO_EMC_B1_16_NETC_PINMUX_ETH2_RXD00

IOMUXC_GPIO_EMC_B1_16_NETC_ETH3_SLV_MDC

IOMUXC_GPIO_EMC_B1_16_GPIO2_IO16

IOMUXC_GPIO_EMC_B1_16_NETC_ETH4_SLV_MDC

IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16

IOMUXC_GPIO_EMC_B1_16_NETC_ETH2_SLV_MDC

IOMUXC_GPIO_EMC_B1_16_LPSPI6_PCS2

IOMUXC_GPIO_EMC_B1_16_AHB_SRAMC_ADDR07

IOMUXC_GPIO_EMC_B1_17_LPSPI6_PCS1

IOMUXC_GPIO_EMC_B1_17_AHB_SRAMC_ADDR08

IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08

IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWMA02

IOMUXC_GPIO_EMC_B1_17_LPUART9_RX

IOMUXC_GPIO_EMC_B1_17_NETC_PINMUX_ETH2_RXD01

IOMUXC_GPIO_EMC_B1_17_NETC_ETH3_SLV_MDIO

IOMUXC_GPIO_EMC_B1_17_GPIO2_IO17

IOMUXC_GPIO_EMC_B1_17_NETC_ETH4_SLV_MDIO

IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17

IOMUXC_GPIO_EMC_B1_17_NETC_ETH2_SLV_MDIO

IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09

IOMUXC_GPIO_EMC_B1_18_FLEXPWM2_PWMA00

IOMUXC_GPIO_EMC_B1_18_QTIMER1_TIMER0

IOMUXC_GPIO_EMC_B1_18_LPSPI6_SCK

IOMUXC_GPIO_EMC_B1_18_NETC_ETH2_CRS

IOMUXC_GPIO_EMC_B1_18_GPIO2_IO18

IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18

IOMUXC_GPIO_EMC_B1_18_NETC_EMDC

IOMUXC_GPIO_EMC_B1_18_AHB_SRAMC_ADDR09

IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11

IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWMB00

IOMUXC_GPIO_EMC_B1_19_QTIMER2_TIMER0

IOMUXC_GPIO_EMC_B1_19_LPSPI6_SDI

IOMUXC_GPIO_EMC_B1_19_NETC_ETH2_COL

IOMUXC_GPIO_EMC_B1_19_GPIO2_IO19

IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19

IOMUXC_GPIO_EMC_B1_19_NETC_EMDIO

IOMUXC_GPIO_EMC_B1_19_AHB_SRAMC_ADDR11

IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12

IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWMA01

IOMUXC_GPIO_EMC_B1_20_QTIMER3_TIMER0

IOMUXC_GPIO_EMC_B1_20_LPSPI6_SDO

IOMUXC_GPIO_EMC_B1_20_NETC_PINMUX_ETH2_TX_ER

IOMUXC_GPIO_EMC_B1_20_GPIO2_IO20

IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20

IOMUXC_GPIO_EMC_B1_20_AHB_SRAMC_ADDR12

IOMUXC_GPIO_EMC_B1_21_FLEXSPI2_BUS2BIT_B_DQS

IOMUXC_GPIO_EMC_B1_21_AHB_SRAMC_ADDR13

IOMUXC_GPIO_EMC_B1_21_SEMC_BA0

IOMUXC_GPIO_EMC_B1_21_FLEXPWM2_PWMB01

IOMUXC_GPIO_EMC_B1_21_QTIMER4_TIMER0

IOMUXC_GPIO_EMC_B1_21_LPSPI6_PCS0

IOMUXC_GPIO_EMC_B1_21_NETC_PINMUX_ETH2_RX_CLK

IOMUXC_GPIO_EMC_B1_21_GPIO2_IO21

IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21

IOMUXC_GPIO_EMC_B1_21_LPUART4_CTS_B

IOMUXC_GPIO_EMC_B1_22_FLEXSPI2_BUS2BIT_B_DATA03

IOMUXC_GPIO_EMC_B1_22_AHB_SRAMC_ADDR14

IOMUXC_GPIO_EMC_B1_22_SEMC_BA1

IOMUXC_GPIO_EMC_B1_22_FLEXPWM2_PWMB02

IOMUXC_GPIO_EMC_B1_22_QTIMER5_TIMER0

IOMUXC_GPIO_EMC_B1_22_LPSPI4_SCK

IOMUXC_GPIO_EMC_B1_22_NETC_PINMUX_ETH2_RXD02

IOMUXC_GPIO_EMC_B1_22_GPIO2_IO22

IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22

IOMUXC_GPIO_EMC_B1_22_LPUART4_RTS_B

IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10

IOMUXC_GPIO_EMC_B1_23_FLEXPWM2_PWMA02

IOMUXC_GPIO_EMC_B1_23_QTIMER6_TIMER0

IOMUXC_GPIO_EMC_B1_23_LPSPI4_SDI

IOMUXC_GPIO_EMC_B1_23_NETC_PINMUX_ETH2_RXD03

IOMUXC_GPIO_EMC_B1_23_GPIO2_IO23

IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23

IOMUXC_GPIO_EMC_B1_23_FLEXSPI2_BUS2BIT_B_DATA02

IOMUXC_GPIO_EMC_B1_23_AHB_SRAMC_ADDR10

IOMUXC_GPIO_EMC_B1_24_FLEXSPI2_BUS2BIT_B_DATA01

IOMUXC_GPIO_EMC_B1_24_AHB_SRAMC_ADDR15

IOMUXC_GPIO_EMC_B1_24_SEMC_CAS

IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWMA00

IOMUXC_GPIO_EMC_B1_24_QTIMER7_TIMER0

IOMUXC_GPIO_EMC_B1_24_LPSPI4_SDO

IOMUXC_GPIO_EMC_B1_24_NETC_PINMUX_ETH2_TXD03

IOMUXC_GPIO_EMC_B1_24_GPIO2_IO24

IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24

IOMUXC_GPIO_EMC_B1_24_NETC_ETH3_SLV_MDC

IOMUXC_GPIO_EMC_B1_25_FLEXSPI2_BUS2BIT_B_DATA00

IOMUXC_GPIO_EMC_B1_25_AHB_SRAMC_ADDR16

IOMUXC_GPIO_EMC_B1_25_SEMC_RAS

IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWMB00

IOMUXC_GPIO_EMC_B1_25_QTIMER8_TIMER0

IOMUXC_GPIO_EMC_B1_25_LPSPI4_PCS0

IOMUXC_GPIO_EMC_B1_25_NETC_PINMUX_ETH2_TXD02

IOMUXC_GPIO_EMC_B1_25_GPIO2_IO25

IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25

IOMUXC_GPIO_EMC_B1_25_NETC_ETH3_SLV_MDIO

IOMUXC_GPIO_EMC_B1_26_SEMC_CLK

IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWMA01

IOMUXC_GPIO_EMC_B1_26_XBAR1_XBAR_INOUT10

IOMUXC_GPIO_EMC_B1_26_FLEXSPI2_BUS2BIT_A_SS1_B

IOMUXC_GPIO_EMC_B1_26_NETC_PINMUX_ETH2_TXD01

IOMUXC_GPIO_EMC_B1_26_GPIO2_IO26

IOMUXC_GPIO_EMC_B1_26_ECAT_TX_DATA1_1

IOMUXC_GPIO_EMC_B1_26_LPSPI6_SCK

IOMUXC_GPIO_EMC_B1_26_AHB_SRAMC_WE

IOMUXC_GPIO_EMC_B1_27_LPSPI6_SDI

IOMUXC_GPIO_EMC_B1_27_AHB_SRAMC_OEB

IOMUXC_GPIO_EMC_B1_27_SEMC_CKE

IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWMB01

IOMUXC_GPIO_EMC_B1_27_XBAR1_XBAR_INOUT11

IOMUXC_GPIO_EMC_B1_27_FLEXSPI2_BUS2BIT_B_SS1_B

IOMUXC_GPIO_EMC_B1_27_NETC_PINMUX_ETH2_TXD00

IOMUXC_GPIO_EMC_B1_27_GPIO2_IO27

IOMUXC_GPIO_EMC_B1_27_ECAT_TX_DATA0_1

IOMUXC_GPIO_EMC_B1_27_LPUART6_RI_B

IOMUXC_GPIO_EMC_B1_28_LPSPI6_SDO

IOMUXC_GPIO_EMC_B1_28_AHB_SRAMC_ADV

IOMUXC_GPIO_EMC_B1_28_SEMC_WE

IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWMB02

IOMUXC_GPIO_EMC_B1_28_XBAR1_XBAR_INOUT12

IOMUXC_GPIO_EMC_B1_28_FLEXSPI2_BUS2BIT_B_SS0_B

IOMUXC_GPIO_EMC_B1_28_NETC_PINMUX_ETH2_TX_EN

IOMUXC_GPIO_EMC_B1_28_GPIO2_IO28

IOMUXC_GPIO_EMC_B1_28_ECAT_TX_EN_1

IOMUXC_GPIO_EMC_B1_28_LPUART6_DTR_B

IOMUXC_GPIO_EMC_B1_29_SEMC_CS0

IOMUXC_GPIO_EMC_B1_29_FLEXPWM1_PWMA02

IOMUXC_GPIO_EMC_B1_29_XBAR1_XBAR_INOUT13

IOMUXC_GPIO_EMC_B1_29_FLEXSPI2_BUS2BIT_B_DQS

IOMUXC_GPIO_EMC_B1_29_NETC_PINMUX_ETH2_TX_CLK

IOMUXC_GPIO_EMC_B1_29_GPIO2_IO29

IOMUXC_GPIO_EMC_B1_29_ECAT_TX_CLK_1

IOMUXC_GPIO_EMC_B1_29_LPUART6_DCD_B

IOMUXC_GPIO_EMC_B1_29_LPSPI6_PCS0

IOMUXC_GPIO_EMC_B1_29_AHB_SRAMC_CS0

IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08

IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWMA00

IOMUXC_GPIO_EMC_B1_30_XBAR1_XBAR_INOUT14

IOMUXC_GPIO_EMC_B1_30_FLEXSPI2_BUS2BIT_B_DATA03

IOMUXC_GPIO_EMC_B1_30_NETC_PINMUX_ETH2_RXD00

IOMUXC_GPIO_EMC_B1_30_GPIO2_IO30

IOMUXC_GPIO_EMC_B1_30_ECAT_RX_DATA0_1

IOMUXC_GPIO_EMC_B1_30_LPUART6_DSR_B

IOMUXC_GPIO_EMC_B1_30_LPSPI6_PCS1

IOMUXC_GPIO_EMC_B1_30_AHB_SRAMC_DATA08

IOMUXC_GPIO_EMC_B1_31_LPSPI6_PCS2

IOMUXC_GPIO_EMC_B1_31_AHB_SRAMC_DATA09

IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09

IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWMB00

IOMUXC_GPIO_EMC_B1_31_LPUART6_TX

IOMUXC_GPIO_EMC_B1_31_FLEXSPI2_BUS2BIT_B_DATA02

IOMUXC_GPIO_EMC_B1_31_NETC_PINMUX_ETH2_RXD01

IOMUXC_GPIO_EMC_B1_31_GPIO2_IO31

IOMUXC_GPIO_EMC_B1_31_ECAT_RX_DATA1_1

IOMUXC_GPIO_EMC_B1_31_LPSPI5_SCK

IOMUXC_GPIO_EMC_B1_32_LPSPI6_PCS3

IOMUXC_GPIO_EMC_B1_32_AHB_SRAMC_DATA10

IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10

IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWMA01

IOMUXC_GPIO_EMC_B1_32_LPUART6_RX

IOMUXC_GPIO_EMC_B1_32_FLEXSPI2_BUS2BIT_B_DATA01

IOMUXC_GPIO_EMC_B1_32_NETC_PINMUX_ETH2_RX_DV

IOMUXC_GPIO_EMC_B1_32_GPIO3_IO00

IOMUXC_GPIO_EMC_B1_32_ECAT_RX_DV_1

IOMUXC_GPIO_EMC_B1_32_LPSPI5_SDO

IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11

IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWMB01

IOMUXC_GPIO_EMC_B1_33_LPUART6_CTS_B

IOMUXC_GPIO_EMC_B1_33_FLEXSPI2_BUS2BIT_B_DATA00

IOMUXC_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_ER

IOMUXC_GPIO_EMC_B1_33_GPIO3_IO01

IOMUXC_GPIO_EMC_B1_33_ECAT_RX_ER_1

IOMUXC_GPIO_EMC_B1_33_LPSPI5_SDI

IOMUXC_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_CLK

IOMUXC_GPIO_EMC_B1_33_AHB_SRAMC_DATA11

IOMUXC_GPIO_EMC_B1_34_LPSPI5_PCS0

IOMUXC_GPIO_EMC_B1_34_AHB_SRAMC_DATA12

IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12

IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWMB02

IOMUXC_GPIO_EMC_B1_34_LPUART6_RTS_B

IOMUXC_GPIO_EMC_B1_34_FLEXSPI2_BUS2BIT_B_SCLK

IOMUXC_GPIO_EMC_B1_34_NETC_PINMUX_ETH2_RXD02

IOMUXC_GPIO_EMC_B1_34_GPIO3_IO02

IOMUXC_GPIO_EMC_B1_34_ECAT_RX_DATA2_1

IOMUXC_GPIO_EMC_B1_34_NETC_PINMUX_ETH0_TXD00

IOMUXC_GPIO_EMC_B1_35_LPSPI5_PCS1

IOMUXC_GPIO_EMC_B1_35_AHB_SRAMC_DATA13

IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13

IOMUXC_GPIO_EMC_B1_35_FLEXPWM3_PWMA02

IOMUXC_GPIO_EMC_B1_35_LPUART5_TX

IOMUXC_GPIO_EMC_B1_35_FLEXSPI2_BUS2BIT_A_DATA00

IOMUXC_GPIO_EMC_B1_35_NETC_PINMUX_ETH2_RXD03

IOMUXC_GPIO_EMC_B1_35_GPIO3_IO03

IOMUXC_GPIO_EMC_B1_35_ECAT_RX_DATA3_1

IOMUXC_GPIO_EMC_B1_35_NETC_PINMUX_ETH0_TXD01

IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14

IOMUXC_GPIO_EMC_B1_36_FLEXPWM1_PWMA00

IOMUXC_GPIO_EMC_B1_36_LPUART5_RX

IOMUXC_GPIO_EMC_B1_36_FLEXSPI2_BUS2BIT_A_DATA01

IOMUXC_GPIO_EMC_B1_36_NETC_PINMUX_ETH2_TXD03

IOMUXC_GPIO_EMC_B1_36_GPIO3_IO04

IOMUXC_GPIO_EMC_B1_36_ECAT_TX_DATA3_1

IOMUXC_GPIO_EMC_B1_36_NETC_PINMUX_ETH0_TX_EN

IOMUXC_GPIO_EMC_B1_36_AHB_SRAMC_DATA14

IOMUXC_GPIO_EMC_B1_37_AHB_SRAMC_DATA15

IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15

IOMUXC_GPIO_EMC_B1_37_FLEXPWM1_PWMB00

IOMUXC_GPIO_EMC_B1_37_LPUART5_CTS_B

IOMUXC_GPIO_EMC_B1_37_FLEXSPI2_BUS2BIT_A_DATA02

IOMUXC_GPIO_EMC_B1_37_NETC_PINMUX_ETH2_TXD02

IOMUXC_GPIO_EMC_B1_37_GPIO3_IO05

IOMUXC_GPIO_EMC_B1_37_ECAT_TX_DATA2_1

IOMUXC_GPIO_EMC_B1_37_NETC_PINMUX_ETH0_TX_CLK

IOMUXC_GPIO_EMC_B1_38_AHB_SRAMC_UBB

IOMUXC_GPIO_EMC_B1_38_SEMC_DM01

IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWMB03

IOMUXC_GPIO_EMC_B1_38_LPUART5_RTS_B

IOMUXC_GPIO_EMC_B1_38_FLEXSPI2_BUS2BIT_A_DATA03

IOMUXC_GPIO_EMC_B1_38_NETC_PINMUX_ETH2_RX_CLK

IOMUXC_GPIO_EMC_B1_38_GPIO3_IO06

IOMUXC_GPIO_EMC_B1_38_ECAT_RX_CLK_1

IOMUXC_GPIO_EMC_B1_38_NETC_PINMUX_ETH0_RXD00

IOMUXC_GPIO_EMC_B1_39_SEMC_DQS

IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWMA03

IOMUXC_GPIO_EMC_B1_39_XBAR1_XBAR_INOUT15

IOMUXC_GPIO_EMC_B1_39_FLEXSPI2_BUS2BIT_A_SS0_B

IOMUXC_GPIO_EMC_B1_39_NETC_PINMUX_ETH2_TX_ER

IOMUXC_GPIO_EMC_B1_39_GPIO3_IO07

IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1

IOMUXC_GPIO_EMC_B1_39_NETC_PINMUX_ETH0_RXD01

IOMUXC_GPIO_EMC_B1_39_AHB_SRAMC_CS1

IOMUXC_GPIO_EMC_B1_40_SEMC_RDY

IOMUXC_GPIO_EMC_B1_40_NETC_EMDC

IOMUXC_GPIO_EMC_B1_40_NETC_ETH2_SLV_MDC

IOMUXC_GPIO_EMC_B1_40_FLEXSPI2_BUS2BIT_A_DQS

IOMUXC_GPIO_EMC_B1_40_NETC_ETH2_CRS

IOMUXC_GPIO_EMC_B1_40_GPIO3_IO08

IOMUXC_GPIO_EMC_B1_40_QTIMER3_TIMER1

IOMUXC_GPIO_EMC_B1_40_NETC_PINMUX_ETH0_RX_DV

IOMUXC_GPIO_EMC_B1_40_AHB_SRAMC_CS2

IOMUXC_GPIO_EMC_B1_41_AHB_SRAMC_CS3

IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00

IOMUXC_GPIO_EMC_B1_41_NETC_EMDIO

IOMUXC_GPIO_EMC_B1_41_NETC_ETH2_SLV_MDIO

IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_BUS2BIT_A_SCLK

IOMUXC_GPIO_EMC_B1_41_NETC_ETH2_COL

IOMUXC_GPIO_EMC_B1_41_GPIO3_IO09

IOMUXC_GPIO_EMC_B1_41_QTIMER4_TIMER1

IOMUXC_GPIO_EMC_B1_41_NETC_PINMUX_ETH0_RX_ER

IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16

IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_EMC_B2_00_QTIMER5_TIMER1

IOMUXC_GPIO_EMC_B2_00_NETC_EMDC

IOMUXC_GPIO_EMC_B2_00_NETC_PINMUX_ETH0_RX_CLK

IOMUXC_GPIO_EMC_B2_00_GPIO3_IO10

IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20

IOMUXC_GPIO_EMC_B2_00_LPSPI5_SCK

IOMUXC_GPIO_EMC_B2_00_LPI2C3_SCL

IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWMA00

IOMUXC_GPIO_EMC_B2_00_ECAT_RX_CLK_0

IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17

IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B

IOMUXC_GPIO_EMC_B2_01_QTIMER6_TIMER1

IOMUXC_GPIO_EMC_B2_01_NETC_EMDIO

IOMUXC_GPIO_EMC_B2_01_NETC_PINMUX_ETH0_RXD02

IOMUXC_GPIO_EMC_B2_01_GPIO3_IO11

IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21

IOMUXC_GPIO_EMC_B2_01_LPSPI5_PCS0

IOMUXC_GPIO_EMC_B2_01_LPI2C3_SDA

IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWMB00

IOMUXC_GPIO_EMC_B2_01_ECAT_RX_DATA2_0

IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18

IOMUXC_GPIO_EMC_B2_02_USDHC2_WP

IOMUXC_GPIO_EMC_B2_02_QTIMER7_TIMER1

IOMUXC_GPIO_EMC_B2_02_NETC_PINMUX_ETH0_RXD03

IOMUXC_GPIO_EMC_B2_02_GPIO3_IO12

IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22

IOMUXC_GPIO_EMC_B2_02_LPSPI5_SDO

IOMUXC_GPIO_EMC_B2_02_CCM_CLKO1

IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWMA01

IOMUXC_GPIO_EMC_B2_02_ECAT_RX_DATA3_0

IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19

IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT

IOMUXC_GPIO_EMC_B2_03_QTIMER8_TIMER1

IOMUXC_GPIO_EMC_B2_03_NETC_PINMUX_ETH0_TXD02

IOMUXC_GPIO_EMC_B2_03_GPIO3_IO13

IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23

IOMUXC_GPIO_EMC_B2_03_LPSPI5_SDI

IOMUXC_GPIO_EMC_B2_03_NETC_ETH3_CRS

IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWMB01

IOMUXC_GPIO_EMC_B2_03_ECAT_TX_DATA2_0

IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20

IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B

IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK

IOMUXC_GPIO_EMC_B2_04_NETC_PINMUX_ETH0_TXD03

IOMUXC_GPIO_EMC_B2_04_GPIO3_IO14

IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24

IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK

IOMUXC_GPIO_EMC_B2_04_NETC_ETH3_COL

IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWMB02

IOMUXC_GPIO_EMC_B2_04_ECAT_TX_DATA3_0

IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21

IOMUXC_GPIO_EMC_B2_05_NETC_ETH4_SLV_MDC

IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC

IOMUXC_GPIO_EMC_B2_05_NETC_PINMUX_ETH0_TXD00

IOMUXC_GPIO_EMC_B2_05_NETC_ETH4_CRS

IOMUXC_GPIO_EMC_B2_05_GPIO3_IO15

IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25

IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0

IOMUXC_GPIO_EMC_B2_05_NETC_PINMUX_ETH3_TXD00

IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWMA02

IOMUXC_GPIO_EMC_B2_05_ECAT_TX_DATA0_0

IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22

IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWMB03

IOMUXC_GPIO_EMC_B2_06_NETC_ETH4_SLV_MDIO

IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK

IOMUXC_GPIO_EMC_B2_06_ECAT_TX_DATA1_0

IOMUXC_GPIO_EMC_B2_06_NETC_PINMUX_ETH0_TXD01

IOMUXC_GPIO_EMC_B2_06_NETC_ETH4_COL

IOMUXC_GPIO_EMC_B2_06_GPIO3_IO16

IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26

IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO

IOMUXC_GPIO_EMC_B2_06_NETC_PINMUX_ETH3_TXD01

IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23

IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH4_TX_ER

IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA

IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH0_TX_EN

IOMUXC_GPIO_EMC_B2_07_GPIO3_IO17

IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27

IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI

IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH3_TX_EN

IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWMA03

IOMUXC_GPIO_EMC_B2_07_ECAT_TX_EN_0

IOMUXC_GPIO_EMC_B2_08_SEMC_DM02

IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH4_RX_CLK

IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA

IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH0_TX_CLK

IOMUXC_GPIO_EMC_B2_08_GPIO3_IO18

IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28

IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS3

IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH3_TX_CLK

IOMUXC_GPIO_EMC_B2_08_CCM_CLKO2

IOMUXC_GPIO_EMC_B2_08_ECAT_TX_CLK_0

IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0

IOMUXC_GPIO_EMC_B2_09_ECAT_RX_DATA0_0

IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24

IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH4_RXD03

IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK

IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH0_RXD00

IOMUXC_GPIO_EMC_B2_09_GPIO3_IO19

IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29

IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2

IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH3_RXD00

IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1

IOMUXC_GPIO_EMC_B2_10_ECAT_RX_DATA1_0

IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25

IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH4_RXD02

IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC

IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH0_RXD01

IOMUXC_GPIO_EMC_B2_10_GPIO3_IO20

IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30

IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS1

IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH3_RXD01

IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26

IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH4_TXD03

IOMUXC_GPIO_EMC_B2_11_SPDIF_OUT

IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH0_RX_DV

IOMUXC_GPIO_EMC_B2_11_LPSPI5_PCS3

IOMUXC_GPIO_EMC_B2_11_GPIO3_IO21

IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31

IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC

IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH3_RX_DV

IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2

IOMUXC_GPIO_EMC_B2_11_ECAT_RX_DV_0

IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27

IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH4_TXD02

IOMUXC_GPIO_EMC_B2_12_SPDIF_IN

IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH0_RX_ER

IOMUXC_GPIO_EMC_B2_12_LPSPI5_PCS2

IOMUXC_GPIO_EMC_B2_12_GPIO3_IO22

IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32

IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK

IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH3_RX_ER

IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3

IOMUXC_GPIO_EMC_B2_12_ECAT_PT0_RX_ER

IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0

IOMUXC_GPIO_EMC_B2_13_ECAT_TX_DATA0_1

IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28

IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH4_TXD00

IOMUXC_GPIO_EMC_B2_13_LPUART11_TX

IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH0_TXD03

IOMUXC_GPIO_EMC_B2_13_LPSPI5_PCS1

IOMUXC_GPIO_EMC_B2_13_GPIO3_IO23

IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33

IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA

IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH3_TXD03

IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29

IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH4_TXD01

IOMUXC_GPIO_EMC_B2_14_LPUART11_RX

IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH0_TXD02

IOMUXC_GPIO_EMC_B2_14_LPUART5_DSR_B

IOMUXC_GPIO_EMC_B2_14_GPIO3_IO24

IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34

IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA

IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH3_TXD02

IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1

IOMUXC_GPIO_EMC_B2_14_ECAT_TX_DATA1_1

IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30

IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH4_TX_EN

IOMUXC_GPIO_EMC_B2_15_LPUART11_CTS_B

IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH0_RX_CLK

IOMUXC_GPIO_EMC_B2_15_LPUART5_DCD_B

IOMUXC_GPIO_EMC_B2_15_GPIO3_IO25

IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35

IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK

IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH3_RX_CLK

IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2

IOMUXC_GPIO_EMC_B2_15_ECAT_TX_EN_1

IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3

IOMUXC_GPIO_EMC_B2_16_ECAT_TX_CLK_1

IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31

IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH4_TX_CLK

IOMUXC_GPIO_EMC_B2_16_LPUART11_RTS_B

IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH0_RXD02

IOMUXC_GPIO_EMC_B2_16_LPUART5_DTR_B

IOMUXC_GPIO_EMC_B2_16_GPIO3_IO26

IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14

IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC

IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH3_RXD02

IOMUXC_GPIO_EMC_B2_17_SEMC_DM03

IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH4_RXD00

IOMUXC_GPIO_EMC_B2_17_LPUART5_TX

IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH0_RXD03

IOMUXC_GPIO_EMC_B2_17_GPIO3_IO27

IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15

IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK

IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH3_RXD03

IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0

IOMUXC_GPIO_EMC_B2_17_ECAT_RX_DATA0_1

IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4

IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH4_RXD01

IOMUXC_GPIO_EMC_B2_18_LPUART5_RX

IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH0_TX_ER

IOMUXC_GPIO_EMC_B2_18_GPIO3_IO28

IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16

IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B

IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH3_TX_ER

IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1

IOMUXC_GPIO_EMC_B2_18_ECAT_RX_DATA1_1

IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2

IOMUXC_GPIO_EMC_B2_19_ECAT_RX_DV_1

IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00

IOMUXC_GPIO_EMC_B2_19_NETC_PINMUX_ETH4_RX_DV

IOMUXC_GPIO_EMC_B2_19_LPUART5_CTS_B

IOMUXC_GPIO_EMC_B2_19_NETC_ETH0_CRS

IOMUXC_GPIO_EMC_B2_19_NETC_EMDC

IOMUXC_GPIO_EMC_B2_19_GPIO3_IO29

IOMUXC_GPIO_EMC_B2_19_XBAR1_XBAR_INOUT36

IOMUXC_GPIO_EMC_B2_19_LPI2C3_SCL

IOMUXC_GPIO_EMC_B2_19_NETC_ETH3_SLV_MDC

IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3

IOMUXC_GPIO_EMC_B2_20_ECAT_RX_ER_1

IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01

IOMUXC_GPIO_EMC_B2_20_NETC_PINMUX_ETH4_RX_ER

IOMUXC_GPIO_EMC_B2_20_LPUART5_RTS_B

IOMUXC_GPIO_EMC_B2_20_NETC_ETH0_COL

IOMUXC_GPIO_EMC_B2_20_NETC_EMDIO

IOMUXC_GPIO_EMC_B2_20_GPIO3_IO30

IOMUXC_GPIO_EMC_B2_20_XBAR1_XBAR_INOUT37

IOMUXC_GPIO_EMC_B2_20_LPI2C3_SDA

IOMUXC_GPIO_EMC_B2_20_NETC_ETH3_SLV_MDIO

IOMUXC_GPIO_AD_00_CAN2_TX

IOMUXC_GPIO_AD_00_MIC_CLK

IOMUXC_GPIO_AD_00_GPT2_CAPTURE1

IOMUXC_GPIO_AD_00_FLEXPWM1_PWMA00

IOMUXC_GPIO_AD_00_GPIO4_IO00

IOMUXC_GPIO_AD_00_SINC1_MOD_CLK0

IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00

IOMUXC_GPIO_AD_00_QTIMER4_TIMER0

IOMUXC_GPIO_AD_01_CAN2_RX

IOMUXC_GPIO_AD_01_MIC_BITSTREAM00

IOMUXC_GPIO_AD_01_GPT2_CAPTURE2

IOMUXC_GPIO_AD_01_FLEXPWM1_PWMB00

IOMUXC_GPIO_AD_01_GPIO4_IO01

IOMUXC_GPIO_AD_01_SINC1_MOD_CLK1

IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01

IOMUXC_GPIO_AD_01_QTIMER4_TIMER1

IOMUXC_GPIO_AD_02_MIC_BITSTREAM01

IOMUXC_GPIO_AD_02_GPT2_COMPARE1

IOMUXC_GPIO_AD_02_FLEXPWM1_PWMA01

IOMUXC_GPIO_AD_02_GPIO4_IO02

IOMUXC_GPIO_AD_02_SINC1_MOD_CLK2

IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02

IOMUXC_GPIO_AD_02_QTIMER4_TIMER2

IOMUXC_GPIO_AD_03_MIC_BITSTREAM02

IOMUXC_GPIO_AD_03_GPT2_COMPARE2

IOMUXC_GPIO_AD_03_FLEXPWM1_PWMB01

IOMUXC_GPIO_AD_03_GPIO4_IO03

IOMUXC_GPIO_AD_03_SINC1_EMCLK00

IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03

IOMUXC_GPIO_AD_03_QTIMER4_TIMER3

IOMUXC_GPIO_AD_04_MIC_BITSTREAM03

IOMUXC_GPIO_AD_04_GPT2_COMPARE3

IOMUXC_GPIO_AD_04_FLEXPWM1_PWMB02

IOMUXC_GPIO_AD_04_GPIO4_IO04

IOMUXC_GPIO_AD_04_SINC1_EMBIT00

IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04

IOMUXC_GPIO_AD_04_QTIMER5_TIMER0

IOMUXC_GPIO_AD_05_GPT2_CLK

IOMUXC_GPIO_AD_05_FLEXPWM1_PWMA02

IOMUXC_GPIO_AD_05_GPIO4_IO05

IOMUXC_GPIO_AD_05_SINC1_EMCLK01

IOMUXC_GPIO_AD_05_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05

IOMUXC_GPIO_AD_05_QTIMER5_TIMER1

IOMUXC_GPIO_AD_06_USB_OTG2_OC

IOMUXC_GPIO_AD_06_CAN3_TX

IOMUXC_GPIO_AD_06_FLEXPWM1_PWMX00

IOMUXC_GPIO_AD_06_GPIO4_IO06

IOMUXC_GPIO_AD_06_SINC1_EMBIT01

IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06

IOMUXC_GPIO_AD_06_QTIMER5_TIMER2

IOMUXC_GPIO_AD_07_USB_OTG2_PWR

IOMUXC_GPIO_AD_07_CAN3_RX

IOMUXC_GPIO_AD_07_FLEXPWM1_PWMX01

IOMUXC_GPIO_AD_07_GPIO4_IO07

IOMUXC_GPIO_AD_07_SINC1_EMCLK02

IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07

IOMUXC_GPIO_AD_07_QTIMER5_TIMER3

IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID

IOMUXC_GPIO_AD_08_LPI2C5_SCL

IOMUXC_GPIO_AD_08_FLEXPWM1_PWMX02

IOMUXC_GPIO_AD_08_GPIO4_IO08

IOMUXC_GPIO_AD_08_SINC1_EMBIT02

IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08

IOMUXC_GPIO_AD_08_QTIMER6_TIMER0

IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID

IOMUXC_GPIO_AD_09_LPI2C5_SDA

IOMUXC_GPIO_AD_09_FLEXPWM1_PWMX03

IOMUXC_GPIO_AD_09_GPIO4_IO09

IOMUXC_GPIO_AD_09_SINC1_EMCLK03

IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09

IOMUXC_GPIO_AD_09_QTIMER6_TIMER1

IOMUXC_GPIO_AD_10_USB_OTG1_PWR

IOMUXC_GPIO_AD_10_FLEXPWM2_PWMX00

IOMUXC_GPIO_AD_10_GPIO4_IO10

IOMUXC_GPIO_AD_10_SINC1_EMBIT03

IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10

IOMUXC_GPIO_AD_10_QTIMER6_TIMER2

IOMUXC_GPIO_AD_11_USB_OTG1_OC

IOMUXC_GPIO_AD_11_FLEXPWM2_PWMX01

IOMUXC_GPIO_AD_11_GPIO4_IO11

IOMUXC_GPIO_AD_11_SINC_FILTER_GLUE1_BREAK

IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11

IOMUXC_GPIO_AD_11_QTIMER6_TIMER3

IOMUXC_GPIO_AD_12_SPDIF_LOCK

IOMUXC_GPIO_AD_12_LPI2C5_SCLS

IOMUXC_GPIO_AD_12_GPT1_CAPTURE1

IOMUXC_GPIO_AD_12_KPP_ROW07

IOMUXC_GPIO_AD_12_FLEXPWM2_PWMX02

IOMUXC_GPIO_AD_12_GPIO4_IO12

IOMUXC_GPIO_AD_12_XBAR1_XBAR_INOUT18

IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B

IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12

IOMUXC_GPIO_AD_13_SPDIF_SR_CLK

IOMUXC_GPIO_AD_13_LPI2C5_SDAS

IOMUXC_GPIO_AD_13_GPT1_CAPTURE2

IOMUXC_GPIO_AD_13_KPP_COL07

IOMUXC_GPIO_AD_13_FLEXPWM2_PWMX03

IOMUXC_GPIO_AD_13_GPIO4_IO13

IOMUXC_GPIO_AD_13_LPUART3_TX

IOMUXC_GPIO_AD_13_USDHC2_CD_B

IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13

IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK

IOMUXC_GPIO_AD_14_LPI2C5_HREQ

IOMUXC_GPIO_AD_14_GPT1_COMPARE1

IOMUXC_GPIO_AD_14_KPP_ROW06

IOMUXC_GPIO_AD_14_FLEXPWM3_PWMX00

IOMUXC_GPIO_AD_14_GPIO4_IO14

IOMUXC_GPIO_AD_14_LPUART3_RX

IOMUXC_GPIO_AD_14_USDHC2_WP

IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14

IOMUXC_GPIO_AD_15_ECAT_CLK_ECAT_CLK25

IOMUXC_GPIO_AD_15_SPDIF_IN

IOMUXC_GPIO_AD_15_LPUART10_TX

IOMUXC_GPIO_AD_15_GPT1_COMPARE2

IOMUXC_GPIO_AD_15_KPP_COL06

IOMUXC_GPIO_AD_15_FLEXPWM3_PWMX01

IOMUXC_GPIO_AD_15_GPIO4_IO15

IOMUXC_GPIO_AD_15_LPUART3_CTS_B

IOMUXC_GPIO_AD_15_LPSPI3_PCS1

IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15

IOMUXC_GPIO_AD_15_CAN1_TX

IOMUXC_GPIO_AD_16_SPDIF_OUT

IOMUXC_GPIO_AD_16_LPUART10_RX

IOMUXC_GPIO_AD_16_GPT1_COMPARE3

IOMUXC_GPIO_AD_16_KPP_ROW05

IOMUXC_GPIO_AD_16_FLEXPWM3_PWMX02

IOMUXC_GPIO_AD_16_GPIO4_IO16

IOMUXC_GPIO_AD_16_LPUART3_RTS_B

IOMUXC_GPIO_AD_16_LPSPI3_SCK

IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16

IOMUXC_GPIO_AD_16_CAN1_RX

IOMUXC_GPIO_AD_16_ECAT_LINK_0

IOMUXC_GPIO_AD_17_SAI4_MCLK

IOMUXC_GPIO_AD_17_ACMP1_CMPO

IOMUXC_GPIO_AD_17_GPT1_CLK

IOMUXC_GPIO_AD_17_KPP_COL05

IOMUXC_GPIO_AD_17_FLEXPWM3_PWMX03

IOMUXC_GPIO_AD_17_GPIO4_IO17

IOMUXC_GPIO_AD_17_I3C2_PUR

IOMUXC_GPIO_AD_17_LPSPI3_PCS0

IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17

IOMUXC_GPIO_AD_17_LPI2C3_HREQ

IOMUXC_GPIO_AD_17_ECAT_LINK_1

IOMUXC_GPIO_AD_18_ECAT_PROM_CLK

IOMUXC_GPIO_AD_18_SAI4_RX_SYNC

IOMUXC_GPIO_AD_18_ACMP2_CMPO

IOMUXC_GPIO_AD_18_LPUART5_RI_B

IOMUXC_GPIO_AD_18_KPP_ROW04

IOMUXC_GPIO_AD_18_FLEXPWM4_PWMX00

IOMUXC_GPIO_AD_18_GPIO4_IO18

IOMUXC_GPIO_AD_18_I3C2_SCL

IOMUXC_GPIO_AD_18_LPSPI3_SDO

IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18

IOMUXC_GPIO_AD_18_LPI2C3_SCL

IOMUXC_GPIO_AD_19_SAI4_RX_BCLK

IOMUXC_GPIO_AD_19_ACMP3_CMPO

IOMUXC_GPIO_AD_19_XBAR1_XBAR_INOUT19

IOMUXC_GPIO_AD_19_KPP_COL04

IOMUXC_GPIO_AD_19_FLEXPWM4_PWMX01

IOMUXC_GPIO_AD_19_GPIO4_IO19

IOMUXC_GPIO_AD_19_I3C2_SDA

IOMUXC_GPIO_AD_19_LPSPI3_SDI

IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19

IOMUXC_GPIO_AD_19_LPI2C3_SDA

IOMUXC_GPIO_AD_19_ECAT_PROM_DATA

IOMUXC_GPIO_AD_20_SAI4_RX_DATA00

IOMUXC_GPIO_AD_20_ACMP4_CMPO

IOMUXC_GPIO_AD_20_LPIT2_TRIGGER00

IOMUXC_GPIO_AD_20_SINC1_EMCLK00

IOMUXC_GPIO_AD_20_FLEXPWM4_PWMX02

IOMUXC_GPIO_AD_20_GPIO4_IO20

IOMUXC_GPIO_AD_20_NETC_TMR_TRIG1

IOMUXC_GPIO_AD_20_NETC_1588_CLK

IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20

IOMUXC_GPIO_AD_21_SAI4_TX_DATA00

IOMUXC_GPIO_AD_21_LPIT2_TRIGGER01

IOMUXC_GPIO_AD_21_SINC1_EMBIT00

IOMUXC_GPIO_AD_21_FLEXPWM4_PWMX03

IOMUXC_GPIO_AD_21_GPIO4_IO21

IOMUXC_GPIO_AD_21_NETC_TMR_TRIG2

IOMUXC_GPIO_AD_21_NETC_TMR_GCLK

IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21

IOMUXC_GPIO_AD_21_ECAT_LED_RUN

IOMUXC_GPIO_AD_22_ECAT_LED_ERR

IOMUXC_GPIO_AD_22_SAI4_TX_BCLK

IOMUXC_GPIO_AD_22_LPIT2_TRIGGER02

IOMUXC_GPIO_AD_22_SINC1_EMCLK01

IOMUXC_GPIO_AD_22_GPIO4_IO22

IOMUXC_GPIO_AD_22_NETC_TMR_ALARM1

IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22

IOMUXC_GPIO_AD_23_SAI4_TX_SYNC

IOMUXC_GPIO_AD_23_LPIT2_TRIGGER03

IOMUXC_GPIO_AD_23_SINC1_EMBIT01

IOMUXC_GPIO_AD_23_GPIO4_IO23

IOMUXC_GPIO_AD_23_NETC_TMR_ALARM2

IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23

IOMUXC_GPIO_AD_23_ECAT_LED_STATE_RUN

IOMUXC_GPIO_AD_24_LPUART6_TX

IOMUXC_GPIO_AD_24_LPI2C4_SCL

IOMUXC_GPIO_AD_24_SINC2_MOD_CLK1

IOMUXC_GPIO_AD_24_FLEXPWM2_PWMA00

IOMUXC_GPIO_AD_24_GPIO4_IO24

IOMUXC_GPIO_AD_24_NETC_TMR_TRIG1

IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24

IOMUXC_GPIO_AD_24_ECAT_LINK_ACT00

IOMUXC_GPIO_AD_25_ECAT_LINK_ACT01

IOMUXC_GPIO_AD_25_LPUART6_RX

IOMUXC_GPIO_AD_25_LPI2C4_SDA

IOMUXC_GPIO_AD_25_LPSPI5_PCS3

IOMUXC_GPIO_AD_25_SINC2_MOD_CLK2

IOMUXC_GPIO_AD_25_FLEXPWM2_PWMB00

IOMUXC_GPIO_AD_25_GPIO4_IO25

IOMUXC_GPIO_AD_25_NETC_TMR_TRIG2

IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25

IOMUXC_GPIO_AD_26_LPUART6_CTS_B

IOMUXC_GPIO_AD_26_LPUART5_TX

IOMUXC_GPIO_AD_26_LPSPI5_PCS2

IOMUXC_GPIO_AD_26_SINC2_EMCLK00

IOMUXC_GPIO_AD_26_FLEXPWM2_PWMA01

IOMUXC_GPIO_AD_26_GPIO4_IO26

IOMUXC_GPIO_AD_26_KPP_ROW00

IOMUXC_GPIO_AD_26_NETC_TMR_PP1

IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26

IOMUXC_GPIO_AD_26_USDHC2_CD_B

IOMUXC_GPIO_AD_26_MIC_BITSTREAM02

IOMUXC_GPIO_AD_27_LPUART6_RTS_B

IOMUXC_GPIO_AD_27_LPUART5_RX

IOMUXC_GPIO_AD_27_LPSPI5_PCS1

IOMUXC_GPIO_AD_27_SINC2_EMBIT00

IOMUXC_GPIO_AD_27_FLEXPWM2_PWMB01

IOMUXC_GPIO_AD_27_GPIO4_IO27

IOMUXC_GPIO_AD_27_KPP_COL00

IOMUXC_GPIO_AD_27_NETC_TMR_PP2

IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27

IOMUXC_GPIO_AD_27_USDHC2_WP

IOMUXC_GPIO_AD_27_MIC_CLK

IOMUXC_GPIO_AD_28_MIC_BITSTREAM00

IOMUXC_GPIO_AD_28_LPSPI5_SCK

IOMUXC_GPIO_AD_28_I3C1_PUR

IOMUXC_GPIO_AD_28_SINC2_EMCLK01

IOMUXC_GPIO_AD_28_FLEXPWM2_PWMB02

IOMUXC_GPIO_AD_28_GPIO4_IO28

IOMUXC_GPIO_AD_28_KPP_ROW03

IOMUXC_GPIO_AD_28_NETC_TMR_PP3

IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28

IOMUXC_GPIO_AD_28_USDHC2_RESET_B

IOMUXC_GPIO_AD_29_LPSPI5_PCS0

IOMUXC_GPIO_AD_29_USDHC2_CD_B

IOMUXC_GPIO_AD_29_SINC2_EMBIT01

IOMUXC_GPIO_AD_29_FLEXPWM2_PWMA02

IOMUXC_GPIO_AD_29_GPIO4_IO29

IOMUXC_GPIO_AD_29_KPP_COL03

IOMUXC_GPIO_AD_29_EWM_EWM_OUT_B

IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29

IOMUXC_GPIO_AD_29_USDHC2_VSELECT

IOMUXC_GPIO_AD_29_MIC_BITSTREAM01

IOMUXC_GPIO_AD_30_LPSPI5_SDO

IOMUXC_GPIO_AD_30_USB_OTG2_OC

IOMUXC_GPIO_AD_30_CAN2_TX

IOMUXC_GPIO_AD_30_SINC2_EMCLK02

IOMUXC_GPIO_AD_30_LPUART8_TX

IOMUXC_GPIO_AD_30_GPIO4_IO30

IOMUXC_GPIO_AD_30_KPP_ROW02

IOMUXC_GPIO_AD_30_NETC_EMDC

IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30

IOMUXC_GPIO_AD_30_XBAR1_XBAR_INOUT24

IOMUXC_GPIO_AD_30_ECAT_MCLK

IOMUXC_GPIO_AD_31_LPSPI5_SDI

IOMUXC_GPIO_AD_31_USB_OTG2_PWR

IOMUXC_GPIO_AD_31_CAN2_RX

IOMUXC_GPIO_AD_31_SINC2_EMBIT02

IOMUXC_GPIO_AD_31_LPUART8_RX

IOMUXC_GPIO_AD_31_GPIO4_IO31

IOMUXC_GPIO_AD_31_KPP_COL02

IOMUXC_GPIO_AD_31_NETC_EMDIO

IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31

IOMUXC_GPIO_AD_31_XBAR1_XBAR_INOUT25

IOMUXC_GPIO_AD_31_ECAT_MDIO

IOMUXC_GPIO_AD_32_MIC_BITSTREAM03

IOMUXC_GPIO_AD_32_LPI2C5_SCL

IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID

IOMUXC_GPIO_AD_32_GPC_PMIC_RDY

IOMUXC_GPIO_AD_32_SINC2_EMCLK03

IOMUXC_GPIO_AD_32_USDHC1_CD_B

IOMUXC_GPIO_AD_32_GPIO5_IO00

IOMUXC_GPIO_AD_32_KPP_ROW01

IOMUXC_GPIO_AD_32_NETC_TMR_TRIG1

IOMUXC_GPIO_AD_32_LPUART10_TX

IOMUXC_GPIO_AD_33_LPI2C5_SDA

IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID

IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17

IOMUXC_GPIO_AD_33_SINC2_EMBIT03

IOMUXC_GPIO_AD_33_USDHC1_WP

IOMUXC_GPIO_AD_33_GPIO5_IO01

IOMUXC_GPIO_AD_33_KPP_COL01

IOMUXC_GPIO_AD_33_NETC_TMR_TRIG2

IOMUXC_GPIO_AD_33_LPUART10_RX

IOMUXC_GPIO_AD_34_I3C2_SCL

IOMUXC_GPIO_AD_34_USB_OTG1_PWR

IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18

IOMUXC_GPIO_AD_34_SINC_FILTER_GLUE2_BREAK

IOMUXC_GPIO_AD_34_USDHC1_VSELECT

IOMUXC_GPIO_AD_34_GPIO5_IO02

IOMUXC_GPIO_AD_34_NETC_TMR_ALARM1

IOMUXC_GPIO_AD_34_LPUART10_CTS_B

IOMUXC_GPIO_AD_35_I3C2_SDA

IOMUXC_GPIO_AD_35_USB_OTG1_OC

IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19

IOMUXC_GPIO_AD_35_SINC2_MOD_CLK0

IOMUXC_GPIO_AD_35_USDHC1_RESET_B

IOMUXC_GPIO_AD_35_GPIO5_IO03

IOMUXC_GPIO_AD_35_NETC_TMR_ALARM2

IOMUXC_GPIO_AD_35_LPUART10_RTS_B

IOMUXC_GPIO_SD_B1_00_USDHC1_CMD

IOMUXC_GPIO_SD_B1_00_SINC1_EMCLK02

IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20

IOMUXC_GPIO_SD_B1_00_LPTMR2_ALT1

IOMUXC_GPIO_SD_B1_00_XSPI_SLV_CS

IOMUXC_GPIO_SD_B1_00_GPIO5_IO04

IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0

IOMUXC_GPIO_SD_B1_00_KPP_ROW07

IOMUXC_GPIO_SD_B1_00_CCM_CLKO1

IOMUXC_GPIO_SD_B1_01_USDHC1_CLK

IOMUXC_GPIO_SD_B1_01_SINC1_EMBIT02

IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21

IOMUXC_GPIO_SD_B1_01_LPTMR2_ALT2

IOMUXC_GPIO_SD_B1_01_XSPI_SLV_CLK

IOMUXC_GPIO_SD_B1_01_GPIO5_IO05

IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK

IOMUXC_GPIO_SD_B1_01_KPP_COL07

IOMUXC_GPIO_SD_B1_01_CCM_CLKO2

IOMUXC_GPIO_SD_B1_02_ECAT_RESET_OUT

IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0

IOMUXC_GPIO_SD_B1_02_SINC1_EMCLK03

IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22

IOMUXC_GPIO_SD_B1_02_LPTMR2_ALT3

IOMUXC_GPIO_SD_B1_02_XSPI_SLV_DATA04

IOMUXC_GPIO_SD_B1_02_GPIO5_IO06

IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO

IOMUXC_GPIO_SD_B1_02_KPP_ROW06

IOMUXC_GPIO_SD_B1_02_FLEXSPI1_BUS2BIT_A_SS1_B

IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1

IOMUXC_GPIO_SD_B1_03_SINC1_EMBIT03

IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23

IOMUXC_GPIO_SD_B1_03_LPTMR3_ALT1

IOMUXC_GPIO_SD_B1_03_XSPI_SLV_DATA05

IOMUXC_GPIO_SD_B1_03_GPIO5_IO07

IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI

IOMUXC_GPIO_SD_B1_03_KPP_COL06

IOMUXC_GPIO_SD_B1_03_FLEXSPI1_BUS2BIT_B_SS1_B

IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2

IOMUXC_GPIO_SD_B1_04_SINC_FILTER_GLUE1_BREAK

IOMUXC_GPIO_SD_B1_04_SINC2_EMCLK02

IOMUXC_GPIO_SD_B1_04_LPTMR3_ALT2

IOMUXC_GPIO_SD_B1_04_XSPI_SLV_DATA06

IOMUXC_GPIO_SD_B1_04_GPIO5_IO08

IOMUXC_GPIO_SD_B1_04_LPSPI3_PCS1

IOMUXC_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B

IOMUXC_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_A_SS1_B

IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3

IOMUXC_GPIO_SD_B1_05_SINC2_EMBIT02

IOMUXC_GPIO_SD_B1_05_LPTMR3_ALT3

IOMUXC_GPIO_SD_B1_05_XSPI_SLV_DATA07

IOMUXC_GPIO_SD_B1_05_GPIO5_IO09

IOMUXC_GPIO_SD_B1_05_LPSPI3_PCS2

IOMUXC_GPIO_SD_B1_05_FLEXSPI1_BUS2BIT_B_SS0_B

IOMUXC_GPIO_SD_B2_00_MIC_BITSTREAM00

IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3

IOMUXC_GPIO_SD_B2_00_FLEXSPI1_BUS2BIT_B_DATA04

IOMUXC_GPIO_SD_B2_00_XSPI_SLV_DATA04

IOMUXC_GPIO_SD_B2_00_XBAR1_XBAR_INOUT17

IOMUXC_GPIO_SD_B2_00_KPP_ROW01

IOMUXC_GPIO_SD_B2_00_GPIO5_IO10

IOMUXC_GPIO_SD_B2_00_LPSPI3_PCS3

IOMUXC_GPIO_SD_B2_00_NETC_1588_CLK

IOMUXC_GPIO_SD_B2_00_LPUART8_TX

IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2

IOMUXC_GPIO_SD_B2_01_FLEXSPI1_BUS2BIT_B_DATA05

IOMUXC_GPIO_SD_B2_01_XSPI_SLV_DATA05

IOMUXC_GPIO_SD_B2_01_QTIMER6_TIMER0

IOMUXC_GPIO_SD_B2_01_KPP_COL01

IOMUXC_GPIO_SD_B2_01_GPIO5_IO11

IOMUXC_GPIO_SD_B2_01_NETC_TMR_GCLK

IOMUXC_GPIO_SD_B2_01_LPUART8_RX

IOMUXC_GPIO_SD_B2_01_MIC_BITSTREAM01

IOMUXC_GPIO_SD_B2_02_MIC_BITSTREAM02

IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1

IOMUXC_GPIO_SD_B2_02_FLEXSPI1_BUS2BIT_B_DATA06

IOMUXC_GPIO_SD_B2_02_XSPI_SLV_DATA06

IOMUXC_GPIO_SD_B2_02_QTIMER6_TIMER1

IOMUXC_GPIO_SD_B2_02_KPP_ROW00

IOMUXC_GPIO_SD_B2_02_GPIO5_IO12

IOMUXC_GPIO_SD_B2_02_NETC_TMR_ALARM1

IOMUXC_GPIO_SD_B2_02_LPUART8_CTS_B

IOMUXC_GPIO_SD_B2_03_MIC_BITSTREAM03

IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0

IOMUXC_GPIO_SD_B2_03_FLEXSPI1_BUS2BIT_B_DATA07

IOMUXC_GPIO_SD_B2_03_XSPI_SLV_DATA07

IOMUXC_GPIO_SD_B2_03_QTIMER6_TIMER2

IOMUXC_GPIO_SD_B2_03_KPP_COL00

IOMUXC_GPIO_SD_B2_03_GPIO5_IO13

IOMUXC_GPIO_SD_B2_03_NETC_TMR_ALARM2

IOMUXC_GPIO_SD_B2_03_LPUART8_RTS_B

IOMUXC_GPIO_SD_B2_04_USDHC2_CLK

IOMUXC_GPIO_SD_B2_04_FLEXSPI1_BUS2BIT_B_SS1_B

IOMUXC_GPIO_SD_B2_04_QTIMER7_TIMER0

IOMUXC_GPIO_SD_B2_04_KPP_ROW03

IOMUXC_GPIO_SD_B2_04_GPIO5_IO14

IOMUXC_GPIO_SD_B2_04_LPUART5_RI_B

IOMUXC_GPIO_SD_B2_04_NETC_TMR_PP1

IOMUXC_GPIO_SD_B2_04_MIC_CLK

IOMUXC_GPIO_SD_B2_05_USDHC2_CMD

IOMUXC_GPIO_SD_B2_05_FLEXSPI1_BUS2BIT_B_DQS

IOMUXC_GPIO_SD_B2_05_XSPI_SLV_DQS

IOMUXC_GPIO_SD_B2_05_QTIMER7_TIMER1

IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS3

IOMUXC_GPIO_SD_B2_05_GPIO5_IO15

IOMUXC_GPIO_SD_B2_05_LPUART5_DTR_B

IOMUXC_GPIO_SD_B2_05_NETC_TMR_PP2

IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B

IOMUXC_GPIO_SD_B2_06_FLEXSPI1_BUS2BIT_B_SS0_B

IOMUXC_GPIO_SD_B2_06_XSPI_SLV_CS

IOMUXC_GPIO_SD_B2_06_QTIMER7_TIMER2

IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS2

IOMUXC_GPIO_SD_B2_06_GPIO5_IO16

IOMUXC_GPIO_SD_B2_06_LPUART5_CTS_B

IOMUXC_GPIO_SD_B2_06_NETC_TMR_PP3

IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE

IOMUXC_GPIO_SD_B2_07_FLEXSPI1_BUS2BIT_B_SCLK

IOMUXC_GPIO_SD_B2_07_XSPI_SLV_CLK

IOMUXC_GPIO_SD_B2_07_QTIMER7_TIMER3

IOMUXC_GPIO_SD_B2_07_LPSPI4_PCS1

IOMUXC_GPIO_SD_B2_07_GPIO5_IO17

IOMUXC_GPIO_SD_B2_07_LPUART5_RTS_B

IOMUXC_GPIO_SD_B2_07_NETC_TMR_ALARM1

IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4

IOMUXC_GPIO_SD_B2_08_FLEXSPI1_BUS2BIT_B_DATA00

IOMUXC_GPIO_SD_B2_08_XSPI_SLV_DATA00

IOMUXC_GPIO_SD_B2_08_QTIMER8_TIMER0

IOMUXC_GPIO_SD_B2_08_LPSPI4_SCK

IOMUXC_GPIO_SD_B2_08_GPIO5_IO18

IOMUXC_GPIO_SD_B2_08_LPUART5_TX

IOMUXC_GPIO_SD_B2_08_NETC_TMR_ALARM2

IOMUXC_GPIO_SD_B2_08_NETC_TMR_PP2

IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5

IOMUXC_GPIO_SD_B2_09_FLEXSPI1_BUS2BIT_B_DATA01

IOMUXC_GPIO_SD_B2_09_XSPI_SLV_DATA01

IOMUXC_GPIO_SD_B2_09_QTIMER8_TIMER1

IOMUXC_GPIO_SD_B2_09_LPSPI4_PCS0

IOMUXC_GPIO_SD_B2_09_GPIO5_IO19

IOMUXC_GPIO_SD_B2_09_LPUART5_RX

IOMUXC_GPIO_SD_B2_09_NETC_TMR_PP1

IOMUXC_GPIO_SD_B2_10_NETC_EMDIO

IOMUXC_GPIO_SD_B2_10_ECAT_MDIO

IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6

IOMUXC_GPIO_SD_B2_10_FLEXSPI1_BUS2BIT_B_DATA02

IOMUXC_GPIO_SD_B2_10_XSPI_SLV_DATA02

IOMUXC_GPIO_SD_B2_10_QTIMER8_TIMER2

IOMUXC_GPIO_SD_B2_10_LPSPI4_SDO

IOMUXC_GPIO_SD_B2_10_GPIO5_IO20

IOMUXC_GPIO_SD_B2_10_LPUART5_DCD_B

IOMUXC_GPIO_SD_B2_10_NETC_TMR_TRIG2

IOMUXC_GPIO_SD_B2_10_NETC_TMR_PP3

IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7

IOMUXC_GPIO_SD_B2_11_FLEXSPI1_BUS2BIT_B_DATA03

IOMUXC_GPIO_SD_B2_11_XSPI_SLV_DATA03

IOMUXC_GPIO_SD_B2_11_QTIMER8_TIMER3

IOMUXC_GPIO_SD_B2_11_LPSPI4_SDI

IOMUXC_GPIO_SD_B2_11_GPIO5_IO21

IOMUXC_GPIO_SD_B2_11_LPUART5_DSR_B

IOMUXC_GPIO_SD_B2_11_SFA_ATX_CLK_OUT

IOMUXC_GPIO_SD_B2_11_NETC_TMR_TRIG1

IOMUXC_GPIO_SD_B2_11_NETC_EMDC

IOMUXC_GPIO_SD_B2_11_ECAT_MCLK

IOMUXC_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_A_DQS

IOMUXC_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_B_DQS

IOMUXC_GPIO_SD_B2_12_DUMMY_GPIO5_IO22

IOMUXC_GPIO_B1_00_NETC_PINMUX_ETH1_TXD00

IOMUXC_GPIO_B1_00_ADC2_CONV_D00

IOMUXC_GPIO_B1_00_SEMC_CSX01

IOMUXC_GPIO_B1_00_QTIMER1_TIMER0

IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT26

IOMUXC_GPIO_B1_00_GPIO6_IO00

IOMUXC_GPIO_B1_00_TPM5_CH00

IOMUXC_GPIO_B1_00_NETC_PINMUX_ETH4_TXD00

IOMUXC_GPIO_B1_01_NETC_PINMUX_ETH1_TXD01

IOMUXC_GPIO_B1_01_ADC2_CONV_D01

IOMUXC_GPIO_B1_01_SEMC_CSX02

IOMUXC_GPIO_B1_01_QTIMER1_TIMER1

IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT27

IOMUXC_GPIO_B1_01_GPIO6_IO01

IOMUXC_GPIO_B1_01_TPM5_CH01

IOMUXC_GPIO_B1_01_NETC_PINMUX_ETH4_TXD01

IOMUXC_GPIO_B1_01_SAI4_RX_DATA00

IOMUXC_GPIO_B1_02_NETC_PINMUX_ETH1_TX_EN

IOMUXC_GPIO_B1_02_ADC2_CONV_D02

IOMUXC_GPIO_B1_02_LPI2C6_SCL

IOMUXC_GPIO_B1_02_QTIMER1_TIMER2

IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT28

IOMUXC_GPIO_B1_02_GPIO6_IO02

IOMUXC_GPIO_B1_02_TPM5_CH02

IOMUXC_GPIO_B1_02_FLEXSPI1_BUS2BIT_B_SS1_B

IOMUXC_GPIO_B1_02_NETC_PINMUX_ETH4_TX_EN

IOMUXC_GPIO_B1_02_LPUART11_TX

IOMUXC_GPIO_B1_02_SAI4_RX_DATA01

IOMUXC_GPIO_B1_03_NETC_PINMUX_ETH1_TX_CLK

IOMUXC_GPIO_B1_03_ADC2_CONV_D03

IOMUXC_GPIO_B1_03_LPI2C6_SDA

IOMUXC_GPIO_B1_03_QTIMER2_TIMER0

IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT29

IOMUXC_GPIO_B1_03_GPIO6_IO03

IOMUXC_GPIO_B1_03_TPM5_CH03

IOMUXC_GPIO_B1_03_FLEXSPI1_BUS2BIT_B_DQS

IOMUXC_GPIO_B1_03_NETC_PINMUX_ETH4_TX_CLK

IOMUXC_GPIO_B1_03_LPUART11_RX

IOMUXC_GPIO_B1_03_SAI4_RX_DATA02

IOMUXC_GPIO_B1_04_NETC_PINMUX_ETH1_RXD00

IOMUXC_GPIO_B1_04_ADC2_CONV_D04

IOMUXC_GPIO_B1_04_LPUART9_RX

IOMUXC_GPIO_B1_04_QTIMER2_TIMER1

IOMUXC_GPIO_B1_04_XBAR1_XBAR_INOUT30

IOMUXC_GPIO_B1_04_GPIO6_IO04

IOMUXC_GPIO_B1_04_TPM5_EXTCLK

IOMUXC_GPIO_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B

IOMUXC_GPIO_B1_04_NETC_PINMUX_ETH4_RXD00

IOMUXC_GPIO_B1_04_SAI4_RX_DATA03

IOMUXC_GPIO_B1_05_NETC_PINMUX_ETH1_RXD01

IOMUXC_GPIO_B1_05_ADC2_CONV_D05

IOMUXC_GPIO_B1_05_LPUART9_CTS_B

IOMUXC_GPIO_B1_05_QTIMER2_TIMER2

IOMUXC_GPIO_B1_05_XBAR1_XBAR_INOUT31

IOMUXC_GPIO_B1_05_GPIO6_IO05

IOMUXC_GPIO_B1_05_TPM6_EXTCLK

IOMUXC_GPIO_B1_05_FLEXSPI1_BUS2BIT_B_SCLK

IOMUXC_GPIO_B1_05_NETC_PINMUX_ETH4_RXD01

IOMUXC_GPIO_B1_05_SAI4_MCLK

IOMUXC_GPIO_B1_06_NETC_PINMUX_ETH1_RX_DV

IOMUXC_GPIO_B1_06_ADC2_CONV_D06

IOMUXC_GPIO_B1_06_LPUART9_TX

IOMUXC_GPIO_B1_06_QTIMER3_TIMER0

IOMUXC_GPIO_B1_06_XBAR1_XBAR_INOUT32

IOMUXC_GPIO_B1_06_GPIO6_IO06

IOMUXC_GPIO_B1_06_TPM6_CH00

IOMUXC_GPIO_B1_06_FLEXSPI1_BUS2BIT_B_DATA07

IOMUXC_GPIO_B1_06_NETC_PINMUX_ETH4_RX_DV

IOMUXC_GPIO_B1_06_SAI4_RX_BCLK

IOMUXC_GPIO_B1_07_NETC_PINMUX_ETH1_TXD02

IOMUXC_GPIO_B1_07_ADC2_CONV_D07

IOMUXC_GPIO_B1_07_LPUART9_RTS_B

IOMUXC_GPIO_B1_07_QTIMER3_TIMER1

IOMUXC_GPIO_B1_07_XBAR1_XBAR_INOUT33

IOMUXC_GPIO_B1_07_GPIO6_IO07

IOMUXC_GPIO_B1_07_TPM6_CH01

IOMUXC_GPIO_B1_07_FLEXSPI1_BUS2BIT_B_DATA06

IOMUXC_GPIO_B1_07_NETC_PINMUX_ETH4_TXD02

IOMUXC_GPIO_B1_07_LPSPI6_SDI

IOMUXC_GPIO_B1_07_SAI4_RX_SYNC

IOMUXC_GPIO_B1_08_SAI4_TX_BCLK

IOMUXC_GPIO_B1_08_NETC_PINMUX_ETH1_TXD03

IOMUXC_GPIO_B1_08_ADC2_CONV_RDY_CLK

IOMUXC_GPIO_B1_08_USDHC1_CD_B

IOMUXC_GPIO_B1_08_QTIMER3_TIMER2

IOMUXC_GPIO_B1_08_XBAR1_XBAR_INOUT36

IOMUXC_GPIO_B1_08_GPIO6_IO08

IOMUXC_GPIO_B1_08_TPM6_CH02

IOMUXC_GPIO_B1_08_FLEXSPI1_BUS2BIT_B_DATA05

IOMUXC_GPIO_B1_08_NETC_PINMUX_ETH4_TXD03

IOMUXC_GPIO_B1_08_LPSPI6_SDO

IOMUXC_GPIO_B1_09_NETC_PINMUX_ETH1_RXD02

IOMUXC_GPIO_B1_09_USDHC1_WP

IOMUXC_GPIO_B1_09_QTIMER4_TIMER0

IOMUXC_GPIO_B1_09_XBAR1_XBAR_INOUT37

IOMUXC_GPIO_B1_09_GPIO6_IO09

IOMUXC_GPIO_B1_09_TPM6_CH03

IOMUXC_GPIO_B1_09_FLEXSPI1_BUS2BIT_B_DATA04

IOMUXC_GPIO_B1_09_NETC_PINMUX_ETH4_RXD02

IOMUXC_GPIO_B1_09_LPSPI6_PCS1

IOMUXC_GPIO_B1_09_SAI4_TX_SYNC

IOMUXC_GPIO_B1_10_NETC_PINMUX_ETH1_RXD03

IOMUXC_GPIO_B1_10_USDHC1_RESET_B

IOMUXC_GPIO_B1_10_QTIMER4_TIMER1

IOMUXC_GPIO_B1_10_XBAR1_XBAR_INOUT34

IOMUXC_GPIO_B1_10_GPIO6_IO10

IOMUXC_GPIO_B1_10_FLEXSPI1_BUS2BIT_B_DATA03

IOMUXC_GPIO_B1_10_NETC_PINMUX_ETH4_RXD03

IOMUXC_GPIO_B1_10_LPSPI6_PCS2

IOMUXC_GPIO_B1_10_SAI4_TX_DATA00

IOMUXC_GPIO_B1_11_NETC_PINMUX_ETH1_RX_CLK

IOMUXC_GPIO_B1_11_QTIMER4_TIMER2

IOMUXC_GPIO_B1_11_XBAR1_XBAR_INOUT35

IOMUXC_GPIO_B1_11_GPIO6_IO11

IOMUXC_GPIO_B1_11_FLEXSPI1_BUS2BIT_B_DATA02

IOMUXC_GPIO_B1_11_NETC_PINMUX_ETH4_RX_CLK

IOMUXC_GPIO_B1_11_LPSPI6_PCS3

IOMUXC_GPIO_B1_11_SAI4_TX_DATA01

IOMUXC_GPIO_B1_12_SAI4_TX_DATA02

IOMUXC_GPIO_B1_12_NETC_PINMUX_ETH1_RX_ER

IOMUXC_GPIO_B1_12_NETC_EMDIO

IOMUXC_GPIO_B1_12_GPIO6_IO12

IOMUXC_GPIO_B1_12_FLEXSPI1_BUS2BIT_B_DATA01

IOMUXC_GPIO_B1_12_NETC_PINMUX_ETH4_RX_ER

IOMUXC_GPIO_B1_12_LPSPI6_PCS0

IOMUXC_GPIO_B1_13_NETC_PINMUX_ETH1_TX_ER

IOMUXC_GPIO_B1_13_NETC_EMDC

IOMUXC_GPIO_B1_13_USDHC1_VSELECT

IOMUXC_GPIO_B1_13_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_B1_13_GPIO6_IO13

IOMUXC_GPIO_B1_13_FLEXSPI1_BUS2BIT_B_DATA00

IOMUXC_GPIO_B1_13_NETC_PINMUX_ETH4_TX_ER

IOMUXC_GPIO_B1_13_LPSPI6_SCK

IOMUXC_GPIO_B1_13_SAI4_TX_DATA03

IOMUXC_GPIO_B2_00_NETC_ETH2_SLV_MDIO

IOMUXC_GPIO_B2_00_ECAT_CLK_ECAT_CLK25

IOMUXC_GPIO_B2_00_NETC_ETH1_CRS

IOMUXC_GPIO_B2_00_SEMC_CSX03

IOMUXC_GPIO_B2_00_LPIT3_TRIGGER00

IOMUXC_GPIO_B2_00_SAI4_MCLK

IOMUXC_GPIO_B2_00_GPIO6_IO14

IOMUXC_GPIO_B2_00_NETC_ETH4_CRS

IOMUXC_GPIO_B2_00_LPSPI6_SDI

IOMUXC_GPIO_B2_01_NETC_ETH2_SLV_MDC

IOMUXC_GPIO_B2_01_NETC_PINMUX_ETH2_RX_ER

IOMUXC_GPIO_B2_01_ECAT_RX_ER_1

IOMUXC_GPIO_B2_01_NETC_ETH1_COL

IOMUXC_GPIO_B2_01_LPIT3_TRIGGER01

IOMUXC_GPIO_B2_01_SAI4_TX_BCLK

IOMUXC_GPIO_B2_01_GPIO6_IO15

IOMUXC_GPIO_B2_01_FLEXSPI1_BUS2BIT_A_SS1_B

IOMUXC_GPIO_B2_01_NETC_ETH4_COL

IOMUXC_GPIO_B2_01_LPSPI6_SDO

IOMUXC_GPIO_B2_02_EWM_EWM_OUT_B

IOMUXC_GPIO_B2_02_NETC_PINMUX_ETH2_RXD02

IOMUXC_GPIO_B2_02_ECAT_RX_DATA2_1

IOMUXC_GPIO_B2_02_LPIT3_TRIGGER02

IOMUXC_GPIO_B2_02_NETC_EMDIO

IOMUXC_GPIO_B2_02_SAI4_TX_SYNC

IOMUXC_GPIO_B2_02_GPIO6_IO16

IOMUXC_GPIO_B2_02_FLEXSPI1_BUS2BIT_B_SCLK

IOMUXC_GPIO_B2_02_CCM_ENET_REF_CLK_25M

IOMUXC_GPIO_B2_03_XSPI_SLV_DATA04

IOMUXC_GPIO_B2_03_NETC_PINMUX_ETH2_RXD03

IOMUXC_GPIO_B2_03_ECAT_RX_DATA3_1

IOMUXC_GPIO_B2_03_LPIT3_TRIGGER03

IOMUXC_GPIO_B2_03_NETC_EMDC

IOMUXC_GPIO_B2_03_SAI4_TX_DATA00

IOMUXC_GPIO_B2_03_GPIO6_IO17

IOMUXC_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04

IOMUXC_GPIO_B2_04_XSPI_SLV_DATA05

IOMUXC_GPIO_B2_04_NETC_PINMUX_ETH2_TXD02

IOMUXC_GPIO_B2_04_ECAT_TX_DATA2_1

IOMUXC_GPIO_B2_04_SINC1_MOD_CLK0

IOMUXC_GPIO_B2_04_SINC2_MOD_CLK0

IOMUXC_GPIO_B2_04_SINC3_MOD_CLK0

IOMUXC_GPIO_B2_04_SAI4_RX_SYNC

IOMUXC_GPIO_B2_04_GPIO6_IO18

IOMUXC_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05

IOMUXC_GPIO_B2_04_TPM3_EXTCLK

IOMUXC_GPIO_B2_05_XSPI_SLV_DATA06

IOMUXC_GPIO_B2_05_NETC_PINMUX_ETH2_TXD03

IOMUXC_GPIO_B2_05_ECAT_TX_DATA3_1

IOMUXC_GPIO_B2_05_SINC1_MOD_CLK1

IOMUXC_GPIO_B2_05_SINC2_MOD_CLK1

IOMUXC_GPIO_B2_05_SINC3_MOD_CLK1

IOMUXC_GPIO_B2_05_SAI4_RX_BCLK

IOMUXC_GPIO_B2_05_GPIO6_IO19

IOMUXC_GPIO_B2_05_MIC_CLK

IOMUXC_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06

IOMUXC_GPIO_B2_05_TPM3_CH00

IOMUXC_GPIO_B2_06_XSPI_SLV_DATA07

IOMUXC_GPIO_B2_06_NETC_PINMUX_ETH2_TXD00

IOMUXC_GPIO_B2_06_ECAT_TX_DATA0_1

IOMUXC_GPIO_B2_06_SINC1_MOD_CLK2

IOMUXC_GPIO_B2_06_SINC2_MOD_CLK2

IOMUXC_GPIO_B2_06_SINC3_MOD_CLK2

IOMUXC_GPIO_B2_06_LPUART6_DSR_B

IOMUXC_GPIO_B2_06_SAI4_RX_DATA00

IOMUXC_GPIO_B2_06_GPIO6_IO20

IOMUXC_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07

IOMUXC_GPIO_B2_06_TPM3_CH01

IOMUXC_GPIO_B2_06_LPUART11_TX

IOMUXC_GPIO_B2_07_XSPI_SLV_DQS

IOMUXC_GPIO_B2_07_NETC_PINMUX_ETH2_TXD01

IOMUXC_GPIO_B2_07_ECAT_TX_DATA1_1

IOMUXC_GPIO_B2_07_QTIMER5_TIMER0

IOMUXC_GPIO_B2_07_LPUART6_DCD_B

IOMUXC_GPIO_B2_07_SAI4_TX_DATA01

IOMUXC_GPIO_B2_07_GPIO6_IO21

IOMUXC_GPIO_B2_07_SAI4_RX_DATA01

IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS

IOMUXC_GPIO_B2_07_TPM3_CH02

IOMUXC_GPIO_B2_07_LPUART11_RX

IOMUXC_GPIO_B2_08_XSPI_SLV_CLK

IOMUXC_GPIO_B2_08_NETC_PINMUX_ETH2_TX_EN

IOMUXC_GPIO_B2_08_ECAT_TX_EN_1

IOMUXC_GPIO_B2_08_QTIMER5_TIMER1

IOMUXC_GPIO_B2_08_SINC2_EMCLK02

IOMUXC_GPIO_B2_08_LPUART6_RI_B

IOMUXC_GPIO_B2_08_GPIO6_IO22

IOMUXC_GPIO_B2_08_LPI2C6_SCL

IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK

IOMUXC_GPIO_B2_08_TPM3_CH03

IOMUXC_GPIO_B2_08_SPDIF_IN

IOMUXC_GPIO_B2_09_XSPI_SLV_CS

IOMUXC_GPIO_B2_09_NETC_PINMUX_ETH2_TX_CLK

IOMUXC_GPIO_B2_09_ECAT_TX_CLK_1

IOMUXC_GPIO_B2_09_QTIMER5_TIMER2

IOMUXC_GPIO_B2_09_SINC2_EMBIT02

IOMUXC_GPIO_B2_09_LPUART6_DTR_B

IOMUXC_GPIO_B2_09_GPIO6_IO23

IOMUXC_GPIO_B2_09_LPI2C6_SDA

IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B

IOMUXC_GPIO_B2_09_TPM4_EXTCLK

IOMUXC_GPIO_B2_09_SPDIF_OUT

IOMUXC_GPIO_B2_10_XSPI_SLV_DATA00

IOMUXC_GPIO_B2_10_NETC_PINMUX_ETH2_RXD00

IOMUXC_GPIO_B2_10_ECAT_RX_DATA0_1

IOMUXC_GPIO_B2_10_MIC_BITSTREAM00

IOMUXC_GPIO_B2_10_SINC2_EMCLK03

IOMUXC_GPIO_B2_10_CAN3_TX

IOMUXC_GPIO_B2_10_LPUART8_CTS_B

IOMUXC_GPIO_B2_10_LPUART6_TX

IOMUXC_GPIO_B2_10_GPIO6_IO24

IOMUXC_GPIO_B2_10_LPI2C4_SCL

IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00

IOMUXC_GPIO_B2_10_TPM4_CH00

IOMUXC_GPIO_B2_10_LPSPI4_SCK

IOMUXC_GPIO_B2_11_XSPI_SLV_DATA01

IOMUXC_GPIO_B2_11_NETC_PINMUX_ETH2_RXD01

IOMUXC_GPIO_B2_11_ECAT_RX_DATA1_1

IOMUXC_GPIO_B2_11_MIC_BITSTREAM01

IOMUXC_GPIO_B2_11_SINC2_EMBIT03

IOMUXC_GPIO_B2_11_CAN3_RX

IOMUXC_GPIO_B2_11_LPUART8_RTS_B

IOMUXC_GPIO_B2_11_LPUART6_RX

IOMUXC_GPIO_B2_11_GPIO6_IO25

IOMUXC_GPIO_B2_11_LPI2C4_SDA

IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01

IOMUXC_GPIO_B2_11_TPM4_CH01

IOMUXC_GPIO_B2_11_LPSPI4_SDI

IOMUXC_GPIO_B2_12_MIC_BITSTREAM02

IOMUXC_GPIO_B2_12_SINC_FILTER_GLUE2_BREAK

IOMUXC_GPIO_B2_12_LPUART8_TX

IOMUXC_GPIO_B2_12_LPUART6_CTS_B

IOMUXC_GPIO_B2_12_GPIO6_IO26

IOMUXC_GPIO_B2_12_CAN3_TX

IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02

IOMUXC_GPIO_B2_12_TPM4_CH02

IOMUXC_GPIO_B2_12_LPSPI4_SDO

IOMUXC_GPIO_B2_12_XSPI_SLV_DATA02

IOMUXC_GPIO_B2_12_NETC_PINMUX_ETH2_RX_DV

IOMUXC_GPIO_B2_12_ECAT_RX_DV_1

IOMUXC_GPIO_B2_13_MIC_BITSTREAM03

IOMUXC_GPIO_B2_13_SINC2_EMCLK00

IOMUXC_GPIO_B2_13_LPUART8_RX

IOMUXC_GPIO_B2_13_LPUART6_RTS_B

IOMUXC_GPIO_B2_13_GPIO6_IO27

IOMUXC_GPIO_B2_13_CAN3_RX

IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03

IOMUXC_GPIO_B2_13_TPM4_CH03

IOMUXC_GPIO_B2_13_LPSPI4_PCS0

IOMUXC_GPIO_B2_13_XSPI_SLV_DATA03

IOMUXC_GPIO_B2_13_NETC_PINMUX_ETH2_RX_CLK

IOMUXC_GPIO_B2_13_ECAT_RX_CLK_1

IOMUXC_GPIO_AON_00_SRC_BOOT_MODE00

IOMUXC_GPIO_AON_00_CAN1_TX

IOMUXC_GPIO_AON_00_LPTMR1_ALT1

IOMUXC_GPIO_AON_00_GPIO1_IO00

IOMUXC_GPIO_AON_00_LPUART2_TX

IOMUXC_GPIO_AON_00_TPM1_EXTCLK

IOMUXC_GPIO_AON_01_SRC_BOOT_MODE01

IOMUXC_GPIO_AON_01_CAN1_RX

IOMUXC_GPIO_AON_01_LPTMR1_ALT2

IOMUXC_GPIO_AON_01_GPIO1_IO01

IOMUXC_GPIO_AON_01_LPUART2_RX

IOMUXC_GPIO_AON_01_TPM1_CH00

IOMUXC_GPIO_AON_02_SRC_BOOT_MODE02

IOMUXC_GPIO_AON_02_CAN3_TX

IOMUXC_GPIO_AON_02_LPSPI2_PCS3

IOMUXC_GPIO_AON_02_LPSPI2_SDO

IOMUXC_GPIO_AON_02_LPTMR1_ALT3

IOMUXC_GPIO_AON_02_GPIO1_IO02

IOMUXC_GPIO_AON_02_LPUART2_RTS_B

IOMUXC_GPIO_AON_02_TPM1_CH01

IOMUXC_GPIO_AON_02_ECAT_CLK_ECAT_CLK25

IOMUXC_GPIO_AON_03_CAN3_RX

IOMUXC_GPIO_AON_03_LPSPI1_PCS1

IOMUXC_GPIO_AON_03_LPSPI2_SDI

IOMUXC_GPIO_AON_03_LPSPI1_PCS3

IOMUXC_GPIO_AON_03_GPIO1_IO03

IOMUXC_GPIO_AON_03_LPUART2_CTS_B

IOMUXC_GPIO_AON_03_TPM1_CH02

IOMUXC_GPIO_AON_03_ECAT_LED_STATE_RUN

IOMUXC_GPIO_AON_04_ECAT_LED_RUN

IOMUXC_GPIO_AON_04_LPSPI1_SCK

IOMUXC_GPIO_AON_04_SAI1_TX_DATA00

IOMUXC_GPIO_AON_04_SAI1_RX_DATA01

IOMUXC_GPIO_AON_04_GPIO1_IO04

IOMUXC_GPIO_AON_04_LPUART7_CTS_B

IOMUXC_GPIO_AON_04_TPM1_CH03

IOMUXC_GPIO_AON_05_LPSPI1_PCS0

IOMUXC_GPIO_AON_05_SAI1_TX_SYNC

IOMUXC_GPIO_AON_05_GPIO1_IO05

IOMUXC_GPIO_AON_05_LPUART7_RTS_B

IOMUXC_GPIO_AON_05_NMI_GLUE_NMI

IOMUXC_GPIO_AON_05_ECAT_LED_ERR

IOMUXC_GPIO_AON_06_LPSPI1_SDO

IOMUXC_GPIO_AON_06_I3C1_PUR

IOMUXC_GPIO_AON_06_SAI1_TX_BCLK

IOMUXC_GPIO_AON_06_LPI2C1_SDA

IOMUXC_GPIO_AON_06_GPIO1_IO06

IOMUXC_GPIO_AON_06_CAN1_TX

IOMUXC_GPIO_AON_06_ECAT_SDA

IOMUXC_GPIO_AON_07_ECAT_SCL

IOMUXC_GPIO_AON_07_LPSPI1_SDI

IOMUXC_GPIO_AON_07_SAI1_MCLK

IOMUXC_GPIO_AON_07_LPI2C1_SCL

IOMUXC_GPIO_AON_07_GPIO1_IO07

IOMUXC_GPIO_AON_07_CAN1_RX

IOMUXC_GPIO_AON_08_LPUART1_TX

IOMUXC_GPIO_AON_08_S400_TX

IOMUXC_GPIO_AON_08_SAI1_RX_DATA00

IOMUXC_GPIO_AON_08_SAI1_TX_DATA01

IOMUXC_GPIO_AON_08_GPIO1_IO08

IOMUXC_GPIO_AON_08_LPI2C1_SDA

IOMUXC_GPIO_AON_08_LPSPI1_PCS1

IOMUXC_GPIO_AON_08_ECAT_LINK_ACT00

IOMUXC_GPIO_AON_09_LPUART1_RX

IOMUXC_GPIO_AON_09_S400_RX

IOMUXC_GPIO_AON_09_SAI1_RX_BCLK

IOMUXC_GPIO_AON_09_LPIT1_TRIGGER00

IOMUXC_GPIO_AON_09_GPIO1_IO09

IOMUXC_GPIO_AON_09_LPI2C1_SCL

IOMUXC_GPIO_AON_09_LPSPI1_PCS2

IOMUXC_GPIO_AON_09_ECAT_LINK_ACT01

IOMUXC_GPIO_AON_10_JTAG_MUX_TRSTB

IOMUXC_GPIO_AON_10_LPSPI2_PCS0

IOMUXC_GPIO_AON_10_SAI1_RX_SYNC

IOMUXC_GPIO_AON_10_LPIT1_TRIGGER01

IOMUXC_GPIO_AON_10_TPM2_EXTCLK

IOMUXC_GPIO_AON_10_GPIO1_IO10

IOMUXC_GPIO_AON_10_LPI2C1_SCLS

IOMUXC_GPIO_AON_11_JTAG_MUX_TDO

IOMUXC_GPIO_AON_11_LPUART1_CTS_B

IOMUXC_GPIO_AON_11_LPIT1_TRIGGER02

IOMUXC_GPIO_AON_11_TPM2_CH00

IOMUXC_GPIO_AON_11_GPIO1_IO11

IOMUXC_GPIO_AON_11_LPI2C1_SDAS

IOMUXC_GPIO_AON_12_JTAG_MUX_TDI

IOMUXC_GPIO_AON_12_LPUART1_RTS_B

IOMUXC_GPIO_AON_12_LPIT1_TRIGGER03

IOMUXC_GPIO_AON_12_TPM2_CH01

IOMUXC_GPIO_AON_12_GPIO1_IO12

IOMUXC_GPIO_AON_12_LPI2C1_HREQ

IOMUXC_GPIO_AON_12_LPSPI1_SCK

IOMUXC_GPIO_AON_13_JTAG_MUX_TCK

IOMUXC_GPIO_AON_13_LPUART12_CTS_B

IOMUXC_GPIO_AON_13_LPUART1_DSR_B

IOMUXC_GPIO_AON_13_TPM2_CH02

IOMUXC_GPIO_AON_13_GPIO1_IO13

IOMUXC_GPIO_AON_13_LPTMR1_ALT1

IOMUXC_GPIO_AON_13_LPSPI1_PCS0

IOMUXC_GPIO_AON_14_JTAG_MUX_TMS

IOMUXC_GPIO_AON_14_LPUART12_RTS_B

IOMUXC_GPIO_AON_14_LPUART1_DCD_B

IOMUXC_GPIO_AON_14_TPM2_CH03

IOMUXC_GPIO_AON_14_GPIO1_IO14

IOMUXC_GPIO_AON_14_LPTMR1_ALT2

IOMUXC_GPIO_AON_14_LPSPI1_SDO

IOMUXC_GPIO_AON_15_FLEXSPI2_BUS2BIT_B_DATA03

IOMUXC_GPIO_AON_15_LPSPI2_PCS1

IOMUXC_GPIO_AON_15_LPUART12_TX

IOMUXC_GPIO_AON_15_LPUART1_RI_B

IOMUXC_GPIO_AON_15_LPI2C2_SDA

IOMUXC_GPIO_AON_15_GPIO1_IO15

IOMUXC_GPIO_AON_15_LPTMR1_ALT3

IOMUXC_GPIO_AON_15_LPSPI1_SDI

IOMUXC_GPIO_AON_15_I3C1_SDA

IOMUXC_GPIO_AON_16_FLEXSPI2_BUS2BIT_B_DATA02

IOMUXC_GPIO_AON_16_LPSPI2_PCS0

IOMUXC_GPIO_AON_16_LPUART12_RX

IOMUXC_GPIO_AON_16_LPUART1_DTR_B

IOMUXC_GPIO_AON_16_LPI2C2_SCL

IOMUXC_GPIO_AON_16_GPIO1_IO16

IOMUXC_GPIO_AON_16_CAN1_TX

IOMUXC_GPIO_AON_16_LPUART7_CTS_B

IOMUXC_GPIO_AON_16_I3C1_SCL

IOMUXC_GPIO_AON_17_FLEXSPI2_BUS2BIT_B_DATA01

IOMUXC_GPIO_AON_17_LPSPI2_SDI

IOMUXC_GPIO_AON_17_LPUART7_TX

IOMUXC_GPIO_AON_17_LPI2C2_SDA

IOMUXC_GPIO_AON_17_LPUART1_DSR_B

IOMUXC_GPIO_AON_17_GPIO1_IO17

IOMUXC_GPIO_AON_17_CAN1_RX

IOMUXC_GPIO_AON_18_FLEXSPI2_BUS2BIT_B_DATA00

IOMUXC_GPIO_AON_18_LPSPI2_SDO

IOMUXC_GPIO_AON_18_LPUART7_RX

IOMUXC_GPIO_AON_18_LPI2C2_SCL

IOMUXC_GPIO_AON_18_LPUART1_DCD_B

IOMUXC_GPIO_AON_18_GPIO1_IO18

IOMUXC_GPIO_AON_18_CAN3_TX

IOMUXC_GPIO_AON_19_FLEXSPI2_BUS2BIT_B_SCLK

IOMUXC_GPIO_AON_19_LPSPI2_SCK

IOMUXC_GPIO_AON_19_FLEXSPI2_BUS2BIT_A_SS1_B

IOMUXC_GPIO_AON_19_LPUART1_CTS_B

IOMUXC_GPIO_AON_19_GPIO1_IO19

IOMUXC_GPIO_AON_19_CAN3_RX

IOMUXC_GPIO_AON_19_LPUART7_RTS_B

IOMUXC_GPIO_AON_19_LPUART12_TX

IOMUXC_GPIO_AON_19_ADC1_CONV_D00

IOMUXC_GPIO_AON_20_FLEXSPI2_BUS2BIT_B_DQS

IOMUXC_GPIO_AON_20_FLEXSPI2_BUS2BIT_A_SS1_B

IOMUXC_GPIO_AON_20_LPI2C1_SDA

IOMUXC_GPIO_AON_20_I3C1_SDA

IOMUXC_GPIO_AON_20_LPUART1_RTS_B

IOMUXC_GPIO_AON_20_GPIO1_IO20

IOMUXC_GPIO_AON_20_LPUART12_RX

IOMUXC_GPIO_AON_20_ADC1_CONV_D01

IOMUXC_GPIO_AON_21_ADC1_CONV_D02

IOMUXC_GPIO_AON_21_FLEXSPI2_BUS2BIT_B_SS0_B

IOMUXC_GPIO_AON_21_LPSPI2_PCS1

IOMUXC_GPIO_AON_21_LPI2C1_SCL

IOMUXC_GPIO_AON_21_I3C1_SCL

IOMUXC_GPIO_AON_21_SAI1_TX_DATA00

IOMUXC_GPIO_AON_21_GPIO1_IO21

IOMUXC_GPIO_AON_21_FLEXSPI2_BUS2BIT_A_DQS

IOMUXC_GPIO_AON_21_SAI1_RX_DATA01

IOMUXC_GPIO_AON_22_CCMSRCGPC_CCMOBS1

IOMUXC_GPIO_AON_22_ADC1_CONV_D03

IOMUXC_GPIO_AON_22_FLEXSPI2_BUS2BIT_A_SS0_B

IOMUXC_GPIO_AON_22_LPI2C2_SDA

IOMUXC_GPIO_AON_22_LPUART7_TX

IOMUXC_GPIO_AON_22_LPUART12_CTS_B

IOMUXC_GPIO_AON_22_SAI1_TX_SYNC

IOMUXC_GPIO_AON_22_GPIO1_IO22

IOMUXC_GPIO_AON_22_LPSPI2_SCK

IOMUXC_GPIO_AON_23_FLEXSPI2_BUS2BIT_A_SCLK

IOMUXC_GPIO_AON_23_LPI2C2_SCL

IOMUXC_GPIO_AON_23_LPUART7_RX

IOMUXC_GPIO_AON_23_LPUART12_RTS_B

IOMUXC_GPIO_AON_23_SAI1_TX_BCLK

IOMUXC_GPIO_AON_23_GPIO1_IO23

IOMUXC_GPIO_AON_23_LPSPI2_SDO

IOMUXC_GPIO_AON_23_CCMSRCGPC_CCMOBS2

IOMUXC_GPIO_AON_23_ADC1_CONV_D04

IOMUXC_GPIO_AON_24_ADC1_CONV_D05

IOMUXC_GPIO_AON_24_FLEXSPI2_BUS2BIT_A_DATA00

IOMUXC_GPIO_AON_24_LPI2C1_SDA

IOMUXC_GPIO_AON_24_LPUART2_RTS_B

IOMUXC_GPIO_AON_24_LPUART7_CTS_B

IOMUXC_GPIO_AON_24_SAI1_MCLK

IOMUXC_GPIO_AON_24_GPIO1_IO24

IOMUXC_GPIO_AON_24_LPSPI2_SDI

IOMUXC_GPIO_AON_25_ADC1_CONV_D06

IOMUXC_GPIO_AON_25_FLEXSPI2_BUS2BIT_A_DATA01

IOMUXC_GPIO_AON_25_LPI2C1_SCL

IOMUXC_GPIO_AON_25_LPUART2_CTS_B

IOMUXC_GPIO_AON_25_LPUART7_RTS_B

IOMUXC_GPIO_AON_25_SAI1_RX_DATA00

IOMUXC_GPIO_AON_25_GPIO1_IO25

IOMUXC_GPIO_AON_25_LPSPI2_PCS0

IOMUXC_GPIO_AON_25_SAI1_TX_DATA01

IOMUXC_GPIO_AON_26_FLEXSPI2_BUS2BIT_A_DATA02

IOMUXC_GPIO_AON_26_LPSPI2_PCS2

IOMUXC_GPIO_AON_26_LPUART2_TX

IOMUXC_GPIO_AON_26_SAI1_RX_BCLK

IOMUXC_GPIO_AON_26_GPIO1_IO26

IOMUXC_GPIO_AON_26_ADC1_CONV_D07

IOMUXC_GPIO_AON_27_ADC1_CONV_RDY_CLK

IOMUXC_GPIO_AON_27_FLEXSPI2_BUS2BIT_A_DATA03

IOMUXC_GPIO_AON_27_LPSPI2_PCS3

IOMUXC_GPIO_AON_27_LPUART2_RX

IOMUXC_GPIO_AON_27_SAI1_RX_SYNC

IOMUXC_GPIO_AON_27_GPIO1_IO27

IOMUXC_GPIO_AON_27_EWM_EWM_OUT_B

IOMUXC_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_A_DQS

IOMUXC_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_B_DQS

IOMUXC_GPIO_AON_28_DUMMY_GPIO1_IO28

IOMUXC_GPR_SAIMCLK_LOWBITMASK

IOMUXC_GPR_SAIMCLK_HIGHBITMASK

static inline void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)

Sets the IOMUXC pin mux mode.

This is an example to set the PTA6 as the lpuart0_tx:

IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);

This is an example to set the PTA0 as GPIOA0:

IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);

Note

The first five parameters can be filled with the pin function ID macros.

Parameters:

• muxRegister – The pin mux register.

• muxMode – The pin mux mode.

• inputRegister – The select input register.

• inputDaisy – The input daisy.

• configRegister – The config register.

• inputOnfield – Software input on field.

static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)

Sets the IOMUXC pin configuration.

This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:

IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))

Note

The previous five parameters can be filled with the pin function ID macros.

Parameters:

• muxRegister – The pin mux register.

• muxMode – The pin mux mode.

• inputRegister – The select input register.

• inputDaisy – The input daisy.

• configRegister – The config register.

• configValue – The pin config value.

FSL_IOMUXC_DRIVER_VERSION

IOMUXC driver version 2.0.0.

FSL_COMPONENT_ID

KPP: KeyPad Port Driver

void KPP_Init(KPP_Type *base, kpp_config_t *configure)

KPP initialize. This function ungates the KPP clock and initializes KPP. This function must be called before calling any other KPP driver functions.

Parameters:

• base – KPP peripheral base address.

• configure – The KPP configuration structure pointer.

void KPP_Deinit(KPP_Type *base)

Deinitializes the KPP module and gates the clock. This function gates the KPP clock. As a result, the KPP module doesn’t work after calling this function.

Parameters:

• base – KPP peripheral base address.

static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask)

Enable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to enable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask)

Disable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to disable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline uint16_t KPP_GetStatusFlag(KPP_Type *base)

Gets the KPP interrupt event status.

Parameters:

• base – KPP peripheral base address.

Returns:

The status of the KPP. Application can use the enum type in the “kpp_interrupt_enable_t” to get the right status of the related event.

static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask)

Clears KPP status flag.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask)

Set KPP synchronization chain.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_sync_operation_t.

status_t KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)

Keypad press scanning.

This function will scanning all columns and rows. so all scanning data will be stored in the data pointer.

Parameters:

• base – KPP peripheral base address.

• data – KPP key press scanning data. The data buffer should be prepared with length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. for example the data[2] = 4, that means in column 1 row 2 has a key press event.

• clockSrc_Hz – Source clock.

Return values:

kStatus_Success – kpp press scan succeed.

FSL_KPP_DRIVER_VERSION

KPP driver version.

enum _kpp_interrupt_enable

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

Values:

enumerator kKPP_keyDepressInterrupt

Keypad depress interrupt source

enumerator kKPP_keyReleaseInterrupt

Keypad release interrupt source

enum _kpp_sync_operation

Lists of KPP synchronize chain operation.

Values:

enumerator kKPP_ClearKeyDepressSyncChain

Keypad depress interrupt status.

enumerator kKPP_SetKeyReleasesSyncChain

Keypad release interrupt status.

typedef enum _kpp_interrupt_enable kpp_interrupt_enable_t

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

typedef enum _kpp_sync_operation kpp_sync_operation_t

Lists of KPP synchronize chain operation.

typedef struct _kpp_config kpp_config_t

Lists of KPP status.

KPP_KEYPAD_COLUMNNUM_MAX

KPP_KEYPAD_ROWNUM_MAX

struct _kpp_config

#include <fsl_kpp.h>

Lists of KPP status.

Public Members

uint8_t activeRow

The row number: bit 7 ~ 0 represents the row 7 ~ 0.

uint8_t activeColumn

The column number: bit 7 ~ 0 represents the column 7 ~ 0.

uint16_t interrupt

KPP interrupt source. A logical OR of “kpp_interrupt_enable_t”.

Common Driver

FSL_COMMON_DRIVER_VERSION

common driver version.

DEBUG_CONSOLE_DEVICE_TYPE_NONE

No debug console.

DEBUG_CONSOLE_DEVICE_TYPE_UART

Debug console based on UART.

DEBUG_CONSOLE_DEVICE_TYPE_LPUART

Debug console based on LPUART.

DEBUG_CONSOLE_DEVICE_TYPE_LPSCI

Debug console based on LPSCI.

DEBUG_CONSOLE_DEVICE_TYPE_USBCDC

Debug console based on USBCDC.

DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM

Debug console based on FLEXCOMM.

DEBUG_CONSOLE_DEVICE_TYPE_IUART

Debug console based on i.MX UART.

DEBUG_CONSOLE_DEVICE_TYPE_VUSART

Debug console based on LPC_VUSART.

DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART

Debug console based on LPC_USART.

DEBUG_CONSOLE_DEVICE_TYPE_SWO

Debug console based on SWO.

DEBUG_CONSOLE_DEVICE_TYPE_QSCI

Debug console based on QSCI.

MIN(a, b)

Computes the minimum of a and b.

MAX(a, b)

Computes the maximum of a and b.

UINT16_MAX

Max value of uint16_t type.

UINT32_MAX

Max value of uint32_t type.

SDK_ATOMIC_LOCAL_ADD(addr, val)

Add value val from the variable at address address.

SDK_ATOMIC_LOCAL_SUB(addr, val)

Subtract value val to the variable at address address.

SDK_ATOMIC_LOCAL_SET(addr, bits)

Set the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR(addr, bits)

Clear the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)

Toggle the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)

For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.

SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)

For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .

SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)

For the variable at address address, set as newValue value and return old value.

USEC_TO_COUNT(us, clockFreqInHz)

Macro to convert a microsecond period to raw count value

COUNT_TO_USEC(count, clockFreqInHz)

Macro to convert a raw count value to microsecond

MSEC_TO_COUNT(ms, clockFreqInHz)

Macro to convert a millisecond period to raw count value

COUNT_TO_MSEC(count, clockFreqInHz)

Macro to convert a raw count value to millisecond

SDK_ISR_EXIT_BARRIER

SDK_ALIGN(var, alignbytes)

Macro to define a variable with alignbytes alignment

SDK_L1DCACHE_ALIGN(var)

Macro to define a variable with L1 d-cache line size alignment

SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L2 cache line size alignment

Macro to change a value to a given size aligned value

AT_NONCACHEABLE_SECTION(var)

Define a variable var, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)

Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_NONCACHEABLE_SECTION_INIT(var)

Define a variable var with initial value, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)

Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

MCUX_CS

AT_CACHE_LINE_SECTION(var)

Define a variable var, which is cache line size aligned and be placed in CacheLineData section.

AT_CACHE_LINE_SECTION_INIT(var)

Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section.

CACHE_LINE_DATA

AT_QUICKACCESS_SECTION_CODE(func)

Place function in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA(var)

Place data in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)

Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes.

RAMFUNCTION_SECTION_CODE(func)

Place function in ram.

enum _status_groups

Status group numbers.

Values:

enumerator kStatusGroup_Generic

Group number for generic status codes.

enumerator kStatusGroup_FLASH

Group number for FLASH status codes.

enumerator kStatusGroup_LPSPI

Group number for LPSPI status codes.

enumerator kStatusGroup_FLEXIO_SPI

Group number for FLEXIO SPI status codes.

enumerator kStatusGroup_DSPI

Group number for DSPI status codes.

enumerator kStatusGroup_FLEXIO_UART

Group number for FLEXIO UART status codes.

enumerator kStatusGroup_FLEXIO_I2C

Group number for FLEXIO I2C status codes.

enumerator kStatusGroup_LPI2C

Group number for LPI2C status codes.

enumerator kStatusGroup_UART

Group number for UART status codes.

enumerator kStatusGroup_I2C

Group number for UART status codes.

enumerator kStatusGroup_LPSCI

Group number for LPSCI status codes.

enumerator kStatusGroup_LPUART

Group number for LPUART status codes.

enumerator kStatusGroup_SPI

Group number for SPI status code.

enumerator kStatusGroup_XRDC

Group number for XRDC status code.

enumerator kStatusGroup_SEMA42

Group number for SEMA42 status code.

enumerator kStatusGroup_SDHC

Group number for SDHC status code

enumerator kStatusGroup_SDMMC

Group number for SDMMC status code

enumerator kStatusGroup_SAI

Group number for SAI status code

enumerator kStatusGroup_MCG

Group number for MCG status codes.

enumerator kStatusGroup_SCG

Group number for SCG status codes.

enumerator kStatusGroup_SDSPI

Group number for SDSPI status codes.

enumerator kStatusGroup_FLEXIO_I2S

Group number for FLEXIO I2S status codes

enumerator kStatusGroup_FLEXIO_MCULCD

Group number for FLEXIO LCD status codes

enumerator kStatusGroup_FLASHIAP

Group number for FLASHIAP status codes

enumerator kStatusGroup_FLEXCOMM_I2C

Group number for FLEXCOMM I2C status codes

enumerator kStatusGroup_I2S

Group number for I2S status codes

enumerator kStatusGroup_IUART

Group number for IUART status codes

enumerator kStatusGroup_CSI

Group number for CSI status codes

enumerator kStatusGroup_MIPI_DSI

Group number for MIPI DSI status codes

enumerator kStatusGroup_SDRAMC

Group number for SDRAMC status codes.

enumerator kStatusGroup_POWER

Group number for POWER status codes.

enumerator kStatusGroup_ENET

Group number for ENET status codes.

enumerator kStatusGroup_PHY

Group number for PHY status codes.

enumerator kStatusGroup_TRGMUX

Group number for TRGMUX status codes.

enumerator kStatusGroup_SMARTCARD

Group number for SMARTCARD status codes.

enumerator kStatusGroup_LMEM

Group number for LMEM status codes.

enumerator kStatusGroup_QSPI

Group number for QSPI status codes.

enumerator kStatusGroup_DMA

Group number for DMA status codes.

enumerator kStatusGroup_EDMA

Group number for EDMA status codes.

enumerator kStatusGroup_DMAMGR

Group number for DMAMGR status codes.

enumerator kStatusGroup_FLEXCAN

Group number for FlexCAN status codes.

enumerator kStatusGroup_LTC

Group number for LTC status codes.

enumerator kStatusGroup_FLEXIO_CAMERA

Group number for FLEXIO CAMERA status codes.

enumerator kStatusGroup_LPC_SPI

Group number for LPC_SPI status codes.

enumerator kStatusGroup_LPC_USART

Group number for LPC_USART status codes.

enumerator kStatusGroup_DMIC

Group number for DMIC status codes.

enumerator kStatusGroup_SDIF

Group number for SDIF status codes.

enumerator kStatusGroup_SPIFI

Group number for SPIFI status codes.

enumerator kStatusGroup_OTP

Group number for OTP status codes.

enumerator kStatusGroup_MCAN

Group number for MCAN status codes.

enumerator kStatusGroup_CAAM

Group number for CAAM status codes.

enumerator kStatusGroup_ECSPI

Group number for ECSPI status codes.

enumerator kStatusGroup_USDHC

Group number for USDHC status codes.

enumerator kStatusGroup_LPC_I2C

Group number for LPC_I2C status codes.

enumerator kStatusGroup_DCP

Group number for DCP status codes.

enumerator kStatusGroup_MSCAN

Group number for MSCAN status codes.

enumerator kStatusGroup_ESAI

Group number for ESAI status codes.

enumerator kStatusGroup_FLEXSPI

Group number for FLEXSPI status codes.

enumerator kStatusGroup_MMDC

Group number for MMDC status codes.

enumerator kStatusGroup_PDM

Group number for MIC status codes.

enumerator kStatusGroup_SDMA

Group number for SDMA status codes.

enumerator kStatusGroup_ICS

Group number for ICS status codes.

enumerator kStatusGroup_SPDIF

Group number for SPDIF status codes.

enumerator kStatusGroup_LPC_MINISPI

Group number for LPC_MINISPI status codes.

enumerator kStatusGroup_HASHCRYPT

Group number for Hashcrypt status codes

enumerator kStatusGroup_LPC_SPI_SSP

Group number for LPC_SPI_SSP status codes.

enumerator kStatusGroup_I3C

Group number for I3C status codes

enumerator kStatusGroup_LPC_I2C_1

Group number for LPC_I2C_1 status codes.

enumerator kStatusGroup_NOTIFIER

Group number for NOTIFIER status codes.

enumerator kStatusGroup_DebugConsole

Group number for debug console status codes.

enumerator kStatusGroup_SEMC

Group number for SEMC status codes.

enumerator kStatusGroup_ApplicationRangeStart

Starting number for application groups.

enumerator kStatusGroup_IAP

Group number for IAP status codes

enumerator kStatusGroup_SFA

Group number for SFA status codes

enumerator kStatusGroup_SPC

Group number for SPC status codes.

enumerator kStatusGroup_PUF

Group number for PUF status codes.

enumerator kStatusGroup_TOUCH_PANEL

Group number for touch panel status codes

enumerator kStatusGroup_VBAT

Group number for VBAT status codes

enumerator kStatusGroup_XSPI

Group number for XSPI status codes

enumerator kStatusGroup_PNGDEC

Group number for PNGDEC status codes

enumerator kStatusGroup_JPEGDEC

Group number for JPEGDEC status codes

enumerator kStatusGroup_AUDMIX

Group number for AUDMIX status codes

enumerator kStatusGroup_HAL_GPIO

Group number for HAL GPIO status codes.

enumerator kStatusGroup_HAL_UART

Group number for HAL UART status codes.

enumerator kStatusGroup_HAL_TIMER

Group number for HAL TIMER status codes.

enumerator kStatusGroup_HAL_SPI

Group number for HAL SPI status codes.

enumerator kStatusGroup_HAL_I2C

Group number for HAL I2C status codes.

enumerator kStatusGroup_HAL_FLASH

Group number for HAL FLASH status codes.

enumerator kStatusGroup_HAL_PWM

Group number for HAL PWM status codes.

enumerator kStatusGroup_HAL_RNG

Group number for HAL RNG status codes.

enumerator kStatusGroup_HAL_I2S

Group number for HAL I2S status codes.

enumerator kStatusGroup_HAL_ADC_SENSOR

Group number for HAL ADC SENSOR status codes.

enumerator kStatusGroup_TIMERMANAGER

Group number for TiMER MANAGER status codes.

enumerator kStatusGroup_SERIALMANAGER

Group number for SERIAL MANAGER status codes.

enumerator kStatusGroup_LED

Group number for LED status codes.

enumerator kStatusGroup_BUTTON

Group number for BUTTON status codes.

enumerator kStatusGroup_EXTERN_EEPROM

Group number for EXTERN EEPROM status codes.

enumerator kStatusGroup_SHELL

Group number for SHELL status codes.

enumerator kStatusGroup_MEM_MANAGER

Group number for MEM MANAGER status codes.

enumerator kStatusGroup_LIST

Group number for List status codes.

enumerator kStatusGroup_OSA

Group number for OSA status codes.

enumerator kStatusGroup_COMMON_TASK

Group number for Common task status codes.

enumerator kStatusGroup_MSG

Group number for messaging status codes.

enumerator kStatusGroup_SDK_OCOTP

Group number for OCOTP status codes.

enumerator kStatusGroup_SDK_FLEXSPINOR

Group number for FLEXSPINOR status codes.

enumerator kStatusGroup_CODEC

Group number for codec status codes.

enumerator kStatusGroup_ASRC

Group number for codec status ASRC.

enumerator kStatusGroup_OTFAD

Group number for codec status codes.

enumerator kStatusGroup_SDIOSLV

Group number for SDIOSLV status codes.

enumerator kStatusGroup_MECC

Group number for MECC status codes.

enumerator kStatusGroup_ENET_QOS

Group number for ENET_QOS status codes.

enumerator kStatusGroup_LOG

Group number for LOG status codes.

enumerator kStatusGroup_I3CBUS

Group number for I3CBUS status codes.

enumerator kStatusGroup_QSCI

Group number for QSCI status codes.

enumerator kStatusGroup_ELEMU

Group number for ELEMU status codes.

enumerator kStatusGroup_QUEUEDSPI

Group number for QSPI status codes.

enumerator kStatusGroup_POWER_MANAGER

Group number for POWER_MANAGER status codes.

enumerator kStatusGroup_IPED

Group number for IPED status codes.

enumerator kStatusGroup_ELS_PKC

Group number for ELS PKC status codes.

enumerator kStatusGroup_CSS_PKC

Group number for CSS PKC status codes.

enumerator kStatusGroup_HOSTIF

Group number for HOSTIF status codes.

enumerator kStatusGroup_CLIF

Group number for CLIF status codes.

enumerator kStatusGroup_BMA

Group number for BMA status codes.

enumerator kStatusGroup_NETC

Group number for NETC status codes.

enumerator kStatusGroup_ELE

Group number for ELE status codes.

enumerator kStatusGroup_GLIKEY

Group number for GLIKEY status codes.

enumerator kStatusGroup_AON_POWER

Group number for AON_POWER status codes.

enumerator kStatusGroup_AON_COMMON

Group number for AON_COMMON status codes.

enumerator kStatusGroup_ENDAT3

Group number for ENDAT3 status codes.

enumerator kStatusGroup_HIPERFACE

Group number for HIPERFACE status codes.

enumerator kStatusGroup_NPX

Group number for NPX status codes.

enumerator kStatusGroup_ELA_CSEC

Group number for ELA_CSEC status codes.

enumerator kStatusGroup_FLEXIO_T_FORMAT

Group number for T-format status codes.

enumerator kStatusGroup_FLEXIO_A_FORMAT

Group number for A-format status codes.

Generic status return codes.

Values:

enumerator kStatus_Success

Generic status for Success.

enumerator kStatus_Fail

Generic status for Fail.

enumerator kStatus_ReadOnly

Generic status for read only failure.

enumerator kStatus_OutOfRange

Generic status for out of range access.

enumerator kStatus_InvalidArgument

Generic status for invalid argument check.

enumerator kStatus_Timeout

Generic status for timeout.

enumerator kStatus_NoTransferInProgress

Generic status for no transfer in progress.

enumerator kStatus_Busy

Generic status for module is busy.

enumerator kStatus_NoData

Generic status for no data is found for the operation.

typedef int32_t status_t

Type used for all status and error return values.

void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size.

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters:

• size – The length required to malloc.

• alignbytes – The alignment size.

Return values:

The – allocated memory.

void SDK_Free(void *ptr)

Free memory.

Parameters:

• ptr – The memory to be release.

void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters:

• delayTime_us – Delay time in unit of microsecond.

• coreClock_Hz – Core clock frequency with Hz.

static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt.

Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt enabled successfully

• kStatus_Fail – Failed to enable the interrupt

static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt.

Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt disabled successfully

• kStatus_Fail – Failed to disable the interrupt

static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to Enable.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to set.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The flag which IRQ to clear.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ.

Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:

Current primask value.

static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ.

Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

• primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().

static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)

static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)

FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ

Macro to use the default weak IRQ handler in drivers.

MAKE_STATUS(group, code)

Construct a status code value from a group and code number.

MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers.

The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).

| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0

ARRAY_SIZE(x)

Computes the number of elements in an array.

UINT64_H(X)

Macro to get upper 32 bits of a 64-bit value

UINT64_L(X)

Macro to get lower 32 bits of a 64-bit value

SUPPRESS_FALL_THROUGH_WARNING()

For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.

MSDK_REG_SECURE_ADDR(x)

Convert the register address to the one used in secure mode.

MSDK_REG_NONSECURE_ADDR(x)

Convert the register address to the one used in non-secure mode.

MSDK_HAS_DWT_CYCCNT

The chip supports DWT CYCCNT or not.

MSDK_INVALID_IRQ_HANDLER

Invalid IRQ handler address.

Lin_lpuart_driver

FSL_LIN_LPUART_DRIVER_VERSION

LIN LPUART driver version.

enum _lin_lpuart_stop_bit_count

Values:

enumerator kLPUART_OneStopBit

One stop bit

enumerator kLPUART_TwoStopBit

Two stop bits

enum _lin_lpuart_flags

Values:

enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty

enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete

enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full

enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected

enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register

enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets

enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected

enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection

enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled

enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected

enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start bit

enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1

enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2

enumerator kLPUART_NoiseErrorInRxDataRegFlag

NOISY bit, sets if noise detected in current data word

enumerator kLPUART_ParityErrorInRxDataRegFlag

PARITY bit, sets if noise detected in current data word

enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty

enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty

enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred

enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred

enum _lin_lpuart_interrupt_enable

Values:

enumerator kLPUART_LinBreakInterruptEnable

LIN break detect.

enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge.

enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty.

enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete.

enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full.

enumerator kLPUART_IdleLineInterruptEnable

Idle line.

enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun.

enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag.

enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag.

enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag.

enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow.

enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow.

enum _lin_lpuart_status

Values:

enumerator kStatus_LPUART_TxBusy

TX busy

enumerator kStatus_LPUART_RxBusy

RX busy

enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle.

enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle.

enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large

enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large

enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear

enumerator kStatus_LPUART_Error

Error happens on LPUART.

enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun.

enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun.

enumerator kStatus_LPUART_NoiseError

LPUART noise error.

enumerator kStatus_LPUART_FramingError

LPUART framing error.

enumerator kStatus_LPUART_ParityError

LPUART parity error.

enum lin_lpuart_bit_count_per_char_t

Values:

enumerator LPUART_8_BITS_PER_CHAR

8-bit data characters

enumerator LPUART_9_BITS_PER_CHAR

9-bit data characters

enumerator LPUART_10_BITS_PER_CHAR

10-bit data characters

typedef enum _lin_lpuart_stop_bit_count lin_lpuart_stop_bit_count_t

static inline bool LIN_LPUART_GetRxDataPolarity(const LPUART_Type *base)

static inline void LIN_LPUART_SetRxDataPolarity(LPUART_Type *base, bool polarity)

static inline void LIN_LPUART_WriteByte(LPUART_Type *base, uint8_t data)

static inline void LIN_LPUART_ReadByte(const LPUART_Type *base, uint8_t *readData)

status_t LIN_LPUART_CalculateBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *osr, uint16_t *sbr)

Calculates the best osr and sbr value for configured baudrate.

Parameters:

• base – LPUART peripheral base address

• baudRate_Bps – user configuration structure of type #lin_user_config_t

• srcClock_Hz – pointer to the LIN_LPUART driver state structure

• osr – pointer to osr value

• sbr – pointer to sbr value

Returns:

An error code or lin_status_t

void LIN_LPUART_SetBaudRate(LPUART_Type *base, uint32_t *osr, uint16_t *sbr)

Configure baudrate according to osr and sbr value.

Parameters:

• base – LPUART peripheral base address

• osr – pointer to osr value

• sbr – pointer to sbr value

lin_status_t LIN_LPUART_Init(LPUART_Type *base, lin_user_config_t *linUserConfig, lin_state_t *linCurrentState, uint32_t linSourceClockFreq)

Initializes an LIN_LPUART instance for LIN Network.

The caller provides memory for the driver state structures during initialization. The user must select the LIN_LPUART clock source in the application to initialize the LIN_LPUART. This function initializes a LPUART instance for operation. This function will initialize the run-time state structure to keep track of the on-going transfers, initialize the module to user defined settings and default settings, set break field length to be 13 bit times minimum, enable the break detect interrupt, Rx complete interrupt, frame error detect interrupt, and enable the LPUART module transmitter and receiver

Parameters:

• base – LPUART peripheral base address

• linUserConfig – user configuration structure of type #lin_user_config_t

• linCurrentState – pointer to the LIN_LPUART driver state structure

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_Deinit(LPUART_Type *base)

Shuts down the LIN_LPUART by disabling interrupts and transmitter/receiver.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_SendFrameDataBlocking(LPUART_Type *base, const uint8_t *txBuff, uint8_t txSize, uint32_t timeoutMSec)

Sends Frame data out through the LIN_LPUART module using blocking method. This function will calculate the checksum byte and send it with the frame data. Blocking means that the function does not return until the transmission is complete.

Parameters:

• base – LPUART peripheral base address

• txBuff – source buffer containing 8-bit data chars to send

• txSize – the number of bytes to send

• timeoutMSec – timeout value in milli seconds

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_SendFrameData(LPUART_Type *base, const uint8_t *txBuff, uint8_t txSize)

Sends frame data out through the LIN_LPUART module using non-blocking method. This enables an a-sync method for transmitting data. Non-blocking means that the function returns immediately. The application has to get the transmit status to know when the transmit is complete. This function will calculate the checksum byte and send it with the frame data.

Parameters:

• base – LPUART peripheral base address

• txBuff – source buffer containing 8-bit data chars to send

• txSize – the number of bytes to send

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_GetTransmitStatus(LPUART_Type *base, uint8_t *bytesRemaining)

Get status of an on-going non-blocking transmission While sending frame data using non-blocking method, users can use this function to get status of that transmission. This function return LIN_TX_BUSY while sending, or LIN_TIMEOUT if timeout has occurred, or return LIN_SUCCESS when the transmission is complete. The bytesRemaining shows number of bytes that still needed to transmit.

Parameters:

• base – LPUART peripheral base address

• bytesRemaining – Number of bytes still needed to transmit

Returns:

lin_status_t LIN_TX_BUSY, LIN_SUCCESS or LIN_TIMEOUT

lin_status_t LIN_LPUART_RecvFrmDataBlocking(LPUART_Type *base, uint8_t *rxBuff, uint8_t rxSize, uint32_t timeoutMSec)

Receives frame data through the LIN_LPUART module using blocking method. This function will check the checksum byte. If the checksum is correct, it will receive the frame data. Blocking means that the function does not return until the reception is complete.

Parameters:

• base – LPUART peripheral base address

• rxBuff – buffer containing 8-bit received data

• rxSize – the number of bytes to receive

• timeoutMSec – timeout value in milli seconds

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_RecvFrmData(LPUART_Type *base, uint8_t *rxBuff, uint8_t rxSize)

Receives frame data through the LIN_LPUART module using non-blocking method. This function will check the checksum byte. If the checksum is correct, it will receive it with the frame data. Non-blocking means that the function returns immediately. The application has to get the receive status to know when the reception is complete.

Parameters:

• base – LPUART peripheral base address

• rxBuff – buffer containing 8-bit received data

• rxSize – the number of bytes to receive

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_AbortTransferData(LPUART_Type *base)

Aborts an on-going non-blocking transmission/reception. While performing a non-blocking transferring data, users can call this function to terminate immediately the transferring.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_GetReceiveStatus(LPUART_Type *base, uint8_t *bytesRemaining)

Get status of an on-going non-blocking reception While receiving frame data using non-blocking method, users can use this function to get status of that receiving. This function return the current event ID, LIN_RX_BUSY while receiving and return LIN_SUCCESS, or timeout (LIN_TIMEOUT) when the reception is complete. The bytesRemaining shows number of bytes that still needed to receive.

Parameters:

• base – LPUART peripheral base address

• bytesRemaining – Number of bytes still needed to receive

Returns:

lin_status_t LIN_RX_BUSY, LIN_TIMEOUT or LIN_SUCCESS

lin_status_t LIN_LPUART_GoToSleepMode(LPUART_Type *base)

This function puts current node to sleep mode This function changes current node state to LIN_NODE_STATE_SLEEP_MODE.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_GotoIdleState(LPUART_Type *base)

Puts current LIN node to Idle state This function changes current node state to LIN_NODE_STATE_IDLE.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_SendWakeupSignal(LPUART_Type *base)

Sends a wakeup signal through the LIN_LPUART interface.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_MasterSendHeader(LPUART_Type *base, uint8_t id)

Sends frame header out through the LIN_LPUART module using a non-blocking method. This function sends LIN Break field, sync field then the ID with correct parity.

Parameters:

• base – LPUART peripheral base address

• id – Frame Identifier

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_EnableIRQ(LPUART_Type *base)

Enables LIN_LPUART hardware interrupts.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_DisableIRQ(LPUART_Type *base)

Disables LIN_LPUART hardware interrupts.

Parameters:

• base – LPUART peripheral base address

Returns:

An error code or lin_status_t

lin_status_t LIN_LPUART_AutoBaudCapture(uint32_t instance)

This function capture bits time to detect break char, calculate baudrate from sync bits and enable transceiver if autobaud successful. This function should only be used in Slave. The timer should be in mode input capture of both rising and falling edges. The timer input capture pin should be externally connected to RXD pin.

Parameters:

• instance – LPUART instance

Returns:

lin_status_t

void LIN_LPUART_IRQHandler(LPUART_Type *base)

LIN_LPUART RX TX interrupt handler.

Parameters:

• base – LPUART peripheral base address

Returns:

void

LIN_LPUART_TRANSMISSION_COMPLETE_TIMEOUT

Max loops to wait for LPUART transmission complete.

When de-initializing the LIN LPUART module, the program shall wait for the previous transmission to complete. This parameter defines how many loops to check completion before return error. If defined as 0, driver will wait forever until completion.

AUTOBAUD_BAUDRATE_TOLERANCE

BIT_RATE_TOLERANCE_UNSYNC

BIT_DURATION_MAX_19200

BIT_DURATION_MIN_19200

BIT_DURATION_MAX_14400

BIT_DURATION_MIN_14400

BIT_DURATION_MAX_9600

BIT_DURATION_MIN_9600

BIT_DURATION_MAX_4800

BIT_DURATION_MIN_4800

BIT_DURATION_MAX_2400

BIT_DURATION_MIN_2400

TWO_BIT_DURATION_MAX_19200

TWO_BIT_DURATION_MIN_19200

TWO_BIT_DURATION_MAX_14400

TWO_BIT_DURATION_MIN_14400

TWO_BIT_DURATION_MAX_9600

TWO_BIT_DURATION_MIN_9600

TWO_BIT_DURATION_MAX_4800

TWO_BIT_DURATION_MIN_4800

TWO_BIT_DURATION_MAX_2400

TWO_BIT_DURATION_MIN_2400

AUTOBAUD_BREAK_TIME_MIN

LPADC: 12-bit SAR Analog-to-Digital Converter Driver

enum _lpadc_status_flags

Define hardware flags of the module.

Values:

enumerator kLPADC_ResultFIFO0OverflowFlag

Indicates that more data has been written to the Result FIFO 0 than it can hold.

enumerator kLPADC_ResultFIFO0ReadyFlag

Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level.

enumerator kLPADC_TriggerExceptionFlag

Indicates that a trigger exception event has occurred.

enumerator kLPADC_TriggerCompletionFlag

Indicates that a trigger completion event has occurred.

enumerator kLPADC_CalibrationReadyFlag

Indicates that the calibration process is done.

enumerator kLPADC_ActiveFlag

Indicates that the ADC is in active state.

enumerator kLPADC_ResultFIFOOverflowFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowFlag as instead.

enumerator kLPADC_ResultFIFOReadyFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0ReadyFlag as instead.

enum _lpadc_interrupt_enable

Define interrupt switchers of the module.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_ResultFIFO0OverflowInterruptEnable

Configures ADC to generate overflow interrupt requests when FOF0 flag is asserted.

enumerator kLPADC_FIFO0WatermarkInterruptEnable

Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted.

enumerator kLPADC_ResultFIFOOverflowInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowInterruptEnable as instead.

enumerator kLPADC_FIFOWatermarkInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_FIFO0WatermarkInterruptEnable as instead.

enumerator kLPADC_TriggerExceptionInterruptEnable

Configures ADC to generate trigger exception interrupt.

enumerator kLPADC_Trigger0CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 0 completion.

enumerator kLPADC_Trigger1CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 1 completion.

enumerator kLPADC_Trigger2CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 2 completion.

enumerator kLPADC_Trigger3CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 3 completion.

enumerator kLPADC_Trigger4CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 4 completion.

enumerator kLPADC_Trigger5CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 5 completion.

enumerator kLPADC_Trigger6CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 6 completion.

enumerator kLPADC_Trigger7CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 7 completion.

enumerator kLPADC_Trigger8CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 8 completion.

enumerator kLPADC_Trigger9CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 9 completion.

enumerator kLPADC_Trigger10CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 10 completion.

enumerator kLPADC_Trigger11CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 11 completion.

enumerator kLPADC_Trigger12CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 12 completion.

enumerator kLPADC_Trigger13CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 13 completion.

enumerator kLPADC_Trigger14CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 14 completion.

enumerator kLPADC_Trigger15CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 15 completion.

enum _lpadc_trigger_status_flags

The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_Trigger0InterruptedFlag

Trigger 0 is interrupted by a high priority exception.

enumerator kLPADC_Trigger1InterruptedFlag

Trigger 1 is interrupted by a high priority exception.

enumerator kLPADC_Trigger2InterruptedFlag

Trigger 2 is interrupted by a high priority exception.

enumerator kLPADC_Trigger3InterruptedFlag

Trigger 3 is interrupted by a high priority exception.

enumerator kLPADC_Trigger4InterruptedFlag

Trigger 4 is interrupted by a high priority exception.

enumerator kLPADC_Trigger5InterruptedFlag

Trigger 5 is interrupted by a high priority exception.

enumerator kLPADC_Trigger6InterruptedFlag

Trigger 6 is interrupted by a high priority exception.

enumerator kLPADC_Trigger7InterruptedFlag

Trigger 7 is interrupted by a high priority exception.

enumerator kLPADC_Trigger8InterruptedFlag

Trigger 8 is interrupted by a high priority exception.

enumerator kLPADC_Trigger9InterruptedFlag

Trigger 9 is interrupted by a high priority exception.

enumerator kLPADC_Trigger10InterruptedFlag

Trigger 10 is interrupted by a high priority exception.

enumerator kLPADC_Trigger11InterruptedFlag

Trigger 11 is interrupted by a high priority exception.

enumerator kLPADC_Trigger12InterruptedFlag

Trigger 12 is interrupted by a high priority exception.

enumerator kLPADC_Trigger13InterruptedFlag

Trigger 13 is interrupted by a high priority exception.

enumerator kLPADC_Trigger14InterruptedFlag

Trigger 14 is interrupted by a high priority exception.

enumerator kLPADC_Trigger15InterruptedFlag

Trigger 15 is interrupted by a high priority exception.

enumerator kLPADC_Trigger0CompletedFlag

Trigger 0 is completed and trigger 0 has enabled completion interrupts.

enumerator kLPADC_Trigger1CompletedFlag

Trigger 1 is completed and trigger 1 has enabled completion interrupts.

enumerator kLPADC_Trigger2CompletedFlag

Trigger 2 is completed and trigger 2 has enabled completion interrupts.

enumerator kLPADC_Trigger3CompletedFlag

Trigger 3 is completed and trigger 3 has enabled completion interrupts.

enumerator kLPADC_Trigger4CompletedFlag

Trigger 4 is completed and trigger 4 has enabled completion interrupts.

enumerator kLPADC_Trigger5CompletedFlag

Trigger 5 is completed and trigger 5 has enabled completion interrupts.

enumerator kLPADC_Trigger6CompletedFlag

Trigger 6 is completed and trigger 6 has enabled completion interrupts.

enumerator kLPADC_Trigger7CompletedFlag

Trigger 7 is completed and trigger 7 has enabled completion interrupts.

enumerator kLPADC_Trigger8CompletedFlag

Trigger 8 is completed and trigger 8 has enabled completion interrupts.

enumerator kLPADC_Trigger9CompletedFlag

Trigger 9 is completed and trigger 9 has enabled completion interrupts.

enumerator kLPADC_Trigger10CompletedFlag

Trigger 10 is completed and trigger 10 has enabled completion interrupts.

enumerator kLPADC_Trigger11CompletedFlag

Trigger 11 is completed and trigger 11 has enabled completion interrupts.

enumerator kLPADC_Trigger12CompletedFlag

Trigger 12 is completed and trigger 12 has enabled completion interrupts.

enumerator kLPADC_Trigger13CompletedFlag

Trigger 13 is completed and trigger 13 has enabled completion interrupts.

enumerator kLPADC_Trigger14CompletedFlag

Trigger 14 is completed and trigger 14 has enabled completion interrupts.

enumerator kLPADC_Trigger15CompletedFlag

Trigger 15 is completed and trigger 15 has enabled completion interrupts.

enum _lpadc_sample_scale_mode

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

Values:

enumerator kLPADC_SamplePartScale

Use divided input voltage signal. (For scale select,please refer to the reference manual).

enumerator kLPADC_SampleFullScale

Full scale (Factor of 1).

enum _lpadc_sample_channel_mode

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

Values:

enumerator kLPADC_SampleChannelSingleEndSideA

Single-end mode, only A-side channel is converted.

enumerator kLPADC_SampleChannelSingleEndSideB

Single-end mode, only B-side channel is converted.

enumerator kLPADC_SampleChannelDiffBothSideAB

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDiffBothSideBA

Differential mode, the ADC result is (CHnB-CHnA).

enumerator kLPADC_SampleChannelDiffBothSide

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDualSingleEndBothSide

Dual-Single-Ended Mode. Both A side and B side channels are converted independently.

enum _lpadc_hardware_average_mode

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

Values:

enumerator kLPADC_HardwareAverageCount1

Single conversion.

enumerator kLPADC_HardwareAverageCount2

2 conversions averaged.

enumerator kLPADC_HardwareAverageCount4

4 conversions averaged.

enumerator kLPADC_HardwareAverageCount8

8 conversions averaged.

enumerator kLPADC_HardwareAverageCount16

16 conversions averaged.

enumerator kLPADC_HardwareAverageCount32

32 conversions averaged.

enumerator kLPADC_HardwareAverageCount64

64 conversions averaged.

enumerator kLPADC_HardwareAverageCount128

128 conversions averaged.

enum _lpadc_sample_time_mode

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

Values:

enumerator kLPADC_SampleTimeADCK3

3 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK5

5 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK7

7 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK11

11 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK19

19 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK35

35 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK67

69 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK131

131 ADCK cycles total sample time.

enum _lpadc_hardware_compare_mode

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

Values:

enumerator kLPADC_HardwareCompareDisabled

Compare disabled.

enumerator kLPADC_HardwareCompareStoreOnTrue

Compare enabled. Store on true.

enumerator kLPADC_HardwareCompareRepeatUntilTrue

Compare enabled. Repeat channel acquisition until true.

enum _lpadc_conversion_resolution_mode

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

Values:

enumerator kLPADC_ConversionResolutionStandard

Standard resolution. Single-ended 12-bit conversion, Differential 13-bit conversion with 2’s complement output.

enumerator kLPADC_ConversionResolutionHigh

High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2’s complement output.

enum _lpadc_conversion_average_mode

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

Values:

enumerator kLPADC_ConversionAverage1

Single conversion.

enumerator kLPADC_ConversionAverage2

2 conversions averaged.

enumerator kLPADC_ConversionAverage4

4 conversions averaged.

enumerator kLPADC_ConversionAverage8

8 conversions averaged.

enumerator kLPADC_ConversionAverage16

16 conversions averaged.

enumerator kLPADC_ConversionAverage32

32 conversions averaged.

enumerator kLPADC_ConversionAverage64

64 conversions averaged.

enumerator kLPADC_ConversionAverage128

128 conversions averaged.

enumerator kLPADC_ConversionAverageMax

enum _lpadc_reference_voltage_mode

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

Values:

enumerator kLPADC_ReferenceVoltageAlt1

Option 1 setting.

enumerator kLPADC_ReferenceVoltageAlt2

Option 2 setting.

enumerator kLPADC_ReferenceVoltageAlt3

Option 3 setting.

enum _lpadc_power_level_mode

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

Values:

enumerator kLPADC_PowerLevelAlt1

Lowest power setting.

enumerator kLPADC_PowerLevelAlt2

Next lowest power setting.

enumerator kLPADC_PowerLevelAlt3

…

enumerator kLPADC_PowerLevelAlt4

Highest power setting.

enum _lpadc_offset_calibration_mode

Define enumeration of offset calibration mode.

Values:

enumerator kLPADC_OffsetCalibration12bitMode

12 bit offset calibration mode.

enumerator kLPADC_OffsetCalibration16bitMode

16 bit offset calibration mode.

enum _lpadc_trigger_priority_policy

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

Values:

enumerator kLPADC_ConvPreemptImmediatelyNotAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion is not automatically resumed or restarted.

enumerator kLPADC_ConvPreemptSoftlyNotAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion is not resumed or restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoRestarted

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptSoftlyAutoRestarted

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be resumed.

enumerator kLPADC_ConvPreemptSoftlyAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will be automatically be resumed.

enumerator kLPADC_TriggerPriorityPreemptImmediately

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityPreemptSoftly

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityExceptionDisabled

High priority trigger exception disabled.

typedef enum _lpadc_sample_scale_mode lpadc_sample_scale_mode_t

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

typedef enum _lpadc_sample_channel_mode lpadc_sample_channel_mode_t

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

typedef enum _lpadc_hardware_average_mode lpadc_hardware_average_mode_t

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

typedef enum _lpadc_sample_time_mode lpadc_sample_time_mode_t

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

typedef enum _lpadc_hardware_compare_mode lpadc_hardware_compare_mode_t

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

typedef enum _lpadc_conversion_resolution_mode lpadc_conversion_resolution_mode_t

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

typedef enum _lpadc_conversion_average_mode lpadc_conversion_average_mode_t

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

typedef enum _lpadc_reference_voltage_mode lpadc_reference_voltage_source_t

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

typedef enum _lpadc_power_level_mode lpadc_power_level_mode_t

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

typedef enum _lpadc_offset_calibration_mode lpadc_offset_calibration_mode_t

Define enumeration of offset calibration mode.

typedef enum _lpadc_trigger_priority_policy lpadc_trigger_priority_policy_t

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

typedef struct _lpadc_calibration_value lpadc_calibration_value_t

A structure of calibration value.

LPADC_CONVERSION_COMPLETE_TIMEOUT

Max loops to wait for LPADC conversion complete.

When doing calibration, driver will wait for the completion of conversion. This parameter defines how many loops to check completion before return timeout. If defined as 0, driver will wait forever until completion.

LPADC_CALIBRATION_READY_TIMEOUT

Max loops to wait for LPADC calibration ready.

Before doing calibration, driver will wait for the calibration ready. This parameter defines how many loops to check the calibration ready. If defined as 0, driver will wait forever until ready.

LPADC_GAIN_CAL_READY_TIMEOUT

Max loops to wait for LPADC gain calibration GAIN_CAL ready.

Before doing calibration, driver will wait for the gain calibration GAIN_CAL ready. This parameter defines how many loops to check the gain calibration GAIN_CAL ready. If defined as 0, driver will wait forever until ready.

LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal)

Define the MACRO function to get command status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal)

Define the MACRO function to get trigger status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)

Initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• config – Pointer to configuration structure. See “lpadc_config_t”.

void LPADC_GetDefaultConfig(lpadc_config_t *config)

Gets an available pre-defined settings for initial configuration.

This function initializes the converter configuration structure with an available settings. The default values are:

config->enableInDozeMode        = true;
config->enableAnalogPreliminary = false;
config->powerUpDelay            = 0x80;
config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
config->powerLevelMode          = kLPADC_PowerLevelAlt1;
config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
config->enableConvPause         = false;
config->convPauseDelay          = 0U;
config->FIFOWatermark           = 0U;

Parameters:

• config – Pointer to configuration structure.

void LPADC_Deinit(ADC_Type *base)

De-initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_Enable(ADC_Type *base, bool enable)

Switch on/off the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the module.

static inline void LPADC_DoResetFIFO(ADC_Type *base)

Do reset the conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_DoResetConfig(ADC_Type *base)

Do reset the module’s configuration.

Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).

Parameters:

• base – LPADC peripheral base address.

static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)

Get status flags.

Parameters:

• base – LPADC peripheral base address.

Returns:

status flags’ mask. See to _lpadc_status_flags.

static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)

Clear status flags.

Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for flags to be cleared. See to _lpadc_status_flags.

static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)

Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high priority trigger exception.

Parameters:

• base – LPADC peripheral base address.

Returns:

The OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)

Clear trigger status flags.

Parameters:

• base – LPADC peripheral base address.

• mask – The mask of trigger status flags to be cleared, should be the OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)

Switch on/off the DMA trigger for FIFO watermark event.

Parameters:

• base – LPADC peripheral base address.

• enable – Switcher to the event.

static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)

Get the count of result kept in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

Returns:

The count of result kept in conversion FIFO.

bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

Returns:

Status whether FIFO entry is valid.

void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO using blocking method.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)

Configure the conversion trigger source.

Each programmable trigger can launch the conversion command in command buffer.

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• config – Pointer to configuration structure. See to lpadc_conv_trigger_config_t.

void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)

Gets an available pre-defined settings for trigger’s configuration.

This function initializes the trigger’s configuration structure with an available settings. The default values are:

config->targetCommandId        = 0U;
config->delayPower             = 0U;
config->priority               = 0U;
config->channelAFIFOSelect     = 0U;
config->channelBFIFOSelect     = 0U;
config->enableHardwareTrigger  = false;

Parameters:

• config – Pointer to configuration structure.

static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)

Do software trigger to conversion command.

Parameters:

• base – LPADC peripheral base address.

• triggerIdMask – Mask value for software trigger indexes, which count from zero.

static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)

Enable hardware trigger command selection.

This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL].

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• enable – True to enable or flase to disable.

void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)

Configure conversion command.

Note

The number of compare value register on different chips is different, that is mean in some chips, some command buffers do not have the compare functionality.

Parameters:

• base – LPADC peripheral base address.

• commandId – ID for command in command buffer. Typically, the available value range is 1 - 15.

• config – Pointer to configuration structure. See to lpadc_conv_command_config_t.

void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)

Gets an available pre-defined settings for conversion command’s configuration.

This function initializes the conversion command’s configuration structure with an available settings. The default values are:

config->sampleScaleMode            = kLPADC_SampleFullScale;
config->channelBScaleMode          = kLPADC_SampleFullScale;
config->sampleChannelMode          = kLPADC_SampleChannelSingleEndSideA;
config->channelNumber              = 0U;
config->channelBNumber             = 0U;
config->chainedNextCommandNumber   = 0U;
config->enableAutoChannelIncrement = false;
config->loopCount                  = 0U;
config->hardwareAverageMode        = kLPADC_HardwareAverageCount1;
config->sampleTimeMode             = kLPADC_SampleTimeADCK3;
config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
config->hardwareCompareValueHigh   = 0U;
config->hardwareCompareValueLow    = 0U;
config->conversionResolutionMode   = kLPADC_ConversionResolutionStandard;
config->enableWaitTrigger          = false;
config->enableChannelB             = false;

Parameters:

• config – Pointer to configuration structure.

void LPADC_EnableCalibration(ADC_Type *base, bool enable)

Enable the calibration function.

When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)

Set proper offset value to trim ADC.

To minimize the offset during normal operation, software should read the conversion result from the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.

Parameters:

• base – LPADC peripheral base address.

• value – Setting offset value.

status_t LPADC_DoAutoCalibration(ADC_Type *base)

Do auto calibration.

Calibration function should be executed before using converter in application. It used the software trigger and a dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -LPADC_EnableCalibration(…) -LPADC_LPADC_SetOffsetValue(…) -LPADC_SetConvCommandConfig(…) -LPADC_SetConvTriggerConfig(…)

Parameters:

• base – LPADC peripheral base address.

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)

Enable the offset calibration function.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)

Set offset calibration mode.

Parameters:

• base – LPADC peripheral base address.

• mode – set offset calibration mode.see to lpadc_offset_calibration_mode_t .

status_t LPADC_DoOffsetCalibration(ADC_Type *base)

Do offset calibration.

Parameters:

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

void LPADC_PrepareAutoCalibration(ADC_Type *base)

Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.

Parameters:

• base – LPADC peripheral base address.

status_t LPADC_FinishAutoCalibration(ADC_Type *base)

Finish auto calibration start with LPADC_PrepareAutoCalibration.

Note

This feature is used for LPADC with CTRL[CALOFSMODE].

Parameters:

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue)

Get calibration value into the memory which is defined by invoker.

Note

Please note the ADC will be disabled temporary.

Note

This function should be used after finish calibration.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure, this memory block should be always powered on even in low power modes.

status_t LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue)

Set calibration value into ADC calibration registers.

Note

Please note the ADC will be disabled temporary.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure which contains ADC’s calibration value.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

FSL_LPADC_DRIVER_VERSION

LPADC driver version 2.9.4.

struct lpadc_config_t

#include <fsl_lpadc.h>

LPADC global configuration.

This structure would used to keep the settings for initialization.

Public Members

bool enableInternalClock

Enables the internally generated clock source. The clock source is used in clock selection logic at the chip level and is optionally used for the ADC clock source.

bool enableVref1LowVoltage

If voltage reference option1 input is below 1.8V, it should be “true”. If voltage reference option1 input is above 1.8V, it should be “false”.

bool enableInDozeMode

Control system transition to Stop and Wait power modes while ADC is converting. When enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.

lpadc_conversion_average_mode_t conversionAverageMode

Auto-Calibration Averages.

bool enableAnalogPreliminary

ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).

uint32_t powerUpDelay

When the analog circuits are not pre-enabled, the ADC analog circuits are only powered while the ADC is active and there is a counted delay defined by this field after an initial trigger transitions the ADC from its Idle state to allow time for the analog circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must result in a longer delay than the analog startup time.

lpadc_reference_voltage_source_t referenceVoltageSource

Selects the voltage reference high used for conversions.

lpadc_power_level_mode_t powerLevelMode

Power Configuration Selection.

lpadc_trigger_priority_policy_t triggerPriorityPolicy

Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t.

bool enableConvPause

Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations, between commands in a sequence, and between conversions when command is executing in “Compare Until True” configuration.

uint32_t convPauseDelay

Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing function is enabled. The available value range is in 9-bit.

uint32_t FIFOWatermark

FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold.

struct lpadc_conv_command_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion command.

Public Members

lpadc_sample_scale_mode_t sampleScaleMode

Sample scale mode.

lpadc_sample_scale_mode_t channelBScaleMode

Alternate channe B Scale mode.

lpadc_sample_channel_mode_t sampleChannelMode

Channel sample mode.

uint32_t channelNumber

Channel number, select the channel or channel pair.

uint32_t channelBNumber

Alternate Channel B number, select the channel.

uint32_t chainedNextCommandNumber

Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command.

bool enableAutoChannelIncrement

Loop with increment: when disabled, the “loopCount” field selects the number of times the selected channel is converted consecutively; when enabled, the “loopCount” field defines how many consecutive channels are converted as part of the command execution.

uint32_t loopCount

Selects how many times this command executes before finish and transition to the next command or Idle state. Command executes LOOP+1 times. 0-15 is available.

lpadc_hardware_average_mode_t hardwareAverageMode

Hardware average selection.

lpadc_sample_time_mode_t sampleTimeMode

Sample time selection.

lpadc_hardware_compare_mode_t hardwareCompareMode

Hardware compare selection.

uint32_t hardwareCompareValueHigh

Compare Value High. The available value range is in 16-bit.

uint32_t hardwareCompareValueLow

Compare Value Low. The available value range is in 16-bit.

lpadc_conversion_resolution_mode_t conversionResolutionMode

Conversion resolution mode.

bool enableWaitTrigger

Wait for trigger assertion before execution: when disabled, this command will be automatically executed; when enabled, the active trigger must be asserted again before executing this command.

struct lpadc_conv_trigger_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion trigger.

Public Members

uint32_t targetCommandId

Select the command from command buffer to execute upon detect of the associated trigger event.

uint32_t delayPower

Select the trigger delay duration to wait at the start of servicing a trigger event. When this field is clear, then no delay is incurred. When this field is set to a non-zero value, the duration for the delay is 2^delayPower ADCK cycles. The available value range is 4-bit.

uint32_t priority

Sets the priority of the associated trigger source. If two or more triggers have the same priority level setting, the lower order trigger event has the higher priority. The lower value for this field is for the higher priority, the available value range is 1-bit.

bool enableHardwareTrigger

Enable hardware trigger source to initiate conversion on the rising edge of the input trigger source or not. THe software trigger is always available.

struct lpadc_conv_result_t

#include <fsl_lpadc.h>

Define the structure to keep the conversion result.

Public Members

uint32_t commandIdSource

Indicate the command buffer being executed that generated this result.

uint32_t loopCountIndex

Indicate the loop count value during command execution that generated this result.

uint32_t triggerIdSource

Indicate the trigger source that initiated a conversion and generated this result.

uint16_t convValue

Data result.

struct _lpadc_calibration_value

#include <fsl_lpadc.h>

A structure of calibration value.

LPI2C: Low Power Inter-Integrated Circuit Driver

void LPI2C_DriverIRQHandler(uint32_t instance)

LPI2C driver IRQ handler common entry.

This function provides the common IRQ request entry for LPI2C.

Parameters:

• instance – LPI2C instance.

FSL_LPI2C_DRIVER_VERSION

LPI2C driver version.

LPI2C status return codes.

Values:

enumerator kStatus_LPI2C_Busy

The master is already performing a transfer.

enumerator kStatus_LPI2C_Idle

The slave driver is idle.

enumerator kStatus_LPI2C_Nak

The slave device sent a NAK in response to a byte.

enumerator kStatus_LPI2C_FifoError

FIFO under run or overrun.

enumerator kStatus_LPI2C_BitError

Transferred bit was not seen on the bus.

enumerator kStatus_LPI2C_ArbitrationLost

Arbitration lost error.

enumerator kStatus_LPI2C_PinLowTimeout

SCL or SDA were held low longer than the timeout.

enumerator kStatus_LPI2C_NoTransferInProgress

Attempt to abort a transfer when one is not in progress.

enumerator kStatus_LPI2C_DmaRequestFail

DMA request failed.

enumerator kStatus_LPI2C_Timeout

Timeout polling status flags.

IRQn_Type const kLpi2cIrqs[]

Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs.

lpi2c_master_isr_t s_lpi2cMasterIsr

Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

void *s_lpi2cMasterHandle[]

Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

uint32_t LPI2C_GetInstance(LPI2C_Type *base)

Returns an instance number given a base address.

If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

LPI2C instance number starting from 0.

I2C_RETRY_TIMES

Retry times for waiting flag.

LPI2C Master Driver

void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)

Provides a default configuration for the LPI2C master peripheral.

This function provides the following default configuration for the LPI2C master peripheral:

masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

• masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t.

void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C master peripheral.

This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

• base – The LPI2C peripheral base address.

• masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void LPI2C_MasterDeinit(LPI2C_Type *base)

Deinitializes the LPI2C master peripheral.

This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)

Configures LPI2C master data match feature.

Parameters:

• base – The LPI2C peripheral base address.

• matchConfig – Settings for the data match feature.

status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)

Convert provided flags to status code, and clear any errors if present.

Parameters:

• base – The LPI2C peripheral base address.

• status – Current status flags value that will be checked.

Return values:

• kStatus_Success –

• kStatus_LPI2C_PinLowTimeout –

• kStatus_LPI2C_ArbitrationLost –

• kStatus_LPI2C_Nak –

• kStatus_LPI2C_FifoError –

status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)

Make sure the bus isn’t already busy.

A busy bus is allowed if we are the one driving it.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success –

• kStatus_LPI2C_Busy –

static inline void LPI2C_MasterReset(LPI2C_Type *base)

Performs a software reset.

Restores the LPI2C master peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as master.

static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C master status flags.

A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_master_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C master status flag state.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_master_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags().

static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C master interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)

Enables or disables LPI2C master DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)

Gets LPI2C master transmit data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Transmit Data Register address.

static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)

Gets LPI2C master receive data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Receive Data Register address.

static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)

Sets the watermarks for LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated.

• rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of words in the LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required.

void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)

Sets the I2C bus frequency for master transactions.

The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note

Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.

Parameters:

• base – The LPI2C peripheral base address.

• sourceClock_Hz – LPI2C functional clock frequency in Hertz.

• baudRate_Hz – Requested bus frequency in Hertz.

static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the master mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a START signal and slave address on the I2C bus.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a repeated START signal and slave address on the I2C bus.

This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note

This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)

Performs a polling send transfer on the I2C bus.

Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was sent successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or over run.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterStop(LPI2C_Type *base)

Sends a STOP signal on the I2C bus.

This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to error happens during transfer.

Parameters:

• base – The LPI2C peripheral base address.

• transfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C master non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• lpi2cMasterHandle – Pointer to the LPI2C master driver handle.

enum _lpi2c_master_flags

LPI2C master peripheral flags.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_MasterTxReadyFlag

Transmit data flag

enumerator kLPI2C_MasterRxReadyFlag

Receive data flag

enumerator kLPI2C_MasterEndOfPacketFlag

End Packet flag

enumerator kLPI2C_MasterStopDetectFlag

Stop detect flag

enumerator kLPI2C_MasterNackDetectFlag

NACK detect flag

enumerator kLPI2C_MasterArbitrationLostFlag

Arbitration lost flag

enumerator kLPI2C_MasterFifoErrFlag

FIFO error flag

enumerator kLPI2C_MasterPinLowTimeoutFlag

Pin low timeout flag

enumerator kLPI2C_MasterDataMatchFlag

Data match flag

enumerator kLPI2C_MasterBusyFlag

Master busy flag

enumerator kLPI2C_MasterBusBusyFlag

Bus busy flag

enumerator kLPI2C_MasterClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_MasterIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_MasterErrorFlags

Errors to check for.

enum _lpi2c_direction

Direction of master and slave transfers.

Values:

enumerator kLPI2C_Write

Master transmit.

enumerator kLPI2C_Read

Master receive.

enum _lpi2c_master_pin_config

LPI2C pin configuration.

Values:

enumerator kLPI2C_2PinOpenDrain

LPI2C Configured for 2-pin open drain mode

enumerator kLPI2C_2PinOutputOnly

LPI2C Configured for 2-pin output only mode (ultra-fast mode)

enumerator kLPI2C_2PinPushPull

LPI2C Configured for 2-pin push-pull mode

enumerator kLPI2C_4PinPushPull

LPI2C Configured for 4-pin push-pull mode

enumerator kLPI2C_2PinOpenDrainWithSeparateSlave

LPI2C Configured for 2-pin open drain mode with separate LPI2C slave

enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave

LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave

enumerator kLPI2C_2PinPushPullWithSeparateSlave

LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave

enumerator kLPI2C_4PinPushPullWithInvertedOutput

LPI2C Configured for 4-pin push-pull mode(inverted outputs)

enum _lpi2c_host_request_source

LPI2C master host request selection.

Values:

enumerator kLPI2C_HostRequestExternalPin

Select the LPI2C_HREQ pin as the host request input

enumerator kLPI2C_HostRequestInputTrigger

Select the input trigger as the host request input

enum _lpi2c_host_request_polarity

LPI2C master host request pin polarity configuration.

Values:

enumerator kLPI2C_HostRequestPinActiveLow

Configure the LPI2C_HREQ pin active low

enumerator kLPI2C_HostRequestPinActiveHigh

Configure the LPI2C_HREQ pin active high

enum _lpi2c_data_match_config_mode

LPI2C master data match configuration modes.

Values:

enumerator kLPI2C_MatchDisabled

LPI2C Match Disabled

enumerator kLPI2C_1stWordEqualsM0OrM1

LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1

enumerator kLPI2C_AnyWordEqualsM0OrM1

LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1

enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1

LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1

enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1

LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1

enumerator kLPI2C_1stWordAndM1EqualsM0AndM1

LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1

enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1

LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1

enum _lpi2c_master_transfer_flags

Transfer option flags.

Note

These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field.

Values:

enumerator kLPI2C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal.

enumerator kLPI2C_TransferNoStartFlag

Don’t send a start condition, address, and sub address

enumerator kLPI2C_TransferRepeatedStartFlag

Send a repeated start condition

enumerator kLPI2C_TransferNoStopFlag

Don’t send a stop condition.

typedef enum _lpi2c_direction lpi2c_direction_t

Direction of master and slave transfers.

typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t

LPI2C pin configuration.

typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t

LPI2C master host request selection.

typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t

LPI2C master host request pin polarity configuration.

typedef struct _lpi2c_master_config lpi2c_master_config_t

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t

LPI2C master data match configuration modes.

typedef struct _lpi2c_match_config lpi2c_data_match_config_t

LPI2C master data match configuration structure.

typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t

LPI2C master descriptor of the transfer.

typedef struct _lpi2c_master_handle lpi2c_master_handle_t

LPI2C master handle of the transfer.

typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)

Master completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Pointer to the LPI2C master driver handle.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)

Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs.

struct _lpi2c_master_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableMaster

Whether to enable master mode.

bool enableDoze

Whether master is enabled in doze mode.

bool debugEnable

Enable transfers to continue when halted in debug mode.

bool ignoreAck

Whether to ignore ACK/NACK.

lpi2c_master_pin_config_t pinConfig

The pin configuration option.

uint32_t baudRate_Hz

Desired baud rate in Hertz.

uint32_t busIdleTimeout_ns

Bus idle timeout in nanoseconds. Set to 0 to disable.

uint32_t pinLowTimeout_ns

Pin low timeout in nanoseconds. Set to 0 to disable.

uint8_t sdaGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable.

uint8_t sclGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable.

struct _lpi2c_master_config hostRequest

Host request options.

struct _lpi2c_match_config

#include <fsl_lpi2c.h>

LPI2C master data match configuration structure.

Public Members

lpi2c_data_match_config_mode_t matchMode

Data match configuration setting.

bool rxDataMatchOnly

When set to true, received data is ignored until a successful match.

uint32_t match0

Match value 0.

uint32_t match1

Match value 1.

struct _lpi2c_master_transfer

#include <fsl_lpi2c.h>

Non-blocking transfer descriptor structure.

This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API.

Public Members

uint32_t flags

Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers.

uint16_t slaveAddress

The 7-bit slave address.

lpi2c_direction_t direction

Either kLPI2C_Read or kLPI2C_Write.

uint32_t subaddress

Sub address. Transferred MSB first.

size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes.

void *data

Pointer to data to transfer.

size_t dataSize

Number of bytes to transfer.

struct _lpi2c_master_handle

#include <fsl_lpi2c.h>

Driver handle for master non-blocking APIs.

Note

The contents of this structure are private and subject to change.

Public Members

uint8_t state

Transfer state machine current state.

uint16_t remainingBytes

Remaining byte count in current state.

uint8_t *buf

Buffer pointer for current state.

uint16_t commandBuffer[6]

LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

struct hostRequest

Public Members

bool enable

Enable host request.

lpi2c_host_request_source_t source

Host request source.

lpi2c_host_request_polarity_t polarity

Host request pin polarity.

LPI2C Master DMA Driver

void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)

Create a new handle for the LPI2C master DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.

For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function.

• txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I2C bus.

The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.

status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

Return values:

• kStatus_Success – A transaction was successfully aborted.

• kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress.

typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t

LPI2C master EDMA handle of the transfer.

typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)

Master DMA completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Handle associated with the completed transfer.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_master_edma_handle

#include <fsl_lpi2c_edma.h>

Driver handle for master DMA APIs.

Note

The contents of this structure are private and subject to change.

Public Members

LPI2C_Type *base

LPI2C base pointer.

bool isBusy

Transfer state machine current state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint16_t commandBuffer[20]

LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_edma_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

edma_handle_t *rx

Handle for receive DMA channel.

edma_handle_t *tx

Handle for transmit DMA channel.

edma_tcd_t tcds[3]

Software TCD. Three are allocated to provide enough room to align to 32-bytes.

LPI2C Slave Driver

void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)

Provides a default configuration for the LPI2C slave peripheral.

This function provides the following default configuration for the LPI2C slave peripheral:

slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;

After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

• slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t.

void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C slave peripheral.

This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

• base – The LPI2C peripheral base address.

• slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time.

void LPI2C_SlaveDeinit(LPI2C_Type *base)

Deinitializes the LPI2C slave peripheral.

This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveReset(LPI2C_Type *base)

Performs a software reset of the LPI2C slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as slave.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as slave.

static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C slave status flags.

A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_slave_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C status flag state.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_slave_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags().

static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C slave interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)

Enables or disables the LPI2C slave peripheral DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request.

• enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable.

• enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable.

static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the slave mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master.

Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

• ackOrNack – Pass true for an ACK or false for a NAK.

static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)

Enables or disables ACKSTALL.

When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – True will enable ACKSTALL,false will disable ACKSTALL.

static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)

Returns the slave address sent by the I2C master.

This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits.

status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)

Performs a polling send transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

• actualTxSize – [out]

Returns:

Error or success status returned by API.

status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

• actualRxSize – [out]

Returns:

Error or success status returned by API.

void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C slave non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C slave driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers.

Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

• eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.

Return values:

• kStatus_Success – Slave transfers were successfully started.

• kStatus_LPI2C_Busy – Slave transfers have already been started on this handle.

status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to i2c_slave_handle_t structure.

• count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress –

void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Aborts the slave non-blocking transfers.

Note

This API could be called at any time to stop slave for handling the bus events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

enum _lpi2c_slave_flags

LPI2C slave peripheral flags.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_SlaveTxReadyFlag

Transmit data flag

enumerator kLPI2C_SlaveRxReadyFlag

Receive data flag

enumerator kLPI2C_SlaveAddressValidFlag

Address valid flag

enumerator kLPI2C_SlaveTransmitAckFlag

Transmit ACK flag

enumerator kLPI2C_SlaveRepeatedStartDetectFlag

Repeated start detect flag

enumerator kLPI2C_SlaveStopDetectFlag

Stop detect flag

enumerator kLPI2C_SlaveBitErrFlag

Bit error flag

enumerator kLPI2C_SlaveFifoErrFlag

FIFO error flag

enumerator kLPI2C_SlaveAddressMatch0Flag

Address match 0 flag

enumerator kLPI2C_SlaveAddressMatch1Flag

Address match 1 flag

enumerator kLPI2C_SlaveGeneralCallFlag

General call flag

enumerator kLPI2C_SlaveBusyFlag

Master busy flag

enumerator kLPI2C_SlaveBusBusyFlag

Bus busy flag

enumerator kLPI2C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_SlaveIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_SlaveErrorFlags

Errors to check for.

enum _lpi2c_slave_address_match

LPI2C slave address match options.

Values:

enumerator kLPI2C_MatchAddress0

Match only address 0.

enumerator kLPI2C_MatchAddress0OrAddress1

Match either address 0 or address 1.

enumerator kLPI2C_MatchAddress0ThroughAddress1

Match a range of slave addresses from address 0 through address 1.

enum _lpi2c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kLPI2C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start.

enumerator kLPI2C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role).

enumerator kLPI2C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kLPI2C_SlaveTransmitAckEvent

Callback needs to either transmit an ACK or NACK.

enumerator kLPI2C_SlaveRepeatedStartEvent

A repeated start was detected.

enumerator kLPI2C_SlaveCompletionEvent

A stop was detected, completing the transfer.

enumerator kLPI2C_SlaveAllEvents

Bit mask of all available events.

typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t

LPI2C slave address match options.

typedef struct _lpi2c_slave_config lpi2c_slave_config_t

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t

LPI2C slave transfer structure.

typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t

LPI2C slave handle structure.

typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type.

This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:

Base address for the LPI2C instance on which the event occurred.

Param transfer:

Pointer to transfer descriptor containing values passed to and/or from the callback.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_slave_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableSlave

Enable slave mode.

uint8_t address0

Slave’s 7-bit address.

uint8_t address1

Alternate slave 7-bit address.

lpi2c_slave_address_match_t addressMatchMode

Address matching options.

bool filterDozeEnable

Enable digital glitch filter in doze mode.

bool filterEnable

Enable digital glitch filter.

bool enableGeneralCall

Enable general call address matching.

struct _lpi2c_slave_config sclStall

SCL stall enable options.

bool ignoreAck

Continue transfers after a NACK is detected.

bool enableReceivedAddressRead

Enable reading the address received address as the first byte of data.

uint32_t sdaGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable.

uint32_t sclGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable.

uint32_t dataValidDelay_ns

Width in nanoseconds of the data valid delay.

uint32_t clockHoldTime_ns

Width in nanoseconds of the clock hold time.

struct _lpi2c_slave_transfer

#include <fsl_lpi2c.h>

LPI2C slave transfer structure.

Public Members

lpi2c_slave_transfer_event_t event

Reason the callback is being invoked.

uint8_t receivedAddress

Matching address send by master.

uint8_t *data

Transfer buffer

size_t dataSize

Transfer size

status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent.

size_t transferredCount

Number of bytes actually transferred since start or last repeated start.

struct _lpi2c_slave_handle

#include <fsl_lpi2c.h>

LPI2C slave handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

lpi2c_slave_transfer_t transfer

LPI2C slave transfer copy.

bool isBusy

Whether transfer is busy.

bool wasTransmit

Whether the last transfer was a transmit.

uint32_t eventMask

Mask of enabled events.

uint32_t transferredCount

Count of bytes transferred.

lpi2c_slave_transfer_callback_t callback

Callback function called at transfer event.

void *userData

Callback parameter passed to callback.

struct sclStall

Public Members

bool enableAck

Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall.

bool enableTx

Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer.

bool enableRx

Enables SCL clock stretching when receive data flag is set during a slave-receive transfer.

bool enableAddress

Enables SCL clock stretching when the address valid flag is asserted.

LPIT: Low-Power Interrupt Timer

void LPIT_Init(LPIT_Type *base, const lpit_config_t *config)

Ungates the LPIT clock and configures the peripheral for a basic operation.

This function issues a software reset to reset all channels and registers except the Module Control register.

Note

This API should be called at the beginning of the application using the LPIT driver.

Parameters:

• base – LPIT peripheral base address.

• config – Pointer to the user configuration structure.

void LPIT_Deinit(LPIT_Type *base)

Disables the module and gates the LPIT clock.

Parameters:

• base – LPIT peripheral base address.

void LPIT_GetDefaultConfig(lpit_config_t *config)

Fills in the LPIT configuration structure with default settings.

The default values are:

config->enableRunInDebug = false;
config->enableRunInDoze = false;

Parameters:

• config – Pointer to the user configuration structure.

status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl_params_t *chnlSetup)

Sets up an LPIT channel based on the user’s preference.

This function sets up the operation mode to one of the options available in the enumeration lpit_timer_modes_t. It sets the trigger source as either internal or external, trigger selection and the timers behaviour when a timeout occurs. It also chains the timer if a prior timer if requested by the user.

Parameters:

• base – LPIT peripheral base address.

• channel – Channel that is being configured.

• chnlSetup – Configuration parameters.

static inline void LPIT_EnableInterrupts(LPIT_Type *base, uint32_t mask)

Enables the selected PIT interrupts.

Parameters:

• base – LPIT peripheral base address.

• mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t

static inline void LPIT_DisableInterrupts(LPIT_Type *base, uint32_t mask)

Disables the selected PIT interrupts.

Parameters:

• base – LPIT peripheral base address.

• mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t

static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type *base)

Gets the enabled LPIT interrupts.

Parameters:

• base – LPIT peripheral base address.

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration lpit_interrupt_enable_t

static inline uint32_t LPIT_GetStatusFlags(LPIT_Type *base)

Gets the LPIT status flags.

Parameters:

• base – LPIT peripheral base address.

Returns:

The status flags. This is the logical OR of members of the enumeration lpit_status_flags_t

static inline void LPIT_ClearStatusFlags(LPIT_Type *base, uint32_t mask)

Clears the LPIT status flags.

Parameters:

• base – LPIT peripheral base address.

• mask – The status flags to clear. This is a logical OR of members of the enumeration lpit_status_flags_t

static inline void LPIT_SetTimerPeriod(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count.

Timers begin counting down from the value set by this function until it reaches 0, at which point it generates an interrupt and loads this register value again. Writing a new value to this register does not restart the timer. Instead, the value is loaded after the timer expires.

Note

User can call the utility macros provided in fsl_common.h to convert to ticks.

Parameters:

• base – LPIT peripheral base address.

• channel – Timer channel number.

• ticks – Timer period in units of ticks.

static inline void LPIT_SetTimerValue(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count.

In the Dual 16-bit Periodic Counter mode, the counter will load and then the lower 16-bits will decrement down to zero, which will assert the output pre-trigger. The upper 16-bits will then decrement down to zero, which will negate the output pre-trigger and set the timer interrupt flag.

Note

Set TVAL register to 0 or 1 is invalid in compare mode.

Parameters:

• base – LPIT peripheral base address.

• channel – Timer channel number.

• ticks – Timer period in units of ticks.

static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type *base, lpit_chnl_t channel)

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds.

Parameters:

• base – LPIT peripheral base address.

• channel – Timer channel number.

Returns:

Current timer counting value in ticks.

static inline void LPIT_StartTimer(LPIT_Type *base, lpit_chnl_t channel)

Starts the timer counting.

After calling this function, timers load the period value and count down to 0. When the timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.

Parameters:

• base – LPIT peripheral base address.

• channel – Timer channel number.

static inline void LPIT_StopTimer(LPIT_Type *base, lpit_chnl_t channel)

Stops the timer counting.

Parameters:

• base – LPIT peripheral base address.

• channel – Timer channel number.

FSL_LPIT_DRIVER_VERSION

Version 2.1.3

enum _lpit_chnl

List of LPIT channels.

Note

Actual number of available channels is SoC-dependent

Values:

enumerator kLPIT_Chnl_0

LPIT channel number 0

enumerator kLPIT_Chnl_1

LPIT channel number 1

enumerator kLPIT_Chnl_2

LPIT channel number 2

enumerator kLPIT_Chnl_3

LPIT channel number 3

enum _lpit_timer_modes

Mode options available for the LPIT timer.

Values:

enumerator kLPIT_PeriodicCounter

Use the all 32-bits, counter loads and decrements to zero

enumerator kLPIT_DualPeriodicCounter

Counter loads, lower 16-bits decrement to zero, then upper 16-bits decrement

enumerator kLPIT_TriggerAccumulator

Counter loads on first trigger and decrements on each trigger

enumerator kLPIT_InputCapture

Counter loads with 0xFFFFFFFF, decrements to zero. It stores the inverse of the current value when a input trigger is detected

enum _lpit_trigger_select

Trigger options available.

This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual.

Values:

enumerator kLPIT_Trigger_TimerChn0

Channel 0 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn1

Channel 1 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn2

Channel 2 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn3

Channel 3 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn4

Channel 4 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn5

Channel 5 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn6

Channel 6 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn7

Channel 7 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn8

Channel 8 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn9

Channel 9 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn10

Channel 10 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn11

Channel 11 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn12

Channel 12 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn13

Channel 13 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn14

Channel 14 is selected as a trigger source

enumerator kLPIT_Trigger_TimerChn15

Channel 15 is selected as a trigger source

enum _lpit_trigger_source

Trigger source options available.

Values:

enumerator kLPIT_TriggerSource_External

Use external trigger input

enumerator kLPIT_TriggerSource_Internal

Use internal trigger

enum _lpit_interrupt_enable

List of LPIT interrupts.

Note

Number of timer channels are SoC-specific. See the SoC Reference Manual.

Values:

enumerator kLPIT_Channel0TimerInterruptEnable

Channel 0 Timer interrupt

enumerator kLPIT_Channel1TimerInterruptEnable

Channel 1 Timer interrupt

enumerator kLPIT_Channel2TimerInterruptEnable

Channel 2 Timer interrupt

enumerator kLPIT_Channel3TimerInterruptEnable

Channel 3 Timer interrupt

enum _lpit_status_flags

List of LPIT status flags.

Note

Number of timer channels are SoC-specific. See the SoC Reference Manual.

Values:

enumerator kLPIT_Channel0TimerFlag

Channel 0 Timer interrupt flag

enumerator kLPIT_Channel1TimerFlag

Channel 1 Timer interrupt flag

enumerator kLPIT_Channel2TimerFlag

Channel 2 Timer interrupt flag

enumerator kLPIT_Channel3TimerFlag

Channel 3 Timer interrupt flag

typedef enum _lpit_chnl lpit_chnl_t

List of LPIT channels.

Note

Actual number of available channels is SoC-dependent

typedef enum _lpit_timer_modes lpit_timer_modes_t

Mode options available for the LPIT timer.

typedef enum _lpit_trigger_select lpit_trigger_select_t

Trigger options available.

This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual.

typedef enum _lpit_trigger_source lpit_trigger_source_t

Trigger source options available.

typedef enum _lpit_interrupt_enable lpit_interrupt_enable_t

List of LPIT interrupts.

Note

Number of timer channels are SoC-specific. See the SoC Reference Manual.

typedef enum _lpit_status_flags lpit_status_flags_t

List of LPIT status flags.

Note

Number of timer channels are SoC-specific. See the SoC Reference Manual.

typedef struct _lpit_chnl_params lpit_chnl_params_t

Structure to configure the channel timer.

typedef struct _lpit_config lpit_config_t

LPIT configuration structure.

This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

static void LPIT_ResetStateDelay(void)

Short wait for LPIT state reset.

After clear or set LPIT_EN, there should be delay longer than 4 LPIT functional clock.

static inline void LPIT_Reset(LPIT_Type *base)

Performs a software reset on the LPIT module.

This resets all channels and registers except the Module Control Register.

Parameters:

• base – LPIT peripheral base address.

LPIT_RESET_STATE_DELAY

Delay used in LPIT_Reset.

The macro value should be larger than 4 * core clock / LPIT peripheral clock.

struct _lpit_chnl_params

#include <fsl_lpit.h>

Structure to configure the channel timer.

Public Members

bool chainChannel

true: Timer chained to previous timer; false: Timer not chained

lpit_timer_modes_t timerMode

Timers mode of operation.

lpit_trigger_select_t triggerSelect

Trigger selection for the timer

lpit_trigger_source_t triggerSource

Decides if we use external or internal trigger.

bool enableReloadOnTrigger

true: Timer reloads when a trigger is detected; false: No effect

bool enableStopOnTimeout

true: Timer will stop after timeout; false: does not stop after timeout

bool enableStartOnTrigger

true: Timer starts when a trigger is detected; false: decrement immediately

struct _lpit_config

#include <fsl_lpit.h>

LPIT configuration structure.

This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

Public Members

bool enableRunInDebug

true: Timers run in debug mode; false: Timers stop in debug mode

bool enableRunInDoze

true: Timers run in doze mode; false: Timers stop in doze mode

LPSPI: Low Power Serial Peripheral Interface

LPSPI Peripheral driver

void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the LPSPI master.

Parameters:

• base – LPSPI peripheral address.

• masterConfig – Pointer to structure lpspi_master_config_t.

• srcClock_Hz – Module source input clock in Hertz

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)

Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:

lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

• masterConfig – pointer to lpspi_master_config_t structure

void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)

LPSPI slave configuration.

Parameters:

• base – LPSPI peripheral address.

• slaveConfig – Pointer to a structure lpspi_slave_config_t.

void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)

Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:

lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

• slaveConfig – pointer to lpspi_slave_config_t structure.

void LPSPI_Deinit(LPSPI_Type *base)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.

Parameters:

• base – LPSPI peripheral address.

void LPSPI_Reset(LPSPI_Type *base)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API.

Parameters:

• base – LPSPI peripheral address.

uint32_t LPSPI_GetInstance(LPSPI_Type *base)

Get the LPSPI instance from peripheral base address.

Parameters:

• base – LPSPI peripheral base address.

Returns:

LPSPI instance.

static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)

Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Parameters:

• base – LPSPI peripheral address.

• enable – Pass true to enable module, false to disable module.

static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)

Gets the LPSPI status flag state.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI status(in SR register).

static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)

Gets the LPSPI Tx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Tx FIFO size.

static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)

Gets the LPSPI Rx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Rx FIFO size.

static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)

Gets the LPSPI Tx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the transmit FIFO.

static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)

Gets the LPSPI Rx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the receive FIFO.

static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)

Clears the LPSPI status flag.

This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:

LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);

Parameters:

• base – LPSPI peripheral address.

• statusFlags – The status flag used from type _lpspi_flags.

static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)

static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI interrupts.

This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.

LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI interrupts.

LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Transmit Data Register address for a DMA operation.

This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Transmit Data Register address.

static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Receive Data Register address for a DMA operation.

This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Receive Data Register address.

bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)

Check the argument for transfer .

Parameters:

• base – LPSPI peripheral address.

• transfer – the transfer struct to be used.

• isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer

Returns:

Return true for right and false for wrong.

static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)

Configures the LPSPI for either master or slave.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

• base – LPSPI peripheral address.

• mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t.

static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)

Configures the peripheral chip select used for the transfer.

Parameters:

• base – LPSPI peripheral address.

• select – LPSPI Peripheral Chip Select (PCS) configuration.

static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)

Set the PCS signal to continuous or uncontinuous mode.

Note

In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).

Parameters:

• base – LPSPI peripheral address.

• IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.

static inline bool LPSPI_IsMaster(LPSPI_Type *base)

Returns whether the LPSPI module is in master mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

Returns true if the module is in master mode or false if the module is in slave mode.

static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)

Flushes the LPSPI FIFOs.

Parameters:

• base – LPSPI peripheral address.

• flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.

• flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.

static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)

Sets the transmit and receive FIFO watermark values.

This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

• base – LPSPI peripheral address.

• txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

• rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)

Configures all LPSPI peripheral chip select polarities simultaneously.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.

LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);

Parameters:

• base – LPSPI peripheral address.

• mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity.

static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)

Configures the frame size.

The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.

Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.

Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

• base – LPSPI peripheral address.

• frameSize – The frame size in number of bits.

uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)

Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• baudRate_Bps – The desired baud rate in bits per second.

• srcClock_Hz – Module source input clock in Hertz.

• tcrPrescaleValue – The TCR prescale value needed to program the TCR.

Returns:

The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• scaler – The 8-bit delay value 0x00 to 0xFF (255).

• whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.

uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.

Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).

Parameters:

• base – LPSPI peripheral address.

• delayTimeInNanoSec – The desired delay value in nano-seconds.

• whichDelay – The desired delay to configuration, which must be of type lpspi_delay_type_t.

• srcClock_Hz – Module source input clock in Hertz.

Returns:

actual Calculated delay value in nano-seconds.

static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)

Writes data into the transmit data buffer.

This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

• base – LPSPI peripheral address.

• data – The data word to be sent.

static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)

Reads data from the data buffer.

This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The data read from the data buffer.

void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)

Set up the dummy data.

Parameters:

• base – LPSPI peripheral address.

• dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)

Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_master_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)

LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)

Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)

Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_slave_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)

Wait for tx FIFO to be empty.

This function wait the tx fifo empty

Parameters:

• base – LPSPI peripheral address.

Returns:

true for the tx FIFO is ready, false is not.

void LPSPI_DriverIRQHandler(uint32_t instance)

LPSPI driver IRQ handler common entry.

This function provides the common IRQ request entry for LPSPI.

Parameters:

• instance – LPSPI instance.

FSL_LPSPI_DRIVER_VERSION

LPSPI driver version.

Status for the LPSPI driver.

Values:

enumerator kStatus_LPSPI_Busy

LPSPI transfer is busy.

enumerator kStatus_LPSPI_Error

LPSPI driver error.

enumerator kStatus_LPSPI_Idle

LPSPI is idle.

enumerator kStatus_LPSPI_OutOfRange

LPSPI transfer out Of range.

enumerator kStatus_LPSPI_Timeout

LPSPI timeout polling status flags.

enum _lpspi_flags

LPSPI status flags in SPIx_SR register.

Values:

enumerator kLPSPI_TxDataRequestFlag

Transmit data flag

enumerator kLPSPI_RxDataReadyFlag

Receive data flag

enumerator kLPSPI_WordCompleteFlag

Word Complete flag

enumerator kLPSPI_FrameCompleteFlag

Frame Complete flag

enumerator kLPSPI_TransferCompleteFlag

Transfer Complete flag

enumerator kLPSPI_TransmitErrorFlag

Transmit Error flag (FIFO underrun)

enumerator kLPSPI_ReceiveErrorFlag

Receive Error flag (FIFO overrun)

enumerator kLPSPI_DataMatchFlag

Data Match flag

enumerator kLPSPI_ModuleBusyFlag

Module Busy flag

enumerator kLPSPI_AllStatusFlag

Used for clearing all w1c status flags

enum _lpspi_interrupt_enable

LPSPI interrupt source.

Values:

enumerator kLPSPI_TxInterruptEnable

Transmit data interrupt enable

enumerator kLPSPI_RxInterruptEnable

Receive data interrupt enable

enumerator kLPSPI_WordCompleteInterruptEnable

Word complete interrupt enable

enumerator kLPSPI_FrameCompleteInterruptEnable

Frame complete interrupt enable

enumerator kLPSPI_TransferCompleteInterruptEnable

Transfer complete interrupt enable

enumerator kLPSPI_TransmitErrorInterruptEnable

Transmit error interrupt enable(FIFO underrun)

enumerator kLPSPI_ReceiveErrorInterruptEnable

Receive Error interrupt enable (FIFO overrun)

enumerator kLPSPI_DataMatchInterruptEnable

Data Match interrupt enable

enumerator kLPSPI_AllInterruptEnable

All above interrupts enable.

enum _lpspi_dma_enable

LPSPI DMA source.

Values:

enumerator kLPSPI_TxDmaEnable

Transmit data DMA enable

enumerator kLPSPI_RxDmaEnable

Receive data DMA enable

enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration.

Values:

enumerator kLPSPI_Master

LPSPI peripheral operates in master mode.

enumerator kLPSPI_Slave

LPSPI peripheral operates in slave mode.

enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Values:

enumerator kLPSPI_Pcs0

PCS[0]

enumerator kLPSPI_Pcs1

PCS[1]

enumerator kLPSPI_Pcs2

PCS[2]

enumerator kLPSPI_Pcs3

PCS[3]

enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

Values:

enumerator kLPSPI_PcsActiveHigh

PCS Active High (idles low)

enumerator kLPSPI_PcsActiveLow

PCS Active Low (idles high)

enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity.

Values:

enumerator kLPSPI_Pcs0ActiveLow

Pcs0 Active Low (idles high).

enumerator kLPSPI_Pcs1ActiveLow

Pcs1 Active Low (idles high).

enumerator kLPSPI_Pcs2ActiveLow

Pcs2 Active Low (idles high).

enumerator kLPSPI_Pcs3ActiveLow

Pcs3 Active Low (idles high).

enumerator kLPSPI_PcsAllActiveLow

Pcs0 to Pcs5 Active Low (idles high).

enum _lpspi_clock_polarity

LPSPI clock polarity configuration.

Values:

enumerator kLPSPI_ClockPolarityActiveHigh

CPOL=0. Active-high LPSPI clock (idles low)

enumerator kLPSPI_ClockPolarityActiveLow

CPOL=1. Active-low LPSPI clock (idles high)

enum _lpspi_clock_phase

LPSPI clock phase configuration.

Values:

enumerator kLPSPI_ClockPhaseFirstEdge

CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.

enumerator kLPSPI_ClockPhaseSecondEdge

CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.

enum _lpspi_shift_direction

LPSPI data shifter direction options.

Values:

enumerator kLPSPI_MsbFirst

Data transfers start with most significant bit.

enumerator kLPSPI_LsbFirst

Data transfers start with least significant bit.

enum _lpspi_host_request_select

LPSPI Host Request select configuration.

Values:

enumerator kLPSPI_HostReqExtPin

Host Request is an ext pin.

enumerator kLPSPI_HostReqInternalTrigger

Host Request is an internal trigger.

enum _lpspi_match_config

LPSPI Match configuration options.

Values:

enumerator kLPSI_MatchDisabled

LPSPI Match Disabled.

enumerator kLPSI_1stWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration.

Values:

enumerator kLPSPI_SdiInSdoOut

LPSPI SDI input, SDO output.

enumerator kLPSPI_SdiInSdiOut

LPSPI SDI input, SDI output.

enumerator kLPSPI_SdoInSdoOut

LPSPI SDO input, SDO output.

enumerator kLPSPI_SdoInSdiOut

LPSPI SDO input, SDI output.

enum _lpspi_data_out_config

LPSPI data output configuration.

Values:

enumerator kLpspiDataOutRetained

Data out retains last value when chip select is de-asserted

enumerator kLpspiDataOutTristate

Data out is tristated when chip select is de-asserted

enum _lpspi_transfer_width

LPSPI transfer width configuration.

Values:

enumerator kLPSPI_SingleBitXfer

1-bit shift at a time, data out on SDO, in on SDI (normal mode)

enumerator kLPSPI_TwoBitXfer

2-bits shift out on SDO/SDI and in on SDO/SDI

enumerator kLPSPI_FourBitXfer

4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]

enum _lpspi_delay_type

LPSPI delay type selection.

Values:

enumerator kLPSPI_PcsToSck

PCS-to-SCK delay.

enumerator kLPSPI_LastSckToPcs

Last SCK edge to PCS delay.

enumerator kLPSPI_BetweenTransfer

Delay between transfers.

enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags.

Values:

enumerator kLPSPI_MasterPcs0

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal

enumerator kLPSPI_MasterPcs1

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal

enumerator kLPSPI_MasterPcs2

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal

enumerator kLPSPI_MasterPcs3

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal

enumerator kLPSPI_MasterPcsContinuous

Is PCS signal continuous

enumerator kLPSPI_MasterByteSwap

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags.

Values:

enumerator kLPSPI_SlavePcs0

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal

enumerator kLPSPI_SlavePcs1

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal

enumerator kLPSPI_SlavePcs2

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal

enumerator kLPSPI_SlavePcs3

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal

enumerator kLPSPI_SlaveByteSwap

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine.

Values:

enumerator kLPSPI_Idle

Nothing in the transmitter/receiver.

enumerator kLPSPI_Busy

Transfer queue is not finished.

enumerator kLPSPI_Error

Transfer error.

typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration.

typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration.

typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration.

typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options.

typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration.

typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options.

typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration.

typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration.

typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration.

typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection.

typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure.

typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure.

typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs.

typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs.

typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure.

volatile uint8_t g_lpspiDummyData[]

Global variable for dummy data value setting.

LPSPI_DUMMY_DATA

LPSPI dummy data if no Tx data.

Dummy data used for tx if there is not txData.

SPI_RETRY_TIMES

Retry times for waiting flag.

LPSPI_MASTER_PCS_SHIFT

LPSPI master PCS shift macro , internal used.

LPSPI_MASTER_PCS_MASK

LPSPI master PCS shift macro , internal used.

LPSPI_SLAVE_PCS_SHIFT

LPSPI slave PCS shift macro , internal used.

LPSPI_SLAVE_PCS_MASK

LPSPI slave PCS shift macro , internal used.

struct _lpspi_master_config

#include <fsl_lpspi.h>

LPSPI master configuration structure.

Public Members

uint32_t baudRate

Baud Rate for LPSPI.

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

uint32_t pcsToSckDelayInNanoSec

PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t lastSckToPcsDelayInNanoSec

Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t betweenTransferDelayInNanoSec

After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (PCS).

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

bool enableInputDelay

Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length.

struct _lpspi_slave_config

#include <fsl_lpspi.h>

LPSPI slave configuration structure.

Public Members

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (pcs)

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

struct _lpspi_transfer

#include <fsl_lpspi.h>

LPSPI master/slave transfer structure.

Public Members

const uint8_t *txData

Send buffer.

uint8_t *rxData

Receive buffer.

volatile size_t dataSize

Transfer bytes.

uint32_t configFlags

Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.

struct _lpspi_master_handle

#include <fsl_lpspi.h>

LPSPI master transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool writeTcrInIsr

A flag that whether should write TCR in ISR.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile bool isTxMask

A flag that whether TCR[TXMSK] is set.

volatile uint16_t bytesPerFrame

Number of bytes in each frame

volatile uint16_t frameSize

Backup of TCR[FRAMESZ]

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if the txData is NULL.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

lpspi_master_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

struct _lpspi_slave_handle

#include <fsl_lpspi.h>

LPSPI slave transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

volatile uint32_t errorCount

Error count for slave transfer.

lpspi_slave_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

LPSPI eDMA Driver

FSL_LPSPI_EDMA_DRIVER_VERSION

LPSPI EDMA driver version.

DMA_MAX_TRANSFER_COUNT

DMA max transfer size.

typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t

Forward declaration of the _lpspi_master_edma_handle typedefs.

typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t

Forward declaration of the _lpspi_slave_edma_handle typedefs.

typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI master eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_master_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)

LPSPI master config transfer parameter while using eDMA.

This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

Returns:

Indicates whether LPSPI master transfer was successful or not.

status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA without configs.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure, config field is not uesed.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

• kStatus_InvalidArgument – The transfer structure is invalid.

Returns:

Indicates whether LPSPI master transfer was successful or not.

void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)

LPSPI master aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)

Gets the master eDMA transfer remaining bytes.

This function gets the master eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the EDMA transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI slave eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.

(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_slave_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfers data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)

LPSPI slave aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)

Gets the slave eDMA transfer remaining bytes.

This function gets the slave eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the eDMA transaction.

Returns:

status of status_t.

struct _lpspi_master_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI master eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

edma_tcd_t *lastTimeTCD

Pointer to the lastTime TCD

bool isMultiDMATransmit

Is there multi DMA transmit

volatile uint8_t dmaTransmitTime

DMA Transfer times.

uint32_t lastTimeDataBytes

DMA transmit last Time data Bytes

uint32_t dataBytesEveryTime

Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT

edma_transfer_config_t transferConfigRx

Config of DMA rx channel.

edma_transfer_config_t transferConfigTx

Config of DMA tx channel.

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

uint32_t transmitCommand

Used to write TCR for DMA purpose.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

lpspi_master_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg buff

edma_tcd_t lpspiSoftwareTCD[3]

SoftwareTCD, internal used

struct _lpspi_slave_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI slave eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

volatile uint8_t state

LPSPI transfer state.

uint32_t errorCount

Error count for slave transfer.

lpspi_slave_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg

edma_tcd_t lpspiSoftwareTCD[2]

SoftwareTCD, internal used

LPTMR: Low-Power Timer

void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)

Ungates the LPTMR clock and configures the peripheral for a basic operation.

Note

This API should be called at the beginning of the application using the LPTMR driver.

Parameters:

• base – LPTMR peripheral base address

• config – A pointer to the LPTMR configuration structure.

void LPTMR_Deinit(LPTMR_Type *base)

Gates the LPTMR clock.

Parameters:

• base – LPTMR peripheral base address

void LPTMR_GetDefaultConfig(lptmr_config_t *config)

Fills in the LPTMR configuration structure with default settings.

The default values are as follows.

config->timerMode = kLPTMR_TimerModeTimeCounter;
config->pinSelect = kLPTMR_PinSelectInput_0;
config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
config->enableFreeRunning = false;
config->bypassPrescaler = true;
config->prescalerClockSource = kLPTMR_PrescalerClock_1;
config->value = kLPTMR_Prescale_Glitch_0;

Parameters:

• config – A pointer to the LPTMR configuration structure.

static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)

Enables the selected LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t

static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)

Disables the selected LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

• mask – The interrupts to disable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t.

static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)

Gets the enabled LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration lptmr_interrupt_enable_t

static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)

Gets the LPTMR status flags.

Parameters:

• base – LPTMR peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration lptmr_status_flags_t

static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)

Clears the LPTMR status flags.

Parameters:

• base – LPTMR peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration lptmr_status_flags_t.

static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)

Sets the timer period in units of count.

Timers counts from 0 until it equals the count value set here. The count value is written to the CMR register.

Note

1. The TCF flag is set with the CNR equals the count provided here and then increments.

2. Call the utility macros provided in the fsl_common.h to convert to ticks.

Parameters:

• base – LPTMR peripheral base address

• ticks – A timer period in units of ticks

static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)

Reads the current timer counting value.

This function returns the real-time timer counting value in a range from 0 to a timer period.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

• base – LPTMR peripheral base address

Returns:

The current counter value in ticks

static inline void LPTMR_StartTimer(LPTMR_Type *base)

Starts the timer.

After calling this function, the timer counts up to the CMR register value. Each time the timer reaches the CMR value and then increments, it generates a trigger pulse and sets the timeout interrupt flag. An interrupt is also triggered if the timer interrupt is enabled.

Parameters:

• base – LPTMR peripheral base address

static inline void LPTMR_StopTimer(LPTMR_Type *base)

Stops the timer.

This function stops the timer and resets the timer’s counter register.

Parameters:

• base – LPTMR peripheral base address

FSL_LPTMR_DRIVER_VERSION

Driver Version

enum _lptmr_pin_select

LPTMR pin selection used in pulse counter mode.

Values:

enumerator kLPTMR_PinSelectInput_0

Pulse counter input 0 is selected

enumerator kLPTMR_PinSelectInput_1

Pulse counter input 1 is selected

enumerator kLPTMR_PinSelectInput_2

Pulse counter input 2 is selected

enumerator kLPTMR_PinSelectInput_3

Pulse counter input 3 is selected

enum _lptmr_pin_polarity

LPTMR pin polarity used in pulse counter mode.

Values:

enumerator kLPTMR_PinPolarityActiveHigh

Pulse Counter input source is active-high

enumerator kLPTMR_PinPolarityActiveLow

Pulse Counter input source is active-low

enum _lptmr_timer_mode

LPTMR timer mode selection.

Values:

enumerator kLPTMR_TimerModeTimeCounter

Time Counter mode

enumerator kLPTMR_TimerModePulseCounter

Pulse Counter mode

enum _lptmr_prescaler_glitch_value

LPTMR prescaler/glitch filter values.

Values:

enumerator kLPTMR_Prescale_Glitch_0

Prescaler divide 2, glitch filter does not support this setting

enumerator kLPTMR_Prescale_Glitch_1

Prescaler divide 4, glitch filter 2

enumerator kLPTMR_Prescale_Glitch_2

Prescaler divide 8, glitch filter 4

enumerator kLPTMR_Prescale_Glitch_3

Prescaler divide 16, glitch filter 8

enumerator kLPTMR_Prescale_Glitch_4

Prescaler divide 32, glitch filter 16

enumerator kLPTMR_Prescale_Glitch_5

Prescaler divide 64, glitch filter 32

enumerator kLPTMR_Prescale_Glitch_6

Prescaler divide 128, glitch filter 64

enumerator kLPTMR_Prescale_Glitch_7

Prescaler divide 256, glitch filter 128

enumerator kLPTMR_Prescale_Glitch_8

Prescaler divide 512, glitch filter 256

enumerator kLPTMR_Prescale_Glitch_9

Prescaler divide 1024, glitch filter 512

enumerator kLPTMR_Prescale_Glitch_10

Prescaler divide 2048 glitch filter 1024

enumerator kLPTMR_Prescale_Glitch_11

Prescaler divide 4096, glitch filter 2048

enumerator kLPTMR_Prescale_Glitch_12

Prescaler divide 8192, glitch filter 4096

enumerator kLPTMR_Prescale_Glitch_13

Prescaler divide 16384, glitch filter 8192

enumerator kLPTMR_Prescale_Glitch_14

Prescaler divide 32768, glitch filter 16384

enumerator kLPTMR_Prescale_Glitch_15

Prescaler divide 65536, glitch filter 32768

enum _lptmr_prescaler_clock_select

LPTMR prescaler/glitch filter clock select.

Note

Clock connections are SoC-specific

Values:

enum _lptmr_interrupt_enable

List of the LPTMR interrupts.

Values:

enumerator kLPTMR_TimerInterruptEnable

Timer interrupt enable

enum _lptmr_status_flags

List of the LPTMR status flags.

Values:

enumerator kLPTMR_TimerCompareFlag

Timer compare flag

typedef enum _lptmr_pin_select lptmr_pin_select_t

LPTMR pin selection used in pulse counter mode.

typedef enum _lptmr_pin_polarity lptmr_pin_polarity_t

LPTMR pin polarity used in pulse counter mode.

typedef enum _lptmr_timer_mode lptmr_timer_mode_t

LPTMR timer mode selection.

typedef enum _lptmr_prescaler_glitch_value lptmr_prescaler_glitch_value_t

LPTMR prescaler/glitch filter values.

typedef enum _lptmr_prescaler_clock_select lptmr_prescaler_clock_select_t

LPTMR prescaler/glitch filter clock select.

Note

Clock connections are SoC-specific

typedef enum _lptmr_interrupt_enable lptmr_interrupt_enable_t

List of the LPTMR interrupts.

typedef enum _lptmr_status_flags lptmr_status_flags_t

List of the LPTMR status flags.

typedef struct _lptmr_config lptmr_config_t

LPTMR config structure.

This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration struct can be made constant so it resides in flash.

static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)

Enable or disable timer DMA request.

Parameters:

• base – base LPTMR peripheral base address

• enable – Switcher of timer DMA feature. “true” means to enable, “false” means to disable.

struct _lptmr_config

#include <fsl_lptmr.h>

LPTMR config structure.

This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration struct can be made constant so it resides in flash.

Public Members

lptmr_timer_mode_t timerMode

Time counter mode or pulse counter mode

lptmr_pin_select_t pinSelect

LPTMR pulse input pin select; used only in pulse counter mode

lptmr_pin_polarity_t pinPolarity

LPTMR pulse input pin polarity; used only in pulse counter mode

bool enableFreeRunning

True: enable free running, counter is reset on overflow False: counter is reset when the compare flag is set

bool bypassPrescaler

True: bypass prescaler; false: use clock from prescaler

lptmr_prescaler_clock_select_t prescalerClockSource

LPTMR clock source

lptmr_prescaler_glitch_value_t value

Prescaler or glitch filter value

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver

LPUART Driver

static inline void LPUART_SoftwareReset(LPUART_Type *base)

Resets the LPUART using software.

This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

• base – LPUART peripheral base address.

status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)

Initializes an LPUART instance with the user configuration structure and the peripheral clock.

This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART.

lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• config – Pointer to a user-defined configuration structure.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source.

• kStatus_Success – LPUART initialize succeed

status_t LPUART_Deinit(LPUART_Type *base)

Deinitializes a LPUART instance.

This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

• base – LPUART peripheral base address.

Return values:

• kStatus_Success – Deinit is success.

• kStatus_LPUART_Timeout – Timeout during deinit.

void LPUART_GetDefaultConfig(lpuart_config_t *config)

Gets the default configuration structure.

This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

• config – Pointer to a configuration structure.

status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the LPUART instance baudrate.

This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.

LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• baudRate_Bps – LPUART baudrate to be set.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source.

• kStatus_Success – Set baudrate succeeded.

void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)

Enable 9-bit data mode for LPUART.

This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

• base – LPUART peripheral base address.

• enable – true to enable, flase to disable.

static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)

Set the LPUART address.

This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note

Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.

Parameters:

• base – LPUART peripheral base address.

• address1 – LPUART slave address1.

• address2 – LPUART slave address2.

static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)

Enable the LPUART match address feature.

Parameters:

• base – LPUART peripheral base address.

• match1 – true to enable match address1, false to disable.

• match2 – true to enable match address2, false to disable.

static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the rx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Rx FIFO watermark.

static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the tx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Tx FIFO watermark.

static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.

This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

• handle – LPUART handle pointer.

• enable – true to enable, false to disable.

uint32_t LPUART_GetStatusFlags(LPUART_Type *base)

Gets LPUART status flags.

This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty:

if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART status flags which are ORed by the enumerators in the _lpuart_flags.

status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)

Clears status flags with a provided mask.

This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

• base – LPUART peripheral base address.

• mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask.

Return values:

• kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware.

• kStatus_Success – Status in the mask are cleared.

Returns:

0 succeed, others failed.

void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)

Enables LPUART interrupts according to a provided mask.

This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt:

LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable.

void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)

Disables LPUART interrupts according to a provided mask.

This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt:

LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable.

uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)

Gets enabled LPUART interrupts.

This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable.

static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)

Gets the LPUART data register address.

This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART data register addresses which are used both by the transmitter and receiver.

static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter DMA request.

This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver DMA.

This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

uint32_t LPUART_GetInstance(LPUART_Type *base)

Get the LPUART instance from peripheral base address.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART instance.

static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter.

This function enables or disables the LPUART transmitter.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver.

This function enables or disables the LPUART receiver.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)

Writes to the transmitter register.

This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

• base – LPUART peripheral base address.

• data – Data write to the TX register.

static inline uint8_t LPUART_ReadByte(LPUART_Type *base)

Reads the receiver register.

This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

• base – LPUART peripheral base address.

Returns:

Data read from data register.

static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)

Gets the rx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

rx FIFO data count.

static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)

Gets the tx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

tx FIFO data count.

void LPUART_SendAddress(LPUART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode.

Parameters:

• base – LPUART peripheral base address.

• address – LPUART slave address.

status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)

Writes to the transmitter register using a blocking method.

This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)

Writes to the transmitter register using a blocking method in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)

Reads the receiver data register using a blocking method.

This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)

Reads the receiver data register in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data by 16bit, only 10bit is valid.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)

Initializes the LPUART handle.

This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.

The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• callback – Callback function.

• userData – User data.

status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note

The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note

When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.

• ringBufferSize – size of the ring buffer.

void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)

Get the length of received data in RX ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

Returns:

Length of received data in RX ring buffer.

void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been sent out to bus.

This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see uart_transfer_t.

• receivedBytes – Bytes received from the ring buffer directly.

Return values:

• kStatus_Success – Successfully queue the transfer into the transmit queue.

• kStatus_LPUART_RxBusy – Previous receive request is not finished.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data receiving.

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received.

This function gets the number of bytes that have been received.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)

LPUART IRQ handle function.

This function handles the LPUART transmit and receive IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)

LPUART Error IRQ handle function.

This function handles the LPUART error IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

void LPUART_DriverIRQHandler(uint32_t instance)

LPUART driver IRQ handler common entry.

This function provides the common IRQ request entry for LPUART.

Parameters:

• instance – LPUART instance.

FSL_LPUART_DRIVER_VERSION

LPUART driver version.

Error codes for the LPUART driver.

Values:

enumerator kStatus_LPUART_TxBusy

TX busy

enumerator kStatus_LPUART_RxBusy

RX busy

enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle.

enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle.

enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large

enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large

enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear

enumerator kStatus_LPUART_Error

Error happens on LPUART.

enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun.

enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun.

enumerator kStatus_LPUART_NoiseError

LPUART noise error.

enumerator kStatus_LPUART_FramingError

LPUART framing error.

enumerator kStatus_LPUART_ParityError

LPUART parity error.

enumerator kStatus_LPUART_BaudrateNotSupport

Baudrate is not support in current clock source

enumerator kStatus_LPUART_IdleLineDetected

IDLE flag.

enumerator kStatus_LPUART_Timeout

LPUART times out.

enum _lpuart_parity_mode

LPUART parity mode.

Values:

enumerator kLPUART_ParityDisabled

Parity disabled

enumerator kLPUART_ParityEven

Parity enabled, type even, bit setting: PE|PT = 10

enumerator kLPUART_ParityOdd

Parity enabled, type odd, bit setting: PE|PT = 11

enum _lpuart_data_bits

LPUART data bits count.

Values:

enumerator kLPUART_EightDataBits

Eight data bit

enumerator kLPUART_SevenDataBits

Seven data bit

enum _lpuart_stop_bit_count

LPUART stop bit count.

Values:

enumerator kLPUART_OneStopBit

One stop bit

enumerator kLPUART_TwoStopBit

Two stop bits

enum _lpuart_transmit_cts_source

LPUART transmit CTS source.

Values:

enumerator kLPUART_CtsSourcePin

CTS resource is the LPUART_CTS pin.

enumerator kLPUART_CtsSourceMatchResult

CTS resource is the match result.

enum _lpuart_transmit_cts_config

LPUART transmit CTS configure.

Values:

enumerator kLPUART_CtsSampleAtStart

CTS input is sampled at the start of each character.

enumerator kLPUART_CtsSampleAtIdle

CTS input is sampled when the transmitter is idle

enum _lpuart_idle_type_select

LPUART idle flag type defines when the receiver starts counting.

Values:

enumerator kLPUART_IdleTypeStartBit

Start counting after a valid start bit.

enumerator kLPUART_IdleTypeStopBit

Start counting after a stop bit.

enum _lpuart_idle_config

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

Values:

enumerator kLPUART_IdleCharacter1

the number of idle characters.

enumerator kLPUART_IdleCharacter2

the number of idle characters.

enumerator kLPUART_IdleCharacter4

the number of idle characters.

enumerator kLPUART_IdleCharacter8

the number of idle characters.

enumerator kLPUART_IdleCharacter16

the number of idle characters.

enumerator kLPUART_IdleCharacter32

the number of idle characters.

enumerator kLPUART_IdleCharacter64

the number of idle characters.

enumerator kLPUART_IdleCharacter128

the number of idle characters.

enum _lpuart_interrupt_enable

LPUART interrupt configuration structure, default settings all disabled.

This structure contains the settings for all LPUART interrupt configurations.

Values:

enumerator kLPUART_LinBreakInterruptEnable

LIN break detect. bit 7

enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge. bit 6

enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty. bit 23

enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete. bit 22

enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full. bit 21

enumerator kLPUART_IdleLineInterruptEnable

Idle line. bit 20

enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun. bit 27

enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag. bit 26

enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag. bit 25

enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag. bit 24

enumerator kLPUART_Match1InterruptEnable

Parity error flag. bit 15

enumerator kLPUART_Match2InterruptEnable

Parity error flag. bit 14

enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow. bit 9

enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow. bit 8

enumerator kLPUART_AllInterruptEnable

enum _lpuart_flags

LPUART status flags.

This provides constants for the LPUART status flags for use in the LPUART functions.

Values:

enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty. bit 23

enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete. bit 22

enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full. bit 21

enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected. bit 20

enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register. bit 19

enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18

enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17

enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection. bit 16

enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31

enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected. bit 30

enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start. bit 24

enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1. bit 15

enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2. bit 14

enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty. bit 7

enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty. bit 6

enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred. bit 1

enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred. bit 0

enumerator kLPUART_AllClearFlags

enumerator kLPUART_AllFlags

typedef enum _lpuart_parity_mode lpuart_parity_mode_t

LPUART parity mode.

typedef enum _lpuart_data_bits lpuart_data_bits_t

LPUART data bits count.

typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t

LPUART stop bit count.

typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t

LPUART transmit CTS source.

typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t

LPUART transmit CTS configure.

typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t

LPUART idle flag type defines when the receiver starts counting.

typedef enum _lpuart_idle_config lpuart_idle_config_t

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

typedef struct _lpuart_config lpuart_config_t

LPUART configuration structure.

typedef struct _lpuart_transfer lpuart_transfer_t

LPUART transfer structure.

typedef struct _lpuart_handle lpuart_handle_t

typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)

void *s_lpuartHandle[]

const IRQn_Type s_lpuartTxIRQ[]

lpuart_isr_t s_lpuartIsr[]

UART_RETRY_TIMES

Retry times for waiting flag.

struct _lpuart_config

#include <fsl_lpuart.h>

LPUART configuration structure.

Public Members

uint32_t baudRate_Bps

LPUART baud rate

lpuart_parity_mode_t parityMode

Parity mode, disabled (default), even, odd

lpuart_data_bits_t dataBitsCount

Data bits count, eight (default), seven

bool isMsb

Data bits order, LSB (default), MSB

lpuart_stop_bit_count_t stopBitCount

Number of stop bits, 1 stop bit (default) or 2 stop bits

uint8_t txFifoWatermark

TX FIFO watermark

uint8_t rxFifoWatermark

RX FIFO watermark

bool enableRxRTS

RX RTS enable

bool enableTxCTS

TX CTS enable

lpuart_transmit_cts_source_t txCtsSource

TX CTS source

lpuart_transmit_cts_config_t txCtsConfig

TX CTS configure

lpuart_idle_type_select_t rxIdleType

RX IDLE type.

lpuart_idle_config_t rxIdleConfig

RX IDLE configuration.

bool enableTx

Enable TX

bool enableRx

Enable RX

struct _lpuart_transfer

#include <fsl_lpuart.h>

LPUART transfer structure.

Public Members

size_t dataSize

The byte count to be transfer.

struct _lpuart_handle

#include <fsl_lpuart.h>

LPUART handle structure.

Public Members

volatile size_t txDataSize

Size of the remaining data to send.

size_t txDataSizeAll

Size of the data to send out.

volatile size_t rxDataSize

Size of the remaining data to receive.

size_t rxDataSizeAll

Size of the data to receive.

size_t rxRingBufferSize

Size of the ring buffer.

volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer.

lpuart_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state.

bool isSevenDataBits

Seven data bits flag.

bool is16bitData

16bit data bits flag, only used for 9bit or 10bit data

union __unnamed85__

Public Members

uint8_t *data

The buffer of data to be transfer.

uint8_t *rxData

The buffer to receive data.

uint16_t *rxData16

The buffer to receive data.

const uint8_t *txData

The buffer of data to be sent.

const uint16_t *txData16

The buffer of data to be sent.

union __unnamed87__

Public Members

const uint8_t *volatile txData

Address of remaining data to send.

const uint16_t *volatile txData16

Address of remaining data to send.

union __unnamed89__

Public Members

uint8_t *volatile rxData

Address of remaining data to receive.

uint16_t *volatile rxData16

Address of remaining data to receive.

union __unnamed91__

Public Members

uint8_t *rxRingBuffer

Start address of the receiver ring buffer.

uint16_t *rxRingBuffer16

Start address of the receiver ring buffer.

LPUART eDMA Driver

void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the LPUART handle which is used in transactional functions.

Note

This function disables all LPUART interrupts.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• callback – Callback function.

• userData – User data.

• txEdmaHandle – User requested DMA handle for TX DMA transfer.

• rxEdmaHandle – User requested DMA handle for RX DMA transfer.

status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART eDMA transfer structure. See lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_LPUART_TxBusy – Previous transfer on going.

• kStatus_InvalidArgument – Invalid argument.

status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• xfer – LPUART eDMA transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others fail.

• kStatus_LPUART_RxBusy – Previous transfer ongoing.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the sent data using eDMA.

This function aborts the sent data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the received data using eDMA.

This function aborts the received data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the LPUART TX register.

This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of received bytes.

This function gets the number of received bytes.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)

LPUART eDMA IRQ handle function.

This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application.

Note

This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.

Parameters:

• base – LPUART peripheral base address.

• lpuartEdmaHandle – LPUART handle pointer.

FSL_LPUART_EDMA_DRIVER_VERSION

LPUART EDMA driver version.

typedef struct _lpuart_edma_handle lpuart_edma_handle_t

typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

struct _lpuart_edma_handle

#include <fsl_lpuart_edma.h>

LPUART eDMA handle.

Public Members

lpuart_edma_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

size_t rxDataSizeAll

Size of the data to receive.

size_t txDataSizeAll

Size of the data to send out.

edma_handle_t *txEdmaHandle

The eDMA TX channel used.

edma_handle_t *rxEdmaHandle

The eDMA RX channel used.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

MECC: internal error correction code

void MECC_Init(MECC_Type *base, mecc_config_t *config)

MECC module initialization function.

Parameters:

• base – MECC base address.

• config – pointer to the MECC configuration structure.

void MECC_Deinit(MECC_Type *base)

Deinitializes the MECC.

Parameters:

• base – MECC base address.

void MECC_GetDefaultConfig(mecc_config_t *config)

Sets the MECC configuration structure to default values.

Parameters:

• config – pointer to the MECC configuration structure.

static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)

Gets MECC status flags.

Parameters:

• base – MECC peripheral base address.

Returns:

MECC status flags.

static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)

MECC module clear interrupt status.

Parameters:

• base – MECC base address.

• mask – status to clear.

static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)

MECC module enable interrupt status.

Parameters:

• base – MECC base address.

• mask – status to enable.

static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)

MECC module disable interrupt status.

Parameters:

• base – MECC base address.

• mask – status to disable.

static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)

MECC module enable interrupt.

Parameters:

• base – MECC base address.

• mask – The interrupts to enable.

static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)

MECC module disable interrupt.

Parameters:

• base – MECC base address.

• mask – The interrupts to disable.

status_t MECC_ErrorInjection(MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)

MECC module error injection.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• lowerrordata – low 32 bits data.

• higherrordata – high 32 bits data.

• eccdata – ecc code.

• banknumber – ocram bank number.

Return values:

kStatus_Success. –

status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber)

MECC module get single error information.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• info – single error information.

• banknumber – ocram bank number.

Return values:

• kStatus_Success. –

• kStatus_MECC_BankMiss. –

status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber)

MECC module get multiple error information.

Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4…..

Parameters:

• base – MECC base address.

• info – multiple error information.

• banknumber – ocram bank number.

Return values:

• kStatus_Success. –

• kStatus_MECC_BankMiss. –

static inline uint32_t MECC_GetPendingFlags(MECC_Type *base)

Get pending flags for OCRAM wait and pipeline enable.

Parameters:

• base – MECC base address.

Returns:

Pending flags, should be the OR’ed value of mecc_pending_flag_t.

FSL_MECC_DRIVER_VERSION

Driver version 2.1.0.

Error codes for the MECC driver.

Values:

enumerator kStatus_MECC_BankMiss

Ocram bank miss

MECC interrupt configuration structure, default settings all disabled.

This structure contains the settings for all of the MECC interrupt configurations.

Values:

enumerator kMECC_SingleError0InterruptEnable

Single Bit Error On Ocram Bank0 interrupt enable.

enumerator kMECC_SingleError1InterruptEnable

Single Bit Error On Ocram Bank1 interrupt enable

enumerator kMECC_SingleError2InterruptEnable

Single Bit Error On Ocram Bank2 interrupt enable

enumerator kMECC_SingleError3InterruptEnable

Single Bit Error On Ocram Bank3 interrupt enable

enumerator kMECC_MultiError0InterruptEnable

Multiple Bits Error On Ocram Bank0 interrupt enable

enumerator kMECC_MultiError1InterruptEnable

Multiple Bits Error On Ocram Bank1 interrupt enable

enumerator kMECC_MultiError2InterruptEnable

Multiple Bits Error On Ocram Bank2 interrupt enable

enumerator kMECC_MultiError3InterruptEnable

Multiple Bits Error On Ocram Bank3 interrupt enable

enumerator kMECC_StrobeError0InterruptEnable

AXI Strobe Error On Ocram Bank0 interrupt enable

enumerator kMECC_StrobeError1InterruptEnable

AXI Strobe Error On Ocram Bank1 interrupt enable

enumerator kMECC_StrobeError2InterruptEnable

AXI Strobe Error On Ocram Bank2 interrupt enable

enumerator kMECC_StrobeError3InterruptEnable

AXI Strobe Error On Ocram Bank3 interrupt enable

enumerator kMECC_AccessError0InterruptEnable

Ocram Access Error On Bank0 interrupt enable

enumerator kMECC_AccessError1InterruptEnable

Ocram Access Error On Bank1 interrupt enable

enumerator kMECC_AccessError2InterruptEnable

Ocram Access Error On Bank2 interrupt enable

enumerator kMECC_AccessError3InterruptEnable

Ocram Access Error On Bank3 interrupt enable

enumerator kMECC_AllInterruptsEnable

all interrupts enable

MECC interrupt status configuration structure, default settings all disabled.

This structure contains the settings for all of the MECC interrupt status configurations.

Values:

enumerator kMECC_SingleError0InterruptStatusEnable

Single Bit Error On Ocram Bank0 interrupt status enable.

enumerator kMECC_SingleError1InterruptStatusEnable

Single Bit Error On Ocram Bank1 interrupt status enable

enumerator kMECC_SingleError2InterruptStatusEnable

Single Bit Error On Ocram Bank2 interrupt status enable

enumerator kMECC_SingleError3InterruptStatusEnable

Single Bit Error On Ocram Bank3 interrupt status enable

enumerator kMECC_MultiError0InterruptStatusEnable

Multiple Bits Error On Ocram Bank0 interrupt status enable

enumerator kMECC_MultiError1InterruptStatusEnable

Multiple Bits Error On Ocram Bank1 interrupt status enable

enumerator kMECC_MultiError2InterruptStatusEnable

Multiple Bits Error On Ocram Bank2 interrupt status enable

enumerator kMECC_MultiError3InterruptStatusEnable

Multiple Bits Error On Ocram Bank3 interrupt status enable

enumerator kMECC_StrobeError0InterruptStatusEnable

AXI Strobe Error On Ocram Bank0 interrupt status enable

enumerator kMECC_StrobeError1InterruptStatusEnable

AXI Strobe Error On Ocram Bank1 interrupt status enable

enumerator kMECC_StrobeError2InterruptStatusEnable

AXI Strobe Error On Ocram Bank2 interrupt status enable

enumerator kMECC_StrobeError3InterruptStatusEnable

AXI Strobe Error On Ocram Bank3 interrupt status enable

enumerator kMECC_AccessError0InterruptStatusEnable

Ocram Access Error On Bank0 interrupt status enable

enumerator kMECC_AccessError1InterruptStatusEnable

Ocram Access Error On Bank1 interrupt status enable

enumerator kMECC_AccessError2InterruptStatusEnable

Ocram Access Error On Bank2 interrupt status enable

enumerator kMECC_AccessError3InterruptStatusEnable

Ocram Access Error On Bank3 interrupt status enable

enumerator kMECC_AllInterruptsStatusEnable

all interrupts enable

MECC status flags.

This provides constants for the MECC status flags for use in the MECC functions.

Values:

enumerator kMECC_SingleError0InterruptFlag

Single Bit Error On Ocram Bank0 interrupt flag

enumerator kMECC_SingleError1InterruptFlag

Single Bit Error On Ocram Bank1 interrupt flag

enumerator kMECC_SingleError2InterruptFlag

Single Bit Error On Ocram Bank2 interrupt flag

enumerator kMECC_SingleError3InterruptFlag

Single Bit Error On Ocram Bank3 interrupt flag

enumerator kMECC_MultiError0InterruptFlag

Multiple Bits Error On Ocram Bank0 interrupt flag

enumerator kMECC_MultiError1InterruptFlag

Multiple Bits Error On Ocram Bank1 interrupt flag

enumerator kMECC_MultiError2InterruptFlag

Multiple Bits Error On Ocram Bank2 interrupt flag

enumerator kMECC_MultiError3InterruptFlag

Multiple Bits Error On Ocram Bank3 interrupt flag

enumerator kMECC_StrobeError0InterruptFlag

AXI Strobe Error On Ocram Bank0 interrupt flag

enumerator kMECC_StrobeError1InterruptFlag

AXI Strobe Error On Ocram Bank1 interrupt flag

enumerator kMECC_StrobeError2InterruptFlag

AXI Strobe Error On Ocram Bank2 interrupt flag

enumerator kMECC_StrobeError3InterruptFlag

AXI Strobe Error On Ocram Bank3 interrupt flag

enumerator kMECC_AccessError0InterruptFlag

Ocram Access Error On Bank0 interrupt flag

enumerator kMECC_AccessError1InterruptFlag

Ocram Access Error On Bank1 interrupt flag

enumerator kMECC_AccessError2InterruptFlag

Ocram Access Error On Bank2 interrupt flag

enumerator kMECC_AccessError3InterruptFlag

Ocram Access Error On Bank3 interrupt flag

enumerator kMECC_AllInterruptsFlag

all interrupts interrupt flag

MECC ocram bank number.

Values:

enumerator kMECC_OcramBank0

ocram bank number 0: ocram_base_address+0x20*i

enumerator kMECC_OcramBank1

ocram bank number 1: ocram_base_address+0x20*i+0x8

enumerator kMECC_OcramBank2

ocram bank number 2: ocram_base_address+0x20*i+0x10

enumerator kMECC_OcramBank3

ocram bank number 3: ocram_base_address+0x20*i+0x18

enum _mecc_pending_flag

Pending flags for OCRAM wait and pipeline enable. .

Values:

enumerator kMECC_ReadDataWaitPendingFlag

Indicate an update pending status for read data wait.

enumerator kMECC_ReadAddrPipelinePendingFlag

Indicate an update pending status for read address pipeline.

enumerator kMECC_WriteDataPipelinePendingFlag

Indicate an update pending status for write data pipeline.

enumerator kMECC_WriteAddrPipelinePendingFlag

Indicate an update pending status for write address pipeline.

enumerator kMECC_AllPendingFlags

Indicate all pending status flags.

typedef struct _mecc_config mecc_config_t

MECC user configuration.

Note

Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

typedef struct _mecc_single_error_info mecc_single_error_info_t

MECC ocram single error information, including single error address, ECC code, error data and error bit position.

typedef struct _mecc_multi_error_info mecc_multi_error_info_t

MECC ocram multiple error information, including multiple error address, ECC code, error data.

struct _mecc_config

#include <fsl_mecc.h>

MECC user configuration.

Note

Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress are removed since 2.1.0 version; This changes will cause compile error for applications which use MECC driver before 2.1.0 version; To resolve compile error please use startAddress and endAddress as instead.

Public Members

bool enableMecc

Enable the MECC function.

uint32_t startAddress

Start address of corresponding OCRAM memory region to enable ECC.

uint32_t endAddress

end address of corresponding OCRAM memory region to enable ECC.

bool enableReadDataWait

uint32_t Ocram1StartAddress; Ocram 1 start address, deprecated since 2.1.0

uint32_t Ocram1EndAddress; Ocram 1 end address, deprecated since 2.1.0

uint32_t Ocram2StartAddress; Ocram 2 start address, deprecated since 2.1.0.

uint32_t Ocram2EndAddress; Ocram 2 end address, deprecated since 2.1.0 If enabled, 1-cycle wait state will be inserted into each read access:

• true Enable read data wait;

• false Disable read data wait.

bool enableReadAddrPipeline

If enabled, the read address will be registered before can be applied to memory cell:

• true Enable Read address pipeline;

• false Disable Read address pipeline.

bool enableWriteDataPipeline

If enabled, the write data will be registered before can be applied to memory cell:

• true Enable write data pipeline;

• false Disable write data pipeline.

bool enableWriteAddrPipeline

If enabled, write address will be registered before can be applied to memory cell:

• true Enable write address pipeline;

• false Disable write address pipeline.

struct _mecc_single_error_info

#include <fsl_mecc.h>

MECC ocram single error information, including single error address, ECC code, error data and error bit position.

Public Members

uint32_t singleErrorAddress

Single error address on Ocram bank n

uint32_t singleErrorDataLow

Single error low 32 bits uncorrected read data on Ocram bank n

uint32_t singleErrorDataHigh

Single error high 32 bits uncorrected read data on Ocram bank n

uint32_t singleErrorPosLow

Single error bit postion of low 32 bits read data on Ocram bank n

uint32_t singleErrorPosHigh

Single error bit postion of high 32 bits read data on Ocram bank n

uint8_t singleErrorEccCode

Single error ECC code on Ocram bank n

struct _mecc_multi_error_info

#include <fsl_mecc.h>

MECC ocram multiple error information, including multiple error address, ECC code, error data.

Public Members

uint32_t multiErrorAddress

Multiple error address on Ocram bank n

uint32_t multiErrorDataLow

Multiple error low 32 bits read data on Ocram bank n

uint32_t multiErrorDataHigh

Multiple error high 32 bits read data on Ocram bank n

uint8_t multiErrorEccCode

Multiple error ECC code on Ocram bank n

MSGINTR: Message Unit

MSGINTR Driver

MU: Messaging Unit

uint32_t MU_GetInstance(MU_Type *base)

Get the MU instance index.

Parameters:

• base – MU peripheral base address.

Returns:

MU instance index.

void MU_Init(MU_Type *base)

Initializes the MU module.

This function enables the MU clock only.

Parameters:

• base – MU peripheral base address.

void MU_Deinit(MU_Type *base)

De-initializes the MU module.

This function disables the MU clock only.

Parameters:

• base – MU peripheral base address.

static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register.

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – TX register index, see mu_msg_reg_index_t.

• msg – Message to send.

status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message.

This function waits until the TX register is empty and sends the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and returns kStatus_Timeout.

Parameters:

• base – MU peripheral base address.

• regIndex – MU message register, see mu_msg_reg_index_t.

• msg – Message to send.

Return values:

• kStatus_Success – Message sent successfully.

• kStatus_Timeout – Timeout occurred while waiting for TX register to be empty.

Returns:

status_t

static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register.

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue)

Blocks to receive a message with timeout protection.

This function waits until the RX register is full and receives the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

This function provides the same blocking behavior as MU_ReceiveMsg() but with additional timeout protection to prevent system hangs if the other core becomes unresponsive or if hardware issues occur.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that this function includes timeout protection while MU_ReceiveMsg() waits indefinitely.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

• readValue – Pointer to store the received message.

Return values:

• kStatus_Success – Message received successfully.

• kStatus_InvalidArgument – Invalid readValue pointer.

• kStatus_Timeout – Timeout occurred while waiting for RX register to be full.

Returns:

status_t

uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message (infinite wait, no timeout protection).

This function waits until the RX register is full and receives the message. This function will wait indefinitely until a message is received.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that MU_ReceiveMsgTimeout() includes timeout protection while this function waits indefinitely.

Warning

This function does not include timeout protection and may cause system hangs if the other core becomes unresponsive. For applications requiring timeout protection, use MU_ReceiveMsgTimeout() instead.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side.

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

status_t MU_SetFlags(MU_Type *base, uint32_t flags)

brief Blocks setting the 3-bit MU flags reflect on the other MU side.

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

return status_t retval kStatus_Success Flags were set successfully. retval kStatus_Timeout Timeout occurred while waiting for flags to update.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side.

This function gets the current 3-bit MU flags on the current side.

Parameters:

• base – MU peripheral base address.

Returns:

flags Current value of the 3-bit flags.

uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags.

This function returns the bit mask of the MU status flags. See _mu_status_flags.

uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}

If there are more than 4 general purpose interrupts, use MU_GetGeneralPurposeStatusFlags.

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU status flags, see _mu_status_flags.

static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts.

This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU IRQs pending.

static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)

Clears the specific MU status flags.

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);

If there are more than 4 general purpose interrupts, use MU_ClearGeneralPurposeStatusFlags.

Parameters:

• base – MU peripheral base address.

• flags – Bit mask of the MU status flags. See _mu_status_flags. Only the following flags can be cleared by software (if applicable for particular device), other flags are cleared by hardware:

  • kMU_GenInt0Flag

  • kMU_GenInt1Flag

  • kMU_GenInt2Flag

  • kMU_GenInt3Flag

  • kMU_MuResetInterruptFlag

  • kMU_OtherSideEnterRunInterruptFlag

  • kMU_OtherSideEnterHaltInterruptFlag

  • kMU_OtherSideEnterWaitInterruptFlag

  • kMU_OtherSideEnterStopInterruptFlag

  • kMU_OtherSideEnterPowerDownInterruptFlag

  • kMU_ResetAssertInterruptFlag

  • kMU_HardwareResetInterruptFlag

static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)

Enables the specific MU interrupts.

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

If there are more than 4 general purpose interrupts, use MU_EnableGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.

static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)

Disables the specific MU interrupts.

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

If there are more than 4 general purpose interrupts, use MU_DisableGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.

status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts)

Triggers interrupts to the other core.

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

If there are more than 4 general purpose interrupts, use MU_TriggerGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.

Return values:

• kStatus_Success – Interrupts have been triggered successfully.

• kStatus_Fail – Previous interrupts have not been accepted.

static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Enables the MU general purpose interrupts.

This function enables the MU general purpose interrupts. The interrupts to enable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_EnableInterrupts only support general interrupt 0~3, this function supports all general interrupts.

For example, to enable general purpose interrupt 0 and 3, use like this:

MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU general purpose interrupts, see mu_general_purpose_interrupt_t.

static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Disables the MU general purpose interrupts.

This function disables the MU general purpose interrupts. The interrupts to disable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_DisableInterrupts only support general interrupt 0~3, this function supports all general interrupts.

For example, to disable general purpose interrupt 0 and 3, use like this:

MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU general purpose interrupts. see mu_general_purpose_interrupt_t.

static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)

Gets the MU general purpose interrupt status flags.

This function returns the bit mask of the MU general purpose interrupt status flags. MU_GetStatusFlags can only get general purpose interrupt status 0~3, this function can get all general purpose interrupts status.

This example shows to check whether general purpose interrupt 0 and 3 happened.

uint32_t flags;
flags = MU_GetGeneralPurposeStatusFlags(base);
if (kMU_GeneralPurposeInterrupt0 & flags)
{
}
if (kMU_GeneralPurposeInterrupt3 & flags)
{
}

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU general purpose interrupt status flags.

static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)

Clear the MU general purpose interrupt status flags.

This function clears the specific MU general purpose interrupt status flags. The flags to clear should be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.

Example to clear general purpose interrupt 0 and general interrupt 1 pending flags.

MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);

Parameters:

• base – MU peripheral base address.

• flags – Bit mask of the MU general purpose interrupt status flags. See mu_general_purpose_interrupt_t.

static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags in reverse numerical order.

This function return the RX status flags in reverse order. Note: RFn bits of SR[3-0](mu status register) are mapped in ascending numerical order: RF0 -> SR[0] RF1 -> SR[1] RF2 -> SR[2] RF3 -> SR[3] This function will return these bits in reverse numerical order(RF3->RF1) to comply with MU_GetRxStatusFlags() of mu driver. See MU_GetRxStatusFlags() from drivers/mu/fsl_mu.h

status_reg = MU_GetRxStatusFlags(base);

Parameters:

• base – MU peripheral base address.

Returns:

MU RX status flags in reverse order

status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Triggers general purpose interrupts to the other core.

This function triggers the specific general purpose interrupts to the other core. The interrupts to trigger are passed in as bit mask. See mu_general_purpose_interrupt_t. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

status_t status;
status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2);

if (kStatus_Success != status)
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the interrupts to trigger. See mu_general_purpose_interrupt_t.

Return values:

• kStatus_Success – Interrupts have been triggered successfully.

• kStatus_Fail – Previous interrupts have not been accepted.

void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)

Boots the other core.

This function boots the other core with a boot configuration.

Parameters:

• base – MU peripheral base address.

• mode – The other core boot mode.

void MU_HoldOtherCoreReset(MU_Type *base)

Holds the other core reset.

This function causes the other core to be held in reset following any reset event.

Parameters:

• base – MU peripheral base address.

static inline status_t MU_ResetBothSides(MU_Type *base)

Resets the MU for both A side and B side.

This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations if waiting for the other side to come out of reset takes too long.

Note

For some platforms, only MU side A could use this function, check reference manual for details.

Parameters:

• base – MU peripheral base address.

Return values:

• kStatus_Success – The MU was reset successfully.

• kStatus_Timeout – Timeout occurred while waiting for the other side to come out of reset.

Returns:

status_t

status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)

Hardware reset the other core.

This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout if waiting for the other core to enter or exit reset takes too long.

Example 1: Reset the other core, and no hold reset

MU_HardwareResetOtherCore(MU_A, true, false, bootMode);

In this example, the core at MU side B will reset with the specified boot mode.

Example 2: Reset the other core and hold it, then boot the other core later. Here the other core enters reset, and the reset is hold

MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);

Current core boot the other core when necessary.

MU_BootOtherCore(MU_A, bootMode);

Note

The feature waitReset, holdReset, and bootMode might be not supported for some platforms. waitReset is only available for platforms that FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not defined as 0.

Parameters:

• base – MU peripheral base address.

• waitReset – Wait the other core enters reset. Only work when there is CSSR0[RAIP].

  • true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked.

  • false: Don’t wait the reset.

• holdReset – Hold the other core reset or not. Only work when there is CCR0[RSTH].

  • true: Hold the other core in reset, this function returns directly when the other core enters reset.

  • false: Don’t hold the other core in reset, this function waits until the other core out of reset.

• bootMode – Boot mode of the other core, if holdReset is true, this parameter is useless.

Return values:

• kStatus_Success – The other core was reset successfully.

• kStatus_Timeout – Timeout occurred while waiting for the other core to enter or exit reset.

Returns:

status_t

FSL_MU_DRIVER_VERSION

MU driver version.

enum _mu_status_flags

MU status flags.

Values:

enumerator kMU_Tx0EmptyFlag

TX0 empty.

enumerator kMU_Tx1EmptyFlag

TX1 empty.

enumerator kMU_Tx2EmptyFlag

TX2 empty.

enumerator kMU_Tx3EmptyFlag

TX3 empty.

enumerator kMU_Rx0FullFlag

RX0 full.

enumerator kMU_Rx1FullFlag

RX1 full.

enumerator kMU_Rx2FullFlag

RX2 full.

enumerator kMU_Rx3FullFlag

RX3 full.

enumerator kMU_GenInt0Flag

General purpose interrupt 0 pending.

enumerator kMU_GenInt1Flag

General purpose interrupt 1 pending.

enumerator kMU_GenInt2Flag

General purpose interrupt 2 pending.

enumerator kMU_GenInt3Flag

General purpose interrupt 3 pending.

enumerator kMU_RxFullPendingFlag

Any RX full flag is pending.

enumerator kMU_TxEmptyPendingFlag

Any TX empty flag is pending.

enumerator kMU_GenIntPendingFlag

Any general interrupt flag is pending.

enumerator kMU_EventPendingFlag

MU event pending.

enumerator kMU_FlagsUpdatingFlag

MU flags update is on-going.

enumerator kMU_MuInResetFlag

MU of any side is in reset.

enumerator kMU_MuResetInterruptFlag

The other side initializes MU reset.

enum _mu_interrupt_enable

MU interrupt source to enable.

Values:

enumerator kMU_Tx0EmptyInterruptEnable

TX0 empty.

enumerator kMU_Tx1EmptyInterruptEnable

TX1 empty.

enumerator kMU_Tx2EmptyInterruptEnable

TX2 empty.

enumerator kMU_Tx3EmptyInterruptEnable

TX3 empty.

enumerator kMU_Rx0FullInterruptEnable

RX0 full.

enumerator kMU_Rx1FullInterruptEnable

RX1 full.

enumerator kMU_Rx2FullInterruptEnable

RX2 full.

enumerator kMU_Rx3FullInterruptEnable

RX3 full.

enumerator kMU_GenInt0InterruptEnable

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptEnable

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptEnable

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptEnable

General purpose interrupt 3.

enumerator kMU_MuResetInterruptEnable

The other side initializes MU reset.

enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core.

Values:

enumerator kMU_GenInt0InterruptTrigger

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptTrigger

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptTrigger

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptTrigger

General purpose interrupt 3.

enum _mu_msg_reg_index

MU message register index.

Values:

enumerator kMU_MsgReg0

Message register 0.

enumerator kMU_MsgReg1

Message register 1.

enumerator kMU_MsgReg2

Message register 2.

enumerator kMU_MsgReg3

Message register 3.

enum _mu_general_purpose_interrupt

MU general purpose interrupts.

Values:

enumerator kMU_GeneralPurposeInterrupt0

General purpose interrupt 0

enumerator kMU_GeneralPurposeInterrupt1

General purpose interrupt 1

enumerator kMU_GeneralPurposeInterrupt2

General purpose interrupt 2

enumerator kMU_GeneralPurposeInterrupt3

General purpose interrupt 3

typedef enum _mu_msg_reg_index mu_msg_reg_index_t

MU message register index.

typedef enum _mu_general_purpose_interrupt mu_general_purpose_interrupt_t

MU general purpose interrupts.

MU_CORE_INTR(intr)

MU_MISC_INTR(intr)

MU_TX_INTR(intr)

MU_RX_INTR(intr)

MU_GI_INTR(intr)

MU_GET_CORE_INTR(intrs)

MU_GET_TX_INTR(intrs)

MU_GET_RX_INTR(intrs)

MU_GET_GI_INTR(intrs)

MU_CORE_FLAG(flag)

MU_STAT_FLAG(flag)

MU_TX_FLAG(flag)

MU_RX_FLAG(flag)

MU_GI_FLAG(flag)

MU_GET_CORE_FLAG(flags)

MU_GET_STAT_FLAG(flags)

MU_GET_TX_FLAG(flags)

MU_GET_RX_FLAG(flags)

MU_GET_GI_FLAG(flags)

MU1_BUSY_POLL_COUNT

Maximum polling iterations for MU waiting loops.

This parameter defines the maximum number of iterations for any polling loop in the MU code before timing out and returning an error.

It applies to all waiting loops in MU driver, such as waiting for TX register to be empty or waiting for RX register to be full.

This is a count of loop iterations, not a time-based value.

If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if a core becomes unresponsive.

NETC driver

Status code for the NETC module.

Values:

enumerator kStatus_NETC_RxFrameEmpty

Rx BD ring empty.

enumerator kStatus_NETC_RxTsrResp

Rx timestamp reference response

enumerator kStatus_NETC_RxFrameError

Rx frame error.

enumerator kStatus_NETC_TxFrameOverLen

Tx frame over length.

enumerator kStatus_NETC_LackOfResource

Lack of resources to configure certain features.

enumerator kStatus_NETC_Unsupported

Unsupported operation/feature.

enumerator kStatus_NETC_RxHRZeroFrame

Rx frame host reason is zero

enumerator kStatus_NETC_RxHRNotZeroFrame

Rx frame host reason is not zero

enumerator kStatus_NETC_NotFound

No entry found in hardware tables

enumerator kStatus_NETC_EntryExists

An entry already exists in hardware tables

enum _netc_ep_event

Defines the common interrupt event for callback use.

Values:

enumerator kNETC_EPRxEvent

EP Rx interrupt event.

enumerator kNETC_EPTxEvent

EP Tx interrupt event.

enum _netc_ep_tx_status

Status for the transmit buffer descriptor.

Values:

enumerator kNETC_EPTxSuccess

Success transmission.

enumerator kNETC_EPTxProgramErr

Error exists in either the Tx BD, the Tx ring registers, or both.

enumerator kNETC_EPTxTsdDrop

The time defined in TX_START expired before frame could be transmitted.

enumerator kNETC_EPTxFrameSizeErr

Frame size error.

enumerator kNETC_EPTxNullAddr

Null address.

enumerator kNETC_EPTxInvalidLength

Invalid frame/buffer/chain length.

enumerator kNETC_EPTxSrcMacSpoofingDetect

Source MAC address spoofing detected.

enumerator kNETC_EPTxPortRestDrop

Frame dropped due to port reset.

enumerator kNETC_EPTxPortDisableDrop

Frame dropped due to port disable.

enumerator kNETC_EPTxVlanTpidDrop

VLAN TPID not allowed.

enumerator kNETC_EPTxSmsoParamErr

Programming error in buffer descriptor used for direct switch enqueue.

enumerator kNETC_EPTxFrameGateErr

Frame too large for time gating window.

enumerator kNETC_EPTxAxiReadErr

AXI read error.

enumerator kNETC_EPTxAxiWriteErr

AXI write error.

enumerator kNETC_EPTxMultiBitECCErr

Frame not transmitted(dropped) due to a multi-bit ECC error detected.

enumerator kNETC_EPTxParityErr

Parity error.

enumerator kNETC_EPTxSwCongestion

Frame dropped due to switch congestion.

enum _netc_vlan_tpid_select

Ethernet VLAN Tag protocol identifier.

Values:

enumerator kNETC_StanCvlan

0x8100.

enumerator kNETC_StanSvlan

0x88A8.

enumerator kNETC_CustomVlan1

CVLANR1[ETYPE]

enumerator kNETC_CustomVlan2

CVLANR2[ETYPE]

enum _netc_packet_type

Ethernet packet type enumerator.

Values:

enumerator kNETC_PacketUnicast

enumerator kNETC_PacketMulticast

enumerator kNETC_PacketBroadcast

enum _netc_host_reason

Host reason.

Values:

enumerator kNETC_RegularFrame

enumerator kNETC_IngressMirror

enumerator kNETC_MACLearning

enumerator kNETC_TimestampResp

enumerator kNETC_SoftwareDefHR0

enumerator kNETC_SoftwareDefHR1

enumerator kNETC_SoftwareDefHR2

enumerator kNETC_SoftwareDefHR3

enumerator kNETC_SoftwareDefHR4

enumerator kNETC_SoftwareDefHR5

enumerator kNETC_SoftwareDefHR6

enumerator kNETC_SoftwareDefHR7

enum _netc_msix_vector_ctrl

MSIX vector control field.

Values:

enumerator kNETC_MsixIntrMaskBit

MSIX vector control interrupt mask bit.

enum _netc_tx_ext_flags

METC Extension Transmit Buffer Descriptor Extension flags field.

Values:

enumerator kNETC_TxExtVlanInsert

Enable VLAN insert.

enumerator kNETC_TxExtTwoStepTs

Enable two-step timestamp offload.

typedef enum _netc_ep_event netc_ep_event_t

Defines the common interrupt event for callback use.

typedef enum _netc_ep_tx_status netc_ep_tx_status_t

Status for the transmit buffer descriptor.

typedef struct _netc_vlan netc_vlan_t

VLAN tag struct.

typedef enum _netc_vlan_tpid_select netc_vlan_tpid_select_t

Ethernet VLAN Tag protocol identifier.

typedef enum _netc_packet_type netc_packet_type_t

Ethernet packet type enumerator.

typedef enum _netc_host_reason netc_host_reason_t

Host reason.

typedef struct _ep_buffer_struct netc_buffer_struct_t

Buffer structure. Driver can send/receive one frame spread across multiple buffers.

typedef struct _ep_frame_struct netc_frame_struct_t

Frame structure for single Tx/Rx frame.

typedef struct _netc_frame_attr_struct netc_frame_attr_t

Frame attribute struct.

typedef struct _netc_tx_frame_info_struct netc_tx_frame_info_t

Frame attribute structure.

typedef enum _netc_msix_vector_ctrl netc_msix_vector_ctrl_t

MSIX vector control field.

typedef struct _netc_msix_entry netc_msix_entry_t

NETC MSIX entry structure.

typedef enum _netc_tx_ext_flags netc_tx_ext_flags_t

METC Extension Transmit Buffer Descriptor Extension flags field.

FSL_NETC_DRIVER_VERSION

Driver Version.

NETC_ADDR_LOW_32BIT(x)

Macro to divides an address into a low 32 bits and a possible high 32 bits.

NETC_ADDR_HIGH_32BIT(x)

struct _netc_vlan

#include <fsl_netc.h>

VLAN tag struct.

Public Members

uint32_t vid

Vlan Identifier.

uint32_t dei

Drop Eligible indicator.

uint32_t pcp

Priority.

uint32_t tpid

Tag protocol identifier.

struct _ep_buffer_struct

#include <fsl_netc.h>

Buffer structure. Driver can send/receive one frame spread across multiple buffers.

Public Members

void *buffer

Buffer address.

uint16_t length

Buffer data length.

struct _ep_frame_struct

#include <fsl_netc.h>

Frame structure for single Tx/Rx frame.

Public Members

netc_buffer_struct_t *buffArray

Buffer array. Tx: [in]App sets, Rx: [in/out]App sets prepared array, driver sets back received buffers array.

uint16_t length

Buffer array length. Tx: [in]App sets, Rx: [in/out]App sets prepared array length, driver sets back received buffers array length.

struct _netc_frame_attr_struct

#include <fsl_netc.h>

Frame attribute struct.

Public Members

bool isTsAvail

Rx frame timestamp is available or not.

bool isVlanExtracted

Rx frame VLAN header is available or not.

uint32_t timestamp

The timestamp of this Rx frame.

struct _netc_tx_frame_info_struct

#include <fsl_netc.h>

Frame attribute structure.

Public Members

bool isTsAvail

Tx frame timestamp is available or not.

uint32_t timestamp

The timestamp of this Tx frame, valid when isTsAvail is true.

void *context

Private context provided by the user.

netc_ep_tx_status_t status

Transmit status.

struct _netc_msix_entry

#include <fsl_netc.h>

NETC MSIX entry structure.

Public Members

uint64_t msgAddr

Message address.

uint32_t msgData

Message data.

uint32_t control

Vector control, netc_msix_vector_ctrl_t.

Abbreviation in NETC driver

API layer

NETC Endpoint (EP) Driver

Endpoint (EP) Generic Configuration

typedef struct _ep_handle ep_handle_t

Endpoint handle.

typedef status_t (*ep_reclaim_cb_t)(ep_handle_t *handle, uint8_t ring, netc_tx_frame_info_t *frameInfo, void *userData)

Callback for reclaimed tx frames.

typedef void *(*ep_rx_alloc_cb_t)(ep_handle_t *handle, uint8_t ring, uint32_t length, void *userData)

Defines the EP Rx memory buffer alloc function pointer.

typedef void (*ep_rx_free_cb_t)(ep_handle_t *handle, uint8_t ring, void *address, void *userData)

Defines the EP Rx memory buffer free function pointer.

typedef status_t (*ep_get_link_status_cb_t)(ep_handle_t *handle, uint8_t *link)

Callback for getting link status.

typedef status_t (*ep_get_link_speed_cb_t)(ep_handle_t *handle, netc_hw_mii_speed_t *speed, netc_hw_mii_duplex_t *duplex)

Callback for getting link speed.

typedef status_t (*ep_preinit_vsi_cb_t)(netc_enetc_hw_t *hw, netc_hw_si_idx_t si)

Callback for vsi pre-init.

typedef struct _ep_config ep_config_t

Configuration for the endpoint handle.

typedef struct _ep_config_const ep_config_const_t

Configuration constant in handle.

status_t EP_Init(ep_handle_t *handle, uint8_t *macAddr, const ep_config_t *config, const netc_bdr_config_t *bdrConfig)

Initialize the endpoint with specified station interface.

Each station interface needs to call this API. In the case of a virtual station interface it’s necessary that the physical station interface has been initialized beforehand.

Parameters:

• handle –

• macAddr – Primary MAC address

• config – The user configuration

• bdrConfig – Array of buffer configurations (for each queue/ring)

Returns:

status_t

status_t EP_Deinit(ep_handle_t *handle)

De-initialize the endpoint.

Parameters:

• handle –

Returns:

status_t

status_t EP_GetDefaultConfig(ep_config_t *config)

Get the default configuration.

Parameters:

• config –

Returns:

status_t

status_t EP_Up(ep_handle_t *handle, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)

Enable MAC transmission/reception To be called when the PHY link is up.

Parameters:

• handle –

• speed –

• duplex –

Returns:

status_t

status_t EP_Down(ep_handle_t *handle)

Disable MAC transmission/reception To be called when the PHY link is down.

Note

Must ensure all active Tx rings finish current transmission before call this API.

Parameters:

• handle –

Returns:

status_t

status_t EP_SetPrimaryMacAddr(ep_handle_t *handle, uint8_t *macAddr)

Set the Primary MAC address.

Parameters:

• handle –

• macAddr –

Returns:

status_t

static inline void EP_SetPortSpeed(ep_handle_t *handle, uint16_t pSpeed)

Set EP port speed.

Parameters:

• handle –

• pSpeed –

struct _ep_config

#include <fsl_netc_endpoint.h>

Configuration for the endpoint handle.

Public Members

netc_hw_si_idx_t si

Station interface index.

netc_hw_enetc_si_config_t siConfig

Station interface configuration.

uint8_t txPrioToTC[8]

Tx BD ring priority to Tx traffic class queue index mapping, range in TC0 ~ TC7.

netc_port_tx_tc_config_t txTcCfg[8]

Tx traffic class related configuration, vaild only on ENETC 0.

netc_ep_psfp_config_t psfpCfg

PSFP configuration,cover the ISI key construction profile and port ingress stream identification configuration.

bool enOuterAsInner

Enable use outer VLAN tag as the inner tag if only one tag is found.

netc_enetc_native_vlan_config_t rxOuterVLANCfg

Port outer native VLAN config.

netc_enetc_native_vlan_config_t rxInnerVLANCfg

Port inner native VLAN config.

netc_enetc_parser_config_t parserCfg

ENETC parser configuration.

uint32_t pauseOnThr

ENETC Port pause ON threshold value, value 0 means disables pause generation.

uint32_t pauseOffThr

ENETC Port pause OFF threshold value, value 0 means disables pause generation.

netc_msix_entry_t *msixEntry

MSIX table entry array.

uint8_t entryNum

MSIX entry number.

uint8_t cmdBdEntryIdx

MSIX entry index of command BD ring interrupt.

uint8_t siComEntryIdx

MSIX entry index of PSI-VSI communication interrupt.

uint8_t timerSyncEntryIdx

MSIX entry index of timer synchronous state change interrupt.

ep_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx frames.

void *userData

User data, return in callback.

bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver.

bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver.

bool rxZeroCopy

Enable/Disable zero-copy receive mode.

ep_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx.

ep_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx.

ep_preinit_vsi_cb_t preinitVsi

Callback function to pre-init VSI

netc_cmd_bdr_config_t cmdBdrConfig

Command BD ring configuration.

struct _ep_config_const

#include <fsl_netc_endpoint.h>

Configuration constant in handle.

Public Members

netc_hw_si_idx_t si

Station interface index.

uint32_t rxRingUse

Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings.

uint32_t txRingUse

Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0.

uint32_t rxBdrGroupNum

Rx BD ring group number, range in 0 ~ 2.

uint32_t ringPerBdrGroup

The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero.

bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver.

bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver.

bool rxZeroCopy

Enable/Disable zero-copy receive mode.

uint8_t entryNum

MSIX entry number.

ep_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx frames.

void *userData

User data, return in callback.

ep_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx.

ep_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx.

struct _ep_handle

#include <fsl_netc_endpoint.h>

Handle for the endpoint Private internal data.

Public Members

netc_enetc_hw_t hw

Hardware register map resource.

netc_enetc_cap_t capability

ENETC capability.

ep_config_const_t cfg

Endpoint configuration constant.

uint8_t ringShift

Endpoint Tx ring shift.

netc_rx_bdr_t rxBdRing[1]

Receive buffer descriptor ring.

netc_tx_bdr_t txBdRing[1]

Transmit buffer descriptor ring.

netc_cmd_bdr_t cmdBdRing

Command BD ring handle for endpoint.

uint8_t unicastHashCount[64]

Unicast hash index collisions counter.

uint8_t multicastHashCount[64]

Multicast hash index collisions counter.

uint8_t vlanHashCount[64]

VLAN hash index collisions counter.

uint8_t macFilterCount[64]

mac address filter index collisions counter.

uint8_t vlanFilterCount[64]

vlan address filter index collisions counter.

ep_get_link_status_cb_t getLinkStatus

Callback to get link status

ep_get_link_speed_cb_t getLinkSpeed

Callback to get link speed

uint16_t vsiBitMapNotifyLinkStatus

VSI bit map for link status notify

uint16_t vsiBitMapNotifyLinkSpeed

VSI bit map for link speed notify

struct port

Public Members

netc_port_ethmac_t ethMac

Ethernet MAC configuration.

netc_port_common_t common

Port common configuration.

bool enableTg

Enable port time gate scheduling.

bool enPseudoMacTxPad

Enable pseudo MAC Port Transmit Padding, will pad the frame to a minimum of 60 bytes and append 4 octets of FCS.

Endpoint (EP) data path

typedef struct _netc_ep_ipf_config netc_ep_ipf_config_t

Port Ingress Filter config.

typedef struct _netc_ep_psfp_config netc_ep_psfp_config_t

PSFP config.

struct _netc_ep_ipf_config

#include <fsl_netc_endpoint.h>

Port Ingress Filter config.

Public Members

netc_ipf_config_t dosCfg

Configuration for L2/3 DOS.

netc_port_ipf_config_t portConfig

Configuration for port connected to enetc peripheral.

struct _netc_ep_psfp_config

#include <fsl_netc_endpoint.h>

PSFP config.

Endpoint (EP) Interrupt Module

enum _ep_interrupt_flag

Interrupt enable/disable flags.

The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER

Values:

enumerator kNETC_EPPSIResetInterruptEnable

enumerator kNETC_EPPSIMsgRxInterruptEnable

typedef enum _ep_interrupt_flag ep_interrupt_flag_t

Interrupt enable/disable flags.

The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER

static inline void EP_CleanTxIntrFlags(ep_handle_t *handle, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)

Clean the SI transmit interrupt flags.

Parameters:

• handle – The EP handle.

• txFrameIntrMask – IPV value to be mapped, bit x represents ring x.

• txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x.

static inline void EP_CleanRxIntrFlags(ep_handle_t *handle, uint32_t rxIntrMask)

Clean the SI receive interrupt flags.

Parameters:

• handle – The EP handle.

• rxIntrMask – Rx interrupt bit mask, bit x represents ring x.

status_t EP_MsixSetGlobalMask(ep_handle_t *handle, bool mask)

Set the global MSIX mask status.

This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.

Parameters:

• handle – The EP handle

• mask – The mask state. True: Mask, False: Unmask.

Returns:

status_t

status_t EP_MsixSetEntryMask(ep_handle_t *handle, uint8_t entryIdx, bool mask)

Set the MSIX entry mask status for specified entry.

This function masks/unmasks MSIX message for specified entry.

Parameters:

• handle – The EP handle

• entryIdx – The entry index in the table.

• mask – The mask state. True: Mask, False: Unmask.

Returns:

status_t

status_t EP_MsixGetPendingStatus(ep_handle_t *handle, uint8_t pbaIdx, uint64_t *status)

Get the MSIX pending status in MSIX PBA table.

This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.

Parameters:

• handle – The EP handle

• pbaIdx – The index of PBA array with 64-bit unit.

• status – Pending status bit mask, bit n for entry n.

Returns:

status_t

Endpoint (EP) Table Management Module

status_t EP_CmdBDRInit(ep_handle_t *handle, const netc_cmd_bdr_config_t *config)

Initialize endpoint command BD ring.

Parameters:

• handle –

• config – The command BD ring configuration

Returns:

status_t

status_t EP_CmdBDRDeinit(ep_handle_t *handle)

Deinit endpoint command BD ring.

Parameters:

• handle –

Returns:

status_t

Endpoint (EP) PSI/VSI

void EP_PsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)

PSI enables/disables specified interrupt.

Parameters:

• handle – The EP handle.

• mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

• enable – Enable/Disable the interrupt.

uint32_t EP_PsiGetStatus(ep_handle_t *handle)

PSI gets interrupt event flag status.

Parameters:

• handle – The EP handle.

Returns:

The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

void EP_PsiClearStatus(ep_handle_t *handle, uint32_t mask)

PSI clears interrupt event flag.

Parameters:

• handle – The EP handle.

• mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

status_t EP_PsiSendMsg(ep_handle_t *handle, uint16_t msg, netc_vsi_number_t vsi)

PSI sends message to specified VSI(s)

Parameters:

• handle – The EP handle.

• msg – The message to be sent.

• vsi – The VSI number.

Returns:

status_t

bool EP_PsiCheckTxBusy(ep_handle_t *handle, netc_vsi_number_t vsi)

PSI checks Tx busy flag which should be cleaned when VSI receive the message data.

Parameters:

• handle – The EP handle.

• vsi – The VSI number.

Returns:

The busy status of specified VSI.

status_t EP_PsiSetRxBuffer(ep_handle_t *handle, netc_vsi_number_t vsi, uint64_t buffAddr)

PSI sets Rx buffer to receive message from specified VSI.

Note

The buffer memory size should be big enough for the message data from VSI

Parameters:

• handle – The EP handle.

• vsi – The VSI number.

• buffAddr – The buffer address to store message data from VSI.

status_t EP_PsiGetRxMsg(ep_handle_t *handle, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)

PSI gets Rx message from specified VSI.

Parameters:

• handle – The EP handle.

• vsi – The VSI number.

• msgInfo – The Rx message information.

void EP_VsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)

Enable VSI interrupt.

Parameters:

• handle – The EP handle.

• mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.

• enable – Enable/Disable interrupt.

uint32_t EP_VsiGetStatus(ep_handle_t *handle)

Get VSI interrupt status.

Parameters:

• handle – The EP handle.

Returns:

A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together.

void EP_VsiClearStatus(ep_handle_t *handle, uint32_t mask)

Clear VSI interrupt status.

Parameters:

• handle – The EP handle.

• mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.

status_t EP_VsiSendMsg(ep_handle_t *handle, uint64_t msgAddr, uint32_t msgLen)

VSI sends message to PSI.

Parameters:

• handle – The EP handle.

• msgAddr – Address to store message ready to be sent, must be 64 bytes aligned.

• msgLen – The message length, must be 32 bytes aligned.

Returns:

status_t

void EP_VsiCheckTxStatus(ep_handle_t *handle, netc_vsi_msg_tx_status_t *status)

Check VSI Tx status.

Parameters:

• handle – The EP handle.

• status – The VSI Tx status structure.

status_t EP_VsiReceiveMsg(ep_handle_t *handle, uint16_t *msg)

VSI receives message from PSI.

Parameters:

• handle – The EP handle.

• msg – The message from PSI.

Returns:

status_t

Endpoint (EP) Ingress data path configuration

static inline status_t EP_RxParserConfig(ep_handle_t *handle, netc_port_parser_config_t *config)

Configure Parser in Receive Data Path.

Parameters:

• handle –

• config –

Returns:

status_t

static inline status_t EP_RxVlanCInit(ep_handle_t *handle, const netc_vlan_classify_config_t *config)

Configure the customer vlan type.

Parameters:

• handle –

• config –

Returns:

status_t

static inline status_t EP_RxVlanCConfigPort(ep_handle_t *handle, netc_port_vlan_classify_config_t *config)

Configure the Accepted Vlan.

Parameters:

• handle –

• config –

Returns:

status_t

status_t EP_RxIPFInit(ep_handle_t *handle, netc_ep_ipf_config_t *config)

Enable / Disable Ingress Port Filtering.

Applied for both Switch and ENETC

Parameters:

• handle –

• config – IPF general features

Returns:

status_t

static inline uint32_t EP_RxIPFGetTableRemainWordNum(ep_handle_t *handle)

Get remaining available word number (words size is 6 bytes) of the ingress Port Filter Table.

Note

This is a ternary match table, and the entries can vary in size, from 2 to 14 words.

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxIPFAddTableEntry(ep_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)

Add an entry for the ingress Port Filter Table.

This function do an add & query with return hardware id which can be used as future query / delete / update.

Parameters:

• handle –

• config – IPF instance configuaration

• entryID – The table entry ID read out

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxIPFUpdateTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)

Update entry in the ingress Port Filter Table.

Parameters:

• handle –

• entryID –

• cfg –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxIPFDelTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry for the ingress Port Filter Table.

Parameters:

• handle –

• entryID – The table entry ID

Returns:

status_t

status_t EP_RxIPFResetMatchCounter(ep_handle_t *handle, uint32_t entryID)

Reset the counter of an ingress port filter entry.

Parameters:

• handle –

• entryID – The table entry ID

Returns:

status_t

status_t EP_RxIPFGetMatchedCount(ep_handle_t *handle, uint32_t entryID, uint64_t *count)

Get the matched count for entry in IPF.

Parameters:

• handle –

• entryID – The table entry ID

• count – A count of how many times this entry has been matched.

Returns:

status_t

static inline status_t EP_RxPSFPInit(ep_handle_t *handle, const netc_ep_psfp_config_t *config)

Init the ENETC PSFP, inlcude.

Parameters:

• handle –

• config –

Returns:

status_t

static inline uint32_t EP_RxPSFPGetISITableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of stream identification table.

Note

This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Filter, table.

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddISITableEntry(ep_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)

Add an entry into the stream identification table.

Parameters:

• handle –

• config –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelISITableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

static inline uint32_t EP_RxPSFPGetISTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of ingress stream table.

Note

This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)

Add an entry into the ingress stream table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPUpdateISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)

Update an entry in the ingress stream table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelISTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table.

Parameters:

• handle –

• entryID –

Returns:

status_t

static inline uint32_t EP_RxPSFPGetISFTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of ingress stream filter table.

Note

This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification table.

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddISFTableEntry(ep_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)

Add an entry into the ingress stream filter table.

Parameters:

• handle –

• config –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPUpdateISFTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)

Update an entry into the ingress stream filter table.

Parameters:

• handle –

• entryID –

• cfg –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelISFTableEntry(ep_handle_t *handle, uint32_t entryID)

Del an entry into the stream filter table.

Parameters:

• handle –

• entryID –

Returns:

status_t

static inline uint32_t EP_RxPSFPGetRPTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of Rate Policer table.

Note

This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Add entry to Rate Policer table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Update entry in Rate Policer table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPAddOrUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Add or update entry in Rate Policer table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelRPTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry in the Rate Policer table.

Parameters:

• handle –

• entryID –

Returns:

status_t

status_t EP_RxPSFPGetRPStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)

Get statistic of specified Rate Policer entry.

Parameters:

• handle –

• entryID –

• statis –

Returns:

status_t

Returns:

See netc_cmd_error_t

static inline uint32_t EP_RxPSFPGetISCTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of ingress stream count table.

Note

This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddISCTableEntry(ep_handle_t *handle, uint32_t entryID)

Add entry in ingress stream count table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPGetISCStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)

Get ingress stream count statistic.

Parameters:

• handle –

• entryID –

• statistic –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPResetISCStatistic(ep_handle_t *handle, uint32_t entryID)

Reset the count of the ingress stream count.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

static inline uint32_t EP_RxPSFPGetSGITableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of stream gate instance table.

Note

This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)

Add entry in stream gate instance table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPUpdateSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)

Update entry in stream gate instance table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelSGITableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry in stream gate instance table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPGetSGIState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state)

Get state of the stream gate instance for specified entry.

Parameters:

• handle –

• entryID –

• state –

Returns:

status_t

Returns:

See netc_cmd_error_t

static inline uint32_t EP_RxPSFPGetSGCLTableRemainWordNum(ep_handle_t *handle)

Get remaining available words number of Stream Gate Control List table.

Note

This is a dynamic bounded index table, and number of words required for a stream gate control list is 1+N/2 where N is number of gate time slots in the stream gate control list. The remaining word should be greater than the want added entry size

Parameters:

• handle –

Returns:

uint32_t

status_t EP_RxPSFPAddSGCLTableEntry(ep_handle_t *handle, netc_tb_sgcl_gcl_t *config)

Add entry into Stream Gate Control List Table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPDelSGCLTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry of Stream Gate Control List Table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPGetSGCLGateList(ep_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)

Get Stream Gate Control List Table entry gate control list.

Parameters:

• handle –

• gcl –

• length –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxPSFPGetSGCLState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)

Get state (ref count) for Stream Gate Control List table entry.

Parameters:

• handle –

• entryID –

• state –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxL2MFInit(ep_handle_t *handle, netc_si_l2mf_config_t *config)

Init the L2 MAC Filter for a specified SI.

Parameters:

• handle – EP handle

• config – The L2 MAC Filter configuration

Returns:

status_t

status_t EP_RxL2MFAddHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)

Add entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

• handle – EP handle

• type – Unicast or multicast MAC address

• macAddr – MAC address to be added in filter table

Returns:

status_t

status_t EP_RxL2MFDelHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)

Delete entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

• handle – EP handle

• type – Unicast or multicast MAC address

• macAddr – MAC address to be deleted from filter table

Returns:

status_t

status_t EP_RxL2MFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint8_t *macAddr)

Add entry into the MAC filter exact match table.

The entry is associated to the current Station Interface

Parameters:

• handle –

• idx – Index in the entry table

• macAddr – MAC address for filter

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxL2MFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)

Delete entry into the MAC filter exact match table.

Parameters:

• handle – EP handle

• idx – Index in the entry table

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxL2VFInit(ep_handle_t *handle, netc_si_l2vf_config_t *config)

For VLAN filter, use inner vlan tag or outer vlan tag.

Parameters:

• handle –

• config –

Returns:

status_t

status_t EP_RxL2VFAddHashEntry(ep_handle_t *handle, uint16_t vlanId)

Add entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

• handle –

• vlanId – VLAN identifier for filter

Returns:

status_t

status_t EP_RxL2VFDelHashEntry(ep_handle_t *handle, uint16_t vlanId)

Delete entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

• handle –

• vlanId – VLAN identifier for filter

Returns:

status_t

status_t EP_RxL2VFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint16_t vlanId, netc_vlan_tpid_select_t tpid)

Add entry into the MAC filter exact match table.

The entry is associated to the current Station Interface

Parameters:

• handle –

• idx – Index in the entry table

• vlanId – VLAN identifier

• tpid – VLAN TPID

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_RxL2VFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)

Delete entry into the VLAN filter exact match table.

Parameters:

• handle –

• idx – Index in the entry table

Returns:

status_t

Returns:

See netc_cmd_error_t

static inline status_t EP_RxMapVlanToIpv(ep_handle_t *handle, netc_vlan_t vlan, uint8_t ipv)

Set the received Frame vlan to IPV mapping.

Parameters:

• handle –

• vlan – Frame VLAN tag.

• ipv – The IPV value to be mapped.

Returns:

status_t

static inline status_t EP_RxMapIpvToRing(ep_handle_t *handle, uint8_t ipv, uint8_t ring)

Set the IPV to Rx ring mapping.

Parameters:

• handle –

• ipv – IPV value to be mapped.

• ring – The Rx BD ring index to be mapped.

Returns:

status_t

static inline status_t EP_RxSetDefaultBDRGroup(ep_handle_t *handle, netc_hw_enetc_si_rxr_group groupIdx)

Set the default used receive Rx BD ring group.

Note

The IPV mapped ring index is the relative index inside the default used group.

Parameters:

• handle –

• groupIdx – The default Rx group index.

Returns:

status_t

Endpoint (EP) Statistic Module

enum _ep_flags

Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR.

Values:

enumerator kNETC_EPTimerSyncedFlag

enumerator kNETC_EPICMBlockedFlag

enumerator kNETC_EPWakeOnLANActiveFlag

typedef enum _ep_flags ep_flags_t

Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR.

static inline status_t EP_GetPortDiscardStatistic(ep_handle_t *handle, bool useTx, netc_port_discard_statistic_t *statistic)

Get the ENETC port discard statistic and reason.

Get the discarded count of frames and its reasons.

Parameters:

• handle –

• useTx – true - Tx port. false - Rx port.

• statistic – pointer to the statistic data

Returns:

status_t

static inline status_t EP_ClearPortDiscardReason(ep_handle_t *handle, bool useTx, uint32_t reason0, uint32_t reason1)

Clean the EP Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.

Parameters:

• handle –

• useTx – true - Tx port. false - Rx port.

• reason0 –

• reason1 –

Returns:

status_t

static inline uint32_t EP_GetPortTGSListStatus(ep_handle_t *handle)

Get EP port time gate scheduling gate list status.

Parameters:

• handle –

Returns:

Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t

Endpoint (EP) Egress data path configuration

status_t EP_TxTGSConfigAdminGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *config)

Config the Time Gate Scheduling entry admin gate control list.

This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_TxPortTGSEnable(ep_handle_t *handle, bool enable, uint8_t gateState)

Enable the EP port time gate scheduling.

Parameters:

• handle –

• enable –

• gateState –

Returns:

status_t

status_t EP_TxtTGSGetOperGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)

Get Time Gate Scheduling entry operation gate control list.

This function is used to read the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

• handle –

• gcl –

• length –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t EP_TxTrafficClassConfig(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config)

Config the TC (traffic class) property.

Parameters:

• handle –

• tcIdx –

• config –

Returns:

status_t

static inline void EP_TxTcConfigPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const bool enable)

Config Preemption for each port TC (traffic class)

Parameters:

• handle –

• tcIdx –

• enable –

static inline void EP_TxGetTcPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, bool *enabled)

Get Preemption configuration for each port TC (traffic class)

Parameters:

• handle –

• tcIdx –

• enabled –

static inline void EP_TxPortEthMacConfigPreemption(ep_handle_t *handle, const netc_port_preemption_config *config)

Configure Preemption control configuration for an ethernet MAC.

Parameters:

• handle –

• config –

static inline void EP_TxPortGetEthMacPreemption(ep_handle_t *handle, netc_port_preemption_config *config, netc_port_phy_mac_preemption_status_t *status)

Get Preemption configuration from ethernet MAC port.

Parameters:

• handle –

• config –

• status –

Endpoint (EP) Transmit/Receive

enum _ep_rx_flags

Values:

enumerator kEP_RX_RSS_VALID

Request timestamp.

enumerator kEP_RX_VLAN_VALID

Specifiy frame departure time.

enumerator kEP_RX_TIMESTAMP_VALID

Enable port masquerading.

enum _ep_tx_opt_flags

Values:

enumerator kEP_TX_OPT_REQ_TS

Request timestamp (IEEE 1588 PTP two-step timestamp).

enumerator kEP_TX_OPT_VLAN_INSERT

Enable VLAN insert.

enumerator kEP_TX_OPT_START_TIME

Specifiy frame departure time.

typedef enum _ep_rx_flags ep_rx_flags_t

typedef enum _ep_tx_opt_flags ep_tx_opt_flags

typedef struct _ep_tx_offload netc_tx_offload_t

typedef struct _ep_tx_opt ep_tx_opt

status_t EP_SendFrameCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, netc_frame_struct_t *frame, void *context, netc_tx_bd_t *txDesc, bool txCacheMaintain)

Common part for transfer regular frame or Switch management frame.

Note

This function is internal used. Please use EP_SendFrame() or SWT_SendFrame() API to send frames.

Parameters:

• handle –

• txBdRing – The Transmit buffer descriptor ring handle

• hwRing – The hardware Tx ring index

• frame – The frame descriptor pointer

• context – Private context provided back by ep_reclaim_cb_t

• txDesc – Point to the Transmits BD Description array.

• txCacheMaintain – Enable/Disable Tx buffer Cache Maintain.

Return values:

status_t –

status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, void *context, ep_tx_opt *opt)

Transmits a frame for specified ring. This API is zero-copy and requires the ep_reclaim_cb_t to be called to free the transmitted frame.

Parameters:

• handle –

• ring – The ring index

• frame – The frame descriptor pointer

• context – Private context provided back by ep_reclaim_cb_t

• opt – Additional tx options. If NULL, default is tx timestamping enabled, no start time and no masquerading.

Return values:

status_t –

static inline void EP_WaitUnitilTxComplete(ep_handle_t *handle, uint8_t ring)

Wait until the EP Tx ring has completed the transfer.

Note

Only call after EP_SendFrame() to do a no-interrupt transfer

Parameters:

• handle –

• ring – The ring index

netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, bool enCallback)

Common part of Reclaim tx descriptors for regular frame or Switch management frame.

Note

This function is internal used. Please use EP_ReclaimTxDescriptor() or SWT_ReclaimTxDescriptor() API to Reclaim tx descriptors.

Parameters:

• handle –

• txBdRing – The Transmit buffer descriptor ring handle

• hwRing – The hardware Tx ring index

• enCallback – Enable/Disable call the Tx Reclaim callback functions.

void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring)

Reclaim tx descriptors. This function is used to update the tx descriptor status and get the tx timestamp. For each reclaimed transmit frame the ep_reclaim_cb_t is called.

This is called after being notified of a transmit completion from ISR. It runs until there are no more frames to be reclaimed in the BD ring.

Parameters:

• handle –

• ring – The ring index

status_t EP_ReceiveFrameCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr, bool rxCacheMaintain)

Common part of receives one frame with zero copy from specified ring.

Note

This function is internal used. Please use EP_ReceiveFrame() or SWT_ReceiveFrame() API.

Parameters:

• handle –

• rxBdRing – Rx BD ring handle

• ring – Ring index

• frame – Frame buffer point

• attr – Frame attribute pointer

• rxCacheMaintain – Enable/Disable Rx buffer Cache maintain

Returns:

status_t

status_t EP_ReceiveFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr)

Receives one frame with zero copy from specified ring.

Note

The sufficient rx frame data structure MUST be provided by appliction.

Parameters:

• handle –

• ring – The ring index

• frame – The frame descriptor pointer

• attr – Frame attribute pointer

Returns:

kStatus_Success Successfully receive a regular frame

Returns:

kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_ReceiveFrame()

Returns:

kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response

Returns:

kStatus_NETC_RxFrameEmpty Rx BD ring is empty

Returns:

kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped

Returns:

kStatus_InvalidArgument Rx BD ring index is out of range

Returns:

kStatus_NETC_LackOfResource Appliction provided buffer is not enough

void EP_DropFrame(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring)

Drop one frame.

Note

This function is internal used.

Parameters:

• handle –

• rxBdRing – Rx BD ring handle

• ring – Ring index

status_t EP_ReceiveFrameCopyCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr, bool rxCacheMaintain)

Common part of receive regular frame or Switch management frame which will be copied in the provided buffer.

Note

This function is internal used. Please use EP_ReceiveFrameCopy() or SWT_ReceiveFrameCopy() API.

Parameters:

• handle –

• rxBdRing – Rx BD ring handle

• ring – Ring index

• buffer – Buffer address

• length – Buffer length

• attr – Frame attribute pointer

• rxCacheMaintain – Enable/Disable Rx buffer Cache maintain

Returns:

status_t

status_t EP_ReceiveFrameCopy(ep_handle_t *handle, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr)

Receives one frame which will be copied in the provided buffer from specified ring.

Note

The buffer size MUST be queried using EP_GetRxFrameSize() beforehand.

Parameters:

• handle –

• ring – Ring index

• buffer – Buffer address

• length – Buffer length

• attr – Frame attribute pointer

Returns:

kStatus_Success Successfully receive a regular frame

Returns:

kStatus_InvalidArgument Rx BD ring index is out of range

status_t EP_GetRxFrameSizeCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint32_t *length)

Common part of get pending frame size API for regular frame or Switch management frame.

Note

This function is internal used. Please use EP_GetRxFrameSize() or SWT_GetRxFrameSize() API.

Parameters:

• handle –

• rxBdRing – Rx BD ring handle

• length – The length of the valid frame received.

Returns:

status_t

status_t EP_GetRxFrameSize(ep_handle_t *handle, uint8_t ring, uint32_t *length)

Gets the size of the pending frame in the specified receive ring buffer.

Note

Frame size without FCS

Parameters:

• handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.

• ring – The ring index

• length – The length of the valid frame received.

Returns:

kStatus_Success Successfully get the length of a regular frame

Returns:

kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_GetRxFrameSize() to get frame size

Returns:

kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response

Returns:

kStatus_NETC_RxFrameEmpty Rx BD ring is empty

Returns:

kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped

Returns:

kStatus_InvalidArgument Rx BD ring index is out of range

struct _ep_tx_offload

#include <fsl_netc_endpoint.h>

Public Members

bool lso

Large send offload.

bool l4Checksum

L4 checksum offload.

bool ipv4Checksum

IPv4 checksum offload.

uint32_t lsoMaxSegSize

Large send offload maximum segment size.

uint32_t l4Type

L4 type. 1-UDP, 2-TCP.

uint32_t l3Type

L3 type. 0-IPv4, 1-IPv6.

uint32_t l3HeaderSize

L3 IP header size in units of 32-bit words.

uint32_t l3Start

Offset of the IPv4/IPv6 header in units of bytes.

struct _ep_tx_opt

#include <fsl_netc_endpoint.h>

Public Members

uint32_t flags

A bitmask of ep_tx_opt_flags

uint32_t timestamp

Departure timestamp, used if kEP_TX_OPT_START_TIME is set

netc_enetc_vlan_tag_t vlan

VLAN tag which will be inserted, used if kEP_TX_OPT_VLAN_INSERT is set

Hardware layer

enum _netc_hw_enetc_idx

ENETC index enumerator.

Values:

enumerator kNETC_ENETC0

ENETC hardware 0

enumerator kNETC_ENETC1

ENETC hardware 0

enum _netc_hw_switch_idx

SWITCH index enumerator.

Values:

enumerator kNETC_SWITCH0

SWITCH hardware 0

enum _netc_hw_port_idx

Port Resource for the NETC module.

Values:

enumerator kNETC_ENETC0Port

MAC port for ENETC0

enumerator kNETC_ENETC1Port

Pseudo MAC port for ENETC1

enumerator kNETC_SWITCH0Port0

MAC port0 for SWITCH

enumerator kNETC_SWITCH0Port1

MAC port1 for SWITCH

enumerator kNETC_SWITCH0Port2

MAC port2 for SWITCH

enumerator kNETC_SWITCH0Port3

MAC port3 for SWITCH

enumerator kNETC_SWITCH0Port4

Pseudo port4 for SWITCH

enum _netc_hw_tc_idx

Traffic class enumerator.

Values:

enumerator kNETC_TxTC0

Traffic class 0

enumerator kNETC_TxTC1

Traffic class 1

enumerator kNETC_TxTC2

Traffic class 2

enumerator kNETC_TxTC3

Traffic class 3

enumerator kNETC_TxTC4

Traffic class 4

enumerator kNETC_TxTC5

Traffic class 5

enumerator kNETC_TxTC6

Traffic class 6

enumerator kNETC_TxTC7

Traffic class 7

enum _netc_hw_bdr_idx

Enumeration for the ENETC SI BDR identifier.

Values:

enumerator kNETC_BDR0

enumerator kNETC_BDR1

enumerator kNETC_BDR2

enumerator kNETC_BDR3

enumerator kNETC_BDR4

enumerator kNETC_BDR5

enumerator kNETC_BDR6

enumerator kNETC_BDR7

enumerator kNETC_BDR8

enumerator kNETC_BDR9

enumerator kNETC_BDR10

enumerator kNETC_BDR11

enumerator kNETC_BDR12

enumerator kNETC_BDR13

enum _netc_hw_swt_cbdr_idx

Switch command BD ring index enumerator.

Values:

enumerator kNETC_SWTCBDR0

Switch command BD ring 0

enumerator kNETC_SWTCBDR1

Switch command BD ring 1

enum _netc_hw_classs_queue_idx

Enumerator for ETM class queue identifier.

Values:

enumerator kNETC_ClassQueue0

ETM Class Queue 0

enumerator kNETC_ClassQueue1

ETM Class Queue 1

enumerator kNETC_ClassQueue2

ETM Class Queue 2

enumerator kNETC_ClassQueue3

ETM Class Queue 3

enumerator kNETC_ClassQueue4

ETM Class Queue 4

enumerator kNETC_ClassQueue5

ETM Class Queue 5

enumerator kNETC_ClassQueue6

ETM Class Queue 6

enumerator kNETC_ClassQueue7

ETM Class Queue 7

enum _netc_hw_congestion_group_idx

Enumerator for the ETM congestion group.

Values:

enumerator kNETC_CongGroup0

enumerator kNETC_CongGroup1

enum _netc_hw_mii_mode

Defines the MII/RGMII mode for data interface between the MAC and the PHY.

Values:

enumerator kNETC_XgmiiMode

XGMII mode for data interface.

enumerator kNETC_MiiMode

MII mode for data interface.

enumerator kNETC_GmiiMode

GMII mode for data interface.

enumerator kNETC_RmiiMode

RMII mode for data interface.

enumerator kNETC_RgmiiMode

RGMII mode for data interface.

enumerator kNETC_SgmiiMode

SGMII mode for data interface.

enum _netc_hw_mii_speed

Defines the speed for the *MII data interface.

Values:

enumerator kNETC_MiiSpeed10M

Speed 10 Mbps.

enumerator kNETC_MiiSpeed100M

Speed 100 Mbps.

enumerator kNETC_MiiSpeed1000M

Speed 1000 Mbps.

enumerator kNETC_MiiSpeed2500M

Speed 2500 Mbps.

enumerator kNETC_MiiSpeed5G

Speed 5Gbps.

enumerator kNETC_MiiSpeed10G

Speed 10Gbps Mbps.

enum _netc_hw_mii_duplex

Defines the half or full duplex for the MII data interface.

Values:

enumerator kNETC_MiiHalfDuplex

Half duplex mode.

enumerator kNETC_MiiFullDuplex

Full duplex mode.

typedef enum _netc_hw_enetc_idx netc_hw_enetc_idx_t

ENETC index enumerator.

typedef enum _netc_hw_switch_idx netc_hw_switch_idx_t

SWITCH index enumerator.

typedef enum _netc_hw_port_idx netc_hw_port_idx_t

Port Resource for the NETC module.

typedef enum _netc_hw_tc_idx netc_hw_tc_idx_t

Traffic class enumerator.

typedef enum _netc_hw_bdr_idx netc_hw_bdr_idx_t

Enumeration for the ENETC SI BDR identifier.

typedef enum _netc_hw_swt_cbdr_idx netc_hw_swt_cbdr_idx_t

Switch command BD ring index enumerator.

typedef enum _netc_hw_classs_queue_idx netc_hw_etm_class_queue_idx_t

Enumerator for ETM class queue identifier.

typedef enum _netc_hw_congestion_group_idx netc_hw_congestion_group_idx_t

Enumerator for the ETM congestion group.

typedef enum _netc_hw_mii_mode netc_hw_mii_mode_t

Defines the MII/RGMII mode for data interface between the MAC and the PHY.

typedef enum _netc_hw_mii_speed netc_hw_mii_speed_t

Defines the speed for the *MII data interface.

typedef enum _netc_hw_mii_duplex netc_hw_mii_duplex_t

Defines the half or full duplex for the MII data interface.

typedef struct _netc_psfp_kc_profile netc_isi_kc_rule_t

NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes.

typedef struct _netc_vlan_classify_config netc_vlan_classify_config_t

NETC Vlan classification config.

typedef struct _netc_qos_classify_profile netc_qos_classify_profile_t

NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map)

typedef struct _netc_ipf_config netc_ipf_config_t

NETC Ingress Filter config.

typedef struct _netc_func netc_func_t

Register groups for the PCIe function.

typedef struct _netc_port_hw netc_port_hw_t

Register groups for the Port/Link hardware.

typedef struct _netc_enetc_hw netc_enetc_hw_t

Register group for the ENETC peripheral hardware.

typedef struct _netc_timer_hw netc_timer_hw_t

Register group for the Timer peripheral hardware.

typedef struct _netc_mdio_hw netc_mdio_hw_t

Register group for both EMDIO and port external MDIO.

getSiInstance(si)

Get SI information from netc_hw_si_idx_t.

The ENETC instance of this SI.

getSiNum(si)

The SI number in the ENETC.

getSiIdx(si)

The actaul index in the netc_hw_si_idx_t.

NETC_MSIX_TABLE_OFFSET

MSIX table address offset.

NETC_MSIX_TABLE_PBA_OFFSET

MSIX PBA address offset.

NETC_NANOSECOND_ONE_SECOND

Nanosecond in one second.

struct _netc_psfp_kc_profile

#include <fsl_netc.h>

NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes.

Public Members

bool etp

2 Byte Ethertype field present in the key

bool sqtp

1 Byte Sequence Tag present in the key

bool ipcpp

inner VLAN header’s PCP field present in the key

bool ividp

inner VLAN ID present in the key

bool opcpp

outer VLAN header’s PCP field present in the key

bool ovidp

outer VLAN ID present in the key

bool smacp

6 bytes of source MAC address present in the key

bool dmacp

6 bytes of destination MAC address present in the key

bool spmp

switch port masquerading flag present in the key

bool portp

source port present in the key

bool valid

Key Construction is valid

struct _netc_vlan_classify_config

#include <fsl_netc.h>

NETC Vlan classification config.

Public Members

bool enableCustom1

Enable/Disable custom0 ether type

uint16_t custom1EtherType

Ethertype

bool enableCustom2

Enable/Disable custom0 ether type

uint16_t custom2EtherType

Ethertype

uint16_t preStandRTAGType

802.1CB draft 2.0 R-TAG Ethertype value. PSRTAGETR. Only applicable for switch

struct _netc_qos_classify_profile

#include <fsl_netc.h>

NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map)

Public Members

uint8_t ipv[16]

Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped IPV for Qos.

uint8_t dr[16]

Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped DR for QoS.

struct _netc_ipf_config

#include <fsl_netc.h>

NETC Ingress Filter config.

Public Members

bool l2DiscardMCSmac

DOSL2CR. Discard received frames with Multicast SMAC address

bool l2DiscardSmacEquDmac

DOSL2CR. Discard received frames with SMAC = DMAC

bool l3DiscardSipEquDip

DOSL3CR. Discard IPV3/IPV6 source address == destination address

struct _netc_func

#include <fsl_netc_hw.h>

Register groups for the PCIe function.

struct _netc_port_hw

#include <fsl_netc_hw.h>

Register groups for the Port/Link hardware.

Public Members

NETC_PORT_Type *port

Port Address

struct _netc_enetc_hw

#include <fsl_netc_hw.h>

Register group for the ENETC peripheral hardware.

Public Members

netc_func_t func

PCIE function register

NETC_ENETC_Type *base

Base register of ENETC module

NETC_SW_ENETC_Type *common

Common register of ENETC module

netc_port_hw_t portGroup

Port register group

ENETC_GLOBAL_Type *global

Global NETC address

ENETC_SI_Type *si

Station Interfce for the P/V SI

netc_msix_entry_t *msixTable

MSIX table address

struct _netc_timer_hw

#include <fsl_netc_hw.h>

Register group for the Timer peripheral hardware.

Public Members

ENETC_PCI_TYPE0_Type *func

PCIE function register

ENETC_PF_TMR_Type *base

Base register address for timer module

ENETC_GLOBAL_Type *global

Global NETC register address

netc_msix_entry_t *msixTable

MSIX table address

struct _netc_mdio_hw

#include <fsl_netc_hw.h>

Register group for both EMDIO and port external MDIO.

Public Members

__IO uint32_t EMDIO_CFG

External MDIO configuration register, offset: 0x1C00

__IO uint32_t EMDIO_CTL

External MDIO interface control register, offset: 0x1C04

__IO uint32_t EMDIO_DATA

External MDIO interface data register, offset: 0x1C08

__IO uint32_t EMDIO_ADDR

External MDIO register address register, offset: 0x1C0C

__I uint32_t EMDIO_STAT

External MDIO status register, offset: 0x1C10

__IO uint32_t PHY_STATUS_CFG

PHY status configuration register, offset: 0x1C20

__IO uint32_t PHY_STATUS_CTL

PHY status control register, offset: 0x1C24

__I uint32_t PHY_STATUS_DATA

PHY status data register, offset: 0x1C28

__IO uint32_t PHY_STATUS_ADDR

PHY status register address register, offset: 0x1C2C

__IO uint32_t PHY_STATUS_EVENT

PHY status event register, offset: 0x1C30

__IO uint32_t PHY_STATUS_MASK

PHY status mask register, offset: 0x1C34

struct payload

Public Members

uint8_t lbMask

Payload Last Byte Mask

uint8_t fbMask

Payload First Byte Mask

uint8_t byteOffset

Payload Byte Offset where field extraction begins

uint8_t numBytes

Specify the size (numBytes + 1) of the payload key field

uint8_t pfp

Payload field Present

union __unnamed212__

Public Members

ENETC_PCI_TYPE0_Type *pf

PSI function

ENETC_VF_PCI_TYPE0_Type *vf

VSI function

union __unnamed214__

Public Members

NETC_ETH_LINK_Type *eth

MAC Port Address

Hardware Common Functions

static inline uint16_t EP_IncreaseIndex(uint16_t index, uint32_t max)

uint16_t NETC_SIGetVsiIndex(netc_vsi_number_t vsi)

Get the VSI index.

Parameters:

• vsi – The VSI number.

static inline void NETC_IPFInit(NETC_SW_ENETC_Type *base, const netc_ipf_config_t *config)

Set layer2/3 Dos configuration.

Parameters:

• base –

• config –

void NETC_PSFPKcProfileInit(NETC_SW_ENETC_Type *base, const netc_isi_kc_rule_t *rule, bool enKcPair1)

Initialize the Ingress Stream Identification Key construction rule profiles.

Parameters:

• base –

• rule –

• enKcPair1 –

Returns:

void

void NETC_RxVlanCInit(NETC_SW_ENETC_Type *base, const netc_vlan_classify_config_t *config, bool enRtag)

Initialize the customer vlan type.

Parameters:

• base –

• config –

• enRtag –

Returns:

void

void NETC_RxQosCInit(NETC_SW_ENETC_Type *base, const netc_qos_classify_profile_t *profile, bool enProfile1)

Initialize the ingress QoS classification.

Parameters:

• base –

• profile –

• enProfile1 –

Hardware ENETC

typedef struct _netc_enetc_vlan_tag_t netc_enetc_vlan_tag_t

ENETC Port outer/inner VLAN tag.

typedef struct _netc_enetc_discard_statistic netc_enetc_port_discard_statistic_t

PORT discard count statistic.

typedef struct _netc_enetc_native_vlan_config_t netc_enetc_native_vlan_config_t

ENETC Port outer/inner native VLAN config.

typedef struct _netc_enetc_parser_config_t netc_enetc_parser_config_t

ENETC parser configuration.

typedef struct _netc_enetc_cap netc_enetc_cap_t

ENETC capability.

static inline bool NETC_EnetcHasManagement(NETC_ENETC_Type *base)

Check whether ENETC has switch management capability.

Parameters:

• base – NETC peripheral base address.

Returns:

true or false

void NETC_EnetcGetCapability(NETC_ENETC_Type *base, netc_enetc_cap_t *capability)

Get ENETC capability.

Parameters:

• base – NETC peripheral base address.

• capability – Pointer to capability structure.

void NETC_EnetcSetSIMacAddr(NETC_ENETC_Type *base, uint8_t si, uint8_t *macAddr)

Set MAC address for specified VSI of ENETC.

Parameters:

• base –

• macAddr –

status_t NETC_EnetcConfigureSI(NETC_ENETC_Type *base, uint8_t si, const netc_hw_enetc_si_config_t *psConfig)

Configure SI.

Parameters:

• base – ENETC peripheral base address.

• si – The SI number

• psConfig – The SI configuration

Returns:

status_t

status_t NETC_EnetcSetMsixEntryNum(NETC_ENETC_Type *base, uint8_t si, uint32_t msixNum)

Set SI MSIX table entry number.

Parameters:

• base – ENETC peripheral base address.

• si – The SI number.

• msixNum – The MSIX table entry number.

Returns:

status_t

static inline void NETC_EnetcEnableSI(NETC_ENETC_Type *base, uint8_t si, bool enable)

Enable/Disable specified SI.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• enable – Enable/Disable SI from ENETC layer.

void NETC_EnetcGetPortDiscardStatistic(NETC_ENETC_Type *base, netc_enetc_port_discard_statistic_t *statistic)

Get ENETC discard statistic data.

Parameters:

• base – ENETC peripheral base address.

• statistic – Statistic data.

void NETC_EnetcEnablePromiscuous(NETC_ENETC_Type *base, uint8_t si, bool enableUCPromis, bool enableMCPromis)

Enable MAC promiscuous mode.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• enableUCPromis – Enable unicast frame promiscuous.

• enableMCPromis – Enable multicast frame promiscuous.

void NETC_EnetcConfigureVlanFilter(NETC_ENETC_Type *base, uint8_t si, netc_si_l2vf_config_t *config)

Configure VLAN filter.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• config – Enable untagged VLAN frame promiscuous.

void NETC_EnetcAddMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)

Add the hash filter for the MAC address.

Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• type – Unicast or multicast frame type.

• hashIndex – The calculated hash index of MAC address.

void NETC_EnetcDelMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)

Remove the hash filter for the MAC address.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• type – Unicast or multicast frame type.

• hashIndex – The calculated hash index of MAC address.

void NETC_EnetcAddVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)

Add the hash filter for the VLAN.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• hashIndex – The calculated hash index of MAC address.

void NETC_EnetcDelVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)

Remove the hash filter for the VLAN.

Parameters:

• base – ENETC peripheral base address.

• si – SI index.

• hashIndex – The calculated hash index of MAC address.

static inline status_t NETC_EnetcPortEnableTSD(NETC_ENETC_Type *base, netc_hw_tc_idx_t tcIdx, bool isEnable)

Enable / Disable ENETC Port Time Specific Departure (TSD) feature.

It can’t work with QBV CBS

Parameters:

• base –

• tcIdx –

• isEnable –

Returns:

status_t

static inline void NETC_EnetcPortSetNativeVLAN(NETC_ENETC_Type *base, const netc_enetc_native_vlan_config_t *config, bool isOuter)

Set ENETC Rx native outer/inner VLAN.

It is used for classification when untagged frames are received by the port.

Parameters:

• base –

• config –

• isOunter –

static inline void NETC_EnetcSetParser(NETC_ENETC_Type *base, const netc_enetc_parser_config_t *config)

Set ENETC Parser configuration.

PARCSCR and PARCE0CR - PARCE3CR.

Parameters:

• base –

• config –

static inline void NETC_EnetcEnableWakeOnLan(NETC_ENETC_Type *base, bool isEnable)

Enable / Disable ENETC Wake-on-LAN mode.

Only available on ENETC 0

Parameters:

• base –

• isEnable –

Returns:

status_t

struct _netc_enetc_vlan_tag_t

#include <fsl_netc.h>

ENETC Port outer/inner VLAN tag.

Public Members

uint16_t pcp

Priority code point

uint16_t dei

Drop eligible indicator

uint16_t vid

VLAN identifier

netc_vlan_tpid_select_t tpid

Tag protocol identifier

struct _netc_enetc_discard_statistic

#include <fsl_netc.h>

PORT discard count statistic.

Public Members

uint32_t ingressDR[4]

Discard count for port ingress congestion different DR

uint32_t broadcastReject

Broadcast frame drops count due to all SI enable broadcast reject

uint32_t smacPruning

Frames discard count due to port MAC source address pruning

uint32_t unicastMacFilt

Unicast frame discard count due to port MAC filtering

uint32_t multicastMacFilt

Multicast frame discard count due to MAC filtering

uint32_t unicastVlanFilt

Unicast frame discard count due to VLAN filtering

uint32_t multicastVlanFilt

Multicast frame discard count due to VLAN filtering

uint32_t boradcastVlanFilt

Broadcast frame discard count due to VLAN filtering

struct _netc_enetc_native_vlan_config_t

#include <fsl_netc.h>

ENETC Port outer/inner native VLAN config.

Public Members

bool enUnderZeroVid

Enable use the port default VLAN VID when the VID in the packet’s is zero

bool enUnderNoVlan

Enable use the port default VLAN VID when the VLAN tag is not present

netc_enetc_vlan_tag_t vlanTag

Port native outer/inner VLAN tag, valid when enUnderZeroVid or enUnderNoVlan is true

struct _netc_enetc_parser_config_t

#include <fsl_netc.h>

ENETC parser configuration.

Public Members

bool disL3Checksum

Disable Layer 3 IPv4 Header checksum validation.

bool disL4Checksum

Disable Layer 4 TCP and UDP checksum validation.

struct _netc_enetc_cap

#include <fsl_netc_hw_enetc.h>

ENETC capability.

Public Members

bool funcSafety

Support for safety capability.

bool wol

Support for Wake-on-LAN in low-power mode.

bool rss

Support for RSS.

bool tsd

Support for time specific departure.

bool rfs

Support for RFS.

uint32_t ipvNum

IPV number.

uint32_t vsiNum

VSI number.

uint32_t msixNum

MSIX table vector/entry number.

uint32_t tcsNum

Traffic class number.

uint16_t uchNum

Unicast hash entry number.

uint16_t mchNum

Multicast hash entry number.

uint16_t rxBdrNum

Rx BD ring number.

uint16_t txBdrNum

Tx BD ring number.

struct custEtype

Public Members

uint16_t etype

Custom Ethertype value. Upon detecting this ether type the associated code point will be mapped to the parse summary as a Non IP code point.

bool en

Enables the detection and mapping.

uint8_t cp

This value is mapped to the parse summary as a Non IP code point.

Hardware Port

enum _netc_port_tgsl_status

Port time gate scheduling gate list status.

Values:

enumerator kNETC_OperListActive

Port operational gate control list is active.

enumerator kNETC_AdminListPending

Administrative gate control list is pending (configured but not installed yet).

enum _netc_port_discard_tpye

Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function.

Values:

enumerator kNETC_RxDiscard

Discarded frames in the receive port datapath processing pipeline.

enumerator kNETC_TxDiscard

Discarded frames in the egress datapath processing pipeline, only for switch.

enumerator kNETC_BridgeDiscard

Discarded frames in the bridge forwarding processing function, only for switch.

enum _netc_port_tpidlist

Defines Port TPID acceptance.

Values:

enumerator kNETC_OuterStanCvlan

Accept outer Standard C-VLAN 0x8100.

enumerator kNETC_OuterStanSvlan

Accept outer Standard S-VLAN 0x88A8.

enumerator kNETC_OuterCustomVlan1

Accept outer Custom VLAN as defined by CVLANR1[ETYPE].

enumerator kNETC_OuterCustomVlan2

Accept outer Custom VLAN as defined by CVLANR2[ETYPE].

enumerator kNETC_InnerStanCvlan

Accept inner Standard C-VLAN 0x8100.

enumerator kNETC_InnerStanSvlan

Accept inner Standard S-VLAN 0x88A8.

enumerator kNETC_InnerCustomVlan1

Accept inner Custom VLAN as defined by CVLANR1[ETYPE].

enumerator kNETC_InnerCustomVlan2

Accept inner Custom VLAN as defined by CVLANR2[ETYPE].

enum _netc_port_ts_select

Defines port timestamp selection.

Values:

enumerator kNETC_SyncTime

Synchronized time.

enumerator kNETC_FreeRunningTime

Free running time.

enum _netc_hw_preemption_mode

Port MAC preemption mode.

Values:

enumerator kNETC_PreemptDisable

Frame preemption is not enabled

enumerator kNETC_PreemptOn64B

Frame preemption is enabled, but transmit only preempts frames on 64B boundaries

enumerator kNETC_PreemptOn4B

Frame preemption is enabled, but transmit only preempts frames on 4B boundaries

enum _netc_hw_raf_size

Port MAC Remote Additional Fragment Size.

Values:

enumerator kNETC_RafSize64

Additional Fragment Size of 64 octets

enumerator kNETC_RafSize128

Additional Fragment Size of 128 octets

enumerator kNETC_RafSize256

Additional Fragment Size of 256 octets

enumerator kNETC_RafSize512

Additional Fragment Size of 512 octets

enum _netc_tc_sdu_type

Type of PDU/SDU (Protocol/Service Data Unit).

Note

Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:

• PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes

• MPDU = add rxMacsecBco/txMacsecBco bytes

• MSDU = minus 16B (12B MAC Header + 4B FCS)

Values:

enumerator kNETC_PDU

Physical Layer PDU, Preamble, IFG, SFD along with MPDU. Not supported if cut-through frames are expected

enumerator kNETC_MPDU

MAC PDU, MAC Header, MSDU and FCS

enumerator kNETC_MSDU

MAC SDU, MPDU minus 12B MAC Header and 4B FCS. Not supported if cut-through frames are expected

enum _netc_port_sg_ogc_mode

Defines the Port’s Stream Gate Open Gate Check mode.

Values:

enumerator kNETC_SGCheckSFD

Check whether frame SFD is within the open gate interval.

enumerator kNETC_SGCheckEntire

Check whether the entire frame is within the open gate interval.

enum _netc_port_intr_flags

Values:

enumerator kNETC_TxEmptyFlag

Tx FIFO empty flag.

enumerator kNETC_RxEmptyFlag

Rx FIFO empty flag.

enumerator kNETC_TxOverflowFlag

Tx overflow flag.

enumerator kNETC_TxUnderflowFlag

Tx underflow flag.

enumerator kNETC_RxOverflowFlag

Rx overflow flag.

enumerator kNETC_MagicPacketFlag

Magic packet detection indication flag.

enumerator kNETC_TxClkStopFlag

Tx clock stop detection flag.

enumerator kNETC_RxClkStopFlag

Rx clock stop detection flag.

enumerator kNETC_SpeedDuplexChangeFlag

Speed/Duplex Change flag

enumerator kNETC_MacMergeSMDErrFlag

MAC merge frame SMD error received event flag

enumerator kNETC_MacMergeAssemblyErrFlag

MAC merge frame assembly error event flag

enum _netc_port_loopback_mode_t

Defines the port MAC frame loopback mode.

Values:

enumerator kNETC_PortLpbWithExtTxClk

Port MAC frame loopback with external Tx clock.

enumerator kNETC_PortLpbWithIntTxClk

Port MAC frame loopback with internal Tx clock.

typedef enum _netc_port_tgsl_status netc_port_tgsl_status_t

Port time gate scheduling gate list status.

typedef enum _netc_port_discard_tpye netc_port_discard_tpye_t

Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function.

typedef enum _netc_port_tpidlist netc_port_tpidlist_t

Defines Port TPID acceptance.

typedef enum _netc_port_ts_select netc_port_ts_select_t

Defines port timestamp selection.

typedef struct _netc_port_qos_mode netc_port_qos_mode_t

Port Qos mode.

typedef struct _netc_port_parser_config netc_port_parser_config_t

Port Parser config.

typedef struct _netc_port_tg_config netc_port_tg_config_t

Port time gate config.

typedef struct _netc_port_tg_preemption_config netc_port_tg_preemption_config

Port time gate config when used with Frame Preemption.

typedef enum _netc_hw_preemption_mode netc_hw_preemption_mode_t

Port MAC preemption mode.

typedef enum _netc_hw_raf_size netc_hw_raf_size_t

Port MAC Remote Additional Fragment Size.

typedef struct _netc_port_preemption_config netc_port_preemption_config

Frame Preemption Portconfig.

typedef struct _netc_port_tc_cbs_config netc_port_tc_cbs_config_t

Configuration for the Credit Based Shaped for port TC.

Note

The 802.1Qav bandwidth availability parameters is is calculated as follows:

• idleSlope (bits) = portTxRate * bwWeight / 100

• sendSlope (bits) = portTxRate * (100 - bwWeight) / 100

• lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100

• hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.

• hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits)

typedef enum _netc_tc_sdu_type netc_tc_sdu_type_t

Type of PDU/SDU (Protocol/Service Data Unit).

Note

Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:

• PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes

• MPDU = add rxMacsecBco/txMacsecBco bytes

• MSDU = minus 16B (12B MAC Header + 4B FCS)

typedef struct _netc_port_tc_sdu_config netc_port_tc_sdu_config_t

typedef struct _netc_port_tx_tc_config netc_port_tx_tc_config_t

Configuration for the port Tx Traffic Class.

typedef struct _netc_port_discard_statistic netc_port_discard_statistic_t

Switch or ENETC port Tx/Rx/Bridge discard statistic / reason.

typedef struct _netc_port_vlan_classify_config netc_port_vlan_classify_config_t

Port accepted Vlan classification config.

typedef struct _netc_port_qos_classify_configs netc_port_qos_classify_config_t

Port Qos Classification Config.

typedef struct _netc_port_ipf_config_t netc_port_ipf_config_t

Port Ingress Filter Config.

typedef struct _netc_port_psfp_isi_config netc_port_psfp_isi_config

PSFP port config.

Port ingress stream identification config

Note

The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows

• RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID

• RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID

• RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID

typedef struct _netc_port_ethmac netc_port_ethmac_t

typedef enum _netc_port_sg_ogc_mode netc_port_sg_ogc_mode_t

Defines the Port’s Stream Gate Open Gate Check mode.

typedef struct _netc_port_common netc_port_common_t

Port common configuration.

typedef enum _netc_port_intr_flags netc_port_intr_flags_t

typedef enum _netc_port_loopback_mode_t netc_port_loopback_mode_t

Defines the port MAC frame loopback mode.

status_t NETC_PortConfig(NETC_PORT_Type *base, const netc_port_common_t *config)

Configure specified PORT.

Parameters:

• base – NETC port module base address.

• config – Port configuration structure.

Returns:

status_t

void NETC_PortSetMacAddr(NETC_PORT_Type *base, const uint8_t *macAddr)

Set the MAC address.

Parameters:

• handle –

• macAddr –

bool NETC_PortIsPseudo(NETC_PORT_Type *base)

Check whether this port a pseudo MAC port.

Parameters:

• base – PORT peripheral base address.

void NETC_PortGetDiscardStatistic(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, netc_port_discard_statistic_t *statistic)

Get specified PORT discard counter.

Parameters:

• base – NETC port module base address.

• discardType – Port discard type.

• statistic – pointer to the statistic data

void NETC_PortClearDiscardReason(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, uint32_t reason0, uint32_t reason1)

Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons.

Parameters:

• base – NETC port module base address.

• discardType – Port discard type.

• reason0 –

• reason1 –

static inline uint32_t NETC_PortGetTGSListStatus(NETC_PORT_Type *base)

Get port time gate scheduling gate list status.

Parameters:

• base – NETC port module base address.

Returns:

Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t

void NETC_PortEthMacGracefulStop(NETC_PORT_Type *base)

Do graceful stop for Port Ethernet MAC receive/transmit.

Parameters:

• base – NETC port module base address.

static inline void NETC_PortSetSpeed(NETC_PORT_Type *base, uint16_t pSpeed)

Set port speed.

Parameters:

• base – NETC port module base address.

• pSpeed – Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable.

NETC_PORT_MIN_FRAME_SIZE

The port supported minimum/maximum frame size.

NETC_PORT_MAX_FRAME_SIZE

struct _netc_port_qos_mode

#include <fsl_netc.h>

Port Qos mode.

Public Members

uint8_t qosVlanMap

Transmit QoS to VLAN PCP Mapping Profile index, only active on switch port

uint8_t vlanQosMap

Receive VLAN PCP/DE to QoS Mapping Profile index, only active on switch port

uint8_t defaultIpv

Port default IPV

uint8_t defaultDr

Port default DR

bool enVlanInfo

Enable use VLAN info to determine IPV and DR (base on VLANIPVMPaR0/1 and VLANDRMPaR)

bool vlanTagSelect

True: Outer VLAN, False: Innner VLAN. Active when enVlanInfo is true

struct _netc_port_parser_config

#include <fsl_netc.h>

Port Parser config.

Public Members

uint8_t l2PloadCount

L2 payload fields size in bytes

bool enableL3Parser

Enable/Disable parser for L3

uint8_t l3PayloadCount

L3 payload fields size in bytes

bool enableL4Parser

Enable/Disable parser for L4

uint8_t l4PayloadCount

L4 payload fields size in bytes

struct _netc_port_tg_config

#include <fsl_netc.h>

Port time gate config.

Public Members

uint16_t advOffset

Advance time offset in ns.

uint32_t holdSkew

Hold-Skew in ns, not effective on ports connected to a pseudo-MAC

struct _netc_port_tg_preemption_config

#include <fsl_netc.h>

Port time gate config when used with Frame Preemption.

Public Members

uint16_t holdAdvance

the amount of time in ns prior to the Set-And-Hold-MAC time slot for asserting a Hold request. Used with frame Preemption.

uint16_t releaseAdvance

the amount of time in ns prior to the Set-And-Release-MAC time slot for asserting a Release request. Used with Frame Preemption.

struct _netc_port_preemption_config

#include <fsl_netc.h>

Frame Preemption Portconfig.

Public Members

bool enMergeVerify

Enable verify the merged preemption frame, need to enable when preemptMode is not zero

uint8_t mergeVerifyTime

The nominal wait time between verification attempts in milliseconds, range in 1 ~ 128

netc_hw_preemption_mode_t preemptMode

When set to not zero, PMAC frames may be preempted by EMAC frames

netc_hw_raf_size_t raf_size

Additional Fragment Size. Indicates the smallest sized fragments that can be sent on Tx

bool PreemptionActive

Local preemption active. Indicates whether preemption is active for this port. This bit will be set if preemption is both enabled and has completed the verification process

struct _netc_port_tc_cbs_config

#include <fsl_netc.h>

Configuration for the Credit Based Shaped for port TC.

Note

The 802.1Qav bandwidth availability parameters is is calculated as follows:

• idleSlope (bits) = portTxRate * bwWeight / 100

• sendSlope (bits) = portTxRate * (100 - bwWeight) / 100

• lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100

• hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.

• hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits)

Public Members

uint8_t bwWeight

Percentage units of the port transmit rate and the credit-based shaper (range from 0 ~ 100), the sum of all traffic class credit-based shaper’s bandwidth cannot exceed 100

uint32_t hiCredit

The maximum allowed accumulation of credits when conflicting transfers occur, in credit units ((enetClockFrequency / portTxRate) * 100)

struct _netc_port_tc_sdu_config

#include <fsl_netc.h>

Public Members

bool enTxMaxSduCheck

Enable Tx Max SDU check for Store and Forward frames, the frame which greater than maxSduSized wiil be discarded, Cut-Through frames will always perform Max SDU check

netc_tc_sdu_type_t sduType

Specifies the type of PDU/SDU whose length is being validated as seen on the link

uint16_t maxSduSized

Transmit Maximum SDU size in bytes, the dequeued frame will be discarded when it SDU size exceeds this value

struct _netc_port_tx_tc_config

#include <fsl_netc.h>

Configuration for the port Tx Traffic Class.

Public Members

bool enPreemption

Frames from traffic class are transmitted on the preemptable MAC, not supported on internal port (ENETC 1 port and Switch port 4)

bool enTcGate

Enable the traffic class gate when no gate control list is operational, or when time gate scheduling is disabled.

bool enableTsd

Enable Time Specific Departure traffic class, only applicable to ENETC

bool enableCbs

Enable Credit based shaper for traffic class

netc_port_tc_cbs_config_t cbsCfg

Configure transmit traffic class credit based shaper (PTC0CBSR0/PTC0CBSR1) if enableCbs set to ture

struct _netc_port_discard_statistic

#include <fsl_netc.h>

Switch or ENETC port Tx/Rx/Bridge discard statistic / reason.

Public Members

uint32_t count

Count of discarded frames. PRXDCR, PTXDCR or BPDCR.

uint32_t reason0

Discard Reason. Find bit detail from PT/RXDCRR0 or BPDCRR0.

uint32_t reason1

Discard Reason. Find bit detail from PT/RXDCRR1 or BPDCRR1.

struct _netc_port_vlan_classify_config

#include <fsl_netc.h>

Port accepted Vlan classification config.

Public Members

uint8_t innerMask

Bitmap identifying which TPIDs are acceptable as Inner VLAN tag. See PTAR

uint8_t outerMask

Bitmap identifying which TPIDs are acceptable as Outter VLAN tag. See PTAR

struct _netc_port_qos_classify_configs

#include <fsl_netc.h>

Port Qos Classification Config.

Public Members

uint8_t vlanQosMap

Receive VLAN PCP/DE to QoS Mapping Profile index

uint8_t defaultIpv

Port default IPV

uint8_t defaultDr

Port default DR

bool enVlanInfo

Enable use VLAN info to determine IPV and DR ,base on VLAN to IPV map (VLANIPVMPaR0/1) and VLAN to DR map (VLANDRMPaR)

bool vlanTagSelect

True: Use received Outer VLAN, False: Use received Innner VLAN. Active when enVlanInfo is true

struct _netc_port_ipf_config_t

#include <fsl_netc.h>

Port Ingress Filter Config.

Public Members

bool enL2Dos

Enable port L2 Ethernet DoS Protection

bool enL3Dos

Enable port L3 IP DoS Protection

bool enIPFTable

Enable port IPF lookup

struct _netc_port_psfp_isi_config

#include <fsl_netc.h>

PSFP port config.

Port ingress stream identification config

Note

The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows

• RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID

• RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID

• RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID

Public Members

uint16_t defaultISEID

Default Ingress Stream Entry ID, has lower precedence value than ISI entry and IPF entry defined IS_EID. 0xFFFF means NULL

bool enKC1

Enable do the second stream identification with key construction rule 1 or rule 3

bool enKC0

Enable do the first stream identification with key construction rule 0 or rule 2

bool kcPair

Indicates which Key Construction pair to use for this port, false - user pair0. true - use pair1 only applicable for Switch

struct _netc_port_ethmac

#include <fsl_netc.h>

Public Members

bool enableRevMii

Enable RevMII mode.

netc_port_ts_select_t txTsSelect

Tx timestamp clock source.

bool isTsPointPhy

True: Timestamp is captured based on PHY SFD detect pulse on Rx and Tx for 2-step timestamping. False: Based on SFD detect at boundary of MAC merge layer and pins/protocol gaskets.

netc_hw_mii_mode_t miiMode

MII mode.

netc_hw_mii_speed_t miiSpeed

MII Speed.

netc_hw_mii_duplex_t miiDuplex

MII duplex.

bool enTxPad

Enable ETH MAC Tx Padding, which will pad the frame to a minimum of 60 bytes and append 4 octets of FCS.

uint8_t rxMinFrameSize

Receive Minimum Frame Length size in bytes, range in 18 ~ 64, received frames shorter than 18B are discarded silently. Both for express MAC and preemptable MAC.

uint16_t rxMaxFrameSize

Receive Maximum Frame Length size in bytes, up to 2000, received frames that exceed this stated maximum are truncated. Both for express MAC and preemptable MAC.

netc_port_preemption_config PreemptionConfig

Frame Preemption configuration

bool rgmiiClkStop

True: RGMII transmit clock is stoppable during low power idle. False: It’s not stoppable.

bool enableHalfDuplexFlowCtrl

Enable/Disable half-duplex flow control.

uint16_t maxBackPressOn

Maximum amount of time backpressure can stay asserted before stopping to prevent excess defer on link partner, in byte times.

uint16_t minBackPressOff

Minimum amount of time backpressure will stay off after reaching the ON max, before backpressure can reassert after checking if icm_pause_notification is still or again asserted, in byte times.

uint32_t txWakeupTimeCycleEEE

Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) required by the PHY to wait before transmitting a new frame after the application has indicated it wants to end the low power state.

uint32_t txSleepTimeCycleEEE

Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) where Tx is idle before mac transmits low power EEE. A value of 0 does not activate low power EEE transmission.

struct _netc_port_common

#include <fsl_netc.h>

Port common configuration.

Public Members

netc_port_vlan_classify_config_t acceptTpid

Port acceptable VLAN tpid configure.

netc_port_ts_select_t rxTsSelect

Eth MAC Rx or pseudo MAC Tx timestamp clock source

uint16_t pSpeed

Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable

uint8_t rxMacsecBco

Port receive MACSec byte count overhead which due to MACSec encapsulation

uint8_t rxPpduBco

Port receive PPDU Byte count overhead which includes IPG, SFD and Preamble

uint8_t txMacsecBco

Port transmit MACSec byte count overhead which due to MACSec encapsulation

uint8_t txPpduBco

Port transmit PPDU Byte count overhead which includes IPG, SFD and Preamble

netc_port_sg_ogc_mode_t ogcMode

Stream Gate Open Gate Check mode, 0b is check whether SFD is within the open gate interval, 1b is check whether the entire frame is within the open gate interval

uint32_t pDelay

Link propagation delay in ns

uint8_t macAddr[6]

Port MAC address, used for Switch egress frame modification action or ENETC SI0 primary MAC address

netc_port_qos_classify_config_t qosMode

Port Rx Qos Classification config

netc_port_ipf_config_t ipfCfg

Port ingress port filter configuration

netc_port_tg_config_t timeGate

Port Tx time gate config

netc_port_parser_config_t parser

Port Rx Parser config

Hardware Port MAC

enum _netc_port_phy_mac_type

Defines the Ethernet MAC physical port type.

Values:

enumerator kNETC_ExpressMAC

The MAC which handles express traffic when frame preemption is enabled or handles all traffic when frame preemption is disabled.

enumerator kNETC_PreemptableMAC

The MAC which handles preemptive traffic when frame preemption is enabled.

enum _netc_port_preemption_verify_status

Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016.

Values:

enumerator kNETC_VerifyDisable

Verification is disabled

enumerator kNETC_VerifyInProgress

Verification is in progress

enumerator kNETC_VerifySuccess

Verification was successful

enumerator kNETC_VerifyFaile

Verification failed

enumerator kNETC_VerifyUndefined

Verification is in an undefined state

typedef enum _netc_port_phy_mac_type netc_port_phy_mac_type_t

Defines the Ethernet MAC physical port type.

typedef enum _netc_port_preemption_verify_status netc_port_preemption_verify_status_t

Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016.

typedef struct _netc_port_phy_mac_preemption_status netc_port_phy_mac_preemption_status_t

Port MAC preemption Status.

typedef struct _netc_port_phy_mac_traffic_statistic netc_port_phy_mac_traffic_statistic_t

Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.

typedef struct _netc_port_phy_mac_discard_statistic netc_port_phy_mac_discard_statistic_t

Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.

typedef struct _netc_port_phy_mac_preemption_statistic netc_port_phy_mac_preemption_statistic_t

Ethernet physical MAC port preemption (Tx/Rx) related statistics counters.

typedef struct _netc_port_pseudo_mac_traffic_statistic netc_port_pseudo_mac_traffic_statistic_t

Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters.

uint32_t NETC_GetPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType)

Get port MAC interrupt flags.

Parameters:

• base – NETC ETH link base register.

• mac – MAC type.

void NETC_ClearPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask)

Clear port MAC interrupt flags.

Parameters:

• base – NETC ETH link base register.

• mac – MAC type.

• mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask.

void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask, bool enable)

Enable/Disable port MAC interrupts.

Parameters:

• base – NETC ETH link base register.

• mac – MAC type.

• mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask.

• enable – Enable/Disable interrupts.

status_t NETC_PortEnableLoopback(NETC_ETH_LINK_Type *base, netc_port_loopback_mode_t loopMode, bool enable)

Enable/Disable Loopback for specified MAC.

Parameters:

• base –

• loopMode –

• enable –

Returns:

status_t

static inline netc_hw_mii_mode_t NETC_PortGetMIIMode(NETC_ETH_LINK_Type *base)

Get ethernet MAC port MII mode.

Parameters:

• base – Ethernet MAC port peripheral base address.

Returns:

netc_hw_mii_mode_t

status_t NETC_PortSetMII(NETC_ETH_LINK_Type *base, netc_hw_mii_mode_t miiMode, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)

Configure ethernet MAC interface mode, speed and duplex for specified PORT.

Parameters:

• base – Ethernet MAC port peripheral base address.

• miiMode – The Ethernet MAC MII mode.

• speed – The Ethernet MAC speed.

• duplex – The Ethernet MAC duplex.

Returns:

status_t

status_t NETC_PortSetMaxFrameSize(NETC_ETH_LINK_Type *base, uint16_t size)

Set the maximum supported received frame size.

Parameters:

• base – Ethernet MAC port peripheral base address.

• size – Maximum frame size to set.

Returns:

status_t

status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_t *config)

Configure ethernet MAC for specified PORT. Set the MII mode, speed/duplex, reverse mode, etc.

Parameters:

• base – Ethernet MAC port peripheral base address.

• config – The Ethernet MAC configuration.

Returns:

status_t

static inline void NETC_PortConfigEthMacPreemption(NETC_ETH_LINK_Type *base, const netc_port_preemption_config *config)

Configure ethernet MAC for Frame preemption on specified PORT.

Parameters:

• base – Ethernet MAC port peripheral base address.

• config – The Ethernet MAC configuration.

Returns:

status_t

static inline void NETC_PortSoftwareResetEthMac(NETC_ETH_LINK_Type *base)

Do software reset for Ethernet MAC.

Note

This can reset all statistic counters.

Parameters:

• base – PORT MAC peripheral base address.

static inline void NETC_PortGetPhyMacPreemptionStatus(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_status_t *status)

Get Ethernet MAC preemption status.

Parameters:

• base – PORT MAC peripheral base address.

• status – Point to the buffer which store status.

static inline void NETC_PortGetPhyMacPreemptionControl(NETC_ETH_LINK_Type *base, netc_port_preemption_config *config)

Get Ethernet MAC preemption control parameters.

Parameters:

• base – PORT MAC peripheral base address.

• config – Pointer to the NETC port preemption configuration.

void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)

Get Ethernet MAC Tx Traffic Statistics .

Parameters:

• base – PORT MAC peripheral base address.

• macType – Express MAC or Preemptable MAC.

• status – Point to the buffer which store statistics.

void NETC_PortGetPhyMacRxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)

Get Ethernet MAC Rx Traffic Statistics .

Parameters:

• base – PORT MAC peripheral base address.

• macType – Express MAC or Preemptable MAC.

• status – Point to the buffer which store statistics.

void NETC_PortGetPhyMacDiscardStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_discard_statistic_t *statistic)

Get Ethernet MAC Rx/Tx Drops/Errors Statistics .

Parameters:

• base – PORT MAC peripheral base address.

• macType – Express MAC or Preemptable MAC.

• status – Point to the buffer which store statistics.

void NETC_PortGetPhyMacPreemptionStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_statistic_t *statistic)

Get Ethernet Preemptable MAC preemption Statistics .

Parameters:

• base – PORT MAC peripheral base address.

• status – Point to the buffer which store statistics.

status_t NETC_PortConfigTxIpgPreamble(NETC_ETH_LINK_Type *base, uint8_t preambleCnt, uint8_t ipgLen)

Configure the port MAC flexible preamble and IPG length.

Parameters:

• base – PORT MAC peripheral base address.

• preambleCnt – Flexible Preamble Count. Valid values are 1 to 7(default).

• ipgLen – Transmit inter-packet gap value. Valid values are 4 to 24(default) with 12 being default.

Returns:

status_t

struct _netc_port_phy_mac_preemption_status

#include <fsl_netc.h>

Port MAC preemption Status.

Public Members

bool mergeActive

Transmit preemption is active or not

netc_port_preemption_verify_status_t verifyStatus

Transmit preemption is active or not

struct _netc_port_phy_mac_traffic_statistic

#include <fsl_netc.h>

Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.

Public Members

uint64_t totalOctet

Count of MAC received/transmitted good/error Ethernet octets.

uint64_t validOctet

Count of MAC received/transmitted good Ethernet octets.

uint64_t pauseFrame

Count of MAC received/transmitted valid PAUSE frames.

uint64_t validFrame

Count of MAC received/transmitted valid frames.

uint64_t vlanFrame

Count of MAC received/transmitted valid VLAN tagged frames.

uint64_t unicastFrame

Count of MAC received/transmitted valid unicast frames.

uint64_t multicastFrame

Count of MAC received/transmitted valid multicast frames.

uint64_t boradcastFrame

Count of MAC received/transmitted valid broadcast frames.

uint64_t totalPacket

Count of MAC received/transmitted good/error packets.

uint64_t rxMinPacket

Count of MAC received min to 63-octet packets.

uint64_t total64BPacket

Count of MAC received/transmitted 64 octet packets.

uint64_t total65To127BPacket

Count of MAC received/transmitted 65 to 127 octet packets.

uint64_t total128To255BPacket

Count of MAC received/transmitted 128 to 255 octet packets.

uint64_t total256To511BPacket

Count of MAC received/transmitted 256 to 511 octet packets.

uint64_t total511To1023BPacket

Count of MAC received/transmitted 512 to 1023 octet packets.

uint64_t total1024To1522BPacket

Count of MAC received/transmitted 1024 to 1522 octet packets.

uint64_t total1523ToMaxBPacket

Count of MAC received/transmitted 1523 to Max octet packets.

uint64_t controlPacket

Count of MAC received/transmitted control packets.

struct _netc_port_phy_mac_discard_statistic

#include <fsl_netc.h>

Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups.

Public Members

uint64_t rxError

Count of MAC received error frames.

uint64_t rxUndersized

Count of MAC received undersized frames.

uint64_t rxOversized

Count of MAC received oversized frames.

uint64_t rxErrorFCS

Count of MAC received check sequence (FCS) error frames.

uint64_t rxFragment

Count of MAC frames which is shorter than the MIN length and received with a wrong FCS/CRC.

uint64_t rxJabber

Count of MAC frames which is larger than the MAX length and received with a wrong FCS/CRC.

uint64_t rxDiscard

Count of MAC drops frame.

uint64_t rxDiscardNoTruncated

Count of MAC non-truncated drops frame.

uint64_t txErrorFCS

Count of MAC transmitted bad FCS frames.

uint64_t txUndersized

Count of MAC transmitted less than 64B with good FCS frames.

struct _netc_port_phy_mac_preemption_statistic

#include <fsl_netc.h>

Ethernet physical MAC port preemption (Tx/Rx) related statistics counters.

Public Members

uint32_t rxReassembledFrame

Count of MAC frames that were successfully reassembled and delivered to the MAC.

uint32_t rxReassembledError

Count of MAC frames with reassembly errors.

uint32_t rxMPacket

Count of the number of additional mPackets received due to preemption.

uint32_t rxSMDError

Count of received MAC frames / MAC frame fragments rejected due to unknown SMD.

uint32_t txPreemptionReq

Count of the number of tx preemption HOLD requests.

uint32_t txMPacket

Count of the number of additional mPackets transmitted due to preemption.

struct _netc_port_pseudo_mac_traffic_statistic

#include <fsl_netc.h>

Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters.

Public Members

uint64_t totalOctet

Count of MAC received/transmitted octets.

uint64_t unicastFrame

Count of MAC received/transmitted unicast frames.

uint64_t multicastFrame

Count of MAC received/transmitted multicast frames.

uint64_t boradcastFrame

Count of MAC received/transmitted broadcast frames .

Hardware Port Rx

static inline void NETC_PortSetParser(NETC_PORT_Type *base, const netc_port_parser_config_t *config)

Set port Parser.

Parameters:

• base – PORT peripheral base address.

• config – The port Parser configuration.

static inline void NETC_PortSetVlanClassify(NETC_PORT_Type *base, const netc_port_vlan_classify_config_t *config)

Set port acceptable VLAN.

Parameters:

• base – PORT peripheral base address.

• config – The port acceptable vlan classification configuration.

static inline status_t NETC_PortSetQosClassify(NETC_PORT_Type *base, const netc_port_qos_classify_config_t *config)

Set port Qos Classification.

Parameters:

• base – PORT peripheral base address.

• config – The port QoS classification configuration.

Returns:

status_t

static inline void NETC_PortSetIPF(NETC_PORT_Type *base, const netc_port_ipf_config_t *config)

Set port ingress filter.

Parameters:

• base – PORT peripheral base address.

• config – The port ingress filter configuration.

static inline void NETC_PortSetISI(NETC_PORT_Type *base, const netc_port_psfp_isi_config *config)

Set port Ingress stream identification.

Parameters:

• base – PORT peripheral base address.

• config – The port Ingress stream identification configuration.

Hardware Port Tx

static inline status_t NETC_PortConfigTGS(NETC_PORT_Type *base, const netc_port_tg_config_t *config)

Configure the port time gating Scheduling.

Parameters:

• base –

• config –

Returns:

status_t

status_t NETC_PortConfigTcCBS(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_cbs_config_t *config)

Config the Credit-Based Shaper (CBS) for specified Port Traffic Class.

Parameters:

• base –

• tcIdx –

• config –

Returns:

status_t

static inline status_t NETC_PortConfigTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_sdu_config_t *config)

Config the max Transmit max SDU for specified Port Traffic Class.

Parameters:

• base –

• tcIdx –

• config –

Returns:

status_t

static inline status_t NETC_PortGetTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, netc_port_tc_sdu_config_t *config)

Read the max Transmit max SDU for specified Port Traffic Class.

Parameters:

• base –

• tcIdx –

• config –

Returns:

status_t

static inline void NETC_PortConfigTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const bool enable)

Config Frame Preemption for specified Port Traffic Class.

Parameters:

• base – NETC PORT base peripheral address

• tcIdx – traffic class index

• enable – enable/disable feature on traffic class

static inline void NETC_PortGetTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, bool *enabled)

Get Frame Preemption configuration for specified Port Traffic Class.

Parameters:

• base – NETC PORT base peripheral address

• tcIdx – traffic class index

• enabled – port tx traffic class enabled flag

static inline void NETC_PortGetTGSFPConfig(NETC_PORT_Type *base, netc_port_tg_preemption_config *config)

Get the port time gating Scheduling configuration specifc for when used with Frame Preemption.

Parameters:

• base – NETC PORT base peripheral address

• config –

Hardware Station Interface(SI)

NETC_SI_TXDESCRIP_RD_FL(n)

Defines for read format.

NETC_SI_TXDESCRIP_RD_TSE_MASK

NETC_SI_TXDESCRIP_RD_TXSTART(n)

NETC_SI_TXDESCRIP_RD_L3START(n)

NETC_SI_TXDESCRIP_RD_IPCS(n)

NETC_SI_TXDESCRIP_RD_L3HDRSIZE(n)

NETC_SI_TXDESCRIP_RD_L3T(n)

NETC_SI_TXDESCRIP_RD_L4T(n)

NETC_SI_TXDESCRIP_RD_L4CS(n)

NETC_SI_TXDESCRIP_RD_LSO(n)

NETC_SI_TXDESCRIP_RD_LSO_MASK

enum _netc_hw_enetc_si_vlan_type

VLAN Ethertypes.

Values:

enumerator kNETC_ENETC_StanCVlan

Standard C-VLAN 0x8100.

enumerator kNETC_ENETC_StanSVlan

Standard S-VLAN 0x88A8.

enumerator kNETC_ENETC_CustomVlan1

Custom VLAN as defined by CVLANR1[ETYPE].

enumerator kNETC_ENETC_CustomVlan2

Custom VLAN as defined by CVLANR2[ETYPE].

enum _netc_hw_enetc_si_rxr_group

SI receive BD ring group index.

Values:

enumerator kNETC_SiBDRGroupOne

SI Rx BD ring group index one.

enumerator kNETC_SiBDRGroupTwo

SI Rx BD ring group index two.

enum _netc_tx_bdr_flags

Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation.

Values:

enumerator kNETC_TxBDRSystemBusErrorFlag

enumerator kNETC_TxBDRBusyFlag

enumerator kNETC_TxBDRStatusFlagsMask

enum _netc_rx_bdr_flags

Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation.

Values:

enumerator kNETC_RxBDRSystemBusErrorFlag

enumerator kNETC_RxBDREmptyFlag

enum _netc_psi_msg_flags_t

PSI message interrupt type.

Values:

enumerator kNETC_PsiRxMsgFromVsi1Flag

Message receive interrupt enable, initiated by VSI1.

enumerator kNETC_PsiRxMsgFromVsi2Flag

Message receive interrupt enable, initiated by VSI2.

enumerator kNETC_PsiRxMsgFromVsi3Flag

Message receive interrupt enable, initiated by VSI3.

enumerator kNETC_PsiFLRFromVsi1Flag

Function level reset interrupt enable, initiated by VSI1.

enum _netc_vsi_msg_flags

VSI message interrupt flags.

Values:

enumerator kNETC_VsiMsgTxFlag

Message sent to PSI has completed and response received.

enumerator kNETC_VsiMsgRxFlag

Message received from PSI.

enum _netc_vsi_number

VSI number bit map, VSI1 starts from bit1.

Values:

enumerator kNETC_Vsi1

enumerator kNETC_Vsi2

enumerator kNETC_Vsi3

enum _enetc_si_bdr_priority

ENETC Station Interface BD Ring priority enumeration.

Values:

enumerator kNETC_SIBdrPriorityLowest

enumerator kNETC_SIBdrPriority0

enumerator kNETC_SIBdrPriority1

enumerator kNETC_SIBdrPriority2

enumerator kNETC_SIBdrPriority3

enumerator kNETC_SIBdrPriority4

enumerator kNETC_SIBdrPriority5

enumerator kNETC_SIBdrPriority6

enumerator kNETC_SIBdrPriority7

enumerator kNETC_SIBdrPriorityHighest

typedef enum _netc_hw_enetc_si_vlan_type netc_hw_enetc_si_vlan_type

VLAN Ethertypes.

typedef enum _netc_hw_enetc_si_rxr_group netc_hw_enetc_si_rxr_group

SI receive BD ring group index.

typedef struct _netc_hw_enetc_si_config netc_hw_enetc_si_config_t

Station Interface configuration.

typedef struct _netc_si_l2mf_config netc_si_l2mf_config_t

L2 Mac Filter Configuration for SI.

typedef struct _netc_si_l2vf_config netc_si_l2vf_config_t

L2 VLAN Filter Configuration for SI.

typedef struct _netc_si_discard_statistic netc_si_discard_statistic_t

SI frame drop statistic struct.

typedef struct _netc_si_traffic_statistic netc_si_traffic_statistic_t

SI traffic statistic struct.

typedef struct _netc_si_config netc_si_config_t

SI Configuration.

typedef union _netc_tx_bd netc_tx_bd_t

Transmit Buffer Descriptor format.

A union type cover the BD used as Standard/Extended/WriteBack format.

typedef union _netc_rx_bd netc_rx_bd_t

Receive Buffer Descriptor format.

typedef struct _netc_tx_bdr_config netc_tx_bdr_config_t

Configuration for the SI Tx Buffer Descriptor Ring Configuration.

typedef struct _netc_tx_bdr netc_tx_bdr_t

Transmit BD ring handler data structure.

typedef enum _netc_tx_bdr_flags netc_tx_bdr_flags_t

Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation.

typedef struct _netc_rx_bdr_config netc_rx_bdr_config_t

Configuration for the SI Rx Buffer Descriptor Ring Configuration.

typedef struct _netc_rx_bdr netc_rx_bdr_t

Receive BD ring handler data structure.

typedef enum _netc_rx_bdr_flags netc_rx_bdr_flags_t

Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation.

typedef struct _netc_bdr_config netc_bdr_config_t

Configuration for the buffer descriptors ring.

typedef enum _netc_psi_msg_flags_t netc_psi_msg_flags_t

PSI message interrupt type.

typedef enum _netc_vsi_msg_flags netc_vsi_msg_flags_t

VSI message interrupt flags.

typedef enum _netc_vsi_number netc_vsi_number_t

VSI number bit map, VSI1 starts from bit1.

typedef struct _netc_psi_rx_msg netc_psi_rx_msg_t

PSI receive message information.

typedef struct _netc_vsi_msg_tx_status netc_vsi_msg_tx_status_t

VSI message transmit status.

typedef enum _enetc_si_bdr_priority enetc_si_bdr_priority_t

ENETC Station Interface BD Ring priority enumeration.

static inline void NETC_ClearTxDescriptor(netc_tx_bd_t *txDesc)

static inline void NETC_CopyTxDescriptor(netc_tx_bd_t *txDescDst, netc_tx_bd_t *txDescSrc)

static inline void NETC_SIEnable(ENETC_SI_Type *base, bool enable)

Enable the Station Interface(SI)

Parameters:

• base –

static inline void NETC_SIRxRingEnable(ENETC_SI_Type *base, uint8_t ring, bool enable)

Enable the specified Rx BD ring.

Parameters:

• base –

• ring – The ring index.

• base – Enable/Disable the ring.

static inline void NETC_SIEnablePromisc(ENETC_SI_Type *base, netc_packet_type_t type, bool enable)

Enable/Disable unicast/multicast/boardcast promisc mode for specified SI.

Parameters:

• base –

• type –

• enable –

static inline void NETC_SISetTxProducer(ENETC_SI_Type *base, uint8_t ring, uint16_t producer)

Set producer index of specified Tx BD ring.

Parameters:

• base – SI base address.

• ring – BD ring index.

• producer – The producer index of specified ring.

static inline uint16_t NETC_SIGetTxConsumer(ENETC_SI_Type *base, uint8_t ring)

Get consumer index of specified Tx BD ring.

Parameters:

• base – SI base address.

• ring – BD ring index.

Returns:

consumer The consumer index of specified ring.

static inline void NETC_SISetRxConsumer(ENETC_SI_Type *base, uint8_t ring, uint16_t consumer)

Set consumer index of specified Rx BD ring.

Parameters:

• base – SI base address.

• ring – BD ring index.

• consumer – The consumer index of specified ring.

static inline uint16_t NETC_SIGetRxProducer(ENETC_SI_Type *base, uint8_t ring)

Get producer index of specified Rx BD ring.

Parameters:

• base – SI base address.

• ring – BD ring index.

Returns:

producer The producer index of specified ring.

status_t NETC_SIConfigTxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_tx_bdr_config_t *bdrConfig)

Configure the Transmit Buffer Descriptor Ring for specified SI.

Parameters:

• base – SI base address.

• ring – BD ring index.

• bdrConfig – The BD ring configuration.

Returns:

status_t

status_t NETC_SIConfigRxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_rx_bdr_config_t *bdrConfig)

Configure the Rx Buffer Descriptor Ring for specified SI.

Parameters:

• base – SI base address.

• ring – BD ring index.

• bdrConfig – The BD ring configuration.

Returns:

status_t

static inline void NETC_SIMapVlanToIpv(ENETC_SI_Type *base, uint8_t pcpDei, uint8_t ipv)

Enable the mapping of VLAN to IPV.

Parameters:

• base – SI base address.

• pcpDei – The VLAN tag pcp dei value (use NETC_VLAN_PCP_DEI_VALUE macro).

• ipv – The IPV value for this VLAN mapping.

static inline void NETC_SIEnableVlanToIpv(ENETC_SI_Type *base, bool enable)

Enable the mapping of VLAN to IPV.

Parameters:

• base – SI base address.

• enable – Whether enable mapping.

Returns:

status_t

static inline void NETC_SIMapIpvToRing(ENETC_SI_Type *base, uint8_t ipv, uint8_t ring)

Set the IPV to ring mapping.

Parameters:

• base – SI base address.

• ipv – IPV value to be mapped.

• ring – The Rx BD ring index to be mapped.

Returns:

status_t

static inline void NETC_SISetRxBDRGroup(ENETC_SI_Type *base, uint8_t groupNum, uint8_t ringPerGroup)

Set the group of Rx BD ring.

Parameters:

• base – SI base address.

• groupNum – Total group number.

• ringPerGroup – Rings per group.

Returns:

status_t

static inline void NETC_SISetDefaultRxBDRGroup(ENETC_SI_Type *base, netc_hw_enetc_si_rxr_group groupIdx)

Set the default used receive Rx BD ring group.

Note

The IPV mapped ring index is the relative index inside the default used group.

Parameters:

• base – SI base address.

• groupNum – The default Rx group index.

Returns:

status_t

static inline void NETC_SICleanTxIntrFlags(ENETC_SI_Type *base, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)

Clean the SI transmit interrupt flags.

Parameters:

• base – SI base address.

• txFrameIntrMask – IPV value to be mapped, bit x represents ring x.

• txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x.

static inline void NETC_SICleanRxIntrFlags(ENETC_SI_Type *base, uint32_t rxIntrMask)

Clean the SI receive interrupt flags.

Parameters:

• base – SI base address.

• rxIntrMask – Rx interrupt bit mask, bit x represents ring x.

void NETC_SIPsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)

PSI enables/disables specified interrupt.

Parameters:

• base – SI base address.

• mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

• enable – Enable/Disable the interrupt.

static inline uint32_t NETC_SIPsiGetStatus(ENETC_SI_Type *base)

PSI gets interrupt event flag status.

Parameters:

• base – SI base address.

Returns:

The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

static inline void NETC_SIPsiClearStatus(ENETC_SI_Type *base, uint32_t mask)

PSI clears interrupt event flag.

Parameters:

• base – SI base address.

• mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together.

status_t NETC_SIPsiSendMsg(ENETC_SI_Type *base, uint16_t msg, netc_vsi_number_t vsi)

PSI sends message to specified VSI(s)

Parameters:

• base – SI base address.

• msg – The message to be sent.

• vsi – The VSI number.

Returns:

status_t

static inline bool NETC_SIPsiCheckTxBusy(ENETC_SI_Type *base, netc_vsi_number_t vsi)

PSI checks Tx busy flag which should be cleaned when VSI receive the message data.

Parameters:

• base – SI base address.

• vsi – The VSI number.

Returns:

The busy status of specified VSI.

status_t NETC_SIPsiSetRxBuffer(ENETC_SI_Type *base, netc_vsi_number_t vsi, uint64_t buffAddr)

PSI sets Rx buffer to receive message from specified VSI.

Note

The buffer memory size should be big enough for the message data from VSI

Parameters:

• base – SI base address.

• vsi – The VSI number.

• buffAddr – The buffer address to store message data from VSI, must be 64 bytes aligned.

Returns:

status_t

status_t NETC_SIPsiGetRxMsg(ENETC_SI_Type *base, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)

PSI gets Rx message from specified VSI.

Parameters:

• base – SI base address.

• vsi – The VSI number.

• msgInfo – The Rx message information.

void NETC_SIVsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)

Enable VSI interrupt.

Parameters:

• base – SI base address.

• mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.

• enable – Enable/Disable interrupt.

static inline uint32_t NETC_SIVsiGetStatus(ENETC_SI_Type *base)

Get VSI interrupt status.

Parameters:

• base – SI base address.

Returns:

A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together.

static inline void NETC_SIVsiClearStatus(ENETC_SI_Type *base, uint32_t mask)

Clear VSI interrupt status.

Parameters:

• base – SI base address.

• mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together.

status_t NETC_SIVsiSendMsg(ENETC_SI_Type *base, uint64_t msgAddr, uint32_t msgLen)

VSI sends message to PSI.

Parameters:

• base – SI base address.

• msgAddr – Address to store message ready to be sent, must be 64 bytes aligned.

• msgLen – The message length, must be 32 bytes aligned.

Returns:

status_t

void NETC_SIVsiCheckTxStatus(ENETC_SI_Type *base, netc_vsi_msg_tx_status_t *status)

Check VSI Tx status.

Parameters:

• base – SI base address.

• status – The VSI Tx status structure.

status_t NETC_SIVsiReceiveMsg(ENETC_SI_Type *base, uint16_t *msg)

VSI receives message from PSI.

Parameters:

• base – SI base address.

• msg – The message from PSI.

Returns:

status_t

void NETC_SIGetDiscardStatistic(ENETC_SI_Type *base, netc_si_discard_statistic_t *statistic)

Get the discard statistic from SI layer.

Parameters:

• base – SI base address.

• statistic – The statistic data.

void NETC_SIGetTrafficStatistic(ENETC_SI_Type *base, netc_si_traffic_statistic_t *statistic)

Get the traffic statistic from SI layer.

Parameters:

• base – SI base address.

• statistic – The statistic data.

NETC_VLAN_PCP_DEI_VALUE(pcp, dei)

Macro to cover VLAN PCP, DEI value to internal used pcpDei value.

struct _netc_hw_enetc_si_config

#include <fsl_netc.h>

Station Interface configuration.

Public Members

uint32_t bandWeight

Station interface traffic class bandwidth weight

uint32_t vlanCtrl

VLAN Ethertypes can be inserted by the SI driver, set with OR of netc_hw_enetc_si_vlan_type.

uint32_t antiSpoofEnable

Anti-spoofing enable

uint32_t vlanInsertEnable

Software SI-based VLAN Insertion enable, avtive when enSIBaseVlan is true

uint32_t vlanExtractEnable

SI-based VLAN removed from frame enable, avtive when enSIBaseVlan is true

uint32_t sourcePruneEnable

Source pruning enable

uint32_t rxRingUse

Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings.

uint32_t txRingUse

Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0.

uint32_t valnToIpvEnable

Enable the VLAN PCP/DEI value (use NETC_VLAN_PCP_DEI_VALUE marco) to internal priority value mapping.

uint32_t rxBdrGroupNum

Rx BD ring group number, range in 0 ~ 2.

uint32_t ringPerBdrGroup

The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero.

netc_hw_enetc_si_rxr_group defaultRxBdrGroup

The selected Rx BD ring group, active when rxBdrGroupNum not equal zero.

uint8_t vlanToIpvMap[16]

Frame VLAN pcp|dei to IPV mapping, active when valnToIpvEnable is true.

uint8_t ipvToRingMap[8]

BD ring used within the default Rx BD ring group for IPV n, active when rxBdrGroupNum not equal zero.

uint8_t vsiTcToTC[8]

Maps the VSI traffic class to transmit traffic class, done after the ENETC txPrio to TC mapping, only available for VSI.

bool enSIBaseVlan

Enable use SI-based VLAN information.

netc_enetc_vlan_tag_t siBaseVlan

SI-based VLAN information, active when enSIBaseVlan is true.

struct _netc_si_l2mf_config

#include <fsl_netc.h>

L2 Mac Filter Configuration for SI.

Public Members

bool macUCPromis

Enable/Disable MAC unicast promiscuous.

bool macMCPromis

Enable/Disable MAC multicast promiscuous.

bool rejectUC

Reject Unicast.

bool rejectMC

Reject Multicast.

bool rejectBC

Reject Broadcast.

struct _netc_si_l2vf_config

#include <fsl_netc.h>

L2 VLAN Filter Configuration for SI.

Public Members

bool acceptUntagged

Accept/Reject untagged frame.

bool enPromis

Enable/Disable VLAN promiscuous.

bool useOuterVlanTag

Use outer/inner VLAN tag for filtering.

struct _netc_si_discard_statistic

#include <fsl_netc.h>

SI frame drop statistic struct.

Public Members

uint32_t programError

Due to programming error ( non-existing BD ring or non-existing group, or SI disabled or BD ring disabled).

uint32_t busError

Due to system bus error.

uint32_t lackBD[14]

Due to lack of Rx BDs available.

struct _netc_si_traffic_statistic

#include <fsl_netc.h>

SI traffic statistic struct.

struct _netc_si_config

#include <fsl_netc.h>

SI Configuration.

Public Members

uint32_t tcBWWeight

SI traffic class bandwidth weight.

union _netc_tx_bd

#include <fsl_netc.h>

Transmit Buffer Descriptor format.

A union type cover the BD used as Standard/Extended/WriteBack format.

Public Members

struct _netc_tx_bd standard

struct _netc_tx_bd ext

struct _netc_tx_bd writeback

uint64_t dword[2]

union _netc_rx_bd

#include <fsl_netc.h>

Receive Buffer Descriptor format.

Public Members

struct _netc_rx_bd standard

struct _netc_rx_bd writeback

struct _netc_rx_bd ext

struct _netc_tx_bdr_config

#include <fsl_netc.h>

Configuration for the SI Tx Buffer Descriptor Ring Configuration.

Public Members

uint32_t len

Size of BD ring which shall be multiple of 8 BD.

netc_tx_bd_t *bdArray

BDR base address which shall be 128 bytes aligned.

netc_tx_frame_info_t *dirtyArray

Tx cleanup ring.

bool enIntr

Enable/Disable completion interrupt.

bool enThresIntr

Enable/Disable threshold interrupt.

bool enCoalIntr

Enable/Disable interrupt coalescing.

uint32_t intrThreshold

Interrupt coalescing packet threshold.

uint32_t intrTimerThres

Interrupt coalescing timer threshold, specified in NETC clock cycles.

uint8_t msixEntryIdx

MSIX entry index of Tx ring interrupt.

bool isVlanInsert

Enable/Disable VLAN insert offload.

bool isUserCRC

Enable/Disable user provided the CRC32 - FCS at end of frame.

uint8_t wrrWeight

Weight used for arbitration when rings have same priority.

uint8_t priority

Priority of the Tx BDR.

struct _netc_tx_bdr

#include <fsl_netc.h>

Transmit BD ring handler data structure.

Public Members

netc_tx_bd_t *bdBase

Tx BDR base address.

netc_tx_frame_info_t *dirtyBase

Tx cleanup ring base address.

uint16_t producerIndex

Current index for transmit.

uint16_t cleanIndex

Current index for tx cleaning.

uint32_t len

Length of this BD ring.

struct _netc_rx_bdr_config

#include <fsl_netc.h>

Configuration for the SI Rx Buffer Descriptor Ring Configuration.

Public Members

bool extendDescEn

False - Use 16Bytes standard BD. True - Use 32Bytes extended BD.

netc_rx_bd_t *bdArray

BD ring base address which shall be 128 bytes aligned.

uint32_t len

BD ring length in the unit of 16Bytes standard BD. Shall be multiple of 8/16 for standard/exteneded BD.

uint64_t *buffAddrArray

Rx buffers array with BD length(half of BD length if use exteneded BD).

uint16_t buffSize

Size of all Rx buffers in this BD ring.

bool enThresIntr

Enable/Disable threshold interrupt.

bool enCoalIntr

Enable/Disable interrupt coalescing.

uint32_t intrThreshold

Interrupt coalescing packet threshold.

uint32_t intrTimerThres

Interrupt coalescing timer threshold, specified in NETC clock cycles.

uint8_t msixEntryIdx

MSIX entry index of Rx ring interrupt.

bool disVlanPresent

Disable/Enable VLAN in BD.

bool enVlanExtract

Enable/Disable VLAN extract.

bool isKeepCRC

Whether user provided the CRC32 - FCS at end of frame.

bool congestionMode

False - lossy. True - lossless.

bool enHeaderAlign

Enable/disable +2B alignment to frame.

struct _netc_rx_bdr

#include <fsl_netc.h>

Receive BD ring handler data structure.

Public Members

netc_rx_bd_t *bdBase

Rx BDR base address.

bool extendDesc

Use extended buffer descriptor.

uint16_t index

Current index for read.

uint32_t len

Length of this BD ring, unit of 16Bytes standard BD.

uint64_t *buffArray

Rx buffers array of this ring.

uint32_t buffSize

Rx buffers size for all BDs in this ring.

struct _netc_bdr_config

#include <fsl_netc.h>

Configuration for the buffer descriptors ring.

Public Members

netc_rx_bdr_config_t *rxBdrConfig

Receive buffer ring configuration array.

netc_tx_bdr_config_t *txBdrConfig

Transmit buffer ring configuration array.

struct _netc_psi_rx_msg

#include <fsl_netc.h>

PSI receive message information.

Public Members

uint8_t *msgBuff

The buffer address application set before receiving message.

uint32_t msgLen

Received message length.

struct _netc_vsi_msg_tx_status

#include <fsl_netc.h>

VSI message transmit status.

Public Members

bool txBusy

The VSI Tx busy flag, become idle when the PSI receive and clear the related status.

bool isTxErr

Tx error flag.

uint16_t msgCode

The error code or user-defined content.

struct standard

Public Members

uint64_t addr

Address of the buffer. Little Endian.

uint16_t bufLen

Length of buffer specifying effective number of bytes.

uint16_t frameLen

Length of Frame.

uint32_t flags

Flags qualified setting.

uint32_t enableInterrupt

Whether enable interrupt on complete of BD.

uint32_t isExtended

Extended BD format flag.

uint32_t isFinal

Final BD flag.

struct ext

Public Members

uint32_t timestamp

IEEE1588 PTP one-step timestamp.

uint32_t __pad0__

Ignore 2-bit MSB.

uint16_t tpid

VLAN TPID type, see netc_vlan_tpid_select_t.

uint16_t vid

VLAN ID.

uint16_t dei

VLAN DEI.

uint16_t pcp

VLAN PCP.

uint8_t eFlags

Tx extension flags.

uint8_t isFinal

Final BD flag.

struct writeback

Public Members

uint32_t timestamp

Timestamp write back.

uint32_t status

Status.

uint32_t written

Write-back flag.

struct standard

Public Members

uint64_t addr

Software write address.

struct writeback

Public Members

uint16_t internetChecksum

Internet Checksum.

uint16_t parserSummary

Parser Summary.

uint16_t bufLen

Length of received buffer.

uint16_t vid

VLAN ID.

uint16_t dei

VLAN DEI.

uint16_t pcp

VLAN PCP.

uint8_t tpid

VLAN TPID.

uint8_t hr

Host Reason.

uint8_t flags

Rx information flags.

uint8_t error

Rx error code.

uint8_t isReady

Received data ready flag.

uint8_t isFinal

Final BD flag.

union __unnamed206__

Public Members

struct _netc_rx_bd

uint32_t rssHashSwt

RSS hash while not used as switch management port.

struct __unnamed208__

Public Members

uint32_t srcPort

Source port received from switch management port.

uint32_t rssHash

RSS Hash high field value.

struct ext

Public Members

uint32_t timestamp

Rx Timestamp.

Hardware Switch

enum _netc_swt_port_bitmap

The switch port bitmap.

Values:

enumerator kNETC_SWTPort0Bit

Switch port0 bitmap

enumerator kNETC_SWTPort1Bit

Switch port1 bitmap

enumerator kNETC_SWTPort2Bit

Switch port2 bitmap

enumerator kNETC_SWTPort3Bit

Switch port3 bitmap

enumerator kNETC_SWTPort4Bit

Switch port4 (internal port) bitmap

enum _netc_swt_imr_dest_port

The switch ingress mirror destination port.

Values:

enumerator kNETC_SWTPort0

Switch port0

enumerator kNETC_SWTPort1

Switch port1

enumerator kNETC_SWTPort2

Switch port2

enumerator kNETC_SWTPort3

Switch port3

enumerator kNETC_SWTPort4

Switch port4

enumerator kNETC_SWTMPort

Switch management port

enum _netc_swt_mac_forward_mode

The switch MAC forwarding options.

Values:

enumerator kNETC_NoFDBLookUp

No FDB lookup is performed, the frame is flooded.

enumerator kNETC_FDBLookUpWithFlood

FDB lookup is performed, and if there is no match, the frame is flooded to the port bitmap in VLAN filter entry.

enumerator kNETC_FDBLookUpWithDiscard

FDB lookup is performed, and if there is no match, the frame is discarded.

enum _netc_swt_mac_learn_mode

The switch MAC learning options.

Values:

enumerator kNETC_DisableMACLearn

Disable MAC learning. SMAC FDB lookup is by-passed.

enumerator kNETC_HardwareMACLearn

Hardware MAC learning is enabled.

enumerator kNETC_SeSoftwareMACLearn

Software MAC learning secure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is redirected to the switch management port.

enumerator kNETC_UnseSoftwareMACLearn

Software MAC learning unsecure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is copied to the switch management port.

enumerator kNETC_DisableMACLearnWithSMAC

Disable MAC learning with SMAC validation. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is discarded.

enum _netc_swt_port_tx_vlan_act

Switch transmit Bridge Port VLAN Tag Action.

Values:

enumerator kNETC_NoTxVlanModify

No egress VLAN modification performed

enumerator kNETC_TxDelOuterVlan

Delete outer VLAN tag

enumerator kNETC_TxReplOuterVlanVid

Replace outer VLAN tag’s VID with 0; frame to be transmitted as a priority tag frame

enum _netc_swt_port_stg_mode

Switch port spanning tree group work mode.

Values:

enumerator kNETC_DiscardFrame

Tx or RX Frames on this port with current spanning tree group ID will be discarded

enumerator kNETC_LearnWithoutFowrad

RX Frames on this port with current spanning tree group ID will do Learn SMAC, but do not forward, Tx Frame will be discarded

enumerator kNETC_ForwardFrame

RX Frames on this port with current spanning tree group ID will do both MAC learning and forwarding, , Tx Frame will be forwarded.

typedef enum _netc_swt_port_bitmap netc_swt_port_bitmap_t

The switch port bitmap.

typedef enum _netc_swt_imr_dest_port netc_swt_imr_dest_port_t

The switch ingress mirror destination port.

typedef enum _netc_swt_mac_forward_mode netc_swt_mac_forward_mode_t

The switch MAC forwarding options.

typedef enum _netc_swt_mac_learn_mode netc_swt_mac_learn_mode_t

The switch MAC learning options.

typedef enum _netc_swt_port_tx_vlan_act netc_swt_port_tx_vlan_act_t

Switch transmit Bridge Port VLAN Tag Action.

typedef enum _netc_swt_port_stg_mode netc_swt_port_stg_mode_t

Switch port spanning tree group work mode.

typedef struct _etc_swt_imr_config netc_swt_imr_config_t

Switch Ingress mirror destination config.

typedef struct _netc_swt_port_config netc_swt_port_bridge_config_t

Switch port bridge configuration.

typedef struct _netc_swt_port_fm_config netc_swt_port_fm_config_t

Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP])

typedef struct _netc_swt_default_vlan_filter netc_swt_default_vlan_filter_t

Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup.

typedef struct _netc_swt_bridge_config netc_swt_bridge_config_t

Bridge config.

typedef struct _netc_swt_psfp_config netc_swt_psfp_config_t

Switch PSFP configuration.

typedef struct _netc_qos_classify_config netc_swt_qos_classify_config_t

Switch Qos Classification configuration (include two profiles)

typedef struct _netc_swt_qos_to_vlan_config netc_swt_qos_to_vlan_config_t

Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag.

typedef struct _netc_switch_inuse_fdb_statistic netc_switch_inuse_fdb_statistic_t

Switch static/dynamic FDB entries in-use statistic.

typedef struct _netc_swt_port_sr_config netc_swt_port_sr_config_t

Port seamless redundancy configuration.

struct _etc_swt_imr_config

#include <fsl_netc.h>

Switch Ingress mirror destination config.

Public Members

bool enMirror

Enable ingress mirroring

netc_swt_imr_dest_port_t destPort

Port where ingress mirrored frames are sent

uint8_t dr

Mirrored packet’s DR (drop resilience)

uint8_t ipv

Mirrored packet’s IPV (internal priority value)

uint8_t efmLengthChange

Egress Frame Modification Frame Length change in 2s complement notation, Vaild if efmEntryID is noy null

uint16_t efmEntryID

Egress Frame Modification Entry Id, note 0xFFFF is a Null Frame Modification Entry, Only applicable if destPort != kNETC_SWTMPort

struct _netc_swt_port_config

#include <fsl_netc.h>

Switch port bridge configuration.

Public Members

netc_swt_port_tx_vlan_act_t txVlanAction

Only applies for the frame outer VLAN tag’s VID is equal to the port default VID

bool isRxVlanAware

Receive VLAN Aware Mode

bool acceptUntag

Accept untagged frame

bool acceptPriorityTag

Accept priority tagged frame (VID = 0)

bool acceptSingleTag

Accept single tagged frame

bool acceptDoubleTag

Accept double tagged frame (ounter and inner)

bool enSrcPortPrun

Enable/Disable received frame be transmitted to same port it was received

bool enMacStationMove

Enable/Disable received frame which ingress port not match the FDB entry Destination Port Bitmap

bool enBcastStormCtrl

Enable/Disable Storm control for broadcast frames

bool enMcastStormCtrl

Enable/Disable Storm control for multicast frames

bool enUnMcastStormCtrl

Enable/Disable Storm control for unknown multicast frames

bool enUnUcastStormCtrl

Enable/Disable Storm control for unknown unicast frames

uint32_t bcastRpEntryID

Broadcast rate policer entry ID. Valid if enBroadStormCtrl = true

uint32_t mcastEntryID

Known multicast rate policer entry ID. Valid if enBroadStormCtrl = true

uint32_t unMcastRpEntryID

Unknown multicast policer entry ID. Valid if enUnMultiStormCtrl = true

uint32_t unUcastRpEntryID

Unknown unicast rate policer entry ID. Valid if enUnUniStormCtrl = true

uint16_t maxDynaFDBEntry

The maximium number of dynamic entries in the FDB table, 0 means no limit

struct _netc_swt_port_fm_config

#include <fsl_netc.h>

Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP])

Public Members

bool ignoreFMMiscfg

Enable/Disable ignore the Frame Modification Misconfiguration Action

bool enEgressPcpMap

Enable egress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action

bool enIngressPcpMap

Enable ingress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action

bool enUpdateVlanDei

Enable update DR value in the outer VLAN based on DEnDEI field, used for egress Frame Modification Outer DEI action

uint8_t drToDeiMap

Mapping of internal QoS’s DR value n to VLAN DEI, The 4 bits correspond to the DR3 ~ DR0, and 1 means DRn mapping to DEI 1, 0 means DRn mapping to DEI 0

uint8_t egressPcpMap

Egress PCP to PCP Mapping Profile instance, active when enEgressPcpMap is true

uint8_t ingressPcpMap

Ingress PCP to PCP Mapping Profile instance, active when enIngressPcpMap is true

uint8_t qosVlanMap

Transmit QoS to VLAN PCP Mapping Profile index, used for egress Frame Modification VLAN Add/Replace Action

struct _netc_swt_default_vlan_filter

#include <fsl_netc.h>

Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup.

Public Members

bool enIPMFlood

Enable IP Multicast Flooding

bool enIPMFilter

Enable IP Multicast Filtering

uint8_t stgID

Spanning Tree Group Member ID, range in 0 ~ 15

uint8_t portMembership

The bit 0 ~ 4 correspond to the 5 ports, When bit set (0b1), means the port is a member of this VLAN. Port membership is used for source/destination pruning

bool enUseFilterID

Enable use the specified filterID as FID, otherwise will use the frame VID

uint16_t filterID

Used as a key value to do FDB table and the L2 IPV4 Multicast Filter table lookup. Valid if enUseFilterID is true

netc_swt_mac_forward_mode_t mfo

MAC forwarding options

netc_swt_mac_learn_mode_t mlo

MAC learning options

uint16_t baseETEID

Base Egress Treatment Entry ID

uint8_t etaPortBitmap

Egress Treatment Applicability Port. Valid if baseETEID is not null.

struct _netc_swt_bridge_config

#include <fsl_netc.h>

Bridge config.

Public Members

netc_swt_default_vlan_filter_t dVFCfg

Default VLAN filter entry configuration when not found in VLAN filter lookup

struct _netc_swt_psfp_config

#include <fsl_netc.h>

Switch PSFP configuration.

Public Members

netc_isi_kc_rule_t kcRule[4]

Key construction rules

struct _netc_qos_classify_config

#include <fsl_netc.h>

Switch Qos Classification configuration (include two profiles)

struct _netc_swt_qos_to_vlan_config

#include <fsl_netc.h>

Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag.

struct fsl_netc

#include <fsl_netc.h>

Public Members

uint8_t qos[32]

Index is created from IPV (3 bits) + DR (2 bits) field. Value is the mapped PCP for VLAN tag.

uint8_t pcp[8]

Index is created from outer PCP (3 bits) field. Value is the mapped PCP for VLAN tag.

struct _netc_switch_inuse_fdb_statistic

#include <fsl_netc.h>

Switch static/dynamic FDB entries in-use statistic.

Public Members

uint16_t camEntries

Number of FDB entries in-use in the CAM.

uint16_t staticEntries

Number of static FDB entries in-use (both hash-based and CAM-based entries).

uint16_t dynamicEntries

Number of dynamic FDB entries in-use (hash-based and CAM-based entries).

uint16_t dynamicEntriesHWM

High water mark of dynamic entries in-use in the FDB table.

struct _netc_swt_port_sr_config

#include <fsl_netc.h>

Port seamless redundancy configuration.

struct defaultVlan

Public Members

uint32_t vid

Vlan Identifier.

uint32_t dei

Drop eligible indicator

uint32_t pcp

Priority code point.

uint32_t tpid

Tag protocol identifier, 0 = Standard C-VLAN 0x8100, 1 = Standard S-VLAN 0x88A8.

Hardware Table Access Functions

enum _netc_tb_index

Table index.

Values:

enumerator kNETC_TGSTable

Time Gate Scheduling table index

enumerator kNETC_RPTable

Rate Policer table index

enumerator kNETC_IPFTable

Ingress Port filter table index

enumerator kNETC_FDBTable

FDB table index

enumerator kNETC_L2MCFTable

L2 IPV4 Multicast Filter table index

enumerator kNETC_VFTable

VLAN Filter table index

enumerator kNETC_ECQTable

ETM Class Queue table index

enumerator kNETC_ECSTable

ETM Class Scheduler table index

enumerator kNETC_ISITable

Ingress Stream Identification table index

enumerator kNETC_ISTable

Ingress Stream table index

enumerator kNETC_ISFTable

Ingress Stream Filter table index

enumerator kNETC_ETTable

Egress Treatment table index

enumerator kNETC_ISGTable

Ingress Sequence Generation table index

enumerator kNETC_ESRTable

Egress Sequence Recovery table index

enumerator kNETC_SGITable

Stream Gate Instance table index

enumerator kNETC_SGCLTable

Stream Gate Control List table index

enumerator kNETC_ISCTable

Ingress Stream Count table index

enumerator kNETC_ECTable

Egress Count table index

enumerator kNETC_FMTable

Frame Modification table index

enumerator kNETC_BPTable

Buffer Pool table index

enumerator kNETC_SBPTable

Shared Buffer Pool table index

enumerator kNETC_ECGTable

ETM Class Group table index

enumerator kNETC_FMDTable

Frame Modification Data table index

enum _netc_tb_cmd

Table management command operations.

Values:

enumerator kNETC_DeleteEntry

Delete operation

enumerator kNETC_UpdateEntry

Update operation

enumerator kNETC_QueryEntry

Query operation

enumerator kNETC_QueryAndDeleteEntry

Query operation followed by a delete operation

enumerator kNETC_QueryAndUpdateEntry

Query operation followed by a update operation

enumerator kNETC_AddEntry

Add operation

enumerator kNETC_AddOrUpdateEntry

If the entry exists, is update operation, if not exist, is the Add operation

enumerator kNETC_AddAndQueryEntry

Add operation followed by a query operation

enumerator kNETC_AddQueryAndUpdateEntry

Add operation followed by a query operation, Then, if the entry existed prior to the Add operation of this command, the Update operation will be performed.

enum _netc_tb_access_mode

Table Access Method.

Values:

enumerator kNETC_EntryIDMatch

Entry ID Match

enumerator kNETC_ExactKeyMatch

Exact Match Key Element Match

enumerator kNETC_Search

Search with search criteria

enumerator kNETC_TernaryKeyMatch

Ternary Match Key Element Match

enum _netc_cbd_version

NTMP version.

Values:

enumerator kNETC_NtmpV1_0

NTMP Version 1.0

enumerator kNETC_NtmpV2_0

NTMP Version 2.0

enum _netc_cmd_error

Table command response error status.

Values:

enumerator kNETC_FormatError

Format error : 1. Illegal class or command. 2. Invalid SF bit setting. 3. LENGTH is zero for long format. 4. LENGTH is too small for buffer size.

enumerator kNETC_SizeError

Size error : 1. Invalid table index, out of range. 2. Table overflow, no additional entries available.

enumerator kNETC_AccessError

Access violation error, the entity is not allowed to perform the task requested

enumerator kNETC_ClassError

Class specific error

enumerator kNETC_IntegrityError

Integrity error, the command did not execute due to a data integrity error (ECC on internal memory or AXI read/write error)

enumerator kNETC_InvTableID

Invalid table ID

enumerator kNETC_InvAccMethod

Invalid Access method

enumerator kNETC_TableIdxOutRange

Table index out of range

enumerator kNETC_DBNotEnough

Request data buffer size or response data buffer size is not sufficient

enumerator kNETC_InvCmd

Invalid command

enumerator kNETC_ReqDBError

Request Data buffer error

enumerator kNETC_MultiBitError

Multi-bit ECC or parity error observed during command processing

enumerator kNETC_HashEntryLimit

Exceeded hash entry limit

enumerator kNETC_HashChainLimit

Exceeded maximum hash collision chain limit and the CAM if present is full

enumerator kNETC_InvHWGenEntryID

Invalid ENTRY_ID for ENTRY_ID generated by hardware

enumerator kNETC_SrchResDBNotEnough

Search command filled the response data buffer before completing the command

enumerator kNETC_CmdIdxTableWithITM

Command for index table before OSR[ITM_STATE]=0

enumerator kNETC_InvQueryAction

Invalid Query action

enumerator kNETC_InvTableAccPrivilege

Invalid table access privilege

enumerator kNETC_ReadSysBusErr

System Bus Read Error

enumerator kNETC_WriteSysBusErr

System Bus Write Error

enumerator kNETC_ClientErr

Client encountered a fault

enumerator kNETC_TGSCmdIssue

Command issued when time gating function is disabled for the port.

enumerator kNETC_TGSUpdateExistList

Update action attempted on an existing admin gate control list. (should delete admin gate control list first before creating a new admin list)

enumerator kNETC_TGSUpdateOverLength

Update action attempted exceeds TGSTCAPR[MAX_GCL_LEN]

enumerator kNETC_TGSUpdateOverSize

Update action attempted exceeds TGSTCAPR[NUM_WORDS].

enumerator kNETC_TGSEntryNotEnough

Insufficient resources to perform the requested operation (not enough free time gate list entries)

enumerator kNETC_TGSUpdateNSList

Update action attempted with ADMIN_CYCLE_TIME, ADMIN_TIME_INTERVAL_GE_i or truncated ADMIN_TIME_INTERVAL_GE_n due ADMIN_CYCLE_TIME specified is not sufficient to transmit 64 byte of frame data + header overhead.

enumerator kNETC_TGSUpdateEarlierStartTime

Update action attempted with ADMIN_BASE_TIME specified s more than one second in the past from tcs advance time.

enumerator kNETC_TGSUpdateOverflowCycle

Update action attempted with ADMIN_CYCLE_TIME + ADMIN_CYCLE_TIME_EXT is greater than 2^32-1.

enumerator kNETC_TGSQueryBeforeListActive

Query action issued when config change occurred. Retry query.

enumerator kNETC_TGSUpdateInvGateValue

Update action attempted with ADMIN_HR_CB_GE_i set to an invalid value

enumerator kNETC_RPSDUTypeOutRange

SDU_TYPE specified in entry CFGE_DATA is out of range

enumerator kNETC_IPFInvHR

HR value not valid. Only checked if command issued from the Switch and FLTFA=0x2 or FLTFA=0x3

enumerator kNETC_IPFEntryNotFit

Entry being added does not fit in table

enumerator kNETC_IPFWithoutSTSE

CFGE_DATA update without STSE_DATA update

enumerator kNETC_IPFInvRPP

RPR set to a reserved value. Only checked if FLTA=0x2.

enumerator kNETC_IPFFLTATGTOutRange

FLTA_TGT is outside valid range and not NULL. Only checked if FLTA>0x0

enumerator kNETC_IPFInvSwtFLTA

FLTA=0x3 when command issued from the Switch.

enumerator kNETC_IPFInvEnetcFLTA

FLTFA>0x1 when command issued from an ENETC PF.

enumerator kNETC_FDBReachPortLimit

Failed to add or update and entry because the Port BPCR[DYN_LIMIT] has been reached

enumerator kNETC_FDBReachSwtLimit

Failed to add entry because the Switch FDBHTMCR[DYN_LIMIT] has been reached.

enumerator kNETC_FDBInvEPORT

EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1)

enumerator kNETC_FDBETEIDOutRange

ET_EID is out of range and not NULL. Only checked if OETEID>0x0

enumerator kNETC_FDBParityErr

Parity error encountered when adding guaranteed entry

enumerator kNETC_L2MCFInvEPORT

EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1)

enumerator kNETC_L2MCFETEIDOutRange

ET_EID is not NULL or within the valid range. Only checked if OETEID>0x0.

enumerator kNETC_L2MCFInvKEYTYPE

KEY_TYPE value not valid

enumerator kNETC_VFBASEETEIDOutRange

BASE_ET_EID is out of range or MLO is not valid.

enumerator kNETC_ECQCQ2CGMAPOutRange

CQ2CG_MAP value out-of-range in update command.

enumerator kNETC_ISIPortIDOutRange

Port ID specified in KEYE_DATA is out of range.

enumerator kNETC_ISIInvISEID

IS_EID in invalid.

enumerator kNETC_ISInvOpt

Option specified in one or more of the following fields is not valid – FA, CTD or ISQA, SDU_TYPE.

enumerator kNETC_ISInvID

One or more of following : 1. Entry IDs are not in valid range or Entry ID is not Null. 2. Check valid ranges specified for these Entry IDs in Ingress Stream table entry – RP_EID, SGI_EID, ISQ_EID, ET_EID or EPORT. 3. ET_EID is checked if (FA =010b .. 101b) & (OETEID!=0). 4. EPORT is checked if (FA = 010b .. 101b) & (OETEID= 0x1 OR CTD= 0x1). 5. HR is chked if FA = 001b, 100b, or 101b. HR specified cannot be 0x0

enumerator kNETC_ISInvFMEID

FM_EID format or index is out of range : 1. FM_EID format option type is invalid. 2. FM_EID format is option 1 and the Index is out of range and not Null, or FM_EID format is option 2 and VUDA or SQTA is out of range.

enumerator kNETC_ISFInvISEID

IS_EID in KEYE_DATA is invalid.

enumerator kNETC_ISFInvCFGE

Any of the following in CFGE_DATA is invalid : 1. One or more of following Entry IDs are not in valid range or Entry ID specified is not Null. Checks are performed for following Entry IDs CFGE DATA – RP_EID, SGI_EID, ISC_EID. 2. SDU_TYPE is invalid

enumerator kNETC_ETInvOpt

Command option specified is invalid or not supported. ESQA is not 00 or 10 (others are reserved), or ECA > 1 (reserved).

enumerator kNETC_ETInvFMEID

FM_EID format or index is out of range. Check performed is as follows : 1. EFM_EID format option type is invalid, or EFM_EID format is option 1 and the Index is out of range and not Null, or EFM_EID format is option 2 and VUDA or SQTA is out of range . 2. the Egress Counter Table index EC_EID is out of range. 3. The Egress Sequence Actions Target Entry ID ESQA_TGT_EID is out of range

enumerator kNETC_ISGInvQSTAG

SQ_TAG specified is not valid

enumerator kNETC_SGISGCLEIDOutRange

SGCL_EID specified in out of range for Add or Update operation.

enumerator kNETC_SGIInvSDUTYPE

SDU_TYPE is specified is invalid for Add or Update operation.

enumerator kNETC_SGISGCLEIDNotAlloc

Either the SGCL_EID specified as admin gate control list in Add or Update operation has not been allocated or SGCL_EID is not the first entry in gate control list or the reference count in SGCL entry is not 0.

enumerator kNETC_SGIInvSGCLEID

SGCL_EID specified for Update operation is in invalid.

enumerator kNETC_SGIInvADMINBASETIME

ADMIN_BASE_TIME specified for Add or Update operation is more than 2^30ns in the past.

enumerator kNETC_SGIInvCYCLETIME

Cumulated time value of CYCLE_TIME in Stream gate Control list plus CYCLE_TIME_EXT specified in Add or Update operation is >=2^30ns or CYCLE_TIME specified is 0.

enumerator kNETC_SGCLOverLength

Number words required for the LIST_LENGTH specified for the Add operation exceeds the number of words allocated for SGCL table

enumerator kNETC_SGCLTimeIntervalZero

TIME_INTERVAL_GE_N specified in Add operation is 0. Note that upper 2 bits of TIME_INTERVAL_GE_N are ignored, TIME_INTERVAL_GE_N[29:0] must not be 0.

enumerator kNETC_SGCLTimeIntervalOverflow

Cumulated time value of TIME_INTERVAL_GE_N[29:0] for the gate list specified in Add operation is >= 2^30ns.

enumerator kNETC_FMInvEMEID

FM_EID format is invalid

enumerator kNETC_FMOptOutRange

Following fields specified are out of range - MAC_HDR_ACT, VLAN_HDR_ACT, SQT_ACT, OUTER_PCP_DEI_ACT, PLD_ACT.

enumerator kNETC_FMFMDOutRange

FMD_EID,FMD_BYTES specified is out of range. When FMD_EID is not set to Null, valid range is FMD_EID[15:0]*24 + FMD_BYTES <= (FMDITCAPR[NUM_WORDS]*24).

enumerator kNETC_BPSBPEIDOutRange

SBP_EN is 1 and SBP_EID value is out-of-range in update command

enum _netc_fm_vlan_ud_act

Frame Modification VLAN Update/Delete Action.

Note

Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame.

Values:

enumerator kNETC_NoUDVlanAction

No Update/Delete VLAN action

enumerator kNETC_ReplVlanPcpAndDei

Replace outer VLAN’s PCP/DEI based on the port’s PPCPDEIMR. The tag’s original VID and TPID are preserved

enumerator kNETC_DelVlan

Delete outer VLAN Tag

enum _netc_fm_sqt_act

Frame Modification Sequence Tag Action.

Note

Must be set to 000b for Ingress frame modification, otherwise misconfiguration error..

Values:

enumerator kNETC_NoSqtAction

No SQT action

enumerator kNETC_ReomveRTag

Remove R-TAG/draft 2.0 R-TAG/HSR tag, If R-TAG/HSR tag not present, misconfiguration error.

enum _netc_fm_vlan_ar_act

Frame Modification VLAN Add/Replace Action.

Note

For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value.

Values:

enumerator kNETC_AddCVlanPcpAndDei

Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x8100

enumerator kNETC_AddSVlanPcpAndDei

Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x88A8

enumerator kNETC_ReplVidOnly

Replace VLAN with VID. The tag’s original PCP, DEI and TPID are preserved

enumerator kNETC_ReplVidPcpAndDei

Replace VLAN with VID and PCP/DEI updated by port’s PPCPDEIMR. The tag’s original TPID is preserved

enum _netc_tb_eteid_access_mode

Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode.

Note

The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached

Values:

enumerator kNETC_NoETAccess

No Egress Treatment table access

enumerator kNETC_SinglePortETAccess

Only frame sent to a special port (define in ePort) can access a single Egress Treatment table entry, the applicability bitmap specified by FDB/L2MCF/IS ePort field

enumerator kNETC_MulitPortPackedETAccess

Only frames sent to a special set of ports (ports set to 1 in ePortBitmap) can access the Egress Treatment table, the applicability bitmap = IS ePortBitmap field or FDB/L2MCF portBitmap field

enumerator kNETC_MulitPortAbsETAccess

Frames sent to all of ports can access the Egress Treatment table, means the applicability bitmap is set with 1 for all ports

enum _netc_tb_ipf_update_action

Ingress Port Filter Table Update Actions.

Values:

enumerator kNETC_IPFCfgEUpdate

Configuration Element Update

enumerator kNETC_IPFStsEUpdate

Statistics Element Update

enum _netc_tb_ipf_attr_mask

Ingress Port Filter frame attribute mask.

Values:

enumerator kNETC_IPFSwtPortMasMask

Switch port masquerading Mask

enumerator kNETC_IPFEthernetMask

Ethernet type Mask

enumerator kNETC_IPFOuterVlanMask

Outer VLAN Mask

enumerator kNETC_IPFInnerVlanMask

Inner VLAN Mask

enumerator kNETC_IPFSeqTagMask

Sequence Tag Code Mask

enumerator kNETC_IPFIpHeaderMask

IP Header Mask

enumerator kNETC_IPFIpVersionMask

IP Version Mask

enumerator kNETC_IPFIpExtMask

IPv4 option / IPv6 extension Mask

enumerator kNETC_IPFL4HeaderMask

L4 Code Mask

enumerator kNETC_IPFWakeOnLanMask

Wake-on-LAN Magic Packet Mask

enum _netc_tb_ipf_seq_tag

Ingress Port Filter frame attribute Sequence Tag Code.

Values:

enumerator kNETC_IPFNoRtag

R-TAG/HSR tag is not present

enumerator kNETC_IPFDraftRtag

802.1CB draft 2.0 R-TAG is present

enumerator kNETC_IPFRtag

802.1CB R-TAG is present

enumerator kNETC_IPFHsrTag

HSR Tag is present

enum _netc_tb_ipf_l4_header

Ingress Port Filter frame attribute L4 Header Code.

Values:

enumerator kNETC_IPFOtherL4

The L4 Header is considered as other L4 if it is not one of the following L4 Headers

enumerator kNETC_IPFTcp

TCP header is present

enumerator kNETC_IPFUdp

UDP header is present

enumerator kNETC_IPFSctp

SCTP header is present

enum _netc_tb_ipf_forward_action

Ingress port filter forwarding Action.

Values:

enumerator kNETC_IPFForwardDiscard

Frame be discard

enumerator kNETC_IPFForwardPermit

Frame be permit

enumerator kNETC_IPFRedirectToMgmtPort

Redirect frame to switch management port without any frame modification, Switch only

enumerator kNETC_IPFCopyToMgmtPort

Copy frame to switch management port without any frame modification, Switch only

enum _netc_tb_ipf_filter_action

Ingress port filter Filter Action.

Values:

enumerator kNETC_IPFNoAction

No action

enumerator kNETC_IPFWithRatePolicer

Rate action with the Rate Policer Entry ID (RP_EID) set to the value configured in the fltaTgt field

enumerator kNETC_IPFWithIngressStream

Ingress stream identification action where the Ingress Stream Entry ID (IS_EID) is set to the value configured in the fltaTgt field

enumerator kNETC_IPFWithL2Filtering

Setting a pre L2 filtering SI bitmap (set to the value configured in the fltaTgt) that will be used by the L2 filtering function to determine the final SI bitmap, ENETC only

enum _netc_tb_isi_key_type

Stream identification table key type.

Values:

enumerator kNETC_KCRule0

Use key construction rule 0 (ISIDKC0CR0)

enumerator kNETC_KCRule1

Use key construction rule 1 (ISIDKC1CR0)

enumerator kNETC_KCRule2

Use key construction rule 2 (ISIDKC2CR0). Only for SWITCH

enumerator kNETC_KCRule3

Use key construction rule 3 (ISIDKC3CR0). Only for SWITCH

enum _netc_tb_is_isq_action

Ingress Stream table Ingress Sequence Action.

Values:

enumerator kNETC_ISNotPerformFRER

Not perform Frame FRER sequence generation function

enumerator kNETC_ISPerformFRER

Perform Frame FRER sequence generation function

enum _netc_tb_is_forward_action

Ingress Stream table forwarding Action.

Values:

enumerator kNETC_ISDiscard

Frame be discard

enumerator kNETC_ISRedirectToMgmtPort

Frame be Re-direct frame to switch management port, Switch only

enumerator kNETC_ISAllow

Frame is allow without setting the pre L2 filtering SI bitmap, ENETC only

enumerator kNETC_ISAllowWithSIMap

Frame is allow with setting the pre L2 filtering SI bitmap to the value configured in the SI_MAP field, ENETC only

enumerator kNETC_ISStreamForward

Frame is forwarded to the port(s) specified in the EGRESS_PORT_BITMAP field, Switch only

enumerator kNETC_ISBridgeForward

Frame is do 802.1Q Bridge forwarding (VLAN processing and L2 forwarding), Switch only

enumerator kNETC_ISCopyToMgmtPortAndStream

Copy frame to switch management port with specified HR and stream forwarding, Switch only

enumerator kNETC_ISCopyToMgmtPortAndBridge

Copy frame to switch management port with specified HR and Bridge forwarding, Switch only

enum _netc_tb_is_ctd_mode

Ingress Stream table Cut-Through Disable mode.

Values:

enumerator kNETC_ISNoCTD

Do not override cut-through state

enumerator kNETC_ISSinglePortCTD

Disable cut-through for the outgoing port specified in the cfge ePort field

enumerator kNETC_ISAllPortCTD

Disable cut-through for all ports specified in cfge portBitmap field

enum _netc_tb_rp_update_action

Rate Policer Table Update Actions.

Values:

enumerator kNETC_RPCfgEUpdate

Configuration Element Update

enumerator kNETC_RPFeEUpdate

Functional Enable Element Update

enumerator kNETC_RPPsEUpdate

Policer State Element Update Element Update

enumerator kNETC_RPStsEUpdate

Statistics Element Update

enum _netc_tb_sgi_update_action

Stream Gate Instance table Update Actions.

Values:

enumerator kNETC_SGIAcfEUpdate

Admin Configuration Element

enumerator kNETC_SGICfgEUpdate

Configuration Element Update

enumerator kNETC_SGISgisEUpdate

Stream Gate Instance State Element Update

enum _netc_tb_sgi_state

Stream Gate Instance State.

Values:

enumerator kNETC_GSNotOper

Gate instance is not operational or Gate instance and lists are not valid

enumerator kNETC_GSUseDefaultParam

Gate instance is operational but no stream gate control list specified, use default Gate Instance parameters

enumerator kNETC_GSUseDefUntilAdminAct

Use default Gate Instance parameters until administrative stream gate control list takes effect

enumerator kNETC_GSUseOperUntilAdminAct

Use Operational stream gate control list until new administrative stream gate control list takes effect

enumerator kNETC_GSUseOperList

Operational stream gate control list is in effect

enum _netc_tb_fm_layer2_act

Frame Modification table Layer 2 Actions.

Note

This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.

Values:

enumerator kNETC_UseL2HeaderAct

L2 actions are specified in L2 header action fields macHdrAct, vlanHdrAct and sqtAct

enumerator kNETC_UseSpecPlayload

The entire L2 PDU is replaced with fmdBytes of data specified in fmdEID, not applicable for ingress frame modifications

enum _netc_tb_fm_mac_header_act

Frame Modification table Layer 2 Header MAC Actions.

Note

Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac.

Values:

enumerator kNETC_NoMacAction

No Mac header action

enumerator kNETC_ReplSmac

Replace SMAC with the contents of the port’s PMAR0/1 register, The port is specified by smacPort field

enumerator kNETC_ReplSmacAndDmacAct1

Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by dmac[6] field

enumerator kNETC_ReplSmacAndDmacAct2

Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by frame’s SMAC

enumerator kNETC_ReplDmac

Replace DMAC with specified dmac[6] field value

enumerator kNETC_SwapDmacAndSmac

Swap DMAC and SMAC

enum _netc_tb_fm_vlan_header_act

Frame Modification table Layer 2 VLAN Actions.

Note

For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

Values:

enumerator kNETC_NoVlanAction

No VLAN header action

enumerator kNETC_DelOuterVlan

Delete outer VLAN header

enumerator kNETC_AddOuterVlan

Add outer VLAN header (new VLAN data will be inserted in the outer position), the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field

enumerator kNETC_ReplOuterVlan

Replace outer VLAN header, the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field

enum _netc_tb_fm_outer_vid_act

Frame Modification table Layer 2 outer VLAN VID Actions.

Note

For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

Values:

enumerator kNETC_UseFrameVid

Use the VID from the valid outer VLAN header of the received frame

enumerator kNETC_UseSpecVid

Use the VID specified in the outerVlanID field

enum _netc_tb_fm_outer_tpid_act

Frame Modification table Outer TPID action.

Note

For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

Values:

enumerator kNETC_UseFrameTpid

Use TPID from outer VLAN header

enumerator kNETC_UseStdCVlan

Set TPID to Standard C-VLAN 0x8100

enumerator kNETC_UseStdSVlan

Set TPID to Standard S-VLAN 0x88A8

enumerator kNETC_UseCustomCVlan

Set TPID to Custom C-VLAN as defined by CVLANR1[ETYPE]

enumerator kNETC_UseCustomSVlan

Set TPID to Custom S-VLAN as defined by CVLANR2[ETYPE]

enum _netc_tb_fm_outer_pcp_act

Frame Modification table Outer PCP action.

Note

For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

Values:

enumerator kNETC_UseFramePcp

Use PCP from frame outer VLAN header

enumerator kNETC_UseSpecPcp

Use the PCP specified in the outerVlanPcp field

enumerator kNETC_UseFramePcpMap

The PCP is mapping from frame outer VLAN PCP (do mapping according to the PCP to PCP mapping profile which specified in PPCPDEIMR[IPCPMP/EPCPMP])

enumerator kNETC_UseQosMap

The PCP is mapping from internal QoS (IPV, DR) (do mapping according to the QOS to PCP mapping profile which specified in QOSVLANMPaR0/1/2/3), not applicable for ingress frame modifications

enum _netc_tb_fm_outer_dei_act

Frame Modification table Outer DEI action.

Note

For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

Values:

enumerator kNETC_UseFrameDei

Use DEI from frame outer VLAN header

enumerator kNETC_UseSpecDei

Use the DEI specified in the outerVlanDei field

enumerator kNETC_UseDrMap

The DEI is mapping from internal DR (do mapping according to the DR to DEI mapping profile which specified in PPCPDEIMR[DRnDEI], not applicable for ingress frame modifications

enum _netc_tb_fm_payload_act

Frame Modification table Payload Actions.

Note

This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.

Values:

enumerator kNETC_NoAction

No Action

enumerator kNETC_ReplAllEthPld

Remove entire Ethernet payload and insert with fmdBytes of data specified in fmdEID

enumerator kNETC_ReplPldWithOffset

Replace fmdBytes of raw data in the Ethernet payload starting at pldOffset, data specified in fmdEID

enum _netc_tb_fdb_update_action

FDB table Update Actions.

Values:

enumerator kNETC_FDBCfgEUpdate

Configuration Element Update

enumerator kNETC_FDBActEUpdate

Activity Element Update

enum _netc_tb_fdb_ctd_mode

FDB table Cut-Through Disable mode.

Values:

enumerator kNETC_FDBNoCTD

Do not override cut-through state

enumerator kNETC_FDBSinglePortCTD

Disable cut-through for the outgoing port specified in the cfge ePort field

enumerator kNETC_FDBAllPortCTD

Disable cut-through for all ports specified in cfge portBitmap field

enum _netc_tb_fdb_sc_keye_mc

FDB table search criteria Key Element Match Criteria.

Values:

enumerator kNETC_FDBKeyeMacthAny

Match any Key Element Criteria

enumerator kNETC_FDBKeyeMacthFID

Match Key Element FID

enumerator kNETC_FDBKeyeMacthMacMulticast

Match Key Element MAC Multicast bit (MAC_ADDR most significant byte’s least significant bit)

enumerator kNETC_FDBKeyeMacthBoth

Match both FID field and MAC Multicast bit

enum _netc_tb_fdb_sc_cfge_mc

FDB table search criteria Configuration Element Match Criteria.

Values:

enumerator kNETC_FDBCfgeMacthAny

Match any Configuration Element Criteria

enumerator kNETC_FDBCfgeMacthDynamic

Match Configuration Element dynamic field

enumerator kNETC_FDBCfgeMacthPortBitmap

Match Configuration Element portBitmap field

enumerator kNETC_FDBCfgeMacthBoth

Match both dynamic field and portBitmap

enum _netc_tb_fdb_sc_acte_mc

FDB table search criteria Activity Element Match Criteria.

Values:

enumerator kNETC_FDBActeMacthAny

Match any Activity Element Criteria

enumerator kNETC_FDBActeMatchExact

Exact match with Activity Element

enum _netc_tb_l2mcf_key_type

L2 IPV4 Multicast Filter table key type.

Values:

enumerator kNETC_IPv4ASMKey

Key consists of a filtering ID (FID) and destination multicast IPv4 address

enumerator kNETC_IPv4SSMKey

Key consists of a filtering ID (FID), IPv4 source address and multicast IPv4 destination address

enum _etc_tb_l2mcf_sc_keye_mc

L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria.

Values:

enumerator kNETC_L2MCFKeyeMacthAny

Match any Key Element Criteria

enumerator kNETC_L2MCFKeyeMacthFID

Match Key Element FID

enum _etc_tb_l2mcf_sc_cfge_mc

L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria.

Values:

enumerator kNETC_L2MCFCfgeMacthAny

Match any Configuration Element Criteria

enumerator kNETC_L2MCFCfgeMacthDynamic

Match Configuration Element dynamic field

enumerator kNETC_L2MCFCfgeMacthPortBitmap

Match Configuration Element portBitmap field

enumerator kNETC_L2MCFCfgeMacthBoth

Match both dynamic field and portBitmap

enum _etc_tb_l2mcf_sc_acte_mc

FDB table search criteria Activity Element Match Criteria.

Values:

enumerator kNETC_L2MCFActeMacthAny

Match any Activity Element Criteria

enumerator kNETC_L2MCFActeMatchExact

Exact match with Activity Element

enum _netc_tb_iseqg_sqtag

Sequence Tag Type.

Values:

enumerator kNETC_SqDraftRTag

802.1CB draft 2.0 R-TAG.

enumerator kNETC_SqRTag

802.1CB R-TAG.

enumerator kNETC_SqHsrTag

HSR Tag.

enum _netc_tb_iseqg_update_action

Ingress Sequence Generation Table Update Actions.

Values:

enumerator kNETC_ISEQGCfgEUpdate

Configuration Element Update

enumerator kNETC_ISEQGSgsEUpdate

Sequence Generation Element Update

enum _netc_tb_eseqr_sqtag

Egress Sequence Recovery table Sequence Tag Type.

Values:

enumerator kNETC_AcceptAnyTag

Accept any incoming tag type (802.1CB draft 2.0 R-TAG, 802.1CB R-TAG or HSR Tag)

enumerator kNETC_AcceptDraftRTag

802.1CB draft 2.0 R-TAG.

enumerator kNETC_AcceptRTag

802.1CB R-TAG.

enumerator kNETC_AcceptHsrTag

HSR Tag.

enum _netc_tb_tgs_entry_id

Time Gate Scheduling table entry ID for switch and ENETC.

Values:

enumerator kNETC_TGSSwtPort0

Switch PORT 0 entry ID

enumerator kNETC_TGSSwtPort1

Switch PORT 1 entry ID

enumerator kNETC_TGSSwtPort2

Switch PORT 2 entry ID

enumerator kNETC_TGSSwtPort3

Switch PORT 3 entry ID

enumerator kNETC_TGSSwtPort4

Switch PORT 4 entry ID

enumerator kNETC_TGSEnetc0Port

ENETC 0 port entry ID

enumerator kNETC_TGSEnetc1Port

ENETC 1 port entry ID

enum _netc_tb_tgs_gate_type

Administrative gate operation type.

Values:

enumerator kNETC_SetGateStates

HoldRequest is unchanged

enumerator kNETC_SetAndHoldMac

HoldRequest is set to value hold, only active when enable preemption

enumerator kNETC_SetAndReleaseMac

HoldRequest is set to value release, only active when enable preemption

enum _netc_tb_et_efm_mode

Egress Frame Modification entry mode.

Values:

enumerator kNETC_NormalMode

Egress Frame Modification entry use normal/Default mode

enumerator kNETC_L2Act1

Egress Frame Modification entry l2Act = kNETC_UseSpecPlayload

enumerator kNETC_PldAct1

Egress Frame Modification entry pldAct = kNETC_ReplAllEthPld

enum _netc_tb_et_esq_act

Egress Sequence Actions.

Values:

enumerator kNETC_NoEsqAction

No Egress Sequence Action required

enumerator kNETC_HasEsqAction

Has Egress Sequence Recovery action

enum _netc_tb_et_ec_act

Egress Counter Action.

Values:

enumerator kNETC_NoEcCounter

Do not increment egress frame counter

enumerator kNETC_HasEcCounter

Increment egress frame counter

enum _netc_tb_etmcq_update_action

ETM Class Queue table Update Actions.

Values:

enumerator kNETC_CQCfgEUpdate

Configuration Element Update

enumerator kNETC_CQStsEUpdate

Statistics Element Update, all counters (except FRM_CNT) within the Statistics Element are reset

enum _netc_tb_etmcs_entry_id

ETM Class Scheduler table entry ID.

Values:

enumerator kNETC_CSSwtPort0

CS Switch PORT 0 entry ID

enumerator kNETC_CSSwtPort1

CS Switch PORT 1 entry ID

enumerator kNETC_CSSwtPort2

CS Switch PORT 2 entry ID

enumerator kNETC_CSSwtPort3

CS Switch PORT 3 entry ID

enumerator kNETC_CSSwtPort4

CS Switch PORT 4 entry ID

enum _netc_tb_etmcs_ca_assg

ETM Class Scheduler table Class queue assignment to scheduler inputs mode.

Values:

enumerator kNETC_CQ7AssignToSchedIn15

CQ 7 assignment to scheduler input 15, means all CQ use strict priority

enumerator kNETC_CQ7AssignToSchedIn14

CQ 7 assignment to scheduler input 14

enumerator kNETC_CQ7AssignToSchedIn13

CQ 7 assignment to scheduler input 13

enumerator kNETC_CQ7AssignToSchedIn12

CQ 7 assignment to scheduler input 12

enumerator kNETC_CQ7AssignToSchedIn11

CQ 7 assignment to scheduler input 11

enumerator kNETC_CQ7AssignToSchedIn10

CQ 7 assignment to scheduler input 10

enumerator kNETC_CQ7AssignToSchedIn9

CQ 7 assignment to scheduler input 9

enumerator kNETC_CQ7AssignToSchedIn8

CQ 7 assignment to scheduler input 8

enumerator kNETC_CQ7AssignToSchedIn7

CQ 7 assignment to scheduler input 7, means all CQ use weighted fair

enum _netc_tb_bp_fc_cfg

Buffer Pool Flow Control (FC) Configuration.

Values:

enumerator kNETC_FlowCtrlDisable

Flow Control disabled

enumerator kNETC_FlowCtrlWithBP

Flow Control enabled using only buffer pool FC state.

enumerator kNETC_FlowCtrlWithSBP

Flow Control enabled using only shared buffer pool FC state.

enumerator kNETC_FlowCtrlWithBPAndSBP

Flow Control enabled using both buffer pool and shared buffer pool FC state, only both 1 trigger the Flow Control ON

typedef enum _netc_tb_index netc_tb_index_t

Table index.

typedef enum _netc_tb_cmd netc_tb_cmd_t

Table management command operations.

typedef enum _netc_tb_access_mode netc_tb_access_mode_t

Table Access Method.

typedef enum _netc_cbd_version netc_cbd_version_t

NTMP version.

typedef enum _netc_cmd_error netc_cmd_error_t

Table command response error status.

typedef union _netc_cmd_bd netc_cmd_bd_t

The Switch/SI command BD data structure.

typedef struct _netc_cmd_bdr_config netc_cmd_bdr_config_t

Configuration for the Switch/SI command BD Ring Configuration.

typedef struct _netc_cmd_bdr netc_cmd_bdr_t

The Switch/SI command BD ring handle data structure.

typedef struct _netc_tb_common_header netc_tb_common_header_t

Table request data buffer common header.

typedef enum _netc_fm_vlan_ud_act netc_fm_vlan_ud_act_t

Frame Modification VLAN Update/Delete Action.

Note

Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame.

typedef enum _netc_fm_sqt_act netc_fm_sqt_act_t

Frame Modification Sequence Tag Action.

Note

Must be set to 000b for Ingress frame modification, otherwise misconfiguration error..

typedef enum _netc_fm_vlan_ar_act netc_fm_vlan_ar_act_t

Frame Modification VLAN Add/Replace Action.

Note

For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value.

typedef enum _netc_tb_eteid_access_mode netc_tb_eteid_access_mode_t

Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode.

Note

The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached

typedef enum _netc_tb_ipf_update_action netc_tb_ipf_update_action_t

Ingress Port Filter Table Update Actions.

typedef enum _netc_tb_ipf_attr_mask netc_tb_ipf_attr_mask_t

Ingress Port Filter frame attribute mask.

typedef enum _netc_tb_ipf_seq_tag netc_tb_ipf_seq_tag_t

Ingress Port Filter frame attribute Sequence Tag Code.

typedef enum _netc_tb_ipf_l4_header netc_tb_ipf_l4_header_t

Ingress Port Filter frame attribute L4 Header Code.

typedef struct _netc_tb_ipf_keye netc_tb_ipf_keye_t

Ingress Port Filter key element.

typedef enum _netc_tb_ipf_forward_action netc_tb_ipf_forward_action_t

Ingress port filter forwarding Action.

typedef enum _netc_tb_ipf_filter_action netc_tb_ipf_filter_action_t

Ingress port filter Filter Action.

typedef struct _netc_tb_ipf_cfge netc_tb_ipf_cfge_t

Ingress port filter config element.

typedef struct _netc_tb_ipf_stse netc_tb_ipf_stse_t

Ingress port filter statistic element.

typedef struct _netc_tb_ipf_req_data netc_tb_ipf_req_data_t

Ingress port filter table entry config.

typedef struct _netc_tb_ipf_rsp_data netc_tb_ipf_rsp_data_t

Ingress port filter table response data.

typedef struct _netc_tb_ipf_data netc_tb_ipf_data_t

Ingress Port filter table data buffer.

typedef struct _netc_tb_ipf_config netc_tb_ipf_config_t

Ingress Port filter entry config.

typedef enum _netc_tb_isi_key_type netc_tb_isi_key_type

Stream identification table key type.

typedef struct _netc_tb_isi_keye netc_tb_isi_keye_t

Stream identification table key element.

typedef struct _netc_tb_isi_cfge netc_tb_isi_cfge_t

Stream identification table config element.

typedef struct _netc_tb_isi_req_data netc_tb_isi_req_data_t

Stream identification table request data buffer.

typedef struct _netc_tb_isi_rsp_data netc_tb_isi_rsp_data_t

Stream identification table request response data buffer.

typedef struct _netc_tb_isi_data netc_tb_isi_data_t

Stream identification table data buffer.

typedef struct _netc_tb_isi_config netc_tb_isi_config_t

Stream identification table entry config.

typedef enum _netc_tb_is_isq_action netc_tb_is_isq_action_t

Ingress Stream table Ingress Sequence Action.

typedef enum _netc_tb_is_forward_action netc_tb_is_forward_action_t

Ingress Stream table forwarding Action.

typedef enum _netc_tb_is_ctd_mode netc_tb_is_ctd_mode_t

Ingress Stream table Cut-Through Disable mode.

typedef netc_tb_eteid_access_mode_t netc_tb_is_oeteid_mode_t

Ingress Stream table Override ET_EID mode.

typedef struct _netc_tb_is_cfge netc_tb_is_cfge_t

Ingress Stream table config element.

typedef struct _netc_tb_is_req_data netc_tb_is_req_data_t

Ingress Stream table request data buffer.

typedef struct _netc_tb_is_rsp_data netc_tb_is_rsp_data_t

Ingress Stream table request response data buffer.

typedef struct _netc_tb_is_data netc_tb_is_data_t

Ingress Stream table data buffer.

typedef struct _netc_tb_is_config netc_tb_is_config_t

Ingress Stream table entry config.

typedef struct _netc_tb_isf_keye netc_tb_isf_keye_t

Ingress Stream Filter table key element.

typedef struct _netc_tb_isf_cfge netc_tb_isf_cfge_t

Ingress Stream Filter table config element.

typedef struct _netc_tb_isf_req_data netc_tb_isf_req_data_t

Ingress Stream Filter table request data buffer.

typedef struct _netc_tb_isf_rsp_data netc_tb_isf_rsp_data_t

Ingress Stream Filter table request response data buffer.

typedef struct _netc_tb_isf_data netc_tb_isf_data_t

Ingress Stream Filter table data buffer.

typedef struct _netc_tb_isf_config netc_tb_isf_config_t

Ingress Stream Filter table entry config.

typedef enum _netc_tb_rp_update_action netc_tb_rp_update_action_t

Rate Policer Table Update Actions.

typedef netc_tc_sdu_type_t netc_tb_rp_sdu_type_t

Rate Policer Table Protocol/Service Data Unit Type.

typedef struct _netc_tb_rp_cfge netc_tb_rp_cfge_t

Rate Policer table config element.

typedef struct _netc_tb_rp_fee netc_tb_rp_fee_t

Rate Policer table Function Enable element.

typedef struct _netc_tb_rp_pse netc_tb_rp_pse_t

Rate Policer table Policer State element.

typedef struct _netc_tb_rp_stse netc_tb_rp_stse_t

Rate Policer table statistic element.

typedef struct _netc_tb_rp_req_data netc_tb_rp_req_data_t

Rate Policer table request data buffer.

typedef struct _netc_tb_rp_rsp_data netc_tb_rp_rsp_data_t

Rate Policer table request response data buffer.

typedef struct _netc_tb_rp_data netc_tb_rp_data_t

Rate Policer table data buffer.

typedef struct _netc_tb_rp_config netc_tb_rp_config_t

Rate Policer table entry config.

typedef struct _netc_tb_isc_stse netc_tb_isc_stse_t

Ingress Stream Count table statistic element.

typedef struct _netc_tb_isc_req_data netc_tb_isc_req_data_t

Ingress Stream Count table request data buffer.

typedef struct _netc_tb_isc_rsp_data netc_tb_isc_rsp_data_t

Ingress Stream Count table request response data buffer.

typedef struct _netc_tb_isc_data netc_tb_isc_data_t

Ingress Stream Count table data buffer.

typedef enum _netc_tb_sgi_update_action netc_tb_sgi_update_action_t

Stream Gate Instance table Update Actions.

typedef netc_tc_sdu_type_t netc_tb_sgi_sdu_type_t

Stream Gate Instance table Protocol/Service Data Unit Type.

typedef enum _netc_tb_sgi_state netc_tb_sgi_state_t

Stream Gate Instance State.

typedef struct _netc_tb_sgi_cfge netc_tb_sgi_cfge_t

Stream Gate Instance table config element.

typedef struct _netc_tb_sgi_acfge netc_tb_sgi_acfge_t

Stream Gate Instance table Admin Configuration element.

typedef struct _netc_tb_sgi_icfge netc_tb_sgi_icfge_t

Stream Gate Instance table Initial Configuration element.

typedef struct _netc_tb_sgi_sgise netc_tb_sgi_sgise_t

Stream Gate Instance table stream gate instance state element.

typedef struct _netc_tb_sgi_req_data netc_tb_sgi_req_data_t

Stream Gate Instance table request data buffer.

typedef struct _netc_tb_sgi_rsp_data netc_tb_sgi_rsp_data_t

Stream Gate Instance table request response data buffer.

typedef struct _netc_tb_sgi_data netc_tb_sgi_data_t

Stream Gate Instance table data buffer.

typedef struct _netc_tb_sgi_config netc_tb_sgi_config_t

Stream Gate Instance table entry config.

typedef struct _netc_sgcl_gate_entry netc_sgcl_gate_entry_t

Defines the Stream Gate Control entry structure.

typedef struct _netc_tb_sgcl_cfge netc_tb_sgcl_cfge_t

Stream Gate Control List table config element.

typedef struct _netc_tb_sgcl_sgclse netc_tb_sgcl_sgclse_t

Stream Gate Control List table Stream Gate Control List State element.

typedef struct _netc_tb_sgcl_req_data netc_tb_sgcl_req_data_t

Stream Gate Control List table request data buffer.

typedef struct _netc_tb_sgcl_rsp_data netc_tb_sgcl_rsp_data_t

Stream Gate Control List table request response data buffer.

typedef struct _netc_tb_sgcl_data netc_tb_sgcl_data_t

Stream Gate Control List table data buffer.

typedef struct _netc_tb_sgcl_gcl netc_tb_sgcl_gcl_t

Stream Gate Control List table entry gate control list structure.

typedef enum _netc_tb_fm_layer2_act netc_tb_fm_layer2_act_t

Frame Modification table Layer 2 Actions.

Note

This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.

typedef enum _netc_tb_fm_mac_header_act netc_tb_fm_mac_header_act_t

Frame Modification table Layer 2 Header MAC Actions.

Note

Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac.

typedef enum _netc_tb_fm_vlan_header_act netc_tb_fm_vlan_header_act_t

Frame Modification table Layer 2 VLAN Actions.

Note

For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef enum _netc_tb_fm_outer_vid_act netc_tb_fm_outer_vid_act_t

Frame Modification table Layer 2 outer VLAN VID Actions.

Note

For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef netc_fm_sqt_act_t netc_tb_fm_sqt_act_t

Frame Modification table Sequence Tag Action.

Note

For use kNETC_ReomveTag action, If R-TAG/draft 2.0 R-TAG/HSR tag not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef enum _netc_tb_fm_outer_tpid_act netc_tb_fm_outer_tpid_act_t

Frame Modification table Outer TPID action.

Note

For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef enum _netc_tb_fm_outer_pcp_act netc_tb_fm_outer_pcp_act_t

Frame Modification table Outer PCP action.

Note

For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef enum _netc_tb_fm_outer_dei_act netc_tb_fm_outer_dei_act_t

Frame Modification table Outer DEI action.

Note

For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register.

typedef enum _netc_tb_fm_payload_act netc_tb_fm_payload_act_t

Frame Modification table Payload Actions.

Note

This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements.

typedef struct _netc_tb_fm_cfge netc_tb_fm_cfge_t

Frame Modification table config element.

typedef struct _netc_tb_fm_req_data netc_tb_fm_req_data_t

Frame Modification table request data buffer.

typedef struct _netc_tb_fm_rsp_data netc_tb_fm_rsp_data_t

Frame Modification table request response data buffer.

typedef struct _netc_tb_fm_data netc_tb_fm_data_t

Frame Modification table data buffer.

typedef struct _netc_tb_fm_config netc_tb_fm_config_t

Frame Modification table entry config.

typedef struct _netc_tb_fmd_req_data netc_tb_fmd_req_data_t

Frame Modification Data table request data buffer.

typedef struct _netc_tb_fmd_rsp_data netc_tb_fmd_rsp_data_t

Frame Modification Data table request response data buffer.

typedef struct _netc_tb_fmd_data netc_tb_fmd_data_t

Frame Modification Data table data buffer.

typedef struct _netc_tb_fmd_update_config netc_tb_fmd_update_config_t

Frame Modification data table entry update config.

typedef struct _netc_tb_fmd_query_buffer netc_tb_fmd_query_buffer_t

Frame Modification data table entry query data buffer.

typedef struct _netc_tb_vf_keye netc_tb_vf_keye_t

Vlan Filter table key element.

typedef struct _netc_tb_vf_cfge netc_tb_vf_cfge_t

Vlan Filter table config element.

typedef struct _netc_tb_vf_search_criteria netc_tb_vf_search_criteria_t

Vlan Filter table search criteria format.

typedef struct _netc_tb_vf_req_data netc_tb_vf_req_data_t

Vlan Filter table request data buffer.

typedef struct _netc_tb_vf_rsp_data netc_tb_vf_rsp_data_t

Vlan Filter table request response data buffer.

typedef struct _netc_tb_vf_data netc_tb_vf_data_t

Vlan Filter table data buffer.

typedef struct _netc_tb_vf_config netc_tb_vf_config_t

Vlan Filter table entry config.

typedef enum _netc_tb_fdb_update_action netc_tb_fdb_update_action_t

FDB table Update Actions.

typedef netc_tb_eteid_access_mode_t netc_tb_fdb_oeteid_mode_t

FDB table entry defined the egress packet processing actions (will cover the actions which specified in the Egress Treatment table )

typedef enum _netc_tb_fdb_ctd_mode netc_tb_fdb_ctd_mode_t

FDB table Cut-Through Disable mode.

typedef struct _netc_tb_fdb_keye netc_tb_fdb_keye_t

typedef struct _netc_tb_fdb_cfge netc_tb_fdb_cfge_t

FDB table configuration element.

typedef struct _netc_tb_fdb_acte netc_tb_fdb_acte_t

FDB table Activity element.

typedef enum _netc_tb_fdb_sc_keye_mc netc_tb_fdb_sc_keye_mc_t

FDB table search criteria Key Element Match Criteria.

typedef enum _netc_tb_fdb_sc_cfge_mc netc_tb_fdb_sc_cfge_mc_t

FDB table search criteria Configuration Element Match Criteria.

typedef enum _netc_tb_fdb_sc_acte_mc netc_tb_fdb_sc_acte_mc_t

FDB table search criteria Activity Element Match Criteria.

typedef struct _netc_tb_fdb_search_criteria netc_tb_fdb_search_criteria_t

FDB table search criteria format.

typedef struct _netc_tb_fdb_req_data netc_tb_fdb_req_data_t

FDB table request data buffer.

typedef struct _netc_tb_fdb_rsp_data netc_tb_fdb_rsp_data_t

FDB table request response data buffer.

typedef struct _netc_tb_fdb_data netc_tb_fdb_data_t

FDB table data buffer.

typedef struct _netc_tb_fdb_config netc_tb_fdb_config_t

FDB table entry config.

typedef enum _netc_tb_l2mcf_key_type netc_tb_l2mcf_key_type_t

L2 IPV4 Multicast Filter table key type.

typedef struct _netc_tb_l2mcf_keye netc_tb_l2mcf_keye_t

L2 IPV4 Multicast Filter table key element.

typedef enum _etc_tb_l2mcf_sc_keye_mc etc_tb_l2mcf_sc_keye_mc_t

L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria.

typedef enum _etc_tb_l2mcf_sc_cfge_mc etc_tb_l2mcf_sc_cfge_mc_t

L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria.

typedef enum _etc_tb_l2mcf_sc_acte_mc etc_tb_l2mcf_sc_acte_mc_t

FDB table search criteria Activity Element Match Criteria.

typedef netc_tb_fdb_cfge_t netc_tb_l2mcf_cfge_t

L2 IPV4 Multicast Filter table config element.

typedef netc_tb_fdb_acte_t netc_tb_l2mcf_acte_t

L2 IPV4 Multicast Filter table activity lement.

typedef struct _etc_tb_l2mcf_search_criteria netc_tb_l2mcf_search_criteria_t

L2 IPV4 Multicast Filter table search criteria format.

typedef struct _netc_tb_l2mcf_req_data netc_tb_l2mcf_req_data_t

L2 IPV4 Multicast Filter table request data buffer.

typedef struct _netc_tb_l2mcf_rsp_data netc_tb_l2mcf_rsp_data_t

L2 IPV4 Multicast Filter table request response data buffer.

typedef struct _netc_tb_l2mcf_data netc_tb_l2mcf_data_t

L2 IPV4 Multicast Filter table data buffer.

typedef struct _netc_tb_l2mcf_config netc_tb_l2mcf_config_t

L2 IPV4 Multicast Filter table entry config.

typedef enum _netc_tb_iseqg_sqtag netc_tb_iseqg_sqtag_t

Sequence Tag Type.

typedef struct _netc_tb_iseqg_cfge netc_tb_iseqg_cfge_t

Ingress Sequence Generation table config element.

typedef struct _netc_tb_iseqg_sgse netc_tb_iseqg_sgse_t

Ingress Sequence Generation table Sequence generation state element.

typedef struct _netc_tb_iseqg_req_data netc_tb_iseqg_req_data_t

Ingress Sequence Generation table request data buffer.

typedef struct _netc_tb_iseqg_rsp_data netc_tb_iseqg_rsp_data_t

Ingress Sequence Generation table request response data buffer.

typedef struct _netc_tb_iseqg_data netc_tb_iseqg_data_t

Ingress Sequence Generation table data buffer.

typedef struct _netc_tb_iseqg_config netc_tb_iseqg_config_t

Ingress Sequence Generation table entry config.

typedef enum _netc_tb_iseqg_update_action netc_tb_iseqg_update_action_t

Ingress Sequence Generation Table Update Actions.

typedef enum _netc_tb_eseqr_sqtag netc_tb_eseqr_sqtag_t

Egress Sequence Recovery table Sequence Tag Type.

typedef struct _netc_tb_eseqr_cfge netc_tb_eseqr_cfge_t

Egress Sequence Recovery table config element.

typedef struct _netc_tb_eseqr_stse netc_tb_eseqr_stse_t

Egress Sequence Recovery table statistic element.

typedef struct _netc_tb_eseqr_srse netc_tb_eseqr_srse_t

Egress Sequence Recovery table sequence recovery state element.

typedef struct _netc_tb_eseqr_req_data netc_tb_eseqr_req_data_t

Egress Sequence Recovery table request data buffer.

typedef struct _netc_tb_eseqr_rsp_data netc_tb_eseqr_rsp_data_t

Egress Sequence Recovery table request response data buffer.

typedef struct _netc_tb_eseqr_data netc_tb_eseqr_data_t

Egress Sequence Recovery table data buffer.

typedef struct _netc_tb_eseqr_config netc_tb_eseqr_config_t

Egress Sequence Recovery table entry config.

typedef enum _netc_tb_tgs_entry_id netc_tb_tgs_entry_id_t

Time Gate Scheduling table entry ID for switch and ENETC.

typedef enum _netc_tb_tgs_gate_type netc_tb_tgs_gate_type_t

Administrative gate operation type.

typedef struct _netc_tgs_gate_entry netc_tgs_gate_entry_t

Defines the Time Gate Scheduling gate control entry structure.

typedef struct _netc_tb_tgs_cfge netc_tb_tgs_cfge_t

Time Gate Scheduling table config element.

typedef struct _netc_tb_tgs_olse netc_tb_tgs_olse_t

Time Gate Scheduling table statistic element.

typedef struct _netc_tb_tgs_req_data netc_tb_tgs_req_data_t

Time Gate Scheduling table request data buffer.

typedef struct _netc_tb_tgs_rsp_data netc_tb_tgs_rsp_data_t

Time Gate Scheduling table request response data buffer.

typedef struct _netc_tb_tgs_data netc_tb_tgs_data_t

Time Gate Scheduling table data buffer, set with max size.

typedef struct _netc_tb_tgs_gcl netc_tb_tgs_gcl_t

Time Gate Scheduling table entry gate control list structure.

typedef enum _netc_tb_et_efm_mode netc_tb_et_efm_mode_t

Egress Frame Modification entry mode.

typedef enum _netc_tb_et_esq_act netc_tb_et_esq_act_t

Egress Sequence Actions.

typedef enum _netc_tb_et_ec_act netc_tb_et_ec_act_t

Egress Counter Action.

typedef struct _netc_tb_et_cfge netc_tb_et_cfge_t

Egress Treatment table config element.

typedef struct _netc_tb_et_req_data netc_tb_et_req_data_t

Egress Treatment table request data buffer.

typedef struct _netc_tb_et_rsp_data netc_tb_et_rsp_data_t

Egress Treatment table request response data buffer.

typedef struct _netc_tb_et_data netc_tb_et_data_t

Egress Treatment table data buffer.

typedef struct _netc_tb_et_config netc_tb_et_config_t

Egress Treatment table entry config.

typedef enum _netc_tb_etmcq_update_action netc_tb_etmcq_update_action_t

ETM Class Queue table Update Actions.

typedef struct _netc_tb_etmcq_cfge netc_tb_etmcq_cfge_t

ETM Class Queue table config element.

typedef struct _netc_tb_etmcq_stse netc_tb_etmcq_stse_t

ETM Class Queue table statistic element.

typedef struct _netc_tb_etmcq_req_data netc_tb_etmcq_req_data_t

ETM Class Queue table request data buffer.

typedef struct _netc_tb_etmcq_rsp_data netc_tb_etmcq_rsp_data_t

ETM Class Queue table request response data buffer.

typedef struct _netc_tb_etmcq_data netc_tb_etmcq_data_t

ETM Class Queue table data buffer.

typedef struct _netc_tb_etmcq_config netc_tb_etmcq_config_t

ETM Class Queue table entry config.

typedef enum _netc_tb_etmcs_entry_id netc_tb_etmcs_entry_id_t

ETM Class Scheduler table entry ID.

typedef enum _netc_tb_etmcs_ca_assg netc_tb_etmcs_ca_assg_t

ETM Class Scheduler table Class queue assignment to scheduler inputs mode.

typedef struct _netc_tb_etmcs_cfge netc_tb_etmcs_cfge_t

ETM Class Scheduler table config element.

typedef struct _netc_tb_etmcs_req_data netc_tb_etmcs_req_data_t

ETM Class Scheduler table request data buffer.

typedef struct _netc_tb_etmcs_rsp_data netc_tb_etmcs_rsp_data_t

ETM Class Scheduler table request response data buffer.

typedef struct _netc_tb_etmcs_data netc_tb_etmcs_data_t

ETM Class Scheduler table data buffer.

typedef struct _netc_tb_etmcs_config netc_tb_etmcs_config_t

ETM Class Scheduler table entry config.

typedef struct _netc_tb_etmcg_cfge netc_tb_etmcg_cfge_t

ETM Congestion Group table config element.

typedef struct _netc_tb_etmcg_stse netc_tb_etmcg_stse_t

ETM Congestion Group table statistic element.

typedef struct _netc_tb_etmcg_req_data netc_tb_etmcg_req_data_t

ETM Congestion Group table request data buffer.

typedef struct _netc_tb_etmcg_rsp_data netc_tb_etmcg_rsp_data_t

ETM Congestion Group table request response data buffer.

typedef struct _netc_tb_etmcg_data netc_tb_etmcg_data_t

ETM Congestion Group table data buffer.

typedef struct _netc_tb_etmcg_config netc_tb_etmcg_config_t

ETM Congestion Group table entry config.

typedef struct _netc_tb_ec_stse netc_tb_ec_stse_t

Egress Count table statistic element.

typedef struct _netc_tb_ec_req_data netc_tb_ec_req_data_t

Egress Count table request data buffer.

typedef struct _netc_tb_ec_rsp_data netc_tb_ec_rsp_data_t

Egress Count table request response data buffer.

typedef struct _netc_tb_ec_data netc_tb_ec_data_t

Egress Count table data buffer.

typedef enum _netc_tb_bp_fc_cfg netc_tb_bp_fc_cfg_t

Buffer Pool Flow Control (FC) Configuration.

typedef struct _netc_tb_bp_cfge netc_tb_bp_cfge_t

Buffer Pool table config element.

typedef struct _netc_tb_bp_bpse netc_tb_bp_bpse_t

Buffer Pool table State Element Data.

typedef struct _netc_tb_bp_req_data netc_tb_bp_req_data_t

Buffer Pool table request data buffer.

typedef struct _netc_tb_bp_rsp_data netc_tb_bp_rsp_data_t

Buffer Pool table request response data buffer.

typedef struct _netc_tb_bp_data netc_tb_bp_data_t

Buffer Pool table data buffer.

typedef struct _netc_tb_bp_config netc_tb_bp_config_t

Buffer Pool table entry config.

typedef struct _netc_tb_sbp_cfge netc_tb_sbp_cfge_t

Shared Buffer Pool table config element.

typedef struct _netc_tb_sbp_sbpse netc_tb_sbp_sbpse_t

Shared Buffer Pool table State Element Data.

typedef struct _netc_tb_sbp_req_data netc_tb_sbp_req_data_t

Shared Buffer Pool table request data buffer.

typedef struct _netc_tb_sbp_rsp_data netc_tb_sbp_rsp_data_t

Shared Buffer Pool table request response data buffer.

typedef struct _netc_tb_sbp_data netc_tb_sbp_data_t

Shared Buffer Pool table data buffer.

typedef struct _netc_tb_sbp_config netc_tb_sbp_config_t

Shared Buffer Pool table entry config.

typedef union _netc_tb_data_buffer netc_tb_data_buffer_t

Table common data buffer.

typedef struct _netc_cbdr_hw netc_cbdr_hw_t

Register group for SI/Switch command bd ring.

typedef struct _netc_cbdr_handle netc_cbdr_handle_t

Handle for common part of EP/Switch NTMP.

status_t NETC_CmdBDRInit(netc_cbdr_hw_t *base, const netc_cmd_bdr_config_t *config)

Initialize the command BD ring.

Parameters:

• base –

• config –

Returns:

kStatus_Success

Returns:

kStatus_Fail

status_t NETC_CmdBDRDeinit(netc_cbdr_hw_t *base)

Deinitialize the command BD ring.

Parameters:

• base –

Returns:

kStatus_Success

status_t NETC_CmdBDSendCommand(netc_cbdr_hw_t *base, netc_cmd_bdr_t *cbdr, netc_cmd_bd_t *cbd, netc_cbd_version_t version)

Send the Command Buffer Descriptor to operate on a NTMP table.

Parameters:

• base –

• cbdr –

• cbd –

• version –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddIPFTableEntry(netc_cbdr_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)

Add entry into the ingress Port Filter Table.

Parameters:

• handle –

• config –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_UpdateIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)

Update entry in the ingress Port Filter Table.

Parameters:

• handle –

• entryID –

• cfg –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_config_t *config)

Query entry in the ingress Port Filter Table.

Parameters:

• handle –

• entryID –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in the ingress Port Filter Table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_ResetIPFMatchCounter(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset the counter of an ingress port filter Table entry.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetIPFMatchedCount(netc_cbdr_handle_t *handle, uint32_t entryID, uint64_t *count)

Get the matched count of an ingress port filter Table entry.

Parameters:

• handle –

• entryID –

• count –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddISITableEntry(netc_cbdr_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)

Add entry into Ingress Stream Identification table.

Parameters:

• handle –

• config –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream identification table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isi_config_t *config)

Query Ingress Stream Identification table.

Parameters:

• handle –

• entryID –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp)

Query Ingress Stream Identification table with key.

Parameters:

• handle –

• keye –

• rsp –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddOrUpdateISTableEntry(netc_cbdr_handle_t *handle, netc_tb_is_config_t *config, bool isAdd)

Add or update entry in Ingress Stream table.

Parameters:

• handle –

• config –

• isAdd –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_is_config_t *config)

Query Ingress Stream table.

Parameters:

• handle –

• entryID –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)

Add entry into ingress stream filter table.

Parameters:

• handle –

• config –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_UpdateISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)

Update entry into ingress stream filter table.

Parameters:

• handle –

• entryID –

• cfg –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream filter table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_keye_t *keye, netc_tb_isf_rsp_data_t *rsp)

Query entry from the Ingress stream filter table.

Parameters:

• handle –

• keye –

• rsp –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddISCTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Add entry in ingress stream count table.

Parameters:

• handle –

• entryID –

Returns:

status_t

status_t NETC_GetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)

Get ingress stream count statistic.

Parameters:

• handle –

• entryID –

• statistic –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_ResetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset the count of the ingress stream count.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddOrUpdateSGITableEntry(netc_cbdr_handle_t *handle, netc_tb_sgi_config_t *config, bool isAdd)

Add or update entry in stream gate instance table.

Parameters:

• handle –

• config –

• isAdd –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_ResetIRXOEXSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset IRX and OEX flags in stream gate instance entry.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry in the stream gate instance table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *statis)

Get statistic of specified stream gate instance table entry.

Parameters:

• handle –

• entryID –

• statis –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config)

Query entry from the stream gate instance table.

Parameters:

• handle –

• entryID –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddSGCLTableEntry(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *config)

Add entry into Stream Gate Control List Table.

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelSGCLTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry of Stream Gate Control List Table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetSGCLGateList(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)

Get Stream Gate Control List Table entry gate control list.

Parameters:

• handle –

• gcl –

• length –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetSGCLState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)

Get state (ref count) for Stream Gate Control List table entry.

Parameters:

• handle –

• entryID –

• state –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_QueryRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp)

Query entry from the Rate Policer table.

Parameters:

• handle –

• entryID –

• rsp –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_AddOrUpdateRPTableEntry(netc_cbdr_handle_t *handle, netc_tb_rp_config_t *config, netc_tb_cmd_t cmd)

Add or update entry in Rate Policer table.

Parameters:

• handle –

• config –

• cmd –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_DelRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry in the Rate Policer table.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetRPStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)

Get statistic of specified Rate Policer table entry.

Parameters:

• handle –

• entryID –

• statis –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_ResetMRRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset mark red parameter of specified Rate Policer table entry.

Parameters:

• handle –

• entryID –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_ConfigTGSAdminList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *config)

Config the QBV (Time Gate Scheduling)

Parameters:

• handle –

• config –

Returns:

status_t

Returns:

See netc_cmd_error_t

status_t NETC_GetTGSOperationList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)

Get time gate table operation list.

Parameters:

• handle –

• gcl –

• length –

Returns:

status_t

Returns:

See netc_cmd_error_t

NETC_FD_EID_ENCODE_OPTION_0(entryId)

Frame Modification Entry ID encode options.

Note

sqta should be netc_fm_sqt_act_t type, vuda should be netc_fm_vlan_ud_act_t type and vara should be netc_fm_vlan_ar_act_t type.

NETC_FD_EID_ENCODE_OPTION_1(sqta, vuda)

NETC_FD_EID_ENCODE_OPTION_2(vara, vid)

NETC_ISI_VLAN_FRAME_KEY(valid, pcp, vid)

2 Bytes VLAN field which may added to the frame Key

NETC_TB_SGCL_MAX_ENTRY

Stream Gate Control List Table maximum gate control list length.

NETC_TB_FMD_UPDATE_CONFIG_LENGTH(x)

TFrame Modification Data table update config Data Buffer length, x is the number of update data bytes.

NETC_TB_TGS_MAX_ENTRY

Time Gate Scheduling Table maximum gate control list length (TGSTCAPR[MAX_GCL_LEN])

NETC_TB_ETM_CQ_ENTRY_ID(portID, cqID)

ETM Class Queue table entry ID macro, cqID is represents the Class Queue ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4.

NETC_TB_ETM_CG_ENTRY_ID(portID, cgID)

ETM Congestion Group table entry ID macro, cgID is represents the Congestion Group ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4.

NETC_TB_BP_THRESH(mant, exp)

Buffer pool and shared buffer pool threshold macro, the threshold = MANT*2^EXP, uint is internal memory words (avergae of 20 bytes each)

union _netc_cmd_bd

#include <fsl_netc.h>

The Switch/SI command BD data structure.

Public Members

struct _netc_cmd_bd req

struct _netc_cmd_bd resp

struct _netc_cmd_bd generic

struct _netc_cmd_bdr_config

#include <fsl_netc.h>

Configuration for the Switch/SI command BD Ring Configuration.

Public Members

netc_cmd_bd_t *bdBase

BDR base address which shall be 128 bytes aligned

uint16_t bdLength

Size of BD ring which shall be multiple of 8 BD

bool enCompInt

Enable/Disable command BD completion interrupt

struct _netc_cmd_bdr

#include <fsl_netc.h>

The Switch/SI command BD ring handle data structure.

Public Members

netc_cmd_bd_t *bdBase

BDR base address which shall be 128 bytes aligned

uint16_t bdLength

Size of BD ring

uint16_t producerIndex

Current index for execution.

uint16_t cleanIndex

Current index for cleaning.

bool bdrEnable

Current command BD ring is enable or not.

struct _netc_tb_common_header

#include <fsl_netc.h>

Table request data buffer common header.

Public Members

uint32_t updateActions

Update Actions

uint32_t queryActions

Query Actions

struct _netc_tb_ipf_keye

#include <fsl_netc.h>

Ingress Port Filter key element.

Public Members

uint16_t precedence

Precedence value of an entry

struct _netc_tb_ipf_keye frameAttr

Frame Attribute flags

uint16_t frameAttrMask

Frame attribute mask, set with OR of netc_tb_ipf_attr_mask_t

uint16_t dscp

Differentiated Services Code Point

uint16_t dscpMask

Differentiated Services Code Point Mask

uint16_t srcPort

Source Port ID

uint16_t srcPortMask

Source Port ID Mask

uint16_t outerVlanTCI

Outer VLAN Tag Control Information

uint16_t outerVlanTCIMask

Outer VLAN Tag Control Information Mask

uint8_t dmac[6]

Destination MAC Address

uint8_t dmacMask[6]

Destination MAC Address Mask

uint8_t smac[6]

Source MAC Address

uint8_t smacMask[6]

Source MAC Address Mask

uint16_t innerVlanTCI

Inner VLAN Tag Control Information

uint16_t innerVlanTCIMask

Inner VLAN Tag Control Information Mask

uint16_t etherType

2-byte EtherType

uint16_t etherTypeMask

EtherType Mask

uint8_t IPProtocol

IP Protocol

uint8_t IPProtocolMask

IP Protocol Mask

uint8_t srcIPAddr[16]

IP Source Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address

uint8_t srcIPAddrMask[16]

IP Source Address Mask

uint16_t l4SrcPort

L4 Source Port

uint16_t l4SrcPortMask

L4 Source Port Mask

uint8_t destIPAddr[16]

IP Destination Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address

uint8_t destIPAddrMask[16]

IP Destination Address Mask

uint16_t l4DestPort

L4 Destination Port

uint16_t l4DestPortMask

L4 Destination Port Mask

struct _netc_tb_ipf_cfge

#include <fsl_netc.h>

Ingress port filter config element.

Public Members

uint32_t ipv

Internal Priority Value

uint32_t oipv

Overwrite IPV

uint32_t dr

Drop Resilience

uint32_t odr

Overwrite DR

netc_tb_ipf_forward_action_t fltfa

Filter Forwarding action.

uint32_t imire

Ingress Mirroring Enable

uint32_t wolte

Wake-onLAN trigger enable

netc_tb_ipf_filter_action_t flta

FIlter Action.

uint32_t rpr

Relative Precedent Resolution

uint32_t ctd

Cut through disable.

netc_host_reason_t hr

Host Reason metadata when frame is redirected/copied to the switch management port

uint32_t timecape

Timestam capture enable

uint32_t rrt

Report Receive Timestamp

uint32_t fltaTgt

Target for selected switch forwarding action or filter action

struct _netc_tb_ipf_stse

#include <fsl_netc.h>

Ingress port filter statistic element.

Public Members

uint32_t matchCount[2]

A count of how many times this entry has been matched.

struct _netc_tb_ipf_req_data

#include <fsl_netc.h>

Ingress port filter table entry config.

struct _netc_tb_ipf_rsp_data

#include <fsl_netc.h>

Ingress port filter table response data.

Public Members

uint32_t entryID

Present only for commands which perform a query

netc_tb_ipf_keye_t keye

Present only for commands which perform a query

netc_tb_ipf_stse_t stse

Present only for commands which perform a query

netc_tb_ipf_cfge_t cfge

Present only for commands which perform a query

struct _netc_tb_ipf_data

#include <fsl_netc.h>

Ingress Port filter table data buffer.

struct _netc_tb_ipf_config

#include <fsl_netc.h>

Ingress Port filter entry config.

struct _netc_tb_isi_keye

#include <fsl_netc.h>

Stream identification table key element.

Public Members

netc_tb_isi_key_type keyType

Define the key type used for the current isi entry

uint8_t srcPortID

Source Port ID, used when kc portp filed is 1. Only for SWITCH

uint8_t spm

Source Port Masquerading, used when kc spm filed is 1. Only for SWITCH

uint8_t framekey[16]

Frame portion of the key.

struct _netc_tb_isi_cfge

#include <fsl_netc.h>

Stream identification table config element.

Public Members

uint32_t iSEID

Ingress stream entry ID, 0xFFFFFFFF means NULL

struct _netc_tb_isi_req_data

#include <fsl_netc.h>

Stream identification table request data buffer.

struct _netc_tb_isi_rsp_data

#include <fsl_netc.h>

Stream identification table request response data buffer.

Public Members

uint32_t entryID

Only present for query command

netc_tb_isi_keye_t keye

Only present for query command

netc_tb_isi_cfge_t cfge

Only present for query command

struct _netc_tb_isi_data

#include <fsl_netc.h>

Stream identification table data buffer.

struct _netc_tb_isi_config

#include <fsl_netc.h>

Stream identification table entry config.

struct _netc_tb_is_cfge

#include <fsl_netc.h>

Ingress Stream table config element.

Public Members

uint32_t sfe

Stream Filtering Enable

uint32_t ipv

Internal Priority Value, active when opiv is set to 1

uint32_t oipv

Override internal priority value

uint32_t dr

Drop Resilience, active when odr is set to 1

uint32_t odr

Overwrite DR

uint32_t imire

Ingress Mirroring Enable, not applicable to ENETC

uint32_t timecape

Timestamp Capture Enable, not applicable to ENETC

uint32_t sppd

Source Port Pruning Disable, not applicable to ENETC

netc_tb_is_isq_action_t isqa

Ingress Sequence Action, not applicable to ENETC

uint32_t orp

Override Rate Policer ID

uint32_t osgi

Override stream gate instance entry id (default is NULL)

netc_host_reason_t hr

Host Reason when frame is redirected (fa = 01b) to the switch management port or copied to the switch management port (fa = 100b or 101b), value specified has to be a software defined Host Reason (8-15).

netc_tb_is_forward_action_t fa

Forwad Option

netc_tc_sdu_type_t sduType

Service Data Unit Type to user for MSDU

uint32_t msdu

Maximum Service Data Unit

uint32_t ifmeLenChange

Ingress Frame Modification Entry Frame Length Change, specified in unit of bytes using a 2’s complement notation

uint32_t eport

Egress Port which need do egress packet processing, active when oeteid is set to 1, not applicable to ENETC

netc_tb_is_oeteid_mode_t oETEID

Override ET_EID (Egress Treatment table entry, which specified egress packet processing actions)

netc_tb_is_ctd_mode_t ctd

Cut-Through Disable mode, valid if fa = 010b ~ 101b

uint32_t isqEID

Ingress Sequence Generation Entry ID, Valid when isqa is set to 1. 0xFFFF_FFFF is NULL. Not applicable to ENETC

uint32_t rpEID

Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL

uint32_t sgiEID

Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL

uint32_t ifmEID

Ingress Frame Modification Entry ID. 0xFFFF_FFFF is NULL

uint32_t etEID

Base Egress Treatment Entry ID for primary Egress Treatment group, Valid alid if fa = 010b ~ 101b. 0xFFFF_FFFF is NULL. Not applicable to ENETC

uint32_t iscEID

Ingress Stream counter Index. 0xFFFF_FFFF is NULL.

uint32_t ePortBitmap

Egress Port bitmap, identifies the ports to which the frame is to be forwarding or ET applicability port bitmap when oETEID = 10b. Not applicable to ENETC

uint32_t siMap

Station Interface Map, only valid for ENETC function when fa field is set to 10b

struct _netc_tb_is_req_data

#include <fsl_netc.h>

Ingress Stream table request data buffer.

Public Members

netc_tb_is_cfge_t cfge

Only perform for update or add command

struct _netc_tb_is_rsp_data

#include <fsl_netc.h>

Ingress Stream table request response data buffer.

Public Members

uint32_t entryID

Only perform for query command

netc_tb_is_cfge_t cfge

Only perform for query command

struct _netc_tb_is_data

#include <fsl_netc.h>

Ingress Stream table data buffer.

struct _netc_tb_is_config

#include <fsl_netc.h>

Ingress Stream table entry config.

struct _netc_tb_isf_keye

#include <fsl_netc.h>

Ingress Stream Filter table key element.

Public Members

uint32_t isEID

Ingress Stream Entry ID

uint8_t pcp

Priority Code Point, Outer VLAN TAG PCP of the received frame

struct _netc_tb_isf_cfge

#include <fsl_netc.h>

Ingress Stream Filter table config element.

Public Members

uint32_t ipv

Internal Priority Value, active when opiv is set to 1

uint32_t oipv

Override internal priority value

uint32_t dr

Drop Resilience, active when odr is set to 1

uint32_t odr

Overwrite DR

uint32_t imire

Ingress Mirroring Enable, not applicable to ENETC

uint32_t timecape

Timestamp Capture Enable, not applicable to ENETC

uint32_t osgi

Override stream gate instance entry id

uint32_t ctd

Cut-Through Disable, will disable cut-through for all destined ports when set 1, not applicable to ENETC

uint32_t orp

Override Rate Policer (instance) ID

netc_tc_sdu_type_t sduType

Service Data Unit Type to user for MSDU

uint32_t msdu

Maximum Service Data Unit

uint32_t rpEID

Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL

uint32_t sgiEID

Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL

uint32_t iscEID

Ingress Stream counter Index. 0xFFFF_FFFF is NULL.

struct _netc_tb_isf_req_data

#include <fsl_netc.h>

Ingress Stream Filter table request data buffer.

Public Members

netc_tb_isf_cfge_t cfge

Only perform for update or add command

struct _netc_tb_isf_rsp_data

#include <fsl_netc.h>

Ingress Stream Filter table request response data buffer.

Public Members

uint32_t entryID

Only perform for query command

netc_tb_isf_keye_t keye

Only perform for query command

netc_tb_isf_cfge_t cfge

Only perform for query command

struct _netc_tb_isf_data

#include <fsl_netc.h>

Ingress Stream Filter table data buffer.

struct _netc_tb_isf_config

#include <fsl_netc.h>

Ingress Stream Filter table entry config.

struct _netc_tb_rp_cfge

#include <fsl_netc.h>

Rate Policer table config element.

Public Members

uint32_t cir

Committed information Rate

uint32_t cbs

Commited Burst Size

uint32_t eir

Excess information Rate

uint32_t ebs

Excess Burst Size

uint32_t mren

Mark All Frames Red Enable, Not valid when ndor=1

uint32_t doy

Drop on Yellow enable

uint32_t cm

Color mode, 0b = Color blind, 1b = Color aware

uint32_t cf

Coupling flag, enables coupling the Committed (C) bucket and Excess (E) bucket

uint32_t ndor

No drop on red

netc_tb_rp_sdu_type_t sduType

Service Data Unit Type

uint32_t __pad0__

Reserved

struct _netc_tb_rp_fee

#include <fsl_netc.h>

Rate Policer table Function Enable element.

Public Members

uint8_t fen

Function Enable

uint8_t __pad0__

Reserved

struct _netc_tb_rp_pse

#include <fsl_netc.h>

Rate Policer table Policer State element.

Public Members

uint8_t mr

Mark Red Flag

uint8_t res0

Reserved

struct _netc_tb_rp_stse

#include <fsl_netc.h>

Rate Policer table statistic element.

Public Members

uint32_t byteCount[2]

Number of bytes received by the rate policer instance

uint32_t dropFrames[2]

Number of frames dropped by the rate policer instance

uint32_t dr0GrnFrames[2]

Number of frames marked green with DR=0 by the rate policer instance

uint32_t dr1GrnFrames[2]

Number of frames marked green with DR=1 by the rate policer instance

uint32_t dr2GrnFrames[2]

Number of frames marked yellow with DR=2 by the rate policer instance

uint32_t remarkYlwFrames[2]

Number of frames re-marked from green to yellow by the rate policer instance

uint32_t dr3RedFrames[2]

Number of frames marked red with DR=3 by the rate policer instance

uint32_t remarkRedFrames[2]

Number of frames re-marked from green or yellow to red by the rate policer instance

uint32_t lts

Last timestamp

uint32_t bci

Committed token bucket contents, integer portion (31 bits)

uint32_t bcs

Committed token bucket sign bit (1 bit)

uint32_t bcf

Committed token bucket contents, fractional portion (31 bits)

uint32_t bei

Excess token bucket contents, integer portion (32 bits)

uint32_t bef

Excess token bucket contents, fractional portion (31 bits)

uint32_t bes

Committed token bucket sign bit

struct _netc_tb_rp_req_data

#include <fsl_netc.h>

Rate Policer table request data buffer.

struct _netc_tb_rp_rsp_data

#include <fsl_netc.h>

Rate Policer table request response data buffer.

Public Members

uint32_t entryID

Present only for commands which perform a query

netc_tb_rp_stse_t stse

Present only for commands which perform a query

struct _netc_tb_rp_data

#include <fsl_netc.h>

Rate Policer table data buffer.

struct _netc_tb_rp_config

#include <fsl_netc.h>

Rate Policer table entry config.

struct _netc_tb_isc_stse

#include <fsl_netc.h>

Ingress Stream Count table statistic element.

Public Members

uint32_t rxCount

Receive Count

uint32_t msduDropCount

MSDU Drop Count

uint32_t policerDropCount

Policer Drop Count

uint32_t sgDropCount

Stream Gating Drop Count

struct _netc_tb_isc_req_data

#include <fsl_netc.h>

Ingress Stream Count table request data buffer.

struct _netc_tb_isc_rsp_data

#include <fsl_netc.h>

Ingress Stream Count table request response data buffer.

struct _netc_tb_isc_data

#include <fsl_netc.h>

Ingress Stream Count table data buffer.

struct _netc_tb_sgi_cfge

#include <fsl_netc.h>

Stream Gate Instance table config element.

Public Members

uint8_t oexen

Octets Exceeded (Gate Closed Due To Octets Exceeded function) Enable

uint8_t irxen

Invalid Receive (Gate Closed Due To Invalid Rx) Enable

netc_tb_sgi_sdu_type_t sduType

The type of PDU/SDU for Interval Octets Maximum check for Gate Entry

struct _netc_tb_sgi_acfge

#include <fsl_netc.h>

Stream Gate Instance table Admin Configuration element.

Public Members

uint32_t adminSgclEID

Administrative Stream Gate Control List Entry ID, 0xFFFFFFFF is NULL

uint32_t adminBaseTime[2]

Admin Base Time

uint32_t adminCycleTimeExt

Admin Cycle Time Extension

struct _netc_tb_sgi_icfge

#include <fsl_netc.h>

Stream Gate Instance table Initial Configuration element.

Public Members

uint8_t ipv

Internal Priority Value (IPV), Valid if oipv is 1

uint8_t oipv

Override frame IPV, otherwise the IPV value is determined by the stream gate control list entry

uint8_t gst

Specifies Gate State before the administrative stream gate control list takes affect, 0b = Closed; 1b = Open

uint8_t ctd

Specifies Cut Through disable status before the administrative stream gate control list takes affect , Not applicable to ENETC function

struct _netc_tb_sgi_sgise

#include <fsl_netc.h>

Stream Gate Instance table stream gate instance state element.

Public Members

uint32_t operSgclEID

Operational Stream Gate Control List Entry ID

uint32_t configChangeTime[2]

Configuration Change Time

uint32_t operBaseTime[2]

Operational Base Time

uint32_t operCycleTimeExt

Oper Cycle Time Extension

uint32_t oex

Octets Exceeded Flag

uint32_t irx

Invalid Receive Flag

netc_tb_sgi_state_t state

Current Gate Instance State

struct _netc_tb_sgi_req_data

#include <fsl_netc.h>

Stream Gate Instance table request data buffer.

struct _netc_tb_sgi_rsp_data

#include <fsl_netc.h>

Stream Gate Instance table request response data buffer.

struct _netc_tb_sgi_data

#include <fsl_netc.h>

Stream Gate Instance table data buffer.

struct _netc_tb_sgi_config

#include <fsl_netc.h>

Stream Gate Instance table entry config.

struct _netc_sgcl_gate_entry

#include <fsl_netc.h>

Defines the Stream Gate Control entry structure.

Public Members

uint32_t timeInterval

Time Interval for Gate Entry

uint32_t iom

Interval Octets Maximum for Gate Entry, specifies the maximum bytes (octets) allowed to pass (open), valid if iomen = 1

uint32_t ipv

Internal Priority Value for Gate Entry

uint32_t oipv

Override Internal Priority Value for Gate Entry

uint32_t ctd

Cut Through Disable for Gate Entry

uint32_t iomen

Interval Octet Maximum Enabled for Gate Entry, 0b = Don’track count, 1b = Track count

uint32_t gtst

Gate State for Gate Entry, 0b = Closed; 1b = Open

struct _netc_tb_sgcl_cfge

#include <fsl_netc.h>

Stream Gate Control List table config element.

Public Members

uint32_t cycleTime

Cycle Time

uint8_t listLength

List Length

uint16_t extOipv

Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value

uint16_t extIpv

List Extension Internal Priority Value, valid if extOipv = 1

uint16_t extCtd

Extension Cut Through Disabled, 0b = No action, 1b = Disabled

uint16_t extGtst

Extension Gate State, 0b = closed, 1b = Open

struct _netc_tb_sgcl_sgclse

#include <fsl_netc.h>

Stream Gate Control List table Stream Gate Control List State element.

Public Members

uint8_t refCount

Reference Count, 1 indicates that the gate control list is an administrative or an operational gate control list in a stream gate instance

struct _netc_tb_sgcl_req_data

#include <fsl_netc.h>

Stream Gate Control List table request data buffer.

struct _netc_tb_sgcl_rsp_data

#include <fsl_netc.h>

Stream Gate Control List table request response data buffer.

struct _netc_tb_sgcl_data

#include <fsl_netc.h>

Stream Gate Control List table data buffer.

struct _netc_tb_sgcl_gcl

#include <fsl_netc.h>

Stream Gate Control List table entry gate control list structure.

Public Members

uint16_t extOipv

Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value

uint16_t extIpv

List Extension Internal Priority Value, valid if extOipv = 1

uint16_t extCtd

Extension Cut Through Disabled, 0b = No action, 1b = Disabled

uint16_t extGtst

Extension Gate State, 0b = closed, 1b = Open

uint32_t cycleTime

Cycle Time

uint32_t numEntries

Control List entry numbers

netc_sgcl_gate_entry_t *gcList

Pointer to stream gate control list array

struct _netc_tb_fm_cfge

#include <fsl_netc.h>

Frame Modification table config element.

Public Members

netc_tb_fm_layer2_act_t l2Act

Layer 2 Actions

netc_tb_fm_mac_header_act_t macHdrAct

Layer 2 Header MAC Actions

netc_tb_fm_vlan_header_act_t vlanHdrAct

Layer 2 VLAN Actions

netc_tb_fm_outer_vid_act_t outerVidAct

Outer VID Actions

netc_tb_fm_sqt_act_t sqtAct

Sequence Tag Action, Not applicable for ingress frame modifications

uint16_t smacPort

Source MAC Address Register Port, valid if macHdrAct=010b,011b,100b

uint8_t dmac[6]

Destination MAC Address, valid if macHdrAct = 011b,101b

uint32_t outerVlanID

Outer VLAN VID, valid if outerVidAct = 01b

uint32_t outerVlanPcp

Outer VLAN PCP, valid if outerPcpAct = 01b

uint32_t outerVlanDei

Outer VLAN DEI, valid if outerDeiAct = 01b

netc_tb_fm_outer_tpid_act_t outerTpidAct

Outer TPID action

netc_tb_fm_outer_pcp_act_t outerPcpAct

Outer PCP action

netc_tb_fm_outer_dei_act_t outerDeiAct

Outer DEI action

netc_tb_fm_payload_act_t pldAct

Payload Actions, Not applicable for ingress frame modifications

uint8_t pldOffset

Payload Offset, valid if outerPldAct = 010b

uint16_t fmdBytes

Frame Modification Bytes, valid if outerPldAct = 001b,010b or l2Act = 1b

uint32_t fmdEID

Frame Modification Data Entry ID, valid if outerPldAct = 001b,010b or l2Act = 1b. 0xFFFF is null pointer

struct _netc_tb_fm_req_data

#include <fsl_netc.h>

Frame Modification table request data buffer.

struct _netc_tb_fm_rsp_data

#include <fsl_netc.h>

Frame Modification table request response data buffer.

struct _netc_tb_fm_data

#include <fsl_netc.h>

Frame Modification table data buffer.

struct _netc_tb_fm_config

#include <fsl_netc.h>

Frame Modification table entry config.

struct _netc_tb_fmd_req_data

#include <fsl_netc.h>

Frame Modification Data table request data buffer.

Public Members

uint8_t cfge[]

Configuration Element Data size is variable

struct _netc_tb_fmd_rsp_data

#include <fsl_netc.h>

Frame Modification Data table request response data buffer.

Public Members

uint8_t cfge[]

Configuration Element Data size is variable

struct _netc_tb_fmd_data

#include <fsl_netc.h>

Frame Modification Data table data buffer.

struct _netc_tb_fmd_update_config

#include <fsl_netc.h>

Frame Modification data table entry update config.

Public Members

uint32_t res

Hold for request->commonHeader

uint8_t cfge[]

Configuration Element Data size is variable

struct _netc_tb_fmd_query_buffer

#include <fsl_netc.h>

Frame Modification data table entry query data buffer.

Public Members

uint32_t entryID

EntryID of the queried entry

uint8_t cfge[]

Configuration Element Data size is variable

struct _netc_tb_vf_keye

#include <fsl_netc.h>

Vlan Filter table key element.

struct _netc_tb_vf_cfge

#include <fsl_netc.h>

Vlan Filter table config element.

Public Members

uint32_t portMembership

Port Membership Bitmap

uint32_t stgID

Spanning Tree Group Member ID

uint32_t fid

Filtering ID

uint32_t mlo

MAC Learning Options

uint32_t mfo

MAC Forwarding Options

uint32_t ipmfe

IP Multicast Filtering Enable

uint32_t ipmfle

IP Multicast Flooding Enable

uint32_t etaPortBitmap

Egress Treatment Applicability Port Bitmap for the secondary Egress Treatment group

uint32_t baseETEID

Base Egress Treatment Entry ID for the secondary Egress Treatment group

struct _netc_tb_vf_search_criteria

#include <fsl_netc.h>

Vlan Filter table search criteria format.

Public Members

uint32_t resumeEntryId

Resume Entry ID, when starting a search, pass the NULL Entry ID.

struct _netc_tb_vf_req_data

#include <fsl_netc.h>

Vlan Filter table request data buffer.

Public Members

netc_tb_vf_cfge_t cfge

Present only for update or add commands

struct _netc_tb_vf_rsp_data

#include <fsl_netc.h>

Vlan Filter table request response data buffer.

Public Members

uint32_t status

Present only for query command with search access method

uint32_t entryID

Present only for query command

netc_tb_vf_keye_t keye

Present only for query command

netc_tb_vf_cfge_t cfge

Present only for query command

struct _netc_tb_vf_data

#include <fsl_netc.h>

Vlan Filter table data buffer.

struct _netc_tb_vf_config

#include <fsl_netc.h>

Vlan Filter table entry config.

struct _netc_tb_fdb_keye

#include <fsl_netc.h>

Public Members

uint8_t macAddr[6]

Destination MAC address of the frame for MAC forwarding lookups and the source MAC address of the frame for MAC learning lookups

uint32_t fid

Filtering ID, is obtained from an ingress lookup into the VLAN Filter table

struct _netc_tb_fdb_cfge

#include <fsl_netc.h>

FDB table configuration element.

Public Members

uint32_t portBitmap

Forwarding destination Port Bitmap and ET applicability port bitmap when oETEID = 10b

netc_tb_fdb_oeteid_mode_t oETEID

Override ET_EID option

uint32_t ePort

Egress Ports, active when oETEid = 01b or ctd = 01b

uint32_t iMirE

Ingress Mirroring Enable

netc_tb_fdb_ctd_mode_t ctd

Cut-Through Disable

uint32_t dynamic

Static or Dynamic Entry, 0b = Static entry, 1b = Dynamic entry

uint32_t timeCapE

Timestamp Capture Enable when set

uint32_t etEID

Base egress treatment table entry id for primary Egress Treatment group, is valid if the oETEID field is set to value other than kNETC_FDBNoEPP. 0xFFFFFFFF is NULL.

struct _netc_tb_fdb_acte

#include <fsl_netc.h>

FDB table Activity element.

Public Members

uint8_t actCnt

Activity Counter

uint8_t actFlag

Activity Flag

struct _netc_tb_fdb_search_criteria

#include <fsl_netc.h>

FDB table search criteria format.

Public Members

uint32_t resumeEntryId

Resume Entry ID, pass the NULL Entry ID when starting a search

netc_tb_fdb_keye_t keye

Key Element data which used to match against the table entries

netc_tb_fdb_cfge_t cfge

Configuration Element data which used to match against the table entries

struct _netc_tb_fdb_req_data

#include <fsl_netc.h>

FDB table request data buffer.

Public Members

netc_tb_common_header_t commonHeader

Define update actions (use netc_tb_fdb_update_action_t) and query actions

netc_tb_fdb_cfge_t cfge

Present only for commands which perform an update or add

struct _netc_tb_fdb_rsp_data

#include <fsl_netc.h>

FDB table request response data buffer.

Public Members

uint32_t status

RESUME_ENTRY_ID, valid only in responses for commands which use the Search Access Method

uint32_t entryID

Present only for query command

netc_tb_fdb_keye_t keye

Present only for query command

netc_tb_fdb_cfge_t cfge

Present only for query command

netc_tb_fdb_acte_t acte

Present only for query command

struct _netc_tb_fdb_data

#include <fsl_netc.h>

FDB table data buffer.

struct _netc_tb_fdb_config

#include <fsl_netc.h>

FDB table entry config.

struct _netc_tb_l2mcf_keye

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table key element.

Public Members

netc_tb_l2mcf_key_type_t keyType

Key Type

uint32_t fid

Filtering ID

uint32_t ipv4DestAddr

IPv4 Destination Address

uint32_t ipv4SrcAddr

IPv4 Source Address

struct _etc_tb_l2mcf_search_criteria

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table search criteria format.

Public Members

uint32_t resumeEntryId

Resume Entry ID, pass the NULL Entry ID when starting a search

netc_tb_l2mcf_keye_t keye

Key Element data which used to match against the table entries

netc_tb_l2mcf_cfge_t cfge

Configuration Element data which used to match against the table entries

struct _netc_tb_l2mcf_req_data

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table request data buffer.

struct _netc_tb_l2mcf_rsp_data

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table request response data buffer.

struct _netc_tb_l2mcf_data

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table data buffer.

struct _netc_tb_l2mcf_config

#include <fsl_netc.h>

L2 IPV4 Multicast Filter table entry config.

struct _netc_tb_iseqg_cfge

#include <fsl_netc.h>

Ingress Sequence Generation table config element.

Public Members

netc_tb_iseqg_sqtag_t sqTag

Sequence Tag Type.

uint8_t __pad0__

Reserved.

struct _netc_tb_iseqg_sgse

#include <fsl_netc.h>

Ingress Sequence Generation table Sequence generation state element.

Public Members

uint16_t sqgNum

Sequence Generation Number

struct _netc_tb_iseqg_req_data

#include <fsl_netc.h>

Ingress Sequence Generation table request data buffer.

struct _netc_tb_iseqg_rsp_data

#include <fsl_netc.h>

Ingress Sequence Generation table request response data buffer.

struct _netc_tb_iseqg_data

#include <fsl_netc.h>

Ingress Sequence Generation table data buffer.

struct _netc_tb_iseqg_config

#include <fsl_netc.h>

Ingress Sequence Generation table entry config.

struct _netc_tb_eseqr_cfge

#include <fsl_netc.h>

Egress Sequence Recovery table config element.

Public Members

netc_tb_eseqr_sqtag_t sqTag

Sequence Tag, specify the expected sequence tag type in the frame

uint32_t sqrTnsq

Sequence Recovery Take No Sequence

uint32_t sqrAlg

Sequence Recovery Algorithm, 0b = Vector algorithm, 1b = Match algorithm

uint32_t sqrType

Sequence Recovery Function type, 0b = Sequence recovery function, 1b = Individual recovery function

uint32_t sqrHl

Sequence Recovery History Length, valid if sqrAlg = 0b

uint32_t sqrFwl

Sequence Recovery Future Window Length, valid if sqrAlg = 0b

uint32_t sqrTp

Sequence Timeout Period, the unit is 1.048576 milliseconds

struct _netc_tb_eseqr_stse

#include <fsl_netc.h>

Egress Sequence Recovery table statistic element.

Public Members

uint32_t inOrderPackets[2]

In Order Packets

uint32_t outOfOrderPackets[2]

Out of Order Packets

uint32_t roguePackets[2]

Rogue Packets

uint32_t duplicatePackets[2]

Duplicate Packets

uint32_t lostPackets[2]

Lost Packets

uint32_t taglessPackets[2]

Tag-Less Packets

uint32_t esqrResetCounts

Sequence Recovery Resets

struct _netc_tb_eseqr_srse

#include <fsl_netc.h>

Egress Sequence Recovery table sequence recovery state element.

Public Members

uint32_t sqrNum

Sequence Recovery Number

uint32_t takeAny

Take Any

uint32_t lce

Lost Count Enable

uint32_t sqrTs

Sequence Recovery Timestamp

uint32_t sqrHistory[4]

Recovery History bit vector, each bit corresponding to sequence numbers, bit 1 means a packet with that sequence number has been previously received

struct _netc_tb_eseqr_req_data

#include <fsl_netc.h>

Egress Sequence Recovery table request data buffer.

struct _netc_tb_eseqr_rsp_data

#include <fsl_netc.h>

Egress Sequence Recovery table request response data buffer.

struct _netc_tb_eseqr_data

#include <fsl_netc.h>

Egress Sequence Recovery table data buffer.

struct _netc_tb_eseqr_config

#include <fsl_netc.h>

Egress Sequence Recovery table entry config.

struct _netc_tgs_gate_entry

#include <fsl_netc.h>

Defines the Time Gate Scheduling gate control entry structure.

Public Members

uint32_t interval

Entry Time Interval

struct _netc_tb_tgs_cfge

#include <fsl_netc.h>

Time Gate Scheduling table config element.

Public Members

uint64_t adminBaseTime

Administrative Base Time

uint32_t adminCycleTime

Administrative Cycle Time

uint32_t adminCycleTimeExt

Administrative Cycle Time Extension

uint32_t adminControlListLength

Administrative Control List Length

netc_tgs_gate_entry_t adminGcl[]

Administrative Gate control list

struct _netc_tb_tgs_olse

#include <fsl_netc.h>

Time Gate Scheduling table statistic element.

Public Members

uint64_t configChangeTime

The time at which this operational gate control list became active

uint64_t configChangeError

Count of error configuration changes

uint64_t operBaseTime

Operational Base Time

uint32_t operCycleTime

Operational Cycle Time

uint32_t operCycleTimeExt

Operational Cycle Time Extension

uint32_t operControlListLength

Operational Control List Length

netc_tgs_gate_entry_t operGcl[]

Operational Gate control list

struct _netc_tb_tgs_req_data

#include <fsl_netc.h>

Time Gate Scheduling table request data buffer.

Public Members

netc_tb_tgs_cfge_t cfge

Present only for commands which perform a update

struct _netc_tb_tgs_rsp_data

#include <fsl_netc.h>

Time Gate Scheduling table request response data buffer.

Public Members

uint32_t entryID

Present only for commands which perform a query

netc_tb_tgs_cfge_t cfge

Present only for commands which perform a query

netc_tb_tgs_olse_t olse

Present only for commands which perform a query

struct _netc_tb_tgs_data

#include <fsl_netc.h>

Time Gate Scheduling table data buffer, set with max size.

struct _netc_tb_tgs_gcl

#include <fsl_netc.h>

Time Gate Scheduling table entry gate control list structure.

Public Members

uint64_t baseTime

Base Time

uint32_t cycleTime

Cycle Time

uint32_t extTime

Cycle Time Extension

uint32_t numEntries

Control List entry numbers

netc_tgs_gate_entry_t *gcList

Pointer to time gate control list array

struct _netc_tb_et_cfge

#include <fsl_netc.h>

Egress Treatment table config element.

Public Members

netc_tb_et_efm_mode_t efmMode

Egress Frame Modification mode

netc_tb_et_esq_act_t esqa

Egress Sequence Actions

netc_tb_et_ec_act_t eca

Egress Counter Action

uint8_t __pad1__

Reserve for data align

uint8_t efmLenChange

Egress Frame Modification Length Change, specified in units of bytes using a 2’s complement notation

uint16_t efmDataLen

Egress Frame Modification Data Length

uint32_t efmEID

Egress Frame Modification Entry Id

uint32_t ecEID

Egress Count Table Entry ID

uint32_t esqaTgtEID

Egress Sequence Actions Target Entry ID, active when esqa = 10b

struct _netc_tb_et_req_data

#include <fsl_netc.h>

Egress Treatment table request data buffer.

struct _netc_tb_et_rsp_data

#include <fsl_netc.h>

Egress Treatment table request response data buffer.

struct _netc_tb_et_data

#include <fsl_netc.h>

Egress Treatment table data buffer.

struct _netc_tb_et_config

#include <fsl_netc.h>

Egress Treatment table entry config.

struct _netc_tb_etmcq_cfge

#include <fsl_netc.h>

ETM Class Queue table config element.

Public Members

netc_hw_etm_class_queue_idx_t cq2cgMap

Class Queue to Congestion Group Mapping

struct _netc_tb_etmcq_stse

#include <fsl_netc.h>

ETM Class Queue table statistic element.

Public Members

uint32_t rejByteCnt[2]

Reject Byte Count

uint32_t rejFrameCnt[2]

Reject Frame Count

uint32_t deqByteCnt[2]

Dequeue Byte Count

uint32_t deqFrameCnt[2]

Dequeue Frame Count

uint32_t dropByteCnt[2]

Dropped Frames, Memory Lost

uint32_t dropFrameCnt[2]

Dropped Frames, Memory Recovered

uint32_t frmCnt

Frame Count

struct _netc_tb_etmcq_req_data

#include <fsl_netc.h>

ETM Class Queue table request data buffer.

struct _netc_tb_etmcq_rsp_data

#include <fsl_netc.h>

ETM Class Queue table request response data buffer.

struct _netc_tb_etmcq_data

#include <fsl_netc.h>

ETM Class Queue table data buffer.

struct _netc_tb_etmcq_config

#include <fsl_netc.h>

ETM Class Queue table entry config.

Public Members

uint32_t entryID

Need use NETC_TB_ETM_CQ_ENTRY_ID macro to create entry ID

struct _netc_tb_etmcs_cfge

#include <fsl_netc.h>

ETM Class Scheduler table config element.

Public Members

netc_tb_etmcs_ca_assg_t cqAssg

Class Queue Assignment, input 0 to 7 are weighted fair whereby input 8 to 15 are strict priority

uint32_t oal

Overead accounting length

struct _netc_tb_etmcs_cfge wbfsWeight[8]

Weight for scheduler input 0 ~ 7, effective weight is: (2^x)/(1-(y/64))

struct _netc_tb_etmcs_req_data

#include <fsl_netc.h>

ETM Class Scheduler table request data buffer.

Public Members

netc_tb_etmcs_entry_id_t entryID

One class scheduler entry per port

struct _netc_tb_etmcs_rsp_data

#include <fsl_netc.h>

ETM Class Scheduler table request response data buffer.

struct _netc_tb_etmcs_data<