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Data Structures
union	FXPQ3115_OUT_P_LSB_t

union	FXPQ3115_OUT_T_LSB_t

union	FXPQ3115_DR_STATUS_t

union	FXPQ3115_OUT_P_DELTA_LSB_t

union	FXPQ3115_OUT_T_DELTA_LSB_t

union	FXPQ3115_F_STATUS_t

union	FXPQ3115_F_SETUP_t

union	FXPQ3115_SYSMOD_t

union	FXPQ3115_INT_SOURCE_t

union	FXPQ3115_PT_DATA_CFG_t

union	FXPQ3115_P_MIN_LSB_t

union	FXPQ3115_T_MIN_LSB_t

union	FXPQ3115_P_MAX_LSB_t

union	FXPQ3115_T_MAX_LSB_t

union	FXPQ3115_CTRL_REG1_t

union	FXPQ3115_CTRL_REG2_t

union	FXPQ3115_CTRL_REG3_t

union	FXPQ3115_CTRL_REG4_t

union	FXPQ3115_CTRL_REG5_t

Macros
#define	FXPQ3115_I2C_ADDRESS (0x60) /* FXPQ3115BV I2C Slave Address. */

#define	FXPQ3115_WHOAMI_VALUE (0xC5) /* FXPQ3115BV WHO_AM_I Value. */

#define	FXPQ3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02)

#define	FXPQ3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1)

#define	FXPQ3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04)

#define	FXPQ3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2)

#define	FXPQ3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08)

#define	FXPQ3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3)

#define	FXPQ3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20)

#define	FXPQ3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5)

#define	FXPQ3115_DR_STATUS_POW_MASK ((uint8_t) 0x40)

#define	FXPQ3115_DR_STATUS_POW_SHIFT ((uint8_t) 6)

#define	FXPQ3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80)

#define	FXPQ3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7)

#define	FXPQ3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition */

#define	FXPQ3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */

#define	FXPQ3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */

#define	FXPQ3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */

#define	FXPQ3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */

#define	FXPQ3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */

#define	FXPQ3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)

#define	FXPQ3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)

#define	FXPQ3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40)

#define	FXPQ3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6)

#define	FXPQ3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)

#define	FXPQ3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)

#define	FXPQ3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */

#define	FXPQ3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */

#define	FXPQ3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */

#define	FXPQ3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */

#define	FXPQ3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)

#define	FXPQ3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)

#define	FXPQ3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)

#define	FXPQ3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)

#define	FXPQ3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */

#define	FXPQ3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when */

#define	FXPQ3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */

#define	FXPQ3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01)

#define	FXPQ3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)

#define	FXPQ3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */

#define	FXPQ3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */

#define	FXPQ3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01)

#define	FXPQ3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0)

#define	FXPQ3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02)

#define	FXPQ3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1)

#define	FXPQ3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04)

#define	FXPQ3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2)

#define	FXPQ3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08)

#define	FXPQ3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3)

#define	FXPQ3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10)

#define	FXPQ3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4)

#define	FXPQ3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20)

#define	FXPQ3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5)

#define	FXPQ3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)

#define	FXPQ3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)

#define	FXPQ3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80)

#define	FXPQ3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7)

#define	FXPQ3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01)

#define	FXPQ3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0)

#define	FXPQ3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02)

#define	FXPQ3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1)

#define	FXPQ3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04)

#define	FXPQ3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2)

#define	FXPQ3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

#define	FXPQ3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */

#define	FXPQ3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

#define	FXPQ3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */

#define	FXPQ3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

#define	FXPQ3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */

#define	FXPQ3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0)

#define	FXPQ3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4)

#define	FXPQ3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01)

#define	FXPQ3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0)

#define	FXPQ3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02)

#define	FXPQ3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1)

#define	FXPQ3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04)

#define	FXPQ3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2)

#define	FXPQ3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38)

#define	FXPQ3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3)

#define	FXPQ3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40)

#define	FXPQ3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6)

#define	FXPQ3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80)

#define	FXPQ3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7)

#define	FXPQ3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */

#define	FXPQ3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */

#define	FXPQ3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */

#define	FXPQ3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */

#define	FXPQ3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */

#define	FXPQ3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */

#define	FXPQ3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */

#define	FXPQ3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */

#define	FXPQ3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples */

#define	FXPQ3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */

#define	FXPQ3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */

#define	FXPQ3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */

#define	FXPQ3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */

#define	FXPQ3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F)

#define	FXPQ3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0)

#define	FXPQ3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10)

#define	FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4)

#define	FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20)

#define	FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5)

#define	FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */

#define	FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */

#define	FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */

#define	FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */

#define	FXPQ3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01)

#define	FXPQ3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0)

#define	FXPQ3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02)

#define	FXPQ3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1)

#define	FXPQ3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10)

#define	FXPQ3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4)

#define	FXPQ3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20)

#define	FXPQ3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5)

#define	FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */

#define	FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */

#define	FXPQ3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */

#define	FXPQ3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */

#define	FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */

#define	FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */

#define	FXPQ3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */

#define	FXPQ3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */

#define	FXPQ3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01)

#define	FXPQ3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0)

#define	FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02)

#define	FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1)

#define	FXPQ3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04)

#define	FXPQ3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2)

#define	FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08)

#define	FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3)

#define	FXPQ3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10)

#define	FXPQ3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4)

#define	FXPQ3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20)

#define	FXPQ3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5)

#define	FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)

#define	FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)

#define	FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80)

#define	FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7)

#define	FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */

#define	FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */

#define	FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20)

#define	FXPQ3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5)

#define	FXPQ3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)

#define	FXPQ3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)

#define	FXPQ3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80)

#define	FXPQ3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7)

#define	FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

#define	FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */

Typedefs
typedef uint8_t	FXPQ3115_STATUS_t

typedef uint8_t	FXPQ3115_OUT_P_MSB_t

typedef uint8_t	FXPQ3115_OUT_P_CSB_t

typedef uint8_t	FXPQ3115_OUT_T_MSB_t

typedef uint8_t	FXPQ3115_OUT_P_DELTA_MSB_t

typedef uint8_t	FXPQ3115_OUT_P_DELTA_CSB_t

typedef uint8_t	FXPQ3115_OUT_T_DELTA_MSB_t

typedef uint8_t	FXPQ3115_WHO_AM_I_t

typedef uint8_t	FXPQ3115_F_DATA_t

typedef uint8_t	FXPQ3115_TIME_DLY_t

typedef uint8_t	FXPQ3115_BAR_IN_MSB_t

typedef uint8_t	FXPQ3115_BAR_IN_LSB_t

typedef uint8_t	FXPQ3115_P_TGT_MSB_t

typedef uint8_t	FXPQ3115_P_TGT_LSB_t

typedef uint8_t	FXPQ3115_T_TGT_t

typedef uint8_t	FXPQ3115_P_WND_MSB_t

typedef uint8_t	FXPQ3115_P_WND_LSB_t

typedef uint8_t	FXPQ3115_T_WND_t

typedef uint8_t	FXPQ3115_P_MIN_MSB_t

typedef uint8_t	FXPQ3115_P_MIN_CSB_t

typedef uint8_t	FXPQ3115_T_MIN_MSB_t

typedef uint8_t	FXPQ3115_P_MAX_MSB_t

typedef uint8_t	FXPQ3115_P_MAX_CSB_t

typedef uint8_t	FXPQ3115_T_MAX_MSB_t

typedef uint8_t	FXPQ3115_OFF_P_t

typedef uint8_t	FXPQ3115_OFF_T_t

typedef uint8_t	FXPQ3115_OFF_H_t

Enumerations
enum	{ FXPQ3115_STATUS = 0x00, FXPQ3115_OUT_P_MSB = 0x01, FXPQ3115_OUT_P_CSB = 0x02, FXPQ3115_OUT_P_LSB = 0x03, FXPQ3115_OUT_T_MSB = 0x04, FXPQ3115_OUT_T_LSB = 0x05, FXPQ3115_DR_STATUS = 0x06, FXPQ3115_OUT_P_DELTA_MSB = 0x07, FXPQ3115_OUT_P_DELTA_CSB = 0x08, FXPQ3115_OUT_P_DELTA_LSB = 0x09, FXPQ3115_OUT_T_DELTA_MSB = 0x0A, FXPQ3115_OUT_T_DELTA_LSB = 0x0B, FXPQ3115_WHO_AM_I = 0x0C, FXPQ3115_F_STATUS = 0x0D, FXPQ3115_F_DATA = 0x0E, FXPQ3115_F_SETUP = 0x0F, FXPQ3115_TIME_DLY = 0x10, FXPQ3115_SYSMOD = 0x11, FXPQ3115_INT_SOURCE = 0x12, FXPQ3115_PT_DATA_CFG = 0x13, FXPQ3115_BAR_IN_MSB = 0x14, FXPQ3115_BAR_IN_LSB = 0x15, FXPQ3115_P_TGT_MSB = 0x16, FXPQ3115_P_TGT_LSB = 0x17, FXPQ3115_T_TGT = 0x18, FXPQ3115_P_WND_MSB = 0x19, FXPQ3115_P_WND_LSB = 0x1A, FXPQ3115_T_WND = 0x1B, FXPQ3115_P_MIN_MSB = 0x1C, FXPQ3115_P_MIN_CSB = 0x1D, FXPQ3115_P_MIN_LSB = 0x1E, FXPQ3115_T_MIN_MSB = 0x1F, FXPQ3115_T_MIN_LSB = 0x20, FXPQ3115_P_MAX_MSB = 0x21, FXPQ3115_P_MAX_CSB = 0x22, FXPQ3115_P_MAX_LSB = 0x23, FXPQ3115_T_MAX_MSB = 0x24, FXPQ3115_T_MAX_LSB = 0x25, FXPQ3115_CTRL_REG1 = 0x26, FXPQ3115_CTRL_REG2 = 0x27, FXPQ3115_CTRL_REG3 = 0x28, FXPQ3115_CTRL_REG4 = 0x29, FXPQ3115_CTRL_REG5 = 0x2A, FXPQ3115_OFF_P = 0x2B, FXPQ3115_OFF_T = 0x2C, FXPQ3115_OFF_H = 0x2D }

Macro Definition Documentation

◆ FXPQ3115_CTRL_REG1_ALT_ALT

#define FXPQ3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */

Definition at line 891 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_ALT_BAR

#define FXPQ3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */

Definition at line 892 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_ALT_MASK

#define FXPQ3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80)

Definition at line 861 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_ALT_SHIFT

#define FXPQ3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7)

Definition at line 862 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_MASK

#define FXPQ3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38)

Definition at line 855 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_1

#define FXPQ3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */

Definition at line 874 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_128

#define FXPQ3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples */

Definition at line 887 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_16

#define FXPQ3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */

Definition at line 881 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_2

#define FXPQ3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 */

Definition at line 875 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_32

#define FXPQ3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */

Definition at line 883 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_4

#define FXPQ3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 */

Definition at line 877 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_64

#define FXPQ3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */

Definition at line 885 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_OSR_8

#define FXPQ3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 */

Definition at line 879 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OS_SHIFT

#define FXPQ3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3)

Definition at line 856 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OST_MASK

#define FXPQ3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02)

Definition at line 849 of file fxpq3115.h.

Referenced by main().

◆ FXPQ3115_CTRL_REG1_OST_RESET

#define FXPQ3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */

Definition at line 870 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OST_SET

#define FXPQ3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */

Definition at line 871 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_OST_SHIFT

#define FXPQ3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1)

Definition at line 850 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RAW_DIS

#define FXPQ3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */

Definition at line 889 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RAW_EN

#define FXPQ3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */

Definition at line 890 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RAW_MASK

#define FXPQ3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40)

Definition at line 858 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RAW_SHIFT

#define FXPQ3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6)

Definition at line 859 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RST_DIS

#define FXPQ3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */

Definition at line 872 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_RST_EN

#define FXPQ3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */

Definition at line 873 of file fxpq3115.h.

Referenced by FXPQ3115_I2C_DeInit().

◆ FXPQ3115_CTRL_REG1_RST_MASK

#define FXPQ3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04)

Definition at line 852 of file fxpq3115.h.

Referenced by FXPQ3115_I2C_DeInit().

◆ FXPQ3115_CTRL_REG1_RST_SHIFT

#define FXPQ3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2)

Definition at line 853 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_SBYB_ACTIVE

#define FXPQ3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */

Definition at line 869 of file fxpq3115.h.

Referenced by FXPQ3115_I2C_Configure().

◆ FXPQ3115_CTRL_REG1_SBYB_MASK

#define FXPQ3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01)

Definition at line 846 of file fxpq3115.h.

Referenced by FXPQ3115_I2C_Configure().

◆ FXPQ3115_CTRL_REG1_SBYB_SHIFT

#define FXPQ3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0)

Definition at line 847 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG1_SBYB_STANDBY

#define FXPQ3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */

Definition at line 868 of file fxpq3115.h.

Referenced by FXPQ3115_I2C_Configure().

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_MASK

#define FXPQ3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10)

Definition at line 922 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT

#define FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4)

Definition at line 923 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT

#define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */

Definition at line 934 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT

#define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */

Definition at line 932 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL

#define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */

Definition at line 936 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK

#define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20)

Definition at line 925 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL

#define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */

Definition at line 937 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT

#define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5)

Definition at line 926 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_ST_MASK

#define FXPQ3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F)

Definition at line 919 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG2_ST_SHIFT

#define FXPQ3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0)

Definition at line 920 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL1_HIGH

#define FXPQ3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */

Definition at line 993 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL1_LOW

#define FXPQ3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */

Definition at line 992 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL1_MASK

#define FXPQ3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20)

Definition at line 979 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL1_SHIFT

#define FXPQ3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5)

Definition at line 980 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL2_HIGH

#define FXPQ3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */

Definition at line 989 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL2_LOW

#define FXPQ3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */

Definition at line 988 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL2_MASK

#define FXPQ3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02)

Definition at line 973 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_IPOL2_SHIFT

#define FXPQ3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1)

Definition at line 974 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP

#define FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */

Definition at line 990 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD1_MASK

#define FXPQ3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10)

Definition at line 976 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN

#define FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */

Definition at line 991 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD1_SHIFT

#define FXPQ3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4)

Definition at line 977 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP

#define FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */

Definition at line 986 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD2_MASK

#define FXPQ3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01)

Definition at line 970 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN

#define FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */

Definition at line 987 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG3_PP_OD2_SHIFT

#define FXPQ3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0)

Definition at line 971 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */

Definition at line 1072 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */

Definition at line 1073 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80)

Definition at line 1051 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7)

Definition at line 1052 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */

Definition at line 1070 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */

Definition at line 1071 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)

Definition at line 1048 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)

Definition at line 1049 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */

Definition at line 1060 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */

Definition at line 1061 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02)

Definition at line 1033 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1)

Definition at line 1034 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */

Definition at line 1064 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */

Definition at line 1065 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08)

Definition at line 1039 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3)

Definition at line 1040 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */

Definition at line 1068 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */

Definition at line 1069 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20)

Definition at line 1045 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5)

Definition at line 1046 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */

Definition at line 1058 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */

Definition at line 1059 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TCHG_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01)

Definition at line 1030 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TCHG_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0)

Definition at line 1031 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TTH_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */

Definition at line 1062 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TTH_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */

Definition at line 1063 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TTH_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04)

Definition at line 1036 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TTH_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2)

Definition at line 1037 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TW_INTDISABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */

Definition at line 1066 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TW_INTENABLED

#define FXPQ3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */

Definition at line 1067 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TW_MASK

#define FXPQ3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10)

Definition at line 1042 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG4_INT_EN_TW_SHIFT

#define FXPQ3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4)

Definition at line 1043 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */

Definition at line 1153 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1152 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_DRDY_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80)

Definition at line 1131 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_DRDY_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7)

Definition at line 1132 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */

Definition at line 1151 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1150 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_FIFO_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)

Definition at line 1128 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_FIFO_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)

Definition at line 1129 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */

Definition at line 1141 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1140 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PCHG_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02)

Definition at line 1113 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PCHG_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1)

Definition at line 1114 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */

Definition at line 1145 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1144 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PTH_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08)

Definition at line 1119 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PTH_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3)

Definition at line 1120 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PW_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */

Definition at line 1149 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PW_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1148 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PW_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20)

Definition at line 1125 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_PW_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5)

Definition at line 1126 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */

Definition at line 1139 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1138 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TCHG_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01)

Definition at line 1110 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TCHG_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0)

Definition at line 1111 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */

Definition at line 1143 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1142 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TTH_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04)

Definition at line 1116 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TTH_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2)

Definition at line 1117 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TW_INT1

#define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */

Definition at line 1147 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TW_INT2

#define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */

Definition at line 1146 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TW_MASK

#define FXPQ3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10)

Definition at line 1122 of file fxpq3115.h.

◆ FXPQ3115_CTRL_REG5_INT_CFG_TW_SHIFT

#define FXPQ3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4)

Definition at line 1123 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PDR_DRDY

#define FXPQ3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */

Definition at line 214 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PDR_MASK

#define FXPQ3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04)

Definition at line 192 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PDR_SHIFT

#define FXPQ3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2)

Definition at line 193 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_POW_MASK

#define FXPQ3115_DR_STATUS_POW_MASK ((uint8_t) 0x40)

Definition at line 201 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_POW_OWR

#define FXPQ3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */

Definition at line 226 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_POW_SHIFT

#define FXPQ3115_DR_STATUS_POW_SHIFT ((uint8_t) 6)

Definition at line 202 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PTDR_DRDY

#define FXPQ3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */

Definition at line 217 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PTDR_MASK

#define FXPQ3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08)

Definition at line 195 of file fxpq3115.h.

Referenced by main().

◆ FXPQ3115_DR_STATUS_PTDR_SHIFT

#define FXPQ3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3)

Definition at line 196 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PTOW_MASK

#define FXPQ3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80)

Definition at line 204 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PTOW_OWR

#define FXPQ3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */

Definition at line 231 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_PTOW_SHIFT

#define FXPQ3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7)

Definition at line 205 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TDR_DRDY

#define FXPQ3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition */

Definition at line 211 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TDR_MASK

#define FXPQ3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02)

Definition at line 189 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TDR_SHIFT

#define FXPQ3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1)

Definition at line 190 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TOW_MASK

#define FXPQ3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20)

Definition at line 198 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TOW_OWR

#define FXPQ3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */

Definition at line 221 of file fxpq3115.h.

◆ FXPQ3115_DR_STATUS_TOW_SHIFT

#define FXPQ3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5)

Definition at line 199 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_MODE_CIR_MODE

#define FXPQ3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when */

Definition at line 418 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_MODE_FIFO_OFF

#define FXPQ3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */

Definition at line 417 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_MODE_MASK

#define FXPQ3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)

Definition at line 410 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_MODE_SHIFT

#define FXPQ3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)

Definition at line 411 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_MODE_STOP_MODE

#define FXPQ3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */

Definition at line 420 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_WMRK_MASK

#define FXPQ3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)

Definition at line 407 of file fxpq3115.h.

◆ FXPQ3115_F_SETUP_F_WMRK_SHIFT

#define FXPQ3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)

Definition at line 408 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_CNT_MASK

#define FXPQ3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)

Definition at line 356 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_CNT_SHIFT

#define FXPQ3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)

Definition at line 357 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_OVF_MASK

#define FXPQ3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)

Definition at line 362 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_OVF_NOOVFL

#define FXPQ3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */

Definition at line 371 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_OVF_OVFLDET

#define FXPQ3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */

Definition at line 372 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_OVF_SHIFT

#define FXPQ3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)

Definition at line 363 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_WMKF_FLAG_EVTDET

#define FXPQ3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */

Definition at line 370 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_WMKF_FLAG_MASK

#define FXPQ3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40)

Definition at line 359 of file fxpq3115.h.

Referenced by main().

◆ FXPQ3115_F_STATUS_F_WMKF_FLAG_NOEVT

#define FXPQ3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */

Definition at line 369 of file fxpq3115.h.

◆ FXPQ3115_F_STATUS_F_WMKF_FLAG_SHIFT

#define FXPQ3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6)

Definition at line 360 of file fxpq3115.h.

◆ FXPQ3115_I2C_ADDRESS

#define FXPQ3115_I2C_ADDRESS (0x60) /* FXPQ3115BV I2C Slave Address. */

Definition at line 64 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_DRDY_MASK

#define FXPQ3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80)

Definition at line 520 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_DRDY_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7)

Definition at line 521 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_FIFO_MASK

#define FXPQ3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)

Definition at line 517 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_FIFO_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)

Definition at line 518 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PCHG_MASK

#define FXPQ3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02)

Definition at line 502 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PCHG_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1)

Definition at line 503 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PTH_MASK

#define FXPQ3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08)

Definition at line 508 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PTH_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3)

Definition at line 509 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PW_MASK

#define FXPQ3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20)

Definition at line 514 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_PW_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5)

Definition at line 515 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TCHG_MASK

#define FXPQ3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01)

Definition at line 499 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TCHG_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0)

Definition at line 500 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TTH_MASK

#define FXPQ3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04)

Definition at line 505 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TTH_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2)

Definition at line 506 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TW_MASK

#define FXPQ3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10)

Definition at line 511 of file fxpq3115.h.

◆ FXPQ3115_INT_SOURCE_SRC_TW_SHIFT

#define FXPQ3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4)

Definition at line 512 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_DELTA_LSB_PCD_MASK

#define FXPQ3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0)

Definition at line 279 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_DELTA_LSB_PCD_SHIFT

#define FXPQ3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4)

Definition at line 280 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_LSB_PD_MASK

#define FXPQ3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0)

Definition at line 115 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_LSB_PD_SHIFT

#define FXPQ3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4)

Definition at line 116 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_DELTA_LSB_TCD_MASK

#define FXPQ3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0)

Definition at line 315 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_DELTA_LSB_TCD_SHIFT

#define FXPQ3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4)

Definition at line 316 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_LSB_PD_MASK

#define FXPQ3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0)

Definition at line 151 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_LSB_PD_SHIFT

#define FXPQ3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4)

Definition at line 152 of file fxpq3115.h.

◆ FXPQ3115_P_MAX_LSB_MAXPAD_MASK

#define FXPQ3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0)

Definition at line 772 of file fxpq3115.h.

◆ FXPQ3115_P_MAX_LSB_MAXPAD_SHIFT

#define FXPQ3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4)

Definition at line 773 of file fxpq3115.h.

◆ FXPQ3115_P_MIN_LSB_MINPAD_MASK

#define FXPQ3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0)

Definition at line 691 of file fxpq3115.h.

◆ FXPQ3115_P_MIN_LSB_MINPAD_SHIFT

#define FXPQ3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4)

Definition at line 692 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_DREM_DISABLED

#define FXPQ3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

Definition at line 569 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_DREM_ENABLED

#define FXPQ3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */

Definition at line 570 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_DREM_MASK

#define FXPQ3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04)

Definition at line 556 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_DREM_SHIFT

#define FXPQ3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2)

Definition at line 557 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_PDEFE_DISABLED

#define FXPQ3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

Definition at line 566 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_PDEFE_ENABLED

#define FXPQ3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */

Definition at line 567 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_PDEFE_MASK

#define FXPQ3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02)

Definition at line 553 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_PDEFE_SHIFT

#define FXPQ3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1)

Definition at line 554 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_TDEFE_DISABLED

#define FXPQ3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */

Definition at line 563 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_TDEFE_ENABLED

#define FXPQ3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */

Definition at line 564 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_TDEFE_MASK

#define FXPQ3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01)

Definition at line 550 of file fxpq3115.h.

◆ FXPQ3115_PT_DATA_CFG_TDEFE_SHIFT

#define FXPQ3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0)

Definition at line 551 of file fxpq3115.h.

◆ FXPQ3115_SYSMOD_SYSMOD_ACTIVE

#define FXPQ3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */

Definition at line 461 of file fxpq3115.h.

◆ FXPQ3115_SYSMOD_SYSMOD_MASK

#define FXPQ3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01)

Definition at line 453 of file fxpq3115.h.

◆ FXPQ3115_SYSMOD_SYSMOD_SHIFT

#define FXPQ3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)

Definition at line 454 of file fxpq3115.h.

◆ FXPQ3115_SYSMOD_SYSMOD_STANDBY

#define FXPQ3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */

Definition at line 460 of file fxpq3115.h.

◆ FXPQ3115_T_MAX_LSB_MAXTD_MASK

#define FXPQ3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0)

Definition at line 808 of file fxpq3115.h.

◆ FXPQ3115_T_MAX_LSB_MAXTD_SHIFT

#define FXPQ3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4)

Definition at line 809 of file fxpq3115.h.

◆ FXPQ3115_T_MIN_LSB_MINTD_MASK

#define FXPQ3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0)

Definition at line 727 of file fxpq3115.h.

◆ FXPQ3115_T_MIN_LSB_MINTD_SHIFT

#define FXPQ3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4)

Definition at line 728 of file fxpq3115.h.

◆ FXPQ3115_WHOAMI_VALUE

#define FXPQ3115_WHOAMI_VALUE (0xC5) /* FXPQ3115BV WHO_AM_I Value. */

Definition at line 65 of file fxpq3115.h.

Referenced by main().

Typedef Documentation

◆ FXPQ3115_BAR_IN_LSB_t

typedef uint8_t FXPQ3115_BAR_IN_LSB_t

Definition at line 592 of file fxpq3115.h.

◆ FXPQ3115_BAR_IN_MSB_t

typedef uint8_t FXPQ3115_BAR_IN_MSB_t

Definition at line 583 of file fxpq3115.h.

◆ FXPQ3115_F_DATA_t

typedef uint8_t FXPQ3115_F_DATA_t

Definition at line 383 of file fxpq3115.h.

◆ FXPQ3115_OFF_H_t

typedef uint8_t FXPQ3115_OFF_H_t

Definition at line 1184 of file fxpq3115.h.

◆ FXPQ3115_OFF_P_t

typedef uint8_t FXPQ3115_OFF_P_t

Definition at line 1164 of file fxpq3115.h.

◆ FXPQ3115_OFF_T_t

typedef uint8_t FXPQ3115_OFF_T_t

Definition at line 1174 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_CSB_t

typedef uint8_t FXPQ3115_OUT_P_CSB_t

Definition at line 93 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_DELTA_CSB_t

typedef uint8_t FXPQ3115_OUT_P_DELTA_CSB_t

Definition at line 257 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_DELTA_MSB_t

typedef uint8_t FXPQ3115_OUT_P_DELTA_MSB_t

Definition at line 248 of file fxpq3115.h.

◆ FXPQ3115_OUT_P_MSB_t

typedef uint8_t FXPQ3115_OUT_P_MSB_t

Definition at line 84 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_DELTA_MSB_t

typedef uint8_t FXPQ3115_OUT_T_DELTA_MSB_t

Definition at line 293 of file fxpq3115.h.

◆ FXPQ3115_OUT_T_MSB_t

typedef uint8_t FXPQ3115_OUT_T_MSB_t

Definition at line 129 of file fxpq3115.h.

◆ FXPQ3115_P_MAX_CSB_t

typedef uint8_t FXPQ3115_P_MAX_CSB_t

Definition at line 750 of file fxpq3115.h.

◆ FXPQ3115_P_MAX_MSB_t

typedef uint8_t FXPQ3115_P_MAX_MSB_t

Definition at line 741 of file fxpq3115.h.

◆ FXPQ3115_P_MIN_CSB_t

typedef uint8_t FXPQ3115_P_MIN_CSB_t

Definition at line 669 of file fxpq3115.h.

◆ FXPQ3115_P_MIN_MSB_t

typedef uint8_t FXPQ3115_P_MIN_MSB_t

Definition at line 660 of file fxpq3115.h.

◆ FXPQ3115_P_TGT_LSB_t

typedef uint8_t FXPQ3115_P_TGT_LSB_t

Definition at line 611 of file fxpq3115.h.

◆ FXPQ3115_P_TGT_MSB_t

typedef uint8_t FXPQ3115_P_TGT_MSB_t

Definition at line 602 of file fxpq3115.h.

◆ FXPQ3115_P_WND_LSB_t

typedef uint8_t FXPQ3115_P_WND_LSB_t

Definition at line 640 of file fxpq3115.h.

◆ FXPQ3115_P_WND_MSB_t

typedef uint8_t FXPQ3115_P_WND_MSB_t

Definition at line 631 of file fxpq3115.h.

◆ FXPQ3115_STATUS_t

typedef uint8_t FXPQ3115_STATUS_t

Definition at line 74 of file fxpq3115.h.

◆ FXPQ3115_T_MAX_MSB_t

typedef uint8_t FXPQ3115_T_MAX_MSB_t

Definition at line 786 of file fxpq3115.h.

◆ FXPQ3115_T_MIN_MSB_t

typedef uint8_t FXPQ3115_T_MIN_MSB_t

Definition at line 705 of file fxpq3115.h.

◆ FXPQ3115_T_TGT_t

typedef uint8_t FXPQ3115_T_TGT_t

Definition at line 621 of file fxpq3115.h.

◆ FXPQ3115_T_WND_t

typedef uint8_t FXPQ3115_T_WND_t

Definition at line 650 of file fxpq3115.h.

◆ FXPQ3115_TIME_DLY_t

typedef uint8_t FXPQ3115_TIME_DLY_t

Definition at line 431 of file fxpq3115.h.

◆ FXPQ3115_WHO_AM_I_t

typedef uint8_t FXPQ3115_WHO_AM_I_t

Definition at line 329 of file fxpq3115.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

FXPQ3115 Sensor Internal Registers

Enumerator
FXPQ3115_STATUS
FXPQ3115_OUT_P_MSB
FXPQ3115_OUT_P_CSB
FXPQ3115_OUT_P_LSB
FXPQ3115_OUT_T_MSB
FXPQ3115_OUT_T_LSB
FXPQ3115_DR_STATUS
FXPQ3115_OUT_P_DELTA_MSB
FXPQ3115_OUT_P_DELTA_CSB
FXPQ3115_OUT_P_DELTA_LSB
FXPQ3115_OUT_T_DELTA_MSB
FXPQ3115_OUT_T_DELTA_LSB
FXPQ3115_WHO_AM_I
FXPQ3115_F_STATUS
FXPQ3115_F_DATA
FXPQ3115_F_SETUP
FXPQ3115_TIME_DLY
FXPQ3115_SYSMOD
FXPQ3115_INT_SOURCE
FXPQ3115_PT_DATA_CFG
FXPQ3115_BAR_IN_MSB
FXPQ3115_BAR_IN_LSB
FXPQ3115_P_TGT_MSB
FXPQ3115_P_TGT_LSB
FXPQ3115_T_TGT
FXPQ3115_P_WND_MSB
FXPQ3115_P_WND_LSB
FXPQ3115_T_WND
FXPQ3115_P_MIN_MSB
FXPQ3115_P_MIN_CSB
FXPQ3115_P_MIN_LSB
FXPQ3115_T_MIN_MSB
FXPQ3115_T_MIN_LSB
FXPQ3115_P_MAX_MSB
FXPQ3115_P_MAX_CSB
FXPQ3115_P_MAX_LSB
FXPQ3115_T_MAX_MSB
FXPQ3115_T_MAX_LSB
FXPQ3115_CTRL_REG1
FXPQ3115_CTRL_REG2
FXPQ3115_CTRL_REG3
FXPQ3115_CTRL_REG4
FXPQ3115_CTRL_REG5
FXPQ3115_OFF_P
FXPQ3115_OFF_T
FXPQ3115_OFF_H

Definition at line 15 of file fxpq3115.h.

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation

◆ FXPQ3115_CTRL_REG1_ALT_ALT

◆ FXPQ3115_CTRL_REG1_ALT_BAR

◆ FXPQ3115_CTRL_REG1_ALT_MASK

◆ FXPQ3115_CTRL_REG1_ALT_SHIFT

◆ FXPQ3115_CTRL_REG1_OS_MASK

◆ FXPQ3115_CTRL_REG1_OS_OSR_1

◆ FXPQ3115_CTRL_REG1_OS_OSR_128

◆ FXPQ3115_CTRL_REG1_OS_OSR_16

◆ FXPQ3115_CTRL_REG1_OS_OSR_2

◆ FXPQ3115_CTRL_REG1_OS_OSR_32

◆ FXPQ3115_CTRL_REG1_OS_OSR_4

◆ FXPQ3115_CTRL_REG1_OS_OSR_64

◆ FXPQ3115_CTRL_REG1_OS_OSR_8

◆ FXPQ3115_CTRL_REG1_OS_SHIFT

◆ FXPQ3115_CTRL_REG1_OST_MASK

◆ FXPQ3115_CTRL_REG1_OST_RESET

◆ FXPQ3115_CTRL_REG1_OST_SET

◆ FXPQ3115_CTRL_REG1_OST_SHIFT

◆ FXPQ3115_CTRL_REG1_RAW_DIS

◆ FXPQ3115_CTRL_REG1_RAW_EN

◆ FXPQ3115_CTRL_REG1_RAW_MASK

◆ FXPQ3115_CTRL_REG1_RAW_SHIFT

◆ FXPQ3115_CTRL_REG1_RST_DIS

◆ FXPQ3115_CTRL_REG1_RST_EN

◆ FXPQ3115_CTRL_REG1_RST_MASK

◆ FXPQ3115_CTRL_REG1_RST_SHIFT

◆ FXPQ3115_CTRL_REG1_SBYB_ACTIVE

◆ FXPQ3115_CTRL_REG1_SBYB_MASK

◆ FXPQ3115_CTRL_REG1_SBYB_SHIFT

◆ FXPQ3115_CTRL_REG1_SBYB_STANDBY

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_MASK

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT

◆ FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL

◆ FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT

◆ FXPQ3115_CTRL_REG2_ST_MASK

◆ FXPQ3115_CTRL_REG2_ST_SHIFT

◆ FXPQ3115_CTRL_REG3_IPOL1_HIGH

◆ FXPQ3115_CTRL_REG3_IPOL1_LOW

◆ FXPQ3115_CTRL_REG3_IPOL1_MASK

◆ FXPQ3115_CTRL_REG3_IPOL1_SHIFT

◆ FXPQ3115_CTRL_REG3_IPOL2_HIGH

◆ FXPQ3115_CTRL_REG3_IPOL2_LOW

◆ FXPQ3115_CTRL_REG3_IPOL2_MASK

◆ FXPQ3115_CTRL_REG3_IPOL2_SHIFT

◆ FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP

◆ FXPQ3115_CTRL_REG3_PP_OD1_MASK

◆ FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN

◆ FXPQ3115_CTRL_REG3_PP_OD1_SHIFT

◆ FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP

◆ FXPQ3115_CTRL_REG3_PP_OD2_MASK

◆ FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN

◆ FXPQ3115_CTRL_REG3_PP_OD2_SHIFT

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK

◆ FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK

◆ FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK

◆ FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK

◆ FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED

◆ FXPQ3115_CTRL_REG4_INT_EN_PW_MASK